323 lines
8.8 KiB
ArmAsm
323 lines
8.8 KiB
ArmAsm
/*----------------------------------------------------------------------------
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* Tencent is pleased to support the open source community by making TencentOS
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* available.
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*
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* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
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* If you have downloaded a copy of the TencentOS binary from Tencent, please
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* note that the TencentOS binary is licensed under the BSD 3-Clause License.
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*
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* If you have downloaded a copy of the TencentOS source code from Tencent,
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* please note that TencentOS source code is licensed under the BSD 3-Clause
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* License, except for the third-party components listed below which are
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* subject to different license terms. Your integration of TencentOS into your
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* own projects may require compliance with the BSD 3-Clause License, as well
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* as the other licenses applicable to the third-party components included
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* within TencentOS.
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*---------------------------------------------------------------------------*/
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#include "port_config.h"
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.global port_int_disable
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.global port_int_enable
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.global port_cpsr_save
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.global port_cpsr_restore
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.global port_sched_start
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.extern k_curr_task
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.extern k_next_task
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.text
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.align 2
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.type port_int_disable, %function
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port_int_disable:
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csrci mstatus, 0x8
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ret
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.type port_int_enable, %function
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port_int_enable:
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csrsi mstatus, 0x8
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ret
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.type port_cpsr_save, %function
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port_cpsr_save:
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csrrci a0, mstatus, 0x8
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ret
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.type port_cpsr_restore, %function
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port_cpsr_restore:
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csrw mstatus, a0
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ret
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.align 2
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.type port_sched_start, %function
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port_sched_start:
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/* load sp from k_curr_task->sp */
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lw t0, k_curr_task
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/* sp = k_curr_task->sp */
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lw sp, (t0)
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j restore_context
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.align 2
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.type restore_context, %function
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restore_context:
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// restore context
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lw t0, __reg_mepc_OFFSET(sp)
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csrw mepc, t0
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lw t0, __reg_mstatus_OFFSET(sp)
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csrw mstatus, t0
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lw x1, __reg_x1_OFFSET(sp)
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lw x3, __reg_x3_OFFSET(sp)
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lw x4, __reg_x4_OFFSET(sp)
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lw x5, __reg_x5_OFFSET(sp)
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lw x6, __reg_x6_OFFSET(sp)
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lw x7, __reg_x7_OFFSET(sp)
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lw x8, __reg_x8_OFFSET(sp)
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lw x9, __reg_x9_OFFSET(sp)
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lw x10, __reg_x10_OFFSET(sp)
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lw x11, __reg_x11_OFFSET(sp)
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lw x12, __reg_x12_OFFSET(sp)
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lw x13, __reg_x13_OFFSET(sp)
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lw x14, __reg_x14_OFFSET(sp)
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lw x15, __reg_x15_OFFSET(sp)
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lw x16, __reg_x16_OFFSET(sp)
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lw x17, __reg_x17_OFFSET(sp)
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lw x18, __reg_x18_OFFSET(sp)
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lw x19, __reg_x19_OFFSET(sp)
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lw x20, __reg_x20_OFFSET(sp)
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lw x21, __reg_x21_OFFSET(sp)
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lw x22, __reg_x22_OFFSET(sp)
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lw x23, __reg_x23_OFFSET(sp)
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lw x24, __reg_x24_OFFSET(sp)
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lw x25, __reg_x25_OFFSET(sp)
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lw x26, __reg_x26_OFFSET(sp)
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lw x27, __reg_x27_OFFSET(sp)
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lw x28, __reg_x28_OFFSET(sp)
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lw x29, __reg_x29_OFFSET(sp)
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lw x30, __reg_x30_OFFSET(sp)
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lw x31, __reg_x31_OFFSET(sp)
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addi sp, sp, 128
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#if ARCH_RISCV_FPU
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flw f0, __reg_f0_OFFSET(sp)
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flw f1, __reg_f1_OFFSET(sp)
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flw f2, __reg_f2_OFFSET(sp)
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flw f3, __reg_f3_OFFSET(sp)
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flw f4, __reg_f4_OFFSET(sp)
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flw f5, __reg_f5_OFFSET(sp)
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flw f6, __reg_f6_OFFSET(sp)
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flw f7, __reg_f7_OFFSET(sp)
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flw f8, __reg_f8_OFFSET(sp)
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flw f9, __reg_f9_OFFSET(sp)
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flw f10, __reg_f10_OFFSET(sp)
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flw f11, __reg_f11_OFFSET(sp)
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flw f12, __reg_f12_OFFSET(sp)
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flw f13, __reg_f13_OFFSET(sp)
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flw f14, __reg_f14_OFFSET(sp)
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flw f15, __reg_f15_OFFSET(sp)
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flw f16, __reg_f16_OFFSET(sp)
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flw f17, __reg_f17_OFFSET(sp)
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flw f18, __reg_f18_OFFSET(sp)
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flw f19, __reg_f19_OFFSET(sp)
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flw f20, __reg_f20_OFFSET(sp)
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flw f21, __reg_f21_OFFSET(sp)
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flw f22, __reg_f22_OFFSET(sp)
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flw f23, __reg_f23_OFFSET(sp)
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flw f24, __reg_f24_OFFSET(sp)
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flw f25, __reg_f25_OFFSET(sp)
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flw f26, __reg_f26_OFFSET(sp)
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flw f27, __reg_f27_OFFSET(sp)
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flw f28, __reg_f28_OFFSET(sp)
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flw f29, __reg_f29_OFFSET(sp)
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flw f30, __reg_f30_OFFSET(sp)
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flw f31, __reg_f31_OFFSET(sp)
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addi sp, sp, 128
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#endif
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mret
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/* just switch at Software interrupt */
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.align 2
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.global SW_Handler
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SW_Handler:
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#if ARCH_RISCV_FPU
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addi sp, sp, -128
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fsw f0, __reg_f0_OFFSET(sp)
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fsw f1, __reg_f1_OFFSET(sp)
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fsw f2, __reg_f2_OFFSET(sp)
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fsw f3, __reg_f3_OFFSET(sp)
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fsw f4, __reg_f4_OFFSET(sp)
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fsw f5, __reg_f5_OFFSET(sp)
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fsw f6, __reg_f6_OFFSET(sp)
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fsw f7, __reg_f7_OFFSET(sp)
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fsw f8, __reg_f8_OFFSET(sp)
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fsw f9, __reg_f9_OFFSET(sp)
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fsw f10, __reg_f10_OFFSET(sp)
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fsw f11, __reg_f11_OFFSET(sp)
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fsw f12, __reg_f12_OFFSET(sp)
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fsw f13, __reg_f13_OFFSET(sp)
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fsw f14, __reg_f14_OFFSET(sp)
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fsw f15, __reg_f15_OFFSET(sp)
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fsw f16, __reg_f16_OFFSET(sp)
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fsw f17, __reg_f17_OFFSET(sp)
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fsw f18, __reg_f18_OFFSET(sp)
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fsw f19, __reg_f19_OFFSET(sp)
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fsw f20, __reg_f20_OFFSET(sp)
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fsw f21, __reg_f21_OFFSET(sp)
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fsw f22, __reg_f22_OFFSET(sp)
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fsw f23, __reg_f23_OFFSET(sp)
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fsw f24, __reg_f24_OFFSET(sp)
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fsw f25, __reg_f25_OFFSET(sp)
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fsw f26, __reg_f26_OFFSET(sp)
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fsw f27, __reg_f27_OFFSET(sp)
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fsw f28, __reg_f28_OFFSET(sp)
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fsw f29, __reg_f29_OFFSET(sp)
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fsw f30, __reg_f30_OFFSET(sp)
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fsw f31, __reg_f31_OFFSET(sp)
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#endif
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addi sp, sp, -128
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sw t0, __reg_x5_OFFSET(sp)
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/* disable HPE */
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li t0, 0x20
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csrs 0x804, t0
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csrr t0, mstatus
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sw t0, __reg_mstatus_OFFSET(sp)
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csrr t0, mepc
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sw t0, __reg_mepc_OFFSET(sp)
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sw x1, __reg_x1_OFFSET(sp)
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sw x3, __reg_x3_OFFSET(sp)
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sw x4, __reg_x4_OFFSET(sp)
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sw x6, __reg_x6_OFFSET(sp)
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sw x7, __reg_x7_OFFSET(sp)
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sw x8, __reg_x8_OFFSET(sp)
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sw x9, __reg_x9_OFFSET(sp)
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sw x10, __reg_x10_OFFSET(sp)
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sw x11, __reg_x11_OFFSET(sp)
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sw x12, __reg_x12_OFFSET(sp)
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sw x13, __reg_x13_OFFSET(sp)
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sw x14, __reg_x14_OFFSET(sp)
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sw x15, __reg_x15_OFFSET(sp)
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sw x16, __reg_x16_OFFSET(sp)
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sw x17, __reg_x17_OFFSET(sp)
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sw x18, __reg_x18_OFFSET(sp)
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sw x19, __reg_x19_OFFSET(sp)
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sw x20, __reg_x20_OFFSET(sp)
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sw x21, __reg_x21_OFFSET(sp)
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sw x22, __reg_x22_OFFSET(sp)
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sw x23, __reg_x23_OFFSET(sp)
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sw x24, __reg_x24_OFFSET(sp)
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sw x25, __reg_x25_OFFSET(sp)
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sw x26, __reg_x26_OFFSET(sp)
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sw x27, __reg_x27_OFFSET(sp)
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sw x28, __reg_x28_OFFSET(sp)
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sw x29, __reg_x29_OFFSET(sp)
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sw x30, __reg_x30_OFFSET(sp)
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sw x31, __reg_x31_OFFSET(sp)
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/* switch to irq stk */
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mv t0, sp
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lw sp, k_irq_stk_top /* cpu_init<EFBFBD>м<EFBFBD>ȥһ<EFBFBD><EFBFBD><EFBFBD>ֿռ<EFBFBD> */
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sw t0, 0(sp)
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/* clear software interrupt */
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call sw_clearpend
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/* resume sp */
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lw sp, 0(sp)
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la t0, k_curr_task // t0 = &k_curr_task
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la t1, k_next_task // t1 = &k_next_task
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// save sp to k_curr_task.sp
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lw t2, (t0)
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sw sp, (t2)
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# switch task
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# k_curr_task = k_next_task
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lw t1, (t1)
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sw t1, (t0)
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# load new task sp
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lw sp, (t1)
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/* new thread restore */
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lw t0, __reg_mstatus_OFFSET(sp)
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csrw mstatus, t0
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lw t0, __reg_mepc_OFFSET(sp)
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csrw mepc, t0
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lw x1, __reg_x1_OFFSET(sp)
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lw x3, __reg_x3_OFFSET(sp)
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lw x4, __reg_x4_OFFSET(sp)
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lw x5, __reg_x5_OFFSET(sp)
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lw x6, __reg_x6_OFFSET(sp)
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lw x7, __reg_x7_OFFSET(sp)
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lw x8, __reg_x8_OFFSET(sp)
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lw x9, __reg_x9_OFFSET(sp)
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lw x10, __reg_x10_OFFSET(sp)
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lw x11, __reg_x11_OFFSET(sp)
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lw x12, __reg_x12_OFFSET(sp)
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lw x13, __reg_x13_OFFSET(sp)
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lw x14, __reg_x14_OFFSET(sp)
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lw x15, __reg_x15_OFFSET(sp)
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lw x16, __reg_x16_OFFSET(sp)
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lw x17, __reg_x17_OFFSET(sp)
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lw x18, __reg_x18_OFFSET(sp)
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lw x19, __reg_x19_OFFSET(sp)
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lw x20, __reg_x20_OFFSET(sp)
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lw x21, __reg_x21_OFFSET(sp)
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lw x22, __reg_x22_OFFSET(sp)
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lw x23, __reg_x23_OFFSET(sp)
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lw x24, __reg_x24_OFFSET(sp)
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lw x25, __reg_x25_OFFSET(sp)
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lw x26, __reg_x26_OFFSET(sp)
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lw x27, __reg_x27_OFFSET(sp)
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lw x28, __reg_x28_OFFSET(sp)
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lw x29, __reg_x29_OFFSET(sp)
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lw x30, __reg_x30_OFFSET(sp)
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lw x31, __reg_x31_OFFSET(sp)
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addi sp, sp, 128
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#if ARCH_RISCV_FPU
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flw f0, __reg_f0_OFFSET(sp)
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flw f1, __reg_f1_OFFSET(sp)
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flw f2, __reg_f2_OFFSET(sp)
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flw f3, __reg_f3_OFFSET(sp)
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flw f4, __reg_f4_OFFSET(sp)
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flw f5, __reg_f5_OFFSET(sp)
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flw f6, __reg_f6_OFFSET(sp)
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flw f7, __reg_f7_OFFSET(sp)
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flw f8, __reg_f8_OFFSET(sp)
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flw f9, __reg_f9_OFFSET(sp)
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flw f10, __reg_f10_OFFSET(sp)
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flw f11, __reg_f11_OFFSET(sp)
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flw f12, __reg_f12_OFFSET(sp)
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flw f13, __reg_f13_OFFSET(sp)
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flw f14, __reg_f14_OFFSET(sp)
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flw f15, __reg_f15_OFFSET(sp)
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flw f16, __reg_f16_OFFSET(sp)
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flw f17, __reg_f17_OFFSET(sp)
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flw f18, __reg_f18_OFFSET(sp)
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flw f19, __reg_f19_OFFSET(sp)
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flw f20, __reg_f20_OFFSET(sp)
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flw f21, __reg_f21_OFFSET(sp)
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flw f22, __reg_f22_OFFSET(sp)
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flw f23, __reg_f23_OFFSET(sp)
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flw f24, __reg_f24_OFFSET(sp)
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flw f25, __reg_f25_OFFSET(sp)
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flw f26, __reg_f26_OFFSET(sp)
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flw f27, __reg_f27_OFFSET(sp)
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flw f28, __reg_f28_OFFSET(sp)
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flw f29, __reg_f29_OFFSET(sp)
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flw f30, __reg_f30_OFFSET(sp)
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flw f31, __reg_f31_OFFSET(sp)
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addi sp, sp, 128
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#endif
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mret
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