421 lines
17 KiB
C
421 lines
17 KiB
C
/*
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* Copyright 2017 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/**
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* @file board.c
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* @brief relative configure for xidatong-arm32
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* @version 2.0
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* @author AIIT XUOS Lab
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* @date 2022.03.15
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*/
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/*************************************************
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File name: board.c
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Description: support imxrt1176-board init function
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Others: take SDK_2.6.1_MIMXRT1052xxxxB for references
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History:
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1. Date: 2022-08-19
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Author: AIIT XUOS Lab
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Modification:
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1. support imxrt1176-board MPU、clock、memory init
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2. support imxrt1176-board uart、sdio driver init
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*************************************************/
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#include <board.h>
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#ifdef BSP_USING_GPIO
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#include <connect_gpio.h>
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#endif
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#ifdef BSP_USING_LPUART
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#include <connect_uart.h>
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#endif
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#if __CORTEX_M == 7
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void BOARD_ConfigMPU(void)
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{
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#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
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extern uint32_t Image$$RW_m_ncache$$Base[];
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/* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
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extern uint32_t Image$$RW_m_ncache_unused$$Base[];
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extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
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uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
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uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
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0 :
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((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
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#elif defined(__MCUXPRESSO)
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#if defined(__USE_SHMEM)
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extern uint32_t __base_rpmsg_sh_mem;
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extern uint32_t __top_rpmsg_sh_mem;
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uint32_t nonCacheStart = (uint32_t)(&__base_rpmsg_sh_mem);
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uint32_t size = (uint32_t)(&__top_rpmsg_sh_mem) - nonCacheStart;
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#else
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extern uint32_t __base_NCACHE_REGION;
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extern uint32_t __top_NCACHE_REGION;
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uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
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uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
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#endif
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#elif defined(__ICCARM__) || defined(__GNUC__)
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extern uint32_t __NCACHE_REGION_START;
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extern uint32_t __NCACHE_REGION_END;
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uint32_t nonCacheStart = (uint32_t)(&__NCACHE_REGION_START);
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uint32_t size = (uint32_t)(&__NCACHE_REGION_END) - nonCacheStart;
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#endif
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volatile uint32_t i = 0;
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#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
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/* Disable I cache and D cache */
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if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
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{
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SCB_DisableICache();
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}
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#endif
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#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
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if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
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{
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SCB_DisableDCache();
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}
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#endif
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/* Disable MPU */
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ARM_MPU_Disable();
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/* MPU configure:
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* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
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* SubRegionDisable, Size)
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* API in mpu_armv7.h.
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* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
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* disabled.
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* param AccessPermission Data access permissions, allows you to configure read/write access for User and
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* Privileged mode.
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* Use MACROS defined in mpu_armv7.h:
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* ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
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* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
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* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
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* 0 x 0 0 Strongly Ordered shareable
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* 0 x 0 1 Device shareable
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* 0 0 1 0 Normal not shareable Outer and inner write
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* through no write allocate
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* 0 0 1 1 Normal not shareable Outer and inner write
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* back no write allocate
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* 0 1 1 0 Normal shareable Outer and inner write
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* through no write allocate
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* 0 1 1 1 Normal shareable Outer and inner write
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* back no write allocate
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* 1 0 0 0 Normal not shareable outer and inner
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* noncache
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* 1 1 0 0 Normal shareable outer and inner
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* noncache
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* 1 0 1 1 Normal not shareable outer and inner write
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* back write/read acllocate
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* 1 1 1 1 Normal shareable outer and inner write
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* back write/read acllocate
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* 2 x 0 0 Device not shareable
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* Above are normal use settings, if your want to see more details or want to config different inner/outter cache
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* policy.
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* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
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* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
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* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
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* mpu_armv7.h.
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*/
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/*
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* Add default region to deny access to whole address space to workaround speculative prefetch.
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* Refer to Arm errata 1013783-B for more details.
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*
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*/
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/* Region 0 setting: Instruction access disabled, No data access permission. */
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MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
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MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
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/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
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MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
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/* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
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MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
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/* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
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MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
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/* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
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MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
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/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
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MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
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/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
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MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_1MB);
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/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
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MPU->RBAR = ARM_MPU_RBAR(7, 0x20300000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
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#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
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/* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back. */
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MPU->RBAR = ARM_MPU_RBAR(8, 0x30000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB);
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#endif
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#ifdef USE_SDRAM
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/* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back */
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MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
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#endif
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while ((size >> i) > 0x1U)
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{
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i++;
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}
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if (i != 0)
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{
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/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
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assert(!(nonCacheStart % size));
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assert(size == (uint32_t)(1 << i));
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assert(i >= 5);
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/* Region 10 setting: Memory with Normal type, not shareable, non-cacheable */
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MPU->RBAR = ARM_MPU_RBAR(10, nonCacheStart);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
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}
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/* Region 11 setting: Memory with Device type, not shareable, non-cacheable */
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MPU->RBAR = ARM_MPU_RBAR(11, 0x40000000);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_16MB);
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/* Region 12 setting: Memory with Device type, not shareable, non-cacheable */
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MPU->RBAR = ARM_MPU_RBAR(12, 0x41000000);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
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/* Region 13 setting: Memory with Device type, not shareable, non-cacheable */
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MPU->RBAR = ARM_MPU_RBAR(13, 0x41400000);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB);
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/* Region 14 setting: Memory with Device type, not shareable, non-cacheable */
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MPU->RBAR = ARM_MPU_RBAR(14, 0x41800000);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
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/* Region 15 setting: Memory with Device type, not shareable, non-cacheable */
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MPU->RBAR = ARM_MPU_RBAR(15, 0x42000000);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB);
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/* Enable MPU */
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ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
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/* Enable I cache and D cache */
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#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
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SCB_EnableDCache();
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#endif
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#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
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SCB_EnableICache();
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#endif
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}
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#elif __CORTEX_M == 4
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void BOARD_ConfigMPU(void)
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{
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#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
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extern uint32_t Image$$RW_m_ncache$$Base[];
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/* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
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extern uint32_t Image$$RW_m_ncache_unused$$Base[];
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extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
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uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
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uint32_t nonCacheSize = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
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0 :
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((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
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#elif defined(__MCUXPRESSO)
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extern uint32_t __base_NCACHE_REGION;
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extern uint32_t __top_NCACHE_REGION;
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uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
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uint32_t nonCacheSize = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
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#elif defined(__ICCARM__) || defined(__GNUC__)
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extern uint32_t __NCACHE_REGION_START[];
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extern uint32_t __NCACHE_REGION_SIZE[];
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uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
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uint32_t nonCacheSize = (uint32_t)__NCACHE_REGION_SIZE;
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#endif
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#if defined(__USE_SHMEM)
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#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
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extern uint32_t Image$$RPMSG_SH_MEM$$Base[];
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/* RPMSG_SH_MEM_unused is a auxiliary region which is used to get the whole size of RPMSG_SH_MEM section */
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extern uint32_t Image$$RPMSG_SH_MEM_unused$$Base[];
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extern uint32_t Image$$RPMSG_SH_MEM_unused$$ZI$$Limit[];
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uint32_t rpmsgShmemStart = (uint32_t)Image$$RPMSG_SH_MEM$$Base;
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uint32_t rpmsgShmemSize = (uint32_t)Image$$RPMSG_SH_MEM_unused$$ZI$$Limit - rpmsgShmemStart;
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#elif defined(__MCUXPRESSO)
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extern uint32_t __base_rpmsg_sh_mem;
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extern uint32_t __top_rpmsg_sh_mem;
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uint32_t rpmsgShmemStart = (uint32_t)(&__base_rpmsg_sh_mem);
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uint32_t rpmsgShmemSize = (uint32_t)(&__top_rpmsg_sh_mem) - rpmsgShmemStart;
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#elif defined(__ICCARM__) || defined(__GNUC__)
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extern uint32_t __RPMSG_SH_MEM_START[];
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extern uint32_t __RPMSG_SH_MEM_SIZE[];
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uint32_t rpmsgShmemStart = (uint32_t)__RPMSG_SH_MEM_START;
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uint32_t rpmsgShmemSize = (uint32_t)__RPMSG_SH_MEM_SIZE;
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#endif
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#endif
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uint32_t i = 0;
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/* Only config non-cacheable region on system bus */
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assert(nonCacheStart >= 0x20000000);
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/* Disable code bus cache */
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if (LMEM_PCCCR_ENCACHE_MASK == (LMEM_PCCCR_ENCACHE_MASK & LMEM->PCCCR))
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{
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/* Enable the processor code bus to push all modified lines. */
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LMEM->PCCCR |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK | LMEM_PCCCR_GO_MASK;
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/* Wait until the cache command completes. */
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while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U)
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{
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}
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/* As a precaution clear the bits to avoid inadvertently re-running this command. */
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LMEM->PCCCR &= ~(LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK);
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/* Now disable the cache. */
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LMEM->PCCCR &= ~LMEM_PCCCR_ENCACHE_MASK;
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}
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/* Disable system bus cache */
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if (LMEM_PSCCR_ENCACHE_MASK == (LMEM_PSCCR_ENCACHE_MASK & LMEM->PSCCR))
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{
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/* Enable the processor system bus to push all modified lines. */
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LMEM->PSCCR |= LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK | LMEM_PSCCR_GO_MASK;
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/* Wait until the cache command completes. */
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while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U)
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{
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}
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/* As a precaution clear the bits to avoid inadvertently re-running this command. */
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LMEM->PSCCR &= ~(LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK);
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/* Now disable the cache. */
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LMEM->PSCCR &= ~LMEM_PSCCR_ENCACHE_MASK;
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}
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/* Disable MPU */
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ARM_MPU_Disable();
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while ((nonCacheSize >> i) > 0x1U)
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{
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i++;
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}
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if (i != 0)
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{
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/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
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assert(!(nonCacheStart % nonCacheSize));
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assert(nonCacheSize == (uint32_t)(1 << i));
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assert(i >= 5);
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/* Region 0 setting: Memory with device type, not shareable, non-cacheable */
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MPU->RBAR = ARM_MPU_RBAR(0, nonCacheStart);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1);
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}
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#if defined(__USE_SHMEM)
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i = 0;
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while ((rpmsgShmemSize >> i) > 0x1U)
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{
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i++;
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}
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if (i != 0)
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{
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/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
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assert(!(rpmsgShmemStart % rpmsgShmemSize));
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assert(rpmsgShmemSize == (uint32_t)(1 << i));
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assert(i >= 5);
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/* Region 1 setting: Memory with device type, not shareable, non-cacheable */
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MPU->RBAR = ARM_MPU_RBAR(1, rpmsgShmemStart);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1);
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}
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#endif
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/* Enable MPU */
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ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
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/* Enables the processor system bus to invalidate all lines in both ways.
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and Initiate the processor system bus cache command. */
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LMEM->PSCCR |= LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_GO_MASK;
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/* Wait until the cache command completes */
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while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U)
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{
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}
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/* As a precaution clear the bits to avoid inadvertently re-running this command. */
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LMEM->PSCCR &= ~(LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK);
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/* Now enable the system bus cache. */
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LMEM->PSCCR |= LMEM_PSCCR_ENCACHE_MASK;
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/* Enables the processor code bus to invalidate all lines in both ways.
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and Initiate the processor code bus code cache command. */
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LMEM->PCCCR |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_GO_MASK;
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/* Wait until the cache command completes. */
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while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U)
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{
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}
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/* As a precaution clear the bits to avoid inadvertently re-running this command. */
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LMEM->PCCCR &= ~(LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK);
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/* Now enable the code bus cache. */
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LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK;
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}
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#endif
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/* This is the timer interrupt service routine. */
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void SysTick_Handler(int irqn, void *arg)
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{
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TickAndTaskTimesliceUpdate();
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}
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DECLARE_HW_IRQ(SYSTICK_IRQN, SysTick_Handler, NONE);
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struct InitSequenceDesc _board_init[] =
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{
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#ifdef BSP_USING_GPIO
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// { "hw_pin", Imxrt1052HwGpioInit },
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#endif
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{ " NONE ",NONE },
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};
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/**
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* This function will initial imxrt1050 board.
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|
*/
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|
void InitBoardHardware()
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|
{
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|
int i = 0;
|
|
int ret = 0;
|
|
|
|
BOARD_ConfigMPU();
|
|
BOARD_InitPins();
|
|
BOARD_BootClockRUN();
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|
|
|
// NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
|
|
SysTick_Config(SystemCoreClock / TICK_PER_SECOND);
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|
|
|
InitBoardMemory((void *)HEAP_BEGIN, (void *)HEAP_END);
|
|
|
|
#ifdef BSP_USING_LPUART
|
|
Imxrt1176HwUartInit();
|
|
#endif
|
|
|
|
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
|
|
KPrintf("\nconsole init completed.\n");
|
|
KPrintf("board initialization......\n");
|
|
|
|
for(i = 0; _board_init[i].fn != NONE; i++) {
|
|
ret = _board_init[i].fn();
|
|
KPrintf("initialize %s %s\n",_board_init[i].fn_name, ret == 0 ? "success" : "failed");
|
|
}
|
|
KPrintf("board init done.\n");
|
|
KPrintf("start kernel...\n");
|
|
}
|
|
|