111 lines
4.0 KiB
C
Executable File
111 lines
4.0 KiB
C
Executable File
/*
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* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*******************************************************************************
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* @file system_gd32vf103.h
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* @brief NMSIS Nuclei N/NX Device Peripheral Access Layer Header File for
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* Device gd32vf103
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* @version V1.00
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* @date 7. Jan 2020
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******************************************************************************/
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#ifndef __SYSTEM_GD32VF103_H__
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#define __SYSTEM_GD32VF103_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include "gd32vf103.h"
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#include "core_feature_eclic.h"
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extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
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typedef struct EXC_Frame {
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unsigned long ra; /* ra: x1, return address for jump */
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unsigned long tp; /* tp: x4, thread pointer */
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unsigned long t0; /* t0: x5, temporary register 0 */
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unsigned long t1; /* t1: x6, temporary register 1 */
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unsigned long t2; /* t2: x7, temporary register 2 */
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unsigned long a0; /* a0: x10, return value or function argument 0 */
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unsigned long a1; /* a1: x11, return value or function argument 1 */
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unsigned long a2; /* a2: x12, function argument 2 */
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unsigned long a3; /* a3: x13, function argument 3 */
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unsigned long a4; /* a4: x14, function argument 4 */
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unsigned long a5; /* a5: x15, function argument 5 */
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unsigned long mcause; /* mcause: machine cause csr register */
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unsigned long mepc; /* mepc: machine exception program counter csr register */
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unsigned long msubm; /* msubm: machine sub-mode csr register, nuclei customized */
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#ifndef __riscv_32e
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unsigned long a6; /* a6: x16, function argument 6 */
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unsigned long a7; /* a7: x17, function argument 7 */
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unsigned long t3; /* t3: x28, temporary register 3 */
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unsigned long t4; /* t4: x29, temporary register 4 */
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unsigned long t5; /* t5: x30, temporary register 5 */
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unsigned long t6; /* t6: x31, temporary register 6 */
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#endif
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} EXC_Frame_Type;
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/**
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\brief Setup the microcontroller system.
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Initialize the System and update the SystemCoreClock variable.
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*/
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extern void SystemInit(void);
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/**
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\brief Update SystemCoreClock variable.
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Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
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*/
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extern void SystemCoreClockUpdate(void);
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/**
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* \brief Dump Exception Frame
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*/
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void Exception_DumpFrame(unsigned long sp);
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/**
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* \brief Register an exception handler for exception code EXCn
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*/
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extern void Exception_Register_EXC(uint32_t EXCn, unsigned long exc_handler);
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/**
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* \brief Get current exception handler for exception code EXCn
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*/
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extern unsigned long Exception_Get_EXC(uint32_t EXCn);
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/**
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* \brief Initialize eclic config
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*/
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extern void ECLIC_Init(void);
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/**
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* \brief Initialize a specific IRQ and register the handler
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* \details
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* This function set vector mode, trigger mode and polarity, interrupt level and priority,
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* assign handler for specific IRQn.
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*/
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extern int32_t ECLIC_Register_IRQ(IRQn_Type IRQn, uint8_t shv, ECLIC_TRIGGER_Type trig_mode, uint8_t lvl, uint8_t priority, void* handler);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __SYSTEM_GD32VF103_H__ */
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