83 lines
1.9 KiB
C
83 lines
1.9 KiB
C
/*
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* Copyright 2014-2016 Freescale Semiconductor, Inc.
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* Copyright 2016-2018 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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/**
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* @file fsl_device_registers.h
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* @brief support fsl device
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* @version 1.0
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* @author AIIT XUOS Lab
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* @date 2022-02-16
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*/
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/*************************************************
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File name: fsl_device_registers.h
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Description: support fsl device
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Others: take for references
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https://github.com/open-isa-org/open-isa.org
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History:
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1. Date: 2022-02-16
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Author: AIIT XUOS Lab
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Modification:
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*************************************************/
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#ifndef __FSL_DEVICE_REGISTERS_H__
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#define __FSL_DEVICE_REGISTERS_H__
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#define CPU_RV32M1_ri5cy
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/*
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* Include the cpu specific register header files.
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*
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* The CPU macro should be declared in the project or makefile.
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*/
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#if defined(CPU_RV32M1_cm0plus)
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#define RV32M1_cm0plus_SERIES
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/* CMSIS-style register definitions */
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#include "RV32M1_cm0plus.h"
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/* CPU specific feature definitions */
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#include "RV32M1_cm0plus_features.h"
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#elif defined(CPU_RV32M1_cm4)
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#define RV32M1_cm4_SERIES
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/* CMSIS-style register definitions */
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#include "RV32M1_cm4.h"
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/* CPU specific feature definitions */
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#include "RV32M1_cm4_features.h"
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#elif defined(CPU_RV32M1_zero_riscy)
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#define RV32M1_zero_riscy_SERIES
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/* CMSIS-style register definitions */
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#include "RV32M1_zero_riscy.h"
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/* CPU specific feature definitions */
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#include "RV32M1_zero_riscy_features.h"
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#elif defined(CPU_RV32M1_ri5cy)
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#define RV32M1_ri5cy_SERIES
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/* CMSIS-style register definitions */
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#include "RV32M1_ri5cy.h"
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/* CPU specific feature definitions */
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#include "RV32M1_ri5cy_features.h"
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#else
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#error "No valid CPU defined!"
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#endif
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#endif /* __FSL_DEVICE_REGISTERS_H__ */
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/*******************************************************************************
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* EOF
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******************************************************************************/
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