Wang_Weigen
499 lines
20 KiB
C
499 lines
20 KiB
C
/*
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* Copyright (c) 2012, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
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* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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/*
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* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
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*
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* This file was generated automatically and any changes may be lost.
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*/
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#ifndef __HW_SDMABP_REGISTERS_H__
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#define __HW_SDMABP_REGISTERS_H__
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#include "regs.h"
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/*
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* i.MX6DQ SDMABP
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*
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* SDMA
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*
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* Registers defined in this header file:
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* - HW_SDMABP_DC0PTR - Channel 0 Pointer
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* - HW_SDMABP_INTR - Channel Interrupts
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* - HW_SDMABP_STOP_STAT - Channel Stop/Channel Status
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* - HW_SDMABP_DSTART - Channel Start
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* - HW_SDMABP_EVTERR - DMA Request Error Register
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* - HW_SDMABP_INTRMASK - Channel DSP Interrupt Mask
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* - HW_SDMABP_EVTERRDBG - DMA Request Error Register
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*
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* - hw_sdmabp_t - Struct containing all module registers.
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*/
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//! @name Module base addresses
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//@{
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#ifndef REGS_SDMABP_BASE
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#define HW_SDMABP_INSTANCE_COUNT (1) //!< Number of instances of the SDMABP module.
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#define REGS_SDMABP_BASE (0x020ec000) //!< Base address for SDMABP.
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_SDMABP_DC0PTR - Channel 0 Pointer
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_SDMABP_DC0PTR - Channel 0 Pointer (RW)
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*
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* Reset value: 0x00000000
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*/
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typedef union _hw_sdmabp_dc0ptr
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{
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reg32_t U;
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struct _hw_sdmabp_dc0ptr_bitfields
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{
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unsigned DC0PTR : 32; //!< [31:0] Channel 0 Pointer contains the 32-bit address, in BP memory, of the array of channel control blocks starting with the one for channel 0 (the control channel).
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} B;
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} hw_sdmabp_dc0ptr_t;
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#endif
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/*!
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* @name Constants and macros for entire SDMABP_DC0PTR register
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*/
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//@{
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#define HW_SDMABP_DC0PTR_ADDR (REGS_SDMABP_BASE + 0x0)
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#ifndef __LANGUAGE_ASM__
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#define HW_SDMABP_DC0PTR (*(volatile hw_sdmabp_dc0ptr_t *) HW_SDMABP_DC0PTR_ADDR)
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#define HW_SDMABP_DC0PTR_RD() (HW_SDMABP_DC0PTR.U)
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#define HW_SDMABP_DC0PTR_WR(v) (HW_SDMABP_DC0PTR.U = (v))
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#define HW_SDMABP_DC0PTR_SET(v) (HW_SDMABP_DC0PTR_WR(HW_SDMABP_DC0PTR_RD() | (v)))
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#define HW_SDMABP_DC0PTR_CLR(v) (HW_SDMABP_DC0PTR_WR(HW_SDMABP_DC0PTR_RD() & ~(v)))
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#define HW_SDMABP_DC0PTR_TOG(v) (HW_SDMABP_DC0PTR_WR(HW_SDMABP_DC0PTR_RD() ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual SDMABP_DC0PTR bitfields
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*/
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/*! @name Register SDMABP_DC0PTR, field DC0PTR[31:0] (RW)
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*
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* Channel 0 Pointer contains the 32-bit address, in BP memory, of the array of channel control
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* blocks starting with the one for channel 0 (the control channel). This register should be
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* initialized by the BP before it enables a channel (for example, channel 0). See the API document
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* SDMA Scripts User Manual for the use of this register. The BP has a read/write access and the
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* SDMA has a read-only access.
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*/
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//@{
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#define BP_SDMABP_DC0PTR_DC0PTR (0) //!< Bit position for SDMABP_DC0PTR_DC0PTR.
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#define BM_SDMABP_DC0PTR_DC0PTR (0xffffffff) //!< Bit mask for SDMABP_DC0PTR_DC0PTR.
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//! @brief Get value of SDMABP_DC0PTR_DC0PTR from a register value.
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#define BG_SDMABP_DC0PTR_DC0PTR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMABP_DC0PTR_DC0PTR) >> BP_SDMABP_DC0PTR_DC0PTR)
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//! @brief Format value for bitfield SDMABP_DC0PTR_DC0PTR.
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#define BF_SDMABP_DC0PTR_DC0PTR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMABP_DC0PTR_DC0PTR) & BM_SDMABP_DC0PTR_DC0PTR)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DC0PTR field to a new value.
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#define BW_SDMABP_DC0PTR_DC0PTR(v) (HW_SDMABP_DC0PTR_WR((HW_SDMABP_DC0PTR_RD() & ~BM_SDMABP_DC0PTR_DC0PTR) | BF_SDMABP_DC0PTR_DC0PTR(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_SDMABP_INTR - Channel Interrupts
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_SDMABP_INTR - Channel Interrupts (W1C)
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*
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* Reset value: 0x00000000
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*/
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typedef union _hw_sdmabp_intr
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{
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reg32_t U;
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struct _hw_sdmabp_intr_bitfields
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{
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unsigned DI : 32; //!< [31:0] The BP Interrupts register contains the 32 DI[i] bits.
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} B;
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} hw_sdmabp_intr_t;
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#endif
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/*!
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* @name Constants and macros for entire SDMABP_INTR register
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*/
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//@{
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#define HW_SDMABP_INTR_ADDR (REGS_SDMABP_BASE + 0x4)
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#ifndef __LANGUAGE_ASM__
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#define HW_SDMABP_INTR (*(volatile hw_sdmabp_intr_t *) HW_SDMABP_INTR_ADDR)
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#define HW_SDMABP_INTR_RD() (HW_SDMABP_INTR.U)
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#define HW_SDMABP_INTR_WR(v) (HW_SDMABP_INTR.U = (v))
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#define HW_SDMABP_INTR_SET(v) (HW_SDMABP_INTR_WR(HW_SDMABP_INTR_RD() | (v)))
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#define HW_SDMABP_INTR_CLR(v) (HW_SDMABP_INTR_WR(HW_SDMABP_INTR_RD() & ~(v)))
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#define HW_SDMABP_INTR_TOG(v) (HW_SDMABP_INTR_WR(HW_SDMABP_INTR_RD() ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual SDMABP_INTR bitfields
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*/
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/*! @name Register SDMABP_INTR, field DI[31:0] (W1C)
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*
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* The BP Interrupts register contains the 32 DI[i] bits. If any bit is set, it will cause an
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* interrupt to the BP. This register is a "write-ones" register to the BP. When the BP sets a bit
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* in this register, the corresponding DI[i] bit is cleared. The interrupt service routine should
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* clear individual channel bits when their interrupts are serviced; failure to do so will cause
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* continuous interrupts. The SDMA is responsible for setting the DI[i] bit corresponding to the
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* current channel when the corresponding done instruction is executed.
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*/
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//@{
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#define BP_SDMABP_INTR_DI (0) //!< Bit position for SDMABP_INTR_DI.
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#define BM_SDMABP_INTR_DI (0xffffffff) //!< Bit mask for SDMABP_INTR_DI.
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//! @brief Get value of SDMABP_INTR_DI from a register value.
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#define BG_SDMABP_INTR_DI(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMABP_INTR_DI) >> BP_SDMABP_INTR_DI)
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//! @brief Format value for bitfield SDMABP_INTR_DI.
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#define BF_SDMABP_INTR_DI(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMABP_INTR_DI) & BM_SDMABP_INTR_DI)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DI field to a new value.
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#define BW_SDMABP_INTR_DI(v) (HW_SDMABP_INTR_WR((HW_SDMABP_INTR_RD() & ~BM_SDMABP_INTR_DI) | BF_SDMABP_INTR_DI(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_SDMABP_STOP_STAT - Channel Stop/Channel Status
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_SDMABP_STOP_STAT - Channel Stop/Channel Status (RW)
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*
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* Reset value: 0x00000000
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*/
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typedef union _hw_sdmabp_stop_stat
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{
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reg32_t U;
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struct _hw_sdmabp_stop_stat_bitfields
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{
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unsigned DE : 32; //!< [31:0] This 32-bit register gives access to the BP (DSP) Enable bits, DE.
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} B;
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} hw_sdmabp_stop_stat_t;
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#endif
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/*!
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* @name Constants and macros for entire SDMABP_STOP_STAT register
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*/
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//@{
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#define HW_SDMABP_STOP_STAT_ADDR (REGS_SDMABP_BASE + 0x8)
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#ifndef __LANGUAGE_ASM__
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#define HW_SDMABP_STOP_STAT (*(volatile hw_sdmabp_stop_stat_t *) HW_SDMABP_STOP_STAT_ADDR)
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#define HW_SDMABP_STOP_STAT_RD() (HW_SDMABP_STOP_STAT.U)
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#define HW_SDMABP_STOP_STAT_WR(v) (HW_SDMABP_STOP_STAT.U = (v))
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#define HW_SDMABP_STOP_STAT_SET(v) (HW_SDMABP_STOP_STAT_WR(HW_SDMABP_STOP_STAT_RD() | (v)))
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#define HW_SDMABP_STOP_STAT_CLR(v) (HW_SDMABP_STOP_STAT_WR(HW_SDMABP_STOP_STAT_RD() & ~(v)))
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#define HW_SDMABP_STOP_STAT_TOG(v) (HW_SDMABP_STOP_STAT_WR(HW_SDMABP_STOP_STAT_RD() ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual SDMABP_STOP_STAT bitfields
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*/
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/*! @name Register SDMABP_STOP_STAT, field DE[31:0] (W1C)
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*
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* This 32-bit register gives access to the BP (DSP) Enable bits, DE. There is one bit for every
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* channel. This register is a "write-ones" register to the BP. When the BP writes 1 in bit i of
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* this register, it clears the DE[i] and DSTART[i] bits. Reading this register yields the current
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* state of the DE[i] bits.
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*/
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//@{
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#define BP_SDMABP_STOP_STAT_DE (0) //!< Bit position for SDMABP_STOP_STAT_DE.
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#define BM_SDMABP_STOP_STAT_DE (0xffffffff) //!< Bit mask for SDMABP_STOP_STAT_DE.
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//! @brief Get value of SDMABP_STOP_STAT_DE from a register value.
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#define BG_SDMABP_STOP_STAT_DE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMABP_STOP_STAT_DE) >> BP_SDMABP_STOP_STAT_DE)
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//! @brief Format value for bitfield SDMABP_STOP_STAT_DE.
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#define BF_SDMABP_STOP_STAT_DE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMABP_STOP_STAT_DE) & BM_SDMABP_STOP_STAT_DE)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DE field to a new value.
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#define BW_SDMABP_STOP_STAT_DE(v) (HW_SDMABP_STOP_STAT_WR((HW_SDMABP_STOP_STAT_RD() & ~BM_SDMABP_STOP_STAT_DE) | BF_SDMABP_STOP_STAT_DE(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_SDMABP_DSTART - Channel Start
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_SDMABP_DSTART - Channel Start (RO)
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*
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* Reset value: 0x00000000
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*/
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typedef union _hw_sdmabp_dstart
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{
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reg32_t U;
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struct _hw_sdmabp_dstart_bitfields
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{
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unsigned DSTART_DE : 32; //!< [31:0] The DSTART_DE registers are 32 bits wide with one bit for every channel.
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} B;
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} hw_sdmabp_dstart_t;
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#endif
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/*!
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* @name Constants and macros for entire SDMABP_DSTART register
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*/
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//@{
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#define HW_SDMABP_DSTART_ADDR (REGS_SDMABP_BASE + 0xc)
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#ifndef __LANGUAGE_ASM__
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#define HW_SDMABP_DSTART (*(volatile hw_sdmabp_dstart_t *) HW_SDMABP_DSTART_ADDR)
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#define HW_SDMABP_DSTART_RD() (HW_SDMABP_DSTART.U)
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#endif
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//@}
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/*
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* constants & macros for individual SDMABP_DSTART bitfields
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*/
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/*! @name Register SDMABP_DSTART, field DSTART_DE[31:0] (RO)
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*
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* The DSTART_DE registers are 32 bits wide with one bit for every channel. When a bit is written to
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* 1, it enables the corresponding channel. Two physical registers are accessed with that address
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* (DSTART and DE), which enables the BP to trigger a channel a second time before the first trigger
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* was processed. This register is a "write-ones" register to the BP. Neither DSTART[i] bit can be
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* set while the corresponding DE[i] bit is cleared. When the BP tries to set the DSTART[i] bit by
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* writing a one (if the corresponding DE[i] bit is clear), the bit in the DSTART[i] register will
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* remain cleared and the DE[i] bit will be set. If the corresponding DE[i] bit was already set, the
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* DSTART[i] bit will be set. The next time the SDMA channel i attempts to clear the DE[i] bit by
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* means of a done instruction, the bit in the DSTART[i] register will be cleared and the DE[i] bit
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* will take the old value of the DSTART[i] bit. Reading this register yields the current state of
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* the DSTART[i] bits. This mechanism enables the BP to pipeline two DSTART commands per channel.
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*/
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//@{
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#define BP_SDMABP_DSTART_DSTART_DE (0) //!< Bit position for SDMABP_DSTART_DSTART_DE.
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#define BM_SDMABP_DSTART_DSTART_DE (0xffffffff) //!< Bit mask for SDMABP_DSTART_DSTART_DE.
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//! @brief Get value of SDMABP_DSTART_DSTART_DE from a register value.
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#define BG_SDMABP_DSTART_DSTART_DE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMABP_DSTART_DSTART_DE) >> BP_SDMABP_DSTART_DSTART_DE)
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_SDMABP_EVTERR - DMA Request Error Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_SDMABP_EVTERR - DMA Request Error Register (RO)
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*
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* Reset value: 0x00000000
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*/
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typedef union _hw_sdmabp_evterr
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{
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reg32_t U;
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struct _hw_sdmabp_evterr_bitfields
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{
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unsigned CHNERR : 32; //!< [31:0] This register is used by the SDMA to warn the BP when an incoming DMA request was detected; it then triggers a channel that is already pending or being serviced, which may mean there is an overflow of data for that channel.
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} B;
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} hw_sdmabp_evterr_t;
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#endif
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/*!
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* @name Constants and macros for entire SDMABP_EVTERR register
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*/
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//@{
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#define HW_SDMABP_EVTERR_ADDR (REGS_SDMABP_BASE + 0x28)
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#ifndef __LANGUAGE_ASM__
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#define HW_SDMABP_EVTERR (*(volatile hw_sdmabp_evterr_t *) HW_SDMABP_EVTERR_ADDR)
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#define HW_SDMABP_EVTERR_RD() (HW_SDMABP_EVTERR.U)
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#endif
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//@}
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/*
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* constants & macros for individual SDMABP_EVTERR bitfields
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*/
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/*! @name Register SDMABP_EVTERR, field CHNERR[31:0] (RO)
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*
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* This register is used by the SDMA to warn the BP when an incoming DMA request was detected; it
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* then triggers a channel that is already pending or being serviced, which may mean there is an
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* overflow of data for that channel. An interrupt is sent to the BP if the corresponding channel
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* bit is set in the INTRMASK register. This is a "write-ones" register for the scheduler. It is
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* only able to set the flags. The flags are cleared when the register is read by the BP or during
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* an SDMA reset. The CHNERR[i] bit is set when a DMA request that triggers channel i is received
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* through the corresponding input pins and the EP[i] bit is already set. The EVTERR[i] bit is
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* unaffected if the BP tries to set the EP[i] bit when that EP[i] bit is already set.
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*/
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//@{
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#define BP_SDMABP_EVTERR_CHNERR (0) //!< Bit position for SDMABP_EVTERR_CHNERR.
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#define BM_SDMABP_EVTERR_CHNERR (0xffffffff) //!< Bit mask for SDMABP_EVTERR_CHNERR.
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//! @brief Get value of SDMABP_EVTERR_CHNERR from a register value.
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#define BG_SDMABP_EVTERR_CHNERR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMABP_EVTERR_CHNERR) >> BP_SDMABP_EVTERR_CHNERR)
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_SDMABP_INTRMASK - Channel DSP Interrupt Mask
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_SDMABP_INTRMASK - Channel DSP Interrupt Mask (RW)
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*
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* Reset value: 0x00000000
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*/
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typedef union _hw_sdmabp_intrmask
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{
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reg32_t U;
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struct _hw_sdmabp_intrmask_bitfields
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{
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unsigned DIMASK : 32; //!< [31:0] The Interrupt Mask Register contains 32 interrupt generation mask bits.
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} B;
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} hw_sdmabp_intrmask_t;
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#endif
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/*!
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* @name Constants and macros for entire SDMABP_INTRMASK register
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*/
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//@{
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#define HW_SDMABP_INTRMASK_ADDR (REGS_SDMABP_BASE + 0x2c)
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#ifndef __LANGUAGE_ASM__
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#define HW_SDMABP_INTRMASK (*(volatile hw_sdmabp_intrmask_t *) HW_SDMABP_INTRMASK_ADDR)
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#define HW_SDMABP_INTRMASK_RD() (HW_SDMABP_INTRMASK.U)
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#define HW_SDMABP_INTRMASK_WR(v) (HW_SDMABP_INTRMASK.U = (v))
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#define HW_SDMABP_INTRMASK_SET(v) (HW_SDMABP_INTRMASK_WR(HW_SDMABP_INTRMASK_RD() | (v)))
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#define HW_SDMABP_INTRMASK_CLR(v) (HW_SDMABP_INTRMASK_WR(HW_SDMABP_INTRMASK_RD() & ~(v)))
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#define HW_SDMABP_INTRMASK_TOG(v) (HW_SDMABP_INTRMASK_WR(HW_SDMABP_INTRMASK_RD() ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual SDMABP_INTRMASK bitfields
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*/
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/*! @name Register SDMABP_INTRMASK, field DIMASK[31:0] (RW)
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*
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* The Interrupt Mask Register contains 32 interrupt generation mask bits. If bit DIMASK[i] is set,
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* the DI[i] bit is set and an interrupt is sent to the BP when a DMA request error is detected on
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* channel i (for example, EVTERR[i] is set).
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*/
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//@{
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#define BP_SDMABP_INTRMASK_DIMASK (0) //!< Bit position for SDMABP_INTRMASK_DIMASK.
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#define BM_SDMABP_INTRMASK_DIMASK (0xffffffff) //!< Bit mask for SDMABP_INTRMASK_DIMASK.
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//! @brief Get value of SDMABP_INTRMASK_DIMASK from a register value.
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#define BG_SDMABP_INTRMASK_DIMASK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMABP_INTRMASK_DIMASK) >> BP_SDMABP_INTRMASK_DIMASK)
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//! @brief Format value for bitfield SDMABP_INTRMASK_DIMASK.
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#define BF_SDMABP_INTRMASK_DIMASK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_SDMABP_INTRMASK_DIMASK) & BM_SDMABP_INTRMASK_DIMASK)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DIMASK field to a new value.
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#define BW_SDMABP_INTRMASK_DIMASK(v) (HW_SDMABP_INTRMASK_WR((HW_SDMABP_INTRMASK_RD() & ~BM_SDMABP_INTRMASK_DIMASK) | BF_SDMABP_INTRMASK_DIMASK(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_SDMABP_EVTERRDBG - DMA Request Error Register
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|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
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|
/*!
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|
* @brief HW_SDMABP_EVTERRDBG - DMA Request Error Register (RO)
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|
*
|
|
* Reset value: 0x00000000
|
|
*/
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|
typedef union _hw_sdmabp_evterrdbg
|
|
{
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reg32_t U;
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|
struct _hw_sdmabp_evterrdbg_bitfields
|
|
{
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|
unsigned CHNERR : 32; //!< [31:0] This register is the same as EVTERR except reading it does not clear its contents.
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|
} B;
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|
} hw_sdmabp_evterrdbg_t;
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|
#endif
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|
|
|
/*!
|
|
* @name Constants and macros for entire SDMABP_EVTERRDBG register
|
|
*/
|
|
//@{
|
|
#define HW_SDMABP_EVTERRDBG_ADDR (REGS_SDMABP_BASE + 0x34)
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|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_SDMABP_EVTERRDBG (*(volatile hw_sdmabp_evterrdbg_t *) HW_SDMABP_EVTERRDBG_ADDR)
|
|
#define HW_SDMABP_EVTERRDBG_RD() (HW_SDMABP_EVTERRDBG.U)
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual SDMABP_EVTERRDBG bitfields
|
|
*/
|
|
|
|
/*! @name Register SDMABP_EVTERRDBG, field CHNERR[31:0] (RO)
|
|
*
|
|
* This register is the same as EVTERR except reading it does not clear its contents. This address
|
|
* is meant to be used in debug mode. The BP OnCE may check this register value without modifying
|
|
* it.
|
|
*/
|
|
//@{
|
|
#define BP_SDMABP_EVTERRDBG_CHNERR (0) //!< Bit position for SDMABP_EVTERRDBG_CHNERR.
|
|
#define BM_SDMABP_EVTERRDBG_CHNERR (0xffffffff) //!< Bit mask for SDMABP_EVTERRDBG_CHNERR.
|
|
|
|
//! @brief Get value of SDMABP_EVTERRDBG_CHNERR from a register value.
|
|
#define BG_SDMABP_EVTERRDBG_CHNERR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_SDMABP_EVTERRDBG_CHNERR) >> BP_SDMABP_EVTERRDBG_CHNERR)
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// hw_sdmabp_t - module struct
|
|
//-------------------------------------------------------------------------------------------
|
|
/*!
|
|
* @brief All SDMABP module registers.
|
|
*/
|
|
#ifndef __LANGUAGE_ASM__
|
|
#pragma pack(1)
|
|
typedef struct _hw_sdmabp
|
|
{
|
|
volatile hw_sdmabp_dc0ptr_t DC0PTR; //!< Channel 0 Pointer
|
|
volatile hw_sdmabp_intr_t INTR; //!< Channel Interrupts
|
|
volatile hw_sdmabp_stop_stat_t STOP_STAT; //!< Channel Stop/Channel Status
|
|
volatile hw_sdmabp_dstart_t DSTART; //!< Channel Start
|
|
reg32_t _reserved0[6];
|
|
volatile hw_sdmabp_evterr_t EVTERR; //!< DMA Request Error Register
|
|
volatile hw_sdmabp_intrmask_t INTRMASK; //!< Channel DSP Interrupt Mask
|
|
reg32_t _reserved1;
|
|
volatile hw_sdmabp_evterrdbg_t EVTERRDBG; //!< DMA Request Error Register
|
|
} hw_sdmabp_t;
|
|
#pragma pack()
|
|
|
|
//! @brief Macro to access all SDMABP registers.
|
|
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
|
//! use the '&' operator, like <code>&HW_SDMABP</code>.
|
|
#define HW_SDMABP (*(hw_sdmabp_t *) REGS_SDMABP_BASE)
|
|
#endif
|
|
|
|
#endif // __HW_SDMABP_REGISTERS_H__
|
|
// v18/121106/1.2.2
|
|
// EOF
|