Wang_Weigen
564 lines
24 KiB
C
564 lines
24 KiB
C
/*
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* Copyright (c) 2012, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
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* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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/*
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* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
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*
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* This file was generated automatically and any changes may be lost.
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*/
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#ifndef __HW_ROMC_REGISTERS_H__
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#define __HW_ROMC_REGISTERS_H__
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#include "regs.h"
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/*
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* i.MX6DQ ROMC
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*
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* ROMC
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*
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* Registers defined in this header file:
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* - HW_ROMC_ROMPATCHnD - ROMC Data Registers
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* - HW_ROMC_ROMPATCHCNTL - ROMC Control Register
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* - HW_ROMC_ROMPATCHENH - ROMC Enable Register High
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* - HW_ROMC_ROMPATCHENL - ROMC Enable Register Low
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* - HW_ROMC_ROMPATCHnA - ROMC Address Registers
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* - HW_ROMC_ROMPATCHSR - ROMC Status Register
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*
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* - hw_romc_t - Struct containing all module registers.
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*/
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//! @name Module base addresses
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//@{
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#ifndef REGS_ROMC_BASE
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#define HW_ROMC_INSTANCE_COUNT (1) //!< Number of instances of the ROMC module.
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#define REGS_ROMC_BASE (0x021ac000) //!< Base address for ROMC.
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_ROMC_ROMPATCHnD - ROMC Data Registers
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_ROMC_ROMPATCHnD - ROMC Data Registers (RW)
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*
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* Reset value: 0x00000000
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*
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* The ROMC data registers (ROMC_ROMPATCHD7 through ROMC_ROMPATCHD0) store the data to use for the 8
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* 1-word data fix events. Each register is associated with an address comparator (7 through 0).
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* When a data fixing event occurs, the value in the data register corresponding to the comparator
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* that has the address match is put on the romc_hrdata[31:0] bus until romc_hready is asserted by
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* the ROM controller to terminate the access. A MUX external to the ROMC will select this data over
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* that of romc_hrdata[31:0] in returning read data to the ARM core. The selection is done with the
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* control bus rompatch_romc_hrdata_ovr[1:0] with both bits asserted by the ROMC. If more than one
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* address comparators match, the highest-numbered one takes precedence, and the value in
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* corresponding data register is used for the patching event.
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*/
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typedef union _hw_romc_rompatchnd
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{
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reg32_t U;
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struct _hw_romc_rompatchnd_bitfields
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{
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unsigned DATAX : 32; //!< [31:0] Data Fix Registers - Stores the data used for 1-word data fix operations.
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} B;
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} hw_romc_rompatchnd_t;
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#endif
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/*!
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* @name Constants and macros for entire ROMC_ROMPATCHnD register
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*/
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//@{
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//! @brief Number of instances of the ROMC_ROMPATCHnD register.
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#define HW_ROMC_ROMPATCHnD_COUNT (8)
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#define HW_ROMC_ROMPATCHnD_ADDR(n) (REGS_ROMC_BASE + 0xd4 + (0x4 * (n)))
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#ifndef __LANGUAGE_ASM__
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#define HW_ROMC_ROMPATCHnD(n) (*(volatile hw_romc_rompatchnd_t *) HW_ROMC_ROMPATCHnD_ADDR(n))
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#define HW_ROMC_ROMPATCHnD_RD(n) (HW_ROMC_ROMPATCHnD(n).U)
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#define HW_ROMC_ROMPATCHnD_WR(n, v) (HW_ROMC_ROMPATCHnD(n).U = (v))
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#define HW_ROMC_ROMPATCHnD_SET(n, v) (HW_ROMC_ROMPATCHnD_WR(n, HW_ROMC_ROMPATCHnD_RD(n) | (v)))
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#define HW_ROMC_ROMPATCHnD_CLR(n, v) (HW_ROMC_ROMPATCHnD_WR(n, HW_ROMC_ROMPATCHnD_RD(n) & ~(v)))
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#define HW_ROMC_ROMPATCHnD_TOG(n, v) (HW_ROMC_ROMPATCHnD_WR(n, HW_ROMC_ROMPATCHnD_RD(n) ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual ROMC_ROMPATCHnD bitfields
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*/
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/*! @name Register ROMC_ROMPATCHnD, field DATAX[31:0] (RW)
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*
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* Data Fix Registers - Stores the data used for 1-word data fix operations. The values stored
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* within these registers do not affect the writes to the memory system. They are selected over the
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* read data from ROM when a data fix event occurs. If any part of the 1-word data fix is read, then
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* the entire word is replaced. Therefore, a byte or half-word read will cause the ROMC to replace
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* the entire word. The word is word address aligned.
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*/
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//@{
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#define BP_ROMC_ROMPATCHnD_DATAX (0) //!< Bit position for ROMC_ROMPATCHnD_DATAX.
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#define BM_ROMC_ROMPATCHnD_DATAX (0xffffffff) //!< Bit mask for ROMC_ROMPATCHnD_DATAX.
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//! @brief Get value of ROMC_ROMPATCHnD_DATAX from a register value.
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#define BG_ROMC_ROMPATCHnD_DATAX(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ROMC_ROMPATCHnD_DATAX) >> BP_ROMC_ROMPATCHnD_DATAX)
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//! @brief Format value for bitfield ROMC_ROMPATCHnD_DATAX.
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#define BF_ROMC_ROMPATCHnD_DATAX(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ROMC_ROMPATCHnD_DATAX) & BM_ROMC_ROMPATCHnD_DATAX)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DATAX field to a new value.
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#define BW_ROMC_ROMPATCHnD_DATAX(n, v) (HW_ROMC_ROMPATCHnD_WR(n, (HW_ROMC_ROMPATCHnD_RD(n) & ~BM_ROMC_ROMPATCHnD_DATAX) | BF_ROMC_ROMPATCHnD_DATAX(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_ROMC_ROMPATCHCNTL - ROMC Control Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_ROMC_ROMPATCHCNTL - ROMC Control Register (RW)
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*
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* Reset value: 0x08400000
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*
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* The ROMC control register (ROMC_ROMPATCHCNTL) contains the block disable bit and the data fix
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* enable bits. The block disable bit provides a means to disable the ROMC data fix and opcode
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* patching functions, even when the address comparators are enabled. The External Boot feature is
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* not affected by this bit. The eight data fix enable bits (0 through 7), when set, assign the
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* associated address comparators to data fix operations Bits 27 and 22 always read as 1s.
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*/
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typedef union _hw_romc_rompatchcntl
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{
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reg32_t U;
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struct _hw_romc_rompatchcntl_bitfields
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{
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unsigned DATAFIX : 8; //!< [7:0] Data Fix Enable - Controls the use of the first 8 address comparators for 1-word data fix or for code patch routine.
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unsigned RESERVED0 : 21; //!< [28:8] Reserved
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unsigned DIS : 1; //!< [29] ROMC Disable -- This bit, when set, disables all ROMC operations.
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unsigned RESERVED1 : 2; //!< [31:30] Reserved
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} B;
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} hw_romc_rompatchcntl_t;
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#endif
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/*!
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* @name Constants and macros for entire ROMC_ROMPATCHCNTL register
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*/
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//@{
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#define HW_ROMC_ROMPATCHCNTL_ADDR (REGS_ROMC_BASE + 0xf4)
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#ifndef __LANGUAGE_ASM__
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#define HW_ROMC_ROMPATCHCNTL (*(volatile hw_romc_rompatchcntl_t *) HW_ROMC_ROMPATCHCNTL_ADDR)
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#define HW_ROMC_ROMPATCHCNTL_RD() (HW_ROMC_ROMPATCHCNTL.U)
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#define HW_ROMC_ROMPATCHCNTL_WR(v) (HW_ROMC_ROMPATCHCNTL.U = (v))
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#define HW_ROMC_ROMPATCHCNTL_SET(v) (HW_ROMC_ROMPATCHCNTL_WR(HW_ROMC_ROMPATCHCNTL_RD() | (v)))
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#define HW_ROMC_ROMPATCHCNTL_CLR(v) (HW_ROMC_ROMPATCHCNTL_WR(HW_ROMC_ROMPATCHCNTL_RD() & ~(v)))
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#define HW_ROMC_ROMPATCHCNTL_TOG(v) (HW_ROMC_ROMPATCHCNTL_WR(HW_ROMC_ROMPATCHCNTL_RD() ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual ROMC_ROMPATCHCNTL bitfields
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*/
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/*! @name Register ROMC_ROMPATCHCNTL, field DATAFIX[7:0] (RW)
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*
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* Data Fix Enable - Controls the use of the first 8 address comparators for 1-word data fix or for
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* code patch routine.
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*
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* Values:
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* - 0 - Address comparator triggers a opcode patch
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* - 1 - Address comparator triggers a data fix
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*/
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//@{
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#define BP_ROMC_ROMPATCHCNTL_DATAFIX (0) //!< Bit position for ROMC_ROMPATCHCNTL_DATAFIX.
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#define BM_ROMC_ROMPATCHCNTL_DATAFIX (0x000000ff) //!< Bit mask for ROMC_ROMPATCHCNTL_DATAFIX.
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//! @brief Get value of ROMC_ROMPATCHCNTL_DATAFIX from a register value.
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#define BG_ROMC_ROMPATCHCNTL_DATAFIX(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ROMC_ROMPATCHCNTL_DATAFIX) >> BP_ROMC_ROMPATCHCNTL_DATAFIX)
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//! @brief Format value for bitfield ROMC_ROMPATCHCNTL_DATAFIX.
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#define BF_ROMC_ROMPATCHCNTL_DATAFIX(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ROMC_ROMPATCHCNTL_DATAFIX) & BM_ROMC_ROMPATCHCNTL_DATAFIX)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DATAFIX field to a new value.
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#define BW_ROMC_ROMPATCHCNTL_DATAFIX(v) (HW_ROMC_ROMPATCHCNTL_WR((HW_ROMC_ROMPATCHCNTL_RD() & ~BM_ROMC_ROMPATCHCNTL_DATAFIX) | BF_ROMC_ROMPATCHCNTL_DATAFIX(v)))
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#endif
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//@}
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/*! @name Register ROMC_ROMPATCHCNTL, field DIS[29] (RW)
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*
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* ROMC Disable -- This bit, when set, disables all ROMC operations. This bit is used to enable
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* secure operations.
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*
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* Values:
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* - 0 - Does not affect any ROMC functions (default)
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* - 1 - Disable all ROMC functions: data fixing, and opcode patching
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*/
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//@{
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#define BP_ROMC_ROMPATCHCNTL_DIS (29) //!< Bit position for ROMC_ROMPATCHCNTL_DIS.
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#define BM_ROMC_ROMPATCHCNTL_DIS (0x20000000) //!< Bit mask for ROMC_ROMPATCHCNTL_DIS.
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//! @brief Get value of ROMC_ROMPATCHCNTL_DIS from a register value.
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#define BG_ROMC_ROMPATCHCNTL_DIS(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ROMC_ROMPATCHCNTL_DIS) >> BP_ROMC_ROMPATCHCNTL_DIS)
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//! @brief Format value for bitfield ROMC_ROMPATCHCNTL_DIS.
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#define BF_ROMC_ROMPATCHCNTL_DIS(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ROMC_ROMPATCHCNTL_DIS) & BM_ROMC_ROMPATCHCNTL_DIS)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DIS field to a new value.
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#define BW_ROMC_ROMPATCHCNTL_DIS(v) (HW_ROMC_ROMPATCHCNTL_WR((HW_ROMC_ROMPATCHCNTL_RD() & ~BM_ROMC_ROMPATCHCNTL_DIS) | BF_ROMC_ROMPATCHCNTL_DIS(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_ROMC_ROMPATCHENH - ROMC Enable Register High
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_ROMC_ROMPATCHENH - ROMC Enable Register High (RO)
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*
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* Reset value: 0x00000000
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*
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* The ROMC enable register high (ROMC_ROMPATCHENH) and ROMC enable register low (ROMC_ROMPATCHENL)
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* control whether or not the associated address comparator can trigger a opcode patch or data fix
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* event. This implementation of the ROMC only has 16 comparators, therefore ROMC_ROMPATCHENH and
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* the upper half of ROMC_OMPATCHENL are read-only. ROMC_ROMPATCHENL[15:0] are associated with
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* comparators 15 through 0. ROMC_ROMPATCHENLH[31:0] would have been associated with comparators 63
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* through 32.
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*/
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typedef union _hw_romc_rompatchenh
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{
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reg32_t U;
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struct _hw_romc_rompatchenh_bitfields
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{
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unsigned RESERVED0 : 32; //!< [31:0] Reserved
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} B;
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} hw_romc_rompatchenh_t;
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#endif
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/*!
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* @name Constants and macros for entire ROMC_ROMPATCHENH register
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*/
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//@{
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#define HW_ROMC_ROMPATCHENH_ADDR (REGS_ROMC_BASE + 0xf8)
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#ifndef __LANGUAGE_ASM__
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#define HW_ROMC_ROMPATCHENH (*(volatile hw_romc_rompatchenh_t *) HW_ROMC_ROMPATCHENH_ADDR)
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#define HW_ROMC_ROMPATCHENH_RD() (HW_ROMC_ROMPATCHENH.U)
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#endif
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//@}
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/*
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* constants & macros for individual ROMC_ROMPATCHENH bitfields
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*/
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//-------------------------------------------------------------------------------------------
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// HW_ROMC_ROMPATCHENL - ROMC Enable Register Low
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_ROMC_ROMPATCHENL - ROMC Enable Register Low (RW)
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*
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* Reset value: 0x00000000
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*
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* The ROMC enable register high (ROMC_ROMPATCHENH) and ROMC enable register low (ROMC_ROMPATCHENL)
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* control whether or not the associated address comparator can trigger a opcode patch or data fix
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* event. This implementation of the ROMC only has 16 comparators, therefore ROMC_ROMPATCHENH and
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* the upper half of ROMC_ROMPATCHENL are read-only. ROMC_ROMPATCHENL[15:0] are associated with
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* comparators 15 through 0. ROMC_ROMPATCHENLH[31:0] would have been associated with comparators 63
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* through 32.
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*/
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typedef union _hw_romc_rompatchenl
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{
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reg32_t U;
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struct _hw_romc_rompatchenl_bitfields
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{
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unsigned ENABLE : 16; //!< [15:0] Enable Address Comparator - This bit enables the corresponding address comparator to trigger an event.
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unsigned RESERVED0 : 16; //!< [31:16]
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} B;
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} hw_romc_rompatchenl_t;
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#endif
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/*!
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* @name Constants and macros for entire ROMC_ROMPATCHENL register
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*/
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//@{
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#define HW_ROMC_ROMPATCHENL_ADDR (REGS_ROMC_BASE + 0xfc)
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#ifndef __LANGUAGE_ASM__
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#define HW_ROMC_ROMPATCHENL (*(volatile hw_romc_rompatchenl_t *) HW_ROMC_ROMPATCHENL_ADDR)
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#define HW_ROMC_ROMPATCHENL_RD() (HW_ROMC_ROMPATCHENL.U)
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#define HW_ROMC_ROMPATCHENL_WR(v) (HW_ROMC_ROMPATCHENL.U = (v))
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#define HW_ROMC_ROMPATCHENL_SET(v) (HW_ROMC_ROMPATCHENL_WR(HW_ROMC_ROMPATCHENL_RD() | (v)))
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#define HW_ROMC_ROMPATCHENL_CLR(v) (HW_ROMC_ROMPATCHENL_WR(HW_ROMC_ROMPATCHENL_RD() & ~(v)))
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#define HW_ROMC_ROMPATCHENL_TOG(v) (HW_ROMC_ROMPATCHENL_WR(HW_ROMC_ROMPATCHENL_RD() ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual ROMC_ROMPATCHENL bitfields
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*/
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/*! @name Register ROMC_ROMPATCHENL, field ENABLE[15:0] (RW)
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*
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* Enable Address Comparator - This bit enables the corresponding address comparator to trigger an
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* event.
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*
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* Values:
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* - 0 - Address comparator disabled
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* - 1 - Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the
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* associated address
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*/
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//@{
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#define BP_ROMC_ROMPATCHENL_ENABLE (0) //!< Bit position for ROMC_ROMPATCHENL_ENABLE.
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#define BM_ROMC_ROMPATCHENL_ENABLE (0x0000ffff) //!< Bit mask for ROMC_ROMPATCHENL_ENABLE.
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//! @brief Get value of ROMC_ROMPATCHENL_ENABLE from a register value.
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#define BG_ROMC_ROMPATCHENL_ENABLE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ROMC_ROMPATCHENL_ENABLE) >> BP_ROMC_ROMPATCHENL_ENABLE)
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//! @brief Format value for bitfield ROMC_ROMPATCHENL_ENABLE.
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#define BF_ROMC_ROMPATCHENL_ENABLE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ROMC_ROMPATCHENL_ENABLE) & BM_ROMC_ROMPATCHENL_ENABLE)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the ENABLE field to a new value.
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#define BW_ROMC_ROMPATCHENL_ENABLE(v) (HW_ROMC_ROMPATCHENL_WR((HW_ROMC_ROMPATCHENL_RD() & ~BM_ROMC_ROMPATCHENL_ENABLE) | BF_ROMC_ROMPATCHENL_ENABLE(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_ROMC_ROMPATCHnA - ROMC Address Registers
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_ROMC_ROMPATCHnA - ROMC Address Registers (RW)
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*
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* Reset value: 0x00000000
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*
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* The ROMC address registers (ROMC_ROMPATCHA0 through ROMC_ROMPATCHA15) store the memory addresses
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* where opcode patching begins and data fixing occurs. The address registers ROMC_ROMPATCHA0
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* through ROMC_ROMPATCHA15 are each 21 bits wide and dedicated to one 4 Mbyte memory space. Bits 21
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* through 2 are address bits, to be compared with romc_haddr[21:2] for a match; bit 1 is also an
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* address bit used for half word selection. Bit 0 is the mode bit (set to 1 for THUMB mode). 1-word
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* data fixing can only be used on the first 8 of the address comparators. ROMC_ROMPATCHA0 through
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* ROMC_ROMPATCHA15 are associated each with address comparators 0 through 15.
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*/
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typedef union _hw_romc_rompatchna
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{
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reg32_t U;
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struct _hw_romc_rompatchna_bitfields
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{
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unsigned THUMBX : 1; //!< [0] THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an ARM opcode patch.
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unsigned ADDRX : 22; //!< [22:1] Address Comparator Registers - Indicates the memory address to be watched.
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unsigned RESERVED0 : 9; //!< [31:23] Reserved
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} B;
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} hw_romc_rompatchna_t;
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#endif
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/*!
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* @name Constants and macros for entire ROMC_ROMPATCHnA register
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*/
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//@{
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//! @brief Number of instances of the ROMC_ROMPATCHnA register.
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#define HW_ROMC_ROMPATCHnA_COUNT (16)
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#define HW_ROMC_ROMPATCHnA_ADDR(n) (REGS_ROMC_BASE + 0x100 + (0x4 * (n)))
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#ifndef __LANGUAGE_ASM__
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#define HW_ROMC_ROMPATCHnA(n) (*(volatile hw_romc_rompatchna_t *) HW_ROMC_ROMPATCHnA_ADDR(n))
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#define HW_ROMC_ROMPATCHnA_RD(n) (HW_ROMC_ROMPATCHnA(n).U)
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#define HW_ROMC_ROMPATCHnA_WR(n, v) (HW_ROMC_ROMPATCHnA(n).U = (v))
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#define HW_ROMC_ROMPATCHnA_SET(n, v) (HW_ROMC_ROMPATCHnA_WR(n, HW_ROMC_ROMPATCHnA_RD(n) | (v)))
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#define HW_ROMC_ROMPATCHnA_CLR(n, v) (HW_ROMC_ROMPATCHnA_WR(n, HW_ROMC_ROMPATCHnA_RD(n) & ~(v)))
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#define HW_ROMC_ROMPATCHnA_TOG(n, v) (HW_ROMC_ROMPATCHnA_WR(n, HW_ROMC_ROMPATCHnA_RD(n) ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual ROMC_ROMPATCHnA bitfields
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*/
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/*! @name Register ROMC_ROMPATCHnA, field THUMBX[0] (RW)
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*
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* THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an ARM
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* opcode patch. If this watchpoint is selected to be a data fix, then this bit is ignored as all
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* data fixes are 1-word data fixes.
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*
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* Values:
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* - 0 - ARM patch
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* - 1 - THUMB patch (ignore if data fix)
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*/
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//@{
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#define BP_ROMC_ROMPATCHnA_THUMBX (0) //!< Bit position for ROMC_ROMPATCHnA_THUMBX.
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#define BM_ROMC_ROMPATCHnA_THUMBX (0x00000001) //!< Bit mask for ROMC_ROMPATCHnA_THUMBX.
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//! @brief Get value of ROMC_ROMPATCHnA_THUMBX from a register value.
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#define BG_ROMC_ROMPATCHnA_THUMBX(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ROMC_ROMPATCHnA_THUMBX) >> BP_ROMC_ROMPATCHnA_THUMBX)
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//! @brief Format value for bitfield ROMC_ROMPATCHnA_THUMBX.
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#define BF_ROMC_ROMPATCHnA_THUMBX(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ROMC_ROMPATCHnA_THUMBX) & BM_ROMC_ROMPATCHnA_THUMBX)
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|
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the THUMBX field to a new value.
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|
#define BW_ROMC_ROMPATCHnA_THUMBX(n, v) (HW_ROMC_ROMPATCHnA_WR(n, (HW_ROMC_ROMPATCHnA_RD(n) & ~BM_ROMC_ROMPATCHnA_THUMBX) | BF_ROMC_ROMPATCHnA_THUMBX(v)))
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#endif
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|
//@}
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|
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|
/*! @name Register ROMC_ROMPATCHnA, field ADDRX[22:1] (RW)
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|
*
|
|
* Address Comparator Registers - Indicates the memory address to be watched. All 16 registers can
|
|
* be used for code patch address comparison. Only the first 8 registers can be used for a 1-word
|
|
* data fix address comparison. Bit 1 is ignored if data fix. Only used in code patch
|
|
*/
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|
//@{
|
|
#define BP_ROMC_ROMPATCHnA_ADDRX (1) //!< Bit position for ROMC_ROMPATCHnA_ADDRX.
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#define BM_ROMC_ROMPATCHnA_ADDRX (0x007ffffe) //!< Bit mask for ROMC_ROMPATCHnA_ADDRX.
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|
|
|
//! @brief Get value of ROMC_ROMPATCHnA_ADDRX from a register value.
|
|
#define BG_ROMC_ROMPATCHnA_ADDRX(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ROMC_ROMPATCHnA_ADDRX) >> BP_ROMC_ROMPATCHnA_ADDRX)
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|
|
|
//! @brief Format value for bitfield ROMC_ROMPATCHnA_ADDRX.
|
|
#define BF_ROMC_ROMPATCHnA_ADDRX(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ROMC_ROMPATCHnA_ADDRX) & BM_ROMC_ROMPATCHnA_ADDRX)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ADDRX field to a new value.
|
|
#define BW_ROMC_ROMPATCHnA_ADDRX(n, v) (HW_ROMC_ROMPATCHnA_WR(n, (HW_ROMC_ROMPATCHnA_RD(n) & ~BM_ROMC_ROMPATCHnA_ADDRX) | BF_ROMC_ROMPATCHnA_ADDRX(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_ROMC_ROMPATCHSR - ROMC Status Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_ROMC_ROMPATCHSR - ROMC Status Register (W1C)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*
|
|
* The ROMC status register (ROMC_ROMPATCHSR) indicates the current state of the ROMC and the source
|
|
* number of the most recent address comparator event.
|
|
*/
|
|
typedef union _hw_romc_rompatchsr
|
|
{
|
|
reg32_t U;
|
|
struct _hw_romc_rompatchsr_bitfields
|
|
{
|
|
unsigned SOURCE : 6; //!< [5:0] ROMC Source Number - Binary encoding of the number of the address comparator which has an address match in the most recent patch event on ROMC AHB.
|
|
unsigned RESERVED0 : 11; //!< [16:6] Reserved
|
|
unsigned SW : 1; //!< [17] ROMC AHB Multiple Address Comparator matches Indicator - Indicates that multiple address comparator matches occurred.
|
|
unsigned RESERVED1 : 14; //!< [31:18] Reserved
|
|
} B;
|
|
} hw_romc_rompatchsr_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire ROMC_ROMPATCHSR register
|
|
*/
|
|
//@{
|
|
#define HW_ROMC_ROMPATCHSR_ADDR (REGS_ROMC_BASE + 0x208)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_ROMC_ROMPATCHSR (*(volatile hw_romc_rompatchsr_t *) HW_ROMC_ROMPATCHSR_ADDR)
|
|
#define HW_ROMC_ROMPATCHSR_RD() (HW_ROMC_ROMPATCHSR.U)
|
|
#define HW_ROMC_ROMPATCHSR_WR(v) (HW_ROMC_ROMPATCHSR.U = (v))
|
|
#define HW_ROMC_ROMPATCHSR_SET(v) (HW_ROMC_ROMPATCHSR_WR(HW_ROMC_ROMPATCHSR_RD() | (v)))
|
|
#define HW_ROMC_ROMPATCHSR_CLR(v) (HW_ROMC_ROMPATCHSR_WR(HW_ROMC_ROMPATCHSR_RD() & ~(v)))
|
|
#define HW_ROMC_ROMPATCHSR_TOG(v) (HW_ROMC_ROMPATCHSR_WR(HW_ROMC_ROMPATCHSR_RD() ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual ROMC_ROMPATCHSR bitfields
|
|
*/
|
|
|
|
/*! @name Register ROMC_ROMPATCHSR, field SOURCE[5:0] (RO)
|
|
*
|
|
* ROMC Source Number - Binary encoding of the number of the address comparator which has an address
|
|
* match in the most recent patch event on ROMC AHB. If multiple matches occurred, the highest
|
|
* priority source number is used.
|
|
*
|
|
* Values:
|
|
* - 0 - Address Comparator 0 matched
|
|
* - 1 - Address Comparator 1 matched
|
|
* - 15 - Address Comparator 15 matched
|
|
*/
|
|
//@{
|
|
#define BP_ROMC_ROMPATCHSR_SOURCE (0) //!< Bit position for ROMC_ROMPATCHSR_SOURCE.
|
|
#define BM_ROMC_ROMPATCHSR_SOURCE (0x0000003f) //!< Bit mask for ROMC_ROMPATCHSR_SOURCE.
|
|
|
|
//! @brief Get value of ROMC_ROMPATCHSR_SOURCE from a register value.
|
|
#define BG_ROMC_ROMPATCHSR_SOURCE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ROMC_ROMPATCHSR_SOURCE) >> BP_ROMC_ROMPATCHSR_SOURCE)
|
|
//@}
|
|
|
|
/*! @name Register ROMC_ROMPATCHSR, field SW[17] (W1C)
|
|
*
|
|
* ROMC AHB Multiple Address Comparator matches Indicator - Indicates that multiple address
|
|
* comparator matches occurred. Writing a 1 to this bit will clear this it.
|
|
*
|
|
* Values:
|
|
* - 0 - no event or comparator collisions
|
|
* - 1 - a collision has occurred
|
|
*/
|
|
//@{
|
|
#define BP_ROMC_ROMPATCHSR_SW (17) //!< Bit position for ROMC_ROMPATCHSR_SW.
|
|
#define BM_ROMC_ROMPATCHSR_SW (0x00020000) //!< Bit mask for ROMC_ROMPATCHSR_SW.
|
|
|
|
//! @brief Get value of ROMC_ROMPATCHSR_SW from a register value.
|
|
#define BG_ROMC_ROMPATCHSR_SW(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_ROMC_ROMPATCHSR_SW) >> BP_ROMC_ROMPATCHSR_SW)
|
|
|
|
//! @brief Format value for bitfield ROMC_ROMPATCHSR_SW.
|
|
#define BF_ROMC_ROMPATCHSR_SW(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_ROMC_ROMPATCHSR_SW) & BM_ROMC_ROMPATCHSR_SW)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the SW field to a new value.
|
|
#define BW_ROMC_ROMPATCHSR_SW(v) (HW_ROMC_ROMPATCHSR_WR((HW_ROMC_ROMPATCHSR_RD() & ~BM_ROMC_ROMPATCHSR_SW) | BF_ROMC_ROMPATCHSR_SW(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// hw_romc_t - module struct
|
|
//-------------------------------------------------------------------------------------------
|
|
/*!
|
|
* @brief All ROMC module registers.
|
|
*/
|
|
#ifndef __LANGUAGE_ASM__
|
|
#pragma pack(1)
|
|
typedef struct _hw_romc
|
|
{
|
|
reg32_t _reserved0[53];
|
|
volatile hw_romc_rompatchnd_t ROMPATCHnD[8]; //!< ROMC Data Registers
|
|
volatile hw_romc_rompatchcntl_t ROMPATCHCNTL; //!< ROMC Control Register
|
|
volatile hw_romc_rompatchenh_t ROMPATCHENH; //!< ROMC Enable Register High
|
|
volatile hw_romc_rompatchenl_t ROMPATCHENL; //!< ROMC Enable Register Low
|
|
volatile hw_romc_rompatchna_t ROMPATCHnA[16]; //!< ROMC Address Registers
|
|
reg32_t _reserved1[50];
|
|
volatile hw_romc_rompatchsr_t ROMPATCHSR; //!< ROMC Status Register
|
|
} hw_romc_t;
|
|
#pragma pack()
|
|
|
|
//! @brief Macro to access all ROMC registers.
|
|
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
|
//! use the '&' operator, like <code>&HW_ROMC</code>.
|
|
#define HW_ROMC (*(hw_romc_t *) REGS_ROMC_BASE)
|
|
#endif
|
|
|
|
#endif // __HW_ROMC_REGISTERS_H__
|
|
// v18/121106/1.2.2
|
|
// EOF
|