Wang_Weigen
836 lines
33 KiB
C
836 lines
33 KiB
C
/*
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* Copyright (c) 2012, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
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* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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/*
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* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
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*
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* This file was generated automatically and any changes may be lost.
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*/
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#ifndef __HW_DCIC_REGISTERS_H__
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#define __HW_DCIC_REGISTERS_H__
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#include "regs.h"
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/*
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* i.MX6DQ DCIC
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*
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* DCIC
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*
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* Registers defined in this header file:
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* - HW_DCIC_DCICC - DCIC Control Register
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* - HW_DCIC_DCICIC - DCIC Interrupt Control Register
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* - HW_DCIC_DCICS - DCIC Status Register
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* - HW_DCIC_DCICRC - DCIC ROI Config Register m
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* - HW_DCIC_DCICRS - DCIC ROI Size Register m
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* - HW_DCIC_DCICRRS - DCIC ROI Reference Signature Register m
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* - HW_DCIC_DCICRCS - DCIC ROI Calculated Signature m
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*
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* - hw_dcic_t - Struct containing all module registers.
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*/
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//! @name Module base addresses
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//@{
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#ifndef REGS_DCIC_BASE
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#define HW_DCIC_INSTANCE_COUNT (2) //!< Number of instances of the DCIC module.
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#define HW_DCIC1 (1) //!< Instance number for DCIC1.
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#define HW_DCIC2 (2) //!< Instance number for DCIC2.
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#define REGS_DCIC1_BASE (0x020e4000) //!< Base address for DCIC instance number 1.
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#define REGS_DCIC2_BASE (0x020e8000) //!< Base address for DCIC instance number 2.
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//! @brief Get the base address of DCIC by instance number.
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//! @param x DCIC instance number, from 1 through 2.
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#define REGS_DCIC_BASE(x) ( (x) == HW_DCIC1 ? REGS_DCIC1_BASE : (x) == HW_DCIC2 ? REGS_DCIC2_BASE : 0x00d00000)
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//! @brief Get the instance number given a base address.
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//! @param b Base address for an instance of DCIC.
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#define REGS_DCIC_INSTANCE(b) ( (b) == REGS_DCIC1_BASE ? HW_DCIC1 : (b) == REGS_DCIC2_BASE ? HW_DCIC2 : 0)
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_DCIC_DCICC - DCIC Control Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_DCIC_DCICC - DCIC Control Register (RW)
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*
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* Reset value: 0x00000070
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*/
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typedef union _hw_dcic_dcicc
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{
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reg32_t U;
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struct _hw_dcic_dcicc_bitfields
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{
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unsigned IC_EN : 1; //!< [0] Integrity Check enable.
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unsigned RESERVED0 : 3; //!< [3:1] Reserved
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unsigned DE_POL : 1; //!< [4] DATA_EN_IN signal polarity.
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unsigned HSYNC_POL : 1; //!< [5] HSYNC_IN signal polarity.
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unsigned VSYNC_POL : 1; //!< [6] VSYNC_IN signal polarity.
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unsigned CLK_POL : 1; //!< [7] DISP_CLK signal polarity.
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unsigned RESERVED1 : 24; //!< [31:8] Reserved
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} B;
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} hw_dcic_dcicc_t;
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#endif
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/*!
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* @name Constants and macros for entire DCIC_DCICC register
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*/
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//@{
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#define HW_DCIC_DCICC_ADDR(x) (REGS_DCIC_BASE(x) + 0x0)
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#ifndef __LANGUAGE_ASM__
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#define HW_DCIC_DCICC(x) (*(volatile hw_dcic_dcicc_t *) HW_DCIC_DCICC_ADDR(x))
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#define HW_DCIC_DCICC_RD(x) (HW_DCIC_DCICC(x).U)
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#define HW_DCIC_DCICC_WR(x, v) (HW_DCIC_DCICC(x).U = (v))
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#define HW_DCIC_DCICC_SET(x, v) (HW_DCIC_DCICC_WR(x, HW_DCIC_DCICC_RD(x) | (v)))
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#define HW_DCIC_DCICC_CLR(x, v) (HW_DCIC_DCICC_WR(x, HW_DCIC_DCICC_RD(x) & ~(v)))
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#define HW_DCIC_DCICC_TOG(x, v) (HW_DCIC_DCICC_WR(x, HW_DCIC_DCICC_RD(x) ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual DCIC_DCICC bitfields
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*/
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/*! @name Register DCIC_DCICC, field IC_EN[0] (RW)
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*
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* Integrity Check enable. Main enable switch.
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*
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* Values:
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* - 0 - Disabled
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* - 1 - Enabled
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*/
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//@{
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#define BP_DCIC_DCICC_IC_EN (0) //!< Bit position for DCIC_DCICC_IC_EN.
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#define BM_DCIC_DCICC_IC_EN (0x00000001) //!< Bit mask for DCIC_DCICC_IC_EN.
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//! @brief Get value of DCIC_DCICC_IC_EN from a register value.
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#define BG_DCIC_DCICC_IC_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICC_IC_EN) >> BP_DCIC_DCICC_IC_EN)
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//! @brief Format value for bitfield DCIC_DCICC_IC_EN.
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#define BF_DCIC_DCICC_IC_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICC_IC_EN) & BM_DCIC_DCICC_IC_EN)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the IC_EN field to a new value.
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#define BW_DCIC_DCICC_IC_EN(x, v) (HW_DCIC_DCICC_WR(x, (HW_DCIC_DCICC_RD(x) & ~BM_DCIC_DCICC_IC_EN) | BF_DCIC_DCICC_IC_EN(v)))
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#endif
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//@}
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/*! @name Register DCIC_DCICC, field DE_POL[4] (RW)
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*
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* DATA_EN_IN signal polarity.
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*
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* Values:
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* - 0 - Active High.
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* - 1 - Active Low (default).
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*/
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//@{
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#define BP_DCIC_DCICC_DE_POL (4) //!< Bit position for DCIC_DCICC_DE_POL.
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#define BM_DCIC_DCICC_DE_POL (0x00000010) //!< Bit mask for DCIC_DCICC_DE_POL.
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//! @brief Get value of DCIC_DCICC_DE_POL from a register value.
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#define BG_DCIC_DCICC_DE_POL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICC_DE_POL) >> BP_DCIC_DCICC_DE_POL)
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//! @brief Format value for bitfield DCIC_DCICC_DE_POL.
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#define BF_DCIC_DCICC_DE_POL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICC_DE_POL) & BM_DCIC_DCICC_DE_POL)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the DE_POL field to a new value.
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#define BW_DCIC_DCICC_DE_POL(x, v) (HW_DCIC_DCICC_WR(x, (HW_DCIC_DCICC_RD(x) & ~BM_DCIC_DCICC_DE_POL) | BF_DCIC_DCICC_DE_POL(v)))
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#endif
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//@}
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/*! @name Register DCIC_DCICC, field HSYNC_POL[5] (RW)
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*
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* HSYNC_IN signal polarity.
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*
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* Values:
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* - 0 - Active High.
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* - 1 - Active Low (default).
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*/
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//@{
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#define BP_DCIC_DCICC_HSYNC_POL (5) //!< Bit position for DCIC_DCICC_HSYNC_POL.
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#define BM_DCIC_DCICC_HSYNC_POL (0x00000020) //!< Bit mask for DCIC_DCICC_HSYNC_POL.
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//! @brief Get value of DCIC_DCICC_HSYNC_POL from a register value.
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#define BG_DCIC_DCICC_HSYNC_POL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICC_HSYNC_POL) >> BP_DCIC_DCICC_HSYNC_POL)
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//! @brief Format value for bitfield DCIC_DCICC_HSYNC_POL.
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#define BF_DCIC_DCICC_HSYNC_POL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICC_HSYNC_POL) & BM_DCIC_DCICC_HSYNC_POL)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the HSYNC_POL field to a new value.
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#define BW_DCIC_DCICC_HSYNC_POL(x, v) (HW_DCIC_DCICC_WR(x, (HW_DCIC_DCICC_RD(x) & ~BM_DCIC_DCICC_HSYNC_POL) | BF_DCIC_DCICC_HSYNC_POL(v)))
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#endif
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//@}
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/*! @name Register DCIC_DCICC, field VSYNC_POL[6] (RW)
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*
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* VSYNC_IN signal polarity.
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*
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* Values:
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* - 0 - Active High.
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* - 1 - Active Low (default).
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*/
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//@{
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#define BP_DCIC_DCICC_VSYNC_POL (6) //!< Bit position for DCIC_DCICC_VSYNC_POL.
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#define BM_DCIC_DCICC_VSYNC_POL (0x00000040) //!< Bit mask for DCIC_DCICC_VSYNC_POL.
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//! @brief Get value of DCIC_DCICC_VSYNC_POL from a register value.
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#define BG_DCIC_DCICC_VSYNC_POL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICC_VSYNC_POL) >> BP_DCIC_DCICC_VSYNC_POL)
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//! @brief Format value for bitfield DCIC_DCICC_VSYNC_POL.
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#define BF_DCIC_DCICC_VSYNC_POL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICC_VSYNC_POL) & BM_DCIC_DCICC_VSYNC_POL)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the VSYNC_POL field to a new value.
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#define BW_DCIC_DCICC_VSYNC_POL(x, v) (HW_DCIC_DCICC_WR(x, (HW_DCIC_DCICC_RD(x) & ~BM_DCIC_DCICC_VSYNC_POL) | BF_DCIC_DCICC_VSYNC_POL(v)))
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#endif
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//@}
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/*! @name Register DCIC_DCICC, field CLK_POL[7] (RW)
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*
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* DISP_CLK signal polarity.
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*
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* Values:
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* - 0 - Not inverted (default).
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* - 1 - Inverted.
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*/
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//@{
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#define BP_DCIC_DCICC_CLK_POL (7) //!< Bit position for DCIC_DCICC_CLK_POL.
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#define BM_DCIC_DCICC_CLK_POL (0x00000080) //!< Bit mask for DCIC_DCICC_CLK_POL.
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//! @brief Get value of DCIC_DCICC_CLK_POL from a register value.
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#define BG_DCIC_DCICC_CLK_POL(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICC_CLK_POL) >> BP_DCIC_DCICC_CLK_POL)
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//! @brief Format value for bitfield DCIC_DCICC_CLK_POL.
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#define BF_DCIC_DCICC_CLK_POL(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICC_CLK_POL) & BM_DCIC_DCICC_CLK_POL)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the CLK_POL field to a new value.
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#define BW_DCIC_DCICC_CLK_POL(x, v) (HW_DCIC_DCICC_WR(x, (HW_DCIC_DCICC_RD(x) & ~BM_DCIC_DCICC_CLK_POL) | BF_DCIC_DCICC_CLK_POL(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_DCIC_DCICIC - DCIC Interrupt Control Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_DCIC_DCICIC - DCIC Interrupt Control Register (RW)
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*
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* Reset value: 0x00000003
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*/
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typedef union _hw_dcic_dcicic
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{
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reg32_t U;
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struct _hw_dcic_dcicic_bitfields
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{
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unsigned EI_MASK : 1; //!< [0] Error Interrupt mask.
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unsigned FI_MASK : 1; //!< [1] Functional Interrupt mask.
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unsigned RESERVED0 : 1; //!< [2] Reserved
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unsigned FREEZE_MASK : 1; //!< [3] Disable change of interrupt masks.
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unsigned RESERVED1 : 12; //!< [15:4] Reserved
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unsigned EXT_SIG_EN : 1; //!< [16] External controller mismatch indication signal.
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unsigned RESERVED2 : 15; //!< [31:17] Reserved
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} B;
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} hw_dcic_dcicic_t;
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#endif
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/*!
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* @name Constants and macros for entire DCIC_DCICIC register
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*/
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//@{
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#define HW_DCIC_DCICIC_ADDR(x) (REGS_DCIC_BASE(x) + 0x4)
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#ifndef __LANGUAGE_ASM__
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#define HW_DCIC_DCICIC(x) (*(volatile hw_dcic_dcicic_t *) HW_DCIC_DCICIC_ADDR(x))
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#define HW_DCIC_DCICIC_RD(x) (HW_DCIC_DCICIC(x).U)
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#define HW_DCIC_DCICIC_WR(x, v) (HW_DCIC_DCICIC(x).U = (v))
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#define HW_DCIC_DCICIC_SET(x, v) (HW_DCIC_DCICIC_WR(x, HW_DCIC_DCICIC_RD(x) | (v)))
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#define HW_DCIC_DCICIC_CLR(x, v) (HW_DCIC_DCICIC_WR(x, HW_DCIC_DCICIC_RD(x) & ~(v)))
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#define HW_DCIC_DCICIC_TOG(x, v) (HW_DCIC_DCICIC_WR(x, HW_DCIC_DCICIC_RD(x) ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual DCIC_DCICIC bitfields
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*/
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/*! @name Register DCIC_DCICIC, field EI_MASK[0] (RW)
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*
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* Error Interrupt mask. Can be changed only while FREEZE_MASK = 0.
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*
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* Values:
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* - 0 - Mask disabled - Interrupt assertion enabled
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* - 1 - Mask enabled - Interrupt assertion disabled (default)
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*/
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//@{
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#define BP_DCIC_DCICIC_EI_MASK (0) //!< Bit position for DCIC_DCICIC_EI_MASK.
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#define BM_DCIC_DCICIC_EI_MASK (0x00000001) //!< Bit mask for DCIC_DCICIC_EI_MASK.
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//! @brief Get value of DCIC_DCICIC_EI_MASK from a register value.
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#define BG_DCIC_DCICIC_EI_MASK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICIC_EI_MASK) >> BP_DCIC_DCICIC_EI_MASK)
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//! @brief Format value for bitfield DCIC_DCICIC_EI_MASK.
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#define BF_DCIC_DCICIC_EI_MASK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICIC_EI_MASK) & BM_DCIC_DCICIC_EI_MASK)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the EI_MASK field to a new value.
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#define BW_DCIC_DCICIC_EI_MASK(x, v) (HW_DCIC_DCICIC_WR(x, (HW_DCIC_DCICIC_RD(x) & ~BM_DCIC_DCICIC_EI_MASK) | BF_DCIC_DCICIC_EI_MASK(v)))
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#endif
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//@}
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/*! @name Register DCIC_DCICIC, field FI_MASK[1] (RW)
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*
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* Functional Interrupt mask. Can be changed only while FREEZE_MASK = 0.
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*
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* Values:
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* - 0 - Mask disabled - Interrupt assertion enabled
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* - 1 - Mask enabled - Interrupt assertion disabled (default)
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*/
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//@{
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#define BP_DCIC_DCICIC_FI_MASK (1) //!< Bit position for DCIC_DCICIC_FI_MASK.
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#define BM_DCIC_DCICIC_FI_MASK (0x00000002) //!< Bit mask for DCIC_DCICIC_FI_MASK.
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//! @brief Get value of DCIC_DCICIC_FI_MASK from a register value.
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#define BG_DCIC_DCICIC_FI_MASK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICIC_FI_MASK) >> BP_DCIC_DCICIC_FI_MASK)
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//! @brief Format value for bitfield DCIC_DCICIC_FI_MASK.
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#define BF_DCIC_DCICIC_FI_MASK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICIC_FI_MASK) & BM_DCIC_DCICIC_FI_MASK)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the FI_MASK field to a new value.
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#define BW_DCIC_DCICIC_FI_MASK(x, v) (HW_DCIC_DCICIC_WR(x, (HW_DCIC_DCICIC_RD(x) & ~BM_DCIC_DCICIC_FI_MASK) | BF_DCIC_DCICIC_FI_MASK(v)))
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#endif
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//@}
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/*! @name Register DCIC_DCICIC, field FREEZE_MASK[3] (RW)
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*
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* Disable change of interrupt masks. "Sticky" bit which can be set once and cleared by reset only.
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*
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* Values:
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* - 0 - Masks change allowed (default)
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* - 1 - Masks are frozen
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*/
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//@{
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#define BP_DCIC_DCICIC_FREEZE_MASK (3) //!< Bit position for DCIC_DCICIC_FREEZE_MASK.
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#define BM_DCIC_DCICIC_FREEZE_MASK (0x00000008) //!< Bit mask for DCIC_DCICIC_FREEZE_MASK.
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//! @brief Get value of DCIC_DCICIC_FREEZE_MASK from a register value.
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#define BG_DCIC_DCICIC_FREEZE_MASK(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICIC_FREEZE_MASK) >> BP_DCIC_DCICIC_FREEZE_MASK)
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//! @brief Format value for bitfield DCIC_DCICIC_FREEZE_MASK.
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#define BF_DCIC_DCICIC_FREEZE_MASK(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICIC_FREEZE_MASK) & BM_DCIC_DCICIC_FREEZE_MASK)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the FREEZE_MASK field to a new value.
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#define BW_DCIC_DCICIC_FREEZE_MASK(x, v) (HW_DCIC_DCICIC_WR(x, (HW_DCIC_DCICIC_RD(x) & ~BM_DCIC_DCICIC_FREEZE_MASK) | BF_DCIC_DCICIC_FREEZE_MASK(v)))
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#endif
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//@}
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/*! @name Register DCIC_DCICIC, field EXT_SIG_EN[16] (RW)
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*
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* External controller mismatch indication signal.
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*
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* Values:
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* - 0 - Disabled (default)
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* - 1 - Enabled
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*/
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//@{
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#define BP_DCIC_DCICIC_EXT_SIG_EN (16) //!< Bit position for DCIC_DCICIC_EXT_SIG_EN.
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#define BM_DCIC_DCICIC_EXT_SIG_EN (0x00010000) //!< Bit mask for DCIC_DCICIC_EXT_SIG_EN.
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//! @brief Get value of DCIC_DCICIC_EXT_SIG_EN from a register value.
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#define BG_DCIC_DCICIC_EXT_SIG_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICIC_EXT_SIG_EN) >> BP_DCIC_DCICIC_EXT_SIG_EN)
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//! @brief Format value for bitfield DCIC_DCICIC_EXT_SIG_EN.
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#define BF_DCIC_DCICIC_EXT_SIG_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICIC_EXT_SIG_EN) & BM_DCIC_DCICIC_EXT_SIG_EN)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the EXT_SIG_EN field to a new value.
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#define BW_DCIC_DCICIC_EXT_SIG_EN(x, v) (HW_DCIC_DCICIC_WR(x, (HW_DCIC_DCICIC_RD(x) & ~BM_DCIC_DCICIC_EXT_SIG_EN) | BF_DCIC_DCICIC_EXT_SIG_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_DCIC_DCICS - DCIC Status Register
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_DCIC_DCICS - DCIC Status Register (W1C)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_dcic_dcics
|
|
{
|
|
reg32_t U;
|
|
struct _hw_dcic_dcics_bitfields
|
|
{
|
|
unsigned ROI_MATCH_STAT : 16; //!< [15:0] Each set bit of this field indicates there was a mismatch at appropriate ROIs signature during the last frame.
|
|
unsigned EI_STAT : 1; //!< [16] Error Interrupt status.
|
|
unsigned FI_STAT : 1; //!< [17] Functional Interrupt status.
|
|
unsigned RESERVED0 : 14; //!< [31:18] Reserved
|
|
} B;
|
|
} hw_dcic_dcics_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire DCIC_DCICS register
|
|
*/
|
|
//@{
|
|
#define HW_DCIC_DCICS_ADDR(x) (REGS_DCIC_BASE(x) + 0x8)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_DCIC_DCICS(x) (*(volatile hw_dcic_dcics_t *) HW_DCIC_DCICS_ADDR(x))
|
|
#define HW_DCIC_DCICS_RD(x) (HW_DCIC_DCICS(x).U)
|
|
#define HW_DCIC_DCICS_WR(x, v) (HW_DCIC_DCICS(x).U = (v))
|
|
#define HW_DCIC_DCICS_SET(x, v) (HW_DCIC_DCICS_WR(x, HW_DCIC_DCICS_RD(x) | (v)))
|
|
#define HW_DCIC_DCICS_CLR(x, v) (HW_DCIC_DCICS_WR(x, HW_DCIC_DCICS_RD(x) & ~(v)))
|
|
#define HW_DCIC_DCICS_TOG(x, v) (HW_DCIC_DCICS_WR(x, HW_DCIC_DCICS_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual DCIC_DCICS bitfields
|
|
*/
|
|
|
|
/*! @name Register DCIC_DCICS, field ROI_MATCH_STAT[15:0] (W1C)
|
|
*
|
|
* Each set bit of this field indicates there was a mismatch at appropriate ROIs signature during
|
|
* the last frame. Valid only for active ROIs. Write "1" to clear.
|
|
*
|
|
* Values:
|
|
* - 0 - ROI calculated CRC matches expected signature
|
|
* - 1 - Mismatch at ROI calculated CRC
|
|
*/
|
|
//@{
|
|
#define BP_DCIC_DCICS_ROI_MATCH_STAT (0) //!< Bit position for DCIC_DCICS_ROI_MATCH_STAT.
|
|
#define BM_DCIC_DCICS_ROI_MATCH_STAT (0x0000ffff) //!< Bit mask for DCIC_DCICS_ROI_MATCH_STAT.
|
|
|
|
//! @brief Get value of DCIC_DCICS_ROI_MATCH_STAT from a register value.
|
|
#define BG_DCIC_DCICS_ROI_MATCH_STAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICS_ROI_MATCH_STAT) >> BP_DCIC_DCICS_ROI_MATCH_STAT)
|
|
|
|
//! @brief Format value for bitfield DCIC_DCICS_ROI_MATCH_STAT.
|
|
#define BF_DCIC_DCICS_ROI_MATCH_STAT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICS_ROI_MATCH_STAT) & BM_DCIC_DCICS_ROI_MATCH_STAT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ROI_MATCH_STAT field to a new value.
|
|
#define BW_DCIC_DCICS_ROI_MATCH_STAT(x, v) (HW_DCIC_DCICS_WR(x, (HW_DCIC_DCICS_RD(x) & ~BM_DCIC_DCICS_ROI_MATCH_STAT) | BF_DCIC_DCICS_ROI_MATCH_STAT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register DCIC_DCICS, field EI_STAT[16] (RO)
|
|
*
|
|
* Error Interrupt status. Result of "OR" operation on ROI_MATCH_STAT[15:0] bits. Cleared when these
|
|
* bits are clear.
|
|
*
|
|
* Values:
|
|
* - 0 - No pending Interrupt
|
|
* - 1 - Pending Interrupt
|
|
*/
|
|
//@{
|
|
#define BP_DCIC_DCICS_EI_STAT (16) //!< Bit position for DCIC_DCICS_EI_STAT.
|
|
#define BM_DCIC_DCICS_EI_STAT (0x00010000) //!< Bit mask for DCIC_DCICS_EI_STAT.
|
|
|
|
//! @brief Get value of DCIC_DCICS_EI_STAT from a register value.
|
|
#define BG_DCIC_DCICS_EI_STAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICS_EI_STAT) >> BP_DCIC_DCICS_EI_STAT)
|
|
//@}
|
|
|
|
/*! @name Register DCIC_DCICS, field FI_STAT[17] (W1C)
|
|
*
|
|
* Functional Interrupt status. Write "1" to clear.
|
|
*
|
|
* Values:
|
|
* - 0 - No pending Interrupt
|
|
* - 1 - Pending Interrupt
|
|
*/
|
|
//@{
|
|
#define BP_DCIC_DCICS_FI_STAT (17) //!< Bit position for DCIC_DCICS_FI_STAT.
|
|
#define BM_DCIC_DCICS_FI_STAT (0x00020000) //!< Bit mask for DCIC_DCICS_FI_STAT.
|
|
|
|
//! @brief Get value of DCIC_DCICS_FI_STAT from a register value.
|
|
#define BG_DCIC_DCICS_FI_STAT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICS_FI_STAT) >> BP_DCIC_DCICS_FI_STAT)
|
|
|
|
//! @brief Format value for bitfield DCIC_DCICS_FI_STAT.
|
|
#define BF_DCIC_DCICS_FI_STAT(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICS_FI_STAT) & BM_DCIC_DCICS_FI_STAT)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the FI_STAT field to a new value.
|
|
#define BW_DCIC_DCICS_FI_STAT(x, v) (HW_DCIC_DCICS_WR(x, (HW_DCIC_DCICS_RD(x) & ~BM_DCIC_DCICS_FI_STAT) | BF_DCIC_DCICS_FI_STAT(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_DCIC_DCICRC - DCIC ROI Config Register m
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_DCIC_DCICRC - DCIC ROI Config Register m (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_dcic_dcicrc
|
|
{
|
|
reg32_t U;
|
|
struct _hw_dcic_dcicrc_bitfields
|
|
{
|
|
unsigned START_OFFSET_X : 13; //!< [12:0] Column number of ROIs upper-left corner (X coordinate)
|
|
unsigned RESERVED0 : 3; //!< [15:13] Reserved
|
|
unsigned START_OFFSET_Y : 12; //!< [27:16] Row number of ROIs upper-left corner (Y coordinate)
|
|
unsigned RESERVED1 : 2; //!< [29:28] Reserved
|
|
unsigned ROI_FREEZE : 1; //!< [30] When set, the only parameter of ROI #m that can be changed is reference signature.
|
|
unsigned ROI_EN : 1; //!< [31] ROI #m tracking enable
|
|
} B;
|
|
} hw_dcic_dcicrc_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire DCIC_DCICRC register
|
|
*/
|
|
//@{
|
|
#define HW_DCIC_DCICRC_ADDR(x) (REGS_DCIC_BASE(x) + 0x10)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_DCIC_DCICRC(x) (*(volatile hw_dcic_dcicrc_t *) HW_DCIC_DCICRC_ADDR(x))
|
|
#define HW_DCIC_DCICRC_RD(x) (HW_DCIC_DCICRC(x).U)
|
|
#define HW_DCIC_DCICRC_WR(x, v) (HW_DCIC_DCICRC(x).U = (v))
|
|
#define HW_DCIC_DCICRC_SET(x, v) (HW_DCIC_DCICRC_WR(x, HW_DCIC_DCICRC_RD(x) | (v)))
|
|
#define HW_DCIC_DCICRC_CLR(x, v) (HW_DCIC_DCICRC_WR(x, HW_DCIC_DCICRC_RD(x) & ~(v)))
|
|
#define HW_DCIC_DCICRC_TOG(x, v) (HW_DCIC_DCICRC_WR(x, HW_DCIC_DCICRC_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual DCIC_DCICRC bitfields
|
|
*/
|
|
|
|
/*! @name Register DCIC_DCICRC, field START_OFFSET_X[12:0] (RW)
|
|
*
|
|
* Column number of ROIs upper-left corner (X coordinate) Range: 0 to 2^ 13 -1
|
|
*/
|
|
//@{
|
|
#define BP_DCIC_DCICRC_START_OFFSET_X (0) //!< Bit position for DCIC_DCICRC_START_OFFSET_X.
|
|
#define BM_DCIC_DCICRC_START_OFFSET_X (0x00001fff) //!< Bit mask for DCIC_DCICRC_START_OFFSET_X.
|
|
|
|
//! @brief Get value of DCIC_DCICRC_START_OFFSET_X from a register value.
|
|
#define BG_DCIC_DCICRC_START_OFFSET_X(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICRC_START_OFFSET_X) >> BP_DCIC_DCICRC_START_OFFSET_X)
|
|
|
|
//! @brief Format value for bitfield DCIC_DCICRC_START_OFFSET_X.
|
|
#define BF_DCIC_DCICRC_START_OFFSET_X(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICRC_START_OFFSET_X) & BM_DCIC_DCICRC_START_OFFSET_X)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the START_OFFSET_X field to a new value.
|
|
#define BW_DCIC_DCICRC_START_OFFSET_X(x, v) (HW_DCIC_DCICRC_WR(x, (HW_DCIC_DCICRC_RD(x) & ~BM_DCIC_DCICRC_START_OFFSET_X) | BF_DCIC_DCICRC_START_OFFSET_X(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register DCIC_DCICRC, field START_OFFSET_Y[27:16] (RW)
|
|
*
|
|
* Row number of ROIs upper-left corner (Y coordinate) Range: 0 to 2^ 12 -1
|
|
*/
|
|
//@{
|
|
#define BP_DCIC_DCICRC_START_OFFSET_Y (16) //!< Bit position for DCIC_DCICRC_START_OFFSET_Y.
|
|
#define BM_DCIC_DCICRC_START_OFFSET_Y (0x0fff0000) //!< Bit mask for DCIC_DCICRC_START_OFFSET_Y.
|
|
|
|
//! @brief Get value of DCIC_DCICRC_START_OFFSET_Y from a register value.
|
|
#define BG_DCIC_DCICRC_START_OFFSET_Y(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICRC_START_OFFSET_Y) >> BP_DCIC_DCICRC_START_OFFSET_Y)
|
|
|
|
//! @brief Format value for bitfield DCIC_DCICRC_START_OFFSET_Y.
|
|
#define BF_DCIC_DCICRC_START_OFFSET_Y(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICRC_START_OFFSET_Y) & BM_DCIC_DCICRC_START_OFFSET_Y)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the START_OFFSET_Y field to a new value.
|
|
#define BW_DCIC_DCICRC_START_OFFSET_Y(x, v) (HW_DCIC_DCICRC_WR(x, (HW_DCIC_DCICRC_RD(x) & ~BM_DCIC_DCICRC_START_OFFSET_Y) | BF_DCIC_DCICRC_START_OFFSET_Y(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register DCIC_DCICRC, field ROI_FREEZE[30] (RW)
|
|
*
|
|
* When set, the only parameter of ROI #m that can be changed is reference signature. "Sticky" bit -
|
|
* can be set once and cleared by reset only.
|
|
*
|
|
* Values:
|
|
* - 0 - ROI configuration can be changed
|
|
* - 1 - ROI configuration is frozen
|
|
*/
|
|
//@{
|
|
#define BP_DCIC_DCICRC_ROI_FREEZE (30) //!< Bit position for DCIC_DCICRC_ROI_FREEZE.
|
|
#define BM_DCIC_DCICRC_ROI_FREEZE (0x40000000) //!< Bit mask for DCIC_DCICRC_ROI_FREEZE.
|
|
|
|
//! @brief Get value of DCIC_DCICRC_ROI_FREEZE from a register value.
|
|
#define BG_DCIC_DCICRC_ROI_FREEZE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICRC_ROI_FREEZE) >> BP_DCIC_DCICRC_ROI_FREEZE)
|
|
|
|
//! @brief Format value for bitfield DCIC_DCICRC_ROI_FREEZE.
|
|
#define BF_DCIC_DCICRC_ROI_FREEZE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICRC_ROI_FREEZE) & BM_DCIC_DCICRC_ROI_FREEZE)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ROI_FREEZE field to a new value.
|
|
#define BW_DCIC_DCICRC_ROI_FREEZE(x, v) (HW_DCIC_DCICRC_WR(x, (HW_DCIC_DCICRC_RD(x) & ~BM_DCIC_DCICRC_ROI_FREEZE) | BF_DCIC_DCICRC_ROI_FREEZE(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register DCIC_DCICRC, field ROI_EN[31] (RW)
|
|
*
|
|
* ROI #m tracking enable
|
|
*
|
|
* Values:
|
|
* - 0 - Disabled
|
|
* - 1 - Enabled
|
|
*/
|
|
//@{
|
|
#define BP_DCIC_DCICRC_ROI_EN (31) //!< Bit position for DCIC_DCICRC_ROI_EN.
|
|
#define BM_DCIC_DCICRC_ROI_EN (0x80000000) //!< Bit mask for DCIC_DCICRC_ROI_EN.
|
|
|
|
//! @brief Get value of DCIC_DCICRC_ROI_EN from a register value.
|
|
#define BG_DCIC_DCICRC_ROI_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICRC_ROI_EN) >> BP_DCIC_DCICRC_ROI_EN)
|
|
|
|
//! @brief Format value for bitfield DCIC_DCICRC_ROI_EN.
|
|
#define BF_DCIC_DCICRC_ROI_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICRC_ROI_EN) & BM_DCIC_DCICRC_ROI_EN)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the ROI_EN field to a new value.
|
|
#define BW_DCIC_DCICRC_ROI_EN(x, v) (HW_DCIC_DCICRC_WR(x, (HW_DCIC_DCICRC_RD(x) & ~BM_DCIC_DCICRC_ROI_EN) | BF_DCIC_DCICRC_ROI_EN(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_DCIC_DCICRS - DCIC ROI Size Register m
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_DCIC_DCICRS - DCIC ROI Size Register m (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_dcic_dcicrs
|
|
{
|
|
reg32_t U;
|
|
struct _hw_dcic_dcicrs_bitfields
|
|
{
|
|
unsigned END_OFFSET_X : 13; //!< [12:0] Column number of ROIs lower-right corner (X coordinate)
|
|
unsigned RESERVED0 : 3; //!< [15:13] Reserved
|
|
unsigned END_OFFSET_Y : 12; //!< [27:16] Row number of ROIs lower-right corner (Y coordinate)
|
|
unsigned RESERVED1 : 4; //!< [31:28] Reserved
|
|
} B;
|
|
} hw_dcic_dcicrs_t;
|
|
#endif
|
|
|
|
/*!
|
|
* @name Constants and macros for entire DCIC_DCICRS register
|
|
*/
|
|
//@{
|
|
#define HW_DCIC_DCICRS_ADDR(x) (REGS_DCIC_BASE(x) + 0x14)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
#define HW_DCIC_DCICRS(x) (*(volatile hw_dcic_dcicrs_t *) HW_DCIC_DCICRS_ADDR(x))
|
|
#define HW_DCIC_DCICRS_RD(x) (HW_DCIC_DCICRS(x).U)
|
|
#define HW_DCIC_DCICRS_WR(x, v) (HW_DCIC_DCICRS(x).U = (v))
|
|
#define HW_DCIC_DCICRS_SET(x, v) (HW_DCIC_DCICRS_WR(x, HW_DCIC_DCICRS_RD(x) | (v)))
|
|
#define HW_DCIC_DCICRS_CLR(x, v) (HW_DCIC_DCICRS_WR(x, HW_DCIC_DCICRS_RD(x) & ~(v)))
|
|
#define HW_DCIC_DCICRS_TOG(x, v) (HW_DCIC_DCICRS_WR(x, HW_DCIC_DCICRS_RD(x) ^ (v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*
|
|
* constants & macros for individual DCIC_DCICRS bitfields
|
|
*/
|
|
|
|
/*! @name Register DCIC_DCICRS, field END_OFFSET_X[12:0] (RW)
|
|
*
|
|
* Column number of ROIs lower-right corner (X coordinate) Range: 1 to 2^ 13 -1
|
|
*/
|
|
//@{
|
|
#define BP_DCIC_DCICRS_END_OFFSET_X (0) //!< Bit position for DCIC_DCICRS_END_OFFSET_X.
|
|
#define BM_DCIC_DCICRS_END_OFFSET_X (0x00001fff) //!< Bit mask for DCIC_DCICRS_END_OFFSET_X.
|
|
|
|
//! @brief Get value of DCIC_DCICRS_END_OFFSET_X from a register value.
|
|
#define BG_DCIC_DCICRS_END_OFFSET_X(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICRS_END_OFFSET_X) >> BP_DCIC_DCICRS_END_OFFSET_X)
|
|
|
|
//! @brief Format value for bitfield DCIC_DCICRS_END_OFFSET_X.
|
|
#define BF_DCIC_DCICRS_END_OFFSET_X(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICRS_END_OFFSET_X) & BM_DCIC_DCICRS_END_OFFSET_X)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the END_OFFSET_X field to a new value.
|
|
#define BW_DCIC_DCICRS_END_OFFSET_X(x, v) (HW_DCIC_DCICRS_WR(x, (HW_DCIC_DCICRS_RD(x) & ~BM_DCIC_DCICRS_END_OFFSET_X) | BF_DCIC_DCICRS_END_OFFSET_X(v)))
|
|
#endif
|
|
//@}
|
|
|
|
/*! @name Register DCIC_DCICRS, field END_OFFSET_Y[27:16] (RW)
|
|
*
|
|
* Row number of ROIs lower-right corner (Y coordinate) Range: 1 to 2^ 12 -1
|
|
*/
|
|
//@{
|
|
#define BP_DCIC_DCICRS_END_OFFSET_Y (16) //!< Bit position for DCIC_DCICRS_END_OFFSET_Y.
|
|
#define BM_DCIC_DCICRS_END_OFFSET_Y (0x0fff0000) //!< Bit mask for DCIC_DCICRS_END_OFFSET_Y.
|
|
|
|
//! @brief Get value of DCIC_DCICRS_END_OFFSET_Y from a register value.
|
|
#define BG_DCIC_DCICRS_END_OFFSET_Y(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICRS_END_OFFSET_Y) >> BP_DCIC_DCICRS_END_OFFSET_Y)
|
|
|
|
//! @brief Format value for bitfield DCIC_DCICRS_END_OFFSET_Y.
|
|
#define BF_DCIC_DCICRS_END_OFFSET_Y(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICRS_END_OFFSET_Y) & BM_DCIC_DCICRS_END_OFFSET_Y)
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
//! @brief Set the END_OFFSET_Y field to a new value.
|
|
#define BW_DCIC_DCICRS_END_OFFSET_Y(x, v) (HW_DCIC_DCICRS_WR(x, (HW_DCIC_DCICRS_RD(x) & ~BM_DCIC_DCICRS_END_OFFSET_Y) | BF_DCIC_DCICRS_END_OFFSET_Y(v)))
|
|
#endif
|
|
//@}
|
|
|
|
//-------------------------------------------------------------------------------------------
|
|
// HW_DCIC_DCICRRS - DCIC ROI Reference Signature Register m
|
|
//-------------------------------------------------------------------------------------------
|
|
|
|
#ifndef __LANGUAGE_ASM__
|
|
/*!
|
|
* @brief HW_DCIC_DCICRRS - DCIC ROI Reference Signature Register m (RW)
|
|
*
|
|
* Reset value: 0x00000000
|
|
*/
|
|
typedef union _hw_dcic_dcicrrs
|
|
{
|
|
reg32_t U;
|
|
struct _hw_dcic_dcicrrs_bitfields
|
|
{
|
|
unsigned REFERENCE_SIGNATURE : 32; //!< [31:0] 32-bit expected signature (CRC calculation result) for ROI #m
|
|
} B;
|
|
} hw_dcic_dcicrrs_t;
|
|
#endif
|
|
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/*!
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* @name Constants and macros for entire DCIC_DCICRRS register
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*/
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//@{
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#define HW_DCIC_DCICRRS_ADDR(x) (REGS_DCIC_BASE(x) + 0x18)
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#ifndef __LANGUAGE_ASM__
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#define HW_DCIC_DCICRRS(x) (*(volatile hw_dcic_dcicrrs_t *) HW_DCIC_DCICRRS_ADDR(x))
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#define HW_DCIC_DCICRRS_RD(x) (HW_DCIC_DCICRRS(x).U)
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#define HW_DCIC_DCICRRS_WR(x, v) (HW_DCIC_DCICRRS(x).U = (v))
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#define HW_DCIC_DCICRRS_SET(x, v) (HW_DCIC_DCICRRS_WR(x, HW_DCIC_DCICRRS_RD(x) | (v)))
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#define HW_DCIC_DCICRRS_CLR(x, v) (HW_DCIC_DCICRRS_WR(x, HW_DCIC_DCICRRS_RD(x) & ~(v)))
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#define HW_DCIC_DCICRRS_TOG(x, v) (HW_DCIC_DCICRRS_WR(x, HW_DCIC_DCICRRS_RD(x) ^ (v)))
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#endif
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//@}
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/*
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* constants & macros for individual DCIC_DCICRRS bitfields
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*/
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/*! @name Register DCIC_DCICRRS, field REFERENCE_SIGNATURE[31:0] (RW)
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*
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* 32-bit expected signature (CRC calculation result) for ROI #m
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*/
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//@{
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#define BP_DCIC_DCICRRS_REFERENCE_SIGNATURE (0) //!< Bit position for DCIC_DCICRRS_REFERENCE_SIGNATURE.
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#define BM_DCIC_DCICRRS_REFERENCE_SIGNATURE (0xffffffff) //!< Bit mask for DCIC_DCICRRS_REFERENCE_SIGNATURE.
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//! @brief Get value of DCIC_DCICRRS_REFERENCE_SIGNATURE from a register value.
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#define BG_DCIC_DCICRRS_REFERENCE_SIGNATURE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICRRS_REFERENCE_SIGNATURE) >> BP_DCIC_DCICRRS_REFERENCE_SIGNATURE)
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//! @brief Format value for bitfield DCIC_DCICRRS_REFERENCE_SIGNATURE.
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#define BF_DCIC_DCICRRS_REFERENCE_SIGNATURE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_DCIC_DCICRRS_REFERENCE_SIGNATURE) & BM_DCIC_DCICRRS_REFERENCE_SIGNATURE)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the REFERENCE_SIGNATURE field to a new value.
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#define BW_DCIC_DCICRRS_REFERENCE_SIGNATURE(x, v) (HW_DCIC_DCICRRS_WR(x, (HW_DCIC_DCICRRS_RD(x) & ~BM_DCIC_DCICRRS_REFERENCE_SIGNATURE) | BF_DCIC_DCICRRS_REFERENCE_SIGNATURE(v)))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_DCIC_DCICRCS - DCIC ROI Calculated Signature m
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_DCIC_DCICRCS - DCIC ROI Calculated Signature m (RO)
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*
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* Reset value: 0x00000000
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*/
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typedef union _hw_dcic_dcicrcs
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{
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reg32_t U;
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struct _hw_dcic_dcicrcs_bitfields
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{
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unsigned CALCULATED_SIGNATURE : 32; //!< [31:0] 32-bit actual signature (CRC calculation result) for ROI #m during the last frame.
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} B;
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} hw_dcic_dcicrcs_t;
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#endif
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/*!
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* @name Constants and macros for entire DCIC_DCICRCS register
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*/
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//@{
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#define HW_DCIC_DCICRCS_ADDR(x) (REGS_DCIC_BASE(x) + 0x1c)
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#ifndef __LANGUAGE_ASM__
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#define HW_DCIC_DCICRCS(x) (*(volatile hw_dcic_dcicrcs_t *) HW_DCIC_DCICRCS_ADDR(x))
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#define HW_DCIC_DCICRCS_RD(x) (HW_DCIC_DCICRCS(x).U)
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#endif
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//@}
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/*
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* constants & macros for individual DCIC_DCICRCS bitfields
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*/
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/*! @name Register DCIC_DCICRCS, field CALCULATED_SIGNATURE[31:0] (RO)
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*
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* 32-bit actual signature (CRC calculation result) for ROI #m during the last frame. Updated
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* automatically at the beginning of a next frame.
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*/
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//@{
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#define BP_DCIC_DCICRCS_CALCULATED_SIGNATURE (0) //!< Bit position for DCIC_DCICRCS_CALCULATED_SIGNATURE.
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#define BM_DCIC_DCICRCS_CALCULATED_SIGNATURE (0xffffffff) //!< Bit mask for DCIC_DCICRCS_CALCULATED_SIGNATURE.
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//! @brief Get value of DCIC_DCICRCS_CALCULATED_SIGNATURE from a register value.
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#define BG_DCIC_DCICRCS_CALCULATED_SIGNATURE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_DCIC_DCICRCS_CALCULATED_SIGNATURE) >> BP_DCIC_DCICRCS_CALCULATED_SIGNATURE)
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//@}
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//-------------------------------------------------------------------------------------------
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// hw_dcic_t - module struct
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//-------------------------------------------------------------------------------------------
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/*!
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* @brief All DCIC module registers.
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*/
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#ifndef __LANGUAGE_ASM__
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#pragma pack(1)
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typedef struct _hw_dcic
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{
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volatile hw_dcic_dcicc_t DCICC; //!< DCIC Control Register
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volatile hw_dcic_dcicic_t DCICIC; //!< DCIC Interrupt Control Register
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volatile hw_dcic_dcics_t DCICS; //!< DCIC Status Register
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reg32_t _reserved0;
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volatile hw_dcic_dcicrc_t DCICRC; //!< DCIC ROI Config Register m
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volatile hw_dcic_dcicrs_t DCICRS; //!< DCIC ROI Size Register m
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volatile hw_dcic_dcicrrs_t DCICRRS; //!< DCIC ROI Reference Signature Register m
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volatile hw_dcic_dcicrcs_t DCICRCS; //!< DCIC ROI Calculated Signature m
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} hw_dcic_t;
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#pragma pack()
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//! @brief Macro to access all DCIC registers.
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//! @param x DCIC instance number.
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//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
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//! use the '&' operator, like <code>&HW_DCIC(0)</code>.
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#define HW_DCIC(x) (*(hw_dcic_t *) REGS_DCIC_BASE(x))
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#endif
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#endif // __HW_DCIC_REGISTERS_H__
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// v18/121106/1.2.2
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// EOF
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