songyanguang
149 lines
4.8 KiB
C
149 lines
4.8 KiB
C
/*
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* Copyright (c) 2020 AIIT XUOS Lab
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* XiUOS is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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* See the Mulan PSL v2 for more details.
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*/
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/**
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* @file bootmmu.c
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* @brief build pagetable and enable mmu in boot time
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* @version 1.0
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* @author AIIT XUOS Lab
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* @date 2024.04.26
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*/
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/*************************************************
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File name: bootmmu.c
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Description: build pagetable and enable mmu in boot time
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Others:
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History:
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Author: AIIT XUOS Lab
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Modification:
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1. first version
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*************************************************/
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#include "core.h"
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#include "memlayout.h"
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#include "mmio_access.h"
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#include "mmu.h"
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#include "pagetable.h"
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#include "registers.h"
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#include <stdint.h>
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#include <string.h>
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extern uint64_t kernel_data_end[];
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extern uint64_t kernel_data_begin[];
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// clang-format off
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#define L2_TYPE_TAB 2
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#define L2_PTE_VALID 1
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#define L3_TYPE_TAB 2
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#define L3_PTE_VALID 1
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#define L4_TYPE_PAGE (3 << 0)
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#define L4_PTE_DEV ((0b00) << 2) // Device memory
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#define L4_PTE_NORMAL ((0b01) << 2) // Device memory
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#define L4_PTE_AF (1 << 10) // Data Access Permissions
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#define L4_PTE_PXN (1UL << 53) // Privileged eXecute Never
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#define L4_PTE_UXN (1UL << 54) // Unprivileged(user) eXecute Never
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#define L4_PTE_XN (PTE_PXN|PTE_UXN) // eXecute Never
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#define IDX_MASK (0b111111111)
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#define L3_PDE_INDEX(idx) ((idx << LEVEL3_PDE_SHIFT) & L3_IDX_MASK)
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// clang-format on
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uint64_t boot_l2pgdir[NUM_LEVEL2_PDE] __attribute__((aligned(0x1000))) = { 0 };
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uint64_t boot_dev_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 };
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uint64_t boot_kern_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 };
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uint64_t boot_dev_l4pgdirs[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 };
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uint64_t boot_kern_l4pgdirs[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 };
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static void build_boot_pgdir()
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{
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static bool built = false;
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if (!built) {
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uint64_t dev_phy_mem_base = DEV_PHYMEM_BASE;
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// dev mem
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boot_l2pgdir[(dev_phy_mem_base >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
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boot_l2pgdir[(MMIO_P2V_WO(dev_phy_mem_base) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
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uint64_t cur_mem_paddr = ALIGNDOWN((uint64_t)DEV_PHYMEM_BASE, LEVEL2_PDE_SIZE);
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for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) {
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boot_dev_l3pgdir[i] = (uint64_t)boot_dev_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID;
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for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) {
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boot_dev_l4pgdirs[i][j] = cur_mem_paddr | L4_TYPE_PAGE | L4_PTE_DEV | L4_PTE_AF | L4_PTE_XN;
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if (cur_mem_paddr >= DEV_PHYMEM_BASE && cur_mem_paddr < DEV_PHYMEM_BASE + DEV_MEM_SIZE) {
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boot_dev_l4pgdirs[i][j] = cur_mem_paddr | 0x403;
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} else {
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boot_dev_l4pgdirs[i][j] = cur_mem_paddr | 0x403;
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}
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cur_mem_paddr += PAGE_SIZE;
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}
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}
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// identical mem
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boot_l2pgdir[(PHY_MEM_BASE >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
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boot_l2pgdir[(P2V_WO(PHY_MEM_BASE) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
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cur_mem_paddr = ALIGNDOWN((uint64_t)0x00000000ULL, PAGE_SIZE);
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for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) {
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boot_kern_l3pgdir[i] = (uint64_t)boot_kern_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID;
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for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) {
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boot_kern_l4pgdirs[i][j] = cur_mem_paddr | 0x713;
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cur_mem_paddr += PAGE_SIZE;
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}
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}
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built = true;
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}
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}
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static void load_boot_pgdir()
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{
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TTBR0_W((uintptr_t)boot_l2pgdir);
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TTBR1_W(0);
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#define TCR_TRUE_VALUE (0x0000000080813519ULL)
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uint64_t tcr = 0;
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TCR_R(tcr);
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tcr &= (uint64_t)~0xFF;
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tcr |= 0x19;
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TCR_W(tcr);
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CLEARTLB(0);
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ISB();
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}
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extern void main(void);
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static bool _bss_inited = false;
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void bootmain()
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{
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#if 0
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build_boot_pgdir();
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load_boot_pgdir();
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// __asm__ __volatile__("add sp, sp, %0" ::"r"(KERN_OFFSET));
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if (!_bss_inited) {
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memset(&kernel_data_begin, 0x00, (size_t)((uint64_t)kernel_data_end - (uint64_t)kernel_data_begin));
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_bss_inited = true;
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}
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#endif
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main();
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}
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