chunyexixiaoyu
61aff201a6
1.mdk keil project is supported. 2.gcc is supported. 3.boot image can be configured to be selected or not,if you use mdk keil,please select xip boot image 4. bin and elf files can be load by NXP-MCUBootUtility.exe.
143 lines
4.0 KiB
C
143 lines
4.0 KiB
C
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2009-01-05 Bernard first implementation
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "board.h"
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#include "pin_mux.h"
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#ifdef BSP_USING_DMA
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#include "fsl_dmamux.h"
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#include "fsl_edma.h"
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#endif
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#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
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4 bits for subpriority */
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#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
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3 bits for subpriority */
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#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
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2 bits for subpriority */
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#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
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1 bits for subpriority */
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#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
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0 bits for subpriority */
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/* MPU configuration. */
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static void BOARD_ConfigMPU(void)
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{
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/* Disable I cache and D cache */
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SCB_DisableICache();
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SCB_DisableDCache();
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/* Disable MPU */
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ARM_MPU_Disable();
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/* Region 0 setting */
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MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
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/* Region 1 setting */
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MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
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/* Region 2 setting */
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// spi flash: normal type, cacheable, no bufferable, no shareable
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MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512MB);
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/* Region 3 setting */
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MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
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/* Region 4 setting */
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MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
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/* Region 5 setting */
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MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
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/* Region 6 setting */
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MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
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#if defined(BSP_USING_SDRAM)
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/* Region 7 setting */
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MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
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/* Region 8 setting */
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MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
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#endif
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/* Enable MPU */
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ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
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/* Enable I cache and D cache */
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SCB_EnableDCache();
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SCB_EnableICache();
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}
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/* This is the timer interrupt service routine. */
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void SysTick_Handler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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rt_tick_increase();
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#ifdef BSP_USING_DMA
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void imxrt_dma_init(void)
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{
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edma_config_t config;
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DMAMUX_Init(DMAMUX);
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EDMA_GetDefaultConfig(&config);
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EDMA_Init(DMA0, &config);
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}
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#endif
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void rt_hw_board_init()
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{
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BOARD_ConfigMPU();
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BOARD_InitPins();
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BOARD_BootClockRUN();
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NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
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SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
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#ifdef BSP_USING_DMA
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imxrt_dma_init();
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#endif
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#ifdef RT_USING_HEAP
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rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
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#endif
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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}
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void rt_hw_us_delay(rt_uint32_t usec)
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{
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;
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}
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