songyanguang
120 lines
3.9 KiB
C
120 lines
3.9 KiB
C
/*
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* Copyright (c) 2020 AIIT XUOS Lab
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* XiUOS is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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* See the Mulan PSL v2 for more details.
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*/
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/**
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* @file mmu.h
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* @brief mmu related configure and registers
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* @version 1.0
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* @author AIIT XUOS Lab
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* @date 2024-04-26
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*/
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/*************************************************
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File name: mmu.h
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Description: mmu related configure and registers
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Others:
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History:
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Author: AIIT XUOS Lab
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Modification:
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1. first version
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*************************************************/
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#pragma once
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#include <stdint.h>
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#include "memlayout.h"
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// #define TCR_SH1_INNER (0b11 << 28)
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// #define TCR_ORGN1_IRGN1_WRITEBACK_WRITEALLOC ((0b01 << 26) | (0b01 << 24))
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// #define TCR_SH0_INNER (0b11 << 12)
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// #define TCR_ORGN0_IRGN0_WRITEBACK_WRITEALLOC ((0b01 << 10) | (0b01 << 8))
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#define TCR_IPS (0 << 0)
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#define TCR_TG1_4K (0b10 << 30)
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#define TCR_TOSZ (0b11001 << 0)
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#define TCR_T1SZ (0b11001 << 16)
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#define TCR_TG0_4K (0 << 14)
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#define TCR_VALUE \
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(TCR_IPS | TCR_TG1_4K | TCR_TG0_4K | TCR_TOSZ | TCR_T1SZ)
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enum AccessPermission {
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AccessPermission_NoAccess = 0,
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AccessPermission_KernelOnly = 1, // EL1
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AccessPermission_Reserved = 2,
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AccessPermission_KernelUser = 3, // EL1&EL0
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};
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void GetDevPteAttr(uintptr_t* attr);
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void GetUsrPteAttr(uintptr_t* attr);
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void GetUsrDevPteAttr(uintptr_t* attr);
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void GetKernPteAttr(uintptr_t* attr);
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void GetPdeAttr(uintptr_t* attr);
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/*
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Enable MMU, cache, write buffer, etc.
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*/
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//#define SCTLR_R(val) __asm__ volatile("mrs %0, sctlr_el1" : "=r"(val)::"memory")
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//#define SCTLR_W(val) __asm__ volatile("msr sctlr_el1, %0" ::"r"(val) : "memory")
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#define SCTLR_R(val) 0
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#define SCTLR_W(val) 0
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/*
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Read and write mmu pagetable register base addr
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*/
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//#define TTBR0_R(val) __asm__ volatile("mrs %0, ttbr0_el1" : "=r"(val)::"memory")
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//#define TTBR0_W(val) __asm__ volatile("msr ttbr0_el1, %0" ::"r"(val) : "memory")
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#define TTBR0_R(val) 0
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#define TTBR0_W(val) 0
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/*
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Read and write mmu pagetable register base addr
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*/
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//#define TTBR1_R(val) __asm__ volatile("mrs %0, ttbr1_el1" : "=r"(val)::"memory")
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//#define TTBR1_W(val) __asm__ volatile("msr ttbr1_el1, %0" ::"r"(val) : "memory")
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#define TTBR1_R(val) 0
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#define TTBR1_W(val) 0
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/*
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Translation Control Register（TCR）
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*/
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//#define TCR_R(val) __asm__ volatile("mrs %0, tcr_el1" : "=r"(val)::"memory")
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//#define TCR_W(val) __asm__ volatile("msr tcr_el1, %0" ::"r"(val) : "memory")
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#define TCR_R(val) 0
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#define TCR_W(val) 0
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//#define MAIR_R(val) __asm__ volatile("mrs %0, mair_el1" : "=r"(val)::"memory")
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//#define MAIR_W(val) __asm__ volatile("msr mair_el1, %0" ::"r"(val) : "memory")
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#define MAIR_R(val) 0
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#define MAIR_W(val) 0
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/*
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Flush TLB when loading a new page table.
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@note If nG is not set in the pte attribute, process switching need flush tlb.
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*/
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// #define CLEARTLB(val) __asm__ volatile("tlbi vmalle1" ::: "memory")
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//#define CLEARTLB(val) __asm__ volatile("tlbi vmalle1is" ::: "memory")
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#define CLEARTLB(val) 0
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/*
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When nG is set in the pte attribute, the process is assigned an ASID, which is stored in the lower 8 bits of the CONTEXTIDR register.
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When the process switches, the flush TLB is no longer required anymore.
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*/
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//#define CONTEXTIDR_R(val) __asm__ volatile("mrs %0, contextidr_el1" : "=r"(val))
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//#define CONTEXTIDR_W(val) __asm__ volatile("msr contextidr_el1, %0" ::"r"(val))
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#define CONTEXTIDR_R(val) 0
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#define CONTEXTIDR_W(val) 0
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#ifndef __ASSEMBLER__
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#include <stdint.h>
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__attribute__((always_inline)) static inline uint64_t v2p(void* a) { return ((uint64_t)(a)) - KERN_MEM_BASE; }
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__attribute__((always_inline)) static inline void* p2v(uint64_t a) { return (void*)((a) + KERN_MEM_BASE); }
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#endif
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