KouweiLee
229 lines
10 KiB
C
229 lines
10 KiB
C
/*
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* Copyright (c) 2020 AIIT XUOS Lab
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* XiUOS is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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* See the Mulan PSL v2 for more details.
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*/
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/*************************************************
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File name: board.c
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Description: support NXP.imx8mp-board init configure and driver/task/... init
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Others:
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History:
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1. Date: 2025-02-26
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Author: AIIT XUOS Lab
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Modification:
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1. support NXP.imx8mp-board InitBoardHardware
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*************************************************/
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#include "clock_config.h"
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#include "board.h"
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#include "fsl_rdc.h"
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#include "pin_mux.h"
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#include "fsl_clock.h"
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#include <device.h>
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#include "rsc_table.h"
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#include "xs_base.h"
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#include <connect_uart.h>
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#define BOARD_IMX8MP
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extern void MU1_M7_IRQHandler(int irqn, void *arg);
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DECLARE_HW_IRQ(MU1_M7_IRQn, MU1_M7_IRQHandler, NONE);
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extern int rpmsg_remote(void);
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void BOARD_ConfigMPU(void)
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{
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/* __CACHE_REGION_START and __CACHE_REGION_SIZE are defined in the linker file */
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extern uint32_t __CACHE_REGION_START[];
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extern uint32_t __CACHE_REGION_SIZE[];
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uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
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uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
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uint32_t i = 0;
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/* Disable I cache and D cache */
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if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
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{
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SCB_DisableICache();
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}
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if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
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{
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SCB_DisableDCache();
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}
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/* Disable MPU */
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ARM_MPU_Disable();
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/* MPU configure:
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* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
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* SubRegionDisable, Size)
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* API in mpu_armv7.h.
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* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
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* disabled.
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* param AccessPermission Data access permissions, allows you to configure read/write access for User and
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* Privileged mode.
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* Use MACROS defined in mpu_armv7.h:
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* ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
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* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
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* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
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* 0 x 0 0 Strongly Ordered shareable
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* 0 x 0 1 Device shareable
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* 0 0 1 0 Normal not shareable Outer and inner write
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* through no write allocate
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* 0 0 1 1 Normal not shareable Outer and inner write
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* back no write allocate
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* 0 1 1 0 Normal shareable Outer and inner write
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* through no write allocate
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* 0 1 1 1 Normal shareable Outer and inner write
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* back no write allocate
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* 1 0 0 0 Normal not shareable outer and inner
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* noncache
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* 1 1 0 0 Normal shareable outer and inner
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* noncache
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* 1 0 1 1 Normal not shareable outer and inner write
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* back write/read acllocate
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* 1 1 1 1 Normal shareable outer and inner write
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* back write/read acllocate
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* 2 x 0 0 Device not shareable
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* Above are normal use settings, if your want to see more details or want to config different inner/outter cache
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* policy.
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* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
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* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
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* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
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* mpu_armv7.h.
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*/
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/* Region 0 [0x0000_0000 - 0x4000_0000] : Memory with Device type, not executable, not shareable, non-cacheable. */
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MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
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MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_FULL, 0, 0, 0, 1, 0, ARM_MPU_REGION_SIZE_1GB);
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/* Region 1 TCML[0x0000_0000 - 0x0001_FFFF]: Memory with Normal type, not shareable, non-cacheable */
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MPU->RBAR = ARM_MPU_RBAR(1, 0x00000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_128KB);
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/* Region 2 QSPI[0x0800_0000 - 0x0FFF_FFFF]: Memory with Normal type, not shareable, cacheable */
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MPU->RBAR = ARM_MPU_RBAR(2, 0x08000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128MB);
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/* Region 3 TCMU[0x2000_0000 - 0x2002_0000]: Memory with Normal type, not shareable, non-cacheable */
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MPU->RBAR = ARM_MPU_RBAR(3, 0x20000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_128KB);
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/* Region 4 DDR[0x4000_0000 - 0x8000_0000]: Memory with Normal type, not shareable, non-cacheable */
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MPU->RBAR = ARM_MPU_RBAR(4, 0x40000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
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/*
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Non-cacheable area is provided in DDR memory, the DDR region [0x80000000 ~ 0x81000000](please see the
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imx8mp-evk-rpmsg.dts) totally 16MB is revserved for CM7 core. You can put global or static uninitialized
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variables in NonCacheable section(initialized variables in NonCacheable.init section) to make them uncacheable.
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Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 5 set
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the address space 0x80000000 ~ 0xBFFFFFFF to be non-cacheable. Then MPU region 6 set the text and data section to
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be cacheable if the program running on DDR. The cacheable area base address should be multiples of its size in
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linker file, they can be modified per your needs.
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*/
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/* Region 5 DDR[0x8000_0000 - 0xBFFFFFFF]: Memory with Normal type, not shareable, non-cacheable */
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MPU->RBAR = ARM_MPU_RBAR(5, 0x80000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
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while ((size >> i) > 0x1U)
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{
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i++;
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}
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/* If run on DDR, configure text and data section to be cacheable */
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if (i != 0)
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{
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/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
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assert((size & (size - 1)) == 0);
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assert(!(cacheStart % size));
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assert(size == (uint32_t)(1 << i));
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assert(i >= 5);
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/* Region 6 DDR[cacheStart]: Memory with Normal type, not shareable, cacheable */
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MPU->RBAR = ARM_MPU_RBAR(6, cacheStart);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 1, 1, 0, (i - 1));
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}
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/*
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* Enable MPU and HFNMIENA feature
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* HFNMIENA ensures that M7 core uses MPU configuration when in hard fault, NMI, and FAULTMASK handlers,
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* otherwise all memory regions are accessed without MPU protection, which has high risks of cacheable,
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* especially for AIPS systems.
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*/
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ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
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/* Enable I cache and D cache */
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SCB_EnableICache();
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SCB_EnableDCache();
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}
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void BOARD_RdcInit(void)
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{
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/* Move M7 core to specific RDC domain 1 */
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rdc_domain_assignment_t assignment = {0};
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assignment.domainId = BOARD_DOMAIN_ID;
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RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M7, &assignment);
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/*
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* The M7 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
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* In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
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* domain 0.
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*/
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CLOCK_EnableClock(kCLOCK_Iomux);
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CLOCK_EnableClock(kCLOCK_Ipmux1);
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CLOCK_EnableClock(kCLOCK_Ipmux2);
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CLOCK_EnableClock(kCLOCK_Ipmux3);
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#if defined(FLASH_TARGET)
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CLOCK_EnableClock(kCLOCK_Qspi);
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#endif
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CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
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CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
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CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
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CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
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CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
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CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
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}
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/* This is the timer interrupt service routine. */
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void SysTick_Handler(int irqn, void *arg)
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{
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TickAndTaskTimesliceUpdate();
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}
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/**
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* This function will initial imx8mp board.
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*/
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void InitBoardHardware()
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{
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char ch;
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/* Init board hardware. */
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/* M7 has its local cache and enabled by default,
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* need to set smart subsystems (0x28000000 ~ 0x3FFFFFFF)
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* non-cacheable before accessing this address region */
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BOARD_ConfigMPU();
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/* Board specific RDC settings */
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BOARD_RdcInit();
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BOARD_InitPins();
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BOARD_BootClockRUN();
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SysTick_Config(SystemCoreClock / TICK_PER_SECOND);
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InitBoardMemory((void *)HEAP_BEGIN, (void *)HEAP_END);
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HwUartInit();
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InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
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KPrintf("\nconsole init completed.\n");
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copyResourceTable();
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KPrintf("board init done.\n");
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KPrintf("start kernel...\n");
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} |