FSP Configuration
  Board "RZ/V2L Evaluation Kit (SMARC)"
  R9A07G054L23GBG_CM33
    part_number: R9A07G054L23GBG_CM33
    rom_size_bytes: 0
    ram_size_bytes: 131072
    package_style: LFBGA
    package_pins: 456
    
  RZV2L
    series: 2
    
  RZV2L Family
  RZ/V2L Common
    Secure stack size (bytes): 0x200
    Main stack size (bytes): 0x200
    Heap size (bytes): 0
    MCU Vcc (mV): 3300
    Parameter checking: Disabled
    Assert Failures: Return FSP_ERR_ASSERTION
    Error Log: No Error Log
    PFS Protect: Enabled
    C Runtime Initialization : Enabled
    
  Clocks
    OSC 24000000Hz
    ICLK 1200000000Hz
    I2CLK 200000000Hz
    GCLK 500000000Hz
    S0CLK 12000Hz
    SPI0CLK 200000000Hz
    SPI1CLK 100000000Hz
    SD0CLK 533000000Hz
    SD1CLK 533000000Hz
    M0CLK 200000000Hz
    M1CLK 3000000000Hz
    M2CLK 266500000Hz
    M3CLK 3000000000Hz
    M4CLK 16656000Hz
    HPCLK 250000000Hz
    TSUCLK 80000000Hz
    ZTCLK 100000000Hz
    P0CLK 100000000Hz
    P1CLK 200000000Hz
    P2CLK 100000000Hz
    ATCLK 400000000Hz
    
  User Events
    
  Module "I/O Port Driver on r_ioport"
    Parameter Checking: Default (BSP)
    
  HAL
    Instance "g_ioport I/O Port Driver on r_ioport"
      Name: g_ioport