Add PLIC
This commit is contained in:
songyanguang
parent
72e3175707
commit
fe26bb4e5a
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@ -0,0 +1,175 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* {read,write}{b,w,l,q} based on arch/arm64/include/asm/io.h
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* which was based on arch/arm/include/io.h
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*
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* Copyright (C) 1996-2000 Russell King
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* Copyright (C) 2012 ARM Ltd.
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* Copyright (C) 2014 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_MMIO_H
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#define _ASM_RISCV_MMIO_H
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//#include <linux/types.h>
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//#include <asm/mmiowb.h>
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#include "asm/const.h"
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#include <stdint.h>
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typedef uint8_t u8;
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typedef uint16_t u16;
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typedef uint32_t u32;
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typedef uint64_t u64;
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typedef uint32_t __le32;
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#ifndef __iomem
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#define __iomem
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#endif
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#ifndef asm
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#define asm __asm__
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#endif
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#define __force
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#define cpu_to_le32(x) (x)
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#define le16_to_cpu(x) (x)
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#define le32_to_cpu(x) (x)
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#define le64_to_cpu(x) (x)
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/* Generic IO read/write. These perform native-endian accesses. */
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#define __raw_writeb __raw_writeb
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static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
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{
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asm volatile("sb %0, 0(%1)" : : "r" (val), "r" (addr));
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}
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#define __raw_writew __raw_writew
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static inline void __raw_writew(u16 val, volatile void __iomem *addr)
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{
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asm volatile("sh %0, 0(%1)" : : "r" (val), "r" (addr));
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}
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#define __raw_writel __raw_writel
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static inline void __raw_writel(u32 val, volatile void __iomem *addr)
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{
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asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
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}
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#ifdef CONFIG_64BIT
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#define __raw_writeq __raw_writeq
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static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
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{
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asm volatile("sd %0, 0(%1)" : : "r" (val), "r" (addr));
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}
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#endif
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#define __raw_readb __raw_readb
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static inline u8 __raw_readb(const volatile void __iomem *addr)
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{
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u8 val;
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asm volatile("lb %0, 0(%1)" : "=r" (val) : "r" (addr));
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return val;
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}
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#define __raw_readw __raw_readw
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static inline u16 __raw_readw(const volatile void __iomem *addr)
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{
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u16 val;
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asm volatile("lh %0, 0(%1)" : "=r" (val) : "r" (addr));
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return val;
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}
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#define __raw_readl __raw_readl
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static inline u32 __raw_readl(const volatile void __iomem *addr)
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{
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u32 val;
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asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
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return val;
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}
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#ifdef CONFIG_64BIT
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#define __raw_readq __raw_readq
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static inline u64 __raw_readq(const volatile void __iomem *addr)
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{
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u64 val;
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asm volatile("ld %0, 0(%1)" : "=r" (val) : "r" (addr));
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return val;
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}
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#endif
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/*
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* Unordered I/O memory access primitives. These are even more relaxed than
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* the relaxed versions, as they don't even order accesses between successive
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* operations to the I/O regions.
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*/
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#define readb_cpu(c) ({ u8 __r = __raw_readb(c); __r; })
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#define readw_cpu(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
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#define readl_cpu(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
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#define writeb_cpu(v, c) ((void)__raw_writeb((v), (c)))
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#define writew_cpu(v, c) ((void)__raw_writew((__force u16)cpu_to_le16(v), (c)))
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#define writel_cpu(v, c) ((void)__raw_writel((__force u32)cpu_to_le32(v), (c)))
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#ifdef CONFIG_64BIT
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#define readq_cpu(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })
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#define writeq_cpu(v, c) ((void)__raw_writeq((__force u64)cpu_to_le64(v), (c)))
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#endif
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/*
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* Relaxed I/O memory access primitives. These follow the Device memory
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* ordering rules but do not guarantee any ordering relative to Normal memory
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* accesses. These are defined to order the indicated access (either a read or
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* write) with all other I/O memory accesses. Since the platform specification
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* defines that all I/O regions are strongly ordered on channel 2, no explicit
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* fences are required to enforce this ordering.
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*/
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/* FIXME: These are now the same as asm-generic */
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#define __io_rbr() do {} while (0)
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#define __io_rar() do {} while (0)
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#define __io_rbw() do {} while (0)
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#define __io_raw() do {} while (0)
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#define readb_relaxed(c) ({ u8 __v; __io_rbr(); __v = readb_cpu(c); __io_rar(); __v; })
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#define readw_relaxed(c) ({ u16 __v; __io_rbr(); __v = readw_cpu(c); __io_rar(); __v; })
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#define readl_relaxed(c) ({ u32 __v; __io_rbr(); __v = readl_cpu(c); __io_rar(); __v; })
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#define writeb_relaxed(v, c) ({ __io_rbw(); writeb_cpu((v), (c)); __io_raw(); })
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#define writew_relaxed(v, c) ({ __io_rbw(); writew_cpu((v), (c)); __io_raw(); })
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#define writel_relaxed(v, c) ({ __io_rbw(); writel_cpu((v), (c)); __io_raw(); })
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#ifdef CONFIG_64BIT
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#define readq_relaxed(c) ({ u64 __v; __io_rbr(); __v = readq_cpu(c); __io_rar(); __v; })
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#define writeq_relaxed(v, c) ({ __io_rbw(); writeq_cpu((v), (c)); __io_raw(); })
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#endif
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/*
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* I/O memory access primitives. Reads are ordered relative to any
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* following Normal memory access. Writes are ordered relative to any prior
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* Normal memory access. The memory barriers here are necessary as RISC-V
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* doesn't define any ordering between the memory space and the I/O space.
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*/
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#define __io_br() do {} while (0)
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#define __io_ar(v) __asm__ __volatile__ ("fence i,r" : : : "memory")
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#define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory")
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//#define __io_aw() mmiowb_set_pending()
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#define __io_aw() do {} while (0)
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#define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; })
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#define readw(c) ({ u16 __v; __io_br(); __v = readw_cpu(c); __io_ar(__v); __v; })
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#define readl(c) ({ u32 __v; __io_br(); __v = readl_cpu(c); __io_ar(__v); __v; })
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#define writeb(v, c) ({ __io_bw(); writeb_cpu((v), (c)); __io_aw(); })
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#define writew(v, c) ({ __io_bw(); writew_cpu((v), (c)); __io_aw(); })
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#define writel(v, c) ({ __io_bw(); writel_cpu((v), (c)); __io_aw(); })
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#ifdef CONFIG_64BIT
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#define readq(c) ({ u64 __v; __io_br(); __v = readq_cpu(c); __io_ar(__v); __v; })
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#define writeq(v, c) ({ __io_bw(); writeq_cpu((v), (c)); __io_aw(); })
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#endif
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#endif /* _ASM_RISCV_MMIO_H */
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@ -1,4 +1,4 @@
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SRC_FILES := entry.S trampoline.S $(BOARD)/trap_common.c $(BOARD)/trap.c error_debug.c hard_spinlock.S
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SRC_FILES := entry.S trampoline.S $(BOARD)/trap_common.c $(BOARD)/trap.c $(BOARD)/plic.c error_debug.c hard_spinlock.S
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ifeq ($(BOARD), jh7110)
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SRC_DIR := gicv3
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@ -0,0 +1,73 @@
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/*
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* This driver implements a version of the RISC-V PLIC with the actual layout
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* specified in chapter 8 of the SiFive U5 Coreplex Series Manual:
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*
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* https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
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*
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*/
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#include "asm/csr.h"
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#include "printf.h"
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#include "plic.h"
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#include "asm/mmio.h"
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#include "ptrace.h"
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extern unsigned long boot_cpu_hartid;
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#define MAX_CPUS 4
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#define MAX_PLIC_IRQS 136
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#define CPU_TO_HART(cpu) ((2 * cpu) + 2)
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void plic_set_priority(int hwirq, int pro)
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{
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unsigned int reg = PLIC_PRIORITY(hwirq);
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writel(pro, reg);
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}
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void plic_enable_irq(int cpu, int hwirq, int enable)
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{
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unsigned int hwirq_mask = 1 << (hwirq % 32);
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int hart = CPU_TO_HART(cpu);
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unsigned int reg = PLIC_MENABLE(hart) + 4 * (hwirq / 32);
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if (enable) {
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writel(readl(reg) | hwirq_mask, reg);
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}
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else {
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writel(readl(reg) & ~hwirq_mask, reg);
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}
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}
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//TODO: to debug
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int plic_init(void)
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{
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int i;
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int hwirq;
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printk("plic_init boot_cpu_hartid=%lu\n", boot_cpu_hartid);
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for (i = 0; i < MAX_CPUS; i++) {
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writel(0, PLIC_MTHRESHOLD(CPU_TO_HART(i)));
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for (hwirq = 1; hwirq <= MAX_PLIC_IRQS; hwirq++) {
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plic_enable_irq(i, hwirq, 0);
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plic_set_priority(hwirq, 1);
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}
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}
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csr_set(CSR_IE, IE_EIE);
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return 0;
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}
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void plic_handle_irq(struct pt_regs *regs)
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{
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int hwirq;
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int hart = CPU_TO_HART(0);
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unsigned int claim_reg = PLIC_MCLAIM(hart);
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csr_clear(CSR_IE, IE_EIE);
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//TODO
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csr_set(CSR_IE, IE_EIE);
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}
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@ -0,0 +1,20 @@
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#ifndef _RISCV_PLIC_H
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#define _RISCV_PLIC_H
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#include "memlayout.h"
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#include "ptrace.h"
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#define PLIC_BASE PLIC_PHYMEM_BASE
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#define PLIC_PRIORITY(hwirq) (PLIC_BASE + (hwirq) * 4)
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#define PLIC_PENDING(hwirq) (PLIC_BASE + 0x1000 + ((hwirq) / 32) * 4)
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#define PLIC_MENABLE(hart) (PLIC_BASE + 0x2000 + (hart) * 0x80)
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#define PLIC_MTHRESHOLD(hart) (PLIC_BASE + 0x200000 + (hart) * 0x1000)
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#define PLIC_MCLAIM(hart) (PLIC_BASE + 0x200004 + (hart) * 0x1000)
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int plic_init(void);
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void plic_enable_irq(int cpu, int hwirq, int enable);
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void plic_handle_irq(struct pt_regs *regs);
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#endif /* _RISCV_PLIC_H */
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@ -40,6 +40,7 @@ Modification:
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#include "asm/csr.h"
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#include "ptrace.h"
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#include "plic.h"
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extern void dabort_handler(struct trapframe* r);
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@ -126,6 +127,16 @@ void syscall_arch_handler(struct trapframe* tf)
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extern void do_exception_vector(void);
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void trap_init(void)
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{
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csr_write(stvec, do_exception_vector);
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csr_write(sie, 0);
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}
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static void do_trap_error(struct pt_regs *regs, const char *str)
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{
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printk("Oops: %s\n", str);
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@ -179,26 +190,6 @@ static const struct fault_info fault_inf[] = {
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};
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/*
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void delegate_traps(void)
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{
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unsigned long interrupts = MIP_SSIP | MIP_STIP | MIP_SEIP;
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unsigned long exceptions = (1UL << CAUSE_MISALIGNED_FETCH) |
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(1UL << CAUSE_FETCH_PAGE_FAULT) |
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(1UL << CAUSE_BREAKPOINT) |
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(1UL << CAUSE_LOAD_PAGE_FAULT) |
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(1UL << CAUSE_STORE_PAGE_FAULT) |
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(1UL << CAUSE_USER_ECALL) |
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(1UL << CAUSE_LOAD_ACCESS_FAULT) |
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(1UL << CAUSE_STORE_ACCESS_FAULT);
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csr_write(mideleg, interrupts);
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csr_write(medeleg, exceptions);
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}
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*/
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struct fault_info * ec_to_fault_info(unsigned long scause)
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{
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struct fault_info *inf;
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@ -209,12 +200,22 @@ struct fault_info * ec_to_fault_info(unsigned long scause)
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inf = &fault_inf[scause];
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return inf;
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}
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extern void do_exception_vector(void);
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void trap_init(void)
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void handle_irq(struct pt_regs *regs, unsigned long scause)
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{
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csr_write(stvec, do_exception_vector);
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//printk("stvec=0x%lx, do_exception_vector=0x%lx\n", csr_read(stvec), (unsigned long)do_exception_vector);
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csr_write(sie, 0);
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switch (scause & ~CAUSE_IRQ_FLAG) {
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case IRQ_S_TIMER:
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//handle_timer_irq();
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break;
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case IRQ_S_EXT:
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plic_handle_irq(regs);
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break;
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case IRQ_S_SOFT:
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// TODO
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break;
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default:
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panic("unexpected interrupt cause\n");
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}
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}
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void do_exception(struct pt_regs *regs, unsigned long scause)
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@ -224,7 +225,7 @@ void do_exception(struct pt_regs *regs, unsigned long scause)
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printk("%s, scause: 0x%lx\n", __func__, scause);
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if (scause & CAUSE_IRQ_FLAG) {
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// TODO: 处理中断
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handle_irq(regs, scause);
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}
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else {
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inf = ec_to_fault_info(scause);
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@ -233,3 +234,4 @@ void do_exception(struct pt_regs *regs, unsigned long scause)
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}
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}
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}
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@ -37,6 +37,8 @@ Modification:
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#include "log.h"
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#include "multicores.h"
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#include "plic.h"
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static struct XiziTrapDriver xizi_trap_driver;
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void panic(char* s)
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@ -46,18 +48,26 @@ void panic(char* s)
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;
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}
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extern void alltraps();
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//extern void alltraps();
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extern void trap_init(void);
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static void _sys_irq_init(int cpu_id)
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{
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// primary core init intr
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xizi_trap_driver.switch_hw_irqtbl((uintptr_t*)alltraps);
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// xizi_trap_driver.switch_hw_irqtbl((uintptr_t*)alltraps);
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if (cpu_id == 0) {
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gic_init();
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plic_init();
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}
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gicv3inithart(cpu_id);
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}
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static void _sys_trap_init(int cpu_id)
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{
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if (cpu_id == 0) {
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trap_init();
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}
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_sys_irq_init(cpu_id);
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}
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static void _cpu_irq_enable(void)
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{
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intr_on();
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@ -70,12 +80,12 @@ static void _cpu_irq_disable(void)
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static void _single_irq_enable(int irq, int cpu, int prio)
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{
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gic_setup_ppi((uint32_t)cpu, (uint32_t)irq);
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plic_enable_irq(cpu, irq, 1);
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}
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static void _single_irq_disable(int irq, int cpu)
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{
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return;
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plic_enable_irq(cpu, irq, 0);
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}
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static inline uintptr_t* _switch_hw_irqtbl(uintptr_t* new_tbl_base)
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@ -113,7 +123,7 @@ int _cur_cpu_id()
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}
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static struct XiziTrapDriver xizi_trap_driver = {
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.sys_irq_init = _sys_irq_init,
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.sys_irq_init = _sys_trap_init,
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.cur_cpu_id = _cur_cpu_id,
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.cpu_irq_enable = _cpu_irq_enable,
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@ -1,16 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2012 Regents of the University of California
|
||||
*/
|
||||
|
||||
#ifndef _ASM_RISCV_PTRACE_H
|
||||
#define _ASM_RISCV_PTRACE_H
|
||||
|
||||
//#include <uapi/asm/ptrace.h>
|
||||
//#include <asm/csr.h>
|
||||
//#include <linux/compiler.h>
|
||||
|
||||
|
||||
struct pt_regs {
|
||||
unsigned long epc;
|
||||
unsigned long ra;
|
||||
|
|
|
|||
|
|
@ -78,6 +78,11 @@ Modification:
|
|||
#define KERN_MEM_BASE ((0 - 0x0000002000000000ULL) + PHY_MEM_BASE) // First kernel virtual address
|
||||
#define KERN_OFFSET (KERN_MEM_BASE - PHY_MEM_BASE)
|
||||
|
||||
/* PLIC (platform-level interrupt controller) memory layout */
|
||||
#define PLIC_PHYMEM_BASE (0x0C000000ULL)
|
||||
#define PLIC_MEM_SIZE (0x00400000ULL)
|
||||
|
||||
|
||||
#define V2P(a) (((uint64_t)(a)) - KERN_OFFSET)
|
||||
#define P2V(a) ((void *)(((char *)(a)) + KERN_OFFSET))
|
||||
|
||||
|
|
|
|||
|
|
@ -56,6 +56,7 @@ static pmd_t early_pmd[PTRS_PER_PMD] __initdata __attribute__((aligned(PAGE_SIZE
|
|||
static pmd_t early_uart_pmd[PTRS_PER_PMD] __initdata __attribute__((aligned(PAGE_SIZE)));
|
||||
static pmd_t early_pmd_free[((PHY_USER_FREEMEM_BASE - PHY_MEM_BASE) >> PGDIR_SHIFT) + 1][PTRS_PER_PMD] __initdata __attribute__((aligned(PAGE_SIZE)));
|
||||
static pmd_t early_pmd_inear_map[PTRS_PER_PMD] __initdata __attribute__((aligned(PAGE_SIZE)));
|
||||
static pmd_t early_plic_pmd[PTRS_PER_PMD] __initdata __attribute__((aligned(PAGE_SIZE)));
|
||||
|
||||
|
||||
static pmd_t *__init get_pmd_virt_early(phys_addr_t pa)
|
||||
|
|
@ -125,7 +126,6 @@ static void __init create_kernel_page_table_early(pgd_t *pgdir, bool early)
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
static void __init create_kernel_pgd_mapping_free_early(pgd_t *pgdp,
|
||||
uintptr_t va, phys_addr_t pa,
|
||||
phys_addr_t sz, pgprot_t prot)
|
||||
|
|
@ -195,6 +195,17 @@ static void __init create_kernel_page_table_linear_map_early(pgd_t *pgdir, bool
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
static void __init create_plic_page_table_early(pgd_t *pgdir, bool early)
|
||||
{
|
||||
uintptr_t va;
|
||||
|
||||
for (va = PLIC_PHYMEM_BASE; va < PLIC_PHYMEM_BASE + PLIC_MEM_SIZE; va += PMD_SIZE) {
|
||||
create_pgd_mapping_early(pgdir, va, (uintptr_t)early_plic_pmd, PGDIR_SIZE, PAGE_TABLE);
|
||||
create_pmd_mapping_early(early_plic_pmd, va, va, PMD_SIZE, PAGE_KERNEL);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* setup_vm_early() is called from boot.S with MMU-off.
|
||||
*
|
||||
|
|
@ -238,5 +249,8 @@ void __init setup_vm_early(void)
|
|||
|
||||
/* Setup kernel linear map PGD and PMD */
|
||||
create_kernel_page_table_linear_map_early(early_pg_dir, true);
|
||||
|
||||
/* Setup PLIC PGD and PMD */
|
||||
create_plic_page_table_early(early_pg_dir, true);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue