Modify handle_exception according to the Linux code
This commit is contained in:
songyanguang
parent
301073476f
commit
ee49e0d71c
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@ -1,4 +1,4 @@
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SRC_FILES := entry.S trampoline.S $(BOARD)/trap_common.c $(BOARD)/trap.c $(BOARD)/plic.c error_debug.c hard_spinlock.S
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SRC_FILES := trampoline.S $(BOARD)/trap_common.c $(BOARD)/trap.c $(BOARD)/plic.c error_debug.c hard_spinlock.S
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ifeq ($(BOARD), jh7110)
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SRC_DIR := gicv3
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@ -7,3 +7,4 @@ endif
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include $(KERNEL_ROOT)/compiler.mk
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@ -1,139 +0,0 @@
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/*
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* Copyright (c) 2020 AIIT XUOS Lab
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* XiUOS is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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* See the Mulan PSL v2 for more details.
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*/
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/**
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* @file entry.S
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* @brief trap in and out code
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* @version 1.0
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* @author AIIT XUOS Lab
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* @date 2024-12-10
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*/
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/*************************************************
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File name: entry.S
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Description: trap in and out code
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Others:
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History:
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1. Date: 2024-12-10
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Author: AIIT XUOS Lab
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Modification:
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1. first version
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*************************************************/
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#include "asm/asm-offsets.h"
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.macro kernel_entry
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addi sp, sp, -(PT_SIZE)
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sd x1, PT_RA(sp)
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sd x3, PT_GP(sp)
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sd x5, PT_T0(sp)
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sd x6, PT_T1(sp)
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sd x7, PT_T2(sp)
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sd x8, PT_S0(sp)
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sd x9, PT_S1(sp)
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sd x10, PT_A0(sp)
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sd x11, PT_A1(sp)
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sd x12, PT_A2(sp)
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sd x13, PT_A3(sp)
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sd x14, PT_A4(sp)
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sd x15, PT_A5(sp)
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sd x16, PT_A6(sp)
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sd x17, PT_A7(sp)
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sd x18, PT_S2(sp)
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sd x19, PT_S3(sp)
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sd x20, PT_S4(sp)
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sd x21, PT_S5(sp)
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sd x22, PT_S6(sp)
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sd x23, PT_S7(sp)
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sd x24, PT_S8(sp)
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sd x25, PT_S9(sp)
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sd x26, PT_S10(sp)
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sd x27, PT_S11(sp)
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sd x28, PT_T3(sp)
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sd x29, PT_T4(sp)
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sd x30, PT_T5(sp)
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sd x31, PT_T6(sp)
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csrr s2, sepc
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sd s2, PT_EPC(sp)
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csrr s3, sbadaddr
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sd s3, PT_BADADDR(sp)
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csrr s4, scause
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sd s4, PT_CAUSE(sp)
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csrr s5, sscratch
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sd s5, PT_TP(sp)
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addi s0, sp, PT_SIZE
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sd sp, PT_SP(sp)
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.endm
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.macro kernel_exit
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ld a0, PT_STATUS(sp)
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csrw sstatus, a0
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ld a2, PT_EPC(sp)
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csrw sepc, a2
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ld x1, PT_RA(sp)
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ld x3, PT_GP(sp)
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ld x5, PT_T0(sp)
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ld x6, PT_T1(sp)
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ld x7, PT_T2(sp)
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ld x8, PT_S0(sp)
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ld x9, PT_S1(sp)
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ld x10, PT_A0(sp)
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ld x11, PT_A1(sp)
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ld x12, PT_A2(sp)
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ld x13, PT_A3(sp)
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ld x14, PT_A4(sp)
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ld x15, PT_A5(sp)
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ld x16, PT_A6(sp)
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ld x17, PT_A7(sp)
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ld x18, PT_S2(sp)
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ld x19, PT_S3(sp)
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ld x20, PT_S4(sp)
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ld x21, PT_S5(sp)
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ld x22, PT_S6(sp)
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ld x23, PT_S7(sp)
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ld x24, PT_S8(sp)
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ld x25, PT_S9(sp)
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ld x26, PT_S10(sp)
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ld x27, PT_S11(sp)
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ld x28, PT_T3(sp)
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ld x29, PT_T4(sp)
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ld x30, PT_T5(sp)
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ld x31, PT_T6(sp)
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ld x2, PT_SP(sp)
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.endm
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.align 4
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.global do_exception_vector
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do_exception_vector:
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kernel_entry
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la ra, ret_from_exception
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mv a0, sp /* pt_regs */
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mv a1, s4
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tail do_exception
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ret_from_exception:
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restore_all:
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kernel_exit
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sret
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.global trigger_fault
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trigger_fault:
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li a0, 0x70000000
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ld a0, (a0)
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ret
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@ -127,15 +127,24 @@ void syscall_arch_handler(struct trapframe* tf)
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extern void do_exception_vector(void);
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extern void handle_exception(void);
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void trap_init(void)
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{
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csr_write(stvec, do_exception_vector);
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csr_write(stvec, handle_exception);
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csr_write(sie, 0);
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__asm__ volatile("csrw sscratch, zero" : : : "memory");
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#if 0
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printk("trap_init test\n");
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__asm__ volatile("ebreak");
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printk("trap_init test ok\n");
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#endif
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}
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void trap_set_exception_vector(uint64_t new_tbl_base)
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{
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csr_write(stvec, new_tbl_base);
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}
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static void do_trap_error(struct pt_regs *regs, const char *str)
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{
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@ -225,7 +234,7 @@ void do_exception(struct pt_regs *regs, unsigned long scause)
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printk("%s, scause: 0x%lx\n", __func__, scause);
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if (scause & CAUSE_IRQ_FLAG) {
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handle_irq(regs, scause);
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intr_irq_dispatch((struct trapframe *)regs);
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}
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else {
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inf = ec_to_fault_info(scause);
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@ -235,3 +244,10 @@ void do_exception(struct pt_regs *regs, unsigned long scause)
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}
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}
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#define INIT_THREAD_INFO \
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{ \
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.flags = 0, \
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.preempt_count = 1, \
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}
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struct thread_info init_thread_info = INIT_THREAD_INFO;
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@ -41,6 +41,9 @@ Modification:
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static struct XiziTrapDriver xizi_trap_driver;
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extern void trap_init(void);
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extern void trap_set_exception_vector(uint64_t new_tbl_base);
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void panic(char* s)
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{
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KPrintf("panic: %s\n", s);
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@ -48,12 +51,9 @@ void panic(char* s)
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;
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}
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//extern void alltraps();
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extern void trap_init(void);
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static void _sys_irq_init(int cpu_id)
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{
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// primary core init intr
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// xizi_trap_driver.switch_hw_irqtbl((uintptr_t*)alltraps);
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if (cpu_id == 0) {
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plic_init();
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}
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@ -90,8 +90,7 @@ static void _single_irq_disable(int irq, int cpu)
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static inline uintptr_t* _switch_hw_irqtbl(uintptr_t* new_tbl_base)
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{
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w_vbar_el1((uint64_t)new_tbl_base);
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trap_set_exception_vector(new_tbl_base);
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return NULL;
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}
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@ -29,84 +29,198 @@ Modification:
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*************************************************/
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#include "memlayout.h"
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#include "core.h"
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.macro savereg
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.endm
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.macro restorereg
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.endm
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.macro usavereg
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.endm
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.macro urestorereg
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.endm
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#include "asm/csr.h"
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#include "asm/asm-offsets.h"
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.global alltraps
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.balign 0x800
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alltraps:
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// Current EL with sp0
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j badtrap
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.balign 0x80
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j badtrap
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.balign 0x80
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j badtrap
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.balign 0x80
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j badtrap
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.align 4
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.global handle_exception
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handle_exception:
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csrrw tp, CSR_SCRATCH, tp
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bnez tp, _save_context
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// Current EL with spx
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.balign 0x80
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j el1sync
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.balign 0x80
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j el1irq
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.balign 0x80
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j badtrap
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.balign 0x80
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j badtrap
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_restore_kernel_tpsp:
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csrr tp, CSR_SCRATCH
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REG_S sp, TASK_TI_KERNEL_SP(tp)
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// Lower EL using aarch64
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.balign 0x80
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j el0sync
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.balign 0x80
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j el0irq
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.balign 0x80
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j badtrap
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.balign 0x80
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j badtrap
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_save_context:
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REG_S sp, TASK_TI_USER_SP(tp)
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REG_L sp, TASK_TI_KERNEL_SP(tp)
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addi sp, sp, -(PT_SIZE_ON_STACK)
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REG_S x1, PT_RA(sp)
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REG_S x3, PT_GP(sp)
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REG_S x5, PT_T0(sp)
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REG_S x6, PT_T1(sp)
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REG_S x7, PT_T2(sp)
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REG_S x8, PT_S0(sp)
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REG_S x9, PT_S1(sp)
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REG_S x10, PT_A0(sp)
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REG_S x11, PT_A1(sp)
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REG_S x12, PT_A2(sp)
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REG_S x13, PT_A3(sp)
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REG_S x14, PT_A4(sp)
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REG_S x15, PT_A5(sp)
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REG_S x16, PT_A6(sp)
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REG_S x17, PT_A7(sp)
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REG_S x18, PT_S2(sp)
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REG_S x19, PT_S3(sp)
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REG_S x20, PT_S4(sp)
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REG_S x21, PT_S5(sp)
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REG_S x22, PT_S6(sp)
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REG_S x23, PT_S7(sp)
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REG_S x24, PT_S8(sp)
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REG_S x25, PT_S9(sp)
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REG_S x26, PT_S10(sp)
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REG_S x27, PT_S11(sp)
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REG_S x28, PT_T3(sp)
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REG_S x29, PT_T4(sp)
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REG_S x30, PT_T5(sp)
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REG_S x31, PT_T6(sp)
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// Lower EL using aarch32
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.balign 0x80
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j badtrap
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.balign 0x80
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j badtrap
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.balign 0x80
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j badtrap
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.balign 0x80
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j badtrap
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/*
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* Disable user-mode memory access as it should only be set in the
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* actual user copy routines.
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*
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* Disable the FPU to detect illegal usage of floating point in kernel
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* space.
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*/
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li t0, SR_SUM | SR_FS
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badtrap:
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REG_L s0, TASK_TI_USER_SP(tp)
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csrrc s1, CSR_STATUS, t0
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csrr s2, CSR_EPC
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csrr s3, CSR_TVAL
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csrr s4, CSR_CAUSE
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csrr s5, CSR_SCRATCH
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REG_S s0, PT_SP(sp)
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REG_S s1, PT_STATUS(sp)
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REG_S s2, PT_EPC(sp)
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REG_S s3, PT_BADADDR(sp)
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REG_S s4, PT_CAUSE(sp)
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REG_S s5, PT_TP(sp)
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/*
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* Set the scratch register to 0, so that if a recursive exception
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* occurs, the exception vector knows it came from the kernel
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*/
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csrw CSR_SCRATCH, x0
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/* Load the global pointer */
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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/*
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* MSB of cause differentiates between
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* interrupts and exceptions
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*/
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bge s4, zero, 1f
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la ra, ret_from_exception
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/* Handle interrupts */
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move a0, sp /* pt_regs */
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//la a1, handle_arch_irq
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la a1, intr_irq_dispatch
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REG_L a1, (a1)
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jr a1
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1:
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/*
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* Exceptions run with interrupts enabled or disabled depending on the
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* state of SR_PIE in m/sstatus.
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*/
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andi t0, s1, SR_PIE
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beqz t0, 1f
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/* kprobes, entered via ebreak, must have interrupts disabled. */
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li t0, EXC_BREAKPOINT
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beq s4, t0, 1f
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csrs CSR_STATUS, SR_IE
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1:
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la ra, ret_from_exception
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/* Handle syscalls */
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li t0, EXC_SYSCALL
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beq s4, t0, handle_syscall
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mv a0, sp
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mv a1, s4
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tail do_exception
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handle_syscall:
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j .
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el1sync:
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j .
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el1irq:
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ret
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ret_from_exception:
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REG_L s0, PT_STATUS(sp)
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csrc CSR_STATUS, SR_IE
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el0sync:
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andi s0, s0, SR_SPP
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bnez s0, resume_kernel
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ret
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resume_userspace:
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/* Save unwound kernel stack pointer in thread_info */
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addi s0, sp, PT_SIZE_ON_STACK
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REG_S s0, TASK_TI_KERNEL_SP(tp)
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el0irq:
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jal intr_irq_dispatch
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/*
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* Save TP into the scratch register , so we can find the kernel data
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* structures again.
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*/
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csrw CSR_SCRATCH, tp
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.global trap_return
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trap_return:
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ret
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restore_all:
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REG_L a0, PT_STATUS(sp)
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REG_L a2, PT_EPC(sp)
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REG_SC x0, a2, PT_EPC(sp)
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csrw CSR_STATUS, a0
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csrw CSR_EPC, a2
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REG_L x1, PT_RA(sp)
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REG_L x3, PT_GP(sp)
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REG_L x4, PT_TP(sp)
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REG_L x5, PT_T0(sp)
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REG_L x6, PT_T1(sp)
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REG_L x7, PT_T2(sp)
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REG_L x8, PT_S0(sp)
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REG_L x9, PT_S1(sp)
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REG_L x10, PT_A0(sp)
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REG_L x11, PT_A1(sp)
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REG_L x12, PT_A2(sp)
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REG_L x13, PT_A3(sp)
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REG_L x14, PT_A4(sp)
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REG_L x15, PT_A5(sp)
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REG_L x16, PT_A6(sp)
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REG_L x17, PT_A7(sp)
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REG_L x18, PT_S2(sp)
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REG_L x19, PT_S3(sp)
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REG_L x20, PT_S4(sp)
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REG_L x21, PT_S5(sp)
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REG_L x22, PT_S6(sp)
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REG_L x23, PT_S7(sp)
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REG_L x24, PT_S8(sp)
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REG_L x25, PT_S9(sp)
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REG_L x26, PT_S10(sp)
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REG_L x27, PT_S11(sp)
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REG_L x28, PT_T3(sp)
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REG_L x29, PT_T4(sp)
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REG_L x30, PT_T5(sp)
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REG_L x31, PT_T6(sp)
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|
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REG_L x2, PT_SP(sp)
|
||||
|
||||
sret
|
||||
|
||||
resume_kernel:
|
||||
j restore_all
|
||||
|
||||
|
||||
.global task_prepare_enter
|
||||
task_prepare_enter:
|
||||
call xizi_leave_kernel
|
||||
j ret_from_exception
|
||||
|
|
|
|||
Loading…
Reference in New Issue