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support ch32v208

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gqk 2025-02-13 16:38:19 +08:00
parent dca3e93959
commit ec9bcaefb5
260 changed files with 58756 additions and 411 deletions
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2
APP_Framework/Applications/connection_app/4g_app/Makefile
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SRC_FILES := 4g_app.c
SRC_FILES := 4g_app.c ch32v208_adl400.c
include $(KERNEL_ROOT)/compiler.mk

673
APP_Framework/Applications/connection_app/4g_app/ch32v208_adl400.c Normal file
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/**
* @file ch32v208_adl400.c
* @brief ch32v208 board gets data from Acrel-ADL400 electricity meter with rs485 bus,
* and then sends it to the server with 4G.
* @author Huo Yujia (huoyujia081@126.com)
* @version 1.0
* @date 2024-07-10
*/
#include <ModuleConfig.h>
#include <adapter.h>
#include <transform.h>
#define MAX_FRAME_SIZE 256 // 最大帧大小
#define MAX_BUFFER_SIZE 1024 * 2 // 最大缓冲区大小
#define RECEIVE_DATA_INTERVAL_MS 1000 * 60 * 2 // ADL400数据采集间隔时间，单位为毫秒
#define RESEND_COUNT 3 // 最大帧重发次数
#define RECONNECT_COUNT 5 // 最大连接次数
#define WATING_RESPONSE_MS 5000 // 等待响应时间，单位为毫秒
/**
* @brief 生成Modbus RTU请求帧中的CRC循环冗余码
* @param CRC_Ptr
* @param LEN 需要生成CRC冗余码的数据长度
* @return uint16_t 以小端顺序返回CRC循环冗余码
*/
static uint16_t generateCRC(uint8_t *CRC_Ptr, uint8_t LEN) {
uint16_t CRC_Value = 0;
uint8_t i = 0;
uint8_t j = 0;
CRC_Value = 0xffff;
for (i = 0; i < LEN; i++) // LEN为数组长度
{
CRC_Value ^= *(CRC_Ptr + i);
for (j = 0; j < 8; j++) {
if (CRC_Value & 0x00001)
CRC_Value = (CRC_Value >> 1) ^ 0xA001;
else
CRC_Value = (CRC_Value >> 1);
}
}
CRC_Value = ((CRC_Value >> 8) + (CRC_Value << 8)); // 交换高低字节
return CRC_Value;
}
/**
* @brief 生成Modbus RTU请求帧，用于获取指定寄存器的值
* @param address 请求的Modbus地址
* @param functionCode 功能码
* @param startAddress 数据起始地址
* @param quantity 数据读取个数
* @param modbusRtuRequestFrame 生成的ModBus RTU请求帧数组
* @param requestFrameArrLength 生成的ModBus RTU请求帧数组长度，固定为8
* @return int 0表示生成成功，其他结果表示生成失败
* @note Modbus
* RTU请求帧格式：地址（1字节）+功能码（1字节）+数据起始地址（2字节）+数据读取个数（2字节）+校验码（2字节）
*/
static int generateRequestFrame(unsigned char address, unsigned char functionCode, unsigned short startAddress, unsigned short quantity,
unsigned char modbusRtuRequestFrame[], int requestFrameArrLength) {
if (requestFrameArrLength != 8) {
printf("the length of request frame array is not 8\n");
return -1;
}
modbusRtuRequestFrame[0] = address;
modbusRtuRequestFrame[1] = functionCode;
modbusRtuRequestFrame[2] = (startAddress >> 8) & 0xff;
modbusRtuRequestFrame[3] = startAddress & 0xff;
modbusRtuRequestFrame[4] = (quantity >> 8) & 0xff;
modbusRtuRequestFrame[5] = quantity & 0xff;
modbusRtuRequestFrame[6] = (generateCRC(modbusRtuRequestFrame, 6) >> 8) & 0xff;
modbusRtuRequestFrame[7] = generateCRC(modbusRtuRequestFrame, 6) & 0xff;
return 0;
}
/**
* @brief 将要上传服务器的数据帧
*/
struct DataFrame {
unsigned char id[13]; // 用响应的时间戳作为数据帧的id
unsigned char data[MAX_FRAME_SIZE]; // 上传服务器的数据帧字符串，前12字节表示数据帧id。字符串格式：数据帧id,数据1,数据2,数据3...
};
/**
* @brief Modbus RTU响应数据帧的缓存，使用循环队列作为数据结构
*/
struct QueueBuffer {
struct DataFrame *buffer[MAX_BUFFER_SIZE / sizeof(struct DataFrame)]; // 循环队列存储空间，使用数组存储
int front; // 循环队列队头
int rear; // 循环队列队尾
pthread_mutex_t mutex; // 互斥访问循环队列信号量
sem_t full; // 循环队列中有效成员个数的信号量
};
#define BUFFER_ELEM_COUNT (MAX_BUFFER_SIZE / sizeof(struct DataFrame)) // 循环队列中可以容纳的最大成员个数
/**
* @brief 初始化循环队列
* @param pQueueBuffer 循环队列指针
* @return * int 0表示初始化成功，其他表示初始化失败
*/
static int initBuffer(struct QueueBuffer *pQueueBuffer) {
pQueueBuffer->front = 0;
pQueueBuffer->rear = 0;
if (PrivMutexCreate(&pQueueBuffer->mutex, 0) < 0) {
printf("buffer mutex create failed.\n");
return -1;
}
if (PrivSemaphoreCreate(&pQueueBuffer->full, 0, 0) < 0) {
printf("buffer full semaphore create failed.\n");
return -1;
}
return 0;
}
/**
* @brief 循环队列入队，如果循环队列已满，则将最旧的成员出队后，新成员再入队
* @param pQueueBuffer 循环队列指针
* @param pDataFrame ADL400响应数据帧
* @return int 0表示入队成功，其他表示入队失败
*/
static int offerBuffer(struct QueueBuffer *pQueueBuffer, struct DataFrame *pDataFrame) {
/* 循环队列已满，将最旧的成员出队 */
if ((pQueueBuffer->rear + 1) % BUFFER_ELEM_COUNT == pQueueBuffer->front) {
struct DataFrame *frontDataFrame = pQueueBuffer->buffer[pQueueBuffer->front];
PrivFree(frontDataFrame);
pQueueBuffer->front = (pQueueBuffer->front + 1) % BUFFER_ELEM_COUNT;
}
/* 新成员入队 */
pQueueBuffer->buffer[pQueueBuffer->rear] = pDataFrame;
pQueueBuffer->rear = (pQueueBuffer->rear + 1) % BUFFER_ELEM_COUNT;
printf("front: %d\n", pQueueBuffer->front);
printf("rear: %d\n", pQueueBuffer->rear);
return 0;
}
/**
* @brief 循环队列出队，如果队列为空则返回NULL
* @param pQueueBuffer 循环队列指针
* @return struct DataFrame* 出队成员，如果队列为空则返回NULL
*/
static struct DataFrame *pollBuffer(struct QueueBuffer *pQueueBuffer) {
/* 队列为空，返回NULL */
if (pQueueBuffer->front == pQueueBuffer->rear) {
return NULL;
}
/* 最旧的成员出队 */
struct DataFrame *pFrontDataFrame = pQueueBuffer->buffer[pQueueBuffer->front];
pQueueBuffer->buffer[pQueueBuffer->front] = NULL;
pQueueBuffer->front = (pQueueBuffer->front + 1) % BUFFER_ELEM_COUNT;
printf("front: %d\n", pQueueBuffer->front);
printf("rear: %d\n", pQueueBuffer->rear);
return pFrontDataFrame;
}
/**
* @brief 查看队头元素，如果队列为空则返回NULL
* @param pQueueBuffer 循环队列指针
* @return struct DataFrame* 队头元素，如果队列为空则返回NULL
*/
static struct DataFrame *peekBuffer(struct QueueBuffer *pQueueBuffer) {
/* 如果队列为空，返回NULL */
if (pQueueBuffer->front == pQueueBuffer->rear) {
return NULL;
}
/* 返回队头元素，但不出队 */
return pQueueBuffer->buffer[pQueueBuffer->front];
}
/**
* @brief 改写PrivRead函数，原有函数只会读取接收缓冲区的当前已有字节，新函数会读取指定字节数再返回
* @param fd 文件描述符
* @param buf 数据读取到的位置
* @param len 读取的指定字节数
* @return int 如果读取到指定字节数返回0；如果到达WATING_RESPONSE_MS仍未读取到指定字节数，或者读数据错误，返回-1
*/
static int privReadEnoughData(int fd, void *buf, size_t len) {
char *buffer = (char *)buf; // 将接收的存储空间指针强制转型
int gottenBytes = 0; // 已经读取到的字节数
int remainTime = WATING_RESPONSE_MS; // 剩余的时间
/* 只有接收的字节数不够，并且还有剩余时间，才可以继续读取 */
while (gottenBytes < len && remainTime > 0) {
int bytes = PrivRead(fd, buffer + gottenBytes, len - gottenBytes); // 从设备读取
if (bytes > 0) {
gottenBytes += bytes; // 读取到字节
} else if (bytes < 0) {
printf("Error reading from serial port\n");
return -1; // 读取错误
}
PrivTaskDelay(100); // 每100ms读取一次
remainTime -= 100; // 剩余时间减去100ms
}
/* 若没有剩余时间，表示还没有读取到指定的字节数，返回-1；若有剩余时间，表示已经读取了指定的字节数，返回0 */
return remainTime < 0 ? -1 : 0;
}
/**
* @brief 解析ADL400响应的Modbus RTU数据帧
* @param modbusRtuResponseFrame0 请求数据后ADL400的响应帧
* @param modbusRtuResponseFrame1 请求时间戳后ADL400的响应帧
* @param modbusRtuResponseFrame2 请求电流电压比后ADL400的响应帧
* @param pDataFrame 将要上传给服务器的数据帧，包括id和数据
*/
static void parseModBusRtuResponseFrame(unsigned char *modbusRtuResponseFrame0, unsigned char *modbusRtuResponseFrame1,
unsigned char *modbusRtuResponseFrame2, struct DataFrame *pDataFrame) {
/* 从frame2中获取电压变比pt和电流变比ct */
unsigned char *p = modbusRtuResponseFrame2;
int pt = (unsigned short)modbusRtuResponseFrame2[3] << 8 | (unsigned short)modbusRtuResponseFrame2[4];
int ct = (unsigned short)modbusRtuResponseFrame2[5] << 8 | (unsigned short)modbusRtuResponseFrame2[6];
/* 从frame1中获取时间戳，即数据帧的id */
for (int i = 8; i >= 3; i--) {
sprintf(pDataFrame->id, "%s%02x", pDataFrame->id, modbusRtuResponseFrame1[i]);
sprintf(pDataFrame->data, "%s%02x", pDataFrame->data, modbusRtuResponseFrame1[i]);
}
/* 从frame0中获取要上传到服务器的ADL400的数据 */
for (int i = 3; i < modbusRtuResponseFrame0[2] + 3; i += 4) {
int originalData = (unsigned int)modbusRtuResponseFrame0[i] << 24 | (unsigned int)modbusRtuResponseFrame0[i + 1] << 16 |
(unsigned int)modbusRtuResponseFrame0[i + 2] << 8 | (unsigned int)modbusRtuResponseFrame0[i + 3];
sprintf(pDataFrame->data, "%s,%d", pDataFrame->data, originalData); // 将数据拼接到字符串
}
strcat(pDataFrame->data, "\n"); // 字符串末尾添加换行符，表示数据帧结束
}
/**
* @brief 从ADL400接收数据的线程
* @param arg 循环队列指针
* @return void* 目前返回值无意义
*/
static void *receiveDataFromADL400Task(void *arg) {
struct QueueBuffer *pQueueBuffer = (struct QueueBuffer *)arg; // 循环队列指针
int fd = PrivOpen("/dev/rs485_dev1", O_RDWR); // 打开设备文件
if (fd < 0) { // 打开设备文件失败，打印错误信息
printf("open rs485 fd error: %d\n", fd);
return NULL;
}
struct SerialDataCfg rs485Configuration;
memset(&rs485Configuration, 0, sizeof(struct SerialDataCfg));
/* 读取RS485配置信息 */
PrivMutexObtain(&romConfigurationMutex); // 若其他线程正在读取或者写入CFG，则阻塞等待
int baudRatesOption = CFG->baudRate_Rs485;
int dataBitsOption = CFG->dataBits_Rs485;
int stopBitsOption = CFG->stopBits_Rs485;
int parityOption = CFG->parity_Rs485;
PrivMutexAbandon(&romConfigurationMutex); // 释放互斥锁
switch (baudRatesOption) {
case 1:
rs485Configuration.serial_baud_rate = BAUD_RATE_2400;
break;
case 2:
rs485Configuration.serial_baud_rate = BAUD_RATE_4800;
break;
case 3:
rs485Configuration.serial_baud_rate = BAUD_RATE_9600;
break;
case 4:
rs485Configuration.serial_baud_rate = BAUD_RATE_19200;
break;
case 5:
rs485Configuration.serial_baud_rate = BAUD_RATE_38400;
break;
case 6:
rs485Configuration.serial_baud_rate = BAUD_RATE_57600;
break;
case 7:
rs485Configuration.serial_baud_rate = BAUD_RATE_115200;
break;
case 8:
rs485Configuration.serial_baud_rate = BAUD_RATE_230400;
break;
default:
rs485Configuration.serial_baud_rate = BAUD_RATE_9600;
break;
}
switch (dataBitsOption) {
case 1:
rs485Configuration.serial_data_bits = DATA_BITS_8;
break;
case 2:
rs485Configuration.serial_data_bits = DATA_BITS_9;
break;
default:
rs485Configuration.serial_data_bits = DATA_BITS_8;
break;
}
switch (stopBitsOption) {
case 1:
rs485Configuration.serial_stop_bits = STOP_BITS_1;
break;
case 2:
rs485Configuration.serial_stop_bits = STOP_BITS_2;
break;
default:
rs485Configuration.serial_stop_bits = STOP_BITS_1;
break;
}
switch (parityOption) {
case 1:
rs485Configuration.serial_parity_mode = PARITY_NONE;
break;
case 2:
rs485Configuration.serial_parity_mode = PARITY_ODD;
break;
case 3:
rs485Configuration.serial_parity_mode = PARITY_EVEN;
break;
}
struct PrivIoctlCfg ioctl_cfg;
ioctl_cfg.ioctl_driver_type = SERIAL_TYPE;
ioctl_cfg.args = (void *)&rs485Configuration;
if (0 != PrivIoctl(fd, OPE_INT, &ioctl_cfg)) {
printf("ioctl uart fd error %d\n", fd);
PrivClose(fd);
return NULL;
}
unsigned char modbusRtuRequestFrame[8]; // 定义Modbus RTU请求帧
unsigned char modBusRtuResponseFrame0[256]; // 定义Modbus RTU响应帧0
unsigned char modBusRtuResponseFrame1[256]; // 定义Modbus RTU响应帧1
unsigned char modBusRtuResponseFrame2[32]; // 定义Modbus RTU响应帧2
while (1) {
/* 生成Modbus RTU请求帧0，用于请求ADL400数据 */
if (generateRequestFrame(0x93, 0x03, 0x0000, 0x003C, modbusRtuRequestFrame, sizeof(modbusRtuRequestFrame)) < 0) {
break; // 生成请求帧失败，退出循环
}
PrivWrite(fd, modbusRtuRequestFrame, sizeof(modbusRtuRequestFrame)); // 发送Modbus RTU请求帧
/* 读取Modbus RTU响应帧0数据 */
if (privReadEnoughData(fd, modBusRtuResponseFrame0, 5 + (0x003C << 1)) < 0) {
printf("read data from adl400 time out\n"); // 读取超时，打印错误信息
break; // 读取失败，退出循环
}
/* 生成Modbus RTU请求帧1，用于请求时间戳 */
if (generateRequestFrame(0x93, 0x03, 0x003C, 0x0003, modbusRtuRequestFrame, sizeof(modbusRtuRequestFrame)) < 0) {
break; // 生成请求帧失败，退出循环
}
PrivWrite(fd, modbusRtuRequestFrame, sizeof(modbusRtuRequestFrame)); // 发送Modbus RTU请求帧
/* 读取Modbus RTU响应帧1数据 */
if (privReadEnoughData(fd, modBusRtuResponseFrame1, 5 + (0x0003 << 1)) < 0) {
printf("read data from adl400 time out\n"); // 读取超时，打印错误信息
break; // 读取失败，退出循环
}
/* 生成Modbus RTU请求帧2，用于请求电压电流变比 */
if (generateRequestFrame(0x93, 0x03, 0x008D, 0x0002, modbusRtuRequestFrame, sizeof(modbusRtuRequestFrame)) < 0) {
break; // 生成请求帧失败，退出循环
}
PrivWrite(fd, modbusRtuRequestFrame, sizeof(modbusRtuRequestFrame)); // 发送Modbus RTU请求帧
/* 读取Modbus RTU响应帧2 */
if (privReadEnoughData(fd, modBusRtuResponseFrame2, 5 + (0x0002 << 1)) < 0) {
printf("read data from adl400 time out\n"); // 读取超时，打印错误信息
break; // 读取失败，退出循环
}
/* 解析Modbus RTU响应帧 */
struct DataFrame *pDataFrame = (struct DataFrame *)PrivMalloc(sizeof(struct DataFrame));
memset(pDataFrame, 0, sizeof(struct DataFrame));
parseModBusRtuResponseFrame(modBusRtuResponseFrame0, modBusRtuResponseFrame1, modBusRtuResponseFrame2, pDataFrame);
/* 将解析后的数据帧放入循环队列 */
PrivMutexObtain(&pQueueBuffer->mutex); // 获取互斥锁
offerBuffer(pQueueBuffer, pDataFrame); // 将数据帧放入队列
printf("receive data from ADL400, id: %s\n", pDataFrame->id); // 打印接收到的数据帧ID
PrivMutexAbandon(&pQueueBuffer->mutex); // 释放互斥锁
PrivSemaphoreAbandon(&pQueueBuffer->full); // 释放信号量，即告知发送数据线程，队列中有新的数据帧
PrivTaskDelay(RECEIVE_DATA_INTERVAL_MS); // 延迟一段时间再读取下一帧数据
}
PrivClose(fd); // 关闭设备文件
return NULL;
}
/**
* @brief 通过4G向服务器发送数据的线程
* @param arg 循环队列指针
* @return void* 目前返回值无意义
*/
static void *sendDataToServerTask_4G(void *arg) {
uint8_t serverIpAddress[16] = {}; // 目的IP地址
uint8_t serverPort[6] = {}; // 目的端口号
struct QueueBuffer *pQueueBuffer = (struct QueueBuffer *)arg; // 循环队列指针
unsigned char receiveBuffer[256]; // 从服务器接收每帧响应的存储空间
struct Adapter *adapter = AdapterDeviceFindByName(ADAPTER_4G_NAME); // 查找4G模块适配器
AdapterDeviceOpen(adapter); // 打开适配器对应的设备（实际打开串口中断）
int baud_rate = BAUD_RATE_115200; // 波特率，用于设置4G模块串口
AdapterDeviceControl(adapter, OPE_INT, &baud_rate); // 对适配器对应设备进行配置（实际配置波特率）
struct DataFrame *pDataFrame = NULL; // 数据帧定义
while (1) {
PrivSemaphoreObtainWait(&pQueueBuffer->full, NULL); // 尝试获取循环队列队头元素，如果获取信号量失败，则等待信号量
#ifdef BSP_BLE_CONFIG // 如果启用了BLE配置功能
/* 获取互斥锁 */
PrivMutexObtain(&adapter->lock); // 若其他线程正在使用adapter，则阻塞等待
PrivMutexObtain(&romConfigurationMutex); // 若其他线程正在读取或者写入CFG，则阻塞等待
/* 尝试连接服务器 */
sprintf(serverIpAddress, "%u.%u.%u.%u", CFG->destinationIpAddress_4G[0], CFG->destinationIpAddress_4G[1],
CFG->destinationIpAddress_4G[2], CFG->destinationIpAddress_4G[3]);
sprintf(serverPort, "%u", (unsigned short)CFG->destinationPort_4G[0] | CFG->destinationPort_4G[1] << 8);
printf("-*-*-*-*sendDataToServerTask_4G*-*-*-*\n");
printf("serverIpAddress:\t%s\n", serverIpAddress);
printf("serverPort:\t\t%s\n", serverPort);
printf("-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\n");
if (CFG->mqttSwitch_4G == 1) { // 如果使能MQTT
AdapterDeviceMqttConnect(adapter, serverIpAddress, serverPort, CFG->mqttClientId_4G, CFG->mqttUsername_4G,
CFG->mqttPassword_4G);
} else { // 如果禁用MQTT
AdapterDeviceConnect(adapter, CLIENT, serverIpAddress, serverPort, IPV4);
}
AdapterDeviceNetstat(adapter); // 读取网络连接状态
/* 若连接失败，则等待10s再次尝试连接 */
if (CFG->mqttSwitch_4G == 0 && !adapter->network_info.is_connected ||
CFG->mqttSwitch_4G == 1 && !adapter->network_info.mqttIsConnected) {
PrivSemaphoreAbandon(&pQueueBuffer->full); // 释放信号量
/* 释放互斥锁 */
PrivMutexAbandon(&romConfigurationMutex);
PrivMutexAbandon(&adapter->lock);
printf("4G connect to server failed\n"); // 连接失败，打印错误信息
PrivTaskDelay(1000 * 10); // 延迟10秒，避免网络拥塞
continue;
}
#else // 如果没有启用BLE配置功能
/* 尝试连接到服务器 */
sprintf(serverIpAddress, "%u.%u.%u.%u", CFG->destinationIpAddress_4G[0], CFG->destinationIpAddress_4G[1],
CFG->destinationIpAddress_4G[2], CFG->destinationIpAddress_4G[3]);
sprintf(serverPort, "%u", (unsigned short)CFG->destinationPort_4G[0] | CFG->destinationPort_4G[1] << 8);
printf("-*-*-*-*sendDataToServerTask_4G*-*-*-*\n");
printf("serverIpAddress:\t%s\n", serverIpAddress);
printf("serverPort:\t\t%s\n", serverPort);
printf("-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\n");
int reconnectCount = RECONNECT_COUNT; // 尝试重新连接服务器最多RECONNECT_COUNT次
while (reconnectCount > 0) {
int res;
if (CFG->mqttSwitch_4G == 1) {
res = AdapterDeviceMqttConnect(adapter, mqttServerIp, mqttServerPort, CFG->mqttClientId_4G, CFG->mqttUsername_4G,
CFG->mqttPassword_4G);
} else {
res = AdapterDeviceConnect(adapter, CLIENT, serverIpAddress, serverPort, IPV4);
}
if (res == 0) {
break;
}
reconnectCount--;
}
if (reconnectCount <= 0) { // 若RECONNECT_COUNT次都连接失败，则等待10s再次尝试连接
PrivSemaphoreAbandon(&pQueueBuffer->full); // 释放信号量
printf("4G connect to server failed\n"); // 连接失败，打印错误信息
PrivTaskDelay(1000 * 10); // 延迟10秒，避免网络拥塞
continue;
}
#endif
PrivMutexObtain(&pQueueBuffer->mutex); // 获取互斥锁
pDataFrame = pollBuffer(pQueueBuffer); // 从队列中获取数据帧
PrivMutexAbandon(&pQueueBuffer->mutex); // 释放互斥锁
int resendCount = RESEND_COUNT; // 定义数据帧重发次数
while (pDataFrame != NULL && resendCount > 0) { // 只有数据帧非空并且还有剩余重发次数，才进行发送
/* 向服务器发送数据 */
printf("pDataFrame->data: %s", pDataFrame->data);
printf("send data to server, id: %s\n", pDataFrame->id);
if (CFG->mqttSwitch_4G == 1) { // MQTT模式下，无需服务器响应数据
AdapterDeviceMqttSend(adapter, CFG->mqttTopic_4G, pDataFrame->data,
strlen(pDataFrame->data)); // 发送数据，注意当前最多发送256字节
break;
} else {
AdapterDeviceSend(adapter, pDataFrame->data,
strlen(pDataFrame->data)); // 发送数据，注意当前最多发送256字节
/* 从服务器接收响应，约定服务器接收完数据帧后，返回数据帧中的前12个字节，即数据帧id */
/* 多读取2字节，是为了防止前面还有命令模式返回的剩余的\r\n影响判断 */
memset(receiveBuffer, 0, sizeof(receiveBuffer));
int receiveLength = AdapterDeviceRecv(adapter, receiveBuffer, strlen(pDataFrame->id) + 2);
if (receiveLength == strlen(pDataFrame->id) + 2 || receiveLength == strlen(pDataFrame->id)) {
/* 打印服务器响应 */
printf("receiveLength: %d\n", receiveLength);
printf("receiveBuffer: ");
for (int i = 0; i < receiveLength; i++) {
printf("%c", receiveBuffer[i]);
}
printf("\n");
/* 比较服务器响应的内容与发送的数据帧id是否一致 */
if (strstr(receiveBuffer, pDataFrame->id) != NULL) {
break; // 接收成功，退出循环
}
} else {
printf("receiveLength: %d\n", receiveLength);
printf("receiveBuffer: ");
for (int i = 0; i < receiveLength; i++) {
printf("%d ", receiveBuffer[i]);
}
printf("\n");
}
}
resendCount--;
}
if (pDataFrame != NULL) {
PrivFree(pDataFrame); // 释放数据帧内存
pDataFrame = NULL; // 避免野指针
}
// AdapterDeviceDisconnect(adapter, NULL); // 关闭适配器对应的设备
#ifdef BSP_BLE_CONFIG
/* 释放互斥锁 */
PrivMutexAbandon(&romConfigurationMutex);
PrivMutexAbandon(&adapter->lock);
#endif
if (resendCount <= 0) { // 如果数据帧重发次数超过上限，表示发送失败，丢弃该帧
PrivTaskDelay(1000 * 10); // 延迟10秒，避免网络拥塞
}
}
return NULL;
}
/**
* @brief 通过以太网向服务器发送数据的线程
* @param arg 循环队列指针
* @return void* 目前返回值无意义
*/
static void *sendDataToServerTask_Ethernet(void *arg) {
uint8_t serverIpAddress[16] = {}; // 目的IP地址
uint8_t serverPort[6] = {}; // 目的端口号
struct QueueBuffer *pQueueBuffer = (struct QueueBuffer *)arg; // 循环队列指针
unsigned char receiveBuffer[256]; // 从服务器接收每帧响应的存储空间
struct Adapter *adapter = AdapterDeviceFindByName(ADAPTER_ETHERNET_NAME); // 查找以太网模块适配器
#ifndef BSP_BLE_CONFIG // 如果没有使能蓝牙配置功能
AdapterDeviceSetUp(adapter); // 启动以太网主任务线程
AdapterDeviceSetDhcp(adapter, CFG->dhcpSwitch_Ethernet); // 启用或禁用DHCP
#endif
struct DataFrame *pDataFrame = NULL; // 数据帧定义
while (1) {
PrivSemaphoreObtainWait(&pQueueBuffer->full, NULL); // 尝试获取循环队列队头元素，如果获取信号量失败，则等待信号量
#ifdef BSP_BLE_CONFIG // 使能蓝牙配置功能
/* 获取互斥锁 */
PrivMutexObtain(&adapter->lock); // 若其他线程正在使用adapter，则阻塞等待
PrivMutexObtain(&romConfigurationMutex); // 若其他线程正在读取或者写入CFG，则阻塞等待;
/* 尝试连接服务器 */
sprintf(serverIpAddress, "%u.%u.%u.%u", CFG->destinationIpAddress_Ethernet[0], CFG->destinationIpAddress_Ethernet[1],
CFG->destinationIpAddress_Ethernet[2], CFG->destinationIpAddress_Ethernet[3]);
sprintf(serverPort, "%u", (unsigned short)CFG->destinationPort_Ethernet[0] | CFG->destinationPort_Ethernet[1] << 8);
printf("-*-*-*-*sendDataToServerTask_Ethernet*-*-*-*\n");
printf("serverIpAddress:\t%s\n", serverIpAddress);
printf("serverPort:\t\t%s\n", serverPort);
printf("-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\n");
int res = AdapterDeviceConnect(adapter, CLIENT, serverIpAddress, serverPort, IPV4);
/* 连接失败，则等待10s再次尝试连接 */
if (res != 0 && res != 0x1D) {
PrivSemaphoreAbandon(&pQueueBuffer->full); // 释放信号量
/* 释放互斥锁 */
PrivMutexAbandon(&romConfigurationMutex);
PrivMutexAbandon(&adapter->lock);
printf("Ethernet connect to server failed\n"); // 连接失败，打印错误信息
PrivTaskDelay(1000 * 10); // 延迟10秒，避免网络拥塞
continue;
}
#else
/* 尝试连接到服务器 */
sprintf(serverIpAddress, "%u.%u.%u.%u", CFG->destinationIpAddress_Ethernet[0], CFG->destinationIpAddress_Ethernet[1],
CFG->destinationIpAddress_Ethernet[2], CFG->destinationIpAddress_Ethernet[3]);
sprintf(serverPort, "%u", (unsigned short)CFG->destinationPort_Ethernet[0] | CFG->destinationPort_Ethernet[1] << 8);
printf("-*-*-*-*sendDataToServerTask_Ethernet*-*-*-*\n");
printf("serverIpAddress:\t%s\n", serverIpAddress);
printf("serverPort:\t\t%s\n", serverPort);
printf("-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\n");
int reconnectCount = RECONNECT_COUNT; // 尝试重新连接服务器最多RECONNECT_COUNT次
while (reconnectCount > 0) {
int res = AdapterDeviceConnect(adapter, CLIENT, serverIpAddress, serverPort, IPV4); // 尝试连接服务器
if (res == 0 || res == 0x1D) {
break;
}
reconnectCount--;
}
if (reconnectCount <= 0) { // 若RECONNECT_COUNT次都连接失败，则等待10s再次尝试连接
PrivSemaphoreAbandon(&pQueueBuffer->full); // 释放信号量
printf("Ethernet connect to server failed\n"); // 连接失败，打印错误信息
PrivTaskDelay(1000 * 10); // 延迟10秒，避免网络拥塞
continue;
}
#endif
PrivMutexObtain(&pQueueBuffer->mutex); // 获取互斥锁
pDataFrame = pollBuffer(pQueueBuffer); // 从队列中获取数据帧
PrivMutexAbandon(&pQueueBuffer->mutex); // 释放互斥锁
int resendCount = RESEND_COUNT; // 定义数据帧重发次数
/* 只有数据帧非空并且还有剩余重发次数，才进行发送 */
while (pDataFrame != NULL && resendCount > 0) {
/* 向服务器发送数据 */
printf("send data to server, id: %s\n", pDataFrame->id);
printf("pDataFrame->data: %s", pDataFrame->data);
AdapterDeviceSend(adapter, pDataFrame->data,
strlen(pDataFrame->data)); // 发送数据，注意当前最多发送256字节
/* 从服务器接收响应，约定服务器接收完数据帧后，返回数据帧中的前12个字节，即数据帧id */
memset(receiveBuffer, 0, sizeof(receiveBuffer));
PrivTaskDelay(6000);
if (AdapterDeviceRecv(adapter, receiveBuffer, strlen(pDataFrame->id)) == strlen(pDataFrame->id)) {
/* 打印服务器响应 */
printf("receiveBuffer: ");
for (int i = 0; i < strlen(receiveBuffer); i++) {
printf("%c", receiveBuffer[i]);
}
printf("\n");
/* 比较服务器响应的内容与发送的数据帧id是否一致 */
if (strstr(pDataFrame->id, receiveBuffer) != NULL) {
break; // 接收成功，退出循环
}
}
resendCount--;
}
if (pDataFrame != NULL) {
PrivFree(pDataFrame); // 释放数据帧内存
pDataFrame = NULL; // 避免野指针
}
AdapterDeviceDisconnect(adapter, NULL);
#ifdef BSP_BLE_CONFIG
/* 释放互斥锁 */
PrivMutexAbandon(&romConfigurationMutex);
PrivMutexAbandon(&adapter->lock);
#endif
if (resendCount <= 0) { // 如果数据帧重发次数超过上限，表示发送失败，丢弃该帧
PrivTaskDelay(1000 * 10); // 延迟10秒，避免网络拥塞
}
}
return NULL;
}
/**
* @brief 开启从ADL400接收数据的线程以及上传数据到服务器的线程，此方法在main方法中被调用，开机或复位启动
*/
void startUpTransformDataTask(void) {
/* 分配循环队列空间 */
struct QueueBuffer *pQueueBuffer = (struct QueueBuffer *)PrivCalloc(1, sizeof(struct QueueBuffer));
if (initBuffer(pQueueBuffer) < 0) {
PrivFree(pQueueBuffer);
return;
}
/* 启动从ADL400接收数据的线程 */
pthread_attr_t receiveDataFromADL400TaskAttr;
pthread_args_t receiveDataFromADL400TaskArgs;
receiveDataFromADL400TaskAttr.schedparam.sched_priority = 16; // 线程优先级
receiveDataFromADL400TaskAttr.stacksize = 2048; // 线程栈大小
receiveDataFromADL400TaskArgs.pthread_name = "receiveDataFromADL400Task"; // 线程名字
receiveDataFromADL400TaskArgs.arg = pQueueBuffer; // 线程参数
pthread_t receiveDataThread; // 线程ID
PrivTaskCreate(&receiveDataThread, &receiveDataFromADL400TaskAttr, receiveDataFromADL400Task, &receiveDataFromADL400TaskArgs);
PrivTaskStartup(&receiveDataThread);
/* 启动上传数据到服务器的线程 */
pthread_attr_t sendDataToServerTaskAttr;
pthread_args_t sendDataToServerTaskArgs;
sendDataToServerTaskAttr.schedparam.sched_priority = 16; // 线程优先级
sendDataToServerTaskAttr.stacksize = 2200; // 线程栈大小
sendDataToServerTaskArgs.pthread_name = "sendDataToServerTask"; // 线程名字
sendDataToServerTaskArgs.arg = pQueueBuffer; // 线程参数
pthread_t sendDataThread; // 线程ID
void *(*start_routine)(void *) = sendDataToServerTask_4G; // 通过4G模块上传到服务器
// void *(*start_routine)(void *) = sendDataToServerTask_Ethernet; // 通过以太网模块上传到服务器
PrivTaskCreate(&sendDataThread, &sendDataToServerTaskAttr, start_routine, &sendDataToServerTaskArgs); // 通过4G模块上传到服务器
PrivTaskStartup(&sendDataThread);
}

8
APP_Framework/Framework/connection/4g/Kconfig
View File

@ -13,3 +13,11 @@ config ADAPTER_EC200A
if ADAPTER_EC200A
source "$APP_DIR/Framework/connection/4g/ec200a/Kconfig"
endif
config ADAPTER_GM800TF
bool "Using 4G adapter device GM800TF"
default n
if ADAPTER_GM800TF
source "$APP_DIR/Framework/connection/4g/gm800tf/Kconfig"
endif

4
APP_Framework/Framework/connection/4g/Makefile
View File

@ -17,5 +17,9 @@ ifeq ($(CONFIG_ADD_XIZI_FEATURES),y)
SRC_DIR += ec200a
endif
ifeq ($(CONFIG_ADAPTER_GM800TF),y)
SRC_DIR += gm800tf
endif
include $(KERNEL_ROOT)/compiler.mk
endif

118
APP_Framework/Framework/connection/4g/adapter_4g.c
View File

@ -28,6 +28,10 @@ extern AdapterProductInfoType Ec200tAttach(struct Adapter *adapter);
extern AdapterProductInfoType Ec200aAttach(struct Adapter *adapter);
#endif
#ifdef ADAPTER_GM800TF
extern AdapterProductInfoType Gm800tfAttach(struct Adapter *adapter);
#endif
static int Adapter4GRegister(struct Adapter *adapter)
{
int ret = 0;
@ -92,6 +96,20 @@ int Adapter4GInit(void)
adapter->info = product_info;
adapter->done = product_info->model_done;
#endif
#ifdef ADAPTER_GM800TF
AdapterProductInfoType product_info = Gm800tfAttach(adapter);
if (!product_info) {
printf("Adapter4GInit gm800tf attach error\n");
PrivFree(adapter);
return -1;
}
adapter->product_info_flag = 1;
adapter->info = product_info;
adapter->done = product_info->model_done;
#endif
return ret;
@ -164,6 +182,106 @@ int Adapter4GTest(void)
}
#endif
#ifdef ADAPTER_GM800TF
uint8 server_addr[64] = "115.238.53.59";
uint8 server_port[64] = "10208";
adapter->socket.socket_id = 0;
AdapterDeviceOpen(adapter);
AdapterDeviceControl(adapter, OPE_INT, &baud_rate);
AdapterDeviceConnect(adapter, CLIENT, server_addr, server_port, IPV4);
// AdapterDeviceDisconnect(adapter, NULL);
// AdapterDeviceConnect(adapter, CLIENT, server_addr, server_port, IPV4);
AdapterDeviceNetstat(adapter);
// char sendData[15] = "Hello World!";
char sendData = 'a';
char receiveData = 0;
int failCount = 0;
for (int i = 0; i < 1024; i++) { // send 1kB data
AdapterDeviceSend(adapter, &sendData, 1);
sendData = sendData + 1 > 'z' ? 'a' : sendData + 1;
}
// AdapterDeviceSend(adapter, sendData, 13);
// while (1) {
// // if (sendData > 'z') {
// // break;
// // }
// AdapterDeviceSend(adapter, &sendData, 1);
// sendData = sendData + 1 > 'z' ? 'a' : sendData + 1;
// // int ret = AdapterDeviceRecv(adapter, &receiveData, 1);
// // printf("receiveData: %d\n", receiveData);
// // if (ret >= 0 && receiveData == sendData) {
// // sendData = sendData + 1 > 'z' ? 'a' : sendData + 1;
// // failCount = 0;
// // } else {
// // failCount++;
// // if (failCount >= 10) {
// // AdapterDeviceConnect(adapter, CLIENT, server_addr, server_port, IPV4);
// // failCount = 0;
// // }
// // }
// // printf("4G recv msg %c\n", receiveData);
// // receiveData = 0;
// }
// PrivTaskDelay(10000);
AdapterDeviceClose(adapter);
#endif
return 0;
}
PRIV_SHELL_CMD_FUNCTION(Adapter4GTest, a EC200T or EC200A adapter sample, PRIV_SHELL_CMD_FUNC_ATTR);
#ifdef ADAPTER_GM800TF
// unsigned char data[1024 * 40];
void *uploadDataTask(void *param) {
int baud_rate = BAUD_RATE_115200;
struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_4G_NAME);
int reconnectLimit = 3; // try reconnect to server up to 3 times
uint8 server_addr[64] = "115.238.53.59";
uint8 server_port[64] = "10208";
adapter->socket.socket_id = 0;
AdapterDeviceOpen(adapter);
AdapterDeviceControl(adapter, OPE_INT, &baud_rate);
/* try to connect to server */
do {
AdapterDeviceConnect(adapter, CLIENT, server_addr, server_port, IPV4);
AdapterDeviceNetstat(adapter);
if (adapter->network_info.is_connected && adapter->network_info.signal_strength < 99) {
break;
}
} while (--reconnectLimit > 0);
if (reconnectLimit <= 0) {
printf("4G connect to server failed\n");
AdapterDeviceClose(adapter);
return NULL;
}
/* send data to server */
char sendData[15] = "Hello World!";
AdapterDeviceSend(adapter, &sendData, 13);
// char sendData = 'a';
// char receiveData = 0;
// int failCount = 0;
// for (int i = 0; i < 1024; i++) { // send 1kB data
// AdapterDeviceSend(adapter, &sendData, 1);
// sendData = sendData + 1 > 'z' ? 'a' : sendData + 1;
// }
AdapterDeviceClose(adapter);
}
void startUploadDataTask(void) {
pthread_attr_t attr;
attr.schedparam.sched_priority = 20;
attr.stacksize = 8096;
// char task_name[] = "upload_data_task";
pthread_t thread;
PrivTaskCreate(&thread, &attr, uploadDataTask, NULL);
PrivTaskStartup(&thread);
}
#endif

21
APP_Framework/Framework/connection/4g/gm800tf/Kconfig Normal file
View File

@ -0,0 +1,21 @@
config ADAPTER_4G_GM800TF
string "GM800TF adapter name"
default "gm800tf"
if ADD_XIZI_FEATURES
config ADAPTER_GM800TF_DEV
string "GM800TF device path"
default "/dev/lte_dev1"
endif
if ADD_NUTTX_FEATURES
config ADAPTER_GM800TF_DEV
string "GM800TF device path"
default "/dev/ttyS8"
endif
if ADD_RTTHREAD_FEATURES
config ADAPTER_GM800TF_DEV
string "GM800TF device path"
default "/dev/usart8"
endif

6
APP_Framework/Framework/connection/4g/gm800tf/Make.defs Normal file
View File

@ -0,0 +1,6 @@
############################################################################
# APP_Framework/Framework/connection/4g/gm800tf/Make.defs
############################################################################
ifneq ($(CONFIG_ADAPTER_4G_GM800TF),)
CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework/Framework/connection/4g/gm800tf
endif

14
APP_Framework/Framework/connection/4g/gm800tf/Makefile Normal file
View File

@ -0,0 +1,14 @@
include $(KERNEL_ROOT)/.config
ifeq ($(CONFIG_ADD_NUTTX_FEATURES),y)
include $(APPDIR)/Make.defs
CSRCS += gm800tf.c gm800tf_mqtt.c
include $(APPDIR)/Application.mk
endif
ifeq ($(CONFIG_ADD_XIZI_FEATURES),y)
SRC_FILES := gm800tf.c gm800tf_mqtt.c
include $(KERNEL_ROOT)/compiler.mk
endif

10
APP_Framework/Framework/connection/4g/gm800tf/SConscript Normal file
View File

@ -0,0 +1,10 @@
from building import *
import os
cwd = GetCurrentDir()
src = []
if GetDepend(['ADAPTER_GM800TF']):
src += ['gm800tf.c']
group = DefineGroup('connection 4g gm800tf', src, depend = [], CPPPATH = [cwd])
Return('group')

639
APP_Framework/Framework/connection/4g/gm800tf/gm800tf.c Normal file
View File

@ -0,0 +1,639 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file gm800tf.c
* @brief Implement the connection 4G adapter function, using GM800TF device
* @author Huo Yujia (huoyujia081@126.com)
* @version 1.0
* @date 2024-07-05
*/
#include <adapter.h>
#include <at_agent.h>
#define GM800TF_AT_MODE_CMD "+++"
#define GM800TF_GET_ICCID_CMD "AT+ICCID\r\n"
#define GM800TF_SETUP_SOCKET_CMD "AT+SOCK%c=TCP,%s,%s\r\n"
#define GM800TF_OPEN_SOCKET_CMD "AT+SOCK%cEN=ON\r\n"
#define GM800TF_CLOSE_SOCKET_CMD "AT+SOCK%cEN=OFF\r\n"
#define GM800TF_SET_WKMOD_NET_CMD "AT+WKMOD=NET\r\n"
#define GM800TF_GET_WKMOD_CMD "AT+WKMOD?\r\n"
#define GM800TF_SAVE_CFG_CMD "AT+S\r\n"
#define GM800TF_GET_CSQ_CMD "AT+CSQ\r\n"
#define GM800TF_ENTM_MODE_CMD "AT+ENTM\r\n"
#define GM800TF_GET_SOCKET_PARAM_CMD "AT+SOCK%c?\r\n"
#define GM800TF_GET_SOCKET_STATUS_CMD "AT+SOCK%cLK\r\n"
#define GM800TF_RESET_CMD "AT+CLEAR\r\n"
#define GM800TF_SET_HEART_CMD "AT+HEARTEN=%s\r\n"
#define GM800TF_SET_HEART_DATA_CMD "AT+HEARTDT=%s\r\n"
#define GM800TF_SET_HEART_TIME_CMD "AT+HEARTTM=%d\r\n"
#define GM800TF_GET_MQTT_STATUS_CMD "AT+MQTTSTA?\r\n"
#define GM800TF_GET_MQTT_SERVER_CMD "AT+MQTTSVR?\r\n"
#define GM800TF_GET_MQTT_CLIENTID_CMD "AT+MQTTCID?\r\n"
#define GM800TF_GET_MQTT_USERNAME_CMD "AT+MQTTUSER?\r\n"
#define GM800TF_GET_MQTT_PASSWORD_CMD "AT+MQTTPSW?\r\n"
#define GM800TF_OK_REPLY "OK"
#define GM800TF_READY_REPLY "READY"
#define GM800TF_CREG_REPLY ",1"
#define GM800TF_CONNECT_REPLY "CONNECT"
#define TRY_TIMES 10
/**
* @brief convert string to corresponding hex string
* @param input original string
* @param output hex string
*/
void string_to_hex(const char *input, char *output) {
while (*input) {
sprintf(output, "%02X", (unsigned char)*input);
input++;
output += 2;
}
*output = '\0'; // Null-terminate the output string
}
/**
* @brief enter the configuration mode
* @param adapter
* @return int
*/
int Gm800tfEnterAtMode(struct Adapter *adapter) {
AtSetReplyEndChar(adapter->agent, 'o', 'k');
AtSetReplyCharNum(adapter->agent, 256);
AtSetReplyLrEnd(adapter->agent, 1);
ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "+++");
PrivTaskDelay(500);
ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "a");
PrivTaskDelay(100);
ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "\r\n"); // clear the "+++a", confirm it will not be added to the following command.
PrivTaskDelay(500);
return 0;
}
/**
* @brief open the GM800TF(aka. init the serial) and init the AT agent
* @param adapter
* @return int
*/
static int Gm800tfOpen(struct Adapter *adapter) {
/*step1: open gm800tf serial port*/
adapter->fd = PrivOpen(ADAPTER_GM800TF_DEV, O_RDWR);
if (adapter->fd < 0) {
printf("Gm800tfOpen get serial %s fd error\n", ADAPTER_GM800TF_DEV);
return -1;
}
/*step2: init AT agent*/
if (!adapter->agent) {
char *agent_name = "4G_uart_client";
if (0 != InitATAgent(agent_name, adapter->fd, 256)) {
printf("at agent init failed !\n");
return -1;
}
ATAgentType at_agent = GetATAgent(agent_name);
adapter->agent = at_agent;
}
/* step3: reset gm800tf */
ADAPTER_DEBUG("Gm800tf reseting configuration\n");
Gm800tfEnterAtMode(adapter);
AtSetReplyEndChar(adapter->agent, 'O', 'K');
AtSetReplyCharNum(adapter->agent, 256);
AtSetReplyLrEnd(adapter->agent, 0);
ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+CLEAR\r\n");
PrivTaskDelay(15000); // after reset configuration, wait at least 10s for restarting
/* step4: communication from sockA channel only*/
adapter->socket.socket_id = 0;
ADAPTER_DEBUG("Gm800tf open done\n");
return 0;
}
/**
* @brief close the GM800TF(aka. disable the interrupt) and disconnect the socket
* @param adapter
* @return int
*/
static int Gm800tfClose(struct Adapter *adapter) {
int ret = 0;
uint8_t gm800tf_cmd[64];
if (!adapter->agent) {
printf("Gm800tfClose AT agent NULL\n");
return -1;
}
AtSetReplyEndChar(adapter->agent, 0x4F, 0x4B); //'O', 'K'
/*step1: serial write "+++", quit transparent mode*/
ret = Gm800tfEnterAtMode(adapter);
if (ret < 0) {
goto out;
}
/*step2: serial write "AT+SOCKAEN=OFF" or "AT+SOCKBEN=OFF", close socket connect before open socket*/
memset(gm800tf_cmd, 0, sizeof(gm800tf_cmd));
sprintf(gm800tf_cmd, GM800TF_CLOSE_SOCKET_CMD, 'A' + adapter->socket.socket_id);
ret = AtCmdConfigAndCheck(adapter->agent, gm800tf_cmd, GM800TF_OK_REPLY);
if (ret < 0) {
goto out;
}
/*step3: serial write "AT+S", save configuration and restart 4G module*/
ret = AtCmdConfigAndCheck(adapter->agent, GM800TF_SAVE_CFG_CMD, GM800TF_OK_REPLY);
if (ret < 0) {
goto out;
}
PrivTaskDelay(15000); // after save configuration, wait at least 10s for restarting
out:
/*step4: close gm800tf serial port and delete ATAgentReceiveProcess*/
// DeleteATAgent(adapter->agent);
// adapter->agent = NULL;
PrivClose(adapter->fd);
return ret;
}
/**
* @brief config the serial and enable the interrupt
* @param adapter
* @param cmd
* @param args
* @return int
*/
static int Gm800tfIoctl(struct Adapter *adapter, int cmd, void *args) {
if (OPE_INT != cmd) {
printf("Gm800tfIoctl only support OPE_INT, do not support %d\n", cmd);
return -1;
}
uint32_t baud_rate = *((uint32_t *)args);
struct SerialDataCfg serial_cfg;
memset(&serial_cfg, 0, sizeof(struct SerialDataCfg));
serial_cfg.serial_baud_rate = baud_rate;
serial_cfg.serial_data_bits = DATA_BITS_8;
serial_cfg.serial_stop_bits = STOP_BITS_1;
serial_cfg.serial_buffer_size = SERIAL_RB_BUFSZ;
serial_cfg.serial_parity_mode = PARITY_NONE;
serial_cfg.serial_bit_order = STOP_BITS_1;
serial_cfg.serial_invert_mode = NRZ_NORMAL;
#ifdef TOOL_USING_OTA
serial_cfg.serial_timeout = OTA_RX_TIMEOUT;
#else
// serial receive timeout 10s
serial_cfg.serial_timeout = 100000;
#endif
serial_cfg.is_ext_uart = 0;
struct PrivIoctlCfg ioctl_cfg;
ioctl_cfg.ioctl_driver_type = SERIAL_TYPE;
ioctl_cfg.args = &serial_cfg;
PrivIoctl(adapter->fd, OPE_INT, &ioctl_cfg);
return 0;
}
/**
* @brief connect to the server
* @param adapter
* @param net_role
* @param ip
* @param port
* @param ip_type
* @return int
*/
static int Gm800tfConnect(struct Adapter *adapter, enum NetRoleType net_role, const char *ip, const char *port, enum IpType ip_type) {
int ret = 0;
int try = 0;
uint8_t gm800tf_cmd[64];
/*step0: compare ip and port with current configuration, and if they are the same there is no need to connect again*/
AdapterDeviceNetstat(adapter);
if (adapter->network_info.workMode == 1 && strcmp(adapter->network_info.ip_address, ip) == 0 &&
adapter->network_info.port == atoi(port) && adapter->network_info.is_connected && adapter->network_info.signal_strength < 99) {
return 0;
}
/*step1: serial write "+++" and "a", quit transparent mode*/
ret = Gm800tfEnterAtMode(adapter);
if (ret < 0) {
goto out;
}
AtSetReplyEndChar(adapter->agent, 'O', 'K');
AtSetReplyCharNum(adapter->agent, 256);
AtSetReplyLrEnd(adapter->agent, 0);
/*step2: serial write "AT+ICCID", get SIM ID*/
ret = AtCmdConfigAndCheck(adapter->agent, GM800TF_GET_ICCID_CMD, GM800TF_OK_REPLY);
if (ret < 0) {
goto out;
}
/*step3: serial write "AT+SOCKA=<protocol>,<address>,<port>" or "AT+SOCKB=<protocol>,<address>,<port>", connect
* socket using TCP*/
memset(gm800tf_cmd, 0, sizeof(gm800tf_cmd));
sprintf(gm800tf_cmd, GM800TF_SETUP_SOCKET_CMD, 'A' + adapter->socket.socket_id, ip, port);
ret = AtCmdConfigAndCheck(adapter->agent, gm800tf_cmd, GM800TF_OK_REPLY);
if (ret < 0) {
goto out;
}
/*step4: serial write "AT+SOCKAEN=ON" or "AT+SOCKBEN=ON", connect socket using TCP*/
memset(gm800tf_cmd, 0, sizeof(gm800tf_cmd));
sprintf(gm800tf_cmd, GM800TF_OPEN_SOCKET_CMD, 'A' + adapter->socket.socket_id);
ret = AtCmdConfigAndCheck(adapter->agent, gm800tf_cmd, GM800TF_OK_REPLY);
if (ret < 0) {
goto out;
}
/* step5: set up the heartbeat */
// char *heartbeatData = "heartbeat test";
// int heartbeatTime = 30;
// char heartbeatDataHex[65] = {}; // 最多32个字符
// string_to_hex(heartbeatData, heartbeatDataHex);
// memset(gm800tf_cmd, 0, sizeof(gm800tf_cmd));
// sprintf(gm800tf_cmd, GM800TF_SET_HEART_CMD, "ON");
// ret = AtCmdConfigAndCheck(adapter->agent, gm800tf_cmd, GM800TF_OK_REPLY);
// if (ret < 0) {
// goto out;
// }
// memset(gm800tf_cmd, 0, sizeof(gm800tf_cmd));
// sprintf(gm800tf_cmd, GM800TF_SET_HEART_DATA_CMD, heartbeatDataHex);
// ret = AtCmdConfigAndCheck(adapter->agent, gm800tf_cmd, GM800TF_OK_REPLY);
// if (ret < 0) {
// goto out;
// }
// memset(gm800tf_cmd, 0, sizeof(gm800tf_cmd));
// sprintf(gm800tf_cmd, GM800TF_SET_HEART_TIME_CMD, heartbeatTime);
// ret = AtCmdConfigAndCheck(adapter->agent, gm800tf_cmd, GM800TF_OK_REPLY);
// if (ret < 0) {
// goto out;
// }
/* step5: set down the heartbeat */
memset(gm800tf_cmd, 0, sizeof(gm800tf_cmd));
sprintf(gm800tf_cmd, GM800TF_SET_HEART_CMD, "OFF");
ret = AtCmdConfigAndCheck(adapter->agent, gm800tf_cmd, GM800TF_OK_REPLY);
if (ret < 0) {
goto out;
}
/* step6: serial write "AT+WKMOD=NET", set the working mode to network transparent transmission mode */
ret = AtCmdConfigAndCheck(adapter->agent, GM800TF_SET_WKMOD_NET_CMD, GM800TF_OK_REPLY);
if (ret < 0) {
goto out;
}
/*step7: serial write "AT+S", save configuration and restart 4G module*/
ret = AtCmdConfigAndCheck(adapter->agent, GM800TF_SAVE_CFG_CMD, GM800TF_OK_REPLY);
if (ret < 0) {
goto out;
}
PrivTaskDelay(15000); // after save configuration, wait at least 10s for restarting
ADAPTER_DEBUG("Gm800tf connect TCP done\n");
return 0;
out:
ADAPTER_DEBUG("Gm800tf connect TCP failed.\n");
return -1;
}
/**
* @brief send the data to the server after connect to the server
* @param adapter
* @param buf
* @param len
* @return int
*/
static int Gm800tfSend(struct Adapter *adapter, const void *buf, size_t len) {
/* query for whether socket is connected successfully */
AdapterDeviceNetstat(adapter);
if (adapter->network_info.is_connected == 0) {
printf("[error %s %d]socket has not been connected, please call function AdapterDeviceConnect\n", __func__, __LINE__);
return -1;
}
/* send the buf data */
if (adapter->agent) {
EntmSend(adapter->agent, (const char *)buf, len);
} else {
printf("Gm800tfSend can not find agent\n");
}
return 0;
}
/**
* @brief receive the data from the server after connect to the server
* @param adapter
* @param buf
* @param len
* @return int
*/
static int Gm800tfRecv(struct Adapter *adapter, void *buf, size_t len) {
if (adapter->agent) {
return EntmRecv(adapter->agent, (char *)buf, len, 6);
} else {
printf("Gm800tfRecv can not find agent\n");
}
return -1;
}
/**
* @brief disconnect the server
* @param adapter
* @return int
*/
static int Gm800tfDisconnect(struct Adapter *adapter) {
int ret = 0;
uint8_t gm800tf_cmd[64];
/* query for whether socket is connected successfully */
AdapterDeviceNetstat(adapter);
if (adapter->network_info.is_connected == 0) {
printf("[error %s %d]socket has not been connected, please call function AdapterDeviceConnect\n", __func__, __LINE__);
return 0;
}
/*step1: serial write "+++", quit transparent mode*/
ret = Gm800tfEnterAtMode(adapter);
if (ret < 0) {
goto out;
}
AtSetReplyEndChar(adapter->agent, 'O', 'K');
AtSetReplyCharNum(adapter->agent, 256);
AtSetReplyLrEnd(adapter->agent, 0);
/*step2: serial write "AT+SOCKAEN=OFF" or "AT+SOCKBEN=OFF", close socket connect before open socket*/
memset(gm800tf_cmd, 0, sizeof(gm800tf_cmd));
sprintf(gm800tf_cmd, GM800TF_CLOSE_SOCKET_CMD, 'A' + adapter->socket.socket_id);
ret = AtCmdConfigAndCheck(adapter->agent, gm800tf_cmd, GM800TF_OK_REPLY);
if (ret < 0) {
goto out;
}
/*step3: serial write "AT+S", save configuration and restart 4G module*/
ret = AtCmdConfigAndCheck(adapter->agent, GM800TF_SAVE_CFG_CMD, GM800TF_OK_REPLY);
if (ret < 0) {
goto out;
}
PrivTaskDelay(15000); // after save configuration, wait at least 5s for restarting
ADAPTER_DEBUG("Gm800tf disconnect TCP done\n");
return 0;
out:
ADAPTER_DEBUG("Gm800tf disconnect TCP failed. \n");
return -1;
}
/**
* @brief query for the network status
* @param adapter
* @return int
*/
static int Gm800tfNetstat(struct Adapter *adapter) {
char result[96] = {0};
uint8_t gm800tf_cmd[64];
int ret = 0;
int try = 0;
/*step1: serial write "+++", quit transparent mode*/
ret = Gm800tfEnterAtMode(adapter);
if (ret < 0) {
goto out;
}
AtSetReplyEndChar(adapter->agent, 'O', 'K');
AtSetReplyCharNum(adapter->agent, 256);
AtSetReplyLrEnd(adapter->agent, 0);
/*step2: serial write "AT+ICCID", get SIM ID*/
ret = AtCmdConfigAndCheck(adapter->agent, GM800TF_GET_ICCID_CMD, GM800TF_OK_REPLY);
if (ret < 0) {
printf("[error %s %d]AT+ICCID failed, please check the SIM card\n", __func__, __LINE__);
goto out;
}
printf("-*-*-*-*-*-*-*Gm800tfNetstat*-*-*-*-*-*-*\n");
/*step3: serial write "AT+CSQ", get carrier type*/
memset(result, 0, sizeof(result));
ret = AtGetNetworkInfoReply(adapter->agent, GM800TF_GET_CSQ_CMD, result);
if (ret < 0) {
goto out;
}
if (sscanf(strstr(result, "+CSQ:"), "+CSQ: %d", &adapter->network_info.signal_strength) == 1) {
printf("signal strength:\t%d\n", adapter->network_info.signal_strength);
} else {
printf("Failed to parse signal strength\n");
goto out;
}
/*step4: serial write "AT+WKMOD?", get the current work mode*/
memset(result, 0, sizeof(result));
ret = AtGetNetworkInfoReply(adapter->agent, GM800TF_GET_WKMOD_CMD, result);
if (ret < 0) {
goto out;
}
char workMode[10] = {};
if (sscanf(strstr(result, "+WKMOD:"), "+WKMOD:%s", workMode) == 1) {
printf("work mode:\t\t%s\n", workMode);
if (strcmp(workMode, "NET") == 0) {
adapter->network_info.workMode = 1;
} else if (strcmp(workMode, "MQTT,NOR") == 0) {
adapter->network_info.workMode = 2;
} else {
adapter->network_info.workMode = 0;
}
} else {
printf("Failed to parse work mode\n");
goto out;
}
/*step5: serial write "AT+SOCKA=?", get the current server IP address*/
memset(gm800tf_cmd, 0, sizeof(gm800tf_cmd));
sprintf(gm800tf_cmd, GM800TF_GET_SOCKET_PARAM_CMD, 'A' + adapter->socket.socket_id);
ret = AtGetNetworkInfoReply(adapter->agent, gm800tf_cmd, result);
if (ret < 0) {
goto out;
}
if (sscanf(strstr(result, ",") + 1, "%15[^,],%hu", adapter->network_info.ip_address, &adapter->network_info.port) == 2) {
printf("server ip address:\t%s\n", adapter->network_info.ip_address);
printf("server port:\t\t%hu\n", adapter->network_info.port);
} else {
printf("server ip address:\t%s\n", adapter->network_info.ip_address);
printf("server port:\t\t%d\n", adapter->network_info.port);
printf("Failed to parse IP address and port\n");
goto out;
}
/*step6: serial write "AT+SOCKALK" or "AT+SOCKBLK", get socket status*/
memset(result, 0, sizeof(result));
sprintf(gm800tf_cmd, GM800TF_GET_SOCKET_STATUS_CMD, 'A' + adapter->socket.socket_id);
ret = AtGetNetworkInfoReply(adapter->agent, gm800tf_cmd, result);
if (ret < 0) {
goto out;
}
char socket_status[20] = {};
if (sscanf(strstr(result, "LK:"), "LK: %s", socket_status) == 1) {
printf("socket status:\t\t%s\n", socket_status);
adapter->network_info.is_connected = strcmp(socket_status, "Connected") == 0 ? 1 : 0;
} else {
printf("Failed to parse socket status\n");
goto out;
}
/*step7: serial write "AT+MQTTSVR=?", get the current mqtt server IP address and port*/
memset(result, 0, sizeof(result));
ret = AtGetNetworkInfoReply(adapter->agent, GM800TF_GET_MQTT_SERVER_CMD, result);
if (ret < 0) {
goto out;
}
if (sscanf(strstr(result, ":") + 1, "%15[^,],%hu", adapter->network_info.mqttServerIp, &adapter->network_info.mqttServerPort) == 2) {
printf("mqtt server ip address:\t%s\n", adapter->network_info.mqttServerIp);
printf("mqtt server port:\t%hu\n", adapter->network_info.mqttServerPort);
} else {
printf("mqtt server ip address:\t%s\n", adapter->network_info.mqttServerIp);
printf("mqtt server port:\t%d\n", adapter->network_info.mqttServerPort);
printf("Failed to parse IP address and port\n");
goto out;
}
/* step8: serial write "AT+MQTTCID=?", get the current mqtt client id*/
memset(result, 0, sizeof(result));
ret = AtGetNetworkInfoReply(adapter->agent, GM800TF_GET_MQTT_CLIENTID_CMD, result);
if (ret < 0) {
goto out;
}
if (sscanf(strstr(result, "MQTTCID:"), "MQTTCID:%s", adapter->network_info.mqttClientId) == 1) {
printf("mqtt clientid:\t\t%s\n", adapter->network_info.mqttClientId);
} else {
printf("Failed to parse mqtt clientid\n");
goto out;
}
/* step9: serial write "AT+MQTTUSER=?", get the current mqtt username*/
memset(result, 0, sizeof(result));
ret = AtGetNetworkInfoReply(adapter->agent, GM800TF_GET_MQTT_USERNAME_CMD, result);
if (ret < 0) {
goto out;
}
if (sscanf(strstr(result, "MQTTUSER:"), "MQTTUSER:%s", adapter->network_info.mqttUsername) == 1) {
printf("mqtt username:\t\t%s\n", adapter->network_info.mqttUsername);
} else {
printf("Failed to parse mqtt username\n");
goto out;
}
/* step10: serial write "AT+MQTTPSW?", get the current mqtt password */
memset(result, 0, sizeof(result));
ret = AtGetNetworkInfoReply(adapter->agent, GM800TF_GET_MQTT_PASSWORD_CMD, result);
if (ret < 0) {
goto out;
}
if (sscanf(strstr(result, "MQTTPSW:"), "MQTTPSW:%s", adapter->network_info.mqttPassword) == 1) {
printf("mqtt password:\t\t%s\n", adapter->network_info.mqttPassword);
} else {
printf("Failed to parse mqtt password\n");
goto out;
}
/*step11: serial write "AT+MQTTSTA", get the status of mqtt connection*/
memset(result, 0, sizeof(result));
ret = AtGetNetworkInfoReply(adapter->agent, GM800TF_GET_MQTT_STATUS_CMD, result);
if (ret < 0) {
goto out;
}
char mqtt_status[20] = {};
if (sscanf(strstr(result, "STA:"), "STA: %s", mqtt_status) == 1) {
printf("mqtt status:\t\t%s\n", mqtt_status);
adapter->network_info.mqttIsConnected = strcmp(mqtt_status, "\"CONNECTION\"") == 0 ? 1 : 0;
} else {
printf("Failed to parse mqtt status\n");
goto out;
}
/* step12: serial write "AT+ENTM", enter entm mode */
ret = AtCmdConfigAndCheck(adapter->agent, GM800TF_ENTM_MODE_CMD, GM800TF_OK_REPLY);
if (ret < 0) {
goto out;
}
printf("-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-\n");
return 0;
out:
printf("-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-\n");
ADAPTER_DEBUG("Gm800tf get netstat failed.\n");
return -1;
}
int Gm800tfMqttConnect(struct Adapter *adapter, const char *ip, const char *port, const char *client_id, const char *username,
const char *password);
int Gm800tfMqttDisconnect(struct Adapter *adapter);
int Gm800tfMqttSend(struct Adapter *adapter, const char *topic, const void *buf, size_t len);
int Gm800tfMqttRecv(struct Adapter *adapter, const char *topic, void *buf, size_t len);
static const struct IpProtocolDone gm800tf_done = {
.open = Gm800tfOpen,
.close = Gm800tfClose,
.ioctl = Gm800tfIoctl,
.setup = NULL,
.setdown = NULL,
.setaddr = NULL,
.setdns = NULL,
.setdhcp = NULL,
.ping = NULL,
.netstat = Gm800tfNetstat,
.connect = Gm800tfConnect,
.send = Gm800tfSend,
.recv = Gm800tfRecv,
.disconnect = Gm800tfDisconnect,
.mqttconnect = Gm800tfMqttConnect,
.mqttdisconnect = Gm800tfMqttDisconnect,
.mqttsend = Gm800tfMqttSend,
.mqttrecv = Gm800tfMqttRecv,
};
/**
* @brief expose the behavior of GM800TF to application
* @param adapter
* @return AdapterProductInfoType
*/
AdapterProductInfoType Gm800tfAttach(struct Adapter *adapter) {
struct AdapterProductInfo *product_info = PrivMalloc(sizeof(struct AdapterProductInfo));
if (!product_info) {
printf("Gm800tfAttach malloc product_info error\n");
PrivFree(product_info);
return NULL;
}
strcpy(product_info->model_name, ADAPTER_4G_GM800TF);
product_info->model_done = (void *)&gm800tf_done;
return product_info;
}

316
APP_Framework/Framework/connection/4g/gm800tf/gm800tf_mqtt.c Normal file
View File

@ -0,0 +1,316 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file gm800tf_mqtt.c
* @brief Implement the connection 4G adapter function about mqtt, using GM800TF device
* @author Huo Yujia (huoyujia081@126.com)
* @version 1.0
* @date 2024-07-26
*/
#include <adapter.h>
#include <at_agent.h>
#define GM800TF_GET_ICCID_CMD "AT+ICCID\r\n"
#define GM800TF_SET_WKMOD_MQTT_CMD "AT+WKMOD=MQTT,NOR\r\n"
#define GM800TF_SET_WKMOD_CMD_CMD "AT+WKMOD=CMD\r\n"
#define GM800TF_GET_MQTT_PUBPARAM_CMD "AT+MQTTPUBTP?\r\n"
#define GM800TF_SET_MQTT_PUBPARAM_CMD "AT+MQTTPUBTP=%d,%d,%s,%d,%d\r\n"
#define GM800TF_SET_MQTT_SUBPARAM_CMD "AT+MQTTSUBTP=%d,%d,%s,%d\r\n"
#define GM800TF_SET_MQTT_SERVER_CMD "AT+MQTTSVR=%s,%s\r\n"
#define GM800TF_SET_MQTT_USERNAME_CMD "AT+MQTTUSER=%s\r\n"
#define GM800TF_SET_MQTT_PASSWORD_CMD "AT+MQTTPSW=%s\r\n"
#define GM800TF_SET_MQTT_CLIID_CMD "AT+MQTTCID=%s\r\n"
#define GM800TF_SET_MQTT_MODE_CMD "AT+MQTTMOD=%d\r\n"
#define GM800TF_SET_HEART_DATA_CMD "AT+HEARTDT=%s\r\n"
#define GM800TF_SET_HEART_TIME_CMD "AT+HEARTTM=%d\r\n"
#define GM800TF_SAVE_CFG_CMD "AT+S\r\n"
#define GM800TF_ENTM_MODE_CMD "AT+ENTM\r\n"
#define GM800TF_OK_REPLY "OK"
#define GM800TF_READY_REPLY "READY"
#define GM800TF_CREG_REPLY ",1"
#define GM800TF_PUBEX_REPLY ">"
#define TRY_TIMES 10
int Gm800tfEnterAtMode(struct Adapter *adapter); // defined in gm800tf.c
/**
* @brief connect to mqtt server
* @param adapter
* @param ip mqtt server ip address
* @param port mqtt server port
* @param client_id mqtt client id
* @param username mqtt username
* @param password mqtt password
* @return int 0: success, -1: failed
*/
int Gm800tfMqttConnect(struct Adapter *adapter, const char *ip, const char *port, const char *client_id, const char *username,
const char *password) {
int ret = 0;
uint8_t gm800tf_cmd[64];
/*step0: compare ip and port with current configuration, and if they are the same there is no need to connect again*/
AdapterDeviceNetstat(adapter);
if (adapter->network_info.workMode == 2 && strcmp(adapter->network_info.mqttServerIp, ip) == 0 &&
adapter->network_info.mqttServerPort == atoi(port) && strcmp(adapter->network_info.mqttClientId, client_id) == 0 &&
strcmp(adapter->network_info.mqttUsername, username) == 0 && strcmp(adapter->network_info.mqttPassword, password) == 0 &&
adapter->network_info.mqttIsConnected && adapter->network_info.signal_strength < 99) {
return 0;
}
/*step1: serial write "+++" and "a", quit transparent mode*/
ret = Gm800tfEnterAtMode(adapter);
if (ret < 0) {
goto out;
}
AtSetReplyEndChar(adapter->agent, 'O', 'K');
AtSetReplyCharNum(adapter->agent, 256);
AtSetReplyLrEnd(adapter->agent, 0);
/*step2: serial write "AT+ICCID", get SIM ID*/
ret = AtCmdConfigAndCheck(adapter->agent, GM800TF_GET_ICCID_CMD, GM800TF_OK_REPLY);
if (ret < 0) {
goto out;
}
/*step3: serial write "AT+MQTTSVR=<server>,<port>", config mqtt ip and port*/
memset(gm800tf_cmd, 0, sizeof(gm800tf_cmd));
sprintf(gm800tf_cmd, GM800TF_SET_MQTT_SERVER_CMD, ip, port);
ret = AtCmdConfigAndCheck(adapter->agent, gm800tf_cmd, GM800TF_OK_REPLY);
if (ret < 0) {
goto out;
}
/*step4: serial write "AT+MQTTCID=<clientid>", config mqtt client id*/
memset(gm800tf_cmd, 0, sizeof(gm800tf_cmd));
sprintf(gm800tf_cmd, GM800TF_SET_MQTT_CLIID_CMD, client_id);
ret = AtCmdConfigAndCheck(adapter->agent, gm800tf_cmd, GM800TF_OK_REPLY);
if (ret < 0) {
goto out;
}
/*step5: serial write "AT+MQTTUSER=<username>", config mqtt username*/
memset(gm800tf_cmd, 0, sizeof(gm800tf_cmd));
sprintf(gm800tf_cmd, GM800TF_SET_MQTT_USERNAME_CMD, username);
ret = AtCmdConfigAndCheck(adapter->agent, gm800tf_cmd, GM800TF_OK_REPLY);
if (ret < 0) {
goto out;
}
/*step6: serial write "AT+MQTTPSW=<password>", config mqtt password*/
memset(gm800tf_cmd, 0, sizeof(gm800tf_cmd));
sprintf(gm800tf_cmd, GM800TF_SET_MQTT_PASSWORD_CMD, password);
ret = AtCmdConfigAndCheck(adapter->agent, gm800tf_cmd, GM800TF_OK_REPLY);
if (ret < 0) {
goto out;
}
/*step7: serial write "AT+WKMOD=MQTT", set the working mode to mqtt mode*/
ret = AtCmdConfigAndCheck(adapter->agent, GM800TF_SET_WKMOD_MQTT_CMD, GM800TF_OK_REPLY);
if (ret < 0) {
goto out;
}
/*step8: serial write "AT+MQTTMOD=<mode>, set the mqtt mode*/
/* mode-0: Send data to all preset enabled topics */
/* mode-1: Send data separately to a specific topic */
int mode = 1;
memset(gm800tf_cmd, 0, sizeof(gm800tf_cmd));
sprintf(gm800tf_cmd, GM800TF_SET_MQTT_MODE_CMD, mode);
ret = AtCmdConfigAndCheck(adapter->agent, gm800tf_cmd, GM800TF_OK_REPLY);
if (ret < 0) {
goto out;
}
/*step9: set the heartbeat parameter*/
char *heartbeatData = "heartbeat test";
int heartbeatTime = 30;
char heartbeatDataHex[65] = {}; // 最多32个字符
void string_to_hex(const char *input, char *output);
string_to_hex(heartbeatData, heartbeatDataHex);
memset(gm800tf_cmd, 0, sizeof(gm800tf_cmd));
sprintf(gm800tf_cmd, GM800TF_SET_HEART_DATA_CMD, heartbeatDataHex);
ret = AtCmdConfigAndCheck(adapter->agent, gm800tf_cmd, GM800TF_OK_REPLY);
if (ret < 0) {
goto out;
}
memset(gm800tf_cmd, 0, sizeof(gm800tf_cmd));
sprintf(gm800tf_cmd, GM800TF_SET_HEART_TIME_CMD, heartbeatTime);
ret = AtCmdConfigAndCheck(adapter->agent, gm800tf_cmd, GM800TF_OK_REPLY);
if (ret < 0) {
goto out;
}
/*step10: serial write "AT+S", save configuration and restart mqtt module*/
ret = AtCmdConfigAndCheck(adapter->agent, GM800TF_SAVE_CFG_CMD, GM800TF_OK_REPLY);
if (ret < 0) {
goto out;
}
PrivTaskDelay(20000); // after save configuration, wait at least 10s for restarting
ADAPTER_DEBUG("Gm800tf mqtt connect done\n");
return 0;
out:
ADAPTER_DEBUG("Gm800tf mqtt connect failed. Power down\n");
return -1;
}
/**
* @brief this function has no use
* @param adapter
* @return int
*/
int Gm800tfMqttDisconnect(struct Adapter *adapter) {
int ret = 0;
return 0;
}
/**
* @brief send data to mqtt server
* @param adapter
* @param topic mqtt publish topic
* @param buf data buffer to send to mqtt server
* @param len data length
* @return int 0: success; others: failed
*/
int Gm800tfMqttSend(struct Adapter *adapter, const char *topic, const void *buf, size_t len) {
/* query for whether socket is connected successfully */
AdapterDeviceNetstat(adapter);
if (adapter->network_info.mqttIsConnected == 0) {
printf("[error %s %d]socket has not been connected, please call function AdapterDeviceMqttConnect\n", __func__, __LINE__);
return -1;
}
int ret = 0;
char result[256] = {};
uint8_t gm800tf_cmd[64];
static const char *publishTopics[10] = {NULL}; // save the mqtt publish topics temporarily
static int topicIndex = 0; // the index next mqtt topic to be saved
/* step0: check if the topic in the topics array */
for (int i = 0; i < 10; i++) {
if (publishTopics[i] != NULL && strcmp(publishTopics[i], topic) == 0) {
char num[10];
sprintf(num, "%d,", i + 1);
EntmSend(adapter->agent, num, strlen(num));
EntmSend(adapter->agent, (const char *)buf, len);
return 0;
}
}
topicIndex = topicIndex >= 10 ? 0 : topicIndex;
publishTopics[topicIndex] = topic; // save the topic to the topics array
/* step1: serial send "+++" and "a", quit transparent mode */
ret = Gm800tfEnterAtMode(adapter);
if (ret < 0) {
goto out;
}
AtSetReplyEndChar(adapter->agent, 'O', 'K');
AtSetReplyCharNum(adapter->agent, 256);
AtSetReplyLrEnd(adapter->agent, 0);
/* step2: serial write "AT+MQTTPUBTP=<pubnum>,<puben>,<topic>,<qos>,<retained>", config the publish parameters */
memset(gm800tf_cmd, 0, sizeof(gm800tf_cmd));
sprintf(gm800tf_cmd, GM800TF_SET_MQTT_PUBPARAM_CMD, topicIndex + 1, 1, topic, 2, 0);
ret = AtCmdConfigAndCheck(adapter->agent, gm800tf_cmd, GM800TF_OK_REPLY);
if (ret < 0) {
goto out;
}
/* step3: serial write "AT+S", save the configuration and restart the module */
ret = AtCmdConfigAndCheck(adapter->agent, GM800TF_SAVE_CFG_CMD, GM800TF_OK_REPLY);
if (ret < 0) {
goto out;
}
PrivTaskDelay(15000); // after save configuration, wait at least 10s for restarting
/* step4: send the data to mqtt server */
char num[10];
sprintf(num, "%d,", topicIndex + 1);
EntmSend(adapter->agent, num, strlen(num));
EntmSend(adapter->agent, buf, len);
topicIndex++;
ADAPTER_DEBUG("Gm800tf mqtt send done\n");
return 0;
out:
ADAPTER_DEBUG("Gm800tf mqtt send failed.\n");
return -1;
}
/**
* @brief GM800TF only support transparent mode, so the topic is not used. The Message can't be diffrentiated by
* topic in the received data.
* @param adapter
* @param topic
* @param buf
* @param len
* @return int
* @note 该函数暂时未经过测试
*/
int Gm800tfMqttRecv(struct Adapter *adapter, const char *topic, void *buf, size_t len) {
int ret = 0;
static const char *subscribeTopics[10] = {NULL};
static int topicIndex = 0;
uint8_t gm800tf_cmd[64];
/* check if the topic in the topics array */
for (int i = 0; i < 10; i++) {
if (subscribeTopics[i] != NULL && strcmp(subscribeTopics[i], topic) == 0) {
if (adapter->agent) {
return EntmRecv(adapter->agent, (char *)buf, len, 6);
} else {
printf("Gm800tfRecv can not find agent\n");
return -1;
}
}
}
topicIndex = topicIndex >= 10 ? 0 : topicIndex;
subscribeTopics[topicIndex] = topic;
ret = Gm800tfEnterAtMode(adapter);
if (ret < 0) {
goto out;
}
AtSetReplyEndChar(adapter->agent, 'O', 'K');
AtSetReplyCharNum(adapter->agent, 256);
AtSetReplyLrEnd(adapter->agent, 0);
memset(gm800tf_cmd, 0, sizeof(gm800tf_cmd));
sprintf(gm800tf_cmd, GM800TF_SET_MQTT_SUBPARAM_CMD, topicIndex + 1, 1, topic, 2);
ret = AtCmdConfigAndCheck(adapter->agent, gm800tf_cmd, GM800TF_OK_REPLY);
if (ret < 0) {
goto out;
}
ret = AtCmdConfigAndCheck(adapter->agent, GM800TF_SAVE_CFG_CMD, GM800TF_OK_REPLY);
if (ret < 0) {
goto out;
}
PrivTaskDelay(15000); // after save configuration, wait at least 10s for restarting
if (adapter->agent) {
return EntmRecv(adapter->agent, (char *)buf, len, 6);
} else {
printf("Gm800tfRecv can not find agent\n");
}
out:
ADAPTER_DEBUG("Gm800tf mqtt receive failed.\n");
return -1;
}

12
APP_Framework/Framework/connection/adapter.h
View File

@ -129,6 +129,18 @@ struct NetworkInfo {
enum CarrierType carrier_type;
int signal_strength;
char ip_address[16];
#ifdef ADAPTER_GM800TF
unsigned char workMode; // 工作模式，1为NET，2为MQTT,NOR
unsigned short port; // 目的端口号
unsigned char is_connected; // SOCKET连接状态，0为失败，1为成功
unsigned char mqttSwitch; // MQTT开关
char mqttServerIp[16]; // MQTT目的IP地址
unsigned short mqttServerPort; // MQTT目的端口号
char mqttClientId[64]; // MQTT客户端ID
char mqttUsername[64]; // MQTT用户名
char mqttPassword[64]; // MQTT密码
unsigned char mqttIsConnected; // MQTT连接状态，0为失败，1为成功
#endif
};
struct AdapterData

299
APP_Framework/Framework/connection/adapter_agent.c
View File

@ -1,14 +1,14 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file xs_adapterAT_client.c
@ -18,7 +18,6 @@
* @date 2021.04.22
*/
#include <at_agent.h>
#include <adapter.h>
#include <stdbool.h>
@ -27,7 +26,7 @@
#include <stdlib.h>
#include <string.h>
#ifdef ADD_XIZI_FEATURES
# include <user_api.h>
#include <user_api.h>
#endif
#ifdef ADD_RTTHREAD_FEATURES
#include <rtthread.h>
@ -49,9 +48,11 @@ unsigned int IpTint(char *ipstr)
token = strtok(ipstr, ".");
while (token != NULL) {
while (token != NULL)
{
cur = atoi(token);
if (cur >= 0 && cur <= 255) {
if (cur >= 0 && cur <= 255)
{
total += cur * pow(256, i);
}
i--;
@ -65,8 +66,10 @@ void SwapStr(char *str, int begin, int end)
{
int i, j;
for (i = begin, j = end; i <= j; i++, j--) {
if (str[i] != str[j]) {
for (i = begin, j = end; i <= j; i++, j--)
{
if (str[i] != str[j])
{
str[i] = str[i] ^ str[j];
str[j] = str[i] ^ str[j];
str[i] = str[i] ^ str[j];
@ -83,7 +86,8 @@ char *IpTstr(unsigned int ipint)
char token[4];
int bt, ed, len, cur;
while (ipint) {
while (ipint)
{
cur = ipint % 256;
sprintf(token, "%d", cur);
strcat(new, token);
@ -95,8 +99,10 @@ char *IpTstr(unsigned int ipint)
len = strlen(new);
SwapStr(new, 0, len - 1);
for (bt = ed = 0; ed < len;) {
while (ed < len && new[ed] != '.') {
for (bt = ed = 0; ed < len;)
{
while (ed < len && new[ed] != '.')
{
ed++;
}
SwapStr(new, bt, ed - 1);
@ -125,14 +131,15 @@ void ATSprintf(int fd, const char *format, va_list params)
{
last_cmd_len = vsnprintf(send_buf, sizeof(send_buf), format, params);
#ifdef CONNECTION_FRAMEWORK_DEBUG
printf("AT send %s len %u\n",send_buf, last_cmd_len);
printf("AT send %s len %u\n", send_buf, last_cmd_len);
#endif
PrivWrite(fd, send_buf, last_cmd_len);
PrivWrite(fd, send_buf, last_cmd_len);
}
int ATOrderSend(ATAgentType agent, uint32_t timeout_s, ATReplyType reply, const char *cmd_expr, ...)
{
if (agent == NULL) {
if (agent == NULL)
{
printf("ATAgent is null");
return -1;
}
@ -158,19 +165,23 @@ int ATOrderSend(ATAgentType agent, uint32_t timeout_s, ATReplyType reply, const
agent->reply = reply;
PrivMutexAbandon(&agent->lock);
if(agent->reply != NULL) {
if (agent->reply != NULL)
{
PrivMutexObtain(&agent->lock);
reply->reply_len = 0;
va_start(params, cmd_expr);
ATSprintf(agent->fd, cmd_expr, params);
va_end(params);
PrivMutexAbandon(&agent->lock);
if (PrivSemaphoreObtainWait(&agent->rsp_sem, &abstime) != 0) {
printf("take sem %d timeout\n",agent->rsp_sem);
if (PrivSemaphoreObtainWait(&agent->rsp_sem, &abstime) != 0)
{
printf("take sem %d timeout\n", agent->rsp_sem);
result = -2;
goto __out;
}
} else {
}
else
{
PrivMutexObtain(&agent->lock);
va_start(params, cmd_expr);
ATSprintf(agent->fd, cmd_expr, params);
@ -187,35 +198,42 @@ int AtCmdConfigAndCheck(ATAgentType agent, char *cmd, char *check)
{
int ret = 0;
char *result = NULL;
if (NULL == agent || NULL == cmd || NULL == check ) {
if (NULL == agent || NULL == cmd || NULL == check)
{
return -1;
}
ATReplyType reply = CreateATReply(256);
if (NULL == reply) {
printf("%s %d at_create_resp failed!\n",__func__,__LINE__);
if (NULL == reply)
{
printf("%s %d at_create_resp failed!\n", __func__, __LINE__);
ret = -1;
goto __exit;
}
ret = ATOrderSend(agent, REPLY_TIME_OUT, reply, cmd);
if(ret < 0){
printf("%s %d ATOrderSend failed.\n",__func__,__LINE__);
if (ret < 0)
{
printf("%s %d ATOrderSend failed.\n", __func__, __LINE__);
ret = -1;
goto __exit;
}
//PrivTaskDelay(3000);
// PrivTaskDelay(3000);
result = GetReplyText(reply);
if (!result) {
printf("%s %n get reply failed.\n",__func__,__LINE__);
if (!result)
{
printf("%s %n get reply failed.\n", __func__, __LINE__);
ret = -1;
goto __exit;
}
#ifdef CONNECTION_FRAMEWORK_DEBUG
printf("[reply result: %s]\n", result);
if(!strstr(result, check)) {
printf("%s %d check[%s] reply[%s] failed.\n",__func__,__LINE__,check,result);
#endif
if (!strstr(result, check))
{
printf("%s %d check[%s] reply[%s] failed.\n", __func__, __LINE__, check, result);
ret = -1;
goto __exit;
}
@ -228,34 +246,40 @@ __exit:
int AtGetNetworkInfoReply(ATAgentType agent, char *cmd, char *result)
{
int ret = 0;
if (NULL == agent || NULL == cmd) {
if (NULL == agent || NULL == cmd)
{
return -1;
}
ATReplyType reply = CreateATReply(256);
if (NULL == reply) {
printf("%s %d at_create_resp failed!\n",__func__,__LINE__);
if (NULL == reply)
{
printf("%s %d at_create_resp failed!\n", __func__, __LINE__);
ret = -1;
goto __exit;
}
ret = ATOrderSend(agent, REPLY_TIME_OUT, reply, cmd);
if(ret < 0){
printf("%s %d ATOrderSend failed.\n",__func__,__LINE__);
if (ret < 0)
{
printf("%s %d ATOrderSend failed.\n", __func__, __LINE__);
ret = -1;
goto __exit;
}
const char *replyText = GetReplyText(reply);
if (replyText == NULL || replyText[0] == '\0') {
printf("%s %n get reply failed.\n",__func__,__LINE__);
if (replyText == NULL || replyText[0] == '\0')
{
printf("%s %n get reply failed.\n", __func__, __LINE__);
ret = -1;
goto __exit;
}
strncpy(result, replyText, 63);
result[63] = '\0';
#ifdef CONNECTION_FRAMEWORK_DEBUG
printf("[reply result: %s]\n", result);
#endif
__exit:
DeleteATReply(reply);
@ -269,7 +293,8 @@ char *GetReplyText(ATReplyType reply)
int AtSetReplyLrEnd(ATAgentType agent, char enable)
{
if (!agent) {
if (!agent)
{
return -1;
}
@ -280,7 +305,8 @@ int AtSetReplyLrEnd(ATAgentType agent, char enable)
int AtSetReplyEndChar(ATAgentType agent, char last_ch, char end_ch)
{
if (!agent) {
if (!agent)
{
return -1;
}
@ -292,7 +318,8 @@ int AtSetReplyEndChar(ATAgentType agent, char last_ch, char end_ch)
int AtSetReplyCharNum(ATAgentType agent, unsigned int num)
{
if (!agent) {
if (!agent)
{
return -1;
}
@ -303,8 +330,9 @@ int AtSetReplyCharNum(ATAgentType agent, unsigned int num)
int EntmSend(ATAgentType agent, const char *data, int len)
{
if(len > 256){
printf("send length %d more then max 256 Bytes.\n",len);
if (len > 256)
{
printf("send length %d more then max 256 Bytes.\n", len);
return -1;
}
char *send_buff = (char *)PrivMalloc(256);
@ -333,18 +361,20 @@ int EntmRecv(ATAgentType agent, char *rev_buffer, int buffer_len, int timeout_s)
uint32 real_recv_len = 0;
abstime.tv_sec = timeout_s;
if(buffer_len > ENTM_RECV_MAX){
printf("read length more then max length[%d] Bytes",ENTM_RECV_MAX);
return -1;
if (buffer_len > ENTM_RECV_MAX)
{
printf("read length more then max length[%d] Bytes", ENTM_RECV_MAX);
return -1;
}
PrivMutexObtain(&agent->lock);
agent->receive_mode = ENTM_MODE;
agent->read_len = buffer_len;
PrivMutexAbandon(&agent->lock);
//PrivTaskDelay(1000);
if (PrivSemaphoreObtainWait(&agent->entm_rx_notice, &abstime)) {
// PrivTaskDelay(1000);
if (PrivSemaphoreObtainWait(&agent->entm_rx_notice, &abstime))
{
#ifdef CONNECTION_FRAMEWORK_DEBUG
printf("wait sem[%d] timeout\n",agent->entm_rx_notice);
printf("wait sem[%d] timeout\n", agent->entm_rx_notice);
#endif
agent->entm_recv_len = 0;
return -1;
@ -381,74 +411,86 @@ static int GetCompleteATReply(ATAgentType agent)
PrivMutexAbandon(&agent->lock);
while (1) {
while (1)
{
res = PrivRead(agent->fd, &ch, 1);
#ifdef CONNECTION_FRAMEWORK_DEBUG
if((res == 1) && (ch != 0)) {
if ((res == 1) && (ch != 0))
{
printf(" %c (0x%x)\n", ch, ch);
}
#endif
PrivMutexObtain(&agent->lock);
if (agent->receive_mode == ENTM_MODE) {
if (agent->entm_recv_len < ENTM_RECV_MAX) {
if (agent->receive_mode == ENTM_MODE)
{
if (agent->entm_recv_len < ENTM_RECV_MAX)
{
#ifdef LIB_USING_MQTT
if((res == 1) && (agent->entm_recv_len < agent->read_len))
if ((res == 1) && (agent->entm_recv_len < agent->read_len))
{
agent->entm_recv_buf[agent->entm_recv_len] = ch;
agent->entm_recv_len++;
PrivMutexAbandon(&agent->lock);
continue;
}
}
#else
agent->entm_recv_buf[agent->entm_recv_len] = ch;
agent->entm_recv_len++;
if(agent->entm_recv_len < agent->read_len)
if (agent->entm_recv_len < agent->read_len)
{
PrivMutexAbandon(&agent->lock);
continue;
}
#endif
else
#endif
else
{
#ifdef CONNECTION_FRAMEWORK_DEBUG
printf("ENTM_MODE recv %d Bytes done.\n",agent->entm_recv_len);
printf("ENTM_MODE recv %d Bytes done.\n", agent->entm_recv_len);
#endif
agent->receive_mode = DEFAULT_MODE;
PrivSemaphoreAbandon(&agent->entm_rx_notice);
}
} else {
}
else
{
printf("entm_recv_buf is_full ...\n");
}
}
else if (agent->receive_mode == AT_MODE) {
if (read_len < agent->maintain_max) {
if(ch != 0) { ///< if the char is null then do not save it to the buff
else if (agent->receive_mode == AT_MODE)
{
if (read_len < agent->maintain_max)
{
if (ch != 0)
{ ///< if the char is null then do not save it to the buff
agent->maintain_buffer[read_len] = ch;
read_len++;
agent->maintain_len = read_len;
}
} else {
}
else
{
printf("maintain_len is_full %d ...\n", read_len);
is_full = true;
}
if (((ch == '\n') && (agent->reply_lr_end)) ||
((ch == '\n') && (last_ch == '\r') && (agent->reply_lr_end)) ||
((ch == agent->reply_end_char) && (agent->reply_end_char) &&
(last_ch == agent->reply_end_last_char) && (agent->reply_end_last_char)) ||
((read_len == agent->reply_char_num) && (agent->reply_char_num))) {
if (is_full) {
((ch == agent->reply_end_char) && (agent->reply_end_char) &&
(last_ch == agent->reply_end_last_char) && (agent->reply_end_last_char)) ||
((read_len == agent->reply_char_num) && (agent->reply_char_num)))
{
if (is_full)
{
printf("read line failed. The line data length is out of buffer size(%d)!", agent->maintain_max);
memset(agent->maintain_buffer, 0x00, agent->maintain_max);
agent->maintain_len = 0;
PrivMutexAbandon(&agent->lock);
return -1;
}
#ifdef CONNECTION_FRAMEWORK_DEBUG
printf("GetCompleteATReply done\n");
#endif
agent->receive_mode = DEFAULT_MODE;
PrivMutexAbandon(&agent->lock);
break;
@ -464,9 +506,11 @@ static int GetCompleteATReply(ATAgentType agent)
ATAgentType GetATAgent(const char *agent_name)
{
struct ATAgent* result = NULL;
for (int i = 0; i < AT_AGENT_MAX; i++) {
if (strcmp(at_agent_table[i].agent_name, agent_name) == 0) {
struct ATAgent *result = NULL;
for (int i = 0; i < AT_AGENT_MAX; i++)
{
if (strcmp(at_agent_table[i].agent_name, agent_name) == 0)
{
result = &at_agent_table[i];
}
}
@ -474,45 +518,51 @@ ATAgentType GetATAgent(const char *agent_name)
return result;
}
int DeleteATAgent(ATAgentType agent)
{
printf("delete agent->at_handler = %d\n",agent->at_handler);
if(agent->at_handler > 0){
printf("delete agent->at_handler = %d\n", agent->at_handler);
if (agent->at_handler > 0)
{
PrivTaskDelete(agent->at_handler, 0);
}
if (agent->fd > 0) {
printf("close agent fd = %d\n",agent->fd);
if (agent->fd > 0)
{
printf("close agent fd = %d\n", agent->fd);
PrivClose(agent->fd);
}
#ifdef ADD_NUTTX_FEATURES
if (agent->lock.sem.semcount > 0) {
printf("delete agent lock = %d\n",agent->lock.sem.semcount);
if (agent->lock.sem.semcount > 0)
{
printf("delete agent lock = %d\n", agent->lock.sem.semcount);
PrivMutexDelete(&agent->lock);
}
#elif defined ADD_RTTHREAD_FEATURES
#else
if (agent->lock) {
printf("delete agent lock = %d\n",agent->lock);
if (agent->lock)
{
printf("delete agent lock = %d\n", agent->lock);
PrivMutexDelete(&agent->lock);
}
#endif
#ifdef ADD_XIZI_FEATURES
if (agent->entm_rx_notice) {
printf("delete agent entm_rx_notice = %d\n",agent->entm_rx_notice);
if (agent->entm_rx_notice)
{
printf("delete agent entm_rx_notice = %d\n", agent->entm_rx_notice);
PrivSemaphoreDelete(&agent->entm_rx_notice);
}
#else
#endif
#ifdef ADD_XIZI_FEATURES
if (agent->rsp_sem) {
printf("delete agent rsp_sem = %d\n",agent->rsp_sem);
PrivSemaphoreDelete(&agent->rsp_sem);
if (agent->rsp_sem)
{
printf("delete agent rsp_sem = %d\n", agent->rsp_sem);
PrivSemaphoreDelete(&agent->rsp_sem);
}
#endif
if (agent->maintain_buffer) {
if (agent->maintain_buffer)
{
PrivFree(agent->maintain_buffer);
}
@ -525,18 +575,24 @@ static void *ATAgentReceiveProcess(void *param)
ATAgentType agent = (ATAgentType)param;
const struct at_urc *urc;
while (1) {
if (GetCompleteATReply(agent) > 0) {
while (1)
{
if (GetCompleteATReply(agent) > 0)
{
PrivMutexObtain(&agent->lock);
if (agent->reply != NULL) {
if (agent->reply != NULL)
{
ATReplyType reply = agent->reply;
agent->maintain_buffer[agent->maintain_len] = '\0';
if (agent->maintain_len <= reply->reply_max_len) {
memset(reply->reply_buffer, 0 , reply->reply_max_len);
if (agent->maintain_len <= reply->reply_max_len)
{
memset(reply->reply_buffer, 0, reply->reply_max_len);
memcpy(reply->reply_buffer, agent->maintain_buffer, agent->maintain_len);
reply->reply_len = agent->maintain_len;
} else {
}
else
{
printf("out of memory (%d)!\n", reply->reply_max_len);
}
@ -555,7 +611,8 @@ static int ATAgentInit(ATAgentType agent)
agent->maintain_len = 0;
agent->maintain_buffer = (char *)PrivMalloc(agent->maintain_max);
if (agent->maintain_buffer == NULL) {
if (agent->maintain_buffer == NULL)
{
printf("ATAgentInit malloc maintain_buffer error\n");
goto __out;
}
@ -563,18 +620,21 @@ static int ATAgentInit(ATAgentType agent)
memset(agent->maintain_buffer, 0, agent->maintain_max);
result = PrivSemaphoreCreate(&agent->entm_rx_notice, 0, 0);
if (result < 0) {
if (result < 0)
{
printf("ATAgentInit create entm sem error\n");
goto __out;
}
result = PrivSemaphoreCreate(&agent->rsp_sem, 0, 0);
if (result < 0) {
if (result < 0)
{
printf("ATAgentInit create rsp sem error\n");
goto __out;
}
if(PrivMutexCreate(&agent->lock, 0) < 0) {
if (PrivMutexCreate(&agent->lock, 0) < 0)
{
printf("AdapterFrameworkInit mutex create failed.\n");
goto __out;
}
@ -591,6 +651,10 @@ static int ATAgentInit(ATAgentType agent)
pthread_attr_t attr;
attr.schedparam.sched_priority = 25;
attr.stacksize = 4096;
#ifdef ADAPTER_GM800TF
attr.schedparam.sched_priority = 16;
attr.stacksize = 1800;
#endif
char task_name[] = "at_agent";
pthread_args_t args;
@ -616,15 +680,18 @@ int InitATAgent(const char *agent_name, int agent_fd, uint32 maintain_max)
int open_result = 0;
struct ATAgent *agent = NULL;
if (GetATAgent(agent_name) != NULL) {
if (GetATAgent(agent_name) != NULL)
{
return result;
}
while (i < AT_AGENT_MAX && at_agent_table[i].fd > 0) {
while (i < AT_AGENT_MAX && at_agent_table[i].fd > 0)
{
i++;
}
if (i >= AT_AGENT_MAX) {
if (i >= AT_AGENT_MAX)
{
printf("agent buffer(%d) is full.", AT_AGENT_MAX);
result = -1;
return result;
@ -639,7 +706,8 @@ int InitATAgent(const char *agent_name, int agent_fd, uint32 maintain_max)
agent->maintain_max = maintain_max;
result = ATAgentInit(agent);
if (result == 0) {
if (result == 0)
{
PrivTaskStartup(&agent->at_handler);
}
@ -651,7 +719,8 @@ ATReplyType CreateATReply(uint32 reply_max_len)
ATReplyType reply = NULL;
reply = (ATReplyType)PrivMalloc(sizeof(struct ATReply));
if (reply == NULL) {
if (reply == NULL)
{
printf("no more memory\n");
return NULL;
}
@ -660,7 +729,8 @@ ATReplyType CreateATReply(uint32 reply_max_len)
reply->reply_max_len = reply_max_len;
reply->reply_buffer = (char *)PrivMalloc(reply_max_len);
if (reply->reply_buffer == NULL) {
if (reply->reply_buffer == NULL)
{
printf("no more memory\n");
PrivFree(reply);
return NULL;
@ -673,14 +743,17 @@ ATReplyType CreateATReply(uint32 reply_max_len)
void DeleteATReply(ATReplyType reply)
{
if (reply) {
if (reply->reply_buffer) {
if (reply)
{
if (reply->reply_buffer)
{
PrivFree(reply->reply_buffer);
reply->reply_buffer = NULL;
}
}
if (reply) {
if (reply)
{
PrivFree(reply);
reply = NULL;
}

6
APP_Framework/Framework/connection/at_agent.h
View File

@ -59,7 +59,11 @@ struct ATAgent
uint32 maintain_max;
#ifdef ADD_XIZI_FEATURES
int lock;
#ifdef ADAPTER_GM800TF
pthread_mutex_t lock;
#else
int lock;
#endif
#else
pthread_mutex_t lock;
#endif

6
APP_Framework/Framework/connection/ethernet/Kconfig
View File

@ -3,7 +3,13 @@ config ADAPTER_HFA21_ETHERNET
Please check HFA21 can only work for adapter_wifi or adapter_ethernet in the meantime!
bool "Using ethernet adapter device HFA21"
default n
config ADAPTER_WCHNET_ETHERNET
bool "Using ethernet adapter device WCHNET"
default n
if ADAPTER_HFA21_ETHERNET
source "$APP_DIR/Framework/connection/ethernet/hfa21_ethernet/Kconfig"
endif
if ADAPTER_WCHNET_ETHERNET
source "$APP_DIR/Framework/connection/ethernet/wchnet_ethernet/Kconfig"
endif

3
APP_Framework/Framework/connection/ethernet/Makefile
View File

@ -3,5 +3,8 @@ SRC_FILES := adapter_ethernet.c
ifeq ($(CONFIG_ADAPTER_HFA21_ETHERNET),y)
SRC_DIR += hfa21_ethernet
endif
ifeq ($(CONFIG_ADAPTER_WCHNET_ETHERNET),y)
SRC_DIR += wchnet_ethernet
endif
include $(KERNEL_ROOT)/compiler.mk

95
APP_Framework/Framework/connection/ethernet/adapter_ethernet.c
View File

@ -1,14 +1,14 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file adapter_ethernet.c
@ -23,9 +23,11 @@
#ifdef ADAPTER_HFA21_ETHERNET
extern AdapterProductInfoType Hfa21EthernetAttach(struct Adapter *adapter);
#endif
#ifdef ADAPTER_WCHNET_ETHERNET
extern AdapterProductInfoType wchnetEthernetAttach(struct Adapter *adapter);
#endif
static int AdapterEthernetRegister(struct Adapter *adapter)
{
static int AdapterEthernetRegister(struct Adapter *adapter) {
int ret = 0;
strncpy(adapter->name, ADAPTER_ETHERNET_NAME, NAME_NUM_MAX);
@ -42,8 +44,7 @@ static int AdapterEthernetRegister(struct Adapter *adapter)
return ret;
}
int AdapterEthernetInit(void)
{
int AdapterEthernetInit(void) {
int ret = 0;
struct Adapter *adapter = PrivMalloc(sizeof(struct Adapter));
@ -74,17 +75,28 @@ int AdapterEthernetInit(void)
adapter->info = product_info;
adapter->done = product_info->model_done;
#endif
#ifdef ADAPTER_WCHNET_ETHERNET
AdapterProductInfoType product_info = wchnetEthernetAttach(adapter);
if (!product_info) {
printf("AdapterEthernetInit wchnet attach error\n");
PrivFree(adapter);
return -1;
}
adapter->product_info_flag = 1;
adapter->info = product_info;
adapter->done = product_info->model_done;
#endif
return ret;
}
/******************ethernet TEST*********************/
int AdapterEthernetTest(void)
{
int AdapterEthernetTest(void) {
int baud_rate = BAUD_RATE_57600;
struct Adapter *adapter = AdapterDeviceFindByName(ADAPTER_ETHERNET_NAME);
struct Adapter *adapter = AdapterDeviceFindByName(ADAPTER_ETHERNET_NAME);
#ifdef ADAPTER_HFA21_ETHERNET
@ -96,30 +108,67 @@ int AdapterEthernetTest(void)
AdapterDeviceControl(adapter, OPE_INT, &baud_rate);
AdapterDeviceSetUp(adapter);
const char *ip = "192.168.131.26";
const char *port = "9999";
enum NetRoleType net_role = CLIENT;//SERVER
enum NetRoleType net_role = CLIENT; // SERVER
enum IpType ip_type = IPV4;
AdapterDeviceConnect(adapter, net_role, ip, port, ip_type);
printf("ready to test data transfer\n");
PrivTaskDelay(2000);
len = strlen(ethernet_msg);
for (i = 0;i < 10; i ++) {
for (i = 0; i < 10; i++) {
printf("AdapterEthernetTest send %s\n", ethernet_msg);
AdapterDeviceSend(adapter, ethernet_msg, len);
PrivTaskDelay(4000);
}
while (1) {
AdapterDeviceRecv(adapter, ethernet_recv_msg, 128);
printf("AdapterEthernetTest recv %s\n", ethernet_recv_msg);
memset(ethernet_recv_msg, 0, 128);
}
#endif
#ifdef ADAPTER_WCHNET_ETHERNET
AdapterDeviceSetUp(adapter);
// AdapterDeviceSetAddr(adapter, "192.168.1.10", "255.255.255.0", "192.168.1.1");
// AdapterDeviceSetDhcp(adapter, 1);
// AdapterDeviceConnect(adapter, CLIENT, "115.238.53.59", "10208", IPV4);
AdapterDeviceConnect(adapter, CLIENT, "192.168.1.100", "1000", IPV4);
AdapterDeviceSend(adapter, "Hello World!", sizeof("Hello World!"));
// /* 测试DHCP连接路由器后，连接因特网 */
// AdapterDeviceSend(adapter,
// "GET /v3/weather/weatherInfo?city=%E9%95%BF%E6%B2%99&key=13cb58f5884f9749287abbead9c658f2 "
// "HTTP/1.1\r\nHost: restapi.amap.com\r\n\r\n",
// sizeof("GET
// /v3/weather/weatherInfo?city=%E9%95%BF%E6%B2%99&key=13cb58f5884f9749287abbead9c658f2 "
// "HTTP/1.1\r\nHost: restapi.amap.com\r\n\r\n"));
char receiveBuffer[128] = {};
PrivTaskDelay(20000);
ssize_t readLength = AdapterDeviceRecv(adapter, receiveBuffer, sizeof(receiveBuffer));
// printf("receiveBuffer:%s\n", receiveBuffer);
printf("[socketid-%d]receiveBuffer:", adapter->socket.socket_id);
for (int i = 0; i < readLength; i++) {
printf("%c", receiveBuffer[i]);
}
printf("\n");
AdapterDeviceDisconnect(adapter, NULL);
// AdapterDeviceConnect(adapter, CLIENT, "115.238.53.59", "10208", IPV4);
AdapterDeviceConnect(adapter, CLIENT, "192.168.1.100", "1000", IPV4);
AdapterDeviceSend(adapter, "Hello World!", sizeof("Hello World!"));
PrivTaskDelay(20000);
readLength = AdapterDeviceRecv(adapter, receiveBuffer, sizeof(receiveBuffer));
printf("[socketid-%d]receiveBuffer:", adapter->socket.socket_id);
for (int i = 0; i < readLength; i++) {
printf("%c", receiveBuffer[i]);
}
printf("\n");
AdapterDeviceSetDown(adapter);
AdapterDeviceClose(adapter);
#endif
return 0;
}
PRIV_SHELL_CMD_FUNCTION(AdapterEthernetTest, a ethernet test sample, PRIV_SHELL_CMD_MAIN_ATTR);

3
APP_Framework/Framework/connection/ethernet/wchnet_ethernet/Kconfig Normal file
View File

@ -0,0 +1,3 @@
config ADAPTER_ETHERNET_WCHNET
string "WCHNET ETHERNET adapter name"
default "wchnet_ethernet"

3
APP_Framework/Framework/connection/ethernet/wchnet_ethernet/Makefile Normal file
View File

@ -0,0 +1,3 @@
SRC_FILES := wchnet_ethernet.c
include $(KERNEL_ROOT)/compiler.mk

10
APP_Framework/Framework/connection/ethernet/wchnet_ethernet/SConscript Normal file
View File

@ -0,0 +1,10 @@
from building import *
import os
cwd = GetCurrentDir()
src = []
if GetDepend(['ADAPTER_WCHNET_ETHERNET']):
src += ['wchnet_ethernet.c']
group = DefineGroup('connection ethernet wchnet', src, depend = [], CPPPATH = [cwd])
Return('group')

532
APP_Framework/Framework/connection/ethernet/wchnet_ethernet/wchnet_ethernet.c Normal file
View File

@ -0,0 +1,532 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file wchnet_ethernet.c
* @brief Implement the connection ethernet adapter function, using wchnet device
* @author Huo Yujia (huoyujia081@126.com)
* @version 1.0
* @date 2024-07-17
*/
#include <ModuleConfig.h>
#include <adapter.h>
#include <connect_ether.h>
#include <eth_driver.h>
extern pmodule_cfg CFG; // 从flash中读取的配置信息指针
/* 记录socket会话参数，由于ch32v208内存限制，目前只支持单个会话通信 */
struct WchnetSocketConfiguration wchnetSocketConfiguration;
/**
* @brief wchnet主任务线程，主要用于不断处理以太网中断
* @param argv 参数无意义
* @return void* 返回值无意义
*/
static void *wchnetMainTask(void *argv) {
struct WchnetSocketConfiguration *pWchnetSocketConfiguration = (struct WchnetSocketConfiguration *)argv;
while (1) {
PrivTaskDelay(50);
WCHNET_MainTask();
if (WCHNET_QueryGlobalInt()) {
WCHNET_HandleGlobalInt(pWchnetSocketConfiguration);
}
}
return NULL;
}
/**
* @brief 以太网发送数据
* @param adapter
* @param data 所要发送数据的存储区域指针
* @param len 所要发送数据的长度
* @return int 实际发送的数据长度
*/
static int wchnetEthernetSend(struct Adapter *adapter, const void *data, size_t len) {
struct WchnetSocketConfiguration *pWchnetSocketConfiguration =
(struct WchnetSocketConfiguration *)adapter->adapter_param;
/* 判断是否可以发送数据 */
if (pWchnetSocketConfiguration->wchnetMainThread == 0) { // 判断是否已启动wchnet主任务线程
printf("[error %s %d]wchnetMainThread has not been started, please call function AdapterDeviceSetUp first\n",
__func__, __LINE__);
return -1;
} else if (pWchnetSocketConfiguration->socketStatus != WCHNET_SOCKET_CONNECT_SUCCESS) { // 判断是否已连接socket
printf(
"[error %s %d]socket has not been connected, please call function AdapterDeviceConnect "
"first\n",
__func__, __LINE__);
return -1;
}
/* 发送数据 */
uint32_t tempLen = (uint32_t)len; // 实际发送数据长度
uint8_t res = WCHNET_SocketSend(pWchnetSocketConfiguration->socketId, (uint8_t *)data, &tempLen);
if (res == WCHNET_ERR_SUCCESS) {
printf("[socketid-%d]send data success, len = %d\n", adapter->socket.socket_id, tempLen);
return tempLen;
} else {
mStopIfError(res);
return -1;
}
}
/**
* @brief 以太网接收数据
* @param adapter
* @param rev_buffer 接收数据首地址
* @param buffer_len 期望读取的数据长度
* @return int 实际读取的数据长度
*/
static int wchnetEthernetReceive(struct Adapter *adapter, void *rev_buffer, size_t buffer_len) {
struct WchnetSocketConfiguration *pWchnetSocketConfiguration =
(struct WchnetSocketConfiguration *)adapter->adapter_param;
/* 判断是否可以接收数据 */
if (pWchnetSocketConfiguration->wchnetMainThread == 0) { // 判断是否已启动wchnet主任务线程
printf("[error %s %d]wchnetMainThread has not been started, please call function AdapterDeviceSetUp first\n",
__func__, __LINE__);
return -1;
}
/* 接收数据 */
uint32_t tempLen = (uint32_t)buffer_len; // 实际接收数据长度
uint8_t res = WCHNET_SocketRecv(pWchnetSocketConfiguration->socketId, (u8 *)rev_buffer, &tempLen);
if (res == WCHNET_ERR_SUCCESS) {
printf("[socketid-%d]recv data success, len = %d\n", pWchnetSocketConfiguration->socketId, tempLen);
return tempLen;
} else {
mStopIfError(res);
return -1;
}
}
/**
* @brief 启动wchnet主任务线程，监听以太网中断
* @param adapter
* @return int 0表示线程启动成功，其他表示线程启动失败
*/
static int wchnetEthernetSetUp(struct Adapter *adapter) {
pthread_attr_t wchnetMainTaskAttr;
pthread_args_t wchnetMainTaskArgs;
wchnetMainTaskAttr.schedparam.sched_priority = 16; // 线程优先级
wchnetMainTaskAttr.stacksize = 1100; // 线程栈大小
wchnetMainTaskArgs.pthread_name = "wchnetMainTask"; // 线程名字
wchnetMainTaskArgs.arg = &wchnetSocketConfiguration; // 线程参数
int res = PrivTaskCreate(&wchnetSocketConfiguration.wchnetMainThread, &wchnetMainTaskAttr, wchnetMainTask,
&wchnetMainTaskArgs);
PrivTaskStartup(&wchnetSocketConfiguration.wchnetMainThread);
adapter->adapter_param = &wchnetSocketConfiguration;
return res;
}
/**
* @brief 关闭以太网socket连接
* @param adapter
* @return int 0表示关闭以太网socket连接成功，其他表示关闭以太网socket连接失败
*/
static int wchnetEthernetDisconnect(struct Adapter *adapter) {
struct WchnetSocketConfiguration *pWchnetSocketConfiguration =
(struct WchnetSocketConfiguration *)adapter->adapter_param;
/* 判断是否可以关闭socket */
if (pWchnetSocketConfiguration->wchnetMainThread == 0) { // 判断是否已启动wchnet主任务线程
printf("[error %s %d]wchnetMainThread has not been started, please call function AdapterDeviceSetUp first\n",
__func__, __LINE__);
return -1;
} else if (pWchnetSocketConfiguration->socketStatus !=
WCHNET_SOCKET_CONNECT_SUCCESS) { // 判断当前是否已有socket连接
return WCHNET_ERR_SUCCESS;
}
/* 将目的IP地址和端口号的数组形式转换成字符串形式和unsigned short形式 */
char destinationIpAddress[16]; // 目的IP地址
uint16_t destinationPort; // 目的端口号
sprintf(destinationIpAddress, "%u.%u.%u.%u", pWchnetSocketConfiguration->destinationIpAddress[0],
pWchnetSocketConfiguration->destinationIpAddress[1], pWchnetSocketConfiguration->destinationIpAddress[2],
pWchnetSocketConfiguration->destinationIpAddress[3]);
destinationPort =
(pWchnetSocketConfiguration->destinationPort[1] << 8) + pWchnetSocketConfiguration->destinationPort[0];
/* 关闭socket连接 */
uint8_t res = WCHNET_SocketClose(pWchnetSocketConfiguration->socketId, TCP_CLOSE_NORMAL);
if (res == WCHNET_ERR_SUCCESS) {
while (pWchnetSocketConfiguration->socketStatus == WCHNET_SOCKET_CONNECT_SUCCESS) {
PrivTaskDelay(100); // 每100ms检查一次是否socket关闭完成
}
/* socket关闭完成 */
pWchnetSocketConfiguration->socketStatus = WCHNET_SOCKET_UNDEFINED;
printf("[socketid-%d]socket with %s:%hu has been disconnected\n", pWchnetSocketConfiguration->socketId,
destinationIpAddress, destinationPort);
return WCHNET_ERR_SUCCESS;
} else {
mStopIfError(res);
printf("[socketid-%d]socket with %s:%hu disconnect error\n", pWchnetSocketConfiguration->socketId,
destinationIpAddress, destinationPort);
return res;
}
}
/**
* @brief 建立以太网socket连接
* @param adapter
* @param net_role 网络角色，CLIENT或者SERVER
* @param ip 目的IP地址字符串
* @param port 目的端口号字符串
* @param ip_type IP类型，IPV4或者IPV6
* @return int 0表示建立以太网socket连接成功，其他表示建立以太网socket连接失败
*/
static int wchnetEthernetConnect(struct Adapter *adapter, enum NetRoleType net_role, const char *ip, const char *port,
enum IpType ip_type) {
struct WchnetSocketConfiguration *pWchnetSocketConfiguration =
(struct WchnetSocketConfiguration *)adapter->adapter_param;
/* 由于ch32v208内存限制，当前仅支持IPV4+CLIENT */
if (ip_type != IPV4) {
printf("[error %s %d]wchnetEthernetConnect only support IPV4, do not support IPV6\n", __func__, __LINE__);
return -1;
} else if (net_role != CLIENT) {
printf("[error %s %d]wchnetEthernetConnect only support CLIENT, do not support SERVER\n", __func__, __LINE__);
return -1;
}
/* 将IP地址和端口号的字符串形式转换成数组形式 */
uint8_t destinationIpAddress[4];
uint8_t destinationPort[2];
WCHNET_Aton(ip, destinationIpAddress);
destinationPort[0] = atoi(port) % 256;
destinationPort[1] = atoi(port) / 256;
uint8_t res = WCHNET_ERR_SUCCESS;
if (pWchnetSocketConfiguration->wchnetMainThread == 0) { // 判断是否已启动wchnet主任务线程
printf("[error %s %d]wchnetMainThread has not been started, please call function AdapterDeviceSetUp first\n",
__func__, __LINE__);
return -1;
} else if (pWchnetSocketConfiguration->socketStatus ==
WCHNET_SOCKET_CONNECT_SUCCESS) { // 判断当前是否已有socket连接
if (memcmp(destinationIpAddress, pWchnetSocketConfiguration->destinationIpAddress, 4) == 0 &&
memcmp(destinationPort, pWchnetSocketConfiguration->destinationPort, 2) ==
0) { // 当前连接的socket，目的IP地址和端口号完全一致，无需再次连接
return WCHNET_ERR_SUCCESS;
} else { // 当前连接的socket，目的IP地址和端口号不完全一致，由于ch32v208内存限制，当前仅支持单个socket通信，需断开当前连接
res = wchnetEthernetDisconnect(adapter);
if (res != WCHNET_ERR_SUCCESS) {
mStopIfError(res);
printf("[error %s %d]wchnetEthernetDisconnect fail\n", __func__, __LINE__);
return res;
}
}
}
/* 保存目的IP地址和目的端口号 */
memcpy(pWchnetSocketConfiguration->destinationIpAddress, destinationIpAddress, 4);
memcpy(pWchnetSocketConfiguration->destinationPort, destinationPort, 2);
pWchnetSocketConfiguration->socketStatus = WCHNET_SOCKET_UNDEFINED;
/* 配置socket会话 */
SOCK_INF TmpSocketInf;
memset((void *)&TmpSocketInf, 0, sizeof(SOCK_INF));
memcpy(TmpSocketInf.IPAddr, destinationIpAddress, 4);
TmpSocketInf.SourPort =
(pWchnetSocketConfiguration->sourcePort[1] << 8) + pWchnetSocketConfiguration->sourcePort[0]; // 源端口号
TmpSocketInf.DesPort = (pWchnetSocketConfiguration->destinationPort[1] << 8) +
pWchnetSocketConfiguration->destinationPort[0]; // 目的端口号
TmpSocketInf.ProtoType = PROTO_TYPE_TCP; // 协议类型，TCP
TmpSocketInf.RecvBufLen = RECE_BUF_LEN; // 接收缓冲区大小
/* 创建socket */
res = WCHNET_SocketCreat(&pWchnetSocketConfiguration->socketId, &TmpSocketInf);
if (res == WCHNET_ERR_SUCCESS) {
printf("[socketid-%d]create socketId %d\r\n", pWchnetSocketConfiguration->socketId,
pWchnetSocketConfiguration->socketId);
} else {
mStopIfError(res);
printf("[error %s %d]WCHNET_SocketCreat fail\n", __func__, __LINE__);
return res;
}
/* 连接socket */
res = WCHNET_SocketConnect(pWchnetSocketConfiguration->socketId);
if (res == WCHNET_ERR_SUCCESS) {
printf("[socketid-%d]connecting socketId %d\r\n", pWchnetSocketConfiguration->socketId,
pWchnetSocketConfiguration->socketId);
} else {
mStopIfError(res);
printf("[error %s %d]WCHNET_SocketConnect fail\n", __func__, __LINE__);
return res;
}
/* 每100ms查询一次，直至连接成功或者超时 */
while (pWchnetSocketConfiguration->socketStatus == WCHNET_SOCKET_UNDEFINED) {
printf("[socketid-%d]connecting socketId %d\r\n", pWchnetSocketConfiguration->socketId,
pWchnetSocketConfiguration->socketId);
PrivTaskDelay(1000);
}
if (pWchnetSocketConfiguration->socketStatus == WCHNET_SOCKET_CONNECT_SUCCESS) {
printf("[socketid-%d]socket connect success\n", pWchnetSocketConfiguration->socketId);
return res;
} else if (pWchnetSocketConfiguration->socketStatus == WCHNET_SOCKET_CONNECT_TIMEOUT) {
printf("[socketid-%d]socket connect timeout\n", pWchnetSocketConfiguration->socketId);
return -1;
}
}
/**
* @brief 设置以太网源IP地址，网关地址，子网掩码
* @param adapter
* @param ip 源IP地址
* @param gateway 网关地址
* @param netmask 子网掩码
* @return int 0表示设置成功，其他表示设置失败
*/
static int wchnetEthernetSetAddr(struct Adapter *adapter, const char *ip, const char *gateway, const char *netmask) {
struct WchnetSocketConfiguration *pWchnetSocketConfiguration =
(struct WchnetSocketConfiguration *)adapter->adapter_param;
/* 判断是否已启动wchnet主任务线程 */
if (pWchnetSocketConfiguration->wchnetMainThread == 0) {
printf("[error %s %d]wchnetMainThread has not been started, please call function AdapterDeviceSetUp first\n",
__func__, __LINE__);
return -1;
}
/* 将地址的字符串形式转化为数组形式 */
uint8_t sourceIpAddress[4], sourceGateway[4], sourceSubnetMask[4];
WCHNET_Aton(ip, sourceIpAddress);
WCHNET_Aton(gateway, sourceGateway);
WCHNET_Aton(netmask, sourceSubnetMask);
/* 若配置内容和当前配置保持一致，则无需配置 */
if (memcmp(sourceIpAddress, pWchnetSocketConfiguration->sourceIpAddress, 4) == 0 &&
memcmp(sourceGateway, pWchnetSocketConfiguration->sourceGateway, 4) == 0 &&
memcmp(sourceSubnetMask, pWchnetSocketConfiguration->sourceSubnetMask, 4) == 0) {
return WCHNET_ERR_SUCCESS;
}
/* 若当前有socket正在连接，则需断开socket，再使用新的配置连接socket */
uint8_t socketExists = pWchnetSocketConfiguration->socketStatus == WCHNET_SOCKET_CONNECT_SUCCESS;
if (socketExists) {
wchnetEthernetDisconnect(adapter);
}
/* 进行配置，并重新初始化wchnet */
memcpy(pWchnetSocketConfiguration->sourceIpAddress, sourceIpAddress, 4);
memcpy(pWchnetSocketConfiguration->sourceGateway, sourceGateway, 4);
memcpy(pWchnetSocketConfiguration->sourceSubnetMask, sourceSubnetMask, 4);
uint8_t res = WCHNET_Init(pWchnetSocketConfiguration->sourceIpAddress, pWchnetSocketConfiguration->sourceGateway,
pWchnetSocketConfiguration->sourceSubnetMask, pWchnetSocketConfiguration->macAddress);
if (res == WCHNET_ERR_SUCCESS) { // 初始化wchnet成功
pWchnetSocketConfiguration->dhcpSwitch = 0;
pWchnetSocketConfiguration->dhcpStatus = WCHNET_DHCP_UNDEFINED;
printf("-*-*-*wchnetEthernetSetAddr*-*-*\n");
printf("ip:\t%s\ngateway:%s\nnetmask:%s\n", ip, gateway, netmask);
printf("-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\n");
if (socketExists) { // 若之前有socket正在连接，则需重新连接
char destinationIpAddress[16], destinationPort[6];
sprintf(destinationIpAddress, "%u.%u.%u.%u", pWchnetSocketConfiguration->destinationIpAddress[0],
pWchnetSocketConfiguration->destinationIpAddress[1],
pWchnetSocketConfiguration->destinationIpAddress[2],
pWchnetSocketConfiguration->destinationIpAddress[3]);
sprintf(
destinationPort, "%hu",
(pWchnetSocketConfiguration->destinationPort[1] << 8) + pWchnetSocketConfiguration->destinationPort[0]);
res = wchnetEthernetConnect(adapter, CLIENT, destinationIpAddress, destinationPort, IPV4);
}
}
mStopIfError(res);
return res;
}
/**
* @brief 删除wchnet主任务线程
* @param adapter
* @return int 0表示删除wchnet主任务线程成功，其他表示删除wchnet主任务线程失败
*/
static int wchnetEthernetSetDown(struct Adapter *adapter) {
struct WchnetSocketConfiguration *pWchnetSocketConfiguration =
(struct WchnetSocketConfiguration *)adapter->adapter_param;
/* 如果wchnet主任务线程已经处于关闭状态 */
if (pWchnetSocketConfiguration->wchnetMainThread == 0) {
return WCHNET_ERR_SUCCESS;
}
uint8_t res = WCHNET_ERR_SUCCESS;
/* 如果仍有socket未关闭，先关闭socket */
if (pWchnetSocketConfiguration->socketStatus == WCHNET_SOCKET_CONNECT_SUCCESS) {
res = wchnetEthernetDisconnect(adapter);
if (res != WCHNET_ERR_SUCCESS) {
return res;
}
}
/* 删除wchnet主任务线程 */
res = PrivTaskDelete(pWchnetSocketConfiguration->wchnetMainThread, 0);
if (res != 0) {
printf("wchnet ethernet set down fail\n");
} else {
pWchnetSocketConfiguration->wchnetMainThread = 0;
printf("wchnet ethernet set down success\n");
}
return res;
}
/**
* @brief 设置DHCP
* @param adapter
* @param enable 0表示关闭DHCP，1表示打开DHCP
* @return int 0表示设置成功，其他表示设置失败
* @note 若获得新的动态IP地址，则关闭当前的所有socket连接，并使用新的IP地址建立连接
* @note 若获得的动态IP地址和当前的IP地址一致，则不进行任何操作，继续使用旧的IP地址进行通信
* @note 若获取动态IP地址失败，则继续使用旧的IP地址进行通信
*/
static int wchnetEthernetSetDHCP(struct Adapter *adapter, int enable) {
struct WchnetSocketConfiguration *pWchnetSocketConfiguration =
(struct WchnetSocketConfiguration *)adapter->adapter_param;
if (pWchnetSocketConfiguration->wchnetMainThread == 0) { // 判断是否已启动wchnet主任务线程
printf("[error %s %d]wchnetMainThread has not been started, please call function AdapterDeviceSetUp first\n",
__func__, __LINE__);
return -1;
}
uint8_t res;
switch (enable) {
/* 关闭DHCP */
case 0:
/* 如果原来就没有打开DHCP，无需关闭DHCP */
if (pWchnetSocketConfiguration->dhcpSwitch == 0) {
return WCHNET_ERR_SUCCESS;
}
/* 重新使用静态IP地址初始化，相当于关闭DHCP */
res = WCHNET_Init(pWchnetSocketConfiguration->sourceIpAddress, pWchnetSocketConfiguration->sourceGateway,
pWchnetSocketConfiguration->sourceSubnetMask, pWchnetSocketConfiguration->macAddress);
if (res != WCHNET_ERR_SUCCESS) { // DHCP关闭失败
mStopIfError(res);
} else { // DHCP关闭成功
pWchnetSocketConfiguration->dhcpSwitch = 0;
pWchnetSocketConfiguration->dhcpStatus = WCHNET_DHCP_UNDEFINED;
}
return res;
break;
/* 打开DHCP */
case 1:
/* 如果原来已经打开DHCP */
if (pWchnetSocketConfiguration->dhcpSwitch == 1 &&
(pWchnetSocketConfiguration->dhcpStatus == WCHNET_DHCP_SUCCESS_NEW ||
pWchnetSocketConfiguration->dhcpStatus == WCHNET_DHCP_SUCCESS_OLD)) {
return WCHNET_ERR_SUCCESS;
}
/* 配置DHCP主机名 */
res = WCHNET_DHCPSetHostname("WCHNET");
if (res == WCHNET_ERR_SUCCESS) {
printf("DHCP hostname set success\n");
} else {
mStopIfError(res);
printf("[error %s %d]WCHNET_DHCPSetHostname fail\n", __func__, __LINE__);
}
/* 开启DHCP */
res = WCHNET_DHCPStart(WCHNET_DHCPCallBack);
if (res == WCHNET_ERR_SUCCESS) {
pWchnetSocketConfiguration->dhcpStatus = WCHNET_DHCP_UNDEFINED;
while (pWchnetSocketConfiguration->dhcpStatus == WCHNET_DHCP_UNDEFINED) {
PrivTaskDelay(1000); // 每秒查询一次DHCP状态
printf("DHCP finding IP\n");
}
WCHNET_DHCPStop(); // 停止DHCP
switch (pWchnetSocketConfiguration->dhcpStatus) {
case WCHNET_DHCP_SUCCESS_NEW: // 获取到新的动态IP地址，若之前连接过socket，则重新连接该socket
pWchnetSocketConfiguration->dhcpSwitch = 1;
printf("DHCP set up successfully, getting new IP configuration\n");
if (pWchnetSocketConfiguration->socketStatus == WCHNET_SOCKET_CONNECT_SUCCESS) {
char destinationIpAddress[16];
char destinationPort[6];
sprintf(destinationIpAddress, "%u.%u.%u.%u",
pWchnetSocketConfiguration->destinationIpAddress[0],
pWchnetSocketConfiguration->destinationIpAddress[1],
pWchnetSocketConfiguration->destinationIpAddress[2],
pWchnetSocketConfiguration->destinationIpAddress[3]);
sprintf(destinationPort, "%hu",
(pWchnetSocketConfiguration->destinationPort[1] << 8) +
pWchnetSocketConfiguration->destinationPort[0]);
if (!wchnetEthernetDisconnect(adapter) &&
!wchnetEthernetConnect(adapter, CLIENT, destinationIpAddress, destinationPort, IPV4)) {
printf("[socketid-%d]DHCP: socket with %s:%s has been reset\n",
pWchnetSocketConfiguration->socketId, destinationIpAddress, destinationPort);
} else {
printf("[socketid-%d]DHCP: socket with %s:%s reset failed\n",
pWchnetSocketConfiguration->socketId, pWchnetSocketConfiguration->socketId,
destinationIpAddress, destinationPort);
}
}
return WCHNET_ERR_SUCCESS;
break;
case WCHNET_DHCP_SUCCESS_OLD: // 获取到旧的动态IP地址
pWchnetSocketConfiguration->dhcpSwitch = 1;
printf("DHCP set up successfully, getting the same IP configuration\n");
return WCHNET_ERR_SUCCESS;
break;
case WCHNET_DHCP_FAIL: // 获取动态IP地址错误
pWchnetSocketConfiguration->dhcpSwitch = 0;
printf("[error %s %d]wchnet dhcp fail\n", __func__, __LINE__);
return -1;
}
} else {
mStopIfError(res);
return res;
}
break;
}
}
static const struct IpProtocolDone wchnet_ethernet_done = {
.open = NULL,
.close = NULL,
.ioctl = NULL,
.setup = wchnetEthernetSetUp,
.setdown = wchnetEthernetSetDown,
.setaddr = wchnetEthernetSetAddr,
.setdns = NULL,
.setdhcp = wchnetEthernetSetDHCP,
.ping = NULL,
.netstat = NULL,
.connect = wchnetEthernetConnect,
.send = wchnetEthernetSend,
.recv = wchnetEthernetReceive,
.disconnect = wchnetEthernetDisconnect,
};
/**
* @description: Register ethernet device wchnet
* @return success: product_info, failure: NULL
*/
AdapterProductInfoType wchnetEthernetAttach(struct Adapter *adapter) {
struct AdapterProductInfo *product_info = PrivMalloc(sizeof(struct AdapterProductInfo));
if (!product_info) {
printf("wchnetEthernetAttach Attach malloc product_info error\n");
PrivFree(product_info);
return NULL;
}
strcpy(product_info->model_name, ADAPTER_ETHERNET_WCHNET);
product_info->model_done = (void *)&wchnet_ethernet_done;
return product_info;
}

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SRC_FILES := core_riscv.c
include $(KERNEL_ROOT)/compiler.mk

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Ubiquitous/XiZi_IIoT/arch/risc-v/ch32v208rbt6/Core/core_riscv.c Normal file
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/********************************** (C) COPYRIGHT *******************************
* File Name : core_riscv.c
* Author : WCH
* Version : V1.0.1
* Date : 2023/11/11
* Description : RISC-V V4 Core Peripheral Access Layer Source File for CH32V20x
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include <stdint.h>
/* define compiler specific symbols */
#if defined ( __CC_ARM )
#define __ASM __asm /* asm keyword for ARM Compiler */
#define __INLINE __inline /* inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /* asm keyword for IAR Compiler */
#define __INLINE inline /* inline keyword for IAR Compiler. Only avaiable in High optimization mode */
#elif defined ( __GNUC__ )
#define __ASM __asm /* asm keyword for GNU Compiler */
#define __INLINE inline /* inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /* asm keyword for TASKING Compiler */
#define __INLINE inline /* inline keyword for TASKING Compiler */
#endif
/*********************************************************************
* @fn __get_MSTATUS
*
* @brief Return the Machine Status Register
*
* @return mstatus value
*/
uint32_t __get_MSTATUS(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mstatus" : "=r" (result) );
return (result);
}
/*********************************************************************
* @fn __set_MSTATUS
*
* @brief Set the Machine Status Register
*
* @param value - set mstatus value
*
* @return none
*/
void __set_MSTATUS(uint32_t value)
{
__ASM volatile ("csrw mstatus, %0" : : "r" (value) );
}
/*********************************************************************
* @fn __get_MISA
*
* @brief Return the Machine ISA Register
*
* @return misa value
*/
uint32_t __get_MISA(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "misa" : "=r" (result) );
return (result);
}
/*********************************************************************
* @fn __set_MISA
*
* @brief Set the Machine ISA Register
*
* @param value - set misa value
*
* @return none
*/
void __set_MISA(uint32_t value)
{
__ASM volatile ("csrw misa, %0" : : "r" (value) );
}
/*********************************************************************
* @fn __get_MTVEC
*
* @brief Return the Machine Trap-Vector Base-Address Register
*
* @return mtvec value
*/
uint32_t __get_MTVEC(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mtvec" : "=r" (result) );
return (result);
}
/*********************************************************************
* @fn __set_MTVEC
*
* @brief Set the Machine Trap-Vector Base-Address Register
*
* @param value - set mtvec value
*
* @return none
*/
void __set_MTVEC(uint32_t value)
{
__ASM volatile ("csrw mtvec, %0" : : "r" (value) );
}
/*********************************************************************
* @fn __get_MSCRATCH
*
* @brief Return the Machine Seratch Register
*
* @return mscratch value
*/
uint32_t __get_MSCRATCH(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mscratch" : "=r" (result) );
return (result);
}
/*********************************************************************
* @fn __set_MSCRATCH
*
* @brief Set the Machine Seratch Register
*
* @param value - set mscratch value
*
* @return none
*/
void __set_MSCRATCH(uint32_t value)
{
__ASM volatile ("csrw mscratch, %0" : : "r" (value) );
}
/*********************************************************************
* @fn __get_MEPC
*
* @brief Return the Machine Exception Program Register
*
* @return mepc value
*/
uint32_t __get_MEPC(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mepc" : "=r" (result) );
return (result);
}
/*********************************************************************
* @fn __set_MEPC
*
* @brief Set the Machine Exception Program Register
*
* @return mepc value
*/
void __set_MEPC(uint32_t value)
{
__ASM volatile ("csrw mepc, %0" : : "r" (value) );
}
/*********************************************************************
* @fn __get_MCAUSE
*
* @brief Return the Machine Cause Register
*
* @return mcause value
*/
uint32_t __get_MCAUSE(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mcause" : "=r" (result) );
return (result);
}
/*********************************************************************
* @fn __set_MEPC
*
* @brief Set the Machine Cause Register
*
* @return mcause value
*/
void __set_MCAUSE(uint32_t value)
{
__ASM volatile ("csrw mcause, %0" : : "r" (value) );
}
/*********************************************************************
* @fn __get_MTVAL
*
* @brief Return the Machine Trap Value Register
*
* @return mtval value
*/
uint32_t __get_MTVAL(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mtval" : "=r" (result) );
return (result);
}
/*********************************************************************
* @fn __set_MTVAL
*
* @brief Set the Machine Trap Value Register
*
* @return mtval value
*/
void __set_MTVAL(uint32_t value)
{
__ASM volatile ("csrw mtval, %0" : : "r" (value) );
}
/*********************************************************************
* @fn __get_MVENDORID
*
* @brief Return Vendor ID Register
*
* @return mvendorid value
*/
uint32_t __get_MVENDORID(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) );
return (result);
}
/*********************************************************************
* @fn __get_MARCHID
*
* @brief Return Machine Architecture ID Register
*
* @return marchid value
*/
uint32_t __get_MARCHID(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "marchid" : "=r" (result) );
return (result);
}
/*********************************************************************
* @fn __get_MIMPID
*
* @brief Return Machine Implementation ID Register
*
* @return mimpid value
*/
uint32_t __get_MIMPID(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mimpid" : "=r" (result) );
return (result);
}
/*********************************************************************
* @fn __get_MHARTID
*
* @brief Return Hart ID Register
*
* @return mhartid value
*/
uint32_t __get_MHARTID(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mhartid" : "=r" (result) );
return (result);
}
/*********************************************************************
* @fn __get_SP
*
* @brief Return SP Register
*
* @return SP value
*/
uint32_t __get_SP(void)
{
uint32_t result;
__ASM volatile ( "mv %0," "sp" : "=r"(result) : );
return (result);
}

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/********************************** (C) COPYRIGHT *******************************
* File Name : core_riscv.h
* Author : WCH
* Version : V1.0.1
* Date : 2023/11/11
* Description : RISC-V V4 Core Peripheral Access Layer Header File for CH32V20x
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CORE_RISCV_H__
#define __CORE_RISCV_H__
#ifdef __cplusplus
extern "C" {
#endif
/* IO definitions */
#ifdef __cplusplus
#define __I volatile /* defines 'read only' permissions */
#else
#define __I volatile const /* defines 'read only' permissions */
#endif
#define __O volatile /* defines 'write only' permissions */
#define __IO volatile /* defines 'read / write' permissions */
/* Standard Peripheral Library old types (maintained for legacy purpose) */
typedef __I uint64_t vuc64; /* Read Only */
typedef __I uint32_t vuc32; /* Read Only */
typedef __I uint16_t vuc16; /* Read Only */
typedef __I uint8_t vuc8; /* Read Only */
typedef const uint64_t uc64; /* Read Only */
typedef const uint32_t uc32; /* Read Only */
typedef const uint16_t uc16; /* Read Only */
typedef const uint8_t uc8; /* Read Only */
typedef __I int64_t vsc64; /* Read Only */
typedef __I int32_t vsc32; /* Read Only */
typedef __I int16_t vsc16; /* Read Only */
typedef __I int8_t vsc8; /* Read Only */
typedef const int64_t sc64; /* Read Only */
typedef const int32_t sc32; /* Read Only */
typedef const int16_t sc16; /* Read Only */
typedef const int8_t sc8; /* Read Only */
typedef __IO uint64_t vu64;
typedef __IO uint32_t vu32;
typedef __IO uint16_t vu16;
typedef __IO uint8_t vu8;
typedef uint64_t u64;
typedef uint32_t u32;
typedef uint16_t u16;
typedef uint8_t u8;
typedef __IO int64_t vs64;
typedef __IO int32_t vs32;
typedef __IO int16_t vs16;
typedef __IO int8_t vs8;
typedef int64_t s64;
typedef int32_t s32;
typedef int16_t s16;
typedef int8_t s8;
typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus;
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
#define RV_STATIC_INLINE static inline
/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
typedef struct{
__I uint32_t ISR[8];
__I uint32_t IPR[8];
__IO uint32_t ITHRESDR;
__IO uint32_t RESERVED;
__IO uint32_t CFGR;
__I uint32_t GISR;
__IO uint8_t VTFIDR[4];
uint8_t RESERVED0[12];
__IO uint32_t VTFADDR[4];
uint8_t RESERVED1[0x90];
__O uint32_t IENR[8];
uint8_t RESERVED2[0x60];
__O uint32_t IRER[8];
uint8_t RESERVED3[0x60];
__O uint32_t IPSR[8];
uint8_t RESERVED4[0x60];
__O uint32_t IPRR[8];
uint8_t RESERVED5[0x60];
__IO uint32_t IACTR[8];
uint8_t RESERVED6[0xE0];
__IO uint8_t IPRIOR[256];
uint8_t RESERVED7[0x810];
__IO uint32_t SCTLR;
}PFIC_Type;
/* memory mapped structure for SysTick */
typedef struct
{
__IO uint32_t CTLR;
__IO uint32_t SR;
__IO uint64_t CNT;
__IO uint64_t CMP;
}SysTick_Type;
#define PFIC ((PFIC_Type *) 0xE000E000 )
#define NVIC PFIC
#define NVIC_KEY1 ((uint32_t)0xFA050000)
#define NVIC_KEY2 ((uint32_t)0xBCAF0000)
#define NVIC_KEY3 ((uint32_t)0xBEEF0000)
#define SysTick ((SysTick_Type *) 0xE000F000)
/*********************************************************************
* @fn __enable_irq
*
* @brief Enable Global Interrupt
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq()
{
__asm volatile ("csrs 0x800, %0" : : "r" (0x88) );
}
/*********************************************************************
* @fn __disable_irq
*
* @brief Disable Global Interrupt
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq()
{
__asm volatile ("csrc 0x800, %0" : : "r" (0x88) );
}
/*********************************************************************
* @fn __NOP
*
* @brief nop
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP()
{
__asm volatile ("nop");
}
/*********************************************************************
* @fn NVIC_EnableIRQ
*
* @brief Enable Interrupt
*
* @param IRQn - Interrupt Numbers
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/*********************************************************************
* @fn NVIC_DisableIRQ
*
* @brief Disable Interrupt
*
* @param IRQn - Interrupt Numbers
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/*********************************************************************
* @fn NVIC_GetStatusIRQ
*
* @brief Get Interrupt Enable State
*
* @param IRQn - Interrupt Numbers
*
* @return 1 - Interrupt Pending Enable
* 0 - Interrupt Pending Disable
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/*********************************************************************
* @fn NVIC_GetPendingIRQ
*
* @brief Get Interrupt Pending State
*
* @param IRQn - Interrupt Numbers
*
* @return 1 - Interrupt Pending Enable
* 0 - Interrupt Pending Disable
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/*********************************************************************
* @fn NVIC_SetPendingIRQ
*
* @brief Set Interrupt Pending
*
* @param IRQn - Interrupt Numbers
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/*********************************************************************
* @fn NVIC_ClearPendingIRQ
*
* @brief Clear Interrupt Pending
*
* @param IRQn - Interrupt Numbers
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/*********************************************************************
* @fn NVIC_GetActive
*
* @brief Get Interrupt Active State
*
* @param IRQn - Interrupt Numbers
*
* @return 1 - Interrupt Active
* 0 - Interrupt No Active
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
{
return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/*********************************************************************
* @fn NVIC_SetPriority
*
* @brief Set Interrupt Priority
*
* @param IRQn - Interrupt Numbers
* interrupt nesting enable(CSR-0x804 bit1 = 1)
* priority - bit[7] - Preemption Priority
* bit[6:5] - Sub priority
* bit[4:0] - Reserve
* interrupt nesting disable(CSR-0x804 bit1 = 0)
* priority - bit[7:5] - Sub priority
* bit[4:0] - Reserve
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
{
NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
}
/*********************************************************************
* @fn __WFI
*
* @brief Wait for Interrupt
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
{
NVIC->SCTLR &= ~(1<<3); // wfi
asm volatile ("wfi");
}
/*********************************************************************
* @fn _SEV
*
* @brief Set Event
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void)
{
NVIC->SCTLR |= (1<<5);
}
/*********************************************************************
* @fn _WFE
*
* @brief Wait for Events
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void)
{
uint32_t tmp= NVIC->SCTLR;
tmp &= ~(1<<5);
tmp |= (1<<3);
NVIC->SCTLR = tmp;
asm volatile ("wfi");
}
/*********************************************************************
* @fn __WFE
*
* @brief Wait for Events
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
{
_SEV();
_WFE();
_WFE();
if(*(vu32*)(0x40023800) & (1<<6))
{
NVIC->SCTLR |= (1<<5);
}
}
/*********************************************************************
* @fn SetVTFIRQ
*
* @brief Set VTF Interrupt
*
* @param addr - VTF interrupt service function base address.
* IRQn - Interrupt Numbers
* num - VTF Interrupt Numbers
* NewState - DISABLE or ENABLE
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState)
{
if(num > 3) return ;
if (NewState != DISABLE)
{
NVIC->VTFIDR[num] = IRQn;
NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1);
}
else
{
NVIC->VTFIDR[num] = IRQn;
NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1));
}
}
/*********************************************************************
* @fn NVIC_SystemReset
*
* @brief Initiate a system reset request
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void)
{
NVIC->CFGR = NVIC_KEY3|(1<<7);
}
/*********************************************************************
* @fn __AMOADD_W
*
* @brief Atomic Add with 32bit value
* Atomically ADD 32bit value with value in memory using amoadd.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* value - value to be ADDed
*
* @return return memory value + add value
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value)
{
int32_t result;
__asm volatile ("amoadd.w %0, %2, %1" : \
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr;
}
/*********************************************************************
* @fn __AMOAND_W
*
* @brief Atomic And with 32bit value
* Atomically AND 32bit value with value in memory using amoand.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* value - value to be ANDed
*
* @return return memory value & and value
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value)
{
int32_t result;
__asm volatile ("amoand.w %0, %2, %1" : \
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr;
}
/*********************************************************************
* @fn __AMOMAX_W
*
* @brief Atomic signed MAX with 32bit value
* Atomically signed max compare 32bit value with value in memory using amomax.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* value - value to be compared
*
* @return the bigger value
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value)
{
int32_t result;
__asm volatile ("amomax.w %0, %2, %1" : \
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr;
}
/*********************************************************************
* @fn __AMOMAXU_W
*
* @brief Atomic unsigned MAX with 32bit value
* Atomically unsigned max compare 32bit value with value in memory using amomaxu.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* value - value to be compared
*
* @return return the bigger value
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value)
{
uint32_t result;
__asm volatile ("amomaxu.w %0, %2, %1" : \
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr;
}
/*********************************************************************
* @fn __AMOMIN_W
*
* @brief Atomic signed MIN with 32bit value
* Atomically signed min compare 32bit value with value in memory using amomin.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* value - value to be compared
*
* @return the smaller value
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value)
{
int32_t result;
__asm volatile ("amomin.w %0, %2, %1" : \
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr;
}
/*********************************************************************
* @fn __AMOMINU_W
*
* @brief Atomic unsigned MIN with 32bit value
* Atomically unsigned min compare 32bit value with value in memory using amominu.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* value - value to be compared
*
* @return the smaller value
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value)
{
uint32_t result;
__asm volatile ("amominu.w %0, %2, %1" : \
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr;
}
/*********************************************************************
* @fn __AMOOR_W
*
* @brief Atomic OR with 32bit value
* Atomically OR 32bit value with value in memory using amoor.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* value - value to be ORed
*
* @return return memory value | and value
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value)
{
int32_t result;
__asm volatile ("amoor.w %0, %2, %1" : \
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr;
}
/*********************************************************************
* @fn __AMOSWAP_W
*
* @brief Atomically swap new 32bit value into memory using amoswap.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* newval - New value to be stored into the address
*
* @return return the original value in memory
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval)
{
uint32_t result;
__asm volatile ("amoswap.w %0, %2, %1" : \
"=r"(result), "+A"(*addr) : "r"(newval) : "memory");
return result;
}
/*********************************************************************
* @fn __AMOXOR_W
*
* @brief Atomic XOR with 32bit value
* Atomically XOR 32bit value with value in memory using amoxor.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* value - value to be XORed
*
* @return return memory value ^ and value
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value)
{
int32_t result;
__asm volatile ("amoxor.w %0, %2, %1" : \
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr;
}
/* Core_Exported_Functions */
extern uint32_t __get_MSTATUS(void);
extern void __set_MSTATUS(uint32_t value);
extern uint32_t __get_MISA(void);
extern void __set_MISA(uint32_t value);
extern uint32_t __get_MTVEC(void);
extern void __set_MTVEC(uint32_t value);
extern uint32_t __get_MSCRATCH(void);
extern void __set_MSCRATCH(uint32_t value);
extern uint32_t __get_MEPC(void);
extern void __set_MEPC(uint32_t value);
extern uint32_t __get_MCAUSE(void);
extern void __set_MCAUSE(uint32_t value);
extern uint32_t __get_MTVAL(void);
extern void __set_MTVAL(uint32_t value);
extern uint32_t __get_MVENDORID(void);
extern uint32_t __get_MARCHID(void);
extern uint32_t __get_MIMPID(void);
extern uint32_t __get_MHARTID(void);
extern uint32_t __get_SP(void);
#ifdef __cplusplus
}
#endif
#endif

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SRC_FILES := debug.c
include $(KERNEL_ROOT)/compiler.mk

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/********************************** (C) COPYRIGHT *******************************
* File Name : debug.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for UART
* Printf , Delay functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "debug.h"
#include <stddef.h>
static uint8_t p_us = 0;
static uint16_t p_ms = 0;
// 定义一个结构体保存所有状态
typedef struct {
uint32_t SR;
uint32_t CMP;
uint32_t CTLR;
} SysTickState;
// 定义一个静态变量保存原始状态
static SysTickState originalSysTickState = {0};
#define DEBUG_DATA0_ADDRESS ((volatile uint32_t*)0xE0000380)
#define DEBUG_DATA1_ADDRESS ((volatile uint32_t*)0xE0000384)
/*********************************************************************
* @fn Delay_Init
*
* @brief Initializes Delay Funcation.
*
* @return none
*/
void Delay_Init(void)
{
p_us = SystemCoreClock / 8000000;
p_ms = (uint16_t)p_us * 1000;
}
/*********************************************************************
* @fn Delay_Us
*
* @brief Microsecond Delay Time.
*
* @param n - Microsecond number.
*
* @return None
*/
void Delay_Us(uint32_t n)
{
uint32_t i;
// 保存SysTick所有相关状态
SysTick->CTLR = 0; // 停止SysTick计数器
u64 systick_cmp = SysTick->CMP;
u32 systick_sr = SysTick->SR;
SysTick->SR &= ~(1 << 0);
i = (uint32_t)n * p_us;
SysTick->CMP = i;
SysTick->CTLR |= (1 << 4);
SysTick->CTLR |= (1 << 5) | (1 << 0);
while((SysTick->SR & (1 << 0)) != (1 << 0));
SysTick->CTLR &= ~(1 << 0);
// 恢复SysTick所有状态
SysTick->SR = systick_sr; // 恢复状态寄存器状态，注意清中断位的操作应根据实际情况调整
SysTick->CMP = systick_cmp; // 恢复比较值
SysTick->CTLR = 0xF; // 开启SysTick计数器
}
/*********************************************************************
* @fn Delay_Ms
*
* @brief Millisecond Delay Time.
*
* @param n - Millisecond number.
*
* @return None
*/
void Delay_Ms(uint32_t n)
{
uint32_t i;
// 保存SysTick所有相关状态
SysTick->CTLR = 0; // 停止SysTick计数器
u64 systick_cmp = SysTick->CMP;
u32 systick_sr = SysTick->SR;
SysTick->SR &= ~(1 << 0);
i = (uint32_t)n * p_ms;
SysTick->CMP = i;
SysTick->CTLR |= (1 << 4);
SysTick->CTLR |= (1 << 5) | (1 << 0);
while((SysTick->SR & (1 << 0)) != (1 << 0));
SysTick->CTLR &= ~(1 << 0);
// 恢复SysTick所有状态
SysTick->SR = systick_sr; // 恢复状态寄存器状态，注意清中断位的操作应根据实际情况调整
SysTick->CMP = systick_cmp; // 恢复比较值
SysTick->CTLR = 0xF; // 开启SysTick计数器
}
/*********************************************************************
* @fn USART_Printf_Init
*
* @brief Initializes the USARTx peripheral.
*
* @param baudrate - USART communication baud rate.
*
* @return None
*/
void USART_Printf_Init(uint32_t baudrate)
{
GPIO_InitTypeDef GPIO_InitStructure;
USART_InitTypeDef USART_InitStructure;
#if(DEBUG == DEBUG_UART1)
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOA, &GPIO_InitStructure);
#elif(DEBUG == DEBUG_UART2)
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOA, &GPIO_InitStructure);
#elif(DEBUG == DEBUG_UART3)
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOB, &GPIO_InitStructure);
#endif
USART_InitStructure.USART_BaudRate = baudrate;
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
USART_InitStructure.USART_StopBits = USART_StopBits_1;
USART_InitStructure.USART_Parity = USART_Parity_No;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Tx;
#if(DEBUG == DEBUG_UART1)
USART_Init(USART1, &USART_InitStructure);
USART_Cmd(USART1, ENABLE);
#elif(DEBUG == DEBUG_UART2)
USART_Init(USART2, &USART_InitStructure);
USART_Cmd(USART2, ENABLE);
#elif(DEBUG == DEBUG_UART3)
USART_Init(USART3, &USART_InitStructure);
USART_Cmd(USART3, ENABLE);
#endif
}
/*********************************************************************
* @fn SDI_Printf_Enable
*
* @brief Initializes the SDI printf Function.
*
* @param None
*
* @return None
*/
void SDI_Printf_Enable(void)
{
*(DEBUG_DATA0_ADDRESS) = 0;
Delay_Init();
Delay_Ms(1);
}
/*********************************************************************
* @fn _write
*
* @brief Support Printf Function
*
* @param *buf - UART send Data.
* size - Data length
*
* @return size: Data length
*/
__attribute__((used))
int _write(int fd, char *buf, int size)
{
int i = 0;
#if (SDI_PRINT == SDI_PR_OPEN)
int writeSize = size;
do
{
/**
* data0 data1 8 byte
* data0 The storage length of the lowest byte, with a maximum of 7 bytes.
*/
while( (*(DEBUG_DATA0_ADDRESS) != 0u))
{
}
if(writeSize>7)
{
*(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24);
*(DEBUG_DATA0_ADDRESS) = (7u) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24);
i += 7;
writeSize -= 7;
}
else
{
*(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24);
*(DEBUG_DATA0_ADDRESS) = (writeSize) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24);
writeSize = 0;
}
} while (writeSize);
#else
for(i = 0; i < size; i++){
#if(DEBUG == DEBUG_UART1)
while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET);
USART_SendData(USART1, *buf++);
#elif(DEBUG == DEBUG_UART2)
while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET);
USART_SendData(USART2, *buf++);
#elif(DEBUG == DEBUG_UART3)
while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET);
USART_SendData(USART3, *buf++);
#endif
}
#endif
return size;
}
/*********************************************************************
* @fn _sbrk
*
* @brief Change the spatial position of data segment.
*
* @return size: Data length
*/
__attribute__((used))
void *_sbrk(ptrdiff_t incr)
{
extern char _end[];
extern char _heap_end[];
static char *curbrk = _end;
if ((curbrk + incr < _end) || (curbrk + incr > _heap_end))
return NULL - 1;
curbrk += incr;
return curbrk - incr;
}

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/********************************** (C) COPYRIGHT *******************************
* File Name : debug.h
* Author : WCH
* Version : V1.0.0
* Date : 2023/10/24
* Description : This file contains all the functions prototypes for UART
* Printf , Delay functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __DEBUG_H
#define __DEBUG_H
#include "stdio.h"
#include "ch32v20x.h"
#ifdef __cplusplus
extern "C" {
#endif
/* UART Printf Definition */
#define DEBUG_UART1 1
#define DEBUG_UART2 2
#define DEBUG_UART3 3
/* DEBUG UATR Definition */
#ifndef DEBUG
#define DEBUG DEBUG_UART1
#endif
/* SDI Printf Definition */
#define SDI_PR_CLOSE 0
#define SDI_PR_OPEN 1
#ifndef SDI_PRINT
#define SDI_PRINT SDI_PR_CLOSE
#endif
void Delay_Init(void);
void Delay_Us(uint32_t n);
void Delay_Ms(uint32_t n);
void USART_Printf_Init(uint32_t baudrate);
void SDI_Printf_Enable(void);
#if(DEBUG)
#define PRINT(format, ...) printf(format, ##__VA_ARGS__)
#else
#define PRINT(X...)
#endif
#ifdef __cplusplus
}
#endif
#endif

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SRC_FILES := boot.S interrupt.c tick.c switch.S prepare_rhwstack.c interrupt_switch.S ble_task_scheduler.S
SRC_DIR := Core User Debug
# interrupt_switch.S
include $(KERNEL_ROOT)/compiler.mk

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SRC_FILES := ch32v20x_it.c system_ch32v20x.c
include $(KERNEL_ROOT)/compiler.mk

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_conf.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : Library configuration file.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_CONF_H
#define __CH32V20x_CONF_H
#include "ch32v20x_adc.h"
#include "ch32v20x_bkp.h"
#include "ch32v20x_can.h"
#include "ch32v20x_crc.h"
#include "ch32v20x_dbgmcu.h"
#include "ch32v20x_dma.h"
#include "ch32v20x_exti.h"
#include "ch32v20x_flash.h"
#include "ch32v20x_gpio.h"
#include "ch32v20x_i2c.h"
#include "ch32v20x_iwdg.h"
#include "ch32v20x_pwr.h"
#include "ch32v20x_rcc.h"
#include "ch32v20x_rtc.h"
#include "ch32v20x_spi.h"
#include "ch32v20x_tim.h"
#include "ch32v20x_usart.h"
#include "ch32v20x_wwdg.h"
#include "ch32v20x_it.h"
#include "ch32v20x_misc.h"
#endif /* __CH32V20x_CONF_H */

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_it.c
* Author : WCH
* Version : V1.0.0
* Date : 2023/12/29
* Description : Main Interrupt Service Routines.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "ch32v20x_it.h"
#include "board.h"
#include "ch32v20x_exti.h"
#include "ch32v20x_tim.h"
#include "eth_driver.h"
#include <xs_isr.h>
#include "wchble.h"
void NMI_Handler(void) __attribute__((interrupt()));
void HardFault_Handler(void) __attribute__((interrupt()));
void ETH_IRQHandler(void) __attribute__((interrupt()));
void TIM2_IRQHandler(void) __attribute__((interrupt()));
void BB_IRQHandler(void) __attribute__((interrupt()));
/*********************************************************************
* @fn NMI_Handler
*
* @brief This function handles NMI exception.
*
* @return none
*/
void NMI_Handler(void)
{
GET_INT_SP();
isrManager.done->incCounter();
KPrintf("NMI_Handler.\n");
isrManager.done->decCounter();
FREE_INT_SP();
}
/*********************************************************************
* @fn HardFault_Handler
*
* @brief This function handles Hard Fault exception.
*
* @return none
*/
void HardFault_Handler(void)
{
GET_INT_SP();
isrManager.done->incCounter();
KPrintf("HardFault_Handler.\n");
KPrintf("mepc :%08x\r\n", __get_MEPC());
KPrintf("mcause:%08x\r\n", __get_MCAUSE());
KPrintf("mtval :%08x\r\n", __get_MTVAL());
extern void ShowTask(void);
extern void ShowMemory(void);
ShowTask();
ShowMemory();
while (1)
;
isrManager.done->decCounter();
FREE_INT_SP();
}
/*********************************************************************
* @fn ETH_IRQHandler
*
* @brief This function handles ETH exception.
*
* @return none
*/
#ifdef BSP_USING_ETH
void ETH_IRQHandler(void)
{
WCHNET_ETHIsr();
}
/*********************************************************************
* @fn TIM2_IRQHandler
*
* @brief This function handles TIM2 exception.
*
* @return none
*/
u32 timeCnt;
void TIM2_IRQHandler(void)
{
timeCnt++;
WCHNET_TimeIsr(WCHNETTIMERPERIOD);
TIM_ClearITPendingBit(TIM2, TIM_IT_Update);
}
#endif
/*********************************************************************
* @fn BB_IRQHandler
*
* @brief BB Interrupt for BLE.
*
* @return None
*/
#ifdef BSP_USING_BLE
void BB_IRQHandler(void)
{
BB_IRQLibHandler();
}
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_it.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains the headers of the interrupt handlers.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_IT_H
#define __CH32V20x_IT_H
#include "debug.h"
#define GET_INT_SP() asm("csrrw sp,mscratch,sp")
#define FREE_INT_SP() asm("csrrw sp,mscratch,sp")
#endif /* __CH32V20x_IT_H */

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Ubiquitous/XiZi_IIoT/arch/risc-v/ch32v208rbt6/User/system_ch32v20x.c Normal file
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/********************************** (C) COPYRIGHT *******************************
* File Name : system_ch32v20x.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
* For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "ch32v20x.h"
/*
* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
* reset the HSI is used as SYSCLK source).
* If none of the define below is enabled, the HSI is used as System clock source.
*/
//#define SYSCLK_FREQ_HSE HSE_VALUE
//#define SYSCLK_FREQ_48MHz_HSE 48000000
//#define SYSCLK_FREQ_56MHz_HSE 56000000
//#define SYSCLK_FREQ_72MHz_HSE 72000000
//#define SYSCLK_FREQ_96MHz_HSE 96000000
#define SYSCLK_FREQ_120MHz_HSE 120000000
//#define SYSCLK_FREQ_144MHz_HSE 144000000
//#define SYSCLK_FREQ_HSI HSI_VALUE
//#define SYSCLK_FREQ_48MHz_HSI 48000000
//#define SYSCLK_FREQ_56MHz_HSI 56000000
//#define SYSCLK_FREQ_72MHz_HSI 72000000
// #define SYSCLK_FREQ_96MHz_HSI 96000000
// #define SYSCLK_FREQ_120MHz_HSI 120000000
//#define SYSCLK_FREQ_144MHz_HSI 144000000
/* Clock Definitions */
#ifdef SYSCLK_FREQ_HSE
uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_48MHz_HSE
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_56MHz_HSE
uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_72MHz_HSE
uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_96MHz_HSE
uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSE; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_120MHz_HSE
uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSE; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_144MHz_HSE
uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSE; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_48MHz_HSI
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_56MHz_HSI
uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_72MHz_HSI
uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_96MHz_HSI
uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSI; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_120MHz_HSI
uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSI; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_144MHz_HSI
uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSI; /* System Clock Frequency (Core Clock) */
#else
uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */
#endif
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/* system_private_function_proto_types */
static void SetSysClock(void);
#ifdef SYSCLK_FREQ_HSE
static void SetSysClockToHSE( void );
#elif defined SYSCLK_FREQ_48MHz_HSE
static void SetSysClockTo48_HSE( void );
#elif defined SYSCLK_FREQ_56MHz_HSE
static void SetSysClockTo56_HSE( void );
#elif defined SYSCLK_FREQ_72MHz_HSE
static void SetSysClockTo72_HSE( void );
#elif defined SYSCLK_FREQ_96MHz_HSE
static void SetSysClockTo96_HSE( void );
#elif defined SYSCLK_FREQ_120MHz_HSE
static void SetSysClockTo120_HSE( void );
#elif defined SYSCLK_FREQ_144MHz_HSE
static void SetSysClockTo144_HSE( void );
#elif defined SYSCLK_FREQ_48MHz_HSI
static void SetSysClockTo48_HSI( void );
#elif defined SYSCLK_FREQ_56MHz_HSI
static void SetSysClockTo56_HSI( void );
#elif defined SYSCLK_FREQ_72MHz_HSI
static void SetSysClockTo72_HSI( void );
#elif defined SYSCLK_FREQ_96MHz_HSI
static void SetSysClockTo96_HSI( void );
#elif defined SYSCLK_FREQ_120MHz_HSI
static void SetSysClockTo120_HSI( void );
#elif defined SYSCLK_FREQ_144MHz_HSI
static void SetSysClockTo144_HSI( void );
#endif
/*********************************************************************
* @fn SystemInit
*
* @brief Setup the microcontroller system Initialize the Embedded Flash Interface,
* the PLL and update the SystemCoreClock variable.
*
* @return none
*/
void SystemInit (void)
{
RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 &= (uint32_t)0xF0FF0000;
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
RCC->CFGR0 &= (uint32_t)0xFF00FFFF;
RCC->INTR = 0x009F0000;
SetSysClock();
}
/*********************************************************************
* @fn SystemCoreClockUpdate
*
* @brief Update SystemCoreClock variable according to Clock Register Values.
*
* @return none
*/
void SystemCoreClockUpdate (void)
{
uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
tmp = RCC->CFGR0 & RCC_SWS;
switch (tmp)
{
case 0x00:
SystemCoreClock = HSI_VALUE;
break;
case 0x04:
SystemCoreClock = HSE_VALUE;
break;
case 0x08:
pllmull = RCC->CFGR0 & RCC_PLLMULL;
pllsource = RCC->CFGR0 & RCC_PLLSRC;
pllmull = ( pllmull >> 18) + 2;
if(pllmull == 17) pllmull = 18;
if (pllsource == 0x00)
{
if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){
SystemCoreClock = HSI_VALUE * pllmull;
}
else{
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
}
}
else
{
#if defined (CH32V20x_D8W)
if((RCC->CFGR0 & (3<<22)) == (3<<22))
{
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
}
else
#endif
if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
{
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull;
#else
SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
#endif
}
else
{
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
SystemCoreClock = (HSE_VALUE>>2) * pllmull;
#else
SystemCoreClock = HSE_VALUE * pllmull;
#endif
}
}
if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
SystemCoreClock >>= tmp;
}
/*********************************************************************
* @fn SetSysClock
*
* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClock(void)
{
//GPIO_IPD_Unused();
#ifdef SYSCLK_FREQ_HSE
SetSysClockToHSE();
#elif defined SYSCLK_FREQ_48MHz_HSE
SetSysClockTo48_HSE();
#elif defined SYSCLK_FREQ_56MHz_HSE
SetSysClockTo56_HSE();
#elif defined SYSCLK_FREQ_72MHz_HSE
SetSysClockTo72_HSE();
#elif defined SYSCLK_FREQ_96MHz_HSE
SetSysClockTo96_HSE();
#elif defined SYSCLK_FREQ_120MHz_HSE
SetSysClockTo120_HSE();
#elif defined SYSCLK_FREQ_144MHz_HSE
SetSysClockTo144_HSE();
#elif defined SYSCLK_FREQ_48MHz_HSI
SetSysClockTo48_HSI();
#elif defined SYSCLK_FREQ_56MHz_HSI
SetSysClockTo56_HSI();
#elif defined SYSCLK_FREQ_72MHz_HSI
SetSysClockTo72_HSI();
#elif defined SYSCLK_FREQ_96MHz_HSI
SetSysClockTo96_HSI();
#elif defined SYSCLK_FREQ_120MHz_HSI
SetSysClockTo120_HSI();
#elif defined SYSCLK_FREQ_144MHz_HSI
SetSysClockTo144_HSI();
#endif
/* If none of the define above is enabled, the HSI is used as System clock
* source (default after reset)
*/
}
#ifdef SYSCLK_FREQ_HSE
/*********************************************************************
* @fn SetSysClockToHSE
*
* @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockToHSE(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
/* Select HSE as system clock source
* CH32V20x_D6 (HSE=8MHZ)
* CH32V20x_D8 (HSE=32MHZ)
* CH32V20x_D8W (HSE=32MHZ)
*/
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
/* Wait till HSE is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
{
}
}
else
{
/* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
#elif defined SYSCLK_FREQ_48MHz_HSE
/*********************************************************************
* @fn SetSysClockTo48_HSE
*
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo48_HSE(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ)
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
*/
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
else
{
/*
* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
#elif defined SYSCLK_FREQ_56MHz_HSE
/*********************************************************************
* @fn SetSysClockTo56_HSE
*
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo56_HSE(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
*/
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
else
{
/*
* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
#elif defined SYSCLK_FREQ_72MHz_HSE
/*********************************************************************
* @fn SetSysClockTo72_HSE
*
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo72_HSE(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
*/
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
else
{
/*
* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
#elif defined SYSCLK_FREQ_96MHz_HSE
/*********************************************************************
* @fn SetSysClockTo96_HSE
*
* @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo96_HSE(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
*/
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
else
{
/*
* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
#elif defined SYSCLK_FREQ_120MHz_HSE
/*********************************************************************
* @fn SetSysClockTo120_HSE
*
* @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo120_HSE(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if(HSEStatus == (uint32_t)0x01)
{
#if defined (CH32V20x_D8W)
RCC->CFGR0 |= (uint32_t)(3<<22);
/* HCLK = SYSCLK/2 */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;
#else
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
#endif
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8MHZ)
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 15 = 120 MHz (HSE=32MHZ)
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz (HSE=32MHZ)
*/
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
else
{
/*
* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
#elif defined SYSCLK_FREQ_144MHz_HSE
/*********************************************************************
* @fn SetSysClockTo144_HSE
*
* @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo144_HSE(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
*/
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
else
{
/*
* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
#elif defined SYSCLK_FREQ_48MHz_HSI
/*********************************************************************
* @fn SetSysClockTo48_HSI
*
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo48_HSI(void)
{
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
#elif defined SYSCLK_FREQ_56MHz_HSI
/*********************************************************************
* @fn SetSysClockTo56_HSI
*
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo56_HSI(void)
{
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* PLL configuration: PLLCLK = HSI * 7 = 48 MHz */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
#elif defined SYSCLK_FREQ_72MHz_HSI
/*********************************************************************
* @fn SetSysClockTo72_HSI
*
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo72_HSI(void)
{
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
#elif defined SYSCLK_FREQ_96MHz_HSI
/*********************************************************************
* @fn SetSysClockTo96_HSI
*
* @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo96_HSI(void)
{
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* PLL configuration: PLLCLK = HSI * 12 = 96 MHz */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
#elif defined SYSCLK_FREQ_120MHz_HSI
/*********************************************************************
* @fn SetSysClockTo120_HSI
*
* @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo120_HSI(void)
{
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* PLL configuration: PLLCLK = HSI * 15 = 120 MHz */
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
#elif defined SYSCLK_FREQ_144MHz_HSI
/*********************************************************************
* @fn SetSysClockTo144_HSI
*
* @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo144_HSI(void)
{
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* PLL configuration: PLLCLK = HSI * 18 = 144 MHz */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
#endif

32
Ubiquitous/XiZi_IIoT/arch/risc-v/ch32v208rbt6/User/system_ch32v20x.h Normal file
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/********************************** (C) COPYRIGHT *******************************
* File Name : system_ch32v20x.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Header File.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __SYSTEM_ch32v20x_H
#define __SYSTEM_ch32v20x_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
/* System_Exported_Functions */
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif /*__CH32V20x_SYSTEM_H */

13
Ubiquitous/XiZi_IIoT/arch/risc-v/ch32v208rbt6/arch_interrupt.h Normal file
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#ifndef ARCH_INTERRUPT_H__
#define ARCH_INTERRUPT_H__
#include "ch32v20x.h"
#include "core_riscv.h"
#define ARCH_MAX_IRQ_NUM 128
#define ARCH_IRQ_NUM_OFFSET 0
int ArchEnableHwIrq(uint32_t irq_num);
int ArchDisableHwIrq(uint32_t irq_num);
#endif

127
Ubiquitous/XiZi_IIoT/arch/risc-v/ch32v208rbt6/ble_task_scheduler.S Normal file
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.global Ecall_M_Mode_Handler
.global Ecall_U_Mode_Handler
.global LLE_IRQHandler
.extern g_LLE_IRQLibHandlerLocation
.section .highcode,"ax",@progbits
.align 2
.func
Ecall_M_Mode_Handler:
Ecall_U_Mode_Handler:
addi a1, x0, 0x20
csrs 0x804, a1
lw a1, 0 * 4( sp )
csrw mepc, a1
lw x1, 1 * 4( sp )
lw x4, 2 * 4( sp )
lw x5, 3 * 4( sp )
lw x6, 4 * 4( sp )
lw x7, 5 * 4( sp )
lw x8, 6 * 4( sp )
lw x9, 7 * 4( sp )
lw x10, 8 * 4( sp )
lw x11, 9 * 4( sp )
lw x12, 10 * 4( sp )
lw x13, 11 * 4( sp )
lw x14, 12 * 4( sp )
lw x15, 13 * 4( sp )
lw x16, 14 * 4( sp )
lw x17, 15 * 4( sp )
lw x18, 16 * 4( sp )
lw x19, 17 * 4( sp )
lw x20, 18 * 4( sp )
lw x21, 19 * 4( sp )
lw x22, 20 * 4( sp )
lw x23, 21 * 4( sp )
lw x24, 22 * 4( sp )
lw x25, 23 * 4( sp )
lw x26, 24 * 4( sp )
lw x27, 25 * 4( sp )
lw x28, 26 * 4( sp )
lw x29, 27 * 4( sp )
lw x30, 28 * 4( sp )
lw x31, 29 * 4( sp )
addi sp, sp, 32*4
mret
.endfunc
.section .highcode.LLE_IRQHandler,"ax",@progbits
.align 2
.func
LLE_IRQHandler:
addi sp, sp, -32*4
sw x1, 1 * 4( sp )
sw x4, 2 * 4( sp )
sw x5, 3 * 4( sp )
sw x6, 4 * 4( sp )
sw x7, 5 * 4( sp )
sw x8, 6 * 4( sp )
sw x9, 7 * 4( sp )
sw x10, 8 * 4( sp )
sw x11, 9 * 4( sp )
sw x12, 10 * 4( sp )
sw x13, 11 * 4( sp )
sw x14, 12 * 4( sp )
sw x15, 13 * 4( sp )
sw x16, 14 * 4( sp )
sw x17, 15 * 4( sp )
sw x18, 16 * 4( sp )
sw x19, 17 * 4( sp )
sw x20, 18 * 4( sp )
sw x21, 19 * 4( sp )
sw x22, 20 * 4( sp )
sw x23, 21 * 4( sp )
sw x24, 22 * 4( sp )
sw x25, 23 * 4( sp )
sw x26, 24 * 4( sp )
sw x27, 25 * 4( sp )
sw x28, 26 * 4( sp )
sw x29, 27 * 4( sp )
sw x30, 28 * 4( sp )
sw x31, 29 * 4( sp )
la a1, g_LLE_IRQLibHandlerLocation
lw a0, 0(a1)
jalr x1, 0(a0)
lw x1, 1 * 4( sp )
lw x4, 2 * 4( sp )
lw x5, 3 * 4( sp )
lw x6, 4 * 4( sp )
lw x7, 5 * 4( sp )
lw x8, 6 * 4( sp )
lw x9, 7 * 4( sp )
lw x10, 8 * 4( sp )
lw x11, 9 * 4( sp )
lw x12, 10 * 4( sp )
lw x13, 11 * 4( sp )
lw x14, 12 * 4( sp )
lw x15, 13 * 4( sp )
lw x16, 14 * 4( sp )
lw x17, 15 * 4( sp )
lw x18, 16 * 4( sp )
lw x19, 17 * 4( sp )
lw x20, 18 * 4( sp )
lw x21, 19 * 4( sp )
lw x22, 20 * 4( sp )
lw x23, 21 * 4( sp )
lw x24, 22 * 4( sp )
lw x25, 23 * 4( sp )
lw x26, 24 * 4( sp )
lw x27, 25 * 4( sp )
lw x28, 26 * 4( sp )
lw x29, 27 * 4( sp )
lw x30, 28 * 4( sp )
lw x31, 29 * 4( sp )
addi sp, sp, 32*4
mret
.endfunc

275
Ubiquitous/XiZi_IIoT/arch/risc-v/ch32v208rbt6/boot.S Normal file
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;/********************************** (C) COPYRIGHT *******************************
;* File Name : startup_ch32v20x_D8W.s
;* Author : WCH
;* Version : V1.0.1
;* Date : 2023/11/20
;* Description : CH32V208x
;* vector table for eclipse toolchain.
;*********************************************************************************
;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
;* Attention: This software (modified or not) and binary are used for
;* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
.section .init,"ax",@progbits
.global _start
.align 1
_start:
j handle_reset
.section .vector,"ax",@progbits
.align 1
_vector_base:
.option norvc;
.word _start
.word 0
.word NMI_Handler /* NMI */
.word HardFault_Handler /* Hard Fault */
.word 0
.word Ecall_M_Mode_Handler /* Ecall M Mode */
.word 0
.word 0
.word Ecall_U_Mode_Handler /* Ecall U Mode */
.word Break_Point_Handler /* Break Point */
.word 0
.word 0
.word SysTick_Handler /* SysTick */
.word 0
.word SW_Handler /* SW */
.word 0
/* External Interrupts */
.word WWDG_IRQHandler /* Window Watchdog */
.word PVD_IRQHandler /* PVD through EXTI Line detect */
.word TAMPER_IRQHandler /* TAMPER */
.word RTC_IRQHandler /* RTC */
.word FLASH_IRQHandler /* Flash */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line 0 */
.word EXTI1_IRQHandler /* EXTI Line 1 */
.word EXTI2_IRQHandler /* EXTI Line 2 */
.word EXTI3_IRQHandler /* EXTI Line 3 */
.word EXTI4_IRQHandler /* EXTI Line 4 */
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
.word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
.word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
.word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
.word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
.word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
.word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
.word ADC1_2_IRQHandler /* ADC1_2 */
.word USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */
.word USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
.word EXTI9_5_IRQHandler /* EXTI Line 9..5 */
.word TIM1_BRK_IRQHandler /* TIM1 Break */
.word TIM1_UP_IRQHandler /* TIM1 Update */
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* EXTI Line 15..10 */
.word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
.word USBWakeUp_IRQHandler /* USB Wake up from suspend */
.word USBFS_IRQHandler /* USBFS Break */
.word USBFSWakeUp_IRQHandler /* USBFS Wake up from suspend */
.word ETH_IRQHandler /* ETH global */
.word ETHWakeUp_IRQHandler /* ETH Wake up */
.word BB_IRQHandler /* BLE BB */
.word LLE_IRQHandler /* BLE LLE */
.word TIM5_IRQHandler /* TIM5 */
.word UART4_IRQHandler /* UART4 */
.word DMA1_Channel8_IRQHandler /* DMA1 Channel8 */
.word OSC32KCal_IRQHandler /* OSC32KCal */
.word OSCWakeUp_IRQHandler /* OSC Wake Up */
.option rvc;
.section .text.vector_handler, "ax", @progbits
.weak NMI_Handler /* NMI */
.weak HardFault_Handler /* Hard Fault */
.weak Ecall_M_Mode_Handler /* Ecall M Mode */
.weak Ecall_U_Mode_Handler /* Ecall U Mode */
.weak Break_Point_Handler /* Break Point */
.weak SysTick_Handler /* SysTick */
.weak SW_Handler /* SW */
.weak WWDG_IRQHandler /* Window Watchdog */
.weak PVD_IRQHandler /* PVD through EXTI Line detect */
.weak TAMPER_IRQHandler /* TAMPER */
.weak RTC_IRQHandler /* RTC */
.weak FLASH_IRQHandler /* Flash */
.weak RCC_IRQHandler /* RCC */
.weak EXTI0_IRQHandler /* EXTI Line 0 */
.weak EXTI1_IRQHandler /* EXTI Line 1 */
.weak EXTI2_IRQHandler /* EXTI Line 2 */
.weak EXTI3_IRQHandler /* EXTI Line 3 */
.weak EXTI4_IRQHandler /* EXTI Line 4 */
.weak DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
.weak DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
.weak DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
.weak DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
.weak DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
.weak DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
.weak DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
.weak ADC1_2_IRQHandler /* ADC1_2 */
.weak USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */
.weak USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
.weak CAN1_RX1_IRQHandler /* CAN1 RX1 */
.weak CAN1_SCE_IRQHandler /* CAN1 SCE */
.weak EXTI9_5_IRQHandler /* EXTI Line 9..5 */
.weak TIM1_BRK_IRQHandler /* TIM1 Break */
.weak TIM1_UP_IRQHandler /* TIM1 Update */
.weak TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
.weak TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.weak TIM2_IRQHandler /* TIM2 */
.weak TIM3_IRQHandler /* TIM3 */
.weak TIM4_IRQHandler /* TIM4 */
.weak I2C1_EV_IRQHandler /* I2C1 Event */
.weak I2C1_ER_IRQHandler /* I2C1 Error */
.weak I2C2_EV_IRQHandler /* I2C2 Event */
.weak I2C2_ER_IRQHandler /* I2C2 Error */
.weak SPI1_IRQHandler /* SPI1 */
.weak SPI2_IRQHandler /* SPI2 */
.weak USART1_IRQHandler /* USART1 */
.weak USART2_IRQHandler /* USART2 */
.weak USART3_IRQHandler /* USART3 */
.weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */
.weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
.weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */
.weak USBFS_IRQHandler /* USBFS */
.weak USBFSWakeUp_IRQHandler /* USBFS Wake Up */
.weak ETH_IRQHandler /* ETH global */
.weak ETHWakeUp_IRQHandler /* ETHWakeUp */
.weak BB_IRQHandler /* BLE BB */
.weak LLE_IRQHandler /* BLE LLE */
.weak TIM5_IRQHandler /* TIM5 */
.weak UART4_IRQHandler /* UART4 */
.weak DMA1_Channel8_IRQHandler /* DMA1 Channel8 */
.weak OSC32KCal_IRQHandler /* OSC32 KCal */
.weak OSCWakeUp_IRQHandler /* OSC Wake Up */
NMI_Handler:
HardFault_Handler:
Ecall_M_Mode_Handler:
Ecall_U_Mode_Handler:
Break_Point_Handler:
SysTick_Handler:
SW_Handler:
WWDG_IRQHandler:
PVD_IRQHandler:
TAMPER_IRQHandler:
RTC_IRQHandler:
FLASH_IRQHandler:
RCC_IRQHandler:
EXTI0_IRQHandler:
EXTI1_IRQHandler:
EXTI2_IRQHandler:
EXTI3_IRQHandler:
EXTI4_IRQHandler:
DMA1_Channel1_IRQHandler:
DMA1_Channel2_IRQHandler:
DMA1_Channel3_IRQHandler:
DMA1_Channel4_IRQHandler:
DMA1_Channel5_IRQHandler:
DMA1_Channel6_IRQHandler:
DMA1_Channel7_IRQHandler:
ADC1_2_IRQHandler:
USB_HP_CAN1_TX_IRQHandler:
USB_LP_CAN1_RX0_IRQHandler:
CAN1_RX1_IRQHandler:
CAN1_SCE_IRQHandler:
EXTI9_5_IRQHandler:
TIM1_BRK_IRQHandler:
TIM1_UP_IRQHandler:
TIM1_TRG_COM_IRQHandler:
TIM1_CC_IRQHandler:
TIM2_IRQHandler:
TIM3_IRQHandler:
TIM4_IRQHandler:
I2C1_EV_IRQHandler:
I2C1_ER_IRQHandler:
I2C2_EV_IRQHandler:
I2C2_ER_IRQHandler:
SPI1_IRQHandler:
SPI2_IRQHandler:
USART1_IRQHandler:
USART2_IRQHandler:
USART3_IRQHandler:
EXTI15_10_IRQHandler:
RTCAlarm_IRQHandler:
USBWakeUp_IRQHandler:
USBFS_IRQHandler:
USBFSWakeUp_IRQHandler:
ETH_IRQHandler:
ETHWakeUp_IRQHandler:
BB_IRQHandler:
LLE_IRQHandler:
TIM5_IRQHandler:
UART4_IRQHandler:
DMA1_Channel8_IRQHandler:
OSC32KCal_IRQHandler:
OSCWakeUp_IRQHandler:
1:
j 1b
.section .text.handle_reset,"ax",@progbits
.weak handle_reset
.align 1
handle_reset:
.option push
.option norelax
la gp, __global_pointer$
.option pop
1:
la sp, _eusrstack
2:
/* Load data section from flash to RAM */
la a0, _data_lma
la a1, _data_vma
la a2, _edata
bgeu a1, a2, 2f
1:
lw t0, (a0)
sw t0, (a1)
addi a0, a0, 4
addi a1, a1, 4
bltu a1, a2, 1b
2:
/* Clear bss section */
la a0, _sbss
la a1, _ebss
bgeu a0, a1, 2f
1:
sw zero, (a0)
addi a0, a0, 4
bltu a0, a1, 1b
2:
/* Configure pipelining and instruction prediction */
li t0, 0x1f
csrw 0xbc0, t0
/* Enable interrupt nesting and hardware stack */
li t0, 0x2
csrw 0x804, t0
/* Enable global interrupt and configure privileged mode */
li t0, 0x1800
csrw mstatus, t0
/* Configure the interrupt vector table recognition mode and entry address mode */
la t0, _vector_base
ori t0, t0, 3
csrw mtvec, t0
jal SystemInit
la t0, entry
csrw mepc, t0
mret

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-09-09 WCH the first version
*/
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
#ifndef CPUPORT_H__
#define CPUPORT_H__
/* bytes of register width */
//#define ARCH_RISCV_FPU
#define ARCH_RISCV_FPU_S
#ifdef ARCH_CPU_64BIT
#define STORE sd
#define LOAD ld
#define StoreDS "sd"
#define LoadDS "ld"
#define REGBYTES 8
#define RegLength 8
#define RegLengthS "8"
#else
#define STORE sw
#define LOAD lw
#define StoreDS "sw"
#define LoadDS "lw"
#define RegLength 4
#define REGBYTES 4
#define RegLengthS "4"
#endif
/* FPU */
#ifdef ARCH_RISCV_FPU
#ifdef ARCH_RISCV_FPU_D
#define FSTORE fsd
#define FLOAD fld
#define FREGBYTES 8
#endif
#ifdef ARCH_RISCV_FPU_S
#define FSTORE fsw
#define FLOAD flw
#define FREGBYTES 4
#endif
#endif
#endif

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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
#include <xs_assign.h>
#include <xs_base.h>
#include <xs_isr.h>
#include <xs_ktask.h>
#include "ch32v20x.h"
#include "cpuport.h"
#include "core_riscv.h"
#ifdef TASK_ISOLATION
#include <xs_service.h>
#endif
extern x_ubase interrupt_from_sp;
extern x_ubase interrupt_to_sp;
extern x_ubase interrupt_new_task;
void sw_setpend(void)
{
SysTick->CTLR |= (1<<31);
}
/*
* clear soft interrupt
*/
void sw_clearpend(void)
{
SysTick->CTLR &= ~(1<<31);
}
x_base DisableLocalInterrupt()
{
x_base level;
// asm volatile ("csrrci %0, mstatus, 8" : "=r"(level));
asm("csrrw %0, mstatus, %1":"=r"(level):"r"(0x1800));
return level;
}
void EnableLocalInterrupt(x_base level)
{
asm volatile ("csrw mstatus, %0" :: "r"(level));
}
int ArchEnableHwIrq(uint32_t irq_num)
{
NVIC_SetPriority(irq_num, 1);
NVIC_EnableIRQ(irq_num);
}
int ArchDisableHwIrq(uint32_t irq_num)
{
NVIC_DisableIRQ(irq_num);
}
struct ExceptionStackFrame
{
uint64_t x1;
uint64_t x2;
uint64_t x3;
uint64_t x4;
uint64_t x5;
uint64_t x6;
uint64_t x7;
uint64_t x8;
uint64_t x9;
uint64_t x10;
uint64_t x11;
uint64_t x12;
uint64_t x13;
uint64_t x14;
uint64_t x15;
uint64_t x16;
uint64_t x17;
uint64_t x18;
uint64_t x19;
uint64_t x20;
uint64_t x21;
uint64_t x22;
uint64_t x23;
uint64_t x24;
uint64_t x25;
uint64_t x26;
uint64_t x27;
uint64_t x28;
uint64_t x29;
uint64_t x30;
uint64_t x31;
};
void PrintStackFrame(uintptr_t * sp)
{
struct ExceptionStackFrame * esf = (struct ExceptionStackFrame *)(sp+1);
KPrintf("\n=================================================================\n");
KPrintf("x1 (ra : Return address ) ==> 0x%08x%08x\n", esf->x1 >> 32 , esf->x1 & UINT32_MAX);
KPrintf("x2 (sp : Stack pointer ) ==> 0x%08x%08x\n", esf->x2 >> 32 , esf->x2 & UINT32_MAX);
KPrintf("x3 (gp : Global pointer ) ==> 0x%08x%08x\n", esf->x3 >> 32 , esf->x3 & UINT32_MAX);
KPrintf("x4 (tp : Task pointer ) ==> 0x%08x%08x\n", esf->x4 >> 32 , esf->x4 & UINT32_MAX);
KPrintf("x5 (t0 : Temporary ) ==> 0x%08x%08x\n", esf->x5 >> 32 , esf->x5 & UINT32_MAX);
KPrintf("x6 (t1 : Temporary ) ==> 0x%08x%08x\n", esf->x6 >> 32 , esf->x6 & UINT32_MAX);
KPrintf("x7 (t2 : Temporary ) ==> 0x%08x%08x\n", esf->x7 >> 32 , esf->x7 & UINT32_MAX);
KPrintf("x8 (s0/fp: Save register,frame pointer ) ==> 0x%08x%08x\n", esf->x8 >> 32 , esf->x8 & UINT32_MAX);
KPrintf("x9 (s1 : Save register ) ==> 0x%08x%08x\n", esf->x9 >> 32 , esf->x9 & UINT32_MAX);
KPrintf("x10(a0 : Function argument,return value) ==> 0x%08x%08x\n", esf->x10 >> 32 , esf->x10 & UINT32_MAX);
KPrintf("x11(a1 : Function argument,return value) ==> 0x%08x%08x\n", esf->x11 >> 32 , esf->x11 & UINT32_MAX);
KPrintf("x12(a2 : Function argument ) ==> 0x%08x%08x\n", esf->x12 >> 32 , esf->x12 & UINT32_MAX);
KPrintf("x13(a3 : Function argument ) ==> 0x%08x%08x\n", esf->x13 >> 32 , esf->x13 & UINT32_MAX);
KPrintf("x14(a4 : Function argument ) ==> 0x%08x%08x\n", esf->x14 >> 32 , esf->x14 & UINT32_MAX);
KPrintf("x15(a5 : Function argument ) ==> 0x%08x%08x\n", esf->x15 >> 32 , esf->x15 & UINT32_MAX);
KPrintf("x16(a6 : Function argument ) ==> 0x%08x%08x\n", esf->x16 >> 32 , esf->x16 & UINT32_MAX);
KPrintf("x17(a7 : Function argument ) ==> 0x%08x%08x\n", esf->x17 >> 32 , esf->x17 & UINT32_MAX);
KPrintf("x18(s2 : Save register ) ==> 0x%08x%08x\n", esf->x18 >> 32 , esf->x18 & UINT32_MAX);
KPrintf("x19(s3 : Save register ) ==> 0x%08x%08x\n", esf->x19 >> 32 , esf->x19 & UINT32_MAX);
KPrintf("x20(s4 : Save register ) ==> 0x%08x%08x\n", esf->x20 >> 32 , esf->x20 & UINT32_MAX);
KPrintf("x21(s5 : Save register ) ==> 0x%08x%08x\n", esf->x21 >> 32 , esf->x21 & UINT32_MAX);
KPrintf("x22(s6 : Save register ) ==> 0x%08x%08x\n", esf->x22 >> 32 , esf->x22 & UINT32_MAX);
KPrintf("x23(s7 : Save register ) ==> 0x%08x%08x\n", esf->x23 >> 32 , esf->x23 & UINT32_MAX);
KPrintf("x24(s8 : Save register ) ==> 0x%08x%08x\n", esf->x24 >> 32 , esf->x24 & UINT32_MAX);
KPrintf("x25(s9 : Save register ) ==> 0x%08x%08x\n", esf->x25 >> 32 , esf->x25 & UINT32_MAX);
KPrintf("x26(s10 : Save register ) ==> 0x%08x%08x\n", esf->x26 >> 32 , esf->x26 & UINT32_MAX);
KPrintf("x27(s11 : Save register ) ==> 0x%08x%08x\n", esf->x27 >> 32 , esf->x27 & UINT32_MAX);
KPrintf("x28(t3 : Temporary ) ==> 0x%08x%08x\n", esf->x28 >> 32 , esf->x28 & UINT32_MAX);
KPrintf("x29(t4 : Temporary ) ==> 0x%08x%08x\n", esf->x29 >> 32 , esf->x29 & UINT32_MAX);
KPrintf("x30(t5 : Temporary ) ==> 0x%08x%08x\n", esf->x30 >> 32 , esf->x30 & UINT32_MAX);
KPrintf("x31(t6 : Temporary ) ==> 0x%08x%08x\n", esf->x31 >> 32 , esf->x31 & UINT32_MAX);
KPrintf("=================================================================\n");
}
void HwInterruptcontextSwitch(x_ubase from_sp, x_ubase to_sp, struct TaskDescriptor* new_task, void* context) {
interrupt_from_sp = (x_ubase)from_sp;
interrupt_to_sp = (x_ubase)to_sp;
interrupt_new_task = (x_ubase)new_task;
sw_setpend();
}

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#include "cpuport.h"
.global SW_Handler
.align 2
SW_Handler:
/* save all from thread context */
#ifdef ARCH_RISCV_FPU
addi sp, sp, -32 * FREGBYTES
FSTORE f0, 0 * FREGBYTES(sp)
FSTORE f1, 1 * FREGBYTES(sp)
FSTORE f2, 2 * FREGBYTES(sp)
FSTORE f3, 3 * FREGBYTES(sp)
FSTORE f4, 4 * FREGBYTES(sp)
FSTORE f5, 5 * FREGBYTES(sp)
FSTORE f6, 6 * FREGBYTES(sp)
FSTORE f7, 7 * FREGBYTES(sp)
FSTORE f8, 8 * FREGBYTES(sp)
FSTORE f9, 9 * FREGBYTES(sp)
FSTORE f10, 10 * FREGBYTES(sp)
FSTORE f11, 11 * FREGBYTES(sp)
FSTORE f12, 12 * FREGBYTES(sp)
FSTORE f13, 13 * FREGBYTES(sp)
FSTORE f14, 14 * FREGBYTES(sp)
FSTORE f15, 15 * FREGBYTES(sp)
FSTORE f16, 16 * FREGBYTES(sp)
FSTORE f17, 17 * FREGBYTES(sp)
FSTORE f18, 18 * FREGBYTES(sp)
FSTORE f19, 19 * FREGBYTES(sp)
FSTORE f20, 20 * FREGBYTES(sp)
FSTORE f21, 21 * FREGBYTES(sp)
FSTORE f22, 22 * FREGBYTES(sp)
FSTORE f23, 23 * FREGBYTES(sp)
FSTORE f24, 24 * FREGBYTES(sp)
FSTORE f25, 25 * FREGBYTES(sp)
FSTORE f26, 26 * FREGBYTES(sp)
FSTORE f27, 27 * FREGBYTES(sp)
FSTORE f28, 28 * FREGBYTES(sp)
FSTORE f29, 29 * FREGBYTES(sp)
FSTORE f30, 30 * FREGBYTES(sp)
FSTORE f31, 31 * FREGBYTES(sp)
#endif
addi sp, sp, -32 * REGBYTES
STORE x5, 5 * REGBYTES(sp)
/* saved MPIE */
li t0, 0x80
STORE t0, 2 * REGBYTES(sp)
/* Temporarily disable HPE */
li t0, 0x20
csrs 0x804, t0
STORE x1, 1 * REGBYTES(sp)
STORE x4, 4 * REGBYTES(sp)
STORE x6, 6 * REGBYTES(sp)
STORE x7, 7 * REGBYTES(sp)
STORE x8, 8 * REGBYTES(sp)
STORE x9, 9 * REGBYTES(sp)
STORE x10, 10 * REGBYTES(sp)
STORE x11, 11 * REGBYTES(sp)
STORE x12, 12 * REGBYTES(sp)
STORE x13, 13 * REGBYTES(sp)
STORE x14, 14 * REGBYTES(sp)
STORE x15, 15 * REGBYTES(sp)
STORE x16, 16 * REGBYTES(sp)
STORE x17, 17 * REGBYTES(sp)
STORE x18, 18 * REGBYTES(sp)
STORE x19, 19 * REGBYTES(sp)
STORE x20, 20 * REGBYTES(sp)
STORE x21, 21 * REGBYTES(sp)
STORE x22, 22 * REGBYTES(sp)
STORE x23, 23 * REGBYTES(sp)
STORE x24, 24 * REGBYTES(sp)
STORE x25, 25 * REGBYTES(sp)
STORE x26, 26 * REGBYTES(sp)
STORE x27, 27 * REGBYTES(sp)
STORE x28, 28 * REGBYTES(sp)
STORE x29, 29 * REGBYTES(sp)
STORE x30, 30 * REGBYTES(sp)
STORE x31, 31 * REGBYTES(sp)
csrr a0, mepc
STORE a0, 0 * REGBYTES(sp)
/* switch to interrupt stack */
csrrw sp,mscratch,sp
/* clear interrupt */
jal sw_clearpend
/* switch to from thread stack */
csrrw sp,mscratch,sp
csrr a0, mepc
STORE a0, 0 * REGBYTES(sp)
la s0, interrupt_from_sp
LOAD s1, 0(s0)
STORE sp, 0(s1)
la s0, interrupt_to_sp
LOAD s1, 0(s0)
LOAD sp, 0(s1)
LOAD a0, 0 * REGBYTES(sp)
csrw mepc, a0
LOAD x1, 1 * REGBYTES(sp)
li t0,0x7800
csrs mstatus, t0
LOAD t0, 2*REGBYTES(sp)
csrs mstatus, t0
j SwitchKTaskContextExit

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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
#include "cpuport.h"
#include <board.h>
#include <xs_base.h>
#include <xs_ktask.h>
#include <xs_isr.h>
#ifdef TASK_ISOLATION
#include "encoding.h"
#include <stdint.h>
#include <xs_isolation.h>
#endif
volatile x_ubase interrupt_from_sp = 0;
volatile x_ubase interrupt_to_sp = 0;
volatile x_ubase interrupt_new_task = 0;
struct StackRegisterContext
{
x_ubase epc;
x_ubase ra;
x_ubase mstatus;
x_ubase gp;
x_ubase tp;
x_ubase t0;
x_ubase t1;
x_ubase t2;
x_ubase s0_fp;
x_ubase s1;
x_ubase a0;
x_ubase a1;
x_ubase a2;
x_ubase a3;
x_ubase a4;
x_ubase a5;
x_ubase a6;
x_ubase a7;
x_ubase s2;
x_ubase s3;
x_ubase s4;
x_ubase s5;
x_ubase s6;
x_ubase s7;
x_ubase s8;
x_ubase s9;
x_ubase s10;
x_ubase s11;
x_ubase t3;
x_ubase t4;
x_ubase t5;
x_ubase t6;
/* float register */
#ifdef ARCH_RISCV_FPU
x_ubase f0; /* f0 */
x_ubase f1; /* f1 */
x_ubase f2; /* f2 */
x_ubase f3; /* f3 */
x_ubase f4; /* f4 */
x_ubase f5; /* f5 */
x_ubase f6; /* f6 */
x_ubase f7; /* f7 */
x_ubase f8; /* f8 */
x_ubase f9; /* f9 */
x_ubase f10; /* f10 */
x_ubase f11; /* f11 */
x_ubase f12; /* f12 */
x_ubase f13; /* f13 */
x_ubase f14; /* f14 */
x_ubase f15; /* f15 */
x_ubase f16; /* f16 */
x_ubase f17; /* f17 */
x_ubase f18; /* f18 */
x_ubase f19; /* f19 */
x_ubase f20; /* f20 */
x_ubase f21; /* f21 */
x_ubase f22; /* f22 */
x_ubase f23; /* f23 */
x_ubase f24; /* f24 */
x_ubase f25; /* f25 */
x_ubase f26; /* f26 */
x_ubase f27; /* f27 */
x_ubase f28; /* f28 */
x_ubase f29; /* f29 */
x_ubase f30; /* f30 */
x_ubase f31; /* f31 */
#endif
};
uint8 KTaskStackSetup(struct TaskDescriptor *task)
{
struct StackRegisterContext *stack_contex;
int i;
task->stack_point = (uint8 *)ALIGN_MEN_DOWN((x_ubase)(task->task_base_info.stack_start + task->task_base_info.stack_depth), RegLength);
task->stack_point -= sizeof(struct StackRegisterContext);
stack_contex = (struct StackRegisterContext *)task->stack_point;
for (i = 0; i < sizeof(struct StackRegisterContext) / sizeof(x_ubase); i++)
((x_ubase *)stack_contex)[i] = 0xfadeface;
#ifdef SEPARATE_COMPILE
if (task->task_dync_sched_member.isolation_flag == 1) {
stack_contex->ra = (unsigned long)USERSPACE->us_taskquit;
} else {
stack_contex->ra = (x_ubase)KTaskQuit;
}
#else
stack_contex->ra = (x_ubase)KTaskQuit;
#endif
stack_contex->a0 = (x_ubase)task->task_base_info.func_param;
stack_contex->epc = (x_ubase)task->task_base_info.func_entry;
#ifdef TASK_ISOLATION
stack_contex->tp = (x_ubase)task;
if(task->task_dync_sched_member.isolation_flag == 1)
stack_contex->mstatus = 0x00006080;
else
#endif
stack_contex->mstatus = 0x00007880;
return EOK;
}
#ifdef TASK_ISOLATION
void RestoreMstatus(uintptr_t *sp)
{
struct TaskDescriptor *tid;
tid = (struct TaskDescriptor *)(sp[4]);
if(tid->task_dync_sched_member.isolation_flag == 1 && tid->task_dync_sched_member.isolation_status == 0){
CLEAR_CSR(mstatus, (MSTATUS_MPP));
#ifdef MOMERY_PROTECT_ENABLE
mem_access.Load(tid->task_dync_sched_member.isolation);
#endif
}else{
SET_CSR(mstatus, MSTATUS_MPP);
}
}
#endif

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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
#include "cpuport.h"
.global SwitchKTaskContextExit
SwitchKTaskContextExit:
/* resw ra to mepc */
LOAD a0, 0 * REGBYTES(sp)
csrw mepc, a0
LOAD ra, 1 * REGBYTES(sp)
/* keep machine mode */
li a0, 0x7800
csrw mstatus, a0
/* resume MPIE */
LOAD a0, 2*REGBYTES(sp)
csrs mstatus, a0
LOAD x4, 4 * REGBYTES(sp)
LOAD x5, 5 * REGBYTES(sp)
LOAD x6, 6 * REGBYTES(sp)
LOAD x7, 7 * REGBYTES(sp)
LOAD x8, 8 * REGBYTES(sp)
LOAD x9, 9 * REGBYTES(sp)
LOAD x10, 10 * REGBYTES(sp)
LOAD x11, 11 * REGBYTES(sp)
LOAD x12, 12 * REGBYTES(sp)
LOAD x13, 13 * REGBYTES(sp)
LOAD x14, 14 * REGBYTES(sp)
LOAD x15, 15 * REGBYTES(sp)
LOAD x16, 16 * REGBYTES(sp)
LOAD x17, 17 * REGBYTES(sp)
LOAD x18, 18 * REGBYTES(sp)
LOAD x19, 19 * REGBYTES(sp)
LOAD x20, 20 * REGBYTES(sp)
LOAD x21, 21 * REGBYTES(sp)
LOAD x22, 22 * REGBYTES(sp)
LOAD x23, 23 * REGBYTES(sp)
LOAD x24, 24 * REGBYTES(sp)
LOAD x25, 25 * REGBYTES(sp)
LOAD x26, 26 * REGBYTES(sp)
LOAD x27, 27 * REGBYTES(sp)
LOAD x28, 28 * REGBYTES(sp)
LOAD x29, 29 * REGBYTES(sp)
LOAD x30, 30 * REGBYTES(sp)
LOAD x31, 31 * REGBYTES(sp)
addi sp, sp, 32 * REGBYTES
/* load float reg */
#ifdef ARCH_RISCV_FPU
FLOAD f0, 0 * FREGBYTES(sp)
FLOAD f1, 1 * FREGBYTES(sp)
FLOAD f2, 2 * FREGBYTES(sp)
FLOAD f3, 3 * FREGBYTES(sp)
FLOAD f4, 4 * FREGBYTES(sp)
FLOAD f5, 5 * FREGBYTES(sp)
FLOAD f6, 6 * FREGBYTES(sp)
FLOAD f7, 7 * FREGBYTES(sp)
FLOAD f8, 8 * FREGBYTES(sp)
FLOAD f9, 9 * FREGBYTES(sp)
FLOAD f10, 10 * FREGBYTES(sp)
FLOAD f11, 11 * FREGBYTES(sp)
FLOAD f12, 12 * FREGBYTES(sp)
FLOAD f13, 13 * FREGBYTES(sp)
FLOAD f14, 14 * FREGBYTES(sp)
FLOAD f15, 15 * FREGBYTES(sp)
FLOAD f16, 16 * FREGBYTES(sp)
FLOAD f17, 17 * FREGBYTES(sp)
FLOAD f18, 18 * FREGBYTES(sp)
FLOAD f19, 19 * FREGBYTES(sp)
FLOAD f20, 20 * FREGBYTES(sp)
FLOAD f21, 21 * FREGBYTES(sp)
FLOAD f22, 22 * FREGBYTES(sp)
FLOAD f23, 23 * FREGBYTES(sp)
FLOAD f24, 24 * FREGBYTES(sp)
FLOAD f25, 25 * FREGBYTES(sp)
FLOAD f26, 26 * FREGBYTES(sp)
FLOAD f27, 27 * FREGBYTES(sp)
FLOAD f28, 28 * FREGBYTES(sp)
FLOAD f29, 29 * FREGBYTES(sp)
FLOAD f30, 30 * FREGBYTES(sp)
FLOAD f31, 31 * FREGBYTES(sp)
addi sp, sp, 32 * FREGBYTES
#endif
mret
.global SwitchKtaskContextTo
SwitchKtaskContextTo:
/* first save interrupt stack */
la t0, _eusrstack
addi t0, t0, -512
csrw mscratch,t0
LOAD sp, (a0)
MOVE a0, a1
jal RestoreCpusLockStatus
LOAD a0, 2 * REGBYTES(sp)
csrw mstatus, a0
j SwitchKTaskContextExit
.global SwitchKtaskContext
SwitchKtaskContext:
/* switch in thread */
#ifdef ARCH_RISCV_FPU
addi sp, sp, -32*FREGBYTES
FSTORE f0, 0 * FREGBYTES(sp)
FSTORE f1, 1 * FREGBYTES(sp)
FSTORE f2, 2 * FREGBYTES(sp)
FSTORE f3, 3 * FREGBYTES(sp)
FSTORE f4, 4 * FREGBYTES(sp)
FSTORE f5, 5 * FREGBYTES(sp)
FSTORE f6, 6 * FREGBYTES(sp)
FSTORE f7, 7 * FREGBYTES(sp)
FSTORE f8, 8 * FREGBYTES(sp)
FSTORE f9, 9 * FREGBYTES(sp)
FSTORE f10, 10 * FREGBYTES(sp)
FSTORE f11, 11 * FREGBYTES(sp)
FSTORE f12, 12 * FREGBYTES(sp)
FSTORE f13, 13 * FREGBYTES(sp)
FSTORE f14, 14 * FREGBYTES(sp)
FSTORE f15, 15 * FREGBYTES(sp)
FSTORE f16, 16 * FREGBYTES(sp)
FSTORE f17, 17 * FREGBYTES(sp)
FSTORE f18, 18 * FREGBYTES(sp)
FSTORE f19, 19 * FREGBYTES(sp)
FSTORE f20, 20 * FREGBYTES(sp)
FSTORE f21, 21 * FREGBYTES(sp)
FSTORE f22, 22 * FREGBYTES(sp)
FSTORE f23, 23 * FREGBYTES(sp)
FSTORE f24, 24 * FREGBYTES(sp)
FSTORE f25, 25 * FREGBYTES(sp)
FSTORE f26, 26 * FREGBYTES(sp)
FSTORE f27, 27 * FREGBYTES(sp)
FSTORE f28, 28 * FREGBYTES(sp)
FSTORE f29, 29 * FREGBYTES(sp)
FSTORE f30, 30 * FREGBYTES(sp)
FSTORE f31, 31 * FREGBYTES(sp)
#endif
addi sp, sp, -32 * REGBYTES
/* save from sp */
STORE sp, 0(a0)
/* save ra to epc */
STORE x1, 0 * REGBYTES(sp)
STORE x1, 1 * REGBYTES(sp)
STORE x5, 5 * REGBYTES(sp)
csrr t0, mstatus
andi t0, t0, 8
/* if MIE be enabled,set MPIE */
beqz t0, 1f
li t0, 0x80
1: STORE t0, 2 * REGBYTES(sp)
STORE x4, 4 * REGBYTES(sp)
STORE x6, 6 * REGBYTES(sp)
STORE x7, 7 * REGBYTES(sp)
STORE x8, 8 * REGBYTES(sp)
STORE x9, 9 * REGBYTES(sp)
STORE x10, 10 * REGBYTES(sp)
STORE x11, 11 * REGBYTES(sp)
STORE x12, 12 * REGBYTES(sp)
STORE x13, 13 * REGBYTES(sp)
STORE x14, 14 * REGBYTES(sp)
STORE x15, 15 * REGBYTES(sp)
STORE x16, 16 * REGBYTES(sp)
STORE x17, 17 * REGBYTES(sp)
STORE x18, 18 * REGBYTES(sp)
STORE x19, 19 * REGBYTES(sp)
STORE x20, 20 * REGBYTES(sp)
STORE x21, 21 * REGBYTES(sp)
STORE x22, 22 * REGBYTES(sp)
STORE x23, 23 * REGBYTES(sp)
STORE x24, 24 * REGBYTES(sp)
STORE x25, 25 * REGBYTES(sp)
STORE x26, 26 * REGBYTES(sp)
STORE x27, 27 * REGBYTES(sp)
STORE x28, 28 * REGBYTES(sp)
STORE x29, 29 * REGBYTES(sp)
STORE x30, 30 * REGBYTES(sp)
STORE x31, 31 * REGBYTES(sp)
/* get "to" thread sp */
LOAD sp, (a1)
/*MOVE a0, a2
jal RestoreCpusLockStatus*/
j SwitchKTaskContextExit

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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
#include <xs_ktick.h>
#include <xs_isr.h>
#include <xs_assign.h>
#include "ch32v20x.h"
#include "ch32v20x_it.h"
#include "core_riscv.h"
extern void KTaskOsAssignAfterIrq(void *);
void SysTick_Handler(void) __attribute__((interrupt()));
void SysTick_Handler(void)
{
GET_INT_SP();
/* enter interrupt */
x_base level;
level = DisableLocalInterrupt();
isrManager.done->incCounter();
EnableLocalInterrupt(level);
SysTick->SR = 0;
TickAndTaskTimesliceUpdate();
KTaskOsAssignAfterIrq(NONE);
/* leave interrupt */
level = DisableLocalInterrupt();
isrManager.done->decCounter();
EnableLocalInterrupt(level);
FREE_INT_SP();
}

31
Ubiquitous/XiZi_IIoT/board/ch32v208rbt6/Kconfig Normal file
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mainmenu "XiZi_IIoT Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config KERNEL_DIR
string
option env="KERNEL_ROOT"
default "../.."
config BOARD_CH32V208RBT6
bool
select ARCH_RISCV
default y
source "$KERNEL_DIR/arch/Kconfig"
menu "ch32v208rbt6 feature"
source "$BSP_DIR/third_party_driver/Kconfig"
endmenu
menu "Hardware feature"
source "$KERNEL_DIR/resources/Kconfig"
endmenu
source "$KERNEL_DIR/Kconfig"

6
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SRC_FILES := board.c
SRC_DIR := third_party_driver
include $(KERNEL_ROOT)/compiler.mk

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# 1. 简介
| 硬件 | 描述 |
| --------- | ------------------------------------------------------------ |
| 芯片型号 | CH32V208RBT6 |
| CPU | 单核RISC-V4C |
| 主频 | 144MHz |
| 片内SRAM | 可配：32KB、48KB、64KB |
| 片内FLASH | 可配：160KB、144KB、128KB |
| 外设 | 2Mbps低功耗蓝牙BLE通讯模块、10M以太网MAC+PHY模块、USB2.0全速设备+主机/设备接口、CAN控制器等 |
# 2. 克隆代码
将XiUOS的源代码克隆下来：
```bash
git clone https://gitlink.org.cn/xuos/xiuos.git
```
# 3. 下载编译工具链
编译环境：Ubuntu 20.04.6 LTS
编译工具链：riscv-none-elf-gcc（xpack-riscv-none-elf-gcc-11.3.0-1）
编译工具链可到Github进行下载：https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases
![image-20240509155858504](imgs/image-20240509155858504.png)
下载完成后将其移动到`/opt`目录下，并进行解压：
```bash
sudo tar -xvzf xpack-riscv-none-elf-gcc-11.3.0-1-linux-x64.tar.gz
```
# 4. 编译
## 方式1（推荐）
可以在`Ubiquitous/XiZi_IIoT`目录下创建文件`script.sh`，内容如下：
```sh
#! /bin/env sh
export CROSS_COMPILE=/opt/xpack-riscv-none-elf-gcc-11.3.0-1/bin/riscv-none-elf-
make BOARD=ch32v208rbt6 clean # 将之前的编译生成文件清空
make BOARD=ch32v208rbt6 menuconfig
make BOARD=ch32v208rbt6
```
创建之后，在命令行移动到`XiZi-IIOT`目录下，键入`./script`运行该脚本。
经过KConfig配置、编译后，即可在`Ubiquitous/XiZi_IIoT/build`目录中生成`XiZi-ch32v208rbt6.bin`文件，将该文件拷贝至Windows侧待下一步进行烧录。
> [!CAUTION]
>
> 如果`make BOARD=ch32v208rbt6 menuconfig`显示【无法找到`kconfig-mconf`】，需要先安装`ncurses-devel`和`kconfig-mconf`，如下：
>
> ```bash
> sudo apt install libncurses5-dev kconfig-frontends
## 方式2
1. 设置`CROSS_COMPILE`环境变量，以下为将编译工具链解压到`/opt`目录下时的命令：
```bash
export CROSS_COMPILE=/opt/xpack-riscv-none-elf-gcc-11.3.0-1/bin/riscv-none-elf-
```
2. 在`Ubiquitous/XiZi_IIoT`目录下执行命令：
```bash
make BOARD=ch32v208rbt6 distclean # 将之前的编译生成文件清空
make BOARD=ch32v208rbt6 menuconfig # 进行编译设置
```
如果`make BOARD=ch32v208rbt6 menuconfig`显示【无法找到`kconfig-mconf`】，需要先安装`ncurses-devel`和`kconfig-mconf`，如下：
```bash
sudo apt install libncurses5-dev kconfig-frontends
```
3. 在`menuconfig`配置界面选择要增加的功能。按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后选择Exit保存并退出，完成后会生成`.config`文件。
4. 进行编译：
```bash
make BOARD=ch32v208rbt6
```
5. 编译完成后会在`Ubiquitous/XiZi_IIoT/build`目录中生成`XiZi-ch32v208rbt6.bin`文件，将该文件拷贝至Windows侧待下一步进行烧录。
# 5. 端口连接
`ch32v208rbt6`需要使用`WCH-LINK`模块进行串口连接，各个端口的连接如下：
| 接口组别 | ch32v208rbt6 | WCH-LINK |
| -------------- | ------------ | -------- |
| J2（编程接口） | GND | GND |
| J2（编程接口） | DIO | SWDIO |
| J2（编程接口） | CLK | SWCLK |
| J2（编程接口） | 3V3 | 3V3 |
| J3（通信接口） | GND | GND |
| J3（通信接口） | TX | RX |
| J3（通信接口） | RX | TX |
连接后如下：
![cb4d033a1ed826e9cee7acbdc225fab5](imgs/cb4d033a1ed826e9cee7acbdc225fab5.jpeg)
# 6. WCH-LINK模块固件更新（可选）
如WCH-LINK模块蓝灯闪烁，代表其固件缺失，需要进行固件烧录或者更新。
可以使用[MounRiver Studio](http://www.mounriver.com/download)在线更新。更新步骤如下：
1. 将WCH-LINK连接至电脑。
2. 打开MounRiver Studio，点击`download`图标右边的向下箭头，点击`configuration`，如下所示：
![image-20240509163525255](imgs/image-20240509163525255.png)
3. 显示窗口后，点击任意`query`按钮即可进行固件更新，如下：
<img src="imgs/image-20240509163753634.png" alt="image-20240509163753634" style="zoom:67%;" />
4. 待WCH-LINK模块红灯亮起，表示固件更新完成。
# 7. 烧录
1. 下载`WCH-LinkUtility`工具：https://www.wch.cn/downloads/WCH-LinkUtility_ZIP.html
2. ch32v208rbt6连接电源线（如果电源线只有两根，保证`IN`和其中一个`GND`接地即可），如下：
<img src="imgs/5B75D386B81B5235B2A6274534359E34.png" alt="5B75D386B81B5235B2A6274534359E34" style="zoom:67%;" />
3. 将WCH-LINK连接至电脑，设备管理器显示`WCH-LinkRV`表示连接成功，如下：
<img src="imgs/image-20240509164821442.png" alt="image-20240509164821442" style="zoom:67%;" />
4. 打开烧录软件WCH-LinkUtility，如下：
<img src="imgs/image-20240509165100764.png" alt="image-20240509165100764" style="zoom:67%;" />
1）连接 WCH-Link。
2）选择芯片信息，`MCU Core`选择`RISC-V`，`Series`选择`CH32V20X`。
3）添加固件，即[2. 编译](# 2. 编译)中编译好的`XiZi-ch32v208rbt6.bin`文件。
4）设置配置选项，若芯片为读保护需解除芯片读保护。
5）执行。
## 7.1 指定ROM和RAM大小
> 参考资料：
>
> [1]https://www.cnblogs.com/gscw/p/17286307.html
> [!caution]
>
> WCH-LinkUtility中需要指定ROM和RAM大小，如果大小与源文件`link.ld`中的ROM和RAM大小不一致，可能会导致XiZi启动失败。
在WCH_LinkUtility中，在以下位置指定ROM和RAM大小：
<img src="imgs/image-20240613144008865.png" alt="image-20240613144008865" style="zoom:50%;" />
其中，set按钮用于设置CH32V208的ROM和RAM大小，get按钮用于获取CH32V208的当前ROM和RAM大小。
在`Ubiquitous/XiZi_IIoT/board/ch32v208rbt6/link.ld`中，在以下代码位置配置ROM和RAM大小：
```c
/* CH32V20x_D8 - CH32V203RB
CH32V20x_D8W - CH32V208x
FLASH + RAM supports the following configuration
FLASH-128K + RAM-64K
FLASH-144K + RAM-48K
FLASH-160K + RAM-32K
*/
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 448K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
```
以下是测试成功的RAM和ROM大小配置，如果编译时显示RAM或者ROM不足，则需要调整RAM或者ROM。推荐使用下面的慢速FLASH配置。
1. 仅使用快速FLASH
| link.ld | WCH-LinkUtility |
| ------------------------- | ------------------ |
| 128K（FLASH）+ 64K（RAM） | 128K ROM + 64K RAM |
| 144K（FLASH）+ 48K（RAM） | 144K ROM + 48K RAM |
| 160K（FLASH）+ 32K（RAM） | 160K ROM + 32K RAM |
2. 使用慢速FLASH
| link.ld | WCH-LinkUtility |
| ------------------------- | ------------------ |
| 448K（FLASH）+ 64K（RAM） | 128K ROM + 64K RAM |
# 8. 启动
烧录完成后，并且将WCH-LINK连接至电脑串口。
按下ch32v208rbt6板上的`RST`按钮，即可看到操作系统启动的信息，如下：
![image-20240509165901360](imgs/image-20240509165901360.png)

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/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-07-24 Tanek the first version
* 2018-11-12 Ernest Chen modify copyright
*/
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file board.c
* @brief support ch32v208 init configure and start-up
* @version 1.0
* @author AIIT XUOS Lab
* @date 2024-4-29
*/
#include "board.h"
#include <ModuleConfig.h>
#include <device.h>
#include <stdint.h>
#include <xizi.h>
#include "HAL.h"
#include "adc.h"
#include "ch32v20x.h"
#include "connect_ble.h"
#include "connect_can.h"
#include "connect_ether.h"
#include "connect_lte.h"
#include "connect_rs485.h"
#include "connect_uart.h"
#include "core_riscv.h"
#include "wchble.h"
#include "xsconfig.h"
static uint32_t _SysTick_Config(uint32_t ticks) {
// SystemCoreClockUpdate();
NVIC_SetPriority(SysTicK_IRQn, 0x01);
NVIC_SetPriority(Software_IRQn, 0xf0);
NVIC_EnableIRQ(SysTicK_IRQn);
NVIC_EnableIRQ(Software_IRQn);
SysTick->CTLR = 0;
SysTick->SR = 0;
SysTick->CNT = 0;
SysTick->CMP = ticks - 1;
SysTick->CTLR = 0xF;
return 0;
}
/**
* @brief 从FLASH中读取配置信息。若FLASH中的配置信息无效，则将默认的配置信息写入FLASH，再复位ch32v208。
* @note 目前的配置信息仅包含RS485、以太网、4G（LTE）模块的配置信息。
* @note FLASH中的配置信息存放在PAGE_WRITE_START_ADDR(478K)地址处，大小为1KB。
*/
void readRomConfiguration(void) {
extern module_cfg defaultConfiguration; // 默认配置信息
extern u8 Configbuf[MODULE_CFG_LEN]; // 内存存放从FLASH中读取的配置信息
extern pmodule_cfg CFG; // 指向配置信息的指针
/* 从EEPROM中读取网络配置信息 */
CFG_READ(PAGE_WRITE_START_ADDR, Configbuf, MODULE_CFG_LEN);
/* 如果存储在EEPROM中的网络配置信息无效，或者WCHNET还没有被主机配置过，通过默认配置信息初始化WCHNET */
if ((CFG->cfgFlag[0] != checkcode1) || (CFG->cfgFlag[1] != checkcode2)) {
CFG_ERASE(PAGE_WRITE_START_ADDR, FLASH_PAGE_SIZE);
CFG_WRITE(PAGE_WRITE_START_ADDR, (u8 *)&defaultConfiguration, MODULE_CFG_LEN);
NVIC_SystemReset(); // 复位ch32v208
}
/* 输出配置信息 */
KPrintf("\n*************rom configuration****************\n");
KPrintf("moduleName:\t%s\n", CFG->moduleName);
KPrintf("type:\t\t%u\n", CFG->type);
/* 4G模块目的IP和端口号配置 */
KPrintf("----------------------------------------------\n");
KPrintf(" 4G \n");
KPrintf("destinationIpAddress:\t\t%u.%u.%u.%u\n", CFG->destinationIpAddress_4G[0], CFG->destinationIpAddress_4G[1],
CFG->destinationIpAddress_4G[2], CFG->destinationIpAddress_4G[3]);
KPrintf("destinationPort: \t\t%hu\n", (unsigned short)CFG->destinationPort_4G[0] | CFG->destinationPort_4G[1] << 8);
/* 4G模块MQTT配置 */
KPrintf("mqttSwitch: \t\t\t%s\n", CFG->mqttSwitch_4G ? "on" : "off");
KPrintf("mqttTopic: \t\t\t%s\n", CFG->mqttTopic_4G);
KPrintf("mqttUsername:\t\t\t%s\n", CFG->mqttUsername_4G);
KPrintf("mqttPassword:\t\t\t%s\n", CFG->mqttPassword_4G);
KPrintf("mqttClientId:\t\t\t%s\n", CFG->mqttClientId_4G);
/* Ethernet模块配置 */
KPrintf("----------------------------------------------\n");
KPrintf(" Ethernet \n");
KPrintf("destinationIpAddress: \t\t%u.%u.%u.%u\n", CFG->destinationIpAddress_Ethernet[0], CFG->destinationIpAddress_Ethernet[1],
CFG->destinationIpAddress_Ethernet[2], CFG->destinationIpAddress_Ethernet[3]);
KPrintf("destinationPort: \t\t%hu\n", (unsigned short)CFG->destinationPort_Ethernet[0] | CFG->destinationPort_Ethernet[1] << 8);
KPrintf("dhcpSwitch: \t\t\t%s\n", CFG->dhcpSwitch_Ethernet ? "on" : "off");
KPrintf("sourceIpAddress: \t\t%u.%u.%u.%u\n", CFG->sourceIpAddress_Ethernet[0], CFG->sourceIpAddress_Ethernet[1],
CFG->sourceIpAddress_Ethernet[2], CFG->sourceIpAddress_Ethernet[3]);
KPrintf("sourcePort: \t\t\t%hu\n", (unsigned short)CFG->sourcePort_Ethernet[0] | CFG->sourcePort_Ethernet[1] << 8);
KPrintf("sourceSubnetMask: \t\t%u.%u.%u.%u\n", CFG->sourceSubnetMask_Ethernet[0], CFG->sourceSubnetMask_Ethernet[1],
CFG->sourceSubnetMask_Ethernet[2], CFG->sourceSubnetMask_Ethernet[3]);
KPrintf("sourceClientGateway: \t\t%u.%u.%u.%u\n", CFG->sourceGateway_Ethernet[0], CFG->sourceGateway_Ethernet[1],
CFG->sourceGateway_Ethernet[2], CFG->sourceGateway_Ethernet[3]);
/* RS485模块配置 */
KPrintf("----------------------------------------------\n");
KPrintf(" Rs485 \n");
int baudRate_Rs485;
int dataBits_Rs485;
int stopBits_Rs485;
char *parity_Rs485;
switch (CFG->baudRate_Rs485) {
case 1:
baudRate_Rs485 = BAUD_RATE_2400;
break;
case 2:
baudRate_Rs485 = BAUD_RATE_4800;
break;
case 3:
baudRate_Rs485 = BAUD_RATE_9600;
break;
case 4:
baudRate_Rs485 = BAUD_RATE_19200;
break;
case 5:
baudRate_Rs485 = BAUD_RATE_38400;
break;
case 6:
baudRate_Rs485 = BAUD_RATE_57600;
break;
case 7:
baudRate_Rs485 = BAUD_RATE_115200;
break;
case 8:
baudRate_Rs485 = BAUD_RATE_230400;
break;
default:
baudRate_Rs485 = BAUD_RATE_9600;
break;
}
switch (CFG->dataBits_Rs485) {
case 1:
dataBits_Rs485 = DATA_BITS_8;
break;
case 2:
dataBits_Rs485 = DATA_BITS_9;
break;
default:
dataBits_Rs485 = DATA_BITS_8;
break;
}
switch (CFG->stopBits_Rs485) {
case 1:
stopBits_Rs485 = STOP_BITS_1;
break;
case 2:
stopBits_Rs485 = STOP_BITS_2;
break;
default:
stopBits_Rs485 = STOP_BITS_1;
}
switch (CFG->parity_Rs485) {
case 1:
parity_Rs485 = "NONE";
break;
case 2:
parity_Rs485 = "ODD";
break;
case 3:
parity_Rs485 = "EVEN";
break;
default:
parity_Rs485 = "NONE";
break;
}
KPrintf("baudRate:\t\t\t%d\n", baudRate_Rs485);
KPrintf("dataBits:\t\t\t%d\n", dataBits_Rs485);
KPrintf("stopBits:\t\t\t%d\n", stopBits_Rs485);
KPrintf("parity:\t\t\t\t%s\n", parity_Rs485);
/* 配置有效位校验 */
KPrintf("----------------------------------------------\n");
KPrintf("cfg_flag: 0x%02x 0x%02x\n", CFG->cfgFlag[0], CFG->cfgFlag[1]);
KPrintf("**********************************************\n\n");
}
/**
* This function will initial your board.
*/
void InitBoardHardware() {
Delay_Init();
USART_Printf_Init(115200);
/* System Tick Configuration */
extern uint32_t SystemCoreClock;
_SysTick_Config(SystemCoreClock / TICK_PER_SECOND);
/* initialize memory system */
InitBoardMemory(MEMORY_START_ADDRESS, (void *)MEMORY_END_ADDRESS);
#ifdef BSP_USING_UART
InitHwUart();
InstallConsole("uart1", SERIAL_DRV_NAME_1, SERIAL_1_DEVICE_NAME_0);
KPrintf("console init completed.\n");
#endif
readRomConfiguration(); // 读取配置信息到外部变量CFG中
KPrintf("board initialization......\n");
#ifdef BSP_USING_RS485
InitHwRs485();
#endif
#ifdef BSP_USING_ETH
InitHwEth();
#endif
#ifdef BSP_USING_ADC
ADC_Function_Init(); // 当前CH32V208的ADC引脚和CAN引脚有功能重叠，因此ADC和CAN不能同时使用
#endif
#ifdef BSP_USING_BLE
InitHwBle();
#endif
#ifdef BSP_USING_CAN
InitHwCan();
#endif
#ifdef BSP_USING_LTE
InitHwLte();
#endif
KPrintf("memory address range: [0x%08x - 0x%08x] SRAM_SIZE: %ld, ssize: %ld\n", (x_ubase)MEMORY_START_ADDRESS,
(x_ubase)MEMORY_END_ADDRESS, SRAM_SIZE, __stack_size);
KPrintf("board init done.\n");
KPrintf("start kernel...\n");
}

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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file board.h
* @brief define ch32v208 init configure and start-up function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2024-04-29
*/
/*************************************************
File name: board.h
Description: define ch32v208 rbt6 init configure and start-up function
Others:
History:
1. Date: 2024-04-29
Author: AIIT XUOS Lab
Modification:
1. define ch32v208 rbt6 InitBoardHardware
*************************************************/
#ifndef __BOARD_H__
#define __BOARD_H__
#include "ch32v20x.h"
#include <xsconfig.h>
#define ch32v20x_PIN_NUMBERS 48
/* board configuration */
#define SRAM_SIZE 64
#define EUSR_STACK_SIZE 2048
// #define SRAM_END (0x20000000 + SRAM_SIZE * 0x400)
// #define SRAM_END (0x20008000)
#define SRAM_END (0x20010000)
extern int _ebss;
extern int __stack_size;
#define MEMORY_START_ADDRESS ((void *)&_ebss)
#define MEMORY_END_ADDRESS (SRAM_END)
void InitBoardHardware(void);
#endif /* __BOARD_H__ */

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export CFLAGS := -march=rv32imac -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -g
export AFLAGS := -march=rv32imac -mabi=ilp32 -x assembler-with-cpp -ggdb
export LFLAGS := -march=rv32imac -mabi=ilp32 -nostartfiles -Wl,--gc-sections,-Map=XiZi-ch32v208vct6.map,-cref,-u,_start -T $(BSP_ROOT)/link.ld
# export CFLAGS := -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -g -std=gnu99
# export AFLAGS := -march=rv32imac -mabi=ilp32 -x assembler-with-cpp -ggdb
# export LFLAGS := -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -g -T $(BSP_ROOT)/link.ld -nostartfiles -Xlinker --gc-sections -Wl,-Map,"XiZi-ch32v307vct6.map" --specs=nano.specs --specs=nosys.specs
export APPLFLAGS := -nostartfiles -Wl,--gc-sections,-Map=XiZi-app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
export CXXFLAGS := -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common # -std=gnu99
export CROSS_COMPILE ?=/opt/riscv64-toolchain/bin/riscv64-unknown-elf-
export DEFINES := -DHAVE_CCONFIG_H -DHAVE_SIGINFO
export LINK_WCH_NET := $(KERNEL_ROOT)/board/ch32v208rbt6/third_party_driver/ethernet/libwchnet.a
export LINK_WCH_BLE := $(KERNEL_ROOT)/board/ch32v208rbt6/third_party_driver/ble/lib/libwchble.a
export ARCH = risc-v
export MCU = CH32V208

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38
Ubiquitous/XiZi_IIoT/board/ch32v208rbt6/include/connect_uart.h Normal file
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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_uart.h
* @brief define rvstar uart function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022-08-01
*/
#ifndef CONNECT_UART_H
#define CONNECT_UART_H
#include <device.h>
#ifdef __cplusplus
extern "C" {
#endif
int InitHwUart(void);
#ifdef __cplusplus
}
#endif
#endif

224
Ubiquitous/XiZi_IIoT/board/ch32v208rbt6/link.ld Normal file
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ENTRY( _start )
__stack_size = 2048;
PROVIDE( _stack_size = __stack_size );
MEMORY
{
/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */
/*
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K
*/
/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */
/*
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
*/
/* CH32V20x_D8 - CH32V203RB
CH32V20x_D8W - CH32V208x
FLASH + RAM supports the following configuration
FLASH-128K + RAM-64K
FLASH-144K + RAM-48K
FLASH-160K + RAM-32K
*/
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 448K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
}
SECTIONS
{
.init :
{
_sinit = .;
. = ALIGN(4);
KEEP(*(SORT_NONE(.init)))
. = ALIGN(4);
_einit = .;
} >FLASH AT>FLASH
.vector :
{
*(.vector);
. = ALIGN(64);
} >FLASH AT>FLASH
.highcode :
{
. = ALIGN(4);
*(.highcode);
*(.highcode.*);
. = ALIGN(4);
} >FLASH AT>FLASH
.text :
{
. = ALIGN(4);
EXCLUDE_FILE (*wchble.a) *(.text .text*)
*(.text)
*(.text.*)
*(.rodata)
*(.rodata*)
*(.sdata2.*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t.*)
. = ALIGN(4);
/* section information for shell */
. = ALIGN(4);
_shell_command_start = .;
KEEP (*(shellCommand))
_shell_command_end = .;
. = ALIGN(4);
PROVIDE(__ctors_start__ = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
. = ALIGN(4);
__isrtbl_idx_start = .;
KEEP(*(.isrtbl.idx))
__isrtbl_start = .;
KEEP(*(.isrtbl))
__isrtbl_end = .;
. = ALIGN(4);
PROVIDE(g_service_table_start = ABSOLUTE(.));
KEEP(*(.g_service_table))
PROVIDE(g_service_table_end = ABSOLUTE(.));
*(.gnu.linkonce.t.*)
} >FLASH AT>FLASH
.fini :
{
KEEP(*(SORT_NONE(.fini)))
. = ALIGN(4);
} >FLASH AT>FLASH
PROVIDE( _etext = . );
PROVIDE( _eitcm = . );
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH AT>FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH AT>FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH AT>FLASH
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >FLASH AT>FLASH
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >FLASH AT>FLASH
.dalign :
{
. = ALIGN(4);
PROVIDE(_data_vma = .);
} >RAM AT>FLASH
.dlalign :
{
. = ALIGN(4);
PROVIDE(_data_lma = .);
} >FLASH AT>FLASH
.data :
{
*(.gnu.linkonce.r.*)
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.*)
*(.sdata2.*)
*(.gnu.linkonce.s.*)
. = ALIGN(8);
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
. = ALIGN(4);
PROVIDE( _edata = .);
} >RAM AT>FLASH
.bss :
{
. = ALIGN(4);
PROVIDE( _sbss = .);
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss*)
*(.gnu.linkonce.b.*)
*(COMMON*)
. = ALIGN(4);
PROVIDE( _ebss = .);
} >RAM AT>FLASH
PROVIDE( _end = _ebss);
PROVIDE( end = . );
.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
{
PROVIDE( _heap_end = . );
. = ALIGN(4);
PROVIDE(_susrstack = . );
. = . + __stack_size;
PROVIDE( _eusrstack = .);
} >RAM
}

113
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menuconfig BSP_USING_UART
bool "Using UART device"
default y
select RESOURCES_SERIAL
if BSP_USING_UART
source "$BSP_DIR/third_party_driver/uart/Kconfig"
endif
menuconfig BSP_USING_ETH
bool "Using Ethernet"
default y
menuconfig BSP_USING_ADC
bool "Using ADC"
default y
menuconfig BSP_USING_BLE
bool "Using BLE"
default y
if BSP_USING_BLE
config BSP_BLE_CONFIG
bool "Using BLE config"
default y
help
Enable this option to use BLE (Bluetooth Low Energy) to configure settings.
note: prerequisite: [KConfig - ch32v208rbt6 feature] must enable BLE, ETH, LTE, and RS485 modules.
if BSP_BLE_CONFIG
config DEV_BLE_NAME
string "device ble name"
default "ch32v208rbt6"
config DEV_INFO_SYSTEM_ID_0
int "Device Info System ID Element 0"
default 0
config DEV_INFO_SYSTEM_ID_1
int "Device Info System ID Element 1"
default 0
config DEV_INFO_SYSTEM_ID_2
int "Device Info System ID Element 2"
default 0
config DEV_INFO_SYSTEM_ID_3
int "Device Info System ID Element 3"
default 0
config DEV_INFO_SYSTEM_ID_4
int "Device Info System ID Element 4"
default 0
config DEV_INFO_SYSTEM_ID_5
int "Device Info System ID Element 5"
default 1
config DEV_INFO_SYSTEM_ID_6
int "Device Info System ID Element 6"
default 127
config DEV_INFO_SYSTEM_ID_7
int "Device Info System ID Element 7"
default 1
config DEV_INFO_MODEL_NUMBER
string "dev info model number"
default "Model Number"
config DEV_INFO_SERIAL_NUMBER
string "dev info serial number"
default "Serial Number"
config DEV_INFO_FIRMWARE_REV
string "dev info firmware revision"
default "Firmware Revision"
config DEV_INFO_HARDWARE_REV
string "dev info hardware revision"
default "Hardware Revision"
config DEV_INFO_SOFTWARE_REV
string "dev info software revision"
default "Software Revision"
config DEV_INFO_MANUFACTURER_NAME
string "dev info manufacturer name"
default "Manufacturer Name"
endif
endif
menuconfig BSP_USING_CAN
bool "Using CAN device"
default y
select RESOURCES_CAN
if BSP_USING_CAN
source "$BSP_DIR/third_party_driver/can/Kconfig"
endif
menuconfig BSP_USING_RS485
bool "Using RS485"
default y
if BSP_USING_RS485
config RS485_BUS_NAME
string "rs485 bus name"
default "rs485"
config RS485_DRV_NAME
string "rs485 bus driver name"
default "rs485_drv"
config RS485_DEVICE_NAME_1
string "rs485 bus device 1 name"
default "rs485_dev1"
endif
menuconfig BSP_USING_LTE
bool "Using LTE"
default y
if BSP_USING_LTE
config LTE_BUS_NAME
string "lte bus name"
default "lte"
config LTE_DRV_NAME
string "lte bus driver name"
default "lte_drv"
config LTE_DEVICE_NAME_1
string "lte bus device 1 name"
default "lte_dev1"
endif

25
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SRC_FILES := ModuleConfig.c
SRC_DIR := Peripheral
ifeq ($(CONFIG_BSP_USING_UART),y)
SRC_DIR += uart
endif
ifeq ($(CONFIG_BSP_USING_ETH),y)
SRC_DIR += ethernet
endif
ifeq ($(CONFIG_BSP_USING_ADC),y)
SRC_DIR += adc
endif
ifeq ($(CONFIG_BSP_USING_BLE),y)
SRC_DIR += ble
endif
ifeq ($(CONFIG_BSP_USING_CAN),y)
SRC_DIR += can
endif
ifeq ($(CONFIG_BSP_USING_RS485),y)
SRC_DIR += rs485
endif
ifeq ($(CONFIG_BSP_USING_LTE),y)
SRC_DIR += lte
endif
include $(KERNEL_ROOT)/compiler.mk

657
Ubiquitous/XiZi_IIoT/board/ch32v208rbt6/third_party_driver/ModuleConfig.c Normal file
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/**
* @file ModuleConfig.c
* @brief 从FLASH中读取配置信息；解析蓝牙请求，将配置信息写入到FLASH中
* @author Huo Yujia (huoyujia081@126.com)
* @version 1.0
* @date 2024-08-19
* @note 目前的配置信息仅包含4G、以太网、RS485三个模块的内容
*/
#include <ModuleConfig.h>
#include <adapter.h>
#include <connect_ether.h>
#include <peripheral.h>
#include <stdio.h>
#include <string.h>
#include <transform.h>
#include <wchble.h>
__attribute__((aligned(4))) module_cfg defaultConfiguration = {.moduleName = "XiZi",
.type = NET_MODULE_TYPE_TCP_C_DHCP,
.destinationIpAddress_4G = {115, 238, 53, 59},
.destinationPort_4G[0] = 10208 % 256,
.destinationPort_4G[1] = 10208 / 256,
.mqttSwitch_4G = 0,
.mqttTopic_4G = "/SubTopic1",
.mqttUsername_4G = "username",
.mqttPassword_4G = "password",
.mqttClientId_4G = "clientId",
.destinationIpAddress_Ethernet = {115, 238, 53, 59},
.destinationPort_Ethernet[0] = 10208 % 256,
.destinationPort_Ethernet[1] = 10208 / 256,
.dhcpSwitch_Ethernet = 1,
.sourceIpAddress_Ethernet = {192, 168, 137, 10},
.sourcePort_Ethernet[0] = 1000 % 256,
.sourcePort_Ethernet[1] = 1000 / 256,
.sourceSubnetMask_Ethernet = {255, 255, 255, 0},
.sourceGateway_Ethernet = {192, 168, 137, 1},
.baudRate_Rs485 = 3,
.dataBits_Rs485 = 1,
.stopBits_Rs485 = 1,
.parity_Rs485 = 1,
.cfgFlag[0] = checkcode1,
.cfgFlag[1] = checkcode2}; // 默认配置信息
u8 Configbuf[MODULE_CFG_LEN]; // 从flash中读取的配置信息数组
pmodule_cfg CFG = (pmodule_cfg)Configbuf; // 从flash中读取的配置信息指针
pthread_mutex_t romConfigurationMutex; // CFG的互斥锁
/**
* @brief 擦除FLASH块，最小的块为256B
* @param Page_Address 擦除页的开始地址
* @param Length 擦除数据长度
*/
void CFG_ERASE(uint32_t Page_Address, u32 Length) {
u32 NbrOfPage, EraseCounter;
FLASH_Unlock_Fast();
NbrOfPage = Length / FLASH_PAGE_SIZE;
for (EraseCounter = 0; EraseCounter < NbrOfPage; EraseCounter++) {
FLASH_ErasePage_Fast(Page_Address + (FLASH_PAGE_SIZE * EraseCounter));
}
FLASH_Lock_Fast();
}
/**
* @brief 写FLASH数据块
* @param StartAddr 写入页的开始地址
* @param Buffer 写入的数据缓冲区
* @param Length 写入的数据长度
* @return FLASH_Status FLASH状态，定义位置：Ubiquitous/XiZi_IIoT/board/ch32v208rbt6/third_party_driver/Peripheral/inc/ch32v20x_flash.h
*/
FLASH_Status CFG_WRITE(u32 StartAddr, u8 *Buffer, u32 Length) {
u32 address = StartAddr;
u32 *p_buff = (u32 *)Buffer;
FLASH_Status FLASHStatus = FLASH_COMPLETE;
FLASH_Unlock();
while ((address < (StartAddr + Length)) && (FLASHStatus == FLASH_COMPLETE)) {
FLASHStatus = FLASH_ProgramWord(address, *p_buff);
address += 4;
p_buff++;
}
FLASH_Lock();
return FLASHStatus;
}
/**
* @brief 从FLASH中读取数据块
* @param StartAddr 读取页的开始地址
* @param Buffer 读取的数据缓冲区
* @param Length 读取的数据长度
*/
void CFG_READ(u32 StartAddr, u8 *Buffer, u32 Length) {
u32 address = StartAddr;
u32 *p_buff = (u32 *)Buffer;
while (address < (StartAddr + Length)) {
*p_buff = (*(u32 *)address);
address += 4;
p_buff++;
}
}
/**
* @brief 尝试使用配置通过4G连接到服务器，并且蓝牙响应连接状态报文。
* @param requestId 蓝牙请求报文ID
* @note 在解析完成蓝牙请求和写入FLASH配置之后调用该函数
*/
void connectServer_4G(uint8_t requestId) {
uint8_t destinationIpAddress[16] = {}; // 字符串形式的目的IP地址
uint8_t destinationPort[6] = {}; // 字符串形式的目的端口号
struct Adapter *adapter = AdapterDeviceFindByName(ADAPTER_4G_NAME); // 查找以太网模块适配器
/* 如果4G模块仍未初始化，则返回连接失败报文 */
if (adapter->agent == NULL) {
uint8_t notificationReport[4];
notificationReport[0] = requestId;
notificationReport[1] = 0x02;
notificationReport[2] = 0x01;
notificationReport[3] = 0x02;
bStatus_t res;
while ((res = peripheralNotify(notificationReport, sizeof(notificationReport))) != SUCCESS) {
if (res != blePending) { // 发送失败的原因不是阻塞，放弃继续发送
printf("peripheralNotify failed, res: 0x%02x\n", res);
break;
} else { // 发送失败的原因是阻塞，则等待10ms后再次发送
PrivTaskDelay(10);
}
}
return;
}
/* 获取互斥锁 */
PrivMutexObtain(&adapter->lock); // 若其他线程正在使用adapter，则阻塞等待
PrivMutexObtain(&romConfigurationMutex); // 若其他线程正在读取或者写入CFG，则阻塞等待
/* 尝试连接到服务器 */
sprintf(destinationIpAddress, "%u.%u.%u.%u", CFG->destinationIpAddress_4G[0], CFG->destinationIpAddress_Ethernet[1],
CFG->destinationIpAddress_4G[2], CFG->destinationIpAddress_4G[3]);
sprintf(destinationPort, "%hu", (unsigned short)CFG->destinationPort_4G[0] | CFG->destinationPort_4G[1] << 8);
printf("-*-*-*-*-AdapterDeviceConnect*-*-*-*-\n");
printf("destinationIpAddress: %s\n", destinationIpAddress);
printf("destinationPort: %s\n", destinationPort);
printf("-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*--*-*-*\n");
if (CFG->mqttSwitch_4G == 1) { // 如果使能MQTT
AdapterDeviceMqttConnect(adapter, destinationIpAddress, destinationPort, CFG->mqttClientId_4G, CFG->mqttUsername_4G,
CFG->mqttPassword_4G);
} else { // 如果禁用MQTT
AdapterDeviceConnect(adapter, CLIENT, destinationIpAddress, destinationPort, IPV4);
}
/* 蓝牙反馈连接状态 */
AdapterDeviceNetstat(adapter); // 读取网络状态
if (CFG->mqttSwitch_4G == 0 && adapter->network_info.is_connected ||
CFG->mqttSwitch_4G == 1 && adapter->network_info.mqttIsConnected) { // 如果连接成功
/* 释放互斥锁 */
PrivMutexAbandon(&romConfigurationMutex);
PrivMutexAbandon(&adapter->lock);
/* 发送网络连接成功报文 */
uint8_t notificationReport[4];
notificationReport[0] = requestId;
notificationReport[1] = 0x02;
notificationReport[2] = 0x01;
notificationReport[3] = 0x01;
bStatus_t res;
while ((res = peripheralNotify(notificationReport, sizeof(notificationReport))) != SUCCESS) {
if (res != blePending) { // 发送失败的原因不是阻塞，放弃继续发送
printf("peripheralNotify failed, res: 0x%02x\n", res);
break;
} else { // 发送失败的原因是阻塞，则等待10ms后再次发送
PrivTaskDelay(10);
}
}
} else { // 如果连接失败
printf("4G connect to server failed\n");
/* 释放互斥锁 */
PrivMutexAbandon(&romConfigurationMutex);
PrivMutexAbandon(&adapter->lock);
/* 发送网络连接失败报文 */
uint8_t notificationReport[4];
notificationReport[0] = requestId;
notificationReport[1] = 0x02;
notificationReport[2] = 0x01;
notificationReport[3] = 0x02;
bStatus_t res;
while ((res = peripheralNotify(notificationReport, sizeof(notificationReport))) != SUCCESS) {
if (res != blePending) { // 发送失败的原因不是阻塞，放弃继续发送
printf("peripheralNotify failed, res: 0x%02x\n", res);
break;
} else { // 发送失败的原因是阻塞，则等待10ms后再次发送
PrivTaskDelay(10);
}
}
}
return;
}
/**
* @brief 尝试使用配置通过以太网连接到服务器，并且蓝牙响应连接状态报文。
* @param requestId 蓝牙请求报文ID
* @note 在解析完成蓝牙请求和写入FLASH配置之后调用该函数
*/
void connectServer_Ethernet(uint8_t requestId) {
uint8_t destinationIpAddress[16] = {}; // 字符串形式的目的IP地址
uint8_t destinationPort[6] = {}; // 字符串形式的目的端口号
struct Adapter *adapter = AdapterDeviceFindByName(ADAPTER_ETHERNET_NAME); // 查找以太网模块适配器
/* 如果以太网主任务线程仍未启动，则返回连接失败报文 */
if (adapter->adapter_param == NULL) {
uint8_t notificationReport[4];
notificationReport[0] = requestId;
notificationReport[1] = 0x02;
notificationReport[2] = 0x02;
notificationReport[3] = 0x02;
bStatus_t res;
while ((res = peripheralNotify(notificationReport, sizeof(notificationReport))) != SUCCESS) {
if (res != blePending) { // 发送失败的原因不是阻塞，放弃继续发送
printf("peripheralNotify failed, res: 0x%02x\n", res);
break;
} else { // 发送失败的原因是阻塞，则等待10ms后再次发送
PrivTaskDelay(10);
}
}
return;
}
/* 获取互斥锁 */
PrivMutexObtain(&adapter->lock); // 若其他线程正在使用adapter，则阻塞等待
PrivMutexObtain(&romConfigurationMutex); // 若其他线程正在读取或者写入CFG，则阻塞等待
/* DHCP配置 */
if (CFG->dhcpSwitch_Ethernet == 1) { // 使能DHCP
AdapterDeviceSetDhcp(adapter, 1);
} else { // 禁用DHCP
uint8_t sourceIpAddress[16] = {};
uint8_t sourcePort[6] = {};
uint8_t sourceSubnetMask[16] = {};
uint8_t sourceGateway[16] = {};
memcpy(((struct WchnetSocketConfiguration *)adapter->adapter_param)->sourcePort, CFG->sourcePort_Ethernet, 2);
sprintf(sourceIpAddress, "%u.%u.%u.%u", CFG->sourceIpAddress_Ethernet[0], CFG->sourceIpAddress_Ethernet[1],
CFG->sourceIpAddress_Ethernet[2], CFG->sourceIpAddress_Ethernet[3]);
sprintf(sourcePort, "%u", (unsigned short)CFG->sourcePort_Ethernet[0] | CFG->sourcePort_Ethernet[1] << 8);
sprintf(sourceSubnetMask, "%u.%u.%u.%u", CFG->sourceSubnetMask_Ethernet[0], CFG->sourceSubnetMask_Ethernet[1],
CFG->sourceSubnetMask_Ethernet[2], CFG->sourceSubnetMask_Ethernet[3]);
sprintf(sourceGateway, "%u.%u.%u.%u", CFG->sourceGateway_Ethernet[0], CFG->sourceGateway_Ethernet[1],
CFG->sourceGateway_Ethernet[2], CFG->sourceGateway_Ethernet[3]);
AdapterDeviceSetAddr(adapter, sourceIpAddress, sourceGateway, sourceSubnetMask); // 配置静态IP地址
AdapterDeviceSetDhcp(adapter, 0); // 禁用DHCP
}
/* 尝试连接到服务器 */
sprintf(destinationIpAddress, "%u.%u.%u.%u", CFG->destinationIpAddress_Ethernet[0], CFG->destinationIpAddress_Ethernet[1],
CFG->destinationIpAddress_Ethernet[2], CFG->destinationIpAddress_Ethernet[3]);
sprintf(destinationPort, "%u", (unsigned short)CFG->destinationPort_Ethernet[0] | CFG->destinationPort_Ethernet[1] << 8);
printf("-*-*-*-*-AdapterDeviceConnect*-*-*-*-\n");
printf("destinationIpAddress: %s\n", destinationIpAddress);
printf("destinationPort: %s\n", destinationPort);
printf("-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*--*-*-*\n");
int res = AdapterDeviceConnect(adapter, CLIENT, destinationIpAddress, destinationPort, IPV4);
/* 释放互斥锁 */
PrivMutexAbandon(&romConfigurationMutex);
PrivMutexAbandon(&adapter->lock);
/* 蓝牙反馈连接状态 */
if (res == 0 || res == 0x1D) { // 网络连接成功或之前已经连接
/* 发送网络连接成功报文 */
uint8_t notificationReport[4];
notificationReport[0] = requestId;
notificationReport[1] = 0x02;
notificationReport[2] = 0x02;
notificationReport[3] = 0x01;
bStatus_t res;
while ((res = peripheralNotify(notificationReport, sizeof(notificationReport))) != SUCCESS) {
if (res != blePending) { // 发送失败的原因不是阻塞，放弃继续发送
printf("peripheralNotify failed, res: 0x%02x\n", res);
break;
} else { // 发送失败的原因是阻塞，则等待10ms后再次发送
PrivTaskDelay(10);
}
}
} else { // 网络连接失败
printf("Ethernet connect to server failed\n");
/* 发送网络连接失败报文 */
uint8_t notificationReport[4];
notificationReport[0] = requestId;
notificationReport[1] = 0x02;
notificationReport[2] = 0x02;
notificationReport[3] = 0x02;
bStatus_t res;
while ((res = peripheralNotify(notificationReport, sizeof(notificationReport))) != SUCCESS) {
if (res != blePending) { // 发送失败的原因不是阻塞，放弃继续发送
printf("peripheralNotify failed, res: 0x%02x\n", res);
break;
} else { // 发送失败的原因是阻塞，则等待10ms后再次发送
PrivTaskDelay(10);
}
}
}
return;
}
/**
* @brief 解析蓝牙请求报文线程
* @param arg 指向蓝牙请求报文的指针
* @return void* 返回值暂无意义
*/
void *parseBleRequest(void *arg) {
uint8_t *request = (uint8_t *)arg; // 蓝牙请求报文指针
uint8_t requestId = request[0]; // 请求ID
uint8_t reportType = request[1]; // 报文类型
uint8_t moduleType = request[2]; // 模块类型
/* 蓝牙反馈ch32v208已收到蓝牙请求 */
uint8_t notificationReport[3];
notificationReport[0] = requestId;
notificationReport[1] = 0x01;
notificationReport[2] = 0x02;
bStatus_t res;
while ((res = peripheralNotify(notificationReport, sizeof(notificationReport))) != SUCCESS) {
if (res != blePending) { // 发送失败的原因不是阻塞，放弃继续发送
printf("peripheralNotify failed, res: 0x%02x\n", res);
break;
} else { // 发送失败的原因是阻塞，则等待10ms后再次发送
PrivTaskDelay(10);
}
}
/* 解析蓝牙请求报文 */
PrivMutexObtain(&romConfigurationMutex); // // 若其他线程正在读取或者写入CFG，则阻塞等待
switch (reportType) {
/* 4G模块配置目的IP地址、目的端口号、禁用MQTT */
case 0x01: {
uint8_t *destinationIpAddress_4G = request + 3;
uint8_t *destinationPort_4G = request + 7;
uint8_t *mqttSwitch_4G = request + 9;
memcpy(CFG->destinationIpAddress_4G, destinationIpAddress_4G, 4);
memcpy(CFG->destinationPort_4G, destinationPort_4G, 2);
CFG->mqttSwitch_4G = *mqttSwitch_4G;
/* 配置写入FLASH */
CFG_ERASE(PAGE_WRITE_START_ADDR, FLASH_PAGE_SIZE);
CFG_WRITE(PAGE_WRITE_START_ADDR, Configbuf, MODULE_CFG_LEN);
PrivMutexAbandon(&romConfigurationMutex); // 释放互斥锁
connectServer_4G(requestId); // 尝试连接服务器
break;
}
/* 4G模块配置目的IP地址、目的端口号、使能MQTT、MQTT发布主题、MQTT用户名、MQTT密码、MQTT客户端ID */
case 0x02: {
uint8_t *destinationIpAddress_4G = request + 3;
uint8_t *destinationPort_4G = request + 7;
uint8_t *mqttSwitch_4G = request + 9;
uint8_t *mqttTopic_4G = request + 10;
uint8_t *mqttUsername_4G = request + 74;
uint8_t *mqttPassword_4G = request + 138;
uint8_t *mqttClientId_4G = request + 202;
memcpy(CFG->destinationIpAddress_4G, destinationIpAddress_4G, 4);
memcpy(CFG->destinationPort_4G, destinationPort_4G, 2);
CFG->mqttSwitch_4G = *mqttSwitch_4G;
memcpy(CFG->mqttTopic_4G, mqttTopic_4G, 64);
memcpy(CFG->mqttUsername_4G, mqttUsername_4G, 64);
memcpy(CFG->mqttPassword_4G, mqttPassword_4G, 64);
memcpy(CFG->mqttClientId_4G, mqttClientId_4G, 24);
/* 配置写入FLASH */
CFG_ERASE(PAGE_WRITE_START_ADDR, FLASH_PAGE_SIZE);
CFG_WRITE(PAGE_WRITE_START_ADDR, Configbuf, MODULE_CFG_LEN);
PrivMutexAbandon(&romConfigurationMutex); // 释放互斥锁
connectServer_4G(requestId); // 尝试连接服务器
break;
}
/* 以太网模块配置目的IP地址、目的端口号、使能DHCP */
case 0x03: {
uint8_t *destinationIpAddress_Ethernet = request + 3;
uint8_t *destinationPort_Ethernet = request + 7;
uint8_t *dhcpSwitch_Ethernet = request + 9;
memcpy(CFG->destinationIpAddress_Ethernet, destinationIpAddress_Ethernet, 4);
memcpy(CFG->destinationPort_Ethernet, destinationPort_Ethernet, 2);
CFG->dhcpSwitch_Ethernet = *dhcpSwitch_Ethernet;
/* 配置写入FLASH */
CFG_ERASE(PAGE_WRITE_START_ADDR, FLASH_PAGE_SIZE);
CFG_WRITE(PAGE_WRITE_START_ADDR, Configbuf, MODULE_CFG_LEN);
PrivMutexAbandon(&romConfigurationMutex); // 释放互斥锁
connectServer_Ethernet(requestId); // 尝试连接服务器
break;
}
/* 以太网模块配置目的IP地址、目的端口号、禁用DHCP、源IP地址、源端口号、子网掩码、网关地址 */
case 0x04: {
uint8_t *destinationIpAddress_Ethernet = request + 3;
uint8_t *destinationPort_Ethernet = request + 7;
uint8_t *dhcpSwitch_Ethernet = request + 9;
uint8_t *sourceIpAddress_Ethernet = request + 10;
uint8_t *sourcePort_Ethernet = request + 14;
uint8_t *sourceSubnetMask_Ethernet = request + 16;
uint8_t *sourceGateway_Ethernet = request + 20;
memcpy(CFG->destinationIpAddress_Ethernet, destinationIpAddress_Ethernet, 4);
memcpy(CFG->destinationPort_Ethernet, destinationPort_Ethernet, 2);
CFG->dhcpSwitch_Ethernet = *dhcpSwitch_Ethernet;
memcpy(CFG->sourceIpAddress_Ethernet, sourceIpAddress_Ethernet, 4);
memcpy(CFG->sourcePort_Ethernet, sourcePort_Ethernet, 2);
memcpy(CFG->sourceSubnetMask_Ethernet, sourceSubnetMask_Ethernet, 4);
memcpy(CFG->sourceGateway_Ethernet, sourceGateway_Ethernet, 4);
/* 配置写入FLASH */
CFG_ERASE(PAGE_WRITE_START_ADDR, FLASH_PAGE_SIZE);
CFG_WRITE(PAGE_WRITE_START_ADDR, Configbuf, MODULE_CFG_LEN);
PrivMutexAbandon(&romConfigurationMutex); // 释放互斥锁
connectServer_Ethernet(requestId); // 尝试连接服务器
break;
}
/* RS485模块配置波特率、数据位、停止位、校验方式 */
case 0x10: {
struct SerialDataCfg rs485Configuration;
memset(&rs485Configuration, 0, sizeof(struct SerialDataCfg));
int baudRateOption = request[3];
int dataBitsOption = request[4];
int stopBitsOption = request[5];
int parityOption = request[6];
switch (baudRateOption) {
case 1:
rs485Configuration.serial_baud_rate = BAUD_RATE_2400;
break;
case 2:
rs485Configuration.serial_baud_rate = BAUD_RATE_4800;
break;
case 3:
rs485Configuration.serial_baud_rate = BAUD_RATE_9600;
break;
case 4:
rs485Configuration.serial_baud_rate = BAUD_RATE_19200;
break;
case 5:
rs485Configuration.serial_baud_rate = BAUD_RATE_38400;
break;
case 6:
rs485Configuration.serial_baud_rate = BAUD_RATE_57600;
break;
case 7:
rs485Configuration.serial_baud_rate = BAUD_RATE_115200;
break;
case 8:
rs485Configuration.serial_baud_rate = BAUD_RATE_230400;
break;
default:
rs485Configuration.serial_baud_rate = BAUD_RATE_9600;
break;
}
switch (dataBitsOption) {
case 1:
rs485Configuration.serial_data_bits = DATA_BITS_8;
break;
case 2:
rs485Configuration.serial_data_bits = DATA_BITS_9;
break;
default:
rs485Configuration.serial_data_bits = DATA_BITS_8;
break;
}
switch (stopBitsOption) {
case 1:
rs485Configuration.serial_stop_bits = STOP_BITS_1;
break;
case 2:
rs485Configuration.serial_stop_bits = STOP_BITS_2;
break;
default:
rs485Configuration.serial_stop_bits = STOP_BITS_1;
break;
}
switch (parityOption) {
case 1:
rs485Configuration.serial_parity_mode = PARITY_NONE;
break;
case 2:
rs485Configuration.serial_parity_mode = PARITY_ODD;
break;
case 3:
rs485Configuration.serial_parity_mode = PARITY_EVEN;
break;
}
struct PrivIoctlCfg ioctl_cfg;
ioctl_cfg.ioctl_driver_type = SERIAL_TYPE;
ioctl_cfg.args = (void *)&rs485Configuration;
int rs485_fd = PrivOpen("/dev/rs485_dev1", O_RDWR); // 打开设备文件
if (0 != PrivIoctl(rs485_fd, OPE_INT, &ioctl_cfg)) { // 进行配置
printf("ioctl uart fd error %d\n", rs485_fd);
PrivClose(rs485_fd);
return NULL;
}
/* 配置写入FLASH */
CFG->baudRate_Rs485 = baudRateOption;
CFG->dataBits_Rs485 = dataBitsOption;
CFG->stopBits_Rs485 = stopBitsOption;
CFG->parity_Rs485 = parityOption;
CFG_ERASE(PAGE_WRITE_START_ADDR, FLASH_PAGE_SIZE);
CFG_WRITE(PAGE_WRITE_START_ADDR, Configbuf, MODULE_CFG_LEN);
PrivMutexAbandon(&romConfigurationMutex);
break;
}
/* 报文类型识别失败 */
default:
PrivMutexAbandon(&romConfigurationMutex);
break;
}
PrivFree(request); // 释放内存
return NULL;
}
/**
* @brief 启动解析蓝牙请求报文的线程
* @param request 指向蓝牙请求报文的指针
*/
void startParseBleRequestTask(uint8_t *request) {
/* 启动蓝牙交互的线程 */
pthread_attr_t parseBleRequestTaskAttr;
pthread_args_t parseBleRequestTaskArgs;
parseBleRequestTaskAttr.schedparam.sched_priority = 16; // 线程优先级
parseBleRequestTaskAttr.stacksize = 2048; // 线程栈大小
parseBleRequestTaskArgs.pthread_name = "parseBleRequestTask"; // 线程名字
parseBleRequestTaskArgs.arg = request; // 线程参数
pthread_t parseBleRequestThread; // 线程ID
PrivTaskCreate(&parseBleRequestThread, &parseBleRequestTaskAttr, parseBleRequest, &parseBleRequestTaskArgs);
PrivTaskStartup(&parseBleRequestThread);
}
/**
* @brief 命令行显示配置信息
* @return int 返回值暂无意义
* @note 命令形式：ShowConfig
*/
int ShowConfig(void) {
/* 输出配置信息 */
KPrintf("\n*************rom configuration****************\n");
KPrintf("moduleName:\t%s\n", CFG->moduleName);
KPrintf("type:\t\t%u\n", CFG->type);
/* 4G模块目的IP和端口号配置 */
KPrintf("----------------------------------------------\n");
KPrintf(" 4G \n");
KPrintf("destinationIpAddress:\t\t%u.%u.%u.%u\n", CFG->destinationIpAddress_4G[0], CFG->destinationIpAddress_4G[1],
CFG->destinationIpAddress_4G[2], CFG->destinationIpAddress_4G[3]);
KPrintf("destinationPort: \t\t%hu\n", (unsigned short)CFG->destinationPort_4G[0] | CFG->destinationPort_4G[1] << 8);
/* 4G模块MQTT配置 */
KPrintf("mqttSwitch: \t\t\t%s\n", CFG->mqttSwitch_4G ? "on" : "off");
KPrintf("mqttTopic: \t\t\t%s\n", CFG->mqttTopic_4G);
KPrintf("mqttUsername:\t\t\t%s\n", CFG->mqttUsername_4G);
KPrintf("mqttPassword:\t\t\t%s\n", CFG->mqttPassword_4G);
KPrintf("mqttClientId:\t\t\t%s\n", CFG->mqttClientId_4G);
/* Ethernet模块配置 */
KPrintf("----------------------------------------------\n");
KPrintf(" Ethernet \n");
KPrintf("destinationIpAddress: \t\t%u.%u.%u.%u\n", CFG->destinationIpAddress_Ethernet[0], CFG->destinationIpAddress_Ethernet[1],
CFG->destinationIpAddress_Ethernet[2], CFG->destinationIpAddress_Ethernet[3]);
KPrintf("destinationPort: \t\t%hu\n", (unsigned short)CFG->destinationPort_Ethernet[0] | CFG->destinationPort_Ethernet[1] << 8);
KPrintf("dhcpSwitch: \t\t\t%s\n", CFG->dhcpSwitch_Ethernet ? "on" : "off");
KPrintf("sourceIpAddress: \t\t%u.%u.%u.%u\n", CFG->sourceIpAddress_Ethernet[0], CFG->sourceIpAddress_Ethernet[1],
CFG->sourceIpAddress_Ethernet[2], CFG->sourceIpAddress_Ethernet[3]);
KPrintf("sourcePort: \t\t\t%hu\n", (unsigned short)CFG->sourcePort_Ethernet[0] | CFG->sourcePort_Ethernet[1] << 8);
KPrintf("sourceSubnetMask: \t\t%u.%u.%u.%u\n", CFG->sourceSubnetMask_Ethernet[0], CFG->sourceSubnetMask_Ethernet[1],
CFG->sourceSubnetMask_Ethernet[2], CFG->sourceSubnetMask_Ethernet[3]);
KPrintf("sourceClientGateway: \t\t%u.%u.%u.%u\n", CFG->sourceGateway_Ethernet[0], CFG->sourceGateway_Ethernet[1],
CFG->sourceGateway_Ethernet[2], CFG->sourceGateway_Ethernet[3]);
/* RS485模块配置 */
KPrintf("----------------------------------------------\n");
KPrintf(" Rs485 \n");
int baudRate_Rs485;
int dataBits_Rs485;
int stopBits_Rs485;
char *parity_Rs485;
switch (CFG->baudRate_Rs485) {
case 1:
baudRate_Rs485 = BAUD_RATE_2400;
break;
case 2:
baudRate_Rs485 = BAUD_RATE_4800;
break;
case 3:
baudRate_Rs485 = BAUD_RATE_9600;
break;
case 4:
baudRate_Rs485 = BAUD_RATE_19200;
break;
case 5:
baudRate_Rs485 = BAUD_RATE_38400;
break;
case 6:
baudRate_Rs485 = BAUD_RATE_57600;
break;
case 7:
baudRate_Rs485 = BAUD_RATE_115200;
break;
case 8:
baudRate_Rs485 = BAUD_RATE_230400;
break;
default:
baudRate_Rs485 = BAUD_RATE_9600;
break;
}
switch (CFG->dataBits_Rs485) {
case 1:
dataBits_Rs485 = DATA_BITS_8;
break;
case 2:
dataBits_Rs485 = DATA_BITS_9;
break;
default:
dataBits_Rs485 = DATA_BITS_8;
break;
}
switch (CFG->stopBits_Rs485) {
case 1:
stopBits_Rs485 = STOP_BITS_1;
break;
case 2:
stopBits_Rs485 = STOP_BITS_2;
break;
default:
stopBits_Rs485 = STOP_BITS_1;
}
switch (CFG->parity_Rs485) {
case 1:
parity_Rs485 = "NONE";
break;
case 2:
parity_Rs485 = "ODD";
break;
case 3:
parity_Rs485 = "EVEN";
break;
default:
parity_Rs485 = "NONE";
break;
}
KPrintf("baudRate:\t\t\t%d\n", baudRate_Rs485);
KPrintf("dataBits:\t\t\t%d\n", dataBits_Rs485);
KPrintf("stopBits:\t\t\t%d\n", stopBits_Rs485);
KPrintf("parity:\t\t\t\t%s\n", parity_Rs485);
/* 配置有效位校验 */
KPrintf("----------------------------------------------\n");
KPrintf("cfg_flag: 0x%02x 0x%02x\n", CFG->cfgFlag[0], CFG->cfgFlag[1]);
KPrintf("**********************************************\n\n");
return 0;
}
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC), ShowConfig, ShowConfig, list configuration information);

3
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SRC_DIR := src
include $(KERNEL_ROOT)/compiler.mk

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_adc.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* ADC firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_ADC_H
#define __CH32V20x_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* ADC Init structure definition */
typedef struct
{
uint32_t ADC_Mode; /* Configures the ADC to operate in independent or
dual mode.
This parameter can be a value of @ref ADC_mode */
FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in
Scan (multichannels) or Single (one channel) mode.
This parameter can be set to ENABLE or DISABLE */
FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in
Continuous or Single mode.
This parameter can be set to ENABLE or DISABLE. */
uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog
to digital conversion of regular channels. This parameter
can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right.
This parameter can be a value of @ref ADC_data_align */
uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted
using the sequencer for regular channel group.
This parameter must range from 1 to 16. */
uint32_t ADC_OutputBuffer; /* Specifies whether the ADC channel output buffer is enabled or disabled.
This parameter can be a value of @ref ADC_OutputBuffer */
uint32_t ADC_Pga; /* Specifies the PGA gain multiple.
This parameter can be a value of @ref ADC_Pga */
} ADC_InitTypeDef;
/* ADC_mode */
#define ADC_Mode_Independent ((uint32_t)0x00000000)
#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)
#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)
#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)
#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)
#define ADC_Mode_InjecSimult ((uint32_t)0x00050000)
#define ADC_Mode_RegSimult ((uint32_t)0x00060000)
#define ADC_Mode_FastInterl ((uint32_t)0x00070000)
#define ADC_Mode_SlowInterl ((uint32_t)0x00080000)
#define ADC_Mode_AlterTrig ((uint32_t)0x00090000)
/* ADC_external_trigger_sources_for_regular_channels_conversion */
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000)
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000)
#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000)
#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000)
#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000)
#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000)
#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000)
#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000)
#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000)
#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000)
#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000)
#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000)
#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000)
/* ADC_data_align */
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
#define ADC_DataAlign_Left ((uint32_t)0x00000800)
/* ADC_channels */
#define ADC_Channel_0 ((uint8_t)0x00)
#define ADC_Channel_1 ((uint8_t)0x01)
#define ADC_Channel_2 ((uint8_t)0x02)
#define ADC_Channel_3 ((uint8_t)0x03)
#define ADC_Channel_4 ((uint8_t)0x04)
#define ADC_Channel_5 ((uint8_t)0x05)
#define ADC_Channel_6 ((uint8_t)0x06)
#define ADC_Channel_7 ((uint8_t)0x07)
#define ADC_Channel_8 ((uint8_t)0x08)
#define ADC_Channel_9 ((uint8_t)0x09)
#define ADC_Channel_10 ((uint8_t)0x0A)
#define ADC_Channel_11 ((uint8_t)0x0B)
#define ADC_Channel_12 ((uint8_t)0x0C)
#define ADC_Channel_13 ((uint8_t)0x0D)
#define ADC_Channel_14 ((uint8_t)0x0E)
#define ADC_Channel_15 ((uint8_t)0x0F)
#define ADC_Channel_16 ((uint8_t)0x10)
#define ADC_Channel_17 ((uint8_t)0x11)
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
/*ADC_output_buffer*/
#define ADC_OutputBuffer_Enable ((uint32_t)0x04000000)
#define ADC_OutputBuffer_Disable ((uint32_t)0x00000000)
/*ADC_pga*/
#define ADC_Pga_1 ((uint32_t)0x00000000)
#define ADC_Pga_4 ((uint32_t)0x08000000)
#define ADC_Pga_16 ((uint32_t)0x10000000)
#define ADC_Pga_64 ((uint32_t)0x18000000)
/* ADC_sampling_time */
#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00)
#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01)
#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02)
#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03)
#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04)
#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05)
#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06)
#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07)
/* ADC_external_trigger_sources_for_injected_channels_conversion */
#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000)
#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000)
#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000)
#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000)
#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000)
#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000)
#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000)
#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000)
#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000)
#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000)
#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000)
#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000)
#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000)
/* ADC_injected_channel_selection */
#define ADC_InjectedChannel_1 ((uint8_t)0x14)
#define ADC_InjectedChannel_2 ((uint8_t)0x18)
#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
#define ADC_InjectedChannel_4 ((uint8_t)0x20)
/* ADC_analog_watchdog_selection */
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
/* ADC_interrupts_definition */
#define ADC_IT_EOC ((uint16_t)0x0220)
#define ADC_IT_AWD ((uint16_t)0x0140)
#define ADC_IT_JEOC ((uint16_t)0x0480)
/* ADC_flags_definition */
#define ADC_FLAG_AWD ((uint8_t)0x01)
#define ADC_FLAG_EOC ((uint8_t)0x02)
#define ADC_FLAG_JEOC ((uint8_t)0x04)
#define ADC_FLAG_JSTRT ((uint8_t)0x08)
#define ADC_FLAG_STRT ((uint8_t)0x10)
void ADC_DeInit(ADC_TypeDef *ADCx);
void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct);
void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct);
void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState);
void ADC_ResetCalibration(ADC_TypeDef *ADCx);
FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx);
void ADC_StartCalibration(ADC_TypeDef *ADCx);
FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx);
void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx);
void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number);
void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx);
uint32_t ADC_GetDualModeConversionValue(void);
void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv);
void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx);
void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length);
void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel);
void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog);
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel);
void ADC_TempSensorVrefintCmd(FunctionalState NewState);
FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG);
void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG);
ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT);
void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT);
s32 TempSensor_Volt_To_Temper(s32 Value);
void ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
int16_t Get_CalibrationValue(ADC_TypeDef *ADCx);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_bkp.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* BKP firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_BKP_H
#define __CH32V20x_BKP_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* Tamper_Pin_active_level */
#define BKP_TamperPinLevel_High ((uint16_t)0x0000)
#define BKP_TamperPinLevel_Low ((uint16_t)0x0001)
/* RTC_output_source_to_output_on_the_Tamper_pin */
#define BKP_RTCOutputSource_None ((uint16_t)0x0000)
#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080)
#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100)
#define BKP_RTCOutputSource_Second ((uint16_t)0x0300)
/* Data_Backup_Register */
#define BKP_DR1 ((uint16_t)0x0004)
#define BKP_DR2 ((uint16_t)0x0008)
#define BKP_DR3 ((uint16_t)0x000C)
#define BKP_DR4 ((uint16_t)0x0010)
#define BKP_DR5 ((uint16_t)0x0014)
#define BKP_DR6 ((uint16_t)0x0018)
#define BKP_DR7 ((uint16_t)0x001C)
#define BKP_DR8 ((uint16_t)0x0020)
#define BKP_DR9 ((uint16_t)0x0024)
#define BKP_DR10 ((uint16_t)0x0028)
#define BKP_DR11 ((uint16_t)0x0040)
#define BKP_DR12 ((uint16_t)0x0044)
#define BKP_DR13 ((uint16_t)0x0048)
#define BKP_DR14 ((uint16_t)0x004C)
#define BKP_DR15 ((uint16_t)0x0050)
#define BKP_DR16 ((uint16_t)0x0054)
#define BKP_DR17 ((uint16_t)0x0058)
#define BKP_DR18 ((uint16_t)0x005C)
#define BKP_DR19 ((uint16_t)0x0060)
#define BKP_DR20 ((uint16_t)0x0064)
#define BKP_DR21 ((uint16_t)0x0068)
#define BKP_DR22 ((uint16_t)0x006C)
#define BKP_DR23 ((uint16_t)0x0070)
#define BKP_DR24 ((uint16_t)0x0074)
#define BKP_DR25 ((uint16_t)0x0078)
#define BKP_DR26 ((uint16_t)0x007C)
#define BKP_DR27 ((uint16_t)0x0080)
#define BKP_DR28 ((uint16_t)0x0084)
#define BKP_DR29 ((uint16_t)0x0088)
#define BKP_DR30 ((uint16_t)0x008C)
#define BKP_DR31 ((uint16_t)0x0090)
#define BKP_DR32 ((uint16_t)0x0094)
#define BKP_DR33 ((uint16_t)0x0098)
#define BKP_DR34 ((uint16_t)0x009C)
#define BKP_DR35 ((uint16_t)0x00A0)
#define BKP_DR36 ((uint16_t)0x00A4)
#define BKP_DR37 ((uint16_t)0x00A8)
#define BKP_DR38 ((uint16_t)0x00AC)
#define BKP_DR39 ((uint16_t)0x00B0)
#define BKP_DR40 ((uint16_t)0x00B4)
#define BKP_DR41 ((uint16_t)0x00B8)
#define BKP_DR42 ((uint16_t)0x00BC)
void BKP_DeInit(void);
void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
void BKP_TamperPinCmd(FunctionalState NewState);
void BKP_ITConfig(FunctionalState NewState);
void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
FlagStatus BKP_GetFlagStatus(void);
void BKP_ClearFlag(void);
ITStatus BKP_GetITStatus(void);
void BKP_ClearITPendingBit(void);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_can.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* CAN firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_CAN_H
#define __CH32V20x_CAN_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* CAN init structure definition */
typedef struct
{
uint16_t CAN_Prescaler; /* Specifies the length of a time quantum.
It ranges from 1 to 1024. */
uint8_t CAN_Mode; /* Specifies the CAN operating mode.
This parameter can be a value of
@ref CAN_operating_mode */
uint8_t CAN_SJW; /* Specifies the maximum number of time quanta
the CAN hardware is allowed to lengthen or
shorten a bit to perform resynchronization.
This parameter can be a value of
@ref CAN_synchronisation_jump_width */
uint8_t CAN_BS1; /* Specifies the number of time quanta in Bit
Segment 1. This parameter can be a value of
@ref CAN_time_quantum_in_bit_segment_1 */
uint8_t CAN_BS2; /* Specifies the number of time quanta in Bit
Segment 2.
This parameter can be a value of
@ref CAN_time_quantum_in_bit_segment_2 */
FunctionalState CAN_TTCM; /* Enable or disable the time triggered
communication mode. This parameter can be set
either to ENABLE or DISABLE. */
FunctionalState CAN_ABOM; /* Enable or disable the automatic bus-off
management. This parameter can be set either
to ENABLE or DISABLE. */
FunctionalState CAN_AWUM; /* Enable or disable the automatic wake-up mode.
This parameter can be set either to ENABLE or
DISABLE. */
FunctionalState CAN_NART; /* Enable or disable the no-automatic
retransmission mode. This parameter can be
set either to ENABLE or DISABLE. */
FunctionalState CAN_RFLM; /* Enable or disable the Receive FIFO Locked mode.
This parameter can be set either to ENABLE
or DISABLE. */
FunctionalState CAN_TXFP; /* Enable or disable the transmit FIFO priority.
This parameter can be set either to ENABLE
or DISABLE. */
} CAN_InitTypeDef;
/* CAN filter init structure definition */
typedef struct
{
uint16_t CAN_FilterIdHigh; /* Specifies the filter identification number (MSBs for a 32-bit
configuration, first one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
uint16_t CAN_FilterIdLow; /* Specifies the filter identification number (LSBs for a 32-bit
configuration, second one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
uint16_t CAN_FilterMaskIdHigh; /* Specifies the filter mask number or identification number,
according to the mode (MSBs for a 32-bit configuration,
first one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
uint16_t CAN_FilterMaskIdLow; /* Specifies the filter mask number or identification number,
according to the mode (LSBs for a 32-bit configuration,
second one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
uint16_t CAN_FilterFIFOAssignment; /* Specifies the FIFO (0 or 1) which will be assigned to the filter.
This parameter can be a value of @ref CAN_filter_FIFO */
uint8_t CAN_FilterNumber; /* Specifies the filter which will be initialized. It ranges from 0 to 13. */
uint8_t CAN_FilterMode; /* Specifies the filter mode to be initialized.
This parameter can be a value of @ref CAN_filter_mode */
uint8_t CAN_FilterScale; /* Specifies the filter scale.
This parameter can be a value of @ref CAN_filter_scale */
FunctionalState CAN_FilterActivation; /* Enable or disable the filter.
This parameter can be set either to ENABLE or DISABLE. */
} CAN_FilterInitTypeDef;
/* CAN Tx message structure definition */
typedef struct
{
uint32_t StdId; /* Specifies the standard identifier.
This parameter can be a value between 0 to 0x7FF. */
uint32_t ExtId; /* Specifies the extended identifier.
This parameter can be a value between 0 to 0x1FFFFFFF. */
uint8_t IDE; /* Specifies the type of identifier for the message that
will be transmitted. This parameter can be a value
of @ref CAN_identifier_type */
uint8_t RTR; /* Specifies the type of frame for the message that will
be transmitted. This parameter can be a value of
@ref CAN_remote_transmission_request */
uint8_t DLC; /* Specifies the length of the frame that will be
transmitted. This parameter can be a value between
0 to 8 */
uint8_t Data[8]; /* Contains the data to be transmitted. It ranges from 0
to 0xFF. */
} CanTxMsg;
/* CAN Rx message structure definition */
typedef struct
{
uint32_t StdId; /* Specifies the standard identifier.
This parameter can be a value between 0 to 0x7FF. */
uint32_t ExtId; /* Specifies the extended identifier.
This parameter can be a value between 0 to 0x1FFFFFFF. */
uint8_t IDE; /* Specifies the type of identifier for the message that
will be received. This parameter can be a value of
@ref CAN_identifier_type */
uint8_t RTR; /* Specifies the type of frame for the received message.
This parameter can be a value of
@ref CAN_remote_transmission_request */
uint8_t DLC; /* Specifies the length of the frame that will be received.
This parameter can be a value between 0 to 8 */
uint8_t Data[8]; /* Contains the data to be received. It ranges from 0 to
0xFF. */
uint8_t FMI; /* Specifies the index of the filter the message stored in
the mailbox passes through. This parameter can be a
value between 0 to 0xFF */
} CanRxMsg;
/* CAN_sleep_constants */
#define CAN_InitStatus_Failed ((uint8_t)0x00) /* CAN initialization failed */
#define CAN_InitStatus_Success ((uint8_t)0x01) /* CAN initialization OK */
/* CAN_Mode */
#define CAN_Mode_Normal ((uint8_t)0x00) /* normal mode */
#define CAN_Mode_LoopBack ((uint8_t)0x01) /* loopback mode */
#define CAN_Mode_Silent ((uint8_t)0x02) /* silent mode */
#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /* loopback combined with silent mode */
/* CAN_Operating_Mode */
#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /* Initialization mode */
#define CAN_OperatingMode_Normal ((uint8_t)0x01) /* Normal mode */
#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /* sleep mode */
/* CAN_Mode_Status */
#define CAN_ModeStatus_Failed ((uint8_t)0x00) /* CAN entering the specific mode failed */
#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /* CAN entering the specific mode Succeed */
/* CAN_synchronisation_jump_width */
#define CAN_SJW_1tq ((uint8_t)0x00) /* 1 time quantum */
#define CAN_SJW_2tq ((uint8_t)0x01) /* 2 time quantum */
#define CAN_SJW_3tq ((uint8_t)0x02) /* 3 time quantum */
#define CAN_SJW_4tq ((uint8_t)0x03) /* 4 time quantum */
/* CAN_time_quantum_in_bit_segment_1 */
#define CAN_BS1_1tq ((uint8_t)0x00) /* 1 time quantum */
#define CAN_BS1_2tq ((uint8_t)0x01) /* 2 time quantum */
#define CAN_BS1_3tq ((uint8_t)0x02) /* 3 time quantum */
#define CAN_BS1_4tq ((uint8_t)0x03) /* 4 time quantum */
#define CAN_BS1_5tq ((uint8_t)0x04) /* 5 time quantum */
#define CAN_BS1_6tq ((uint8_t)0x05) /* 6 time quantum */
#define CAN_BS1_7tq ((uint8_t)0x06) /* 7 time quantum */
#define CAN_BS1_8tq ((uint8_t)0x07) /* 8 time quantum */
#define CAN_BS1_9tq ((uint8_t)0x08) /* 9 time quantum */
#define CAN_BS1_10tq ((uint8_t)0x09) /* 10 time quantum */
#define CAN_BS1_11tq ((uint8_t)0x0A) /* 11 time quantum */
#define CAN_BS1_12tq ((uint8_t)0x0B) /* 12 time quantum */
#define CAN_BS1_13tq ((uint8_t)0x0C) /* 13 time quantum */
#define CAN_BS1_14tq ((uint8_t)0x0D) /* 14 time quantum */
#define CAN_BS1_15tq ((uint8_t)0x0E) /* 15 time quantum */
#define CAN_BS1_16tq ((uint8_t)0x0F) /* 16 time quantum */
/* CAN_time_quantum_in_bit_segment_2 */
#define CAN_BS2_1tq ((uint8_t)0x00) /* 1 time quantum */
#define CAN_BS2_2tq ((uint8_t)0x01) /* 2 time quantum */
#define CAN_BS2_3tq ((uint8_t)0x02) /* 3 time quantum */
#define CAN_BS2_4tq ((uint8_t)0x03) /* 4 time quantum */
#define CAN_BS2_5tq ((uint8_t)0x04) /* 5 time quantum */
#define CAN_BS2_6tq ((uint8_t)0x05) /* 6 time quantum */
#define CAN_BS2_7tq ((uint8_t)0x06) /* 7 time quantum */
#define CAN_BS2_8tq ((uint8_t)0x07) /* 8 time quantum */
/* CAN_filter_mode */
#define CAN_FilterMode_IdMask ((uint8_t)0x00) /* identifier/mask mode */
#define CAN_FilterMode_IdList ((uint8_t)0x01) /* identifier list mode */
/* CAN_filter_scale */
#define CAN_FilterScale_16bit ((uint8_t)0x00) /* Two 16-bit filters */
#define CAN_FilterScale_32bit ((uint8_t)0x01) /* One 32-bit filter */
/* CAN_filter_FIFO */
#define CAN_Filter_FIFO0 ((uint8_t)0x00) /* Filter FIFO 0 assignment for filter x */
#define CAN_Filter_FIFO1 ((uint8_t)0x01) /* Filter FIFO 1 assignment for filter x */
/* CAN_identifier_type */
#define CAN_Id_Standard ((uint32_t)0x00000000) /* Standard Id */
#define CAN_Id_Extended ((uint32_t)0x00000004) /* Extended Id */
/* CAN_remote_transmission_request */
#define CAN_RTR_Data ((uint32_t)0x00000000) /* Data frame */
#define CAN_RTR_Remote ((uint32_t)0x00000002) /* Remote frame */
/* CAN_transmit_constants */
#define CAN_TxStatus_Failed ((uint8_t)0x00) /* CAN transmission failed */
#define CAN_TxStatus_Ok ((uint8_t)0x01) /* CAN transmission succeeded */
#define CAN_TxStatus_Pending ((uint8_t)0x02) /* CAN transmission pending */
#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /* CAN cell did not provide an empty mailbox */
/* CAN_receive_FIFO_number_constants */
#define CAN_FIFO0 ((uint8_t)0x00) /* CAN FIFO 0 used to receive */
#define CAN_FIFO1 ((uint8_t)0x01) /* CAN FIFO 1 used to receive */
/* CAN_sleep_constants */
#define CAN_Sleep_Failed ((uint8_t)0x00) /* CAN did not enter the sleep mode */
#define CAN_Sleep_Ok ((uint8_t)0x01) /* CAN entered the sleep mode */
/* CAN_wake_up_constants */
#define CAN_WakeUp_Failed ((uint8_t)0x00) /* CAN did not leave the sleep mode */
#define CAN_WakeUp_Ok ((uint8_t)0x01) /* CAN leaved the sleep mode */
/* CAN_Error_Code_constants */
#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /* No Error */
#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /* Stuff Error */
#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /* Form Error */
#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /* Acknowledgment Error */
#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /* Bit Recessive Error */
#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /* Bit Dominant Error */
#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /* CRC Error */
#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /* Software Set Error */
/* CAN_flags */
/* Transmit Flags */
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
* and CAN_ClearFlag() functions.
* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function.
*/
#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /* Request MailBox0 Flag */
#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /* Request MailBox1 Flag */
#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /* Request MailBox2 Flag */
/* Receive Flags */
#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /* FIFO 0 Message Pending Flag */
#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /* FIFO 0 Full Flag */
#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /* FIFO 0 Overrun Flag */
#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /* FIFO 1 Message Pending Flag */
#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /* FIFO 1 Full Flag */
#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /* FIFO 1 Overrun Flag */
/* Operating Mode Flags */
#define CAN_FLAG_WKU ((uint32_t)0x31000008) /* Wake up Flag */
#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /* Sleep acknowledge Flag */
/* Note:
*When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible.
*In this case the SLAK bit can be polled.
*/
/* Error Flags */
#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /* Error Warning Flag */
#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /* Error Passive Flag */
#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /* Bus-Off Flag */
#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /* Last error code Flag */
/* CAN_interrupts */
#define CAN_IT_TME ((uint32_t)0x00000001) /* Transmit mailbox empty Interrupt*/
/* Receive Interrupts */
#define CAN_IT_FMP0 ((uint32_t)0x00000002) /* FIFO 0 message pending Interrupt*/
#define CAN_IT_FF0 ((uint32_t)0x00000004) /* FIFO 0 full Interrupt*/
#define CAN_IT_FOV0 ((uint32_t)0x00000008) /* FIFO 0 overrun Interrupt*/
#define CAN_IT_FMP1 ((uint32_t)0x00000010) /* FIFO 1 message pending Interrupt*/
#define CAN_IT_FF1 ((uint32_t)0x00000020) /* FIFO 1 full Interrupt*/
#define CAN_IT_FOV1 ((uint32_t)0x00000040) /* FIFO 1 overrun Interrupt*/
/* Operating Mode Interrupts */
#define CAN_IT_WKU ((uint32_t)0x00010000) /* Wake-up Interrupt*/
#define CAN_IT_SLK ((uint32_t)0x00020000) /* Sleep acknowledge Interrupt*/
/* Error Interrupts */
#define CAN_IT_EWG ((uint32_t)0x00000100) /* Error warning Interrupt*/
#define CAN_IT_EPV ((uint32_t)0x00000200) /* Error passive Interrupt*/
#define CAN_IT_BOF ((uint32_t)0x00000400) /* Bus-off Interrupt*/
#define CAN_IT_LEC ((uint32_t)0x00000800) /* Last error code Interrupt*/
#define CAN_IT_ERR ((uint32_t)0x00008000) /* Error Interrupt*/
/* Flags named as Interrupts : kept only for FW compatibility */
#define CAN_IT_RQCP0 CAN_IT_TME
#define CAN_IT_RQCP1 CAN_IT_TME
#define CAN_IT_RQCP2 CAN_IT_TME
/* CAN_Legacy */
#define CANINITFAILED CAN_InitStatus_Failed
#define CANINITOK CAN_InitStatus_Success
#define CAN_FilterFIFO0 CAN_Filter_FIFO0
#define CAN_FilterFIFO1 CAN_Filter_FIFO1
#define CAN_ID_STD CAN_Id_Standard
#define CAN_ID_EXT CAN_Id_Extended
#define CAN_RTR_DATA CAN_RTR_Data
#define CAN_RTR_REMOTE CAN_RTR_Remote
#define CANTXFAILE CAN_TxStatus_Failed
#define CANTXOK CAN_TxStatus_Ok
#define CANTXPENDING CAN_TxStatus_Pending
#define CAN_NO_MB CAN_TxStatus_NoMailBox
#define CANSLEEPFAILED CAN_Sleep_Failed
#define CANSLEEPOK CAN_Sleep_Ok
#define CANWAKEUPFAILED CAN_WakeUp_Failed
#define CANWAKEUPOK CAN_WakeUp_Ok
void CAN_DeInit(CAN_TypeDef *CANx);
uint8_t CAN_Init(CAN_TypeDef *CANx, CAN_InitTypeDef *CAN_InitStruct);
void CAN_FilterInit(CAN_FilterInitTypeDef *CAN_FilterInitStruct);
void CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct);
void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
void CAN_DBGFreeze(CAN_TypeDef *CANx, FunctionalState NewState);
void CAN_TTComModeCmd(CAN_TypeDef *CANx, FunctionalState NewState);
uint8_t CAN_Transmit(CAN_TypeDef *CANx, CanTxMsg *TxMessage);
uint8_t CAN_TransmitStatus(CAN_TypeDef *CANx, uint8_t TransmitMailbox);
void CAN_CancelTransmit(CAN_TypeDef *CANx, uint8_t Mailbox);
void CAN_Receive(CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMsg *RxMessage);
void CAN_FIFORelease(CAN_TypeDef *CANx, uint8_t FIFONumber);
uint8_t CAN_MessagePending(CAN_TypeDef *CANx, uint8_t FIFONumber);
uint8_t CAN_OperatingModeRequest(CAN_TypeDef *CANx, uint8_t CAN_OperatingMode);
uint8_t CAN_Sleep(CAN_TypeDef *CANx);
uint8_t CAN_WakeUp(CAN_TypeDef *CANx);
uint8_t CAN_GetLastErrorCode(CAN_TypeDef *CANx);
uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef *CANx);
uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef *CANx);
void CAN_ITConfig(CAN_TypeDef *CANx, uint32_t CAN_IT, FunctionalState NewState);
FlagStatus CAN_GetFlagStatus(CAN_TypeDef *CANx, uint32_t CAN_FLAG);
void CAN_ClearFlag(CAN_TypeDef *CANx, uint32_t CAN_FLAG);
ITStatus CAN_GetITStatus(CAN_TypeDef *CANx, uint32_t CAN_IT);
void CAN_ClearITPendingBit(CAN_TypeDef *CANx, uint32_t CAN_IT);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_crc.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* CRC firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_CRC_H
#define __CH32V20x_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
void CRC_ResetDR(void);
uint32_t CRC_CalcCRC(uint32_t Data);
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
uint32_t CRC_GetCRC(void);
void CRC_SetIDRegister(uint8_t IDValue);
uint8_t CRC_GetIDRegister(void);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_dbgmcu.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* DBGMCU firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_DBGMCU_H
#define __CH32V20x_DBGMCU_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
#define DBGMCU_SLEEP ((uint32_t)0x00000001)
#define DBGMCU_STOP ((uint32_t)0x00000002)
#define DBGMCU_STANDBY ((uint32_t)0x00000004)
#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)
#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)
#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00000400)
#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00000800)
#define DBGMCU_TIM1_STOP ((uint32_t)0x00001000)
#define DBGMCU_TIM2_STOP ((uint32_t)0x00002000)
#define DBGMCU_TIM3_STOP ((uint32_t)0x00004000)
#define DBGMCU_TIM4_STOP ((uint32_t)0x00008000)
#define DBGMCU_TIM5_STOP ((uint32_t)0x00010000)
#define DBGMCU_TIM6_STOP ((uint32_t)0x00020000)
#define DBGMCU_TIM7_STOP ((uint32_t)0x00040000)
#define DBGMCU_TIM8_STOP ((uint32_t)0x00080000)
#define DBGMCU_CAN1_STOP ((uint32_t)0x00100000)
#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000)
#define DBGMCU_TIM9_STOP ((uint32_t)0x00400000)
#define DBGMCU_TIM10_STOP ((uint32_t)0x00800000)
uint32_t DBGMCU_GetREVID(void);
uint32_t DBGMCU_GetDEVID(void);
uint32_t __get_DEBUG_CR(void);
void __set_DEBUG_CR(uint32_t value);
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
uint32_t DBGMCU_GetCHIPID( void );
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_dma.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* DMA firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_DMA_H
#define __CH32V20x_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* DMA Init structure definition */
typedef struct
{
uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */
uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */
uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination.
This parameter can be a value of @ref DMA_data_transfer_direction */
uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel.
The data unit is equal to the configuration set in DMA_PeripheralDataSize
or DMA_MemoryDataSize members depending in the transfer direction. */
uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not.
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not.
This parameter can be a value of @ref DMA_memory_incremented_mode */
uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width.
This parameter can be a value of @ref DMA_peripheral_data_size */
uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width.
This parameter can be a value of @ref DMA_memory_data_size */
uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx.
This parameter can be a value of @ref DMA_circular_normal_mode.
@note: The circular buffer mode cannot be used if the memory-to-memory
data transfer is configured on the selected Channel */
uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx.
This parameter can be a value of @ref DMA_priority_level */
uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
This parameter can be a value of @ref DMA_memory_to_memory */
} DMA_InitTypeDef;
/* DMA_data_transfer_direction */
#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
/* DMA_peripheral_incremented_mode */
#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
/* DMA_memory_incremented_mode */
#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
/* DMA_peripheral_data_size */
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
/* DMA_memory_data_size */
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
/* DMA_circular_normal_mode */
#define DMA_Mode_Circular ((uint32_t)0x00000020)
#define DMA_Mode_Normal ((uint32_t)0x00000000)
/* DMA_priority_level */
#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
#define DMA_Priority_High ((uint32_t)0x00002000)
#define DMA_Priority_Medium ((uint32_t)0x00001000)
#define DMA_Priority_Low ((uint32_t)0x00000000)
/* DMA_memory_to_memory */
#define DMA_M2M_Enable ((uint32_t)0x00004000)
#define DMA_M2M_Disable ((uint32_t)0x00000000)
/* DMA_interrupts_definition */
#define DMA_IT_TC ((uint32_t)0x00000002)
#define DMA_IT_HT ((uint32_t)0x00000004)
#define DMA_IT_TE ((uint32_t)0x00000008)
#define DMA1_IT_GL1 ((uint32_t)0x00000001)
#define DMA1_IT_TC1 ((uint32_t)0x00000002)
#define DMA1_IT_HT1 ((uint32_t)0x00000004)
#define DMA1_IT_TE1 ((uint32_t)0x00000008)
#define DMA1_IT_GL2 ((uint32_t)0x00000010)
#define DMA1_IT_TC2 ((uint32_t)0x00000020)
#define DMA1_IT_HT2 ((uint32_t)0x00000040)
#define DMA1_IT_TE2 ((uint32_t)0x00000080)
#define DMA1_IT_GL3 ((uint32_t)0x00000100)
#define DMA1_IT_TC3 ((uint32_t)0x00000200)
#define DMA1_IT_HT3 ((uint32_t)0x00000400)
#define DMA1_IT_TE3 ((uint32_t)0x00000800)
#define DMA1_IT_GL4 ((uint32_t)0x00001000)
#define DMA1_IT_TC4 ((uint32_t)0x00002000)
#define DMA1_IT_HT4 ((uint32_t)0x00004000)
#define DMA1_IT_TE4 ((uint32_t)0x00008000)
#define DMA1_IT_GL5 ((uint32_t)0x00010000)
#define DMA1_IT_TC5 ((uint32_t)0x00020000)
#define DMA1_IT_HT5 ((uint32_t)0x00040000)
#define DMA1_IT_TE5 ((uint32_t)0x00080000)
#define DMA1_IT_GL6 ((uint32_t)0x00100000)
#define DMA1_IT_TC6 ((uint32_t)0x00200000)
#define DMA1_IT_HT6 ((uint32_t)0x00400000)
#define DMA1_IT_TE6 ((uint32_t)0x00800000)
#define DMA1_IT_GL7 ((uint32_t)0x01000000)
#define DMA1_IT_TC7 ((uint32_t)0x02000000)
#define DMA1_IT_HT7 ((uint32_t)0x04000000)
#define DMA1_IT_TE7 ((uint32_t)0x08000000)
#define DMA1_IT_GL8 ((uint32_t)0x10000000)
#define DMA1_IT_TC8 ((uint32_t)0x20000000)
#define DMA1_IT_HT8 ((uint32_t)0x40000000)
#define DMA1_IT_TE8 ((uint32_t)0x80000000)
/* DMA_flags_definition */
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
#define DMA1_FLAG_GL8 ((uint32_t)0x10000000)
#define DMA1_FLAG_TC8 ((uint32_t)0x20000000)
#define DMA1_FLAG_HT8 ((uint32_t)0x40000000)
#define DMA1_FLAG_TE8 ((uint32_t)0x80000000)
void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx);
void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct);
void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct);
void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState);
void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber);
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx);
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
void DMA_ClearFlag(uint32_t DMAy_FLAG);
ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
void DMA_ClearITPendingBit(uint32_t DMAy_IT);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_exti.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* EXTI firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_EXTI_H
#define __CH32V20x_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* EXTI mode enumeration */
typedef enum
{
EXTI_Mode_Interrupt = 0x00,
EXTI_Mode_Event = 0x04
} EXTIMode_TypeDef;
/* EXTI Trigger enumeration */
typedef enum
{
EXTI_Trigger_Rising = 0x08,
EXTI_Trigger_Falling = 0x0C,
EXTI_Trigger_Rising_Falling = 0x10
} EXTITrigger_TypeDef;
/* EXTI Init Structure definition */
typedef struct
{
uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled.
This parameter can be any combination of @ref EXTI_Lines */
EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines.
This parameter can be a value of @ref EXTIMode_TypeDef */
EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines.
This parameter can be a value of @ref EXTIMode_TypeDef */
FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines.
This parameter can be set either to ENABLE or DISABLE */
} EXTI_InitTypeDef;
/* EXTI_Lines */
#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */
#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */
#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */
#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */
#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */
#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */
#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */
#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */
#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */
#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */
#define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */
#define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */
#define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */
#define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */
#define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */
#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */
#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */
#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */
#define EXTI_Line18 ((uint32_t)0x40000) /* External interrupt line 18 Connected to the USBD Device \
Wakeup from suspend event */
#define EXTI_Line19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the Ethernet Wakeup event */
#define EXTI_Line20 ((uint32_t)0x100000) /* External interrupt line 20 Connected to the USBFS Wakeup event */
#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
#define EXTI_Line21 ((uint32_t)0x200000) /* External interrupt line 21 Connected to the OSCCAL Wakeup event */
#endif
void EXTI_DeInit(void);
void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct);
void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct);
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
void EXTI_ClearFlag(uint32_t EXTI_Line);
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_flash.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the FLASH
* firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_FLASH_H
#define __CH32V20x_FLASH_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* FLASH Status */
typedef enum
{
FLASH_BUSY = 1,
FLASH_ERROR_PG,
FLASH_ERROR_WRP,
FLASH_COMPLETE,
FLASH_TIMEOUT,
FLASH_OP_RANGE_ERROR = 0xFD,
FLASH_ALIGN_ERROR = 0xFE,
FLASH_ADR_RANGE_ERROR = 0xFF,
} FLASH_Status;
/* Write Protect */
#define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors31to127 ((uint32_t)0x80000000) /* Write protection of page 62 to 255 */
#define FLASH_WRProt_AllSectors ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */
/* Option_Bytes_IWatchdog */
#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */
#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */
/* Option_Bytes_nRST_STOP */
#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */
#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */
/* Option_Bytes_nRST_STDBY */
#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */
/* FLASH_Interrupts */
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */
#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */
#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */
#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */
/* FLASH_Flags */
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */
#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */
/* FLASH_Access_CLK */
#define FLASH_Access_SYSTEM_HALF ((uint32_t)0x00000000) /* FLASH Enhance Clock = SYSTEM */
#define FLASH_Access_SYSTEM ((uint32_t)0x02000000) /* Enhance_CLK = SYSTEM/2 */
/*Functions used for all devices*/
void FLASH_Unlock(void);
void FLASH_Lock(void);
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
FLASH_Status FLASH_EraseAllPages(void);
FLASH_Status FLASH_EraseOptionBytes(void);
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors);
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
uint32_t FLASH_GetUserOptionByte(void);
uint32_t FLASH_GetWriteProtectionOptionByte(void);
FlagStatus FLASH_GetReadOutProtectionStatus(void);
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
FLASH_Status FLASH_GetStatus(void);
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
void FLASH_Unlock_Fast(void);
void FLASH_Lock_Fast(void);
void FLASH_ErasePage_Fast(uint32_t Page_Address);
void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address);
void FLASH_EraseBlock_64K_Fast(uint32_t Block_Address);
void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t *pbuf);
void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK);
void FLASH_Enhance_Mode(FunctionalState NewState);
#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
void FLASH_GetMACAddress(uint8_t *Buffer);
#endif
/* New function used for all devices */
void FLASH_UnlockBank1(void);
void FLASH_LockBank1(void);
FLASH_Status FLASH_EraseAllBank1Pages(void);
FLASH_Status FLASH_GetBank1Status(void);
FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);
FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length);
FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_gpio.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* GPIO firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_GPIO_H
#define __CH32V20x_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* Output Maximum frequency selection */
typedef enum
{
GPIO_Speed_10MHz = 1,
GPIO_Speed_2MHz,
GPIO_Speed_50MHz
} GPIOSpeed_TypeDef;
/* Configuration Mode enumeration */
typedef enum
{
GPIO_Mode_AIN = 0x0,
GPIO_Mode_IN_FLOATING = 0x04,
GPIO_Mode_IPD = 0x28,
GPIO_Mode_IPU = 0x48,
GPIO_Mode_Out_OD = 0x14,
GPIO_Mode_Out_PP = 0x10,
GPIO_Mode_AF_OD = 0x1C,
GPIO_Mode_AF_PP = 0x18
} GPIOMode_TypeDef;
/* GPIO Init structure definition */
typedef struct
{
uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins_define */
GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIOSpeed_TypeDef */
GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIOMode_TypeDef */
} GPIO_InitTypeDef;
/* Bit_SET and Bit_RESET enumeration */
typedef enum
{
Bit_RESET = 0,
Bit_SET
} BitAction;
/* GPIO_pins_define */
#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */
/* GPIO_Remap_define */
/* PCFR1 */
#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */
#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */
#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /* USART1 Alternate Function mapping low bit */
#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /* USART2 Alternate Function mapping */
#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /* USART3 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */
#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */
#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */
#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */
#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */
#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */
#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */
#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */
#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */
#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */
#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */
#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */
#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */
#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /* ADC2 External Trigger Injected Conversion remapping */
#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /* ADC2 External Trigger Regular Conversion remapping */
#define GPIO_Remap_ETH ((uint32_t)0x00200020) /* Ethernet remapping (only for Connectivity line devices) */
#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /* CAN2 remapping (only for Connectivity line devices) */
#define GPIO_Remap_MII_RMII_SEL ((uint32_t)0x00200080) /* MII or RMII selection */
#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */
#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /* SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */
#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected \
to TIM2 Internal Trigger 1 for calibration \
(only for Connectivity line devices) */
#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /* Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
/* PCFR2 */
#define GPIO_Remap_TIM8 ((uint32_t)0x80000004) /* TIM8 Alternate Function mapping */
#define GPIO_PartialRemap_TIM9 ((uint32_t)0x80130008) /* TIM9 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM9 ((uint32_t)0x80130010) /* TIM9 Full Alternate Function mapping */
#define GPIO_PartialRemap_TIM10 ((uint32_t)0x80150020) /* TIM10 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM10 ((uint32_t)0x80150040) /* TIM10 Full Alternate Function mapping */
#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /* FSMC_NADV Alternate Function mapping */
#define GPIO_PartialRemap_USART4 ((uint32_t)0x80300001) /* USART4 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART4 ((uint32_t)0x80300002) /* USART4 Full Alternate Function mapping */
#define GPIO_PartialRemap_USART5 ((uint32_t)0x80320004) /* USART5 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART5 ((uint32_t)0x80320008) /* USART5 Full Alternate Function mapping */
#define GPIO_PartialRemap_USART6 ((uint32_t)0x80340010) /* USART6 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART6 ((uint32_t)0x80340020) /* USART6 Full Alternate Function mapping */
#define GPIO_PartialRemap_USART7 ((uint32_t)0x80360040) /* USART7 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART7 ((uint32_t)0x80360080) /* USART7 Full Alternate Function mapping */
#define GPIO_PartialRemap_USART8 ((uint32_t)0x80380100) /* USART8 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART8 ((uint32_t)0x80380200) /* USART8 Full Alternate Function mapping */
#define GPIO_Remap_USART1_HighBit ((uint32_t)0x80200400) /* USART1 Alternate Function mapping high bit */
/* GPIO_Port_Sources */
#define GPIO_PortSourceGPIOA ((uint8_t)0x00)
#define GPIO_PortSourceGPIOB ((uint8_t)0x01)
#define GPIO_PortSourceGPIOC ((uint8_t)0x02)
#define GPIO_PortSourceGPIOD ((uint8_t)0x03)
#define GPIO_PortSourceGPIOE ((uint8_t)0x04)
#define GPIO_PortSourceGPIOF ((uint8_t)0x05)
#define GPIO_PortSourceGPIOG ((uint8_t)0x06)
/* GPIO_Pin_sources */
#define GPIO_PinSource0 ((uint8_t)0x00)
#define GPIO_PinSource1 ((uint8_t)0x01)
#define GPIO_PinSource2 ((uint8_t)0x02)
#define GPIO_PinSource3 ((uint8_t)0x03)
#define GPIO_PinSource4 ((uint8_t)0x04)
#define GPIO_PinSource5 ((uint8_t)0x05)
#define GPIO_PinSource6 ((uint8_t)0x06)
#define GPIO_PinSource7 ((uint8_t)0x07)
#define GPIO_PinSource8 ((uint8_t)0x08)
#define GPIO_PinSource9 ((uint8_t)0x09)
#define GPIO_PinSource10 ((uint8_t)0x0A)
#define GPIO_PinSource11 ((uint8_t)0x0B)
#define GPIO_PinSource12 ((uint8_t)0x0C)
#define GPIO_PinSource13 ((uint8_t)0x0D)
#define GPIO_PinSource14 ((uint8_t)0x0E)
#define GPIO_PinSource15 ((uint8_t)0x0F)
/* Ethernet_Media_Interface */
#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000)
#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001)
void GPIO_DeInit(GPIO_TypeDef *GPIOx);
void GPIO_AFIODeInit(void);
void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct);
void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct);
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx);
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx);
void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal);
void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
void GPIO_EventOutputCmd(FunctionalState NewState);
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
void GPIO_IPD_Unused(void);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_i2c.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* I2C firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_I2C_H
#define __CH32V20x_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* I2C Init structure definition */
typedef struct
{
uint32_t I2C_ClockSpeed; /* Specifies the clock frequency.
This parameter must be set to a value lower than 400kHz */
uint16_t I2C_Mode; /* Specifies the I2C mode.
This parameter can be a value of @ref I2C_mode */
uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle.
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
uint16_t I2C_OwnAddress1; /* Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */
uint16_t I2C_Ack; /* Enables or disables the acknowledgement.
This parameter can be a value of @ref I2C_acknowledgement */
uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged.
This parameter can be a value of @ref I2C_acknowledged_address */
} I2C_InitTypeDef;
/* I2C_mode */
#define I2C_Mode_I2C ((uint16_t)0x0000)
#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
/* I2C_duty_cycle_in_fast_mode */
#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */
#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */
/* I2C_acknowledgement */
#define I2C_Ack_Enable ((uint16_t)0x0400)
#define I2C_Ack_Disable ((uint16_t)0x0000)
/* I2C_transfer_direction */
#define I2C_Direction_Transmitter ((uint8_t)0x00)
#define I2C_Direction_Receiver ((uint8_t)0x01)
/* I2C_acknowledged_address */
#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
/* I2C_registers */
#define I2C_Register_CTLR1 ((uint8_t)0x00)
#define I2C_Register_CTLR2 ((uint8_t)0x04)
#define I2C_Register_OADDR1 ((uint8_t)0x08)
#define I2C_Register_OADDR2 ((uint8_t)0x0C)
#define I2C_Register_DATAR ((uint8_t)0x10)
#define I2C_Register_STAR1 ((uint8_t)0x14)
#define I2C_Register_STAR2 ((uint8_t)0x18)
#define I2C_Register_CKCFGR ((uint8_t)0x1C)
#define I2C_Register_RTR ((uint8_t)0x20)
/* I2C_SMBus_alert_pin_level */
#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
/* I2C_PEC_position */
#define I2C_PECPosition_Next ((uint16_t)0x0800)
#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
/* I2C_NACK_position */
#define I2C_NACKPosition_Next ((uint16_t)0x0800)
#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
/* I2C_interrupts_definition */
#define I2C_IT_BUF ((uint16_t)0x0400)
#define I2C_IT_EVT ((uint16_t)0x0200)
#define I2C_IT_ERR ((uint16_t)0x0100)
/* I2C_interrupts_definition */
#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
#define I2C_IT_PECERR ((uint32_t)0x01001000)
#define I2C_IT_OVR ((uint32_t)0x01000800)
#define I2C_IT_AF ((uint32_t)0x01000400)
#define I2C_IT_ARLO ((uint32_t)0x01000200)
#define I2C_IT_BERR ((uint32_t)0x01000100)
#define I2C_IT_TXE ((uint32_t)0x06000080)
#define I2C_IT_RXNE ((uint32_t)0x06000040)
#define I2C_IT_STOPF ((uint32_t)0x02000010)
#define I2C_IT_ADD10 ((uint32_t)0x02000008)
#define I2C_IT_BTF ((uint32_t)0x02000004)
#define I2C_IT_ADDR ((uint32_t)0x02000002)
#define I2C_IT_SB ((uint32_t)0x02000001)
/* SR2 register flags */
#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
#define I2C_FLAG_TRA ((uint32_t)0x00040000)
#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
#define I2C_FLAG_MSL ((uint32_t)0x00010000)
/* SR1 register flags */
#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
#define I2C_FLAG_OVR ((uint32_t)0x10000800)
#define I2C_FLAG_AF ((uint32_t)0x10000400)
#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
#define I2C_FLAG_BERR ((uint32_t)0x10000100)
#define I2C_FLAG_TXE ((uint32_t)0x10000080)
#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
#define I2C_FLAG_BTF ((uint32_t)0x10000004)
#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
#define I2C_FLAG_SB ((uint32_t)0x10000001)
/****************I2C Master Events (Events grouped in order of communication)********************/
/********************************************************************************************************************
* @brief Start communicate
*
* After master use I2C_GenerateSTART() function sending the START condition,the master
* has to wait for event 5(the Start condition has been correctly
* released on the I2C bus ).
*
*/
/* EVT5 */
#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
/********************************************************************************************************************
* @brief Address Acknowledge
*
* When start condition correctly released on the bus(check EVT5), the
* master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate
* it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges
* his address. If an acknowledge is sent on the bus, one of the following events will be set:
*
*
*
* 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
* event is set.
*
* 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
* is set
*
* 3) In case of 10-Bit addressing mode, the master (after generating the START
* and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode.
* Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent
* on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part
* of the 10-bit address (LSB) . Then master should wait for event 6.
*
*
*/
/* EVT6 */
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
/*EVT9 */
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
/********************************************************************************************************************
* @brief Communication events
*
* If START condition has generated and slave address
* been acknowledged. then the master has to check one of the following events for
* communication procedures:
*
* 1) Master Receiver mode: The master has to wait on the event EVT7 then use
* I2C_ReceiveData() function to read the data received from the slave .
*
* 2) Master Transmitter mode: The master use I2C_SendData() function to send data
* then to wait on event EVT8 or EVT8_2.
* These two events are similar:
* - EVT8 means that the data has been written in the data register and is
* being shifted out.
* - EVT8_2 means that the data has been physically shifted out and output
* on the bus.
* In most cases, using EVT8 is sufficient for the application.
* Using EVT8_2 will leads to a slower communication speed but will more reliable .
* EVT8_2 is also more suitable than EVT8 for testing on the last data transmission
*
*
* Note:
* In case the user software does not guarantee that this event EVT7 is managed before
* the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED
* and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower.
*
*
*/
/* Master Receive mode */
/* EVT7 */
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
/* Master Transmitter mode*/
/* EVT8 */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
/* EVT8_2 */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
/******************I2C Slave Events (Events grouped in order of communication)******************/
/********************************************************************************************************************
* @brief Start Communicate events
*
* Wait on one of these events at the start of the communication. It means that
* the I2C peripheral detected a start condition of master device generate on the bus.
* If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus.
*
*
*
* a) In normal case (only one address managed by the slave), when the address
* sent by the master matches the own address of the peripheral (configured by
* I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
* (where XXX could be TRANSMITTER or RECEIVER).
*
* b) In case the address sent by the master matches the second address of the
* peripheral (configured by the function I2C_OwnAddress2Config() and enabled
* by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
* (where XXX could be TRANSMITTER or RECEIVER) are set.
*
* c) In case the address sent by the master is General Call (address 0x00) and
* if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
* the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
*
*/
/* EVT1 */
/* a) Case of One Single Address managed by the slave */
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
/* b) Case of Dual address managed by the slave */
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
/* c) Case of General Call enabled for the slave */
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
/********************************************************************************************************************
* @brief Communication events
*
* Wait on one of these events when EVT1 has already been checked :
*
* - Slave Receiver mode:
* - EVT2--The device is expecting to receive a data byte .
* - EVT4--The device is expecting the end of the communication: master
* sends a stop condition and data transmission is stopped.
*
* - Slave Transmitter mode:
* - EVT3--When a byte has been transmitted by the slave and the Master is expecting
* the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
* I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee
* the EVT3 is managed before the current byte end of transfer The second one can optionally
* be used.
* - EVT3_2--When the master sends a NACK to tell slave device that data transmission
* shall end . The slave device has to stop sending
* data bytes and wait a Stop condition from bus.
*
* Note:
* If the user software does not guarantee that the event 2 is
* managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED
* and I2C_FLAG_BTF flag at the same time .
* In this case the communication will be slower.
*
*/
/* Slave Receiver mode*/
/* EVT2 */
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
/* EVT4 */
#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
/* Slave Transmitter mode*/
/* EVT3 */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
/*EVT3_2 */
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
void I2C_DeInit(I2C_TypeDef *I2Cx);
void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct);
void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct);
void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address);
void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState);
void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data);
uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx);
void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction);
uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register);
void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition);
void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert);
void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition);
void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState);
uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx);
void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle);
/*****************************************************************************************
*
* I2C State Monitoring Functions
*
****************************************************************************************
* This I2C driver provides three different ways for I2C state monitoring
* profit the application requirements and constraints:
*
*
* a) First way:
* Using I2C_CheckEvent() function:
* It compares the status registers (STARR1 and STAR2) content to a given event
* (can be the combination of more flags).
* If the current status registers includes the given flags will return SUCCESS.
* and if the current status registers miss flags will returns ERROR.
* - When to use:
* - This function is suitable for most applications as well as for startup
* activity since the events are fully described in the product reference manual
* (CH32FV2x-V3xRM).
* - It is also suitable for users who need to define their own events.
* - Limitations:
* - If an error occurs besides to the monitored error,
* the I2C_CheckEvent() function may return SUCCESS despite the communication
* in corrupted state. it is suggeted to use error interrupts to monitor the error
* events and handle them in IRQ handler.
*
*
* Note:
* The following functions are recommended for error management: :
* - I2C_ITConfig() main function of configure and enable the error interrupts.
* - I2Cx_ER_IRQHandler() will be called when the error interrupt happen.
* Where x is the peripheral instance (I2C1, I2C2 ...)
* - I2Cx_ER_IRQHandler() will call I2C_GetFlagStatus() or I2C_GetITStatus() functions
* to determine which error occurred.
* - I2C_ClearFlag() \ I2C_ClearITPendingBit() \ I2C_SoftwareResetCmd()
* \ I2C_GenerateStop() will be use to clear the error flag and source,
* and return to correct communication status.
*
*
* b) Second way:
* Using the function to get a single word(uint32_t) composed of status register 1 and register 2.
* (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1).
* - When to use:
*
* - This function is suitable for the same applications above but it
* don't have the limitations of I2C_GetFlagStatus() function .
* The returned value could be compared to events already defined in the
* library (CH32V20x_i2c.h) or to custom values defined by user.
* - This function can be used to monitor the status of multiple flags simultaneously.
* - Contrary to the I2C_CheckEvent () function, this function can choose the time to
* accept the event according to the user's needs (when all event flags are set and
* no other flags are set, or only when the required flags are set)
*
* - Limitations:
* - User may need to define his own events.
* - Same remark concerning the error management is applicable for this
* function if user decides to check only regular communication flags (and
* ignores error flags).
*
*
* c) Third way:
* Using the function I2C_GetFlagStatus() get the status of
* one single flag .
* - When to use:
* - This function could be used for specific applications or in debug phase.
* - It is suitable when only one flag checking is needed .
*
* - Limitations:
* - Call this function to access the status register. Some flag bits may be cleared.
* - Function may need to be called twice or more in order to monitor one single event.
*/
/*********************************************************
*
* a) Basic state monitoring(First way)
********************************************************
*/
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
/*********************************************************
*
* b) Advanced state monitoring(Second way:)
********************************************************
*/
uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
/*********************************************************
*
* c) Flag-based state monitoring(Third way)
*********************************************************
*/
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG);
ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT);
void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_iwdg.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* IWDG firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_IWDG_H
#define __CH32V20x_IWDG_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* IWDG_WriteAccess */
#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
/* IWDG_prescaler */
#define IWDG_Prescaler_4 ((uint8_t)0x00)
#define IWDG_Prescaler_8 ((uint8_t)0x01)
#define IWDG_Prescaler_16 ((uint8_t)0x02)
#define IWDG_Prescaler_32 ((uint8_t)0x03)
#define IWDG_Prescaler_64 ((uint8_t)0x04)
#define IWDG_Prescaler_128 ((uint8_t)0x05)
#define IWDG_Prescaler_256 ((uint8_t)0x06)
/* IWDG_Flag */
#define IWDG_FLAG_PVU ((uint16_t)0x0001)
#define IWDG_FLAG_RVU ((uint16_t)0x0002)
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
void IWDG_SetReload(uint16_t Reload);
void IWDG_ReloadCounter(void);
void IWDG_Enable(void);
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_misc.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* miscellaneous firmware library functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_MISC_H
#define __CH32V20x_MISC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* CSR_INTSYSCR_INEST_definition */
#define INTSYSCR_INEST_NoEN 0x00 /* interrupt nesting disable(CSR-0x804 bit1 = 0) */
#define INTSYSCR_INEST_EN 0x01 /* interrupt nesting enable(CSR-0x804 bit1 = 1) */
/* Check the configuration of CSR(0x804) in the startup file(.S)
* interrupt nesting enable(CSR-0x804 bit1 = 1)
* priority - bit[7] - Preemption Priority
* bit[6:5] - Sub priority
* bit[4:0] - Reserve
* interrupt nesting disable(CSR-0x804 bit1 = 0)
* priority - bit[7:5] - Sub priority
* bit[4:0] - Reserve
*/
#ifndef INTSYSCR_INEST
#define INTSYSCR_INEST INTSYSCR_INEST_EN
#endif
/* NVIC Init Structure definition
* interrupt nesting enable(CSR-0x804 bit1 = 1)
* NVIC_IRQChannelPreemptionPriority - range from 0 to 1.
* NVIC_IRQChannelSubPriority - range from 0 to 3.
*
* interrupt nesting disable(CSR-0x804 bit1 = 0)
* NVIC_IRQChannelPreemptionPriority - range is 0.
* NVIC_IRQChannelSubPriority - range from 0 to 7.
*
*/
typedef struct
{
uint8_t NVIC_IRQChannel;
uint8_t NVIC_IRQChannelPreemptionPriority;
uint8_t NVIC_IRQChannelSubPriority;
FunctionalState NVIC_IRQChannelCmd;
} NVIC_InitTypeDef;
/* Preemption_Priority_Group */
#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN)
#define NVIC_PriorityGroup_0 ((uint32_t)0x00) /* interrupt nesting disable(CSR-0x804 bit1 = 0) */
#else
#define NVIC_PriorityGroup_1 ((uint32_t)0x01) /* interrupt nesting enable(CSR-0x804 bit1 = 1) */
#endif
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_opa.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* OPA firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_OPA_H
#define __CH32V20x_OPA_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
#define OPA_PSEL_OFFSET 3
#define OPA_NSEL_OFFSET 2
#define OPA_MODE_OFFSET 1
/* OPA member enumeration */
typedef enum
{
OPA1 = 0,
OPA2,
OPA3,
OPA4
} OPA_Num_TypeDef;
/* OPA PSEL enumeration */
typedef enum
{
CHP0 = 0,
CHP1
} OPA_PSEL_TypeDef;
/* OPA NSEL enumeration */
typedef enum
{
CHN0 = 0,
CHN1
} OPA_NSEL_TypeDef;
/* OPA out channel enumeration */
typedef enum
{
OUT_IO_OUT0 = 0,
OUT_IO_OUT1
} OPA_Mode_TypeDef;
/* OPA Init Structure definition */
typedef struct
{
OPA_Num_TypeDef OPA_NUM; /* Specifies the members of OPA */
OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */
OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */
OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */
} OPA_InitTypeDef;
void OPA_DeInit(void);
void OPA_Init(OPA_InitTypeDef *OPA_InitStruct);
void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct);
void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_pwr.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the PWR
* firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_PWR_H
#define __CH32V20x_PWR_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* PVD_detection_level */
#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000)
#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020)
#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040)
#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060)
#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080)
#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0)
#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0)
#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0)
/* Regulator_state_is_STOP_mode */
#define PWR_Regulator_ON ((uint32_t)0x00000000)
#define PWR_Regulator_LowPower ((uint32_t)0x00000001)
/* STOP_mode_entry */
#define PWR_STOPEntry_WFI ((uint8_t)0x01)
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
/* PWR_Flag */
#define PWR_FLAG_WU ((uint32_t)0x00000001)
#define PWR_FLAG_SB ((uint32_t)0x00000002)
#define PWR_FLAG_PVDO ((uint32_t)0x00000004)
void PWR_DeInit(void);
void PWR_BackupAccessCmd(FunctionalState NewState);
void PWR_PVDCmd(FunctionalState NewState);
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
void PWR_WakeUpPinCmd(FunctionalState NewState);
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
void PWR_EnterSTANDBYMode(void);
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
void PWR_ClearFlag(uint32_t PWR_FLAG);
void PWR_EnterSTANDBYMode_RAM(void);
void PWR_EnterSTANDBYMode_RAM_LV(void);
void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void);
void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void);
void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_rcc.h
* Author : WCH
* Version : V1.0.0
* Date : 2024/02/21
* Description : This file provides all the RCC firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_RCC_H
#define __CH32V20x_RCC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* RCC_Exported_Types */
typedef struct
{
uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */
uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */
uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */
uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */
uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */
} RCC_ClocksTypeDef;
/* HSE_configuration */
#define RCC_HSE_OFF ((uint32_t)0x00000000)
#define RCC_HSE_ON ((uint32_t)0x00010000)
#define RCC_HSE_Bypass ((uint32_t)0x00040000)
/* PLL_entry_clock_source */
#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)
#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)
#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)
/* PLL_multiplication_factor for other CH32V20x */
#define RCC_PLLMul_2 ((uint32_t)0x00000000)
#define RCC_PLLMul_3 ((uint32_t)0x00040000)
#define RCC_PLLMul_4 ((uint32_t)0x00080000)
#define RCC_PLLMul_5 ((uint32_t)0x000C0000)
#define RCC_PLLMul_6 ((uint32_t)0x00100000)
#define RCC_PLLMul_7 ((uint32_t)0x00140000)
#define RCC_PLLMul_8 ((uint32_t)0x00180000)
#define RCC_PLLMul_9 ((uint32_t)0x001C0000)
#define RCC_PLLMul_10 ((uint32_t)0x00200000)
#define RCC_PLLMul_11 ((uint32_t)0x00240000)
#define RCC_PLLMul_12 ((uint32_t)0x00280000)
#define RCC_PLLMul_13 ((uint32_t)0x002C0000)
#define RCC_PLLMul_14 ((uint32_t)0x00300000)
#define RCC_PLLMul_15 ((uint32_t)0x00340000)
#define RCC_PLLMul_16 ((uint32_t)0x00380000)
#define RCC_PLLMul_18 ((uint32_t)0x003C0000)
/* System_clock_source */
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
/* AHB_clock_source */
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
/* APB1_APB2_clock_source */
#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
#define RCC_HCLK_Div2 ((uint32_t)0x00000400)
#define RCC_HCLK_Div4 ((uint32_t)0x00000500)
#define RCC_HCLK_Div8 ((uint32_t)0x00000600)
#define RCC_HCLK_Div16 ((uint32_t)0x00000700)
/* RCC_Interrupt_source */
#define RCC_IT_LSIRDY ((uint8_t)0x01)
#define RCC_IT_LSERDY ((uint8_t)0x02)
#define RCC_IT_HSIRDY ((uint8_t)0x04)
#define RCC_IT_HSERDY ((uint8_t)0x08)
#define RCC_IT_PLLRDY ((uint8_t)0x10)
#define RCC_IT_CSS ((uint8_t)0x80)
/* USB_Device_clock_source */
#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x00)
#define RCC_USBCLKSource_PLLCLK_Div2 ((uint8_t)0x01)
#define RCC_USBCLKSource_PLLCLK_Div3 ((uint8_t)0x02)
#ifdef CH32V20x_D8W
#define RCC_USBCLKSource_PLLCLK_Div5 ((uint8_t)0x03)
#endif
/* ADC_clock_source */
#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
/* LSE_configuration */
#define RCC_LSE_OFF ((uint8_t)0x00)
#define RCC_LSE_ON ((uint8_t)0x01)
#define RCC_LSE_Bypass ((uint8_t)0x04)
/* RTC_clock_source */
#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
#define RCC_RTCCLKSource_HSE_Div512 ((uint32_t)0x00000300)
#else
#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)
#endif
/* AHB_peripheral */
#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
#define RCC_AHBPeriph_RNG ((uint32_t)0x00000200)
#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
#define RCC_AHBPeriph_USBHS ((uint32_t)0x00000800)
#define RCC_AHBPeriph_USBFS ((uint32_t)0x00001000)
#define RCC_AHBPeriph_OTG_FS RCC_AHBPeriph_USBFS
#ifdef CH32V20x_D8W
#define RCC_AHBPeriph_BLE_CRC ((uint32_t)0x00030040)
#endif
/* APB2_peripheral */
#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)
/* APB1_peripheral */
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
#define RCC_APB1Periph_UART6 ((uint32_t)0x00000040)
#define RCC_APB1Periph_UART7 ((uint32_t)0x00000080)
#define RCC_APB1Periph_UART8 ((uint32_t)0x00000100)
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
/* Clock_source_to_output_on_MCO_pin */
#define RCC_MCO_NoClock ((uint8_t)0x00)
#define RCC_MCO_SYSCLK ((uint8_t)0x04)
#define RCC_MCO_HSI ((uint8_t)0x05)
#define RCC_MCO_HSE ((uint8_t)0x06)
#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)
/* RCC_Flag */
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
#define RCC_FLAG_PORRST ((uint8_t)0x7B)
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
/* SysTick_clock_source */
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
/* USBFS_clock_source */
#define RCC_USBPLL_Div1 ((uint32_t)0x00)
#define RCC_USBPLL_Div2 ((uint32_t)0x01)
#define RCC_USBPLL_Div3 ((uint32_t)0x02)
#define RCC_USBPLL_Div4 ((uint32_t)0x03)
#define RCC_USBPLL_Div5 ((uint32_t)0x04)
#define RCC_USBPLL_Div6 ((uint32_t)0x05)
#define RCC_USBPLL_Div7 ((uint32_t)0x06)
#define RCC_USBPLL_Div8 ((uint32_t)0x07)
/* ETH_clock_source */
#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
#define RCC_ETHCLK_Div1 ((uint32_t)0x00)
#define RCC_ETHCLK_Div2 ((uint32_t)0x01)
#endif
void RCC_DeInit(void);
void RCC_HSEConfig(uint32_t RCC_HSE);
ErrorStatus RCC_WaitForHSEStartUp(void);
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
void RCC_HSICmd(FunctionalState NewState);
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
void RCC_PLLCmd(FunctionalState NewState);
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
uint8_t RCC_GetSYSCLKSource(void);
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
void RCC_PCLK1Config(uint32_t RCC_HCLK);
void RCC_PCLK2Config(uint32_t RCC_HCLK);
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
void RCC_LSEConfig(uint8_t RCC_LSE);
void RCC_LSICmd(FunctionalState NewState);
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
void RCC_RTCCLKCmd(FunctionalState NewState);
void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks);
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_BackupResetCmd(FunctionalState NewState);
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
void RCC_MCOConfig(uint8_t RCC_MCO);
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
void RCC_ClearFlag(void);
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
void RCC_ClearITPendingBit(uint8_t RCC_IT);
void RCC_ADCCLKADJcmd(FunctionalState NewState);
#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
void RCC_ETHDIVConfig(uint32_t RCC_ETHPRE_Div);
#endif
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_rtc.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the RTC
* firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_RTC_H
#define __CH32V20x_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
typedef enum
{
Level_32 = 2,
Level_64,
Level_128,
} Cali_LevelTypeDef;
/* RTC_interrupts_define */
#define RTC_IT_OW ((uint16_t)0x0004) /* Overflow interrupt */
#define RTC_IT_ALR ((uint16_t)0x0002) /* Alarm interrupt */
#define RTC_IT_SEC ((uint16_t)0x0001) /* Second interrupt */
/* RTC_interrupts_flags */
#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /* RTC Operation OFF flag */
#define RTC_FLAG_RSF ((uint16_t)0x0008) /* Registers Synchronized flag */
#define RTC_FLAG_OW ((uint16_t)0x0004) /* Overflow flag */
#define RTC_FLAG_ALR ((uint16_t)0x0002) /* Alarm flag */
#define RTC_FLAG_SEC ((uint16_t)0x0001) /* Second flag */
#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
#define RB_OSC32K_HTUNE (0x1FE0)
#define RB_OSC32K_LTUNE (0x1F)
#define RB_OSC_CAL_HALT (0x80)
#define RB_OSC_CAL_EN (0x02)
#define RB_OSC_CAL_INT_EN (0x01)
#define RB_OSC_CAL_OV_CNT (0xFF)
#define RB_OSC_CAL_IF_END (1 << 15)
#define RB_OSC_CAL_CNT_OV (1 << 14)
#define RB_OSC_CAL_CNT (0x3FFF)
#define RB_CAL_LP_EN (1 << 6)
#define RB_CAL_WKUP_EN (1 << 5)
#define RB_OSC_HALT_MD (1 << 4)
#define RB_OSC_CNT_VLU (0x0F)
#ifdef CLK_OSC32K
#if ( CLK_OSC32K == 1 )
#define CAB_LSIFQ 32000
#else
#define CAB_LSIFQ 32768
#endif
#else
#define CAB_LSIFQ 32000
#endif
#endif
void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
void RTC_EnterConfigMode(void);
void RTC_ExitConfigMode(void);
uint32_t RTC_GetCounter(void);
void RTC_SetCounter(uint32_t CounterValue);
void RTC_SetPrescaler(uint32_t PrescalerValue);
void RTC_SetAlarm(uint32_t AlarmValue);
uint32_t RTC_GetDivider(void);
void RTC_WaitForLastTask(void);
void RTC_WaitForSynchro(void);
FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
void RTC_ClearFlag(uint16_t RTC_FLAG);
ITStatus RTC_GetITStatus(uint16_t RTC_IT);
void RTC_ClearITPendingBit(uint16_t RTC_IT);
#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
void Calibration_LSI(Cali_LevelTypeDef cali_Lv);
#endif
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_spi.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* SPI firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_SPI_H
#define __CH32V20x_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* SPI Init structure definition */
typedef struct
{
uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode.
This parameter can be a value of @ref SPI_data_direction */
uint16_t SPI_Mode; /* Specifies the SPI operating mode.
This parameter can be a value of @ref SPI_mode */
uint16_t SPI_DataSize; /* Specifies the SPI data size.
This parameter can be a value of @ref SPI_data_size */
uint16_t SPI_CPOL; /* Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_Clock_Polarity */
uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture.
This parameter can be a value of @ref SPI_Clock_Phase */
uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by
hardware (NSS pin) or by software using the SSI bit.
This parameter can be a value of @ref SPI_Slave_Select_management */
uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be
used to configure the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_BaudRate_Prescaler.
@note The communication clock is derived from the master
clock. The slave clock does not need to be set. */
uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */
} SPI_InitTypeDef;
/* I2S Init structure definition */
typedef struct
{
uint16_t I2S_Mode; /* Specifies the I2S operating mode.
This parameter can be a value of @ref I2S_Mode */
uint16_t I2S_Standard; /* Specifies the standard used for the I2S communication.
This parameter can be a value of @ref I2S_Standard */
uint16_t I2S_DataFormat; /* Specifies the data format for the I2S communication.
This parameter can be a value of @ref I2S_Data_Format */
uint16_t I2S_MCLKOutput; /* Specifies whether the I2S MCLK output is enabled or not.
This parameter can be a value of @ref I2S_MCLK_Output */
uint32_t I2S_AudioFreq; /* Specifies the frequency selected for the I2S communication.
This parameter can be a value of @ref I2S_Audio_Frequency */
uint16_t I2S_CPOL; /* Specifies the idle state of the I2S clock.
This parameter can be a value of @ref I2S_Clock_Polarity */
} I2S_InitTypeDef;
/* SPI_data_direction */
#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
/* SPI_mode */
#define SPI_Mode_Master ((uint16_t)0x0104)
#define SPI_Mode_Slave ((uint16_t)0x0000)
/* SPI_data_size */
#define SPI_DataSize_16b ((uint16_t)0x0800)
#define SPI_DataSize_8b ((uint16_t)0x0000)
/* SPI_Clock_Polarity */
#define SPI_CPOL_Low ((uint16_t)0x0000)
#define SPI_CPOL_High ((uint16_t)0x0002)
/* SPI_Clock_Phase */
#define SPI_CPHA_1Edge ((uint16_t)0x0000)
#define SPI_CPHA_2Edge ((uint16_t)0x0001)
/* SPI_Slave_Select_management */
#define SPI_NSS_Soft ((uint16_t)0x0200)
#define SPI_NSS_Hard ((uint16_t)0x0000)
/* SPI_BaudRate_Prescaler */
#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
/* SPI_MSB_LSB_transmission */
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
#define SPI_FirstBit_LSB ((uint16_t)0x0080)
/* I2S_Mode */
#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
#define I2S_Mode_MasterTx ((uint16_t)0x0200)
#define I2S_Mode_MasterRx ((uint16_t)0x0300)
/* I2S_Standard */
#define I2S_Standard_Phillips ((uint16_t)0x0000)
#define I2S_Standard_MSB ((uint16_t)0x0010)
#define I2S_Standard_LSB ((uint16_t)0x0020)
#define I2S_Standard_PCMShort ((uint16_t)0x0030)
#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
/* I2S_Data_Format */
#define I2S_DataFormat_16b ((uint16_t)0x0000)
#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
#define I2S_DataFormat_24b ((uint16_t)0x0003)
#define I2S_DataFormat_32b ((uint16_t)0x0005)
/* I2S_MCLK_Output */
#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
/* I2S_Audio_Frequency */
#define I2S_AudioFreq_192k ((uint32_t)192000)
#define I2S_AudioFreq_96k ((uint32_t)96000)
#define I2S_AudioFreq_48k ((uint32_t)48000)
#define I2S_AudioFreq_44k ((uint32_t)44100)
#define I2S_AudioFreq_32k ((uint32_t)32000)
#define I2S_AudioFreq_22k ((uint32_t)22050)
#define I2S_AudioFreq_16k ((uint32_t)16000)
#define I2S_AudioFreq_11k ((uint32_t)11025)
#define I2S_AudioFreq_8k ((uint32_t)8000)
#define I2S_AudioFreq_Default ((uint32_t)2)
/* I2S_Clock_Polarity */
#define I2S_CPOL_Low ((uint16_t)0x0000)
#define I2S_CPOL_High ((uint16_t)0x0008)
/* SPI_I2S_DMA_transfer_requests */
#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
/* SPI_NSS_internal_software_management */
#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
/* SPI_CRC_Transmit_Receive */
#define SPI_CRC_Tx ((uint8_t)0x00)
#define SPI_CRC_Rx ((uint8_t)0x01)
/* SPI_direction_transmit_receive */
#define SPI_Direction_Rx ((uint16_t)0xBFFF)
#define SPI_Direction_Tx ((uint16_t)0x4000)
/* SPI_I2S_interrupts_definition */
#define SPI_I2S_IT_TXE ((uint8_t)0x71)
#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
#define SPI_I2S_IT_ERR ((uint8_t)0x50)
#define SPI_I2S_IT_OVR ((uint8_t)0x56)
#define SPI_IT_MODF ((uint8_t)0x55)
#define SPI_IT_CRCERR ((uint8_t)0x54)
#define I2S_IT_UDR ((uint8_t)0x53)
/* SPI_I2S_flags_definition */
#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
#define I2S_FLAG_UDR ((uint16_t)0x0008)
#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
#define SPI_FLAG_MODF ((uint16_t)0x0020)
#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
void SPI_I2S_DeInit(SPI_TypeDef *SPIx);
void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct);
void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct);
void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct);
void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct);
void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState);
void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState);
void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data);
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx);
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft);
void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState);
void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize);
void SPI_TransmitCRC(SPI_TypeDef *SPIx);
void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState);
uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC);
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx);
void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction);
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG);
void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG);
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT);
void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_tim.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* TIM firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_TIM_H
#define __CH32V20x_TIM_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* TIM Time Base Init structure definition */
typedef struct
{
uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock.
This parameter can be a number between 0x0000 and 0xFFFF */
uint16_t TIM_CounterMode; /* Specifies the counter mode.
This parameter can be a value of @ref TIM_Counter_Mode */
uint16_t TIM_Period; /* Specifies the period value to be loaded into the active
Auto-Reload Register at the next update event.
This parameter must be a number between 0x0000 and 0xFFFF. */
uint16_t TIM_ClockDivision; /* Specifies the clock division.
This parameter can be a value of @ref TIM_Clock_Division_CKD */
uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter
reaches zero, an update event is generated and counting restarts
from the RCR value (N).
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
This parameter must be a number between 0x00 and 0xFF.
@note This parameter is valid only for TIM1 and TIM8. */
} TIM_TimeBaseInitTypeDef;
/* TIM Output Compare Init structure definition */
typedef struct
{
uint16_t TIM_OCMode; /* Specifies the TIM mode.
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state.
This parameter can be a value of @ref TIM_Output_Compare_state */
uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state.
This parameter can be a value of @ref TIM_Output_Compare_N_state
@note This parameter is valid only for TIM1 and TIM8. */
uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register.
This parameter can be a number between 0x0000 and 0xFFFF */
uint16_t TIM_OCPolarity; /* Specifies the output polarity.
This parameter can be a value of @ref TIM_Output_Compare_Polarity */
uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity.
This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
@note This parameter is valid only for TIM1 and TIM8. */
uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_Idle_State
@note This parameter is valid only for TIM1 and TIM8. */
uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
@note This parameter is valid only for TIM1 and TIM8. */
} TIM_OCInitTypeDef;
/* TIM Input Capture Init structure definition */
typedef struct
{
uint16_t TIM_Channel; /* Specifies the TIM channel.
This parameter can be a value of @ref TIM_Channel */
uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
uint16_t TIM_ICSelection; /* Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
uint16_t TIM_ICFilter; /* Specifies the input capture filter.
This parameter can be a number between 0x0 and 0xF */
} TIM_ICInitTypeDef;
/* BDTR structure definition */
typedef struct
{
uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode.
This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state.
This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters.
This parameter can be a value of @ref Lock_level */
uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the
switching-on of the outputs.
This parameter can be a number between 0x00 and 0xFF */
uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not.
This parameter can be a value of @ref Break_Input_enable_disable */
uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity.
This parameter can be a value of @ref Break_Polarity */
uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not.
This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
} TIM_BDTRInitTypeDef;
/* TIM_Output_Compare_and_PWM_modes */
#define TIM_OCMode_Timing ((uint16_t)0x0000)
#define TIM_OCMode_Active ((uint16_t)0x0010)
#define TIM_OCMode_Inactive ((uint16_t)0x0020)
#define TIM_OCMode_Toggle ((uint16_t)0x0030)
#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
/* TIM_One_Pulse_Mode */
#define TIM_OPMode_Single ((uint16_t)0x0008)
#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
/* TIM_Channel */
#define TIM_Channel_1 ((uint16_t)0x0000)
#define TIM_Channel_2 ((uint16_t)0x0004)
#define TIM_Channel_3 ((uint16_t)0x0008)
#define TIM_Channel_4 ((uint16_t)0x000C)
/* TIM_Clock_Division_CKD */
#define TIM_CKD_DIV1 ((uint16_t)0x0000)
#define TIM_CKD_DIV2 ((uint16_t)0x0100)
#define TIM_CKD_DIV4 ((uint16_t)0x0200)
/* TIM_Counter_Mode */
#define TIM_CounterMode_Up ((uint16_t)0x0000)
#define TIM_CounterMode_Down ((uint16_t)0x0010)
#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
/* TIM_Output_Compare_Polarity */
#define TIM_OCPolarity_High ((uint16_t)0x0000)
#define TIM_OCPolarity_Low ((uint16_t)0x0002)
/* TIM_Output_Compare_N_Polarity */
#define TIM_OCNPolarity_High ((uint16_t)0x0000)
#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
/* TIM_Output_Compare_state */
#define TIM_OutputState_Disable ((uint16_t)0x0000)
#define TIM_OutputState_Enable ((uint16_t)0x0001)
/* TIM_Output_Compare_N_state */
#define TIM_OutputNState_Disable ((uint16_t)0x0000)
#define TIM_OutputNState_Enable ((uint16_t)0x0004)
/* TIM_Capture_Compare_state */
#define TIM_CCx_Enable ((uint16_t)0x0001)
#define TIM_CCx_Disable ((uint16_t)0x0000)
/* TIM_Capture_Compare_N_state */
#define TIM_CCxN_Enable ((uint16_t)0x0004)
#define TIM_CCxN_Disable ((uint16_t)0x0000)
/* Break_Input_enable_disable */
#define TIM_Break_Enable ((uint16_t)0x1000)
#define TIM_Break_Disable ((uint16_t)0x0000)
/* Break_Polarity */
#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
#define TIM_BreakPolarity_High ((uint16_t)0x2000)
/* TIM_AOE_Bit_Set_Reset */
#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
/* Lock_level */
#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
/* OSSI_Off_State_Selection_for_Idle_mode_state */
#define TIM_OSSIState_Enable ((uint16_t)0x0400)
#define TIM_OSSIState_Disable ((uint16_t)0x0000)
/* OSSR_Off_State_Selection_for_Run_mode_state */
#define TIM_OSSRState_Enable ((uint16_t)0x0800)
#define TIM_OSSRState_Disable ((uint16_t)0x0000)
/* TIM_Output_Compare_Idle_State */
#define TIM_OCIdleState_Set ((uint16_t)0x0100)
#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
/* TIM_Output_Compare_N_Idle_State */
#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
/* TIM_Input_Capture_Polarity */
#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
/* TIM_Input_Capture_Selection */
#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \
connected to IC1, IC2, IC3 or IC4, respectively */
#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \
connected to IC2, IC1, IC4 or IC3, respectively. */
#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
/* TIM_Input_Capture_Prescaler */
#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */
#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */
#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */
#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */
/* TIM_interrupt_sources */
#define TIM_IT_Update ((uint16_t)0x0001)
#define TIM_IT_CC1 ((uint16_t)0x0002)
#define TIM_IT_CC2 ((uint16_t)0x0004)
#define TIM_IT_CC3 ((uint16_t)0x0008)
#define TIM_IT_CC4 ((uint16_t)0x0010)
#define TIM_IT_COM ((uint16_t)0x0020)
#define TIM_IT_Trigger ((uint16_t)0x0040)
#define TIM_IT_Break ((uint16_t)0x0080)
/* TIM_DMA_Base_address */
#define TIM_DMABase_CR1 ((uint16_t)0x0000)
#define TIM_DMABase_CR2 ((uint16_t)0x0001)
#define TIM_DMABase_SMCR ((uint16_t)0x0002)
#define TIM_DMABase_DIER ((uint16_t)0x0003)
#define TIM_DMABase_SR ((uint16_t)0x0004)
#define TIM_DMABase_EGR ((uint16_t)0x0005)
#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
#define TIM_DMABase_CCER ((uint16_t)0x0008)
#define TIM_DMABase_CNT ((uint16_t)0x0009)
#define TIM_DMABase_PSC ((uint16_t)0x000A)
#define TIM_DMABase_ARR ((uint16_t)0x000B)
#define TIM_DMABase_RCR ((uint16_t)0x000C)
#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
#define TIM_DMABase_BDTR ((uint16_t)0x0011)
#define TIM_DMABase_DCR ((uint16_t)0x0012)
/* TIM_DMA_Burst_Length */
#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
/* TIM_DMA_sources */
#define TIM_DMA_Update ((uint16_t)0x0100)
#define TIM_DMA_CC1 ((uint16_t)0x0200)
#define TIM_DMA_CC2 ((uint16_t)0x0400)
#define TIM_DMA_CC3 ((uint16_t)0x0800)
#define TIM_DMA_CC4 ((uint16_t)0x1000)
#define TIM_DMA_COM ((uint16_t)0x2000)
#define TIM_DMA_Trigger ((uint16_t)0x4000)
/* TIM_External_Trigger_Prescaler */
#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
/* TIM_Internal_Trigger_Selection */
#define TIM_TS_ITR0 ((uint16_t)0x0000)
#define TIM_TS_ITR1 ((uint16_t)0x0010)
#define TIM_TS_ITR2 ((uint16_t)0x0020)
#define TIM_TS_ITR3 ((uint16_t)0x0030)
#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
#define TIM_TS_ETRF ((uint16_t)0x0070)
/* TIM_TIx_External_Clock_Source */
#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
/* TIM_External_Trigger_Polarity */
#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
/* TIM_Prescaler_Reload_Mode */
#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
/* TIM_Forced_Action */
#define TIM_ForcedAction_Active ((uint16_t)0x0050)
#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
/* TIM_Encoder_Mode */
#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
/* TIM_Event_Source */
#define TIM_EventSource_Update ((uint16_t)0x0001)
#define TIM_EventSource_CC1 ((uint16_t)0x0002)
#define TIM_EventSource_CC2 ((uint16_t)0x0004)
#define TIM_EventSource_CC3 ((uint16_t)0x0008)
#define TIM_EventSource_CC4 ((uint16_t)0x0010)
#define TIM_EventSource_COM ((uint16_t)0x0020)
#define TIM_EventSource_Trigger ((uint16_t)0x0040)
#define TIM_EventSource_Break ((uint16_t)0x0080)
/* TIM_Update_Source */
#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \
or the setting of UG bit, or an update generation \
through the slave mode controller. */
#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */
/* TIM_Output_Compare_Preload_State */
#define TIM_OCPreload_Enable ((uint16_t)0x0008)
#define TIM_OCPreload_Disable ((uint16_t)0x0000)
/* TIM_Output_Compare_Fast_State */
#define TIM_OCFast_Enable ((uint16_t)0x0004)
#define TIM_OCFast_Disable ((uint16_t)0x0000)
/* TIM_Output_Compare_Clear_State */
#define TIM_OCClear_Enable ((uint16_t)0x0080)
#define TIM_OCClear_Disable ((uint16_t)0x0000)
/* TIM_Trigger_Output_Source */
#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
#define TIM_TRGOSource_Update ((uint16_t)0x0020)
#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
/* TIM_Slave_Mode */
#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
/* TIM_Master_Slave_Mode */
#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
/* TIM_Flags */
#define TIM_FLAG_Update ((uint16_t)0x0001)
#define TIM_FLAG_CC1 ((uint16_t)0x0002)
#define TIM_FLAG_CC2 ((uint16_t)0x0004)
#define TIM_FLAG_CC3 ((uint16_t)0x0008)
#define TIM_FLAG_CC4 ((uint16_t)0x0010)
#define TIM_FLAG_COM ((uint16_t)0x0020)
#define TIM_FLAG_Trigger ((uint16_t)0x0040)
#define TIM_FLAG_Break ((uint16_t)0x0080)
#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
/* TIM_Legacy */
#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
void TIM_DeInit(TIM_TypeDef *TIMx);
void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct);
void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct);
void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct);
void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct);
void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct);
void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct);
void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState);
void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState);
void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState);
void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource);
void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
void TIM_InternalClockConfig(TIM_TypeDef *TIMx);
void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource);
void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource,
uint16_t TIM_ICPolarity, uint16_t ICFilter);
void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
uint16_t ExtTRGFilter);
void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler,
uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
uint16_t ExtTRGFilter);
void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode);
void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource);
void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode,
uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState);
void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState);
void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState);
void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState);
void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity);
void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity);
void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity);
void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState);
void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource);
void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState);
void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode);
void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource);
void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode);
void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode);
void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter);
void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload);
void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1);
void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2);
void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3);
void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4);
void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD);
uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx);
uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx);
uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx);
uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx);
uint16_t TIM_GetCounter(TIM_TypeDef *TIMx);
uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx);
FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG);
void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG);
ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT);
void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_usart.h
* Author : WCH
* Version : V1.0.0
* Date : 2024/01/06
* Description : This file contains all the functions prototypes for the
* USART firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_USART_H
#define __CH32V20x_USART_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* USART Init Structure definition */
typedef struct
{
uint32_t USART_BaudRate; /* This member configures the USART communication baud rate.
The baud rate is computed using the following formula:
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
- FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USART_Word_Length */
uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted.
This parameter can be a value of @ref USART_Stop_Bits */
uint16_t USART_Parity; /* Specifies the parity mode.
This parameter can be a value of @ref USART_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_Mode */
uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled
or disabled.
This parameter can be a value of @ref USART_Hardware_Flow_Control */
} USART_InitTypeDef;
/* USART Clock Init Structure definition */
typedef struct
{
uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled.
This parameter can be a value of @ref USART_Clock */
uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock.
This parameter can be a value of @ref USART_Clock_Polarity */
uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref USART_Clock_Phase */
uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_Last_Bit */
} USART_ClockInitTypeDef;
/* USART_Word_Length */
#define USART_WordLength_8b ((uint16_t)0x0000)
#define USART_WordLength_9b ((uint16_t)0x1000)
/* USART_Stop_Bits */
#define USART_StopBits_1 ((uint16_t)0x0000)
#define USART_StopBits_0_5 ((uint16_t)0x1000)
#define USART_StopBits_2 ((uint16_t)0x2000)
#define USART_StopBits_1_5 ((uint16_t)0x3000)
/* USART_Parity */
#define USART_Parity_No ((uint16_t)0x0000)
#define USART_Parity_Even ((uint16_t)0x0400)
#define USART_Parity_Odd ((uint16_t)0x0600)
/* USART_Mode */
#define USART_Mode_Rx ((uint16_t)0x0004)
#define USART_Mode_Tx ((uint16_t)0x0008)
/* USART_Hardware_Flow_Control */
#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
/* USART_Clock */
#define USART_Clock_Disable ((uint16_t)0x0000)
#define USART_Clock_Enable ((uint16_t)0x0800)
/* USART_Clock_Polarity */
#define USART_CPOL_Low ((uint16_t)0x0000)
#define USART_CPOL_High ((uint16_t)0x0400)
/* USART_Clock_Phase */
#define USART_CPHA_1Edge ((uint16_t)0x0000)
#define USART_CPHA_2Edge ((uint16_t)0x0200)
/* USART_Last_Bit */
#define USART_LastBit_Disable ((uint16_t)0x0000)
#define USART_LastBit_Enable ((uint16_t)0x0100)
/* USART_Interrupt_definition */
#define USART_IT_PE ((uint16_t)0x0028)
#define USART_IT_TXE ((uint16_t)0x0727)
#define USART_IT_TC ((uint16_t)0x0626)
#define USART_IT_RXNE ((uint16_t)0x0525)
#define USART_IT_ORE_RX ((uint16_t)0x0325)
#define USART_IT_IDLE ((uint16_t)0x0424)
#define USART_IT_LBD ((uint16_t)0x0846)
#define USART_IT_CTS ((uint16_t)0x096A)
#define USART_IT_ERR ((uint16_t)0x0060)
#define USART_IT_ORE_ER ((uint16_t)0x0360)
#define USART_IT_NE ((uint16_t)0x0260)
#define USART_IT_FE ((uint16_t)0x0160)
#define USART_IT_ORE USART_IT_ORE_ER
/* USART_DMA_Requests */
#define USART_DMAReq_Tx ((uint16_t)0x0080)
#define USART_DMAReq_Rx ((uint16_t)0x0040)
/* USART_WakeUp_methods */
#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
/* USART_LIN_Break_Detection_Length */
#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
/* USART_IrDA_Low_Power */
#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
#define USART_IrDAMode_Normal ((uint16_t)0x0000)
/* USART_Flags */
#define USART_FLAG_CTS ((uint16_t)0x0200)
#define USART_FLAG_LBD ((uint16_t)0x0100)
#define USART_FLAG_TXE ((uint16_t)0x0080)
#define USART_FLAG_TC ((uint16_t)0x0040)
#define USART_FLAG_RXNE ((uint16_t)0x0020)
#define USART_FLAG_IDLE ((uint16_t)0x0010)
#define USART_FLAG_ORE ((uint16_t)0x0008)
#define USART_FLAG_NE ((uint16_t)0x0004)
#define USART_FLAG_FE ((uint16_t)0x0002)
#define USART_FLAG_PE ((uint16_t)0x0001)
void USART_DeInit(USART_TypeDef *USARTx);
void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct);
void USART_StructInit(USART_InitTypeDef *USART_InitStruct);
void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct);
void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct);
void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState);
void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address);
void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp);
void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength);
void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_SendData(USART_TypeDef *USARTx, uint16_t Data);
uint16_t USART_ReceiveData(USART_TypeDef *USARTx);
void USART_SendBreak(USART_TypeDef *USARTx);
void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime);
void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler);
void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode);
void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState);
FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG);
void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG);
ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT);
void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_usb.h
* Author : WCH
* Version : V1.0.0
* Date : 2024/01/30
* Description : This file contains all the functions prototypes for the USB
* firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20X_USB_H
#define __CH32V20X_USB_H
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************/
/* Header File */
#include "stdint.h"
/*******************************************************************************/
/* USB Communication Related Macro Definition */
#ifndef DEFAULT_ENDP0_SIZE
#define DEFAULT_ENDP0_SIZE 8 // default maximum packet size for endpoint 0
#endif
#ifndef MAX_PACKET_SIZE
#define MAX_PACKET_SIZE 64 // maximum packet size
#endif
/* USB PID */
#ifndef USB_PID_SETUP
#define USB_PID_NULL 0x00
#define USB_PID_SOF 0x05
#define USB_PID_SETUP 0x0D
#define USB_PID_IN 0x09
#define USB_PID_OUT 0x01
#define USB_PID_NYET 0x06
#define USB_PID_ACK 0x02
#define USB_PID_NAK 0x0A
#define USB_PID_STALL 0x0E
#define USB_PID_DATA0 0x03
#define USB_PID_DATA1 0x0B
#define USB_PID_PRE 0x0C
#endif
/* USB standard device request code */
#ifndef USB_GET_DESCRIPTOR
#define USB_GET_STATUS 0x00
#define USB_CLEAR_FEATURE 0x01
#define USB_SET_FEATURE 0x03
#define USB_SET_ADDRESS 0x05
#define USB_GET_DESCRIPTOR 0x06
#define USB_SET_DESCRIPTOR 0x07
#define USB_GET_CONFIGURATION 0x08
#define USB_SET_CONFIGURATION 0x09
#define USB_GET_INTERFACE 0x0A
#define USB_SET_INTERFACE 0x0B
#define USB_SYNCH_FRAME 0x0C
#endif
#define DEF_STRING_DESC_LANG 0x00
#define DEF_STRING_DESC_MANU 0x01
#define DEF_STRING_DESC_PROD 0x02
#define DEF_STRING_DESC_SERN 0x03
/* USB hub class request code */
#ifndef HUB_GET_DESCRIPTOR
#define HUB_GET_STATUS 0x00
#define HUB_CLEAR_FEATURE 0x01
#define HUB_GET_STATE 0x02
#define HUB_SET_FEATURE 0x03
#define HUB_GET_DESCRIPTOR 0x06
#define HUB_SET_DESCRIPTOR 0x07
#endif
/* USB HID class request code */
#ifndef HID_GET_REPORT
#define HID_GET_REPORT 0x01
#define HID_GET_IDLE 0x02
#define HID_GET_PROTOCOL 0x03
#define HID_SET_REPORT 0x09
#define HID_SET_IDLE 0x0A
#define HID_SET_PROTOCOL 0x0B
#endif
/* Bit Define for USB Request Type */
#ifndef USB_REQ_TYP_MASK
#define USB_REQ_TYP_IN 0x80
#define USB_REQ_TYP_OUT 0x00
#define USB_REQ_TYP_READ 0x80
#define USB_REQ_TYP_WRITE 0x00
#define USB_REQ_TYP_MASK 0x60
#define USB_REQ_TYP_STANDARD 0x00
#define USB_REQ_TYP_CLASS 0x20
#define USB_REQ_TYP_VENDOR 0x40
#define USB_REQ_TYP_RESERVED 0x60
#define USB_REQ_RECIP_MASK 0x1F
#define USB_REQ_RECIP_DEVICE 0x00
#define USB_REQ_RECIP_INTERF 0x01
#define USB_REQ_RECIP_ENDP 0x02
#define USB_REQ_RECIP_OTHER 0x03
#define USB_REQ_FEAT_REMOTE_WAKEUP 0x01
#define USB_REQ_FEAT_ENDP_HALT 0x00
#endif
/* USB Descriptor Type */
#ifndef USB_DESCR_TYP_DEVICE
#define USB_DESCR_TYP_DEVICE 0x01
#define USB_DESCR_TYP_CONFIG 0x02
#define USB_DESCR_TYP_STRING 0x03
#define USB_DESCR_TYP_INTERF 0x04
#define USB_DESCR_TYP_ENDP 0x05
#define USB_DESCR_TYP_QUALIF 0x06
#define USB_DESCR_TYP_SPEED 0x07
#define USB_DESCR_TYP_OTG 0x09
#define USB_DESCR_TYP_BOS 0X0F
#define USB_DESCR_TYP_HID 0x21
#define USB_DESCR_TYP_REPORT 0x22
#define USB_DESCR_TYP_PHYSIC 0x23
#define USB_DESCR_TYP_CS_INTF 0x24
#define USB_DESCR_TYP_CS_ENDP 0x25
#define USB_DESCR_TYP_HUB 0x29
#endif
/* USB Device Class */
#ifndef USB_DEV_CLASS_HUB
#define USB_DEV_CLASS_RESERVED 0x00
#define USB_DEV_CLASS_AUDIO 0x01
#define USB_DEV_CLASS_COMMUNIC 0x02
#define USB_DEV_CLASS_HID 0x03
#define USB_DEV_CLASS_MONITOR 0x04
#define USB_DEV_CLASS_PHYSIC_IF 0x05
#define USB_DEV_CLASS_POWER 0x06
#define USB_DEV_CLASS_IMAGE 0x06
#define USB_DEV_CLASS_PRINTER 0x07
#define USB_DEV_CLASS_STORAGE 0x08
#define USB_DEV_CLASS_HUB 0x09
#define USB_DEV_CLASS_VEN_SPEC 0xFF
#endif
/* USB Hub Class Request */
#ifndef HUB_GET_HUB_DESCRIPTOR
#define HUB_CLEAR_HUB_FEATURE 0x20
#define HUB_CLEAR_PORT_FEATURE 0x23
#define HUB_GET_BUS_STATE 0xA3
#define HUB_GET_HUB_DESCRIPTOR 0xA0
#define HUB_GET_HUB_STATUS 0xA0
#define HUB_GET_PORT_STATUS 0xA3
#define HUB_SET_HUB_DESCRIPTOR 0x20
#define HUB_SET_HUB_FEATURE 0x20
#define HUB_SET_PORT_FEATURE 0x23
#endif
/* Hub Class Feature Selectors */
#ifndef HUB_PORT_RESET
#define HUB_C_HUB_LOCAL_POWER 0
#define HUB_C_HUB_OVER_CURRENT 1
#define HUB_PORT_CONNECTION 0
#define HUB_PORT_ENABLE 1
#define HUB_PORT_SUSPEND 2
#define HUB_PORT_OVER_CURRENT 3
#define HUB_PORT_RESET 4
#define HUB_PORT_POWER 8
#define HUB_PORT_LOW_SPEED 9
#define HUB_C_PORT_CONNECTION 16
#define HUB_C_PORT_ENABLE 17
#define HUB_C_PORT_SUSPEND 18
#define HUB_C_PORT_OVER_CURRENT 19
#define HUB_C_PORT_RESET 20
#endif
/* USB HID Class Request Code */
#ifndef HID_GET_REPORT
#define HID_GET_REPORT 0x01
#define HID_GET_IDLE 0x02
#define HID_GET_PROTOCOL 0x03
#define HID_SET_REPORT 0x09
#define HID_SET_IDLE 0x0A
#define HID_SET_PROTOCOL 0x0B
#endif
/* USB CDC Class request code */
#ifndef CDC_GET_LINE_CODING
#define CDC_GET_LINE_CODING 0X21 /* This request allows the host to find out the currently configured line coding */
#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */
#define CDC_SET_LINE_CTLSTE 0X22 /* This request generates RS-232/V.24 style control signals */
#define CDC_SEND_BREAK 0X23 /* Sends special carrier modulation used to specify RS-232 style break */
#endif
/* USB UDisk */
#ifndef USB_BO_CBW_SIZE
#define USB_BO_CBW_SIZE 0x1F
#define USB_BO_CSW_SIZE 0x0D
#endif
#ifndef USB_BO_CBW_SIG0
#define USB_BO_CBW_SIG0 0x55
#define USB_BO_CBW_SIG1 0x53
#define USB_BO_CBW_SIG2 0x42
#define USB_BO_CBW_SIG3 0x43
#define USB_BO_CSW_SIG0 0x55
#define USB_BO_CSW_SIG1 0x53
#define USB_BO_CSW_SIG2 0x42
#define USB_BO_CSW_SIG3 0x53
#endif
/*******************************************************************************/
/* USBFS Related Register Macro Definition */
/* R8_USB_CTRL */
#define USBFS_UC_HOST_MODE 0x80
#define USBFS_UC_LOW_SPEED 0x40
#define USBFS_UC_DEV_PU_EN 0x20
#define USBFS_UC_SYS_CTRL_MASK 0x30
#define USBFS_UC_SYS_CTRL0 0x00
#define USBFS_UC_SYS_CTRL1 0x10
#define USBFS_UC_SYS_CTRL2 0x20
#define USBFS_UC_SYS_CTRL3 0x30
#define USBFS_UC_INT_BUSY 0x08
#define USBFS_UC_RESET_SIE 0x04
#define USBFS_UC_CLR_ALL 0x02
#define USBFS_UC_DMA_EN 0x01
/* R8_USB_INT_EN */
#define USBFS_UIE_DEV_NAK 0x40
#define USBFS_UIE_FIFO_OV 0x10
#define USBFS_UIE_HST_SOF 0x08
#define USBFS_UIE_SUSPEND 0x04
#define USBFS_UIE_TRANSFER 0x02
#define USBFS_UIE_DETECT 0x01
#define USBFS_UIE_BUS_RST 0x01
/* R8_USB_DEV_AD */
#define USBFS_UDA_GP_BIT 0x80
#define USBFS_USB_ADDR_MASK 0x7F
/* R8_USB_MIS_ST */
#define USBFS_UMS_SOF_PRES 0x80
#define USBFS_UMS_SOF_ACT 0x40
#define USBFS_UMS_SIE_FREE 0x20
#define USBFS_UMS_R_FIFO_RDY 0x10
#define USBFS_UMS_BUS_RESET 0x08
#define USBFS_UMS_SUSPEND 0x04
#define USBFS_UMS_DM_LEVEL 0x02
#define USBFS_UMS_DEV_ATTACH 0x01
/* R8_USB_INT_FG */
#define USBFS_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received
#define USBFS_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK
#define USBFS_U_SIE_FREE 0x20 // RO, indicate USB SIE free status
#define USBFS_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
#define USBFS_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
#define USBFS_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
#define USBFS_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
#define USBFS_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear
#define USBFS_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear
/* R8_USB_INT_ST */
#define USBFS_UIS_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode
#define USBFS_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK
#define USBFS_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode
#define USBFS_UIS_TOKEN_OUT 0x00
#define USBFS_UIS_TOKEN_IN 0x20
#define USBFS_UIS_TOKEN_SETUP 0x30
// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode
// 00: OUT token PID received
// 10: IN token PID received
// 11: SETUP token PID received
#define USBFS_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode
#define USBFS_UIS_H_RES_MASK 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received
/* R32_USB_OTG_CR */
#define USBFS_CR_SESS_VTH 0x20
#define USBFS_CR_VBUS_VTH 0x10
#define USBFS_CR_OTG_EN 0x08
#define USBFS_CR_IDPU 0x04
#define USBFS_CR_CHARGE_VBUS 0x02
#define USBFS_CR_DISCHAR_VBUS 0x01
/* R32_USB_OTG_SR */
#define USBFS_SR_ID_DIG 0x08
#define USBFS_SR_SESS_END 0x04
#define USBFS_SR_SESS_VLD 0x02
#define USBFS_SR_VBUS_VLD 0x01
/* R8_UDEV_CTRL */
#define USBFS_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
#define USBFS_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level
#define USBFS_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level
#define USBFS_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed
#define USBFS_UD_GP_BIT 0x02 // general purpose bit
#define USBFS_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable
/* R8_UEP4_1_MOD */
#define USBFS_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT)
#define USBFS_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN)
#define USBFS_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1
#define USBFS_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT)
#define USBFS_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN)
#define USBFS_UEP4_BUF_MOD 0x01
/* R8_UEP2_3_MOD */
#define USBFS_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT)
#define USBFS_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN)
#define USBFS_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3
#define USBFS_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT)
#define USBFS_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN)
#define USBFS_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2
/* R8_UEP5_6_MOD */
#define USBFS_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT)
#define USBFS_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN)
#define USBFS_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6
#define USBFS_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT)
#define USBFS_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN)
#define USBFS_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5
/* R8_UEP7_MOD */
#define USBFS_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT)
#define USBFS_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN)
#define USBFS_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7
/* R8_UEPn_TX_CTRL */
#define USBFS_UEP_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
#define USBFS_UEP_T_TOG 0x04 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
#define USBFS_UEP_T_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN)
#define USBFS_UEP_T_RES_ACK 0x00
#define USBFS_UEP_T_RES_NONE 0x01
#define USBFS_UEP_T_RES_NAK 0x02
#define USBFS_UEP_T_RES_STALL 0x03
// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN)
// 00: DATA0 or DATA1 then expecting ACK (ready)
// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions
// 10: NAK (busy)
// 11: STALL (error)
// host aux setup
/* R8_UEPn_RX_CTRL, n=0-7 */
#define USBFS_UEP_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
#define USBFS_UEP_R_TOG 0x04 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
#define USBFS_UEP_R_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X receiving (OUT)
#define USBFS_UEP_R_RES_ACK 0x00
#define USBFS_UEP_R_RES_NONE 0x01
#define USBFS_UEP_R_RES_NAK 0x02
#define USBFS_UEP_R_RES_STALL 0x03
// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT)
// 00: ACK (ready)
// 01: no response, time out to host, for non-zero endpoint isochronous transactions
// 10: NAK (busy)
// 11: STALL (error)
/* R8_UHOST_CTRL */
#define USBFS_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
#define USBFS_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level
#define USBFS_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level
#define USBFS_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed
#define USBFS_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset
#define USBFS_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached
/* R32_UH_EP_MOD */
#define USBFS_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal
#define USBFS_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint
// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA
// 0 x: disable endpoint and disable buffer
// 1 0: 64 bytes buffer for transmittal (OUT endpoint)
// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes
#define USBFS_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving
#define USBFS_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint
// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA
// 0 x: disable endpoint and disable buffer
// 1 0: 64 bytes buffer for receiving (IN endpoint)
// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes
/* R16_UH_SETUP */
#define USBFS_UH_PRE_PID_EN 0x0400 // USB host PRE PID enable for low speed device via hub
#define USBFS_UH_SOF_EN 0x0004 // USB host automatic SOF enable
/* R8_UH_EP_PID */
#define USBFS_UH_TOKEN_MASK 0xF0 // bit mask of token PID for USB host transfer
#define USBFS_UH_ENDP_MASK 0x0F // bit mask of endpoint number for USB host transfer
/* R8_UH_RX_CTRL */
#define USBFS_UH_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
#define USBFS_UH_R_TOG 0x04 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1
#define USBFS_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions
/* R8_UH_TX_CTRL */
#define USBFS_UH_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
#define USBFS_UH_T_TOG 0x04 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1
#define USBFS_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions
/*******************************************************************************/
/* Struct Definition */
/* USB Setup Request */
typedef struct __attribute__((packed)) _USB_SETUP_REQ
{
uint8_t bRequestType;
uint8_t bRequest;
uint16_t wValue;
uint16_t wIndex;
uint16_t wLength;
} USB_SETUP_REQ, *PUSB_SETUP_REQ;
/* USB Device Descriptor */
typedef struct __attribute__((packed)) _USB_DEVICE_DESCR
{
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t bcdUSB;
uint8_t bDeviceClass;
uint8_t bDeviceSubClass;
uint8_t bDeviceProtocol;
uint8_t bMaxPacketSize0;
uint16_t idVendor;
uint16_t idProduct;
uint16_t bcdDevice;
uint8_t iManufacturer;
uint8_t iProduct;
uint8_t iSerialNumber;
uint8_t bNumConfigurations;
} USB_DEV_DESCR, *PUSB_DEV_DESCR;
/* USB Configuration Descriptor */
typedef struct __attribute__((packed)) _USB_CONFIG_DESCR
{
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t wTotalLength;
uint8_t bNumInterfaces;
uint8_t bConfigurationValue;
uint8_t iConfiguration;
uint8_t bmAttributes;
uint8_t MaxPower;
} USB_CFG_DESCR, *PUSB_CFG_DESCR;
/* USB Interface Descriptor */
typedef struct __attribute__((packed)) _USB_INTERF_DESCR
{
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bInterfaceNumber;
uint8_t bAlternateSetting;
uint8_t bNumEndpoints;
uint8_t bInterfaceClass;
uint8_t bInterfaceSubClass;
uint8_t bInterfaceProtocol;
uint8_t iInterface;
} USB_ITF_DESCR, *PUSB_ITF_DESCR;
/* USB Endpoint Descriptor */
typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR
{
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bEndpointAddress;
uint8_t bmAttributes;
uint8_t wMaxPacketSizeL;
uint8_t wMaxPacketSizeH;
uint8_t bInterval;
} USB_ENDP_DESCR, *PUSB_ENDP_DESCR;
/* USB Configuration Descriptor Set */
typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG
{
USB_CFG_DESCR cfg_descr;
USB_ITF_DESCR itf_descr;
USB_ENDP_DESCR endp_descr[ 1 ];
} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG;
/* USB HUB Descriptor */
typedef struct __attribute__((packed)) _USB_HUB_DESCR
{
uint8_t bDescLength;
uint8_t bDescriptorType;
uint8_t bNbrPorts;
uint8_t wHubCharacteristicsL;
uint8_t wHubCharacteristicsH;
uint8_t bPwrOn2PwrGood;
uint8_t bHubContrCurrent;
uint8_t DeviceRemovable;
uint8_t PortPwrCtrlMask;
} USB_HUB_DESCR, *PUSB_HUB_DESCR;
/* USB HID Descriptor */
typedef struct __attribute__((packed)) _USB_HID_DESCR
{
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t bcdHID;
uint8_t bCountryCode;
uint8_t bNumDescriptors;
uint8_t bDescriptorTypeX;
uint8_t wDescriptorLengthL;
uint8_t wDescriptorLengthH;
} USB_HID_DESCR, *PUSB_HID_DESCR;
/* USB UDisk */
typedef struct __attribute__((packed)) _UDISK_BOC_CBW
{
uint32_t mCBW_Sig;
uint32_t mCBW_Tag;
uint32_t mCBW_DataLen;
uint8_t mCBW_Flag;
uint8_t mCBW_LUN;
uint8_t mCBW_CB_Len;
uint8_t mCBW_CB_Buf[ 16 ];
} UDISK_BOC_CBW, *PXUDISK_BOC_CBW;
/* USB UDisk */
typedef struct __attribute__((packed)) _UDISK_BOC_CSW
{
uint32_t mCBW_Sig;
uint32_t mCBW_Tag;
uint32_t mCSW_Residue;
uint8_t mCSW_Status;
} UDISK_BOC_CSW, *PXUDISK_BOC_CSW;
#ifdef __cplusplus
}
#endif
#endif /*_CH32V20X_USB_H */

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_wwdg.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the WWDG
* firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_WWDG_H
#define __CH32V20x_WWDG_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* WWDG_Prescaler */
#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
void WWDG_DeInit(void);
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
void WWDG_SetWindowValue(uint8_t WindowValue);
void WWDG_EnableIT(void);
void WWDG_SetCounter(uint8_t Counter);
void WWDG_Enable(uint8_t Counter);
FlagStatus WWDG_GetFlagStatus(void);
void WWDG_ClearFlag(void);
#ifdef __cplusplus
}
#endif
#endif

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SRC_FILES := ch32v20x_adc.c \
ch32v20x_bkp.c \
ch32v20x_can.c \
ch32v20x_dbgmcu.c ch32v20x_dma.c \
ch32v20x_exti.c \
ch32v20x_flash.c \
ch32v20x_gpio.c \
ch32v20x_i2c.c ch32v20x_iwdg.c \
ch32v20x_misc.c \
ch32v20x_opa.c \
ch32v20x_pwr.c \
ch32v20x_rcc.c ch32v20x_rtc.c \
ch32v20x_spi.c \
ch32v20x_tim.c \
ch32v20x_usart.c \
ch32v20x_wwdg.c
include $(KERNEL_ROOT)/compiler.mk

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_bkp.c
* Author : WCH
* Version : V1.0.0
* Date : 2023/01/06
* Description : This file provides all the BKP firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "ch32v20x_bkp.h"
#include "ch32v20x_rcc.h"
/* BKP registers bit mask */
/* OCTLR register bit mask */
#define OCTLR_CAL_MASK ((uint16_t)0xFF80)
#define OCTLR_MASK ((uint16_t)0xFC7F)
/*********************************************************************
* @fn BKP_DeInit
*
* @brief Deinitializes the BKP peripheral registers to their default reset values.
*
* @return none
*/
void BKP_DeInit(void)
{
RCC_BackupResetCmd(ENABLE);
RCC_BackupResetCmd(DISABLE);
}
/*********************************************************************
* @fn BKP_TamperPinLevelConfig
*
* @brief Configures the Tamper Pin active level.
*
* @param BKP_TamperPinLevel: specifies the Tamper Pin active level.
* BKP_TamperPinLevel_High - Tamper pin active on high level.
* BKP_TamperPinLevel_Low - Tamper pin active on low level.
*
* @return none
*/
void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
{
if(BKP_TamperPinLevel)
{
BKP->TPCTLR |= (1 << 1);
}
else
{
BKP->TPCTLR &= ~(1 << 1);
}
}
/*********************************************************************
* @fn BKP_TamperPinCmd
*
* @brief Enables or disables the Tamper Pin activation.
*
* @param NewState - ENABLE or DISABLE.
*
* @return none
*/
void BKP_TamperPinCmd(FunctionalState NewState)
{
if(NewState)
{
BKP->TPCTLR |= (1 << 0);
}
else
{
BKP->TPCTLR &= ~(1 << 0);
}
}
/*********************************************************************
* @fn BKP_ITConfig
*
* @brief Enables or disables the Tamper Pin Interrupt.
*
* @param NewState - ENABLE or DISABLE.
*
* @return none
*/
void BKP_ITConfig(FunctionalState NewState)
{
if(NewState)
{
BKP->TPCSR |= (1 << 2);
}
else
{
BKP->TPCSR &= ~(1 << 2);
}
}
/*********************************************************************
* @fn BKP_RTCOutputConfig
*
* @brief Select the RTC output source to output on the Tamper pin.
*
* @param BKP_RTCOutputSource - specifies the RTC output source.
* BKP_RTCOutputSource_None - no RTC output on the Tamper pin.
* BKP_RTCOutputSource_CalibClock - output the RTC clock with
* frequency divided by 64 on the Tamper pin.
* BKP_RTCOutputSource_Alarm - output the RTC Alarm pulse signal
* on the Tamper pin.
* BKP_RTCOutputSource_Second - output the RTC Second pulse
* signal on the Tamper pin.
*
* @return none
*/
void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
{
uint16_t tmpreg = 0;
tmpreg = BKP->OCTLR;
tmpreg &= OCTLR_MASK;
tmpreg |= BKP_RTCOutputSource;
BKP->OCTLR = tmpreg;
}
/*********************************************************************
* @fn BKP_SetRTCCalibrationValue
*
* @brief Sets RTC Clock Calibration value.
*
* @param CalibrationValue - specifies the RTC Clock Calibration value.
* This parameter must be a number between 0 and 0x7F.
*
* @return none
*/
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
{
uint16_t tmpreg = 0;
tmpreg = BKP->OCTLR;
tmpreg &= OCTLR_CAL_MASK;
tmpreg |= CalibrationValue;
BKP->OCTLR = tmpreg;
}
/*********************************************************************
* @fn BKP_WriteBackupRegister
*
* @brief Writes user data to the specified Data Backup Register.
*
* @param BKP_DR - specifies the Data Backup Register.
* Data - data to write.
*
* @return none
*/
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
{
__IO uint32_t tmp = 0;
tmp = (uint32_t)BKP_BASE;
tmp += BKP_DR;
*(__IO uint32_t *)tmp = Data;
}
/*********************************************************************
* @fn BKP_ReadBackupRegister
*
* @brief Reads data from the specified Data Backup Register.
*
* @param BKP_DR - specifies the Data Backup Register.
* This parameter can be BKP_DRx where x=[1, 42].
*
* @return none
*/
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
{
__IO uint32_t tmp = 0;
tmp = (uint32_t)BKP_BASE;
tmp += BKP_DR;
return (*(__IO uint16_t *)tmp);
}
/*********************************************************************
* @fn BKP_GetFlagStatus
*
* @brief Checks whether the Tamper Pin Event flag is set or not.
*
* @return FlagStatus - SET or RESET.
*/
FlagStatus BKP_GetFlagStatus(void)
{
if(BKP->TPCSR & (1 << 8))
{
return SET;
}
else
{
return RESET;
}
}
/*********************************************************************
* @fn BKP_ClearFlag
*
* @brief Clears Tamper Pin Event pending flag.
*
* @return none
*/
void BKP_ClearFlag(void)
{
BKP->TPCSR |= BKP_CTE;
}
/*********************************************************************
* @fn BKP_GetITStatus
*
* @brief Checks whether the Tamper Pin Interrupt has occurred or not.
*
* @return ITStatus - SET or RESET.
*/
ITStatus BKP_GetITStatus(void)
{
if(BKP->TPCSR & (1 << 9))
{
return SET;
}
else
{
return RESET;
}
}
/*********************************************************************
* @fn BKP_ClearITPendingBit
*
* @brief Clears Tamper Pin Interrupt pending bit.
*
* @return none
*/
void BKP_ClearITPendingBit(void)
{
BKP->TPCSR |= BKP_CTI;
}

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_crc.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the CRC firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "ch32v20x_crc.h"
/*********************************************************************
* @fn CRC_ResetDR
*
* @brief Resets the CRC Data register (DR).
*
* @return none
*/
void CRC_ResetDR(void)
{
CRC->CTLR = CRC_CTLR_RESET;
}
/*********************************************************************
* @fn CRC_CalcCRC
*
* @brief Computes the 32-bit CRC of a given data word(32-bit).
*
* @param Data - data word(32-bit) to compute its CRC.
*
* @return 32-bit CRC.
*/
uint32_t CRC_CalcCRC(uint32_t Data)
{
CRC->DATAR = Data;
return (CRC->DATAR);
}
/*********************************************************************
* @fn CRC_CalcBlockCRC
*
* @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
*
* @param pBuffer - pointer to the buffer containing the data to be computed.
* BufferLength - length of the buffer to be computed.
*
* @return 32-bit CRC.
*/
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
{
uint32_t index = 0;
for(index = 0; index < BufferLength; index++){
CRC->DATAR = pBuffer[index];
}
return (CRC->DATAR);
}
/*********************************************************************
* @fn CRC_GetCRC
*
* @brief Returns the current CRC value.
*
* @return 32-bit CRC.
*/
uint32_t CRC_GetCRC(void)
{
return (CRC->DATAR);
}
/*********************************************************************
* @fn CRC_SetIDRegister
*
* @brief Stores a 8-bit data in the Independent Data(ID) register.
*
* @param IDValue - 8-bit value to be stored in the ID register.
*
* @return none
*/
void CRC_SetIDRegister(uint8_t IDValue)
{
CRC->IDATAR = IDValue;
}
/*********************************************************************
* @fn CRC_GetIDRegister
*
* @brief Returns the 8-bit data stored in the Independent Data(ID) register.
*
* @return 8-bit value of the ID register.
*/
uint8_t CRC_GetIDRegister(void)
{
return (CRC->IDATAR);
}

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_dbgmcu.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the DBGMCU firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "ch32v20x_dbgmcu.h"
#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF)
/*********************************************************************
* @fn DBGMCU_GetREVID
*
* @brief Returns the device revision identifier.
*
* @return Revision identifier.
*/
uint32_t DBGMCU_GetREVID(void)
{
return ((*(uint32_t *)0x1FFFF704) >> 16);
}
/*********************************************************************
* @fn DBGMCU_GetDEVID
*
* @brief Returns the device identifier.
*
* @return Device identifier.
*/
uint32_t DBGMCU_GetDEVID(void)
{
return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK);
}
/*********************************************************************
* @fn __get_DEBUG_CR
*
* @brief Return the DEBUGE Control Register
*
* @return DEBUGE Control value
*/
uint32_t __get_DEBUG_CR(void)
{
uint32_t result;
__asm volatile("csrr %0,""0x7C0" : "=r"(result));
return (result);
}
/*********************************************************************
* @fn __set_DEBUG_CR
*
* @brief Set the DEBUGE Control Register
*
* @param value - set DEBUGE Control value
*
* @return none
*/
void __set_DEBUG_CR(uint32_t value)
{
__asm volatile("csrw 0x7C0, %0" : : "r"(value));
}
/*********************************************************************
* @fn DBGMCU_Config
*
* @brief Configures the specified peripheral and low power mode behavior
* when the MCU under Debug mode.
*
* @param DBGMCU_Periph - specifies the peripheral and low power mode.
* DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted
* DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted
* DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted
* DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
{
uint32_t val;
if(NewState != DISABLE)
{
__set_DEBUG_CR(DBGMCU_Periph);
}
else
{
val = __get_DEBUG_CR();
val &= ~(uint32_t)DBGMCU_Periph;
__set_DEBUG_CR(val);
}
}
/*********************************************************************
* @fn DBGMCU_GetCHIPID
*
* @brief Returns the CHIP identifier.
*
* @return Device identifier.
* ChipID List-
* CH32V203C8U6-0x203005x0
* CH32V203C8T6-0x203105x0
* CH32V203K8T6-0x203205x0
* CH32V203C6T6-0x203305x0
* CH32V203K6T6-0x203505x0
* CH32V203G6U6-0x203605x0
* CH32V203G8R6-0x203B05x0
* CH32V203F8U6-0x203E05x0
* CH32V203F6P6-0x203705x0-0x203905x0
* CH32V203F8P6-0x203A05x0
* CH32V203RBT6-0x203405xC
* CH32V208WBU6-0x208005xC
* CH32V208RBT6-0x208105xC
* CH32V208CBU6-0x208205xC
* CH32V208GBU6-0x208305xC
*/
uint32_t DBGMCU_GetCHIPID( void )
{
return( *( uint32_t * )0x1FFFF704 );
}

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_dma.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the DMA firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "ch32v20x_dma.h"
#include "ch32v20x_rcc.h"
/* DMA1 Channelx interrupt pending bit masks */
#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
#define DMA1_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8))
/* DMA2 FLAG mask */
#define FLAG_Mask ((uint32_t)0x10000000)
/* DMA registers Masks */
#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F)
/*********************************************************************
* @fn DMA_DeInit
*
* @brief Deinitializes the DMAy Channelx registers to their default
* reset values.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
*
* @return none
*/
void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx)
{
DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
DMAy_Channelx->CFGR = 0;
DMAy_Channelx->CNTR = 0;
DMAy_Channelx->PADDR = 0;
DMAy_Channelx->MADDR = 0;
if(DMAy_Channelx == DMA1_Channel1)
{
DMA1->INTFCR |= DMA1_Channel1_IT_Mask;
}
else if(DMAy_Channelx == DMA1_Channel2)
{
DMA1->INTFCR |= DMA1_Channel2_IT_Mask;
}
else if(DMAy_Channelx == DMA1_Channel3)
{
DMA1->INTFCR |= DMA1_Channel3_IT_Mask;
}
else if(DMAy_Channelx == DMA1_Channel4)
{
DMA1->INTFCR |= DMA1_Channel4_IT_Mask;
}
else if(DMAy_Channelx == DMA1_Channel5)
{
DMA1->INTFCR |= DMA1_Channel5_IT_Mask;
}
else if(DMAy_Channelx == DMA1_Channel6)
{
DMA1->INTFCR |= DMA1_Channel6_IT_Mask;
}
else if(DMAy_Channelx == DMA1_Channel7)
{
DMA1->INTFCR |= DMA1_Channel7_IT_Mask;
}
else if(DMAy_Channelx == DMA1_Channel8)
{
DMA1->INTFCR |= DMA1_Channel8_IT_Mask;
}
}
/*********************************************************************
* @fn DMA_Init
*
* @brief Initializes the DMAy Channelx according to the specified
* parameters in the DMA_InitStruct.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
* DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
* contains the configuration information for the specified DMA Channel.
*
* @return none
*/
void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct)
{
uint32_t tmpreg = 0;
tmpreg = DMAy_Channelx->CFGR;
tmpreg &= CFGR_CLEAR_Mask;
tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
DMAy_Channelx->CFGR = tmpreg;
DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize;
DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr;
DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr;
}
/*********************************************************************
* @fn DMA_StructInit
*
* @brief Fills each DMA_InitStruct member with its default value.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
* DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
* contains the configuration information for the specified DMA Channel.
*
* @return none
*/
void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct)
{
DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
DMA_InitStruct->DMA_MemoryBaseAddr = 0;
DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
DMA_InitStruct->DMA_BufferSize = 0;
DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
}
/*********************************************************************
* @fn DMA_Cmd
*
* @brief Enables or disables the specified DMAy Channelx.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
* NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
*
* @return none
*/
void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
DMAy_Channelx->CFGR |= DMA_CFGR1_EN;
}
else
{
DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
}
}
/*********************************************************************
* @fn DMA_ITConfig
*
* @brief Enables or disables the specified DMAy Channelx interrupts.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
* DMA_IT - specifies the DMA interrupts sources to be enabled
* or disabled.
* DMA_IT_TC - Transfer complete interrupt mask
* DMA_IT_HT - Half transfer interrupt mask
* DMA_IT_TE - Transfer error interrupt mask
* NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
*
* @return none
*/
void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
{
if(NewState != DISABLE)
{
DMAy_Channelx->CFGR |= DMA_IT;
}
else
{
DMAy_Channelx->CFGR &= ~DMA_IT;
}
}
/*********************************************************************
* @fn DMA_SetCurrDataCounter
*
* @brief Sets the number of data units in the current DMAy Channelx transfer.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
* DataNumber - The number of data units in the current DMAy Channelx
* transfer.
*
* @return none
*/
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber)
{
DMAy_Channelx->CNTR = DataNumber;
}
/*********************************************************************
* @fn DMA_GetCurrDataCounter
*
* @brief Returns the number of remaining data units in the current
* DMAy Channelx transfer.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
*
* @return DataNumber - The number of remaining data units in the current
* DMAy Channelx transfer.
*/
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx)
{
return ((uint16_t)(DMAy_Channelx->CNTR));
}
/*********************************************************************
* @fn DMA_GetFlagStatus
*
* @brief Checks whether the specified DMAy Channelx flag is set or not.
*
* @param DMAy_FLAG - specifies the flag to check.
* DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
* DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
* DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
* DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
* DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
* DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
* DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
* DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
* DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
* DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
* DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
* DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
* DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
* DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
* DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
* DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
* DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
* DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
* DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
* DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
* DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
* DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
* DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
* DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
* DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
* DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
* DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
* DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
* DMA2_FLAG_GL1 - DMA2 Channel1 global flag.
* DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag.
* DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag.
* DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag.
* @return The new state of DMAy_FLAG (SET or RESET).
*/
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
{
FlagStatus bitstatus = RESET;
uint32_t tmpreg = 0;
tmpreg = DMA1->INTFR;
if((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn DMA_ClearFlag
*
* @brief Clears the DMAy Channelx's pending flags.
*
* @param DMAy_FLAG - specifies the flag to check.
* DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
* DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
* DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
* DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
* DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
* DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
* DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
* DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
* DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
* DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
* DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
* DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
* DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
* DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
* DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
* DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
* DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
* DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
* DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
* DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
* DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
* DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
* DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
* DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
* DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
* DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
* DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
* DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
* DMA2_FLAG_GL1 - DMA2 Channel1 global flag.
* DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag.
* DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag.
* DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag.
* @return none
*/
void DMA_ClearFlag(uint32_t DMAy_FLAG)
{
DMA1->INTFCR = DMAy_FLAG;
}
/*********************************************************************
* @fn DMA_GetITStatus
*
* @brief Checks whether the specified DMAy Channelx interrupt has
* occurred or not.
*
* @param DMAy_IT - specifies the DMAy interrupt source to check.
* DMA1_IT_GL1 - DMA1 Channel1 global flag.
* DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
* DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
* DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
* DMA1_IT_GL2 - DMA1 Channel2 global flag.
* DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
* DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
* DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
* DMA1_IT_GL3 - DMA1 Channel3 global flag.
* DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
* DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
* DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
* DMA1_IT_GL4 - DMA1 Channel4 global flag.
* DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
* DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
* DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
* DMA1_IT_GL5 - DMA1 Channel5 global flag.
* DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
* DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
* DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
* DMA1_IT_GL6 - DMA1 Channel6 global flag.
* DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
* DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
* DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
* DMA1_IT_GL7 - DMA1 Channel7 global flag.
* DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
* DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
* DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
* DMA2_IT_GL1 - DMA2 Channel1 global flag.
* DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag.
* DMA2_IT_HT1 - DMA2 Channel1 half transfer flag.
* DMA2_IT_TE1 - DMA2 Channel1 transfer error flag.
* @return The new state of DMAy_IT (SET or RESET).
*/
ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
{
ITStatus bitstatus = RESET;
uint32_t tmpreg = 0;
tmpreg = DMA1->INTFR;
if((tmpreg & DMAy_IT) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn DMA_ClearITPendingBit
*
* @brief Clears the DMAy Channelx's interrupt pending bits.
*
* @param DMAy_IT - specifies the DMAy interrupt source to check.
* DMA1_IT_GL1 - DMA1 Channel1 global flag.
* DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
* DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
* DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
* DMA1_IT_GL2 - DMA1 Channel2 global flag.
* DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
* DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
* DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
* DMA1_IT_GL3 - DMA1 Channel3 global flag.
* DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
* DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
* DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
* DMA1_IT_GL4 - DMA1 Channel4 global flag.
* DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
* DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
* DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
* DMA1_IT_GL5 - DMA1 Channel5 global flag.
* DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
* DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
* DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
* DMA1_IT_GL6 - DMA1 Channel6 global flag.
* DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
* DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
* DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
* DMA1_IT_GL7 - DMA1 Channel7 global flag.
* DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
* DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
* DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
* DMA2_IT_GL1 - DMA2 Channel1 global flag.
* DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag.
* DMA2_IT_HT1 - DMA2 Channel1 half transfer flag.
* DMA2_IT_TE1 - DMA2 Channel1 transfer error flag.
* @return none
*/
void DMA_ClearITPendingBit(uint32_t DMAy_IT)
{
DMA1->INTFCR = DMAy_IT;
}

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_exti.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the EXTI firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "ch32v20x_exti.h"
/* No interrupt selected */
#define EXTI_LINENONE ((uint32_t)0x00000)
/*********************************************************************
* @fn EXTI_DeInit
*
* @brief Deinitializes the EXTI peripheral registers to their default
* reset values.
*
* @return none.
*/
void EXTI_DeInit(void)
{
EXTI->INTENR = 0x00000000;
EXTI->EVENR = 0x00000000;
EXTI->RTENR = 0x00000000;
EXTI->FTENR = 0x00000000;
EXTI->INTFR = 0x000FFFFF;
}
/*********************************************************************
* @fn EXTI_Init
*
* @brief Initializes the EXTI peripheral according to the specified
* parameters in the EXTI_InitStruct.
*
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
*
* @return none.
*/
void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct)
{
uint32_t tmp = 0;
tmp = (uint32_t)EXTI_BASE;
if(EXTI_InitStruct->EXTI_LineCmd != DISABLE)
{
EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line;
EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line;
tmp += EXTI_InitStruct->EXTI_Mode;
*(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line;
EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line;
if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
{
EXTI->RTENR |= EXTI_InitStruct->EXTI_Line;
EXTI->FTENR |= EXTI_InitStruct->EXTI_Line;
}
else
{
tmp = (uint32_t)EXTI_BASE;
tmp += EXTI_InitStruct->EXTI_Trigger;
*(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
}
}
else
{
tmp += EXTI_InitStruct->EXTI_Mode;
*(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line;
}
}
/*********************************************************************
* @fn EXTI_StructInit
*
* @brief Fills each EXTI_InitStruct member with its reset value.
*
* @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure
*
* @return none.
*/
void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct)
{
EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
}
/*********************************************************************
* @fn EXTI_GenerateSWInterrupt
*
* @brief Generates a Software interrupt.
*
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
*
* @return none.
*/
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
{
EXTI->SWIEVR |= EXTI_Line;
}
/*********************************************************************
* @fn EXTI_GetFlagStatus
*
* @brief Checks whether the specified EXTI line flag is set or not.
*
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
*
* @return The new state of EXTI_Line (SET or RESET).
*/
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
{
FlagStatus bitstatus = RESET;
if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn EXTI_ClearFlag
*
* @brief Clears the EXTI's line pending flags.
*
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
*
* @return None
*/
void EXTI_ClearFlag(uint32_t EXTI_Line)
{
EXTI->INTFR = EXTI_Line;
}
/*********************************************************************
* @fn EXTI_GetITStatus
*
* @brief Checks whether the specified EXTI line is asserted or not.
*
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
*
* @return The new state of EXTI_Line (SET or RESET).
*/
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
{
ITStatus bitstatus = RESET;
uint32_t enablestatus = 0;
enablestatus = EXTI->INTENR & EXTI_Line;
if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn EXTI_ClearITPendingBit
*
* @brief Clears the EXTI's line pending bits.
*
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
*
* @return none
*/
void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
{
EXTI->INTFR = EXTI_Line;
}

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_iwdg.c
* Author : WCH
* Version : V1.0.0
* Date : 2023/12/29
* Description : This file provides all the IWDG firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "ch32v20x_iwdg.h"
/* CTLR register bit mask */
#define CTLR_KEY_Reload ((uint16_t)0xAAAA)
#define CTLR_KEY_Enable ((uint16_t)0xCCCC)
/*********************************************************************
* @fn IWDG_WriteAccessCmd
*
* @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers.
*
* @param WDG_WriteAccess - new state of write access to IWDG_PSCR and
* IWDG_RLDR registers.
* IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and
* IWDG_RLDR registers.
* IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR
* and IWDG_RLDR registers.
*
* @return none
*/
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
{
IWDG->CTLR = IWDG_WriteAccess;
}
/*********************************************************************
* @fn IWDG_SetPrescaler
*
* @brief Sets IWDG Prescaler value.
*
* @param IWDG_Prescaler - specifies the IWDG Prescaler value.
* IWDG_Prescaler_4 - IWDG prescaler set to 4.
* IWDG_Prescaler_8 - IWDG prescaler set to 8.
* IWDG_Prescaler_16 - IWDG prescaler set to 16.
* IWDG_Prescaler_32 - IWDG prescaler set to 32.
* IWDG_Prescaler_64 - IWDG prescaler set to 64.
* IWDG_Prescaler_128 - IWDG prescaler set to 128.
* IWDG_Prescaler_256 - IWDG prescaler set to 256.
*
* @return none
*/
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
{
IWDG->PSCR = IWDG_Prescaler;
}
/*********************************************************************
* @fn IWDG_SetReload
*
* @brief Sets IWDG Reload value.
*
* @param Reload - specifies the IWDG Reload value.
* This parameter must be a number between 0 and 0x0FFF.
*
* @return none
*/
void IWDG_SetReload(uint16_t Reload)
{
IWDG->RLDR = Reload;
}
/*********************************************************************
* @fn IWDG_ReloadCounter
*
* @brief Reloads IWDG counter with value defined in the reload register.
*
* @return none
*/
void IWDG_ReloadCounter(void)
{
IWDG->CTLR = CTLR_KEY_Reload;
}
/*********************************************************************
* @fn IWDG_Enable
*
* @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled).
*
* @return none
*/
void IWDG_Enable(void)
{
IWDG->CTLR = CTLR_KEY_Enable;
while((RCC->RSTSCKR)|(0x2)!=SET);
}
/*********************************************************************
* @fn IWDG_GetFlagStatus
*
* @brief Checks whether the specified IWDG flag is set or not.
*
* @param IWDG_FLAG - specifies the flag to check.
* IWDG_FLAG_PVU - Prescaler Value Update on going.
* IWDG_FLAG_RVU - Reload Value Update on going.
*
* @return none
*/
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
{
FlagStatus bitstatus = RESET;
if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_misc.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the miscellaneous firmware functions .
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "ch32v20x_misc.h"
__IO uint32_t NVIC_Priority_Group = 0;
/*********************************************************************
* @fn NVIC_PriorityGroupConfig
*
* @brief Configures the priority grouping - pre-emption priority and subpriority.
*
* @param NVIC_PriorityGroup - specifies the priority grouping bits length.
* NVIC_PriorityGroup_0 - 0 bits for pre-emption priority
* 3 bits for subpriority
* NVIC_PriorityGroup_1 - 1 bits for pre-emption priority
* 2 bits for subpriority
*
* @return none
*/
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
{
NVIC_Priority_Group = NVIC_PriorityGroup;
}
/*********************************************************************
* @fn NVIC_Init
*
* @brief Initializes the NVIC peripheral according to the specified parameters in
* the NVIC_InitStruct.
*
* @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the
* configuration information for the specified NVIC peripheral.
* interrupt nesting enable(CSR-0x804 bit1 = 1)
* NVIC_IRQChannelPreemptionPriority - range from 0 to 1.
* NVIC_IRQChannelSubPriority - range from 0 to 3.
*
* interrupt nesting disable(CSR-0x804 bit1 = 0)
* NVIC_IRQChannelPreemptionPriority - range is 0.
* NVIC_IRQChannelSubPriority - range from 0 to 7.
*
* @return none
*/
void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct)
{
#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN)
if(NVIC_Priority_Group == NVIC_PriorityGroup_0)
{
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4);
}
#else
if(NVIC_Priority_Group == NVIC_PriorityGroup_1)
{
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1)
{
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5));
}
else if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 0)
{
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5));
}
}
#endif
if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
{
NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
}
else
{
NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
}
}

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_opa.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the OPA firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "ch32v20x_opa.h"
#define OPA_MASK ((uint32_t)0x000F)
#define OPA_Total_NUM 4
/*********************************************************************
* @fn OPA_DeInit
*
* @brief Deinitializes the OPA peripheral registers to their default
* reset values.
*
* @return none
*/
void OPA_DeInit(void)
{
OPA->CR = 0;
}
/*********************************************************************
* @fn OPA_Init
*
* @brief Initializes the OPA peripheral according to the specified
* parameters in the OPA_InitStruct.
*
* @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure
*
* @return none
*/
void OPA_Init(OPA_InitTypeDef *OPA_InitStruct)
{
uint32_t tmp = 0;
tmp = OPA->CR;
tmp &= ~(OPA_MASK << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM));
tmp |= (((OPA_InitStruct->PSEL << OPA_PSEL_OFFSET) | (OPA_InitStruct->NSEL << OPA_NSEL_OFFSET) | (OPA_InitStruct->Mode << OPA_MODE_OFFSET)) << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM));
OPA->CR = tmp;
}
/*********************************************************************
* @fn OPA_StructInit
*
* @brief Fills each OPA_StructInit member with its reset value.
*
* @param OPA_StructInit - pointer to a OPA_InitTypeDef structure
*
* @return none
*/
void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct)
{
OPA_InitStruct->Mode = OUT_IO_OUT1;
OPA_InitStruct->PSEL = CHP0;
OPA_InitStruct->NSEL = CHN0;
OPA_InitStruct->OPA_NUM = OPA1;
}
/*********************************************************************
* @fn OPA_Cmd
*
* @brief Enables or disables the specified OPA peripheral.
*
* @param OPA_NUM - Select OPA
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState)
{
if(NewState == ENABLE)
{
OPA->CR |= (1 << (OPA_NUM * OPA_Total_NUM));
}
else
{
OPA->CR &= ~(1 << (OPA_NUM * OPA_Total_NUM));
}
}

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