modify XiUOS DIR : (1.add plc_demo in APP_Framework/control_app; 2.add industrial_network、industrial_fieldbus and industrial_wlan; 3.add XiZi_AIoT and modify XiZi as XiZi_IIoT.)

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/Kconfig

@@ -0,0 +1,138 @@
+menuconfig BSP_USING_CH438
+bool "Using CH438 device"
+default y
+if BSP_USING_CH438
+source "$BSP_DIR/third_party_driver/ch438/Kconfig"
+endif
+
+menuconfig BSP_USING_DMA
+bool "Using DMA device"
+default y
+if BSP_USING_DMA
+source "$BSP_DIR/third_party_driver/common/Kconfig"
+endif
+
+menuconfig BSP_USING_EXTMEM
+bool "Using EXTMEM device"
+default n
+select MEM_EXTERN_SRAM
+if BSP_USING_EXTMEM
+source "$BSP_DIR/third_party_driver/extmem/Kconfig"
+endif
+
+menuconfig BSP_USING_GPIO
+bool "Using GPIO device "
+default y
+select RESOURCES_PIN
+if BSP_USING_GPIO
+source "$BSP_DIR/third_party_driver/gpio/Kconfig"
+endif
+
+menuconfig BSP_USING_I2C
+bool "Using I2C device"
+default n
+select RESOURCES_I2C
+if BSP_USING_I2C
+source "$BSP_DIR/third_party_driver/i2c/Kconfig"
+endif
+
+menuconfig BSP_USING_LCD
+bool "Using LCD device"
+default n
+select RESOURCES_LCD
+if BSP_USING_LCD
+source "$BSP_DIR/third_party_driver/lcd/Kconfig"
+endif
+
+menuconfig BSP_USING_RTC
+bool "Using RTC device"
+default n
+select RESOURCES_RTC
+if BSP_USING_RTC
+source "$BSP_DIR/third_party_driver/rtc/Kconfig"
+endif
+
+menuconfig BSP_USING_SDIO
+bool "Using SDIO device"
+default n
+select RESOURCES_SDIO
+if BSP_USING_SDIO
+source "$BSP_DIR/third_party_driver/sdio/Kconfig"
+endif
+
+menuconfig BSP_USING_SPI
+bool "Using SPI device"
+default n
+select RESOURCES_SPI
+select BSP_USING_DMA
+if BSP_USING_SPI
+source "$BSP_DIR/third_party_driver/spi/Kconfig"
+endif
+
+menuconfig BSP_USING_HWTIMER
+bool "Using HWTIMER device"
+default n
+select RESOURCES_HWTIMER
+if BSP_USING_HWTIMER
+source "$BSP_DIR/third_party_driver/timer/Kconfig"
+endif
+
+menuconfig BSP_USING_TOUCH
+bool "Using TOUCH device"
+default n
+select RESOURCES_TOUCH
+if BSP_USING_TOUCH
+source "$BSP_DIR/third_party_driver/touch/Kconfig"
+endif
+
+menuconfig BSP_USING_UART
+bool "Using UART device"
+default y
+select RESOURCES_SERIAL
+if BSP_USING_UART
+source "$BSP_DIR/third_party_driver/uart/Kconfig"
+endif
+
+menuconfig BSP_USING_ADC
+bool "Using ADC device"
+default n
+select RESOURCES_ADC
+if BSP_USING_ADC
+source "$BSP_DIR/third_party_driver/adc/Kconfig"
+endif
+
+menuconfig BSP_USING_DAC
+bool "Using DAC device"
+default n
+select RESOURCES_DAC
+if BSP_USING_DAC
+source "$BSP_DIR/third_party_driver/dac/Kconfig"
+endif
+
+menuconfig BSP_USING_CAN
+bool "Using CAN device"
+default n
+select RESOURCES_CAN
+if BSP_USING_CAN
+source "$BSP_DIR/third_party_driver/can/Kconfig"
+endif
+
+menuconfig BSP_USING_USB
+bool "Using USB device"
+default n
+select BSP_USING_STM32_USBH
+select RESOURCES_USB
+select RESOURCES_USB_HOST
+select USBH_MSTORAGE
+select RESOURCES_USB_DEVICE
+if BSP_USING_USB
+source "$BSP_DIR/third_party_driver/usb/Kconfig"
+endif
+
+menuconfig BSP_USING_WDT
+bool "Using WATCHDOG device"
+default y
+select RESOURCES_WDT
+if BSP_USING_WDT
+source "$BSP_DIR/third_party_driver/watchdog/Kconfig"
+endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/Makefile

@@ -0,0 +1,67 @@
+SRC_DIR := common    
+
+ifeq ($(CONFIG_BSP_USING_CH438),y)
+  SRC_DIR += ch438
+endif
+
+ifeq ($(CONFIG_BSP_USING_EXTMEM),y)
+  SRC_DIR += extmem
+endif
+
+ifeq ($(CONFIG_BSP_USING_GPIO),y)
+  SRC_DIR += gpio
+endif
+
+ifeq ($(CONFIG_BSP_USING_I2C),y)
+  SRC_DIR += i2c
+endif
+
+ifeq ($(CONFIG_BSP_USING_LCD),y)
+  SRC_DIR += lcd
+endif
+
+ifeq ($(CONFIG_BSP_USING_RTC),y)
+  SRC_DIR += rtc
+endif
+
+ifeq ($(CONFIG_BSP_USING_SDIO),y)
+  SRC_DIR += sdio
+endif
+
+ifeq ($(CONFIG_BSP_USING_SPI),y)
+  SRC_DIR += spi
+endif
+
+ifeq ($(CONFIG_BSP_USING_HWTIMER),y)
+  SRC_DIR += timer
+endif
+
+ifeq ($(CONFIG_BSP_USING_TOUCH),y)
+  SRC_DIR += touch
+endif
+
+ifeq ($(CONFIG_BSP_USING_UART),y)
+  SRC_DIR += uart
+endif
+
+ifeq ($(CONFIG_BSP_USING_USB),y)
+  SRC_DIR += usb
+endif
+
+ifeq ($(CONFIG_BSP_USING_WDT),y)
+  SRC_DIR += watchdog
+endif
+
+ifeq ($(CONFIG_BSP_USING_CAN),y)
+  SRC_DIR += can
+endif
+
+ifeq ($(CONFIG_BSP_USING_ADC),y)
+  SRC_DIR += adc
+endif
+
+ifeq ($(CONFIG_BSP_USING_DAC),y)
+  SRC_DIR += dac
+endif
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/adc/Kconfig

@@ -0,0 +1,76 @@
+
+
+menuconfig BSP_USING_ADC1
+    bool "Enable ADC1"
+    default n
+    if BSP_USING_ADC1
+        config ADC1_BUS_NAME
+            string "adc 1 bus name"
+            default "adc1"
+
+        config ADC1_DRIVER_NAME
+            string "adc 1 driver name"
+            default "adc1_drv"
+
+        config ADC1_DEVICE_NAME
+            string "adc 1 bus device name"
+            default "adc1_dev"
+
+        config ADC1_GPIO_NUM
+            int "adc 1 gpio pin num"
+            default "0"
+        
+        config ADC1_GPIO_DEF
+            string "adc 1 gpio define type"
+            default "A"
+    endif
+
+menuconfig BSP_USING_ADC2
+    bool "Enable ADC2"
+    default n
+    if BSP_USING_ADC2
+        config ADC2_BUS_NAME
+            string "adc 2 bus name"
+            default "adc2"
+
+        config ADC2_DRIVER_NAME
+            string "adc 2 driver name"
+            default "adc2_drv"
+
+        config ADC2_DEVICE_NAME
+            string "adc 2 bus device name"
+            default "adc2_dev"
+
+        config ADC2_GPIO_NUM
+            int "adc 2 gpio pin num"
+            default "6"
+        
+        config ADC2_GPIO_DEF
+            string "adc 2 gpio define type"
+            default "A"
+    endif
+
+menuconfig BSP_USING_ADC3
+    bool "Enable ADC3"
+    default n
+    if BSP_USING_ADC3
+        config ADC3_BUS_NAME
+            string "adc 3 bus name"
+            default "adc3"
+
+        config ADC3_DRIVER_NAME
+            string "adc 3 driver name"
+            default "adc3_drv"
+
+        config ADC3_DEVICE_NAME
+            string "adc 3 bus device name"
+            default "adc3_dev"
+
+        config ADC3_GPIO_NUM
+            int "adc 3 gpio pin num"
+            default "0"
+        
+        config ADC3_GPIO_DEF
+            string "adc 3 gpio define type"
+            default "A"
+    endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/adc/Makefile

@@ -0,0 +1,3 @@
+SRC_FILES := connect_adc.c hardware_adc.c
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/adc/connect_adc.c

@@ -0,0 +1,433 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_adc.c
+* @brief support to register ADC pointer and function
+* @version 1.1
+* @author AIIT XUOS Lab
+* @date 2021-12-28
+*/
+
+#include <connect_adc.h>
+
+#define _ADC_CONS(string1, string2) string1##string2
+#define ADC_CONS(string1, string2) _ADC_CONS(string1, string2)
+
+#ifdef BSP_USING_ADC1
+#define ADC1_GPIO      ADC_CONS(GPIO_Pin_, ADC1_GPIO_NUM)
+#endif
+
+#ifdef BSP_USING_ADC2
+#define ADC2_GPIO      ADC_CONS(GPIO_Pin_, ADC2_GPIO_NUM)
+#endif
+
+#ifdef BSP_USING_ADC3
+#define ADC3_GPIO      ADC_CONS(GPIO_Pin_, ADC3_GPIO_NUM)
+#endif
+
+static int Stm32AdcUdelay(uint32 us)
+{
+    uint32 ticks;
+    uint32 told, tnow, tcnt = 0;
+    uint32 reload = SysTick->LOAD;
+
+    ticks = us * reload / (1000000 / TICK_PER_SECOND);
+    told = SysTick->VAL;
+    while (1) {
+        tnow = SysTick->VAL;
+        if (tnow != told) {
+            if (tnow < told) {
+                tcnt += told - tnow;
+            } else {
+                tcnt += reload - tnow + told;
+            }
+            told = tnow;
+            if (tcnt >= ticks) {
+                return 0;
+                break;
+            }
+        }
+    }
+}
+
+static GPIO_TypeDef* AdcGetGpioType(char *adc_gpio_def)
+{
+    if (0 == strncmp(adc_gpio_def, "A", 2)) {
+        return GPIOA;
+    } else if (0 == strncmp(adc_gpio_def, "B", 2)) {
+        return GPIOB;
+    } else if (0 == strncmp(adc_gpio_def, "C", 2)) {
+        return GPIOC;
+    } else if (0 == strncmp(adc_gpio_def, "F", 2)) {
+        return GPIOF;
+    } else {
+        printf("AdcGetGpioType do not support %s GPIO\n", adc_gpio_def);
+        return GPIOA;
+    }
+}
+
+static uint32 AdcGetGpioRcc(char *adc_gpio_def)
+{
+    if (0 == strncmp(adc_gpio_def, "A", 2)) {
+        return RCC_AHB1Periph_GPIOA;
+    } else if (0 == strncmp(adc_gpio_def, "B", 2)) {
+        return RCC_AHB1Periph_GPIOB;
+    } else if (0 == strncmp(adc_gpio_def, "C", 2)) {
+        return RCC_AHB1Periph_GPIOC;
+    } else if (0 == strncmp(adc_gpio_def, "F", 2)) {
+        return RCC_AHB1Periph_GPIOF;
+    } else {
+        printf("AdcGetGpioRcc do not support %s GPIO\n", adc_gpio_def);
+        return RCC_AHB1Periph_GPIOA;
+    }
+}
+
+static void AdcInit(struct AdcHardwareDevice *adc_dev)
+{    
+    GPIO_InitTypeDef GPIO_InitStructure;
+    ADC_CommonInitTypeDef ADC_CommonInitStructure;
+    ADC_InitTypeDef ADC_InitStructure;
+    uint32_t RCC_AHB1Periph;
+    GPIO_TypeDef* GPIOx;
+
+#ifdef BSP_USING_ADC1
+    if (0 == strncmp(adc_dev->haldev.dev_name, ADC1_DEVICE_NAME, NAME_NUM_MAX)) {
+
+        GPIOx = AdcGetGpioType(ADC1_GPIO_DEF);
+        RCC_AHB1Periph = AdcGetGpioRcc(ADC1_GPIO_DEF);
+
+        RCC_AHB1PeriphClockCmd(RCC_AHB1Periph, ENABLE);//enable GPIOA clock
+        RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);//enable ADC1 clock
+
+        GPIO_InitStructure.GPIO_Pin = ADC1_GPIO;
+        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;//analog input
+        GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+        GPIO_Init(GPIOx, &GPIO_InitStructure);
+
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);	 
+
+        ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent;
+        ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles;
+        ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
+        ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div4;
+        ADC_CommonInit(&ADC_CommonInitStructure);
+
+        ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b;//12 bit mode
+        ADC_InitStructure.ADC_ScanConvMode = DISABLE;	
+        ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
+        ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
+        ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;	
+        ADC_InitStructure.ADC_NbrOfConversion = 1;
+        ADC_Init(ADC1, &ADC_InitStructure);
+
+        ADC_Cmd(ADC1, ENABLE);	
+    }
+#endif
+
+#ifdef BSP_USING_ADC2
+    if (0 == strncmp(adc_dev->haldev.dev_name, ADC2_DEVICE_NAME, NAME_NUM_MAX)) {
+
+        GPIOx = AdcGetGpioType(ADC2_GPIO_DEF);
+        RCC_AHB1Periph = AdcGetGpioRcc(ADC2_GPIO_DEF);
+
+        RCC_AHB1PeriphClockCmd(RCC_AHB1Periph, ENABLE);//enable GPIOA clock
+        RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC2, ENABLE);//enable ADC2 clock
+
+        GPIO_InitStructure.GPIO_Pin = ADC2_GPIO;
+        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;//analog input
+        GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+        GPIO_Init(GPIOx, &GPIO_InitStructure);
+
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);	 
+
+        ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent;
+        ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles;
+        ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
+        ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div4;
+        ADC_CommonInit(&ADC_CommonInitStructure);
+
+        ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b;//12 bit mode
+        ADC_InitStructure.ADC_ScanConvMode = DISABLE;	
+        ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
+        ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
+        ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;	
+        ADC_InitStructure.ADC_NbrOfConversion = 1;
+        ADC_Init(ADC2, &ADC_InitStructure);
+
+        ADC_Cmd(ADC2, ENABLE);	
+    }
+#endif
+
+#ifdef BSP_USING_ADC3
+    if (0 == strncmp(adc_dev->haldev.dev_name, ADC3_DEVICE_NAME, NAME_NUM_MAX)) {
+
+        GPIOx = AdcGetGpioType(ADC3_GPIO_DEF);
+        RCC_AHB1Periph = AdcGetGpioRcc(ADC3_GPIO_DEF);
+
+        RCC_AHB1PeriphClockCmd(RCC_AHB1Periph, ENABLE);//enable GPIOA clock
+        RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC3, ENABLE);//enable ADC3 clock
+
+        GPIO_InitStructure.GPIO_Pin = ADC3_GPIO;
+        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;//analog input
+        GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+        GPIO_Init(GPIOx, &GPIO_InitStructure);
+
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE);	 
+
+        ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent;
+        ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles;
+        ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
+        ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div4;
+        ADC_CommonInit(&ADC_CommonInitStructure);
+
+        ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b;//12 bit mode
+        ADC_InitStructure.ADC_ScanConvMode = DISABLE;	
+        ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
+        ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
+        ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;	
+        ADC_InitStructure.ADC_NbrOfConversion = 1;
+        ADC_Init(ADC3, &ADC_InitStructure);
+
+        ADC_Cmd(ADC3, ENABLE);	
+    }
+#endif
+}				  
+
+static uint16 GetAdcValue(ADC_TypeDef *ADCx, uint8 channel)   
+{
+    //set ADCx channel, rank, sampletime
+	ADC_RegularChannelConfig(ADCx, channel, 1, ADC_SampleTime_480Cycles);			    
+  
+	ADC_SoftwareStartConv(ADCx);
+	 
+	while(!ADC_GetFlagStatus(ADCx, ADC_FLAG_EOC));
+
+	return ADC_GetConversionValue(ADCx);
+}
+
+static uint16 GetAdcAverageValue(ADC_TypeDef *ADCx, uint8 channel, uint8 times)
+{
+	uint32 temp_val = 0;
+	int i;
+
+	for(i = 0;i < times;i ++) {
+		temp_val += GetAdcValue(ADCx, channel) & 0x0FFF;
+        KPrintf("GetAdcAverageValue val %u\n", GetAdcValue(ADCx, channel));
+		Stm32AdcUdelay(5000);
+	}
+	return temp_val / times;
+} 
+
+static uint32 Stm32AdcOpen(void *dev)
+{
+    struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)dev;
+    
+    AdcInit(adc_dev);
+
+    return EOK;
+}
+
+static uint32 Stm32AdcClose(void *dev)
+{
+    struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)dev;
+    
+    ADC_DeInit();
+
+    return EOK;
+}
+
+static uint32 Stm32AdcRead(void *dev, struct BusBlockReadParam *read_param)
+{
+    struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)dev;
+    struct Stm32HwAdc *adc_cfg = (struct Stm32HwAdc *)adc_dev->haldev.private_data;
+
+    uint16 adc_average_value = 0;
+    uint8 times = 20;
+
+    adc_average_value = GetAdcAverageValue(adc_cfg->ADCx, adc_cfg->adc_channel, times);
+
+   *(uint16 *)read_param->buffer = adc_average_value;
+   read_param->read_length = 2;
+
+   return read_param->read_length;
+}
+
+static uint32 Stm32AdcDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(drv);
+    NULL_PARAM_CHECK(configure_info);
+
+    x_err_t ret = EOK;
+    uint8 adc_channel;
+
+    struct AdcDriver *adc_drv = (struct AdcDriver *)drv;
+    struct AdcHardwareDevice *adc_dev = (struct AdcHardwareDevice *)adc_drv->driver.owner_bus->owner_haldev;
+    struct Stm32HwAdc *adc_cfg = (struct Stm32HwAdc *)adc_dev->haldev.private_data;
+
+    switch (configure_info->configure_cmd)
+    {
+        case OPE_CFG:
+            adc_cfg->adc_channel = *(uint8 *)configure_info->private_data;
+            if (adc_cfg->adc_channel > 18) {
+                KPrintf("Stm32AdcDrvConfigure set adc channel(0-18) %u error!", adc_cfg->adc_channel);
+                adc_cfg->adc_channel = 0;
+                ret = ERROR;
+            }
+            break;
+        default:
+            break;
+    }
+
+    return ret;
+}
+
+static const struct AdcDevDone dev_done =
+{
+    Stm32AdcOpen,
+    Stm32AdcClose,
+    NONE,
+    Stm32AdcRead,
+};
+
+int Stm32HwAdcInit(void)
+{
+    x_err_t ret = EOK;
+
+#ifdef BSP_USING_ADC1
+    static struct AdcBus adc1_bus;
+    static struct AdcDriver adc1_drv;
+    static struct AdcHardwareDevice adc1_dev;
+    static struct Stm32HwAdc adc1_cfg;
+
+    adc1_drv.configure = Stm32AdcDrvConfigure;
+
+    ret = AdcBusInit(&adc1_bus, ADC1_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("ADC1 bus init error %d\n", ret);
+        return ERROR;
+    }
+
+    ret = AdcDriverInit(&adc1_drv, ADC1_DRIVER_NAME);
+    if (ret != EOK) {
+        KPrintf("ADC1 driver init error %d\n", ret);
+        return ERROR;
+    }
+    ret = AdcDriverAttachToBus(ADC1_DRIVER_NAME, ADC1_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("ADC1 driver attach error %d\n", ret);
+        return ERROR;
+    }
+
+    adc1_dev.adc_dev_done = &dev_done;
+    adc1_cfg.ADCx = ADC1;
+    adc1_cfg.adc_channel = 0;
+
+    ret = AdcDeviceRegister(&adc1_dev, (void *)&adc1_cfg, ADC1_DEVICE_NAME);
+    if (ret != EOK) {
+        KPrintf("ADC1 device register error %d\n", ret);
+        return ERROR;
+    }
+    ret = AdcDeviceAttachToBus(ADC1_DEVICE_NAME, ADC1_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("ADC1 device register error %d\n", ret);
+        return ERROR;
+    }
+#endif 
+
+#ifdef BSP_USING_ADC2
+    static struct AdcBus adc2_bus;
+    static struct AdcDriver adc2_drv;
+    static struct AdcHardwareDevice adc2_dev;
+    static struct Stm32HwAdc adc2_cfg;
+
+    adc2_drv.configure = Stm32AdcDrvConfigure;
+
+    ret = AdcBusInit(&adc2_bus, ADC2_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("ADC2 bus init error %d\n", ret);
+        return ERROR;
+    }
+
+    ret = AdcDriverInit(&adc2_drv, ADC2_DRIVER_NAME);
+    if (ret != EOK) {
+        KPrintf("ADC2 driver init error %d\n", ret);
+        return ERROR;
+    }
+    ret = AdcDriverAttachToBus(ADC2_DRIVER_NAME, ADC2_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("ADC2 driver attach error %d\n", ret);
+        return ERROR;
+    }
+
+    adc2_dev.adc_dev_done = &dev_done;
+    adc2_cfg.ADCx = ADC2;
+    adc2_cfg.adc_channel = 0;
+
+    ret = AdcDeviceRegister(&adc2_dev, (void *)&adc2_cfg, ADC2_DEVICE_NAME);
+    if (ret != EOK) {
+        KPrintf("ADC2 device register error %d\n", ret);
+        return ERROR;
+    }
+    ret = AdcDeviceAttachToBus(ADC2_DEVICE_NAME, ADC2_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("ADC2 device register error %d\n", ret);
+        return ERROR;
+    }
+#endif 
+
+#ifdef BSP_USING_ADC3
+    static struct AdcBus adc3_bus;
+    static struct AdcDriver adc3_drv;
+    static struct AdcHardwareDevice adc3_dev;
+    static struct Stm32HwAdc adc3_cfg;
+
+    adc3_drv.configure = Stm32AdcDrvConfigure;
+
+    ret = AdcBusInit(&adc3_bus, ADC3_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("ADC3 bus init error %d\n", ret);
+        return ERROR;
+    }
+
+    ret = AdcDriverInit(&adc3_drv, ADC3_DRIVER_NAME);
+    if (ret != EOK) {
+        KPrintf("ADC3 driver init error %d\n", ret);
+        return ERROR;
+    }
+    ret = AdcDriverAttachToBus(ADC3_DRIVER_NAME, ADC3_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("ADC3 driver attach error %d\n", ret);
+        return ERROR;
+    }
+
+    adc3_dev.adc_dev_done = &dev_done;
+    adc3_cfg.ADCx = ADC3;
+    adc3_cfg.adc_channel = 0;
+
+    ret = AdcDeviceRegister(&adc3_dev, (void *)&adc3_cfg, ADC3_DEVICE_NAME);
+    if (ret != EOK) {
+        KPrintf("ADC3 device register error %d\n", ret);
+        return ERROR;
+    }
+    ret = AdcDeviceAttachToBus(ADC3_DEVICE_NAME, ADC3_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("ADC3 device register error %d\n", ret);
+        return ERROR;
+    }
+#endif 
+
+    return ret;
+}

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/can/Kconfig

@@ -0,0 +1,11 @@
+config CAN_BUS_NAME_1
+    string "can bus name"
+    default "can1"
+
+config CAN_DRIVER_NAME
+    string "can driver name"
+    default "can1_drv"
+
+config CAN_1_DEVICE_NAME_1
+    string "can bus 1 device 1 name"
+    default "can1_dev1"

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/can/Makefile

@@ -0,0 +1,4 @@
+SRC_FILES := hardware_can.c  connect_can.c
+
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/can/connect_can.c

@@ -0,0 +1,275 @@
+/*
+ * Copyright (c) Guangzhou Xingyi Electronic  Technology Co., Ltd
+ *
+ * Change Logs:
+ * Date               Author       Notes
+ * 2014-7-4      alientek   first version
+ */
+
+/**
+* @file connect_can.c
+* @brief support aiit-arm32-board can function and register to bus framework
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-22
+*/
+
+/*************************************************
+File name: connect_can.c
+Description: support can configure and spi bus register function
+Others: hardware/can/can.c for references
+History: 
+1. Date: 2021-04-22
+Author: AIIT XUOS Lab
+Modification: 
+1. support aiit-arm32-board can configure, write and read
+2. support aiit-arm32-board can bus device and driver register
+*************************************************/
+
+#include <connect_can.h>
+#include <hardware_gpio.h>
+#include <hardware_rcc.h>
+#include <misc.h>
+
+static struct CanSendConfigure   can_send_deconfig = 
+{
+    .stdid = 0x12,
+    .exdid = 0x12,
+    .ide = 0 ,
+    .rtr = 0,
+    .data_lenth = 8
+};
+
+static void CanGPIOInit(void)
+{
+    CAN_FilterInitTypeDef  can1_filter;
+    GPIO_InitTypeDef           gpio_initstructure;
+    CAN_InitTypeDef             can_initstruction;
+ 
+    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);
+    RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE);
+
+    gpio_initstructure.GPIO_Pin = GPIO_Pin_9 | GPIO_Pin_8;
+    gpio_initstructure.GPIO_Mode = GPIO_Mode_AF;
+    gpio_initstructure.GPIO_OType = GPIO_OType_PP;
+    gpio_initstructure.GPIO_Speed = GPIO_Speed_100MHz;
+    gpio_initstructure.GPIO_PuPd = GPIO_PuPd_UP;
+    GPIO_Init(GPIOB, &gpio_initstructure);
+
+    GPIO_PinAFConfig(GPIOB, GPIO_PinSource9, GPIO_AF_CAN1);
+    GPIO_PinAFConfig(GPIOB, GPIO_PinSource8, GPIO_AF_CAN1);
+}
+
+static void Can1NvicConfig(void)
+{
+    NVIC_InitTypeDef can_nvic_config;
+
+    can_nvic_config.NVIC_IRQChannel = CAN1_RX0_IRQn;
+    can_nvic_config.NVIC_IRQChannelPreemptionPriority = 2;
+    can_nvic_config.NVIC_IRQChannelSubPriority = 2;
+    can_nvic_config.NVIC_IRQChannelCmd = ENABLE;
+    CAN_ITConfig(CAN1, CAN_IT_FMP0, ENABLE);
+    NVIC_Init(&can_nvic_config);
+}
+
+static uint32 CanModeInit(void *drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(drv);
+    NULL_PARAM_CHECK(configure_info);
+    CAN_FilterInitTypeDef can1_filter;
+    CAN_InitTypeDef     can_initstruction;
+
+    struct CanDriverConfigure  *config  = ( struct CanDriverConfigure  *)configure_info->private_data;
+
+    can_initstruction.CAN_TTCM  = DISABLE;
+    can_initstruction.CAN_ABOM = DISABLE;
+    can_initstruction.CAN_AWUM = DISABLE;
+    can_initstruction.CAN_NART   = ENABLE;
+    can_initstruction.CAN_TXFP    = DISABLE;
+    can_initstruction.CAN_Mode   = config->mode;
+    can_initstruction.CAN_RFLM   = DISABLE;
+    can_initstruction.CAN_SJW      = config->tsjw;
+    can_initstruction.CAN_BS1       = config->tbs1;
+    can_initstruction.CAN_BS2       = config->tbs2;
+    can_initstruction.CAN_Prescaler  = config->brp;
+    
+    CAN_Init(CAN1, &can_initstruction);
+
+    can1_filter.CAN_FilterNumber=0;
+    can1_filter.CAN_FilterMode=CAN_FilterMode_IdMask;
+    can1_filter.CAN_FilterScale=CAN_FilterScale_32bit;
+    can1_filter.CAN_FilterIdHigh=0x0000;
+    can1_filter.CAN_FilterIdLow=0x0000;
+    can1_filter.CAN_FilterMaskIdHigh=0x0000;
+    can1_filter.CAN_FilterMaskIdLow=0x0000;
+    can1_filter.CAN_FilterFIFOAssignment=CAN_Filter_FIFO0;
+    can1_filter.CAN_FilterActivation=ENABLE;
+    CAN_FilterInit(&can1_filter);
+
+    #ifdef  CAN_USING_INTERRUPT
+       Can1NvicConfig();
+    #endif
+
+    return 0;
+}
+
+static uint32 CanSendMsg(void * dev , struct BusBlockWriteParam *write_param )
+{
+    NULL_PARAM_CHECK(write_param);
+
+    uint8  *data   = (uint8  * ) write_param->buffer;
+    u8  messege_box;
+    u16  i = 0;
+    u16  timer_count = 1000;
+    CanTxMsg  tx_data;
+    tx_data.StdId  = 0x55;
+    tx_data.ExtId   = 0x00;
+    tx_data.IDE      =  0;
+    tx_data.RTR     =  0;
+    tx_data.DLC     =  write_param->size;
+
+    for(i = 0;i < tx_data.DLC;i ++) {
+        tx_data.Data[i] = data[i];
+    }
+
+    messege_box = CAN_Transmit(CAN1,&tx_data);
+
+    while (CAN_TransmitStatus(CAN1,messege_box)==  CAN_TxStatus_Failed &&timer_count) {
+        timer_count--;
+    }
+
+    if (timer_count<=0) {
+        return ERROR;
+    }
+    return EOK;
+}
+
+static uint32 CanRecvMsg(void *dev , struct BusBlockReadParam *databuf)
+{
+    NULL_PARAM_CHECK(dev);
+    int  i;
+    uint8  * buf  = (uint8 *)databuf->buffer;
+    CanRxMsg msg;
+    if (CAN_MessagePending(CAN1, CAN_FIFO0) == 0)
+        return 0;
+    CAN_Receive(CAN1, CAN_FIFO0, &msg);
+    for(i = 0 ;i < msg.DLC;i ++)
+         buf[i] = msg.Data[i];
+    databuf->size  =  msg.DLC ; 
+
+    return msg.DLC;
+}
+
+static struct CanDevDone dev_done = 
+{
+    .open  = NONE,
+    .close  = NONE,
+    .write  = CanSendMsg,
+    .read   = CanRecvMsg
+};
+
+static struct CanHardwareDevice dev;
+
+#ifdef  CAN_USING_INTERRUPT
+void CAN1_RX0_IRQHandler(void)
+{
+    CanRxMsg   rxmsg;
+    int i = 0;
+    CAN_Receive(CAN1, 0, &rxmsg);
+    for (i = 0;i < 8;i ++)
+          KPrintf("rxbuf [%d] = :%d",i,rxmsg.Data[i]);
+}
+DECLARE_HW_IRQ(CAN1_RX0_IRQn, CAN1_RX0_IRQHandler, NONE);
+#endif
+
+static int BoardCanBusInit(struct Stm32Can *stm32can_bus, struct CanDriver *can_driver)
+{
+    x_err_t ret = EOK;
+
+    /*Init the can bus */
+    ret = CanBusInit(&stm32can_bus->can_bus, stm32can_bus->bus_name);
+    if (EOK != ret) {
+        KPrintf("Board_can_init canBusInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Init the can driver*/
+    ret = CanDriverInit(can_driver, CAN_DRIVER_NAME);
+    if (EOK != ret) {
+        KPrintf("Board_can_init canDriverInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Attach the can driver to the can bus*/
+    ret = CanDriverAttachToBus(CAN_DRIVER_NAME, stm32can_bus->bus_name);
+    if (EOK != ret) {
+        KPrintf("Board_can_init CanDriverAttachToBus error %d\n", ret);
+        return ERROR;
+    } 
+
+    return ret;
+}
+
+static x_err_t HwCanDeviceAttach(const char *bus_name, const char *device_name)
+{
+    NULL_PARAM_CHECK(bus_name);
+    NULL_PARAM_CHECK(device_name);
+
+    x_err_t result;
+    struct CanHardwareDevice *can_device;
+
+    /* attach the device to can bus*/
+    can_device = (struct CanHardwareDevice *)x_malloc(sizeof(struct CanHardwareDevice));
+    CHECK(can_device);
+    memset(can_device, 0, sizeof(struct CanHardwareDevice));
+    can_device->dev_done = &dev_done;
+
+     result = CanDeviceRegister(can_device, NONE, device_name);
+    if (EOK != result) {
+        KPrintf("board_can_init canDeviceInit device %s error %d\n", "can1", result);
+        return ERROR;
+    }  
+
+    result = CanDeviceAttachToBus(device_name, bus_name);
+    if (result != EOK) {
+        SYS_ERR("%s attach to %s faild, %d\n", device_name, bus_name, result);
+    }
+
+    CHECK(result == EOK);
+
+    KPrintf("%s attach to %s done\n", device_name, bus_name);
+
+    return result;
+}
+
+struct Stm32Can  can1;
+
+ int Stm32HwCanBusInit(void)
+{
+    x_err_t ret = EOK;
+    struct Stm32Can *stm32_can_bus;
+
+    static struct CanDriver can_driver;
+    memset(&can_driver, 0, sizeof(struct CanDriver));
+    can_driver.configure = CanModeInit;
+
+    CanGPIOInit();
+    stm32_can_bus = &can1;
+    stm32_can_bus->instance = CAN1;
+    stm32_can_bus->bus_name = CAN_BUS_NAME_1;
+    stm32_can_bus->can_bus.private_data = &can1;
+    
+    ret = BoardCanBusInit(stm32_can_bus, &can_driver);
+   
+    if (EOK != ret) {
+      KPrintf(" can_bus_init %s error ret %u\n", stm32_can_bus->bus_name, ret);
+      return ERROR;
+    }
+
+     ret  =  HwCanDeviceAttach(CAN_BUS_NAME_1,CAN_1_DEVICE_NAME_1);  
+    if (EOK != ret) {
+      KPrintf(" HwCanDeviceAttach %s error ret %u\n", stm32_can_bus->bus_name, ret);
+      return ERROR;
+    }
+    return EOK;
+}

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/ch438/Kconfig

@@ -0,0 +1,39 @@
+config CH438_BUS_NAME
+    string
+    default "extuart"
+
+config CH438_DRIVER_NAME
+    string
+    default "extuart_drv"
+
+config CH438_DEVICE_NAME_0
+    string
+    default "extuart_dev0"
+
+config CH438_DEVICE_NAME_1
+    string
+    default "extuart_dev1"
+
+config CH438_DEVICE_NAME_2
+    string
+    default "extuart_dev2"
+
+config CH438_DEVICE_NAME_3
+    string
+    default "extuart_dev3"
+
+config CH438_DEVICE_NAME_4
+    string
+    default "extuart_dev4"
+
+config CH438_DEVICE_NAME_5
+    string
+    default "extuart_dev5"
+
+config CH438_DEVICE_NAME_6
+    string
+    default "extuart_dev6"
+
+config CH438_DEVICE_NAME_7
+    string
+    default "extuart_dev7"

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/ch438/Makefile

@@ -0,0 +1,4 @@
+SRC_FILES := connect_ch438.c
+
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/common/Makefile

@@ -0,0 +1,9 @@
+SRC_FILES := misc.c  hardware_rcc.c hardware_exti.c \
+	hardware_it.c hardware_pwr.c hardware_syscfg.c hardware_fsmc.c\
+	
+
+ifeq ($(CONFIG_BSP_USING_DMA),y)
+  SRC_FILES +=  hardware_dma.c
+endif
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/common/hardware_exti.c

@@ -0,0 +1,326 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_exti.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    30-September-2011
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the EXTI peripheral:           
+  *           - Initialization and Configuration
+  *           - Interrupts and flags management
+  *
+  *  @verbatim  
+  *  
+  *          ===================================================================
+  *                                     EXTI features
+  *          ===================================================================
+  *    
+  *          External interrupt/event lines are mapped as following:
+  *            1- All available GPIO pins are connected to the 16 external 
+  *               interrupt/event lines from EXTI0 to EXTI15.
+  *            2- EXTI line 16 is connected to the PVD Output
+  *            3- EXTI line 17 is connected to the RTC Alarm event
+  *            4- EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event                                    
+  *            5- EXTI line 19 is connected to the Ethernet Wakeup event
+  *            6- EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event 
+  *            7- EXTI line 21 is connected to the RTC Tamper and Time Stamp events                                               
+  *            8- EXTI line 22 is connected to the RTC Wakeup event
+  *        
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================  
+  *              
+  *          In order to use an I/O pin as an external interrupt source, follow
+  *          steps below:
+  *            1- Configure the I/O in input mode using GPIO_Init()
+  *            2- Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig()
+  *            3- Select the mode(interrupt, event) and configure the trigger 
+  *               selection (Rising, falling or both) using EXTI_Init()
+  *            4- Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init()
+  *   
+  *  @note  SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
+  *         registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+  *          
+  *  @endverbatim                  
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/**
+* @file: hardware_exti.c
+* @brief: support hardware exti function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/*************************************************
+File name: hardware_exti.c
+Description: support hardware exti function
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_exti.c for XiZi
+*************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include <hardware_exti.h>
+#include <stm32_assert_template.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup EXTI 
+  * @brief EXTI driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+#define EXTI_LINENONE    ((uint32_t)0x00000)  /* No interrupt selected */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup EXTI_Private_Functions
+  * @{
+  */
+
+/** @defgroup EXTI_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                  Initialization and Configuration functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the EXTI peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void EXTI_DeInit(void)
+{
+  EXTI->IMR = 0x00000000;
+  EXTI->EMR = 0x00000000;
+  EXTI->RTSR = 0x00000000;
+  EXTI->FTSR = 0x00000000;
+  EXTI->PR = 0x007FFFFF;
+}
+
+/**
+  * @brief  Initializes the EXTI peripheral according to the specified
+  *         parameters in the EXTI_InitStruct.
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
+  *         that contains the configuration information for the EXTI peripheral.
+  * @retval None
+  */
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+  uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
+  assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
+  assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));  
+  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
+
+  tmp = (uint32_t)EXTI_BASE;
+     
+  if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+  {
+    /* Clear EXTI line configuration */
+    EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
+    EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
+    
+    tmp += EXTI_InitStruct->EXTI_Mode;
+
+    *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+
+    /* Clear Rising Falling edge configuration */
+    EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
+    EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
+    
+    /* Select the trigger for the selected external interrupts */
+    if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+    {
+      /* Rising Falling edge */
+      EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
+      EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
+    }
+    else
+    {
+      tmp = (uint32_t)EXTI_BASE;
+      tmp += EXTI_InitStruct->EXTI_Trigger;
+
+      *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+    }
+  }
+  else
+  {
+    tmp += EXTI_InitStruct->EXTI_Mode;
+
+    /* Disable the selected external lines */
+    *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
+  }
+}
+
+/**
+  * @brief  Fills each EXTI_InitStruct member with its reset value.
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+  EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
+  EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+  EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+  EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/**
+  * @brief  Generates a Software interrupt on selected EXTI line.
+  * @param  EXTI_Line: specifies the EXTI line on which the software interrupt
+  *         will be generated.
+  *         This parameter can be any combination of EXTI_Linex where x can be (0..22)
+  * @retval None
+  */
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+  
+  EXTI->SWIER |= EXTI_Line;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Group2 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim   
+ ===============================================================================
+                  Interrupts and flags management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the specified EXTI line flag is set or not.
+  * @param  EXTI_Line: specifies the EXTI line flag to check.
+  *          This parameter can be EXTI_Linex where x can be(0..22)
+  * @retval The new state of EXTI_Line (SET or RESET).
+  */
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+  
+  if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the EXTI's line pending flags.
+  * @param  EXTI_Line: specifies the EXTI lines flags to clear.
+  *          This parameter can be any combination of EXTI_Linex where x can be (0..22)
+  * @retval None
+  */
+void EXTI_ClearFlag(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+  
+  EXTI->PR = EXTI_Line;
+}
+
+/**
+  * @brief  Checks whether the specified EXTI line is asserted or not.
+  * @param  EXTI_Line: specifies the EXTI line to check.
+  *          This parameter can be EXTI_Linex where x can be(0..22)
+  * @retval The new state of EXTI_Line (SET or RESET).
+  */
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+  /* Check the parameters */
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+  
+  enablestatus =  EXTI->IMR & EXTI_Line;
+  if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the EXTI's line pending bits.
+  * @param  EXTI_Line: specifies the EXTI lines to clear.
+  *          This parameter can be any combination of EXTI_Linex where x can be (0..22)
+  * @retval None
+  */
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+  
+  EXTI->PR = EXTI_Line;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/common/hardware_it.c

@@ -0,0 +1,137 @@
+/**
+  ******************************************************************************
+  * @file    IO_Toggle/stm32f4xx_it.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    19-September-2011
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/**
+* @file: hardware_it.c
+* @brief: support hardware it function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/*************************************************
+File name: hardware_it.c
+Description: support hardware it function
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_it.c for XiZi
+*************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include <board.h>
+#include <stm32f4xx.h>
+#include <xizi.h>
+
+/** @addtogroup STM32F4_Discovery_Peripheral_Examples
+  * @{
+  */
+
+/** @addtogroup IO_Toggle
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/*            Cortex-M4 Processor Exceptions Handlers                         */
+/******************************************************************************/
+
+/**
+  * @brief   This function handles NMI exception.
+  * @param  None
+  * @retval None
+  */
+void NMI_Handler(int irqn, void *arg)
+{
+}
+DECLARE_HW_IRQ(NonMaskableInt_IRQn, NMI_Handler, NONE);
+
+/**
+  * @brief  This function handles Memory Manage exception.
+  * @param  None
+  * @retval None
+  */
+void MemManage_Handler(int irqn, void *arg)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {
+  }
+}
+DECLARE_HW_IRQ(MemoryManagement_IRQn, MemManage_Handler, NONE);
+
+/**
+  * @brief  This function handles Bus Fault exception.
+  * @param  None
+  * @retval None
+  */
+void BusFault_Handler(int irqn, void *arg)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+DECLARE_HW_IRQ(BusFault_IRQn, BusFault_Handler, NONE);
+
+/**
+  * @brief  This function handles Usage Fault exception.
+  * @param  None
+  * @retval None
+  */
+void UsageFault_Handler(int irqn, void *arg)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+DECLARE_HW_IRQ(UsageFault_IRQn, UsageFault_Handler, NONE);
+
+/**
+  * @brief  This function handles SVCall exception.
+  * @param  None
+  * @retval None
+  */
+void SVC_Handler(int irqn, void *arg)
+{
+}
+DECLARE_HW_IRQ(SVCall_IRQn, SVC_Handler, NONE);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/common/hardware_pwr.c

@@ -0,0 +1,673 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_pwr.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    30-September-2011
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Power Controller (PWR) peripheral:           
+  *           - Backup Domain Access
+  *           - PVD configuration
+  *           - WakeUp pin configuration
+  *           - Main and Backup Regulators configuration
+  *           - FLASH Power Down configuration
+  *           - Low Power modes configuration
+  *           - Flags management
+  *               
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/**
+* @file: hardware_pwr.c
+* @brief: support hardware pwr function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/*************************************************
+File name: hardware_pwr.c
+Description: support hardware pwr function
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_pwr.c for XiZi
+*************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include <hardware_pwr.h>
+#include <hardware_rcc.h>
+#include <stm32_assert_template.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup PWR 
+  * @brief PWR driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* --------- PWR registers bit address in the alias region ---------- */
+#define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+
+/* Alias word address of DBP bit */
+#define CR_OFFSET                (PWR_OFFSET + 0x00)
+#define DBP_BitNumber            0x08
+#define CR_DBP_BB                (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BitNumber           0x04
+#define CR_PVDE_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
+
+/* Alias word address of FPDS bit */
+#define FPDS_BitNumber           0x09
+#define CR_FPDS_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4))
+
+/* Alias word address of PMODE bit */
+#define PMODE_BitNumber           0x0E
+#define CR_PMODE_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))
+
+
+/* --- CSR Register ---*/
+
+/* Alias word address of EWUP bit */
+#define CSR_OFFSET               (PWR_OFFSET + 0x04)
+#define EWUP_BitNumber           0x08
+#define CSR_EWUP_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
+
+/* Alias word address of BRE bit */
+#define BRE_BitNumber            0x09
+#define CSR_BRE_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
+
+/* ------------------ PWR registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CR_DS_MASK               ((uint32_t)0xFFFFFFFC)
+#define CR_PLS_MASK              ((uint32_t)0xFFFFFF1F)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup PWR_Private_Functions
+  * @{
+  */
+
+/** @defgroup PWR_Group1 Backup Domain Access function 
+ *  @brief   Backup Domain Access function  
+ *
+@verbatim   
+ ===============================================================================
+                            Backup Domain Access function 
+ ===============================================================================  
+
+  After reset, the backup domain (RTC registers, RTC backup data 
+  registers and backup SRAM) is protected against possible unwanted 
+  write accesses. 
+  To enable access to the RTC Domain and RTC registers, proceed as follows:
+    - Enable the Power Controller (PWR) APB1 interface clock using the
+      RCC_APB1PeriphClockCmd() function.
+    - Enable access to RTC domain using the PWR_BackupAccessCmd() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the PWR peripheral registers to their default reset values.     
+  * @param  None
+  * @retval None
+  */
+void PWR_DeInit(void)
+{
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
+}
+
+/**
+  * @brief  Enables or disables access to the backup domain (RTC registers, RTC 
+  *         backup data registers and backup SRAM).
+  * @note   If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 
+  *         Backup Domain Access should be kept enabled.
+  * @param  NewState: new state of the access to the backup domain.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_BackupAccessCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group2 PVD configuration functions
+ *  @brief   PVD configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                           PVD configuration functions
+ ===============================================================================  
+
+ - The PVD is used to monitor the VDD power supply by comparing it to a threshold
+   selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
+ - A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the 
+   PVD threshold. This event is internally connected to the EXTI line16
+   and can generate an interrupt if enabled through the EXTI registers.
+ - The PVD is stopped in Standby mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+  * @param  PWR_PVDLevel: specifies the PVD detection level
+  *          This parameter can be one of the following values:
+  *            @arg PWR_PVDLevel_0: PVD detection level set to 2.0V
+  *            @arg PWR_PVDLevel_1: PVD detection level set to 2.2V
+  *            @arg PWR_PVDLevel_2: PVD detection level set to 2.3V
+  *            @arg PWR_PVDLevel_3: PVD detection level set to 2.5V
+  *            @arg PWR_PVDLevel_4: PVD detection level set to 2.7V
+  *            @arg PWR_PVDLevel_5: PVD detection level set to 2.8V
+  *            @arg PWR_PVDLevel_6: PVD detection level set to 2.9V
+  *            @arg PWR_PVDLevel_7: PVD detection level set to 3.0V
+  * @note   Refer to the electrical characteristics of you device datasheet for more details. 
+  * @retval None
+  */
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
+  
+  tmpreg = PWR->CR;
+  
+  /* Clear PLS[7:5] bits */
+  tmpreg &= CR_PLS_MASK;
+  
+  /* Set PLS[7:5] bits according to PWR_PVDLevel value */
+  tmpreg |= PWR_PVDLevel;
+  
+  /* Store the new value */
+  PWR->CR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the Power Voltage Detector(PVD).
+  * @param  NewState: new state of the PVD.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_PVDCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group3 WakeUp pin configuration functions
+ *  @brief   WakeUp pin configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                    WakeUp pin configuration functions
+ ===============================================================================  
+
+ - WakeUp pin is used to wakeup the system from Standby mode. This pin is 
+   forced in input pull down configuration and is active on rising edges.
+ - There is only one WakeUp pin: WakeUp Pin 1 on PA.00.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the WakeUp Pin functionality.
+  * @param  NewState: new state of the WakeUp Pin functionality.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_WakeUpPinCmd(FunctionalState NewState)
+{
+  /* Check the parameters */  
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group4 Main and Backup Regulators configuration functions
+ *  @brief   Main and Backup Regulators configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                    Main and Backup Regulators configuration functions
+ ===============================================================================  
+
+ - The backup domain includes 4 Kbytes of backup SRAM accessible only from the 
+   CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is retained 
+   even in Standby or VBAT mode when the low power backup regulator is enabled. 
+   It can be considered as an internal EEPROM when VBAT is always present.
+   You can use the PWR_BackupRegulatorCmd() function to enable the low power
+   backup regulator and use the PWR_GetFlagStatus(PWR_FLAG_BRR) to check if it is
+   ready or not. 
+
+ - When the backup domain is supplied by VDD (analog switch connected to VDD) 
+   the backup SRAM is powered from VDD which replaces the VBAT power supply to 
+   save battery life.
+
+ - The backup SRAM is not mass erased by an tamper event. It is read protected 
+   to prevent confidential data, such as cryptographic private key, from being 
+   accessed. The backup SRAM can be erased only through the Flash interface when
+   a protection level change from level 1 to level 0 is requested. 
+   Refer to the description of Read protection (RDP) in the Flash programming manual.
+
+ - The main internal regulator can be configured to have a tradeoff between performance
+   and power consumption when the device does not operate at the maximum frequency. 
+   This is done through PWR_MainRegulatorModeConfig() function which configure VOS bit
+   in PWR_CR register: 
+      - When this bit is set (Regulator voltage output Scale 1 mode selected) the System
+        frequency can go up to 168 MHz. 
+      - When this bit is reset (Regulator voltage output Scale 2 mode selected) the System
+        frequency can go up to 144 MHz. 
+   Refer to the datasheets for more details.
+           
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the Backup Regulator.
+  * @param  NewState: new state of the Backup Regulator.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_BackupRegulatorCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Configures the main internal regulator output voltage.
+  * @param  PWR_Regulator_Voltage: specifies the regulator output voltage to achieve
+  *         a tradeoff between performance and power consumption when the device does
+  *         not operate at the maximum frequency (refer to the datasheets for more details).
+  *          This parameter can be one of the following values:
+  *            @arg PWR_Regulator_Voltage_Scale1: Regulator voltage output Scale 1 mode, 
+  *                                                System frequency up to 168 MHz. 
+  *            @arg PWR_Regulator_Voltage_Scale2: Regulator voltage output Scale 2 mode, 
+  *                                                System frequency up to 144 MHz.    
+  * @retval None
+  */
+void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR_VOLTAGE(PWR_Regulator_Voltage));
+
+  if (PWR_Regulator_Voltage == PWR_Regulator_Voltage_Scale2)
+  {
+    PWR->CR &= ~PWR_Regulator_Voltage_Scale1;
+  }
+  else
+  {    
+    PWR->CR |= PWR_Regulator_Voltage_Scale1;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group5 FLASH Power Down configuration functions
+ *  @brief   FLASH Power Down configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+           FLASH Power Down configuration functions
+ ===============================================================================  
+
+ - By setting the FPDS bit in the PWR_CR register by using the PWR_FlashPowerDownCmd()
+   function, the Flash memory also enters power down mode when the device enters 
+   Stop mode. When the Flash memory is in power down mode, an additional startup 
+   delay is incurred when waking up from Stop mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the Flash Power Down in STOP mode.
+  * @param  NewState: new state of the Flash power mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_FlashPowerDownCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group6 Low Power modes configuration functions
+ *  @brief   Low Power modes configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                    Low Power modes configuration functions
+ ===============================================================================  
+
+  The devices feature 3 low-power modes:
+   - Sleep mode: Cortex-M4 core stopped, peripherals kept running.
+   - Stop mode: all clocks are stopped, regulator running, regulator in low power mode
+   - Standby mode: 1.2V domain powered off.
+   
+   Sleep mode
+   ===========
+    - Entry:
+      - The Sleep mode is entered by using the __WFI() or __WFE() functions.
+    - Exit:
+      - Any peripheral interrupt acknowledged by the nested vectored interrupt 
+        controller (NVIC) can wake up the device from Sleep mode.
+
+   Stop mode
+   ==========
+   In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
+   and the HSE RC oscillators are disabled. Internal SRAM and register contents 
+   are preserved.
+   The voltage regulator can be configured either in normal or low-power mode.
+   To minimize the consumption In Stop mode, FLASH can be powered off before 
+   entering the Stop mode. It can be switched on again by software after exiting 
+   the Stop mode using the PWR_FlashPowerDownCmd() function. 
+   
+    - Entry:
+      - The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) 
+        function with regulator in LowPower or with Regulator ON.
+    - Exit:
+      - Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
+      
+   Standby mode
+   ============
+   The Standby mode allows to achieve the lowest power consumption. It is based 
+   on the Cortex-M4 deepsleep mode, with the voltage regulator disabled. 
+   The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and 
+   the HSE oscillator are also switched off. SRAM and register contents are lost 
+   except for the RTC registers, RTC backup registers, backup SRAM and Standby 
+   circuitry.
+   
+   The voltage regulator is OFF.
+      
+    - Entry:
+      - The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
+    - Exit:
+      - WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
+        tamper event, time-stamp event, external reset in NRST pin, IWDG reset.              
+
+   Auto-wakeup (AWU) from low-power mode
+   =====================================
+   The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC 
+   Wakeup event, a tamper event, a time-stamp event, or a comparator event, 
+   without depending on an external interrupt (Auto-wakeup mode).
+
+   - RTC auto-wakeup (AWU) from the Stop mode
+     ----------------------------------------
+     
+     - To wake up from the Stop mode with an RTC alarm event, it is necessary to:
+       - Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt 
+         or Event modes) using the EXTI_Init() function.
+       - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
+       - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() 
+         and RTC_AlarmCmd() functions.
+     - To wake up from the Stop mode with an RTC Tamper or time stamp event, it 
+       is necessary to:
+       - Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt 
+         or Event modes) using the EXTI_Init() function.
+       - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() 
+         function
+       - Configure the RTC to detect the tamper or time stamp event using the
+         RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
+         functions.
+     - To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
+       - Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt 
+         or Event modes) using the EXTI_Init() function.
+       - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
+       - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), 
+         RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
+
+   - RTC auto-wakeup (AWU) from the Standby mode
+     -------------------------------------------
+     - To wake up from the Standby mode with an RTC alarm event, it is necessary to:
+       - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
+       - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() 
+         and RTC_AlarmCmd() functions.
+     - To wake up from the Standby mode with an RTC Tamper or time stamp event, it 
+       is necessary to:
+       - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() 
+         function
+       - Configure the RTC to detect the tamper or time stamp event using the
+         RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
+         functions.
+     - To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
+       - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
+       - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), 
+         RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enters STOP mode.
+  *   
+  * @note   In Stop mode, all I/O pins keep the same state as in Run mode.
+  * @note   When exiting Stop mode by issuing an interrupt or a wakeup event, 
+  *         the HSI RC oscillator is selected as system clock.
+  * @note   When the voltage regulator operates in low power mode, an additional 
+  *         startup delay is incurred when waking up from Stop mode. 
+  *         By keeping the internal regulator ON during Stop mode, the consumption 
+  *         is higher although the startup time is reduced.           
+  *     
+  * @param  PWR_Regulator: specifies the regulator state in STOP mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_Regulator_ON: STOP mode with regulator ON
+  *            @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
+  * @param  PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
+  *            @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
+  * @retval None
+  */
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(PWR_Regulator));
+  assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+  
+  /* Select the regulator state in STOP mode ---------------------------------*/
+  tmpreg = PWR->CR;
+  /* Clear PDDS and LPDSR bits */
+  tmpreg &= CR_DS_MASK;
+  
+  /* Set LPDSR bit according to PWR_Regulator value */
+  tmpreg |= PWR_Regulator;
+  
+  /* Store the new value */
+  PWR->CR = tmpreg;
+  
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+  
+  /* Select STOP mode entry --------------------------------------------------*/
+  if(PWR_STOPEntry == PWR_STOPEntry_WFI)
+  {   
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __WFE();
+  }
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);  
+}
+
+/**
+  * @brief  Enters STANDBY mode.
+  * @note   In Standby mode, all I/O pins are high impedance except for:
+  *          - Reset pad (still available) 
+  *          - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC 
+  *            Alarm out, or RTC clock calibration out.
+  *          - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.  
+  *          - WKUP pin 1 (PA0) if enabled.       
+  * @param  None
+  * @retval None
+  */
+void PWR_EnterSTANDBYMode(void)
+{
+  /* Clear Wakeup flag */
+  PWR->CR |= PWR_CR_CWUF;
+  
+  /* Select STANDBY mode */
+  PWR->CR |= PWR_CR_PDDS;
+  
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+  
+
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group7 Flags management functions
+ *  @brief   Flags management functions 
+ *
+@verbatim   
+ ===============================================================================
+                           Flags management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the specified PWR flag is set or not.
+  * @param  PWR_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event 
+  *                  was received from the WKUP pin or from the RTC alarm (Alarm A 
+  *                  or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
+  *                  An additional wakeup event is detected if the WKUP pin is enabled 
+  *                  (by setting the EWUP bit) when the WKUP pin level is already high.  
+  *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
+  *                  resumed from StandBy mode.    
+  *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled 
+  *                  by the PWR_PVDCmd() function. The PVD is stopped by Standby mode 
+  *                  For this reason, this bit is equal to 0 after Standby or reset
+  *                  until the PVDE bit is set.
+  *            @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset 
+  *                  when the device wakes up from Standby mode or by a system reset 
+  *                  or power reset.  
+  *            @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage 
+  *                 scaling output selection is ready. 
+  * @retval The new state of PWR_FLAG (SET or RESET).
+  */
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  
+  /* Check the parameters */
+  assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
+  
+  if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the PWR's pending flags.
+  * @param  PWR_FLAG: specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_FLAG_WU: Wake Up flag
+  *            @arg PWR_FLAG_SB: StandBy flag
+  * @retval None
+  */
+void PWR_ClearFlag(uint32_t PWR_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
+         
+  PWR->CR |=  PWR_FLAG << 2;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/common/hardware_syscfg.c

@@ -0,0 +1,217 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_syscfg.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    30-September-2011
+  * @brief   This file provides firmware functions to manage the SYSCFG peripheral.
+  *
+  *  @verbatim
+  *  
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================
+  *                  
+  *          This driver provides functions for:
+  *          
+  *          1. Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig()
+  *              
+  *          2. Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig()
+  *            
+  *          3. Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig()
+  *
+  *  @note  SYSCFG APB clock must be enabled to get write access to SYSCFG registers,
+  *         using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+  *                 
+  *  @endverbatim
+  *      
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/**
+* @file: hardware_syscfg.c
+* @brief: support hardware syscfg function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/*************************************************
+File name: hardware_syscfg.c
+Description: support hardware syscfg function
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_syscfg.c for XiZi
+*************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include <hardware_syscfg.h>
+#include <hardware_rcc.h>
+#include <stm32_assert_template.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup SYSCFG 
+  * @brief SYSCFG driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define SYSCFG_OFFSET             (SYSCFG_BASE - PERIPH_BASE)
+/* ---  PMC Register ---*/ 
+/* Alias word address of MII_RMII_SEL bit */ 
+#define PMC_OFFSET                (SYSCFG_OFFSET + 0x04) 
+#define MII_RMII_SEL_BitNumber    ((uint8_t)0x17) 
+#define PMC_MII_RMII_SEL_BB       (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) 
+
+/* ---  CMPCR Register ---*/ 
+/* Alias word address of CMP_PD bit */ 
+#define CMPCR_OFFSET              (SYSCFG_OFFSET + 0x20) 
+#define CMP_PD_BitNumber          ((uint8_t)0x00) 
+#define CMPCR_CMP_PD_BB           (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4)) 
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SYSCFG_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  Deinitializes the Alternate Functions (remap and EXTI configuration)
+  *   registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void SYSCFG_DeInit(void)
+{
+   RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+   RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE);
+}
+
+/**
+  * @brief  Changes the mapping of the specified pin.
+  * @param  SYSCFG_Memory: selects the memory remapping.
+  *         This parameter can be one of the following values:
+  *            @arg SYSCFG_MemoryRemap_Flash:       Main Flash memory mapped at 0x00000000  
+  *            @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000
+  *            @arg SYSCFG_MemoryRemap_FSMC:        FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
+  *            @arg SYSCFG_MemoryRemap_SRAM:        Embedded SRAM (112kB) mapped at 0x00000000
+  * @retval None
+  */
+void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap));
+
+  SYSCFG->MEMRMP = SYSCFG_MemoryRemap;
+}
+
+/**
+  * @brief  Selects the GPIO pin used as EXTI Line.
+  * @param  EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for
+  *          EXTI lines where x can be (A..I).
+  * @param  EXTI_PinSourcex: specifies the EXTI line to be configured.
+  *           This parameter can be EXTI_PinSourcex where x can be (0..15, except
+  *           for EXTI_PortSourceGPIOI x can be (0..11).
+  * @retval None
+  */
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
+{
+  uint32_t tmp = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
+  assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
+
+  tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
+  SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
+  SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
+}
+
+/**
+  * @brief  Selects the ETHERNET media interface 
+  * @param  SYSCFG_ETH_MediaInterface: specifies the Media Interface mode. 
+  *          This parameter can be one of the following values: 
+  *            @arg SYSCFG_ETH_MediaInterface_MII: MII mode selected
+  *            @arg SYSCFG_ETH_MediaInterface_RMII: RMII mode selected 
+  * @retval None 
+  */
+void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface) 
+{ 
+  assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE(SYSCFG_ETH_MediaInterface)); 
+  /* Configure MII_RMII selection bit */ 
+  *(__IO uint32_t *) PMC_MII_RMII_SEL_BB = SYSCFG_ETH_MediaInterface; 
+}
+
+/**
+  * @brief  Enables or disables the I/O Compensation Cell.
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V.  
+  * @param  NewState: new state of the I/O Compensation Cell.
+  *          This parameter can be one of the following values:
+  *            @arg ENABLE: I/O compensation cell enabled  
+  *            @arg DISABLE: I/O compensation cell power-down mode  
+  * @retval None
+  */
+void SYSCFG_CompensationCellCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CMPCR_CMP_PD_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Checks whether the I/O Compensation Cell ready flag is set or not.
+  * @param  None
+  * @retval The new state of the I/O Compensation Cell ready flag (SET or RESET)
+  */
+FlagStatus SYSCFG_GetCompensationCellStatus(void)
+{
+  FlagStatus bitstatus = RESET;
+    
+  if ((SYSCFG->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/   

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/common/misc.c

@@ -0,0 +1,252 @@
+/**
+  ******************************************************************************
+  * @file    misc.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    30-September-2011
+  * @brief   This file provides all the miscellaneous firmware functions (add-on
+  *          to CMSIS functions).
+  *          
+  *  @verbatim   
+  *                               
+  *          ===================================================================      
+  *                        How to configure Interrupts using driver 
+  *          ===================================================================      
+  * 
+  *            This section provide functions allowing to configure the NVIC interrupts (IRQ).
+  *            The Cortex-M4 exceptions are managed by CMSIS functions.
+  *
+  *            1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
+  *                function according to the following table.
+ 
+  *  The table below gives the allowed values of the pre-emption priority and subpriority according
+  *  to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+  *    ==========================================================================================================================
+  *      NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  |       Description
+  *    ==========================================================================================================================
+  *     NVIC_PriorityGroup_0  |                0                  |            0-15             | 0 bits for pre-emption priority
+  *                           |                                   |                             | 4 bits for subpriority
+  *    --------------------------------------------------------------------------------------------------------------------------
+  *     NVIC_PriorityGroup_1  |                0-1                |            0-7              | 1 bits for pre-emption priority
+  *                           |                                   |                             | 3 bits for subpriority
+  *    --------------------------------------------------------------------------------------------------------------------------    
+  *     NVIC_PriorityGroup_2  |                0-3                |            0-3              | 2 bits for pre-emption priority
+  *                           |                                   |                             | 2 bits for subpriority
+  *    --------------------------------------------------------------------------------------------------------------------------    
+  *     NVIC_PriorityGroup_3  |                0-7                |            0-1              | 3 bits for pre-emption priority
+  *                           |                                   |                             | 1 bits for subpriority
+  *    --------------------------------------------------------------------------------------------------------------------------    
+  *     NVIC_PriorityGroup_4  |                0-15               |            0                | 4 bits for pre-emption priority
+  *                           |                                   |                             | 0 bits for subpriority                       
+  *    ==========================================================================================================================     
+  *
+  *            2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init()  
+  *
+  * @note  When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. 
+  *        The pending IRQ priority will be managed only by the subpriority.
+  *
+  * @note  IRQ priority order (sorted by highest to lowest priority):
+  *         - Lowest pre-emption priority
+  *         - Lowest subpriority
+  *         - Lowest hardware priority (IRQ number)
+  *
+  *  @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/**
+* @file: misc.c
+* @brief: support misc function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include <misc.h>
+#include <stm32_assert_template.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup MISC 
+  * @brief MISC driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup MISC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Configures the priority grouping: pre-emption priority and subpriority.
+  * @param  NVIC_PriorityGroup: specifies the priority grouping bits length. 
+  *   This parameter can be one of the following values:
+  *     @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
+  *                                4 bits for subpriority
+  *     @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
+  *                                3 bits for subpriority
+  *     @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
+  *                                2 bits for subpriority
+  *     @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
+  *                                1 bits for subpriority
+  *     @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
+  *                                0 bits for subpriority
+  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. 
+  *         The pending IRQ priority will be managed only by the subpriority. 
+  * @retval None
+  */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
+  
+  /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+  SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+/**
+  * @brief  Initializes the NVIC peripheral according to the specified
+  *         parameters in the NVIC_InitStruct.
+  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+  *         function should be called before. 
+  * @param  NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
+  *         the configuration information for the specified NVIC peripheral.
+  * @retval None
+  */
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
+{
+  uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));  
+  assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
+    
+  if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+  {
+    /* Compute the Corresponding IRQ Priority --------------------------------*/    
+    tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
+    tmppre = (0x4 - tmppriority);
+    tmpsub = tmpsub >> tmppriority;
+
+    tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+    tmppriority |=  (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub);
+        
+    tmppriority = tmppriority << 0x04;
+        
+    NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
+    
+    /* Enable the Selected IRQ Channels --------------------------------------*/
+    NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+  }
+  else
+  {
+    /* Disable the Selected IRQ Channels -------------------------------------*/
+    NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+  }
+}
+
+/**
+  * @brief  Sets the vector table location and Offset.
+  * @param  NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
+  *   This parameter can be one of the following values:
+  *     @arg NVIC_VectTab_RAM: Vector Table in internal SRAM.
+  *     @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH.
+  * @param  Offset: Vector Table base offset field. This value must be a multiple of 0x200.
+  * @retval None
+  */
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
+{ 
+  /* Check the parameters */
+  assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
+  assert_param(IS_NVIC_OFFSET(Offset));  
+   
+  SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+  * @brief  Selects the condition for the system to enter low power mode.
+  * @param  LowPowerMode: Specifies the new mode for the system to enter low power mode.
+  *   This parameter can be one of the following values:
+  *     @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.
+  *     @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
+  *     @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
+  * @param  NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_LP(LowPowerMode));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));  
+  
+  if (NewState != DISABLE)
+  {
+    SCB->SCR |= LowPowerMode;
+  }
+  else
+  {
+    SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
+  }
+}
+
+/**
+  * @brief  Configures the SysTick clock source.
+  * @param  SysTick_CLKSource: specifies the SysTick clock source.
+  *   This parameter can be one of the following values:
+  *     @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
+  *     @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
+  * @retval None
+  */
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
+  if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
+  {
+    SysTick->CTRL |= SysTick_CLKSource_HCLK;
+  }
+  else
+  {
+    SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/dac/Kconfig

@@ -0,0 +1,17 @@
+if BSP_USING_DAC
+    config DAC_BUS_NAME
+        string "dac bus name"
+        default "dac"
+
+    config DAC_DRIVER_NAME
+        string "dac driver name"
+        default "dac_drv"
+
+    config DAC_DEVICE_NAME
+        string "dac bus device name"
+        default "dac_dev"
+
+    config DAC_GPIO_NUM
+        int "dac gpio pin num(only support 4 or 5)"
+        default "4"
+endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/dac/Makefile

@@ -0,0 +1,3 @@
+SRC_FILES := connect_dac.c hardware_dac.c
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/dac/connect_dac.c

@@ -0,0 +1,168 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_dac.c
+* @brief support to register DAC pointer and function
+* @version 2.0
+* @author AIIT XUOS Lab
+* @date 2022-1-10
+*/
+
+#include <connect_dac.h>
+
+#define _DAC_CONS(string1, string2) string1##string2
+#define DAC_CONS(string1, string2) _DAC_CONS(string1, string2)
+
+#ifdef BSP_USING_DAC
+#define DAC_GPIO      DAC_CONS(GPIO_Pin_, DAC_GPIO_NUM)
+#endif
+
+static void DacInit(struct DacHardwareDevice *dac_dev)
+{    
+    GPIO_InitTypeDef GPIO_InitStructure;
+    DAC_InitTypeDef DAC_InitType;
+
+#ifdef BSP_USING_DAC
+    if (0 == strncmp(dac_dev->haldev.dev_name, DAC_DEVICE_NAME, NAME_NUM_MAX)) {
+        RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);//enable GPIOA clock
+        RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE);//enable DAC clock
+            
+        GPIO_InitStructure.GPIO_Pin = DAC_GPIO;
+        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;
+        GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN;
+        GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+        DAC_InitType.DAC_Trigger = DAC_Trigger_None;//disable trigger function TEN1=0
+        DAC_InitType.DAC_WaveGeneration = DAC_WaveGeneration_None;//disable wave generation function
+        DAC_InitType.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;//mask and amplitude configure
+        DAC_InitType.DAC_OutputBuffer = DAC_OutputBuffer_Disable;//disable DAC1 output buffer BOFF1=1
+        DAC_Init(DAC_Channel_1, &DAC_InitType);
+
+        DAC_Cmd(DAC_Channel_1, ENABLE);//enable DAC channel 1
+
+        DAC_SetChannel1Data(DAC_Align_12b_R, 0);//12 bits、R-Align data format, default 0
+    }
+#endif
+}				  
+
+static uint32 Stm32DacOpen(void *dev)
+{
+    struct DacHardwareDevice *dac_dev = (struct DacHardwareDevice *)dev;
+
+    DacInit(dac_dev);
+
+    return EOK;
+}
+
+static uint32 Stm32DacClose(void *dev)
+{
+    struct DacHardwareDevice *dac_dev = (struct DacHardwareDevice *)dev;
+
+    DAC_DeInit();
+
+    return EOK;
+}
+
+static uint32 Stm32DacRead(void *dev, struct BusBlockReadParam *read_param)
+{
+    struct DacHardwareDevice *dac_dev = (struct DacHardwareDevice *)dev;
+
+    uint16 dac_set_value = 0;
+
+    dac_set_value = DAC_GetDataOutputValue(DAC_Channel_1);
+
+   *(uint16 *)read_param->buffer = dac_set_value;
+   read_param->read_length = 2;
+
+   return read_param->read_length;
+}
+
+static uint32 Stm32DacDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(drv);
+    NULL_PARAM_CHECK(configure_info);
+
+    x_err_t ret = EOK;
+
+    struct DacDriver *dac_drv = (struct DacDriver *)drv;
+    struct DacHardwareDevice *dac_dev = (struct DacHardwareDevice *)dac_drv->driver.owner_bus->owner_haldev;
+    struct Stm32HwDac *dac_cfg = (struct Stm32HwDac *)dac_dev->haldev.private_data;
+
+    switch (configure_info->configure_cmd)
+    {
+        case OPE_CFG:
+            dac_cfg->digital_data = *(uint16 *)configure_info->private_data;
+            DAC_SetChannel1Data(DAC_Align_12b_R, dac_cfg->digital_data);//12 bits、R-Align data format, digital data
+            break;
+        default:
+            break;
+    }
+
+    return ret;
+}
+
+static const struct DacDevDone dev_done =
+{
+    Stm32DacOpen,
+    Stm32DacClose,
+    NONE,
+    Stm32DacRead,
+};
+
+int Stm32HwDacInit(void)
+{
+    x_err_t ret = EOK;
+
+#ifdef BSP_USING_DAC
+    static struct DacBus dac_bus;
+    static struct DacDriver dac_drv;
+    static struct DacHardwareDevice dac_dev;
+    static struct Stm32HwDac dac_cfg;
+
+    dac_drv.configure = Stm32DacDrvConfigure;
+
+    ret = DacBusInit(&dac_bus, DAC_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("DAC bus init error %d\n", ret);
+        return ERROR;
+    }
+
+    ret = DacDriverInit(&dac_drv, DAC_DRIVER_NAME);
+    if (ret != EOK) {
+        KPrintf("DAC driver init error %d\n", ret);
+        return ERROR;
+    }
+    ret = DacDriverAttachToBus(DAC_DRIVER_NAME, DAC_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("DAC driver attach error %d\n", ret);
+        return ERROR;
+    }
+
+    dac_dev.dac_dev_done = &dev_done;
+    dac_cfg.DACx = DAC;
+    dac_cfg.digital_data = 0;
+
+    ret = DacDeviceRegister(&dac_dev, (void *)&dac_cfg, DAC_DEVICE_NAME);
+    if (ret != EOK) {
+        KPrintf("DAC device register error %d\n", ret);
+        return ERROR;
+    }
+    ret = DacDeviceAttachToBus(DAC_DEVICE_NAME, DAC_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("DAC device register error %d\n", ret);
+        return ERROR;
+    }
+#endif 
+
+    return ret;
+}

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/dac/hardware_dac.c

@@ -0,0 +1,733 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_dac.c
+  * @author  MCD Application Team
+  * @version V1.4.0
+  * @date    04-August-2014
+   * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Digital-to-Analog Converter (DAC) peripheral: 
+  *           + DAC channels configuration: trigger, output buffer, data format
+  *           + DMA management      
+  *           + Interrupts and flags management
+  *
+ @verbatim      
+ ===============================================================================
+                      ##### DAC Peripheral features #####
+ ===============================================================================
+    [..]        
+      *** DAC Channels ***
+      ====================  
+    [..]  
+    The device integrates two 12-bit Digital Analog Converters that can 
+    be used independently or simultaneously (dual mode):
+      (#) DAC channel1 with DAC_OUT1 (PA4) as output
+      (#) DAC channel2 with DAC_OUT2 (PA5) as output
+  
+      *** DAC Triggers ***
+      ====================
+    [..]
+    Digital to Analog conversion can be non-triggered using DAC_Trigger_None
+    and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register 
+    using DAC_SetChannel1Data() / DAC_SetChannel2Data() functions.
+    [..] 
+    Digital to Analog conversion can be triggered by:
+      (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
+          The used pin (GPIOx_Pin9) must be configured in input mode.
+  
+      (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8 
+          (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...)
+          The timer TRGO event should be selected using TIM_SelectOutputTrigger()
+  
+      (#) Software using DAC_Trigger_Software
+  
+      *** DAC Buffer mode feature ***
+      =============================== 
+      [..] 
+      Each DAC channel integrates an output buffer that can be used to 
+      reduce the output impedance, and to drive external loads directly
+      without having to add an external operational amplifier.
+      To enable, the output buffer use  
+      DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+      [..]           
+      (@) Refer to the device datasheet for more details about output 
+          impedance value with and without output buffer.
+            
+       *** DAC wave generation feature ***
+       =================================== 
+       [..]     
+       Both DAC channels can be used to generate
+         (#) Noise wave using DAC_WaveGeneration_Noise
+         (#) Triangle wave using DAC_WaveGeneration_Triangle
+          
+          -@-  Wave generation can be disabled using DAC_WaveGeneration_None
+  
+       *** DAC data format ***
+       =======================
+       [..]   
+       The DAC data format can be:
+         (#) 8-bit right alignment using DAC_Align_8b_R
+         (#) 12-bit left alignment using DAC_Align_12b_L
+         (#) 12-bit right alignment using DAC_Align_12b_R
+  
+       *** DAC data value to voltage correspondence ***  
+       ================================================ 
+       [..] 
+       The analog output voltage on each DAC channel pin is determined
+       by the following equation: 
+       DAC_OUTx = VREF+ * DOR / 4095
+       with  DOR is the Data Output Register
+          VEF+ is the input voltage reference (refer to the device datasheet)
+        e.g. To set DAC_OUT1 to 0.7V, use
+          DAC_SetChannel1Data(DAC_Align_12b_R, 868);
+          Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
+  
+       *** DMA requests  ***
+       =====================
+       [..]    
+       A DMA1 request can be generated when an external trigger (but not
+       a software trigger) occurs if DMA1 requests are enabled using
+       DAC_DMACmd()
+       [..]
+       DMA1 requests are mapped as following:
+         (#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be 
+             already configured
+         (#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be 
+             already configured
+  
+      
+                      ##### How to use this driver #####
+ ===============================================================================
+    [..]          
+      (+) DAC APB clock must be enabled to get write access to DAC
+          registers using
+          RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)
+      (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
+      (+) Configure the DAC channel using DAC_Init() function
+      (+) Enable the DAC channel using DAC_Cmd() function
+   
+ @endverbatim    
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************  
+  */ 
+
+/**
+* @file: hardware_dac.c
+* @brief: support hardware dac function
+* @version: 2.0
+* @author:  AIIT XUOS Lab
+* @date:    2022/1/11
+*/
+
+/*************************************************
+File name: hardware_dac.c
+Description: support hardware dac function
+Others: 
+History: 
+1. Date: 2022-1-11
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_dac.c for XiZi
+*************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include <hardware_dac.h>
+#include <hardware_rcc.h>
+#include <hardware_conf.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DAC 
+  * @brief DAC driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* CR register Mask */
+#define CR_CLEAR_MASK              ((uint32_t)0x00000FFE)
+
+/* DAC Dual Channels SWTRIG masks */
+#define DUAL_SWTRIG_SET            ((uint32_t)0x00000003)
+#define DUAL_SWTRIG_RESET          ((uint32_t)0xFFFFFFFC)
+
+/* DHR registers offsets */
+#define DHR12R1_OFFSET             ((uint32_t)0x00000008)
+#define DHR12R2_OFFSET             ((uint32_t)0x00000014)
+#define DHR12RD_OFFSET             ((uint32_t)0x00000020)
+
+/* DOR register offset */
+#define DOR_OFFSET                 ((uint32_t)0x0000002C)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DAC_Private_Functions
+  * @{
+  */
+
+/** @defgroup DAC_Group1 DAC channels configuration
+ *  @brief   DAC channels configuration: trigger, output buffer, data format 
+ *
+@verbatim   
+ ===============================================================================
+   ##### DAC channels configuration: trigger, output buffer, data format #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the DAC peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void DAC_DeInit(void)
+{
+  /* Enable DAC reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
+  /* Release DAC from reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
+}
+
+/**
+  * @brief  Initializes the DAC peripheral according to the specified parameters
+  *         in the DAC_InitStruct.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains
+  *         the configuration information for the  specified DAC channel.
+  * @retval None
+  */
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
+{
+  uint32_t tmpreg1 = 0, tmpreg2 = 0;
+
+  /* Check the DAC parameters */
+  assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
+  assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
+  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
+  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
+
+/*---------------------------- DAC CR Configuration --------------------------*/
+  /* Get the DAC CR value */
+  tmpreg1 = DAC->CR;
+  /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+  tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
+  /* Configure for the selected DAC channel: buffer output, trigger, 
+     wave generation, mask/amplitude for wave generation */
+  /* Set TSELx and TENx bits according to DAC_Trigger value */
+  /* Set WAVEx bits according to DAC_WaveGeneration value */
+  /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ 
+  /* Set BOFFx bit according to DAC_OutputBuffer value */   
+  tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
+             DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \
+             DAC_InitStruct->DAC_OutputBuffer);
+  /* Calculate CR register value depending on DAC_Channel */
+  tmpreg1 |= tmpreg2 << DAC_Channel;
+  /* Write to DAC CR */
+  DAC->CR = tmpreg1;
+}
+
+/**
+  * @brief  Fills each DAC_InitStruct member with its default value.
+  * @param  DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will 
+  *         be initialized.
+  * @retval None
+  */
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
+{
+/*--------------- Reset DAC init structure parameters values -----------------*/
+  /* Initialize the DAC_Trigger member */
+  DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
+  /* Initialize the DAC_WaveGeneration member */
+  DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
+  /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
+  DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
+  /* Initialize the DAC_OutputBuffer member */
+  DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+}
+
+/**
+  * @brief  Enables or disables the specified DAC channel.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the DAC channel. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   When the DAC channel is enabled the trigger source can no more be modified.
+  * @retval None
+  */
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC channel */
+    DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC channel */
+    DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel software trigger.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the selected DAC channel software trigger.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable software trigger for the selected DAC channel */
+    DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
+  }
+  else
+  {
+    /* Disable software trigger for the selected DAC channel */
+    DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
+  }
+}
+
+/**
+  * @brief  Enables or disables simultaneously the two DAC channels software triggers.
+  * @param  NewState: new state of the DAC channels software triggers.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable software trigger for both DAC channels */
+    DAC->SWTRIGR |= DUAL_SWTRIG_SET;
+  }
+  else
+  {
+    /* Disable software trigger for both DAC channels */
+    DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel wave generation.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_Wave: specifies the wave type to enable or disable.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Wave_Noise: noise wave generation
+  *            @arg DAC_Wave_Triangle: triangle wave generation
+  * @param  NewState: new state of the selected DAC channel wave generation.
+  *          This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_WAVE(DAC_Wave)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected wave generation for the selected DAC channel */
+    DAC->CR |= DAC_Wave << DAC_Channel;
+  }
+  else
+  {
+    /* Disable the selected wave generation for the selected DAC channel */
+    DAC->CR &= ~(DAC_Wave << DAC_Channel);
+  }
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel1.
+  * @param  DAC_Align: Specifies the data alignment for DAC channel1.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Align_8b_R: 8bit right data alignment selected
+  *            @arg DAC_Align_12b_L: 12bit left data alignment selected
+  *            @arg DAC_Align_12b_R: 12bit right data alignment selected
+  * @param  Data: Data to be loaded in the selected data holding register.
+  * @retval None
+  */
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
+{  
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data));
+  
+  tmp = (uint32_t)DAC_BASE; 
+  tmp += DHR12R1_OFFSET + DAC_Align;
+
+  /* Set the DAC channel1 selected data holding register */
+  *(__IO uint32_t *) tmp = Data;
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel2.
+  * @param  DAC_Align: Specifies the data alignment for DAC channel2.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Align_8b_R: 8bit right data alignment selected
+  *            @arg DAC_Align_12b_L: 12bit left data alignment selected
+  *            @arg DAC_Align_12b_R: 12bit right data alignment selected
+  * @param  Data: Data to be loaded in the selected data holding register.
+  * @retval None
+  */
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data));
+  
+  tmp = (uint32_t)DAC_BASE;
+  tmp += DHR12R2_OFFSET + DAC_Align;
+
+  /* Set the DAC channel2 selected data holding register */
+  *(__IO uint32_t *)tmp = Data;
+}
+
+/**
+  * @brief  Set the specified data holding register value for dual channel DAC.
+  * @param  DAC_Align: Specifies the data alignment for dual channel DAC.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Align_8b_R: 8bit right data alignment selected
+  *            @arg DAC_Align_12b_L: 12bit left data alignment selected
+  *            @arg DAC_Align_12b_R: 12bit right data alignment selected
+  * @param  Data2: Data for DAC Channel2 to be loaded in the selected data holding register.
+  * @param  Data1: Data for DAC Channel1 to be loaded in the selected data  holding register.
+  * @note   In dual mode, a unique register access is required to write in both
+  *          DAC channels at the same time.
+  * @retval None
+  */
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
+{
+  uint32_t data = 0, tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data1));
+  assert_param(IS_DAC_DATA(Data2));
+  
+  /* Calculate and set dual DAC data holding register value */
+  if (DAC_Align == DAC_Align_8b_R)
+  {
+    data = ((uint32_t)Data2 << 8) | Data1; 
+  }
+  else
+  {
+    data = ((uint32_t)Data2 << 16) | Data1;
+  }
+  
+  tmp = (uint32_t)DAC_BASE;
+  tmp += DHR12RD_OFFSET + DAC_Align;
+
+  /* Set the dual DAC selected data holding register */
+  *(__IO uint32_t *)tmp = data;
+}
+
+/**
+  * @brief  Returns the last data output value of the selected DAC channel.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @retval The selected DAC channel data output value.
+  */
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  
+  tmp = (uint32_t) DAC_BASE ;
+  tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
+  
+  /* Returns the DAC channel data output register value */
+  return (uint16_t) (*(__IO uint32_t*) tmp);
+}
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Group2 DMA management functions
+ *  @brief   DMA management functions
+ *
+@verbatim   
+ ===============================================================================
+                       ##### DMA management functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified DAC channel DMA request.
+  * @note   When enabled DMA1 is generated when an external trigger (EXTI Line9,
+  *         TIM2, TIM4, TIM5, TIM6, TIM7 or TIM8  but not a software trigger) occurs.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the selected DAC channel DMA request.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   The DAC channel1 is mapped on DMA1 Stream 5 channel7 which must be
+  *          already configured.
+  * @note   The DAC channel2 is mapped on DMA1 Stream 6 channel7 which must be
+  *          already configured.    
+  * @retval None
+  */
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC channel DMA request */
+    DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC channel DMA request */
+    DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Group3 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim   
+ ===============================================================================
+             ##### Interrupts and flags management functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified DAC interrupts.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. 
+  *          This parameter can be the following values:
+  *            @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+  * @note   The DMA underrun occurs when a second external trigger arrives before the 
+  *         acknowledgement for the first external trigger is received (first request).
+  * @param  NewState: new state of the specified DAC interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */ 
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)  
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_DAC_IT(DAC_IT)); 
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC interrupts */
+    DAC->CR |=  (DAC_IT << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC interrupts */
+    DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
+  }
+}
+
+/**
+  * @brief  Checks whether the specified DAC flag is set or not.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_FLAG: specifies the flag to check. 
+  *          This parameter can be only of the following value:
+  *            @arg DAC_FLAG_DMAUDR: DMA underrun flag
+  * @note   The DMA underrun occurs when a second external trigger arrives before the 
+  *         acknowledgement for the first external trigger is received (first request).
+  * @retval The new state of DAC_FLAG (SET or RESET).
+  */
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_FLAG(DAC_FLAG));
+
+  /* Check the status of the specified DAC flag */
+  if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
+  {
+    /* DAC_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DAC_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the DAC_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DAC channel's pending flags.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_FLAG: specifies the flag to clear. 
+  *          This parameter can be of the following value:
+  *            @arg DAC_FLAG_DMAUDR: DMA underrun flag 
+  * @note   The DMA underrun occurs when a second external trigger arrives before the 
+  *         acknowledgement for the first external trigger is received (first request).                           
+  * @retval None
+  */
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_FLAG(DAC_FLAG));
+
+  /* Clear the selected DAC flags */
+  DAC->SR = (DAC_FLAG << DAC_Channel);
+}
+
+/**
+  * @brief  Checks whether the specified DAC interrupt has occurred or not.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_IT: specifies the DAC interrupt source to check. 
+  *          This parameter can be the following values:
+  *            @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+  * @note   The DMA underrun occurs when a second external trigger arrives before the 
+  *         acknowledgement for the first external trigger is received (first request).
+  * @retval The new state of DAC_IT (SET or RESET).
+  */
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_IT(DAC_IT));
+
+  /* Get the DAC_IT enable bit status */
+  enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
+  
+  /* Check the status of the specified DAC interrupt */
+  if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
+  {
+    /* DAC_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DAC_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the DAC_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DAC channel's interrupt pending bits.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_IT: specifies the DAC interrupt pending bit to clear.
+  *          This parameter can be the following values:
+  *            @arg DAC_IT_DMAUDR: DMA underrun interrupt mask                         
+  * @note   The DMA underrun occurs when a second external trigger arrives before the 
+  *         acknowledgement for the first external trigger is received (first request).                           
+  * @retval None
+  */
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_IT(DAC_IT)); 
+
+  /* Clear the selected DAC interrupt pending bits */
+  DAC->SR = (DAC_IT << DAC_Channel);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/extmem/Kconfig

@@ -0,0 +1,17 @@
+if  BSP_USING_EXTMEM
+    config EXTSRAM_MAX_NUM
+        int
+        default 4
+        
+    config BSP_USING_FSMC_BANK1_NORSRAM3
+        bool "config fsmc bank1 sram3"
+        default n
+        if BSP_USING_FSMC_BANK1_NORSRAM3
+            config BANK1_NORSRAM3_SIZE
+                hex "config sram3 chip size"
+                default 0x100000
+            config BANK1_NORSRAM3_DATA_WIDTH
+                int "config sram3 chip data width"
+                default 16 
+        endif
+endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/extmem/Makefile

@@ -0,0 +1,3 @@
+SRC_FILES := connect_extmem.c
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/extmem/connect_extmem.c

@@ -0,0 +1,162 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_extmem.c
+* @brief support extern memory by fsmc
+* @version 1.0
+* @author AIIT XUOS Lab
+* @date 2021-05-28
+*/
+
+#include "connect_extmem.h"
+#include "hardware_fsmc.h"
+#include "hardware_gpio.h"
+#include "hardware_rcc.h"
+#include <string.h>
+#include <xs_base.h>
+
+#define FSMC_BANK1_NORSRAM3_START_ADDRESS 0x68000000
+
+static FSMC_NORSRAMInitTypeDef hsram3;
+static FSMC_NORSRAMTimingInitTypeDef hsram_read3;
+static FSMC_NORSRAMTimingInitTypeDef hsram_write3;
+
+extern void ExtSramInitBoardMemory(void *start_phy_address, void *end_phy_address, uint8 extsram_idx);
+
+int HwSramInit(void)
+{
+    GPIO_InitTypeDef GPIO_InitStructure;
+
+	RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD|RCC_AHB1Periph_GPIOE|RCC_AHB1Periph_GPIOF|RCC_AHB1Periph_GPIOG, ENABLE);
+	RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC,ENABLE);
+
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+	GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
+	GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+	GPIO_Init(GPIOD, &GPIO_InitStructure);
+		
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+	GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
+	GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+	GPIO_Init(GPIOE, &GPIO_InitStructure);  
+	
+ 	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+	GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
+	GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+	GPIO_Init(GPIOF, &GPIO_InitStructure);
+
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_10 | GPIO_Pin_12;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+	GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
+	GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+	GPIO_Init(GPIOG, &GPIO_InitStructure);
+	
+	GPIO_PinAFConfig(GPIOD,GPIO_PinSource0,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOD,GPIO_PinSource1,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOD,GPIO_PinSource4,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOD,GPIO_PinSource5,GPIO_AF_FSMC); 
+	GPIO_PinAFConfig(GPIOD,GPIO_PinSource8,GPIO_AF_FSMC); 
+	GPIO_PinAFConfig(GPIOD,GPIO_PinSource9,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOD,GPIO_PinSource10,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOD,GPIO_PinSource11,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOD,GPIO_PinSource12,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOD,GPIO_PinSource13,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOD,GPIO_PinSource14,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOD,GPIO_PinSource15,GPIO_AF_FSMC);
+ 
+	GPIO_PinAFConfig(GPIOE,GPIO_PinSource7,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOE,GPIO_PinSource8,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOE,GPIO_PinSource9,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOE,GPIO_PinSource10,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOE,GPIO_PinSource11,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOE,GPIO_PinSource12,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOE,GPIO_PinSource13,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOE,GPIO_PinSource14,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOE,GPIO_PinSource15,GPIO_AF_FSMC);
+	
+	GPIO_PinAFConfig(GPIOF,GPIO_PinSource0,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOF,GPIO_PinSource1,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOF,GPIO_PinSource2,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOF,GPIO_PinSource3,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOF,GPIO_PinSource4,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOF,GPIO_PinSource5,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOF,GPIO_PinSource12,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOF,GPIO_PinSource13,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOF,GPIO_PinSource14,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOF,GPIO_PinSource15,GPIO_AF_FSMC);
+		
+	GPIO_PinAFConfig(GPIOG,GPIO_PinSource0,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOG,GPIO_PinSource1,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOG,GPIO_PinSource2,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOG,GPIO_PinSource3,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOG,GPIO_PinSource4,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOG,GPIO_PinSource5,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOG,GPIO_PinSource10,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOG,GPIO_PinSource12,GPIO_AF_FSMC);
+
+	hsram3.FSMC_ReadWriteTimingStruct = &hsram_read3;
+	hsram3.FSMC_WriteTimingStruct = &hsram_write3;
+
+    /* hsram3.Init */
+    hsram3.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+    hsram3.FSMC_MemoryType = FSMC_MemoryType_SRAM;
+    hsram3.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+    hsram3.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+    hsram3.FSMC_WrapMode = FSMC_WrapMode_Disable;
+    hsram3.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+    hsram3.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+    hsram3.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+    hsram3.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+    hsram3.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+
+    hsram_read3.FSMC_AddressSetupTime = 0;
+    hsram_read3.FSMC_AddressHoldTime = 0;
+    hsram_read3.FSMC_DataSetupTime = 8;
+    hsram_read3.FSMC_BusTurnAroundDuration = 0;
+    hsram_read3.FSMC_CLKDivision = 0;
+    hsram_read3.FSMC_DataLatency = 0;
+    hsram_read3.FSMC_AccessMode = FSMC_AccessMode_A;
+
+    hsram_write3.FSMC_AddressSetupTime = 0;
+    hsram_write3.FSMC_AddressHoldTime = 0;
+    hsram_write3.FSMC_DataSetupTime = 8;
+    hsram_write3.FSMC_BusTurnAroundDuration = 0;
+    hsram_write3.FSMC_CLKDivision = 0;
+    hsram_write3.FSMC_DataLatency = 0;
+    hsram_write3.FSMC_AccessMode = FSMC_AccessMode_A;
+
+#ifdef BSP_USING_FSMC_BANK1_NORSRAM3
+    hsram3.FSMC_Bank = FSMC_Bank1_NORSRAM3;
+#if BANK1_NORSRAM3_DATA_WIDTH == 8
+    hsram3.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
+#elif BANK1_NORSRAM3_DATA_WIDTH == 16
+    hsram3.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+#else
+    hsram3.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_32b;
+#endif
+	FSMC_NORSRAMInit(&hsram3);
+    FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
+	
+	ExtSramInitBoardMemory((void*)(FSMC_BANK1_NORSRAM3_START_ADDRESS), (void*)((FSMC_BANK1_NORSRAM3_START_ADDRESS + BANK1_NORSRAM3_SIZE)), 2);
+
+#endif
+
+    return 0;
+}

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/gpio/Kconfig

@@ -0,0 +1,12 @@
+
+config PIN_BUS_NAME
+    string "pin bus name"
+    default "pin"
+
+config PIN_DRIVER_NAME
+    string "pin driver name"
+    default "pin_drv"
+
+config PIN_DEVICE_NAME
+    string "pin device name"
+    default "pin_dev"

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/gpio/Makefile

@@ -0,0 +1,3 @@
+SRC_FILES := connect_gpio.c hardware_gpio.c
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/gpio/connect_gpio.c

@@ -0,0 +1,919 @@
+/*
+ * Copyright (c) 2020 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2018-11-06     balanceTWK        first version
+ * 2019-04-23     WillianChan       Fix GPIO serial number disorder
+*/
+
+/**
+* @file connect_gpio.c
+* @brief support gpio function using bus driver framework
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+/*************************************************
+File name: connect_gpio.c
+Description: support  gpio configure and register to bus framework
+Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_gpio.c for references
+                https://github.com/RT-Thread/rt-thread/tree/v4.0.2
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: add bus driver framework support for gpio
+*************************************************/
+
+#include <board.h>
+#include <connect_gpio.h>
+#include <hardware_gpio.h>
+#include <hardware_exti.h>
+#include <hardware_rcc.h>
+#include <hardware_syscfg.h>
+#include <misc.h>
+
+#define STM32_PIN_NUMBERS 144 
+
+#define __STM32_PIN(index, rcc, gpio, gpio_index) { 0, RCC_##rcc##Periph_GPIO##gpio, GPIO##gpio, GPIO_Pin_##gpio_index}
+#define __STM32_PIN_DEFAULT {-1, 0, 0, 0}
+
+#define ITEM_NUM(items) sizeof(items)/sizeof(items[0])
+
+struct PinIndex
+{
+    int index;
+    uint32_t rcc;
+    GPIO_TypeDef *gpio;
+    uint32_t pin;
+};
+
+struct PinIrq
+{
+    uint8 port_source;
+    uint8 pin_source;
+    enum IRQn irq_exti_channel;
+    uint32 exti_line;
+};
+
+static const struct PinIndex pins[] =
+{
+#if (STM32_PIN_NUMBERS == 48)
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(2, AHB1, C, 13),
+    __STM32_PIN(3, AHB1, C, 14),
+    __STM32_PIN(4, AHB1, C, 15),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(10, AHB1, A, 0),
+    __STM32_PIN(11, AHB1, A, 1),
+    __STM32_PIN(12, AHB1, A, 2),
+    __STM32_PIN(13, AHB1, A, 3),
+    __STM32_PIN(14, AHB1, A, 4),
+    __STM32_PIN(15, AHB1, A, 5),
+    __STM32_PIN(16, AHB1, A, 6),
+    __STM32_PIN(17, AHB1, A, 7),
+    __STM32_PIN(18, AHB1, B, 0),
+    __STM32_PIN(19, AHB1, B, 1),
+    __STM32_PIN(20, AHB1, B, 2),
+    __STM32_PIN(21, AHB1, B, 10),
+    __STM32_PIN(22, AHB1, B, 11),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(25, AHB1, B, 12),
+    __STM32_PIN(26, AHB1, B, 13),
+    __STM32_PIN(27, AHB1, B, 14),
+    __STM32_PIN(28, AHB1, B, 15),
+    __STM32_PIN(29, AHB1, A, 8),
+    __STM32_PIN(30, AHB1, A, 9),
+    __STM32_PIN(31, AHB1, A, 10),
+    __STM32_PIN(32, AHB1, A, 11),
+    __STM32_PIN(33, AHB1, A, 12),
+    __STM32_PIN(34, AHB1, A, 13),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(37, AHB1, A, 14),
+    __STM32_PIN(38, AHB1, A, 15),
+    __STM32_PIN(39, AHB1, B, 3),
+    __STM32_PIN(40, AHB1, B, 4),
+    __STM32_PIN(41, AHB1, B, 5),
+    __STM32_PIN(42, AHB1, B, 6),
+    __STM32_PIN(43, AHB1, B, 7),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(45, AHB1, B, 8),
+    __STM32_PIN(46, AHB1, B, 9),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+
+#endif
+#if (STM32_PIN_NUMBERS == 64)
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(2, AHB1, C, 13),
+    __STM32_PIN(3, AHB1, C, 14),
+    __STM32_PIN(4, AHB1, C, 15),
+    __STM32_PIN(5, AHB1, D, 0),
+    __STM32_PIN(6, AHB1, D, 1),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(8, AHB1, C, 0),
+    __STM32_PIN(9, AHB1, C, 1),
+    __STM32_PIN(10, AHB1, C, 2),
+    __STM32_PIN(11, AHB1, C, 3),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(14, AHB1, A, 0),
+    __STM32_PIN(15, AHB1, A, 1),
+    __STM32_PIN(16, AHB1, A, 2),
+    __STM32_PIN(17, AHB1, A, 3),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(20, AHB1, A, 4),
+    __STM32_PIN(21, AHB1, A, 5),
+    __STM32_PIN(22, AHB1, A, 6),
+    __STM32_PIN(23, AHB1, A, 7),
+    __STM32_PIN(24, AHB1, C, 4),
+    __STM32_PIN(25, AHB1, C, 5),
+    __STM32_PIN(26, AHB1, B, 0),
+    __STM32_PIN(27, AHB1, B, 1),
+    __STM32_PIN(28, AHB1, B, 2),
+    __STM32_PIN(29, AHB1, B, 10),
+    __STM32_PIN(30, AHB1, B, 11),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(33, AHB1, B, 12),
+    __STM32_PIN(34, AHB1, B, 13),
+    __STM32_PIN(35, AHB1, B, 14),
+    __STM32_PIN(36, AHB1, B, 15),
+    __STM32_PIN(37, AHB1, C, 6),
+    __STM32_PIN(38, AHB1, C, 7),
+    __STM32_PIN(39, AHB1, C, 8),
+    __STM32_PIN(40, AHB1, C, 9),
+    __STM32_PIN(41, AHB1, A, 8),
+    __STM32_PIN(42, AHB1, A, 9),
+    __STM32_PIN(43, AHB1, A, 10),
+    __STM32_PIN(44, AHB1, A, 11),
+    __STM32_PIN(45, AHB1, A, 12),
+    __STM32_PIN(46, AHB1, A, 13),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(49, AHB1, A, 14),
+    __STM32_PIN(50, AHB1, A, 15),
+    __STM32_PIN(51, AHB1, C, 10),
+    __STM32_PIN(52, AHB1, C, 11),
+    __STM32_PIN(53, AHB1, C, 12),
+    __STM32_PIN(54, AHB1, D, 2),
+    __STM32_PIN(55, AHB1, B, 3),
+    __STM32_PIN(56, AHB1, B, 4),
+    __STM32_PIN(57, AHB1, B, 5),
+    __STM32_PIN(58, AHB1, B, 6),
+    __STM32_PIN(59, AHB1, B, 7),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(61, AHB1, B, 8),
+    __STM32_PIN(62, AHB1, B, 9),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+#endif
+#if (STM32_PIN_NUMBERS == 100)
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(1, AHB1, E, 2),
+    __STM32_PIN(2, AHB1, E, 3),
+    __STM32_PIN(3, AHB1, E, 4),
+    __STM32_PIN(4, AHB1, E, 5),
+    __STM32_PIN(5, AHB1, E, 6),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(7, AHB1, C, 13),
+    __STM32_PIN(8, AHB1, C, 14),
+    __STM32_PIN(9, AHB1, C, 15),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(15, AHB1, C, 0),
+    __STM32_PIN(16, AHB1, C, 1),
+    __STM32_PIN(17, AHB1, C, 2),
+    __STM32_PIN(18, AHB1, C, 3),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(23, AHB1, A, 0),
+    __STM32_PIN(24, AHB1, A, 1),
+    __STM32_PIN(25, AHB1, A, 2),
+    __STM32_PIN(26, AHB1, A, 3),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(29, AHB1, A, 4),
+    __STM32_PIN(30, AHB1, A, 5),
+    __STM32_PIN(31, AHB1, A, 6),
+    __STM32_PIN(32, AHB1, A, 7),
+    __STM32_PIN(33, AHB1, C, 4),
+    __STM32_PIN(34, AHB1, C, 5),
+    __STM32_PIN(35, AHB1, B, 0),
+    __STM32_PIN(36, AHB1, B, 1),
+    __STM32_PIN(37, AHB1, B, 2),
+    __STM32_PIN(38, AHB1, E, 7),
+    __STM32_PIN(39, AHB1, E, 8),
+    __STM32_PIN(40, AHB1, E, 9),
+    __STM32_PIN(41, AHB1, E, 10),
+    __STM32_PIN(42, AHB1, E, 11),
+    __STM32_PIN(43, AHB1, E, 12),
+    __STM32_PIN(44, AHB1, E, 13),
+    __STM32_PIN(45, AHB1, E, 14),
+    __STM32_PIN(46, AHB1, E, 15),
+    __STM32_PIN(47, AHB1, B, 10),
+    __STM32_PIN(48, AHB1, B, 11),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(51, AHB1, B, 12),
+    __STM32_PIN(52, AHB1, B, 13),
+    __STM32_PIN(53, AHB1, B, 14),
+    __STM32_PIN(54, AHB1, B, 15),
+    __STM32_PIN(55, AHB1, D, 8),
+    __STM32_PIN(56, AHB1, D, 9),
+    __STM32_PIN(57, AHB1, D, 10),
+    __STM32_PIN(58, AHB1, D, 11),
+    __STM32_PIN(59, AHB1, D, 12),
+    __STM32_PIN(60, AHB1, D, 13),
+    __STM32_PIN(61, AHB1, D, 14),
+    __STM32_PIN(62, AHB1, D, 15),
+    __STM32_PIN(63, AHB1, C, 6),
+    __STM32_PIN(64, AHB1, C, 7),
+    __STM32_PIN(65, AHB1, C, 8),
+    __STM32_PIN(66, AHB1, C, 9),
+    __STM32_PIN(67, AHB1, A, 8),
+    __STM32_PIN(68, AHB1, A, 9),
+    __STM32_PIN(69, AHB1, A, 10),
+    __STM32_PIN(70, AHB1, A, 11),
+    __STM32_PIN(71, AHB1, A, 12),
+    __STM32_PIN(72, AHB1, A, 13),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(76, AHB1, A, 14),
+    __STM32_PIN(77, AHB1, A, 15),
+    __STM32_PIN(78, AHB1, C, 10),
+    __STM32_PIN(79, AHB1, C, 11),
+    __STM32_PIN(80, AHB1, C, 12),
+    __STM32_PIN(81, AHB1, D, 0),
+    __STM32_PIN(82, AHB1, D, 1),
+    __STM32_PIN(83, AHB1, D, 2),
+    __STM32_PIN(84, AHB1, D, 3),
+    __STM32_PIN(85, AHB1, D, 4),
+    __STM32_PIN(86, AHB1, D, 5),
+    __STM32_PIN(87, AHB1, D, 6),
+    __STM32_PIN(88, AHB1, D, 7),
+    __STM32_PIN(89, AHB1, B, 3),
+    __STM32_PIN(90, AHB1, B, 4),
+    __STM32_PIN(91, AHB1, B, 5),
+    __STM32_PIN(92, AHB1, B, 6),
+    __STM32_PIN(93, AHB1, B, 7),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(95, AHB1, B, 8),
+    __STM32_PIN(96, AHB1, B, 9),
+    __STM32_PIN(97, AHB1, E, 0),
+    __STM32_PIN(98, AHB1, E, 1),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+#endif
+#if (STM32_PIN_NUMBERS == 144)
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(1, AHB1, E, 2),
+    __STM32_PIN(2, AHB1, E, 3),
+    __STM32_PIN(3, AHB1, E, 4),
+    __STM32_PIN(4, AHB1, E, 5),
+    __STM32_PIN(5, AHB1, E, 6),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(7, AHB1, C, 13),
+    __STM32_PIN(8, AHB1, C, 14),
+    __STM32_PIN(9, AHB1, C, 15),
+
+    __STM32_PIN(10, AHB1, F, 0),
+    __STM32_PIN(11, AHB1, F, 1),
+    __STM32_PIN(12, AHB1, F, 2),
+    __STM32_PIN(13, AHB1, F, 3),
+    __STM32_PIN(14, AHB1, F, 4),
+    __STM32_PIN(15, AHB1, F, 5),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(18, AHB1, F, 6),
+    __STM32_PIN(19, AHB1, F, 7),
+    __STM32_PIN(20, AHB1, F, 8),
+    __STM32_PIN(21, AHB1, F, 9),
+    __STM32_PIN(22, AHB1, F, 10),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(26, AHB1, C, 0),
+    __STM32_PIN(27, AHB1, C, 1),
+    __STM32_PIN(28, AHB1, C, 2),
+    __STM32_PIN(29, AHB1, C, 3),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(34, AHB1, A, 0),
+    __STM32_PIN(35, AHB1, A, 1),
+    __STM32_PIN(36, AHB1, A, 2),
+    __STM32_PIN(37, AHB1, A, 3),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(40, AHB1, A, 4),
+    __STM32_PIN(41, AHB1, A, 5),
+    __STM32_PIN(42, AHB1, A, 6),
+    __STM32_PIN(43, AHB1, A, 7),
+    __STM32_PIN(44, AHB1, C, 4),
+    __STM32_PIN(45, AHB1, C, 5),
+    __STM32_PIN(46, AHB1, B, 0),
+    __STM32_PIN(47, AHB1, B, 1),
+    __STM32_PIN(48, AHB1, B, 2),
+    __STM32_PIN(49, AHB1, F, 11),
+    __STM32_PIN(50, AHB1, F, 12),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(53, AHB1, F, 13),
+    __STM32_PIN(54, AHB1, F, 14),
+    __STM32_PIN(55, AHB1, F, 15),
+    __STM32_PIN(56, AHB1, G, 0),
+    __STM32_PIN(57, AHB1, G, 1),
+    __STM32_PIN(58, AHB1, E, 7),
+    __STM32_PIN(59, AHB1, E, 8),
+    __STM32_PIN(60, AHB1, E, 9),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(63, AHB1, E, 10),
+    __STM32_PIN(64, AHB1, E, 11),
+    __STM32_PIN(65, AHB1, E, 12),
+    __STM32_PIN(66, AHB1, E, 13),
+    __STM32_PIN(67, AHB1, E, 14),
+    __STM32_PIN(68, AHB1, E, 15),
+    __STM32_PIN(69, AHB1, B, 10),
+    __STM32_PIN(70, AHB1, B, 11),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(73, AHB1, B, 12),
+    __STM32_PIN(74, AHB1, B, 13),
+    __STM32_PIN(75, AHB1, B, 14),
+    __STM32_PIN(76, AHB1, B, 15),
+    __STM32_PIN(77, AHB1, D, 8),
+    __STM32_PIN(78, AHB1, D, 9),
+    __STM32_PIN(79, AHB1, D, 10),
+    __STM32_PIN(80, AHB1, D, 11),
+    __STM32_PIN(81, AHB1, D, 12),
+    __STM32_PIN(82, AHB1, D, 13),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(85, AHB1, D, 14),
+    __STM32_PIN(86, AHB1, D, 15),
+    __STM32_PIN(87, AHB1, G, 2),
+    __STM32_PIN(88, AHB1, G, 3),
+    __STM32_PIN(89, AHB1, G, 4),
+    __STM32_PIN(90, AHB1, G, 5),
+    __STM32_PIN(91, AHB1, G, 6),
+    __STM32_PIN(92, AHB1, G, 7),
+    __STM32_PIN(93, AHB1, G, 8),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(96, AHB1, C, 6),
+    __STM32_PIN(97, AHB1, C, 7),
+    __STM32_PIN(98, AHB1, C, 8),
+    __STM32_PIN(99, AHB1, C, 9),
+    __STM32_PIN(100, AHB1, A, 8),
+    __STM32_PIN(101, AHB1, A, 9),
+    __STM32_PIN(102, AHB1, A, 10),
+    __STM32_PIN(103, AHB1, A, 11),
+    __STM32_PIN(104, AHB1, A, 12),
+    __STM32_PIN(105, AHB1, A, 13),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(109, AHB1, A, 14),
+    __STM32_PIN(110, AHB1, A, 15),
+    __STM32_PIN(111, AHB1, C, 10),
+    __STM32_PIN(112, AHB1, C, 11),
+    __STM32_PIN(113, AHB1, C, 12),
+    __STM32_PIN(114, AHB1, D, 0),
+    __STM32_PIN(115, AHB1, D, 1),
+    __STM32_PIN(116, AHB1, D, 2),
+    __STM32_PIN(117, AHB1, D, 3),
+    __STM32_PIN(118, AHB1, D, 4),
+    __STM32_PIN(119, AHB1, D, 5),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(122, AHB1, D, 6),
+    __STM32_PIN(123, AHB1, D, 7),
+    __STM32_PIN(124, AHB1, G, 9),
+    __STM32_PIN(125, AHB1, G, 10),
+    __STM32_PIN(126, AHB1, G, 11),
+    __STM32_PIN(127, AHB1, G, 12),
+    __STM32_PIN(128, AHB1, G, 13),
+    __STM32_PIN(129, AHB1, G, 14),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(132, AHB1, G, 15),
+    __STM32_PIN(133, AHB1, B, 3),
+    __STM32_PIN(134, AHB1, B, 4),
+    __STM32_PIN(135, AHB1, B, 5),
+    __STM32_PIN(136, AHB1, B, 6),
+    __STM32_PIN(137, AHB1, B, 7),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN(139, AHB1, B, 8),
+    __STM32_PIN(140, AHB1, B, 9),
+    __STM32_PIN(141, AHB1, E, 0),
+    __STM32_PIN(142, AHB1, E, 1),
+    __STM32_PIN_DEFAULT,
+    __STM32_PIN_DEFAULT,
+#endif
+};
+
+struct PinIrqHdr pin_irq_hdr_tab[] =
+{
+    {-1, 0, NONE, NONE},
+    {-1, 0, NONE, NONE},
+    {-1, 0, NONE, NONE},
+    {-1, 0, NONE, NONE},
+    {-1, 0, NONE, NONE},
+    {-1, 0, NONE, NONE},
+    {-1, 0, NONE, NONE},
+    {-1, 0, NONE, NONE},
+    {-1, 0, NONE, NONE},
+    {-1, 0, NONE, NONE},
+    {-1, 0, NONE, NONE},
+    {-1, 0, NONE, NONE},
+    {-1, 0, NONE, NONE},
+    {-1, 0, NONE, NONE},
+    {-1, 0, NONE, NONE},
+    {-1, 0, NONE, NONE},                  
+};
+const struct PinIndex *GetPin(uint8_t pin)
+{
+    const struct PinIndex *index;
+
+    if (pin < ITEM_NUM(pins)){
+        index = &pins[pin];
+        if (index->index == -1)
+            index = NONE;
+    }
+    else {
+        index = NONE;
+    }
+
+    return index;
+};
+
+static int32 GpioConfigMode(int mode, const struct PinIndex* index)
+{
+    GPIO_InitTypeDef gpio_initstructure;
+    NULL_PARAM_CHECK(index);
+
+    RCC_AHB1PeriphClockCmd(index->rcc, ENABLE);
+
+    gpio_initstructure.GPIO_Pin   = index->pin;
+    gpio_initstructure.GPIO_Speed = GPIO_Speed_2MHz;
+    gpio_initstructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+
+    switch (mode)
+    {
+        case GPIO_CFG_OUTPUT:
+            gpio_initstructure.GPIO_Mode  = GPIO_Mode_OUT;
+            gpio_initstructure.GPIO_OType = GPIO_OType_PP;
+            break;
+        case GPIO_CFG_INPUT:
+            gpio_initstructure.GPIO_Mode = GPIO_Mode_IN;
+            gpio_initstructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+            break;
+        case GPIO_CFG_INPUT_PULLUP:
+            gpio_initstructure.GPIO_Mode = GPIO_Mode_IN;
+            gpio_initstructure.GPIO_PuPd = GPIO_PuPd_UP;
+            break;
+        case GPIO_CFG_INPUT_PULLDOWN:
+            gpio_initstructure.GPIO_Mode = GPIO_Mode_IN;
+            gpio_initstructure.GPIO_PuPd = GPIO_PuPd_DOWN;
+            break;
+        case GPIO_CFG_OUTPUT_OD:
+            gpio_initstructure.GPIO_Mode  = GPIO_Mode_OUT;
+            gpio_initstructure.GPIO_OType = GPIO_OType_OD;
+            break;
+        default:
+            break;
+    }
+    GPIO_Init(index->gpio, &gpio_initstructure);
+    return EOK;
+}
+
+static __inline int32 Bit2Bitnum(uint32 bit)
+{
+    for (int i = 0; i < 32; i++) {
+        if ((1UL << i) == bit) {
+            return i;
+        }
+    }
+    return -1;
+}
+
+static __inline int32 Bitno2Bit(uint32 bitno)
+{
+    if (bitno <= 32) {
+        return 1UL << bitno;
+    } else {
+        return 0;
+    }
+}
+static const struct PinIrq *GetPinIrq(uint16_t pin)
+{
+    static struct PinIrq irq;
+    const struct PinIndex* index = GetPin(pin);
+
+    if (index == NONE) {
+        return NONE;
+    }
+
+    irq.exti_line = index->pin;
+    irq.pin_source = Bit2Bitnum(index->pin);
+    irq.port_source = ((uint32_t)index->gpio - GPIOA_BASE) / (GPIOB_BASE - GPIOA_BASE);
+    switch (irq.pin_source)
+    {
+        case 0 : irq.irq_exti_channel = EXTI0_IRQn;break;
+        case 1 : irq.irq_exti_channel = EXTI1_IRQn;break;
+        case 2 : irq.irq_exti_channel = EXTI2_IRQn;break;
+        case 3 : irq.irq_exti_channel = EXTI3_IRQn;break;
+        case 4 : irq.irq_exti_channel = EXTI4_IRQn;break;
+        case 5 :
+        case 6 :
+        case 7 :
+        case 8 :
+        case 9 : irq.irq_exti_channel = EXTI9_5_IRQn;break;
+        case 10 :
+        case 11 :
+        case 12 :
+        case 13 :
+        case 14 :
+        case 15 : irq.irq_exti_channel = EXTI15_10_IRQn;break;
+        default : return NONE;
+    }
+
+    return &irq;
+};
+
+static int32 GpioIrqRegister(int32 pin, int32 mode, void (*hdr)(void *args), void *args)
+{
+    const struct PinIndex* index = GetPin(pin);
+    int32 irqindex = -1;
+
+    irqindex = Bit2Bitnum(index->pin);
+    if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)) {
+        return -ENONESYS;
+    }
+
+    x_base level = CriticalAreaLock();
+    if (pin_irq_hdr_tab[irqindex].pin == pin   &&
+        pin_irq_hdr_tab[irqindex].hdr == hdr   &&
+        pin_irq_hdr_tab[irqindex].mode == mode &&
+        pin_irq_hdr_tab[irqindex].args == args
+    )
+    {
+        CriticalAreaUnLock(level);
+        return EOK;
+    }
+    if (pin_irq_hdr_tab[irqindex].pin != -1) {
+        CriticalAreaUnLock(level);
+        return -EDEV_BUSY;
+    }
+    pin_irq_hdr_tab[irqindex].pin = pin;
+    pin_irq_hdr_tab[irqindex].hdr = hdr;
+    pin_irq_hdr_tab[irqindex].mode = mode;
+    pin_irq_hdr_tab[irqindex].args = args;
+    CriticalAreaUnLock(level);
+ 
+    return EOK;
+}
+
+static uint32 GpioIrqFree(int32 pin)
+{
+    const struct PinIndex* index = GetPin(pin);
+    int32 irqindex = -1;
+
+    irqindex = Bit2Bitnum(index->pin);
+    if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)) {
+        return ENONESYS;
+    }
+
+    x_base level = CriticalAreaLock();
+    if (pin_irq_hdr_tab[irqindex].pin == -1) {
+        CriticalAreaUnLock(level);
+        return EOK;
+    }
+    pin_irq_hdr_tab[irqindex].pin  = -1;
+    pin_irq_hdr_tab[irqindex].hdr  = NONE;
+    pin_irq_hdr_tab[irqindex].mode = 0;
+    pin_irq_hdr_tab[irqindex].args = NONE;
+    CriticalAreaUnLock(level);
+ 
+    return EOK;
+}
+
+static int32 GpioIrqEnable(x_base pin)
+{
+    const struct PinIndex* index = GetPin(pin);
+    int32 irqindex = -1;
+    const struct PinIrq *irq;
+    NVIC_InitTypeDef NVIC_InitStructure;
+    EXTI_InitTypeDef exit_init_structure;
+
+    irqindex = Bit2Bitnum(index->pin);
+    if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)) {
+        return -ENONESYS;
+    }
+    x_base level = CriticalAreaLock();
+    if (pin_irq_hdr_tab[irqindex].pin == -1) {
+        CriticalAreaUnLock(level);
+        return -ENONESYS;
+    }
+
+    irq = GetPinIrq(pin);
+    if (irq == NONE) {
+        CriticalAreaUnLock(level);
+        return -ENONESYS;
+    }
+    SYSCFG_EXTILineConfig(irq->port_source, irq->pin_source);
+    exit_init_structure.EXTI_Line = irq->exti_line;
+    exit_init_structure.EXTI_Mode = EXTI_Mode_Interrupt;
+    switch (pin_irq_hdr_tab[irqindex].mode)
+    {
+        case GPIO_IRQ_EDGE_RISING:
+            exit_init_structure.EXTI_Trigger = EXTI_Trigger_Rising;
+            break;
+        case GPIO_IRQ_EDGE_FALLING:
+            exit_init_structure.EXTI_Trigger = EXTI_Trigger_Falling;
+            break;
+        case GPIO_IRQ_EDGE_BOTH:
+            exit_init_structure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
+            break;
+    }
+    exit_init_structure.EXTI_LineCmd = ENABLE;
+    EXTI_Init(&exit_init_structure);
+    NVIC_InitStructure.NVIC_IRQChannel = irq->irq_exti_channel;
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+    NVIC_Init(&NVIC_InitStructure);
+
+    CriticalAreaUnLock(level);
+    return EOK;
+}
+
+static int32 GpioIrqDisable(x_base pin)
+{
+    const struct PinIndex* index = GetPin(pin);
+    const struct PinIrq *irq;
+    EXTI_InitTypeDef exit_init_structure;
+    
+    irq = GetPinIrq(index->pin);
+    NULL_PARAM_CHECK(irq);
+
+    exit_init_structure.EXTI_Line = irq->exti_line;
+    exit_init_structure.EXTI_Mode = EXTI_Mode_Interrupt;
+    exit_init_structure.EXTI_Trigger = EXTI_Trigger_Rising;
+    exit_init_structure.EXTI_LineCmd = DISABLE;  
+    EXTI_Init(&exit_init_structure);
+    return EOK; 
+}
+
+static uint32 Stm32PinConfigure(struct PinParam *param)
+{
+    NULL_PARAM_CHECK(param);    
+    int ret = EOK;
+
+    const struct PinIndex *index = GetPin(param->pin);
+
+    switch(param->cmd)
+    {
+        case GPIO_CONFIG_MODE:
+            GpioConfigMode(param->mode, index);
+            break;
+        case GPIO_IRQ_REGISTER:
+            ret = GpioIrqRegister(param->pin,param->irq_set.irq_mode,param->irq_set.hdr,param->irq_set.args);
+            break;
+        case GPIO_IRQ_FREE:
+            ret = GpioIrqFree(param->pin);
+            break;
+        case GPIO_IRQ_ENABLE:
+            ret = GpioIrqEnable(param->pin);
+            break;
+        case GPIO_IRQ_DISABLE:
+            ret = GpioIrqDisable(param->pin);
+            break;
+        default:
+            ret = EINVALED;
+            break;
+    }
+
+    return ret;
+}
+
+static uint32 Stm32PinInit(void)
+{
+    static x_bool PinInitFlag = RET_FALSE;
+
+    if (!PinInitFlag) {
+        RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+        PinInitFlag = RET_TRUE;
+    }
+    
+    return EOK;
+}
+
+static uint32 Stm32GpioDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(drv);
+    NULL_PARAM_CHECK(configure_info);
+
+    x_err_t ret = EOK;
+    struct PinParam *param;
+
+    switch (configure_info->configure_cmd)
+    {
+        case OPE_INT:
+            ret = Stm32PinInit();
+            break;    
+        case OPE_CFG:
+            param = (struct PinParam *)configure_info->private_data;
+            ret = Stm32PinConfigure(param);
+            break;
+        default:
+            break;
+    }
+
+    return ret;
+}
+
+uint32 Stm32PinWrite(void *dev, struct BusBlockWriteParam *write_param)
+{
+    NULL_PARAM_CHECK(dev);
+    NULL_PARAM_CHECK(write_param);
+    struct PinStat *pinstat = (struct PinStat *)write_param->buffer;
+    const struct PinIndex* index = GetPin(pinstat->pin);
+    NULL_PARAM_CHECK(index);
+
+    if (GPIO_LOW == pinstat->val) {
+        GPIO_ResetBits(index->gpio, index->pin);
+    } else {
+        GPIO_SetBits(index->gpio, index->pin);
+    }
+    return EOK;
+}
+
+uint32 Stm32PinRead(void *dev, struct BusBlockReadParam *read_param)
+{
+    NULL_PARAM_CHECK(dev);
+    NULL_PARAM_CHECK(read_param);
+    struct PinStat *pinstat = (struct PinStat *)read_param->buffer;
+    const struct PinIndex* index = GetPin(pinstat->pin);
+    NULL_PARAM_CHECK(index);
+    
+    if (GPIO_ReadInputDataBit(index->gpio, index->pin) == Bit_RESET) {
+        pinstat->val = GPIO_LOW;
+    } else {
+        pinstat->val = GPIO_HIGH;
+    }
+    return pinstat->val;
+}
+
+static const struct PinDevDone dev_done =
+{
+    .open  = NONE,
+    .close = NONE,
+    .write = Stm32PinWrite,
+    .read  = Stm32PinRead,
+};
+
+int Stm32HwGpioInit(void)
+{
+    x_err_t ret = EOK;
+
+    static struct PinBus pin;
+
+    ret = PinBusInit(&pin, PIN_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("gpio bus init error %d\n", ret);
+        return ERROR;
+    }
+
+    static struct PinDriver drv;
+    drv.configure = &Stm32GpioDrvConfigure;
+    
+    ret = PinDriverInit(&drv, PIN_DRIVER_NAME, NONE);
+    if (ret != EOK) {
+        KPrintf("pin driver init error %d\n", ret);
+        return ERROR;
+    }
+    ret = PinDriverAttachToBus(PIN_DRIVER_NAME, PIN_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("pin driver attach error %d\n", ret);
+        return ERROR;
+    }
+
+    static struct PinHardwareDevice dev;
+    dev.dev_done = &dev_done;
+
+    ret = PinDeviceRegister(&dev, NONE, PIN_DEVICE_NAME);
+    if (ret != EOK) {
+        KPrintf("pin device register error %d\n", ret);
+        return ERROR;
+    }
+    ret = PinDeviceAttachToBus(PIN_DEVICE_NAME, PIN_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("pin device register error %d\n", ret);
+        return ERROR;
+    }
+
+    return ret;
+}
+
+static __inline void PinIrqHdr(int irqno)
+{
+    EXTI_ClearITPendingBit(Bitno2Bit(irqno));
+    if (pin_irq_hdr_tab[irqno].hdr) {
+       pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
+    }
+}
+
+void EXTI0_IRQHandler(int irq_num, void *arg)
+{
+    PinIrqHdr(0);
+}
+DECLARE_HW_IRQ(EXTI0_IRQn, EXTI0_IRQHandler, NONE);
+
+void EXTI1_IRQHandler(int irq_num, void *arg)
+{
+    PinIrqHdr(1);
+}
+DECLARE_HW_IRQ(EXTI1_IRQn, EXTI1_IRQHandler, NONE);
+
+void EXTI2_IRQHandler(int irq_num, void *arg)
+{
+    PinIrqHdr(2);
+}
+DECLARE_HW_IRQ(EXTI2_IRQn, EXTI2_IRQHandler, NONE);
+
+void EXTI3_IRQHandler(int irq_num, void *arg)
+{
+    PinIrqHdr(3);
+}
+DECLARE_HW_IRQ(EXTI3_IRQn, EXTI3_IRQHandler, NONE);
+
+void EXTI4_IRQHandler(int irq_num, void *arg)
+{
+    PinIrqHdr(4);
+}
+DECLARE_HW_IRQ(EXTI4_IRQn, EXTI4_IRQHandler, NONE);
+
+void EXTI9_5_IRQHandler(int irq_num, void *arg)
+{
+    if (EXTI_GetITStatus(EXTI_Line5) != RESET) {
+        PinIrqHdr(5);
+    }
+    if (EXTI_GetITStatus(EXTI_Line6) != RESET) {
+        PinIrqHdr(6);
+    }
+    if (EXTI_GetITStatus(EXTI_Line7) != RESET) {
+        PinIrqHdr(7);
+    }
+    if (EXTI_GetITStatus(EXTI_Line8) != RESET) {
+        PinIrqHdr(8);
+    }
+    if (EXTI_GetITStatus(EXTI_Line9) != RESET) {
+        PinIrqHdr(9);
+    }
+}
+DECLARE_HW_IRQ(EXTI9_5_IRQn, EXTI9_5_IRQHandler, NONE);
+
+void EXTI15_10_IRQHandler(int irq_num, void *arg)
+{
+    if (EXTI_GetITStatus(EXTI_Line10) != RESET) {
+        PinIrqHdr(10);
+    }
+    if (EXTI_GetITStatus(EXTI_Line11) != RESET) {
+        PinIrqHdr(11);
+    }
+    if (EXTI_GetITStatus(EXTI_Line12) != RESET) {
+        PinIrqHdr(12);
+    }
+    if (EXTI_GetITStatus(EXTI_Line13) != RESET) {
+        PinIrqHdr(13);
+    }
+    if (EXTI_GetITStatus(EXTI_Line14) != RESET) {
+        PinIrqHdr(14);
+    }
+    if (EXTI_GetITStatus(EXTI_Line15) != RESET) {
+        PinIrqHdr(15);
+    }
+}
+DECLARE_HW_IRQ(EXTI15_10_IRQn, EXTI15_10_IRQHandler, NONE);

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/gpio/hardware_gpio.c

@@ -0,0 +1,581 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_gpio.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    30-September-2011
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the GPIO peripheral:           
+  *           - Initialization and Configuration
+  *           - GPIO Read and Write
+  *           - GPIO Alternate functions configuration
+  * 
+  *  @verbatim
+  *
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================       
+  *           1. Enable the GPIO AHB clock using the following function
+  *                RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
+  *             
+  *           2. Configure the GPIO pin(s) using GPIO_Init()
+  *              Four possible configuration are available for each pin:
+  *                - Input: Floating, Pull-up, Pull-down.
+  *                - Output: Push-Pull (Pull-up, Pull-down or no Pull)
+  *                          Open Drain (Pull-up, Pull-down or no Pull).
+  *                  In output mode, the speed is configurable: 2 MHz, 25 MHz,
+  *                  50 MHz or 100 MHz.
+  *                - Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull)
+  *                                      Open Drain (Pull-up, Pull-down or no Pull).
+  *                - Analog: required mode when a pin is to be used as ADC channel
+  *                          or DAC output.
+  * 
+  *          3- Peripherals alternate function:
+  *              - For ADC and DAC, configure the desired pin in analog mode using 
+  *                  GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN;
+  *              - For other peripherals (TIM, USART...):
+  *                 - Connect the pin to the desired peripherals' Alternate 
+  *                   Function (AF) using GPIO_PinAFConfig() function
+  *                 - Configure the desired pin in alternate function mode using
+  *                   GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+  *                 - Select the type, pull-up/pull-down and output speed via 
+  *                   GPIO_PuPd, GPIO_OType and GPIO_Speed members
+  *                 - Call GPIO_Init() function
+  *        
+  *          4. To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
+  *          
+  *          5. To set/reset the level of a pin configured in output mode use
+  *             GPIO_SetBits()/GPIO_ResetBits()
+  *               
+  *          6. During and just after reset, the alternate functions are not 
+  *             active and the GPIO pins are configured in input floating mode
+  *             (except JTAG pins).
+  *
+  *          7. The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as 
+  *             general-purpose (PC14 and PC15, respectively) when the LSE
+  *             oscillator is off. The LSE has priority over the GPIO function.
+  *
+  *          8. The HSE oscillator pins OSC_IN/OSC_OUT can be used as 
+  *             general-purpose PH0 and PH1, respectively, when the HSE 
+  *             oscillator is off. The HSE has priority over the GPIO function.
+  *             
+  *  @endverbatim        
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/**
+* @file: hardware_gpio.c
+* @brief: support hardware gpio function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/*************************************************
+File name: hardware_gpio.c
+Description: support hardware gpio function
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_gpio.c for XiZi
+*************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include <hardware_gpio.h>
+#include <hardware_rcc.h>
+#include <stm32_assert_template.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup GPIO 
+  * @brief GPIO driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup GPIO_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup GPIO_Group1 Initialization and Configuration
+ *  @brief   Initialization and Configuration
+ *
+@verbatim   
+ ===============================================================================
+                        Initialization and Configuration
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the GPIOx peripheral registers to their default reset values.
+  * @note   By default, The GPIO pins are configured in input floating mode (except JTAG pins).
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
+  * @retval None
+  */
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  if (GPIOx == GPIOA)
+  {
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE);
+  }
+  else if (GPIOx == GPIOB)
+  {
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE);
+  }
+  else if (GPIOx == GPIOC)
+  {
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE);
+  }
+  else if (GPIOx == GPIOD)
+  {
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE);
+  }
+  else if (GPIOx == GPIOE)
+  {
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE);
+  }
+  else if (GPIOx == GPIOF)
+  {
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE);
+  }
+  else if (GPIOx == GPIOG)
+  {
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE);
+  }
+  else if (GPIOx == GPIOH)
+  {
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE);
+  }
+  else
+  {
+    if (GPIOx == GPIOI)
+    {
+      RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE);
+      RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE);
+    }
+  }
+}
+
+/**
+  * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
+  * @param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains
+  *         the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
+{
+  uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
+  assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
+  assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
+
+  /* -------------------------Configure the port pins---------------- */
+  /*-- GPIO Mode Configuration --*/
+  for (pinpos = 0x00; pinpos < 0x10; pinpos++)
+  {
+    pos = ((uint32_t)0x01) << pinpos;
+    /* Get the port pins position */
+    currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
+
+    if (currentpin == pos)
+    {
+      GPIOx->MODER  &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
+      GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
+
+      if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
+      {
+        /* Check Speed mode parameters */
+        assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
+
+        /* Speed mode configuration */
+        GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
+        GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
+
+        /* Check Output mode parameters */
+        assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
+
+        /* Output mode configuration*/
+        GPIOx->OTYPER  &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;
+        GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
+      }
+
+      /* Pull-up Pull down resistor configuration*/
+      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
+      GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
+    }
+  }
+}
+
+/**
+  * @brief  Fills each GPIO_InitStruct member with its default value.
+  * @param  GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
+{
+  /* Reset GPIO init structure parameters values */
+  GPIO_InitStruct->GPIO_Pin  = GPIO_Pin_All;
+  GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
+  GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
+}
+
+/**
+  * @brief  Locks GPIO Pins configuration registers.
+  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+  * @note   The configuration of the locked GPIO pins can no longer be modified
+  *         until the next reset.
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be locked.
+  *          This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  __IO uint32_t tmp = 0x00010000;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  tmp |= GPIO_Pin;
+  /* Set LCKK bit */
+  GPIOx->LCKR = tmp;
+  /* Reset LCKK bit */
+  GPIOx->LCKR =  GPIO_Pin;
+  /* Set LCKK bit */
+  GPIOx->LCKR = tmp;
+  /* Read LCKK bit*/
+  tmp = GPIOx->LCKR;
+  /* Read LCKK bit*/
+  tmp = GPIOx->LCKR;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Group2 GPIO Read and Write
+ *  @brief   GPIO Read and Write
+ *
+@verbatim   
+ ===============================================================================
+                              GPIO Read and Write
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Reads the specified input port pin.
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to read.
+  *         This parameter can be GPIO_Pin_x where x can be (0..15).
+  * @retval The input port pin value.
+  */
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  uint8_t bitstatus = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
+  {
+    bitstatus = (uint8_t)Bit_SET;
+  }
+  else
+  {
+    bitstatus = (uint8_t)Bit_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Reads the specified GPIO input data port.
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
+  * @retval GPIO input data port value.
+  */
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  return ((uint16_t)GPIOx->IDR);
+}
+
+/**
+  * @brief  Reads the specified output data port bit.
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to read.
+  *          This parameter can be GPIO_Pin_x where x can be (0..15).
+  * @retval The output port pin value.
+  */
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  uint8_t bitstatus = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+  if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
+  {
+    bitstatus = (uint8_t)Bit_SET;
+  }
+  else
+  {
+    bitstatus = (uint8_t)Bit_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Reads the specified GPIO output data port.
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
+  * @retval GPIO output data port value.
+  */
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  return ((uint16_t)GPIOx->ODR);
+}
+
+/**
+  * @brief  Sets the selected data port bits.
+  * @note   This functions uses GPIOx_BSRR register to allow atomic read/modify 
+  *         accesses. In this way, there is no risk of an IRQ occurring between
+  *         the read and the modify access.
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bits to be written.
+  *          This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  GPIOx->BSRRL = GPIO_Pin;
+}
+
+/**
+  * @brief  Clears the selected data port bits.
+  * @note   This functions uses GPIOx_BSRR register to allow atomic read/modify 
+  *         accesses. In this way, there is no risk of an IRQ occurring between
+  *         the read and the modify access.
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bits to be written.
+  *          This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  GPIOx->BSRRH = GPIO_Pin;
+}
+
+/**
+  * @brief  Sets or clears the selected data port bit.
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *          This parameter can be one of GPIO_Pin_x where x can be (0..15).
+  * @param  BitVal: specifies the value to be written to the selected bit.
+  *          This parameter can be one of the BitAction enum values:
+  *            @arg Bit_RESET: to clear the port pin
+  *            @arg Bit_SET: to set the port pin
+  * @retval None
+  */
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_BIT_ACTION(BitVal));
+
+  if (BitVal != Bit_RESET)
+  {
+    GPIOx->BSRRL = GPIO_Pin;
+  }
+  else
+  {
+    GPIOx->BSRRH = GPIO_Pin ;
+  }
+}
+
+/**
+  * @brief  Writes data to the specified GPIO data port.
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
+  * @param  PortVal: specifies the value to be written to the port output data register.
+  * @retval None
+  */
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  GPIOx->ODR = PortVal;
+}
+
+/**
+  * @brief  Toggles the specified GPIO pins..
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
+  * @param  GPIO_Pin: Specifies the pins to be toggled.
+  * @retval None
+  */
+void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  GPIOx->ODR ^= GPIO_Pin;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function
+ *  @brief   GPIO Alternate functions configuration function
+ *
+@verbatim   
+ ===============================================================================
+               GPIO Alternate functions configuration function
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Changes the mapping of the specified pin.
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
+  * @param  GPIO_PinSource: specifies the pin for the Alternate function.
+  *         This parameter can be GPIO_PinSourcex where x can be (0..15).
+  * @param  GPIO_AFSelection: selects the pin to used as Alternate function.
+  *          This parameter can be one of the following values:
+  *            @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset) 
+  *            @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset) 
+  *            @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset) 
+  *            @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset) 
+  *            @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset)
+  *            @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1
+  *            @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1
+  *            @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2
+  *            @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2
+  *            @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2
+  *            @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3
+  *            @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3
+  *            @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3
+  *            @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3
+  *            @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4
+  *            @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4
+  *            @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4
+  *            @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5
+  *            @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5
+  *            @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6
+  *            @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7
+  *            @arg GPIO_AF_USART1: Connect USART1 pins to AF7
+  *            @arg GPIO_AF_USART2: Connect USART2 pins to AF7
+  *            @arg GPIO_AF_USART3: Connect USART3 pins to AF7
+  *            @arg GPIO_AF_UART4: Connect UART4 pins to AF8
+  *            @arg GPIO_AF_UART5: Connect UART5 pins to AF8
+  *            @arg GPIO_AF_USART6: Connect USART6 pins to AF8
+  *            @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9
+  *            @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9
+  *            @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9
+  *            @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9
+  *            @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9
+  *            @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10
+  *            @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10
+  *            @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11
+  *            @arg GPIO_AF_FSMC: Connect FSMC pins to AF12
+  *            @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12
+  *            @arg GPIO_AF_SDIO: Connect SDIO pins to AF12
+  *            @arg GPIO_AF_DCMI: Connect DCMI pins to AF13
+  *            @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15
+  * @retval None
+  */
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
+{
+  uint32_t temp = 0x00;
+  uint32_t temp_2 = 0x00;
+  
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+  assert_param(IS_GPIO_AF(GPIO_AF));
+  
+  temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
+  GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
+  temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
+  GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/i2c/Kconfig

@@ -0,0 +1,11 @@
+if BSP_USING_I2C
+    config I2C_BUS_NAME_1
+        string "i2c bus 1 name"
+        default "i2c1"
+    config I2C_DRV_NAME_1
+        string "i2c bus 1 driver name"
+        default "i2c1_drv"
+    config I2C_1_DEVICE_NAME_0
+            string "i2c bus 1 device 0 name"
+            default "i2c1_dev0"     
+endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/i2c/Makefile

@@ -0,0 +1,3 @@
+SRC_FILES := hardware_i2c.c connect_i2c.c
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/i2c/connect_i2c.c

@@ -0,0 +1,737 @@
+/*
+ * Copyright (c) 2020 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2012-04-25     weety         first version
+ */
+
+/**
+* @file connect_i2c.c
+* @brief support aiit-arm32-board i2c function and register to bus framework
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+/*************************************************
+File name: connect_i2c.c
+Description: support aiit-arm32-board i2c configure and i2c bus register function
+Others: take RT-Thread v4.0.2/components/drivers/i2c/i2c-bit-ops.c for references
+                https://github.com/RT-Thread/rt-thread/tree/v4.0.2
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. support aiit-arm32-board i2c bit configure, write and read
+2. support aiit-arm32-board i2c bus device and driver register
+*************************************************/
+
+#include <board.h>
+#include <connect_i2c.h>
+#include <core_cm4.h>
+
+#ifndef BSP_USING_I2C1
+#define BSP_USING_I2C1
+#endif
+
+#define I2C_SDA_FUNC_GPIO 137
+#define I2C_SCL_FUNC_GPIO 136
+
+static I2cBusParam i2c_bus_param =
+{
+    _FUNC_GPIO,
+    I2C_SCL_FUNC_GPIO,
+};
+static BusType pin;
+
+#define SET_SDA(done, val)   done->SetSdaState(done->data, val)
+#define SET_SCL(done, val)   done->SetSclState(done->data, val)
+#define GET_SDA(done)          done->GetSdaState(done->data)
+#define GET_SCL(done)          done->GetSclState(done->data)
+#define SdaLow(done)             SET_SDA(done, 0)
+#define SdaHigh(done)            SET_SDA(done, 1)
+#define SclLow(done)               SET_SCL(done, 0)
+
+static void I2cGpioInit(const I2cBusParam *bus_param)
+{
+    struct PinParam i2c_scl;
+    struct PinStat i2c_scl_stat;
+    struct PinParam i2c_sda;
+    struct PinStat i2c_sda_stat;
+
+	struct BusConfigureInfo configure_info;
+	struct BusBlockWriteParam write_param;
+
+    int ret = 0;
+
+    pin = BusFind(PIN_BUS_NAME);
+    if (!pin) {
+        KPrintf("find %s failed!\n", PIN_BUS_NAME);
+        return ;
+    }
+    pin->owner_driver = BusFindDriver(pin, PIN_DRIVER_NAME);
+    pin->owner_haldev = BusFindDevice(pin, PIN_DEVICE_NAME);
+
+	configure_info.configure_cmd = OPE_INT;
+    ret = BusDrvConfigure(pin->owner_driver, &configure_info);
+    if (ret != EOK) {
+        KPrintf("initialize %s failed!\n", PIN_BUS_NAME);
+        return ;
+    }
+
+    /* config scl pin as output*/
+    i2c_scl.cmd = GPIO_CONFIG_MODE;
+    i2c_scl.pin = bus_param->i2c_scl_pin;
+    i2c_scl.mode = GPIO_CFG_OUTPUT_OD;
+
+	configure_info.configure_cmd = OPE_CFG;
+	configure_info.private_data = (void *)&i2c_scl;
+    ret = BusDrvConfigure(pin->owner_driver, &configure_info);
+    if (ret != EOK) {
+        KPrintf("config i2c scl pin %d failed!\n", bus_param->i2c_scl_pin);
+        return ;
+    }
+    /* set scl pin as high*/
+    i2c_scl_stat.pin = bus_param->i2c_scl_pin;
+    i2c_scl_stat.val = GPIO_HIGH;
+    write_param.buffer = (void *)&i2c_scl_stat;
+    BusDevWriteData(pin->owner_haldev, &write_param);
+
+    /* config sda pin as output*/
+    i2c_sda.cmd = GPIO_CONFIG_MODE;
+    i2c_sda.pin = bus_param->i2c_sda_pin;
+    i2c_sda.mode = GPIO_CFG_OUTPUT_OD;
+
+	configure_info.configure_cmd = OPE_CFG;
+	configure_info.private_data = (void *)&i2c_sda;    
+    ret = BusDrvConfigure(pin->owner_driver, &configure_info);
+    if (ret != EOK) {
+        KPrintf("config i2c sda pin %d failed!\n", bus_param->i2c_sda_pin);
+        return ;
+    }
+    /* set sda pin as high*/
+    i2c_sda_stat.pin = bus_param->i2c_sda_pin;
+    i2c_sda_stat.val = GPIO_HIGH;
+    write_param.buffer = (void *)&i2c_sda_stat;
+    BusDevWriteData(pin->owner_haldev, &write_param);
+}
+
+static void SetSdaState(void *data, uint8 sda_state)
+{
+    struct PinStat i2c_sda_stat;
+    struct BusBlockWriteParam write_param;
+    I2cBusParam *bus_param = (I2cBusParam *)data;
+    if (sda_state) {
+        i2c_sda_stat.pin = bus_param->i2c_sda_pin;
+        i2c_sda_stat.val = GPIO_HIGH;
+
+        write_param.buffer = (void *)&i2c_sda_stat;
+        BusDevWriteData(pin->owner_haldev, &write_param);
+    } else {
+        i2c_sda_stat.pin = bus_param->i2c_sda_pin;
+        i2c_sda_stat.val = GPIO_LOW;
+
+        write_param.buffer = (void *)&i2c_sda_stat;
+        BusDevWriteData(pin->owner_haldev, &write_param);
+    }
+}
+
+static void SetSclState(void *data, uint8 scl_state)
+{
+    struct PinStat i2c_scl_stat;
+    struct BusBlockWriteParam write_param;
+    I2cBusParam *bus_param = (I2cBusParam *)data;
+
+    if (scl_state) {
+        i2c_scl_stat.pin = bus_param->i2c_scl_pin;
+        i2c_scl_stat.val = GPIO_HIGH;
+
+        write_param.buffer = (void *)&i2c_scl_stat;
+        BusDevWriteData(pin->owner_haldev, &write_param);
+    } else {
+        i2c_scl_stat.pin = bus_param->i2c_scl_pin;
+        i2c_scl_stat.val = GPIO_LOW;
+
+        write_param.buffer = (void *)&i2c_scl_stat;
+        BusDevWriteData(pin->owner_haldev, &write_param);
+    }
+}
+
+static uint8 GetSdaState(void *data)
+{
+    struct PinStat i2c_sda_stat;
+    struct BusBlockReadParam read_param;
+    I2cBusParam *bus_param = (I2cBusParam *)data;
+
+    i2c_sda_stat.pin = bus_param->i2c_sda_pin;
+
+    read_param.buffer = (void *)&i2c_sda_stat;
+    return BusDevReadData(pin->owner_haldev, &read_param);
+}
+
+static uint8 GetSclState(void *data)
+{
+    struct PinStat i2c_scl_stat;
+    struct BusBlockReadParam read_param;
+    I2cBusParam *bus_param = (I2cBusParam *)data;
+    i2c_scl_stat.pin = bus_param->i2c_scl_pin;
+
+    read_param.buffer = (void *)&i2c_scl_stat;
+    return BusDevReadData(pin->owner_haldev, &read_param);
+}
+
+ int Stm32Udelay(uint32 us)
+{
+    uint32 ticks;
+    uint32 told, tnow, tcnt = 0;
+    uint32 reload = SysTick->LOAD;
+
+    ticks = us * reload / (1000000 / TICK_PER_SECOND);
+    told = SysTick->VAL;
+    while (1) {
+        tnow = SysTick->VAL;
+        if (tnow != told) {
+            if (tnow < told) {
+                tcnt += told - tnow;
+            } else {
+                tcnt += reload - tnow + told;
+            }
+            told = tnow;
+            if (tcnt >= ticks) {
+                return 0;
+                break;
+            }
+        }
+    }
+}
+
+static const struct I2cHalDrvDone i2c_hal_drv_done =
+{
+    .data = (&i2c_bus_param),
+    .SetSdaState = SetSdaState,
+    .SetSclState = SetSclState,
+    .GetSdaState = GetSdaState,
+    .GetSclState = GetSclState,
+    .udelay = Stm32Udelay,
+    .delay_us = 1,
+    .timeout = 100
+};
+
+static x_err_t I2cBusReset(const I2cBusParam *bus_param)
+{
+    int32 i = 0;
+
+    if (GPIO_LOW == GetSdaState((void *)bus_param)) {
+        while (i++ < 9) {
+            SetSclState((void *)bus_param,GPIO_HIGH);
+            Stm32Udelay(100);
+            SetSclState((void *)bus_param,GPIO_LOW);
+            Stm32Udelay(100);
+        }
+    }
+
+    if (GPIO_LOW == GetSdaState((void *)bus_param)) {
+        return -ERROR;
+    }
+    return EOK;
+}
+
+static __inline void I2cDelay(struct I2cHalDrvDone *done)
+{
+    done->udelay((done->delay_us + 1) >> 1);
+}
+
+static __inline void I2cDelay2(struct I2cHalDrvDone *done)
+{
+    done->udelay(done->delay_us);
+}
+
+static x_err_t SclHigh(struct I2cHalDrvDone *done)
+{
+    x_ticks_t start;
+
+    SET_SCL(done, 1);
+
+    if (!done->GetSclState)
+        goto done;
+
+    start = CurrentTicksGain();
+    while (!GET_SCL(done)) {
+        if ((CurrentTicksGain() - start) > done->timeout)
+            return -ETIMEOUT;
+        DelayKTask((done->timeout + 1) >> 1);
+    }
+
+done:
+    I2cDelay(done);
+
+    return EOK;
+}
+
+static void I2cStart(struct I2cHalDrvDone *done)
+{
+    SdaLow(done);
+    I2cDelay(done);
+    SclLow(done);
+}
+
+static void I2cRestart(struct I2cHalDrvDone *done)
+{
+    SdaHigh(done);
+    SclHigh(done);
+    I2cDelay(done);
+    SdaLow(done);
+    I2cDelay(done);
+    SclLow(done);
+}
+
+static void I2cStop(struct I2cHalDrvDone *done)
+{
+    SdaLow(done);
+    I2cDelay(done);
+    SclHigh(done);
+    I2cDelay(done);
+    SdaHigh(done);
+    I2cDelay2(done);
+}
+
+static __inline x_bool I2cWaitack(struct I2cHalDrvDone *done)
+{
+    x_bool ack;
+
+    SdaHigh(done);
+     GET_SDA(done);    
+    I2cDelay(done);
+
+    if (SclHigh(done) < 0) {
+        KPrintf("wait ack timeout");
+        return -ETIMEOUT;
+    }
+
+    ack = !GET_SDA(done);
+
+    SclLow(done);
+
+    return ack;
+}
+
+static int32 I2cWriteb(struct I2cBus *bus, uint8 data)
+{
+    int32 i;
+    uint8 bit;
+
+    struct I2cHalDrvDone *done = (struct I2cHalDrvDone *)bus->private_data;
+
+    for (i = 7; i >= 0; i--) {
+        SclLow(done);
+        bit = (data >> i) & 1;
+        SET_SDA(done, bit);
+        I2cDelay(done);
+        if (SclHigh(done) < 0) {
+            KPrintf("I2cWriteb: 0x%02x, "
+                    "wait scl pin high timeout at bit %d",
+                    data, i);
+
+            return -ETIMEOUT;
+        }
+    }
+    SclLow(done);
+    I2cDelay(done);
+
+    return I2cWaitack(done);
+}
+
+static int32 I2cReadb(struct I2cBus *bus)
+{
+    uint8 i;
+    uint8 data = 0;
+    struct I2cHalDrvDone *done = (struct I2cHalDrvDone *)bus->private_data;
+
+    SdaHigh(done);
+    GET_SDA(done);
+    I2cDelay(done);
+    for (i = 0; i < 8; i++) {
+        data <<= 1;
+
+        if (SclHigh(done) < 0) {
+            KPrintf("I2cReadb: wait scl pin high "
+                    "timeout at bit %d", 7 - i);
+
+            return -ETIMEOUT;
+        }
+
+        if (GET_SDA(done))
+            data |= 1;
+        SclLow(done);
+        I2cDelay2(done);
+    }
+
+    return data;
+}
+
+static x_size_t I2cSendBytes(struct I2cBus *bus, struct I2cDataStandard *msg)
+{
+    int32 ret;
+    x_size_t bytes = 0;
+    const uint8 *ptr = msg->buf;
+    int32 count = msg->len;
+    uint16 ignore_nack = msg->flags & I2C_IGNORE_NACK;
+
+    while (count > 0) {
+        ret = I2cWriteb(bus, *ptr);
+
+        if ((ret > 0) || (ignore_nack && (ret == 0))) {
+            count --;
+            ptr ++;
+            bytes ++;
+        } else if (ret == 0) {
+            //KPrintf("send bytes: NACK.");
+
+            return 0;
+        } else {
+            KPrintf("send bytes: error %d", ret);
+
+            return ret;
+        }
+    }
+
+    return bytes;
+}
+
+static x_err_t I2cSendAckOrNack(struct I2cBus *bus, int ack)
+{
+    struct I2cHalDrvDone *done = (struct I2cHalDrvDone *)bus->private_data;
+
+    if (ack)
+        SET_SDA(done, 0);
+    I2cDelay(done);
+    if (SclHigh(done) < 0) {
+        KPrintf("ACK or NACK timeout.");
+
+        return -ETIMEOUT;
+    }
+    SclLow(done);
+
+    return EOK;
+}
+
+static x_size_t I2cRecvBytes(struct I2cBus *bus, struct I2cDataStandard *msg)
+{
+    int32 val;
+    int32 bytes = 0;
+    uint8 *ptr = msg->buf;
+    int32 count = msg->len;
+    const uint32 flags = msg->flags;
+
+    while (count > 0) {
+        val = I2cReadb(bus);
+        if (val >= 0) {
+            *ptr = val;
+            bytes ++;
+        } else {
+            break;
+        }
+
+        ptr ++;
+        count --;
+
+        if (!(flags & I2C_NO_READ_ACK)) {
+            val = I2cSendAckOrNack(bus, count);
+            if (val < 0)
+                return val;
+        }
+    }
+
+    return bytes;
+}
+
+static int32 I2cSendAddress(struct I2cBus *bus, uint8 addr, int32 retries)
+{
+    struct I2cHalDrvDone *done = (struct I2cHalDrvDone *)bus->private_data;
+    int32 i;
+    x_err_t ret = 0;
+
+    for (i = 0; i <= retries; i++) {
+        ret = I2cWriteb(bus, addr);
+        if (ret == 1 || i == retries)
+            break;
+        I2cStop(done);
+        I2cDelay2(done);
+        I2cStart(done);
+    }
+
+    return ret;
+}
+
+static x_err_t I2cBitSendAddress(struct I2cBus *bus, struct I2cDataStandard *msg)
+{
+    uint16 flags = msg->flags;
+    uint16 ignore_nack = msg->flags & I2C_IGNORE_NACK;
+    struct I2cHalDrvDone *done = (struct I2cHalDrvDone *)bus->private_data;
+
+    uint8 addr1, addr2;
+    int32 retries;
+    x_err_t ret;
+
+    retries = ignore_nack ? 0 : msg->retries;
+
+    if (flags & I2C_ADDR_10BIT) {
+        addr1 = 0xf0 | ((msg->addr >> 7) & 0x06);
+        addr2 = msg->addr & 0xff;
+
+        //KPrintf("addr1: %d, addr2: %d", addr1, addr2);
+
+        ret = I2cSendAddress(bus, addr1, retries);
+        if ((ret != 1) && !ignore_nack) {
+            //KPrintf("NACK: sending first addr");
+
+            return -EPIO;
+        }
+
+        ret = I2cWriteb(bus, addr2);
+        if ((ret != 1) && !ignore_nack) {
+            //KPrintf("NACK: sending second addr");
+
+            return -EPIO;
+        }
+        if (flags & I2C_RD) {
+            //KPrintf("send repeated start condition");
+            I2cRestart(done);
+            addr1 |= 0x01;
+            ret = I2cSendAddress(bus, addr1, retries);
+            if ((ret != 1) && !ignore_nack) {
+                //KPrintf("NACK: sending repeated addr");
+
+                return -EPIO;
+            }
+        }
+    } else {
+        addr1 = msg->addr << 1;
+        if (flags & I2C_RD)
+            addr1 |= 1;
+        ret = I2cSendAddress(bus, addr1, retries);
+        if ((ret != 1) && !ignore_nack)
+            return -EPIO;
+    }
+
+    return EOK;
+}
+
+static uint32 I2cWriteData(struct I2cHardwareDevice *i2c_dev, struct I2cDataStandard *msg)
+{
+    struct I2cBus *bus = (struct I2cBus *)i2c_dev->haldev.owner_bus;
+    bus->private_data = i2c_dev->haldev.owner_bus->private_data;
+    struct I2cHalDrvDone *done = (struct I2cHalDrvDone *)bus->private_data;
+    int32 ret;
+    int32 i = 0;
+    uint16 ignore_nack;
+
+    I2cStart(done);
+    while (NONE != msg) {
+        ignore_nack = msg->flags & I2C_IGNORE_NACK;
+        if (!(msg->flags & I2C_NO_START)) {
+            if (i) {
+                I2cRestart(done);
+            }
+            ret = I2cBitSendAddress(bus, msg);
+            if ((ret != EOK) && !ignore_nack) {
+                goto out;
+            }
+        }
+        if (msg->flags & I2C_WR) {
+            ret = I2cSendBytes(bus, msg);
+            if (ret >= 1)
+                //KPrintf("write %d byte%s", ret, ret == 1 ? "" : "s");
+            if (ret < msg->len) {
+                if (ret >= 0)
+                    ret = -ERROR;
+                goto out;
+            }
+        }
+        msg = msg->next;
+        i++;
+    }
+    ret = i;
+
+out:
+    I2cStop(done);
+
+    return ret;
+}
+
+static uint32 I2cReadData(struct I2cHardwareDevice *i2c_dev, struct I2cDataStandard *msg)
+{
+    struct I2cBus *bus = (struct I2cBus *)i2c_dev->haldev.owner_bus;
+    bus->private_data = i2c_dev->haldev.owner_bus->private_data;
+    struct I2cHalDrvDone *done = (struct I2cHalDrvDone *)bus->private_data;
+    int32 ret;
+    int32 i = 0;
+    uint16 ignore_nack;
+
+    I2cStart(done);
+    while (NONE != msg) {
+        ignore_nack = msg->flags & I2C_IGNORE_NACK;
+        if (!(msg->flags & I2C_NO_START)) {
+            if (i) {
+                I2cRestart(done);
+            }
+            ret = I2cBitSendAddress(bus, msg);
+            if ((ret != EOK) && !ignore_nack) {
+                goto out;
+            }
+        }
+        if (msg->flags & I2C_RD) {
+            ret = I2cRecvBytes(bus, msg);
+            if (ret >= 1)
+                //KPrintf("read %d byte%s", ret, ret == 1 ? "" : "s");
+            if (ret < msg->len) {
+                if (ret >= 0)
+                    ret = -EPIO;
+                goto out;
+            }
+        }
+        msg = msg->next;
+        i++;
+    }
+    ret = i;
+
+out:
+    I2cStop(done);
+
+    return ret;
+}
+
+static uint32 I2cInit(struct I2cDriver *i2c_drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(i2c_drv);
+
+    struct I2cHardwareDevice *i2c_dev = (struct I2cHardwareDevice *)i2c_drv->driver.owner_bus->owner_haldev;
+
+    if (configure_info->private_data) {
+        i2c_dev->i2c_dev_addr = *((uint16 *)configure_info->private_data);
+        return EOK;
+    }
+    
+    KPrintf("I2cInit need set i2c dev addr\n");
+    return ERROR;
+}
+
+static uint32 I2cDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(drv);
+    NULL_PARAM_CHECK(configure_info);
+
+    x_err_t ret = EOK;
+    struct I2cDriver *i2c_drv = (struct I2cDriver *)drv;
+
+    switch (configure_info->configure_cmd)
+    {
+        case OPE_INT:
+            ret = I2cInit(i2c_drv, configure_info);
+            break;
+        default:
+            break;
+    }
+
+    return ret;
+}
+
+/*manage the i2c device operations*/
+static const struct I2cDevDone i2c_dev_done =
+{
+    .dev_open = NONE,
+    .dev_close = NONE,
+    .dev_write = I2cWriteData,
+    .dev_read = I2cReadData,
+};
+
+/*Init i2c bus*/
+static int BoardI2cBusInit(struct I2cBus *i2c_bus, struct I2cDriver *i2c_driver)
+{
+    x_err_t ret = EOK;
+
+    /*Init the i2c bus */
+    i2c_bus->private_data = (void *)&i2c_hal_drv_done;
+    ret = I2cBusInit(i2c_bus, I2C_BUS_NAME_1);
+    if (EOK != ret) {
+        KPrintf("board_i2c_init I2cBusInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Init the i2c driver*/
+    i2c_driver->private_data = (void *)&i2c_hal_drv_done;
+    ret = I2cDriverInit(i2c_driver, I2C_DRV_NAME_1);
+    if (EOK != ret) {
+        KPrintf("board_i2c_init I2cDriverInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Attach the i2c driver to the i2c bus*/
+    ret = I2cDriverAttachToBus(I2C_DRV_NAME_1, I2C_BUS_NAME_1);
+    if (EOK != ret) {
+        KPrintf("board_i2c_init I2cDriverAttachToBus error %d\n", ret);
+        return ERROR;
+    } 
+
+    return ret;
+}
+
+/*Attach the i2c device to the i2c bus*/
+static int BoardI2cDevBend(void)
+{
+    x_err_t ret = EOK;
+    static struct I2cHardwareDevice i2c_device0;
+    memset(&i2c_device0, 0, sizeof(struct I2cHardwareDevice));
+
+    i2c_device0.i2c_dev_done = &i2c_dev_done;
+
+    ret = I2cDeviceRegister(&i2c_device0, NONE, I2C_1_DEVICE_NAME_0);
+    if (EOK != ret) {
+        KPrintf("board_i2c_init I2cDeviceInit device %s error %d\n", I2C_1_DEVICE_NAME_0, ret);
+        return ERROR;
+    }  
+
+    ret = I2cDeviceAttachToBus(I2C_1_DEVICE_NAME_0, I2C_BUS_NAME_1);
+    if (EOK != ret) {
+        KPrintf("board_i2c_init I2cDeviceAttachToBus device %s error %d\n", I2C_1_DEVICE_NAME_0, ret);
+        return ERROR;
+    }  
+
+    return ret;
+}
+
+/*ARM-32 BOARD I2C INIT*/
+int Stm32HwI2cInit(void)
+{
+    x_err_t ret = EOK;
+    static struct I2cBus i2c_bus;
+    memset(&i2c_bus, 0, sizeof(struct I2cBus));
+
+    static struct I2cDriver i2c_driver;
+    memset(&i2c_driver, 0, sizeof(struct I2cDriver));
+
+#ifdef  BSP_USING_I2C1
+    I2cGpioInit(&i2c_bus_param);
+
+    i2c_driver.configure = I2cDrvConfigure;
+
+    ret = BoardI2cBusInit(&i2c_bus, &i2c_driver);
+    if (EOK != ret) {
+        KPrintf("board_i2c_Init error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardI2cDevBend();
+    if (EOK != ret) {
+        KPrintf("board_i2c_Init error ret %u\n", ret);
+        return ERROR;
+    }   
+
+    I2cBusReset(&i2c_bus_param);
+#endif
+
+    return ret;
+}

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/connect_adc.h

@@ -0,0 +1,37 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_adc.h
+* @brief define aiit-arm32-board adc function and struct
+* @version 1.1
+* @author AIIT XUOS Lab
+* @date 2021-12-28
+*/
+
+#ifndef CONNECT_ADC_H
+#define CONNECT_ADC_H
+
+#include <device.h>
+#include <hardware_adc.h>
+#include <hardware_rcc.h>
+#include <hardware_gpio.h>
+
+struct Stm32HwAdc 
+{
+    ADC_TypeDef *ADCx;
+    uint8 adc_channel;
+};
+
+int Stm32HwAdcInit(void);
+
+#endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/connect_can.h

@@ -0,0 +1,41 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_can.h
+* @brief define aiit-arm32-board can function and struct
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef CONNECT_CAN_H
+#define CONNECT_CAN_H
+
+#include <device.h>
+#include <hardware_can.h>
+
+struct Stm32Can
+{
+    CAN_TypeDef *instance;
+
+    char *bus_name;
+
+    CAN_InitTypeDef init;
+
+    uint8 can_flag;
+    struct CanBus can_bus;
+};
+
+int Stm32HwCanBusInit(void);
+
+#endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/connect_ch438.h

@@ -0,0 +1,278 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_ch438.h
+* @brief define aiit-arm32-board ch438 function and struct
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef CONNECT_CH438_H
+#define CONNECT_CH438_H
+
+#include <board.h>
+#include <device.h>
+
+#define CH438_BUFFSIZE 255
+
+/******************************************************************************************/
+
+/* chip definition */
+/* CH438serial port0 register address */
+
+#define REG_RBR0_ADDR            0x00      /* serial port0receive buffer register address */
+#define REG_THR0_ADDR            0x00      /* serial port0send hold register address */
+#define REG_IER0_ADDR            0x01      /* serial port0interrupt enable register address */
+#define REG_IIR0_ADDR            0x02      /* serial port0interrupt identifies register address */
+#define REG_FCR0_ADDR            0x02      /* serial port0FIFO controls register address */
+#define REG_LCR0_ADDR            0x03      /* serial port0circuit control register address */
+#define REG_MCR0_ADDR            0x04      /* serial port0MODEM controls register address */
+#define REG_LSR0_ADDR            0x05      /* serial port0line status register address */
+#define REG_MSR0_ADDR            0x06      /* serial port0address of MODEM status register */
+#define REG_SCR0_ADDR            0x07      /* serial port0the user can define the register address */
+#define REG_DLL0_ADDR            0x00      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM0_ADDR            0x01      /* Baud rate divisor latch high 8-bit byte address */
+
+/* CH438serial port1 register address */
+
+#define REG_RBR1_ADDR            0x10      /* serial port1receive buffer register address */
+#define REG_THR1_ADDR            0x10      /* serial port1send hold register address */
+#define REG_IER1_ADDR            0x11      /* serial port1interrupt enable register address */
+#define REG_IIR1_ADDR            0x12      /* serial port1interrupt identifies register address */
+#define REG_FCR1_ADDR            0x12      /* serial port1FIFO controls register address */
+#define REG_LCR1_ADDR            0x13      /* serial port1circuit control register address */
+#define REG_MCR1_ADDR            0x14      /* serial port1MODEM controls register address */
+#define REG_LSR1_ADDR            0x15      /* serial port1line status register address */
+#define REG_MSR1_ADDR            0x16      /* serial port1address of MODEM status register */
+#define REG_SCR1_ADDR            0x17      /* serial port1the user can define the register address */
+#define REG_DLL1_ADDR            0x10      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM1_ADDR            0x11      /* Baud rate divisor latch high 8-bit byte address */
+
+
+/* CH438serial port2 register address */
+
+#define REG_RBR2_ADDR            0x20      /* serial port2receive buffer register address */
+#define REG_THR2_ADDR            0x20      /* serial port2send hold register address */
+#define REG_IER2_ADDR            0x21      /* serial port2interrupt enable register address */
+#define REG_IIR2_ADDR            0x22      /* serial port2interrupt identifies register address */
+#define REG_FCR2_ADDR            0x22      /* serial port2FIFO controls register address */
+#define REG_LCR2_ADDR            0x23      /* serial port2circuit control register address */
+#define REG_MCR2_ADDR            0x24      /* serial port2MODEM controls register address */
+#define REG_LSR2_ADDR            0x25      /* serial port2line status register address */
+#define REG_MSR2_ADDR            0x26      /* serial port2address of MODEM status register */
+#define REG_SCR2_ADDR            0x27      /* serial port2the user can define the register address */
+#define REG_DLL2_ADDR            0x20      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM2_ADDR            0x21      /* Baud rate divisor latch high 8-bit byte address */
+
+
+
+/* CH438serial port3 register address */
+
+#define REG_RBR3_ADDR            0x30      /* serial port3receive buffer register address */
+#define REG_THR3_ADDR            0x30      /* serial port3send hold register address */
+#define REG_IER3_ADDR            0x31      /* serial port3interrupt enable register address */
+#define REG_IIR3_ADDR            0x32      /* serial port3interrupt identifies register address */
+#define REG_FCR3_ADDR            0x32      /* serial port3FIFO controls register address */
+#define REG_LCR3_ADDR            0x33      /* serial port3circuit control register address */
+#define REG_MCR3_ADDR            0x34      /* serial port3MODEM controls register address */
+#define REG_LSR3_ADDR            0x35      /* serial port3line status register address */
+#define REG_MSR3_ADDR            0x36      /* serial port3address of MODEM status register */
+#define REG_SCR3_ADDR            0x37      /* serial port3the user can define the register address */
+#define REG_DLL3_ADDR            0x30      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM3_ADDR            0x31      /* Baud rate divisor latch high 8-bit byte address */
+
+
+/* CH438serial port4 register address */
+
+#define REG_RBR4_ADDR            0x08      /* serial port4receive buffer register address */
+#define REG_THR4_ADDR            0x08      /* serial port4send hold register address */
+#define REG_IER4_ADDR            0x09      /* serial port4interrupt enable register address */
+#define REG_IIR4_ADDR            0x0A      /* serial port4interrupt identifies register address */
+#define REG_FCR4_ADDR            0x0A      /* serial port4FIFO controls register address */
+#define REG_LCR4_ADDR            0x0B      /* serial port4circuit control register address */
+#define REG_MCR4_ADDR            0x0C      /* serial port4MODEM controls register address */
+#define REG_LSR4_ADDR            0x0D      /* serial port4line status register address */
+#define REG_MSR4_ADDR            0x0E      /* serial port4address of MODEM status register */
+#define REG_SCR4_ADDR            0x0F      /* serial port4the user can define the register address */
+#define REG_DLL4_ADDR            0x08      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM4_ADDR            0x09      /* Baud rate divisor latch high 8-bit byte address */
+
+
+
+/* CH438serial port5 register address */
+
+#define REG_RBR5_ADDR            0x18      /* serial port5receive buffer register address */
+#define REG_THR5_ADDR            0x18      /* serial port5send hold register address */
+#define REG_IER5_ADDR            0x19      /* serial port5interrupt enable register address */
+#define REG_IIR5_ADDR            0x1A      /* serial port5interrupt identifies register address */
+#define REG_FCR5_ADDR            0x1A      /* serial port5FIFO controls register address */
+#define REG_LCR5_ADDR            0x1B      /* serial port5circuit control register address */
+#define REG_MCR5_ADDR            0x1C      /* serial port5MODEM controls register address */
+#define REG_LSR5_ADDR            0x1D      /* serial port5line status register address */
+#define REG_MSR5_ADDR            0x1E      /* serial port5address of MODEM status register */
+#define REG_SCR5_ADDR            0x1F      /* serial port5the user can define the register address */
+#define REG_DLL5_ADDR            0x18      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM5_ADDR            0x19      /* Baud rate divisor latch high 8-bit byte address */
+
+
+/* CH438serial port6 register address */
+
+#define REG_RBR6_ADDR            0x28      /* serial port6receive buffer register address */
+#define REG_THR6_ADDR            0x28      /* serial port6send hold register address */
+#define REG_IER6_ADDR            0x29      /* serial port6interrupt enable register address */
+#define REG_IIR6_ADDR            0x2A      /* serial port6interrupt identifies register address */
+#define REG_FCR6_ADDR            0x2A      /* serial port6FIFO controls register address */
+#define REG_LCR6_ADDR            0x2B      /* serial port6circuit control register address */
+#define REG_MCR6_ADDR            0x2C      /* serial port6MODEM controls register address */
+#define REG_LSR6_ADDR            0x2D      /* serial port6line status register address */
+#define REG_MSR6_ADDR            0x2E      /* serial port6address of MODEM status register */
+#define REG_SCR6_ADDR            0x2F      /* serial port6the user can define the register address */
+#define REG_DLL6_ADDR            0x28      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM6_ADDR            0x29      /* Baud rate divisor latch high 8-bit byte address */
+
+
+/* CH438serial port7 register address */
+
+#define REG_RBR7_ADDR            0x38      /* serial port7receive buffer register address */
+#define REG_THR7_ADDR            0x38      /* serial port7send hold register address */
+#define REG_IER7_ADDR            0x39      /* serial port7interrupt enable register address */
+#define REG_IIR7_ADDR            0x3A      /* serial port7interrupt identifies register address */
+#define REG_FCR7_ADDR            0x3A      /* serial port7FIFO controls register address */
+#define REG_LCR7_ADDR            0x3B      /* serial port7circuit control register address */
+#define REG_MCR7_ADDR            0x3C      /* serial port7MODEM controls register address */
+#define REG_LSR7_ADDR            0x3D      /* serial port7line status register address */
+#define REG_MSR7_ADDR            0x3E      /* serial port7address of MODEM status register */
+#define REG_SCR7_ADDR            0x3F      /* serial port7the user can define the register address */
+#define REG_DLL7_ADDR            0x38      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM7_ADDR            0x39      /* Baud rate divisor latch high 8-bit byte address */
+
+
+#define REG_SSR_ADDR             0x4F       /* pecial status register address */
+
+
+/* IER register bit */
+
+#define BIT_IER_RESET            0x80      /* The bit is 1 soft reset serial port */
+#define BIT_IER_LOWPOWER         0x40      /* The bit is 1 close serial port internal reference clock */
+#define BIT_IER_SLP              0x20      /* serial port0 is SLP, 1 close clock vibrator  */
+#define BIT_IER1_CK2X            0x20      /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */
+#define BIT_IER_IEMODEM          0x08      /* The bit is 1 allows MODEM input status to interrupt */
+#define BIT_IER_IELINES          0x04      /* The bit is 1 allow receiving line status to be interrupted */
+#define BIT_IER_IETHRE           0x02      /* The bit is 1 allows the send hold register to break in mid-air */
+#define BIT_IER_IERECV           0x01      /* The bit is 1 allows receiving data interrupts */
+
+/* IIR register bit */
+
+#define BIT_IIR_FIFOENS1         0x80
+#define BIT_IIR_FIFOENS0         0x40      /* The two is 1 said use FIFO */
+
+/* Interrupt type: 0001 has no interrupt, 0110 receiving line status is interrupted, 0100 receiving data can be interrupted,
+1100 received data timeout interrupt, 0010THR register air interrupt, 0000MODEM input change interrupt */
+#define BIT_IIR_IID3             0x08
+#define BIT_IIR_IID2             0x04
+#define BIT_IIR_IID1             0x02
+#define BIT_IIR_NOINT            0x01
+
+/* FCR register bit */
+
+/* Trigger point: 00 corresponds to 1 byte, 01 corresponds to 16 bytes, 10 corresponds to 64 bytes, 11 corresponds to 112 bytes */
+#define BIT_FCR_RECVTG1          0x80      /* Set the trigger point for FIFO interruption and automatic hardware flow control */
+#define BIT_FCR_RECVTG0          0x40      /* Set the trigger point for FIFO interruption and automatic hardware flow control */
+
+#define BIT_FCR_TFIFORST         0x04      /* The bit is 1 empty the data sent in FIFO */
+#define BIT_FCR_RFIFORST         0x02      /* The bit is 1 empty the data sent in FIFO */
+#define BIT_FCR_FIFOEN           0x01      /* The bit is 1 use FIFO, 0 disable FIFO */
+
+/* LCR register bit */
+
+#define BIT_LCR_DLAB             0x80      /* To access DLL, DLM, 0 to access RBR/THR/IER */
+#define BIT_LCR_BREAKEN          0x40      /* 1 forces a BREAK line interval*/
+
+/* Set the check format: when PAREN is 1, 00 odd check, 01 even check, 10 MARK (set 1), 11 blank (SPACE, clear 0) */
+#define BIT_LCR_PARMODE1         0x20      /* Sets the parity bit format */
+#define BIT_LCR_PARMODE0         0x10      /* Sets the parity bit format */
+
+#define BIT_LCR_PAREN            0x08      /* A value of 1 allows you to generate and receive parity bits when sending */
+#define BIT_LCR_STOPBIT          0x04      /* If is 1, then two stop bits, is 0, a stop bit */
+
+/* Set word length: 00 for 5 data bits, 01 for 6 data bits, 10 for 7 data bits and 11 for 8 data bits */
+#define BIT_LCR_WORDSZ1          0x02      /* Set the word length length */
+#define BIT_LCR_WORDSZ0          0x01
+
+/* MCR register bit */
+
+#define BIT_MCR_AFE              0x20      /* For 1 allows automatic flow control of CTS and RTS hardware */
+#define BIT_MCR_LOOP             0x10      /* Is the test mode of 1 enabling internal loop */
+#define BIT_MCR_OUT2             0x08      /* 1 Allows an interrupt request for the serial port output  */
+#define BIT_MCR_OUT1             0x04      /* The MODEM control bit defined for the user */
+#define BIT_MCR_RTS              0x02      /* The bit is 1 RTS pin  output  effective  */
+#define BIT_MCR_DTR              0x01      /* The bit is 1 DTR pin  output  effective  */
+
+/* LSR register bit */
+
+#define BIT_LSR_RFIFOERR         0x80      /* 1 said There is at least one error in receiving FIFO */
+#define BIT_LSR_TEMT             0x40      /* 1 said THR and TSR are empty */
+#define BIT_LSR_THRE             0x20      /* 1 said THR is empty*/
+#define BIT_LSR_BREAKINT         0x10      /* The bit is 1 said the BREAK line interval was detected*/
+#define BIT_LSR_FRAMEERR         0x08      /* The bit is 1 said error reading data frame */
+#define BIT_LSR_PARERR           0x04      /* The bit is 1 said parity error */
+#define BIT_LSR_OVERR            0x02      /*  1 said receive FIFO buffer overflow */
+#define BIT_LSR_DATARDY          0x01      /* The bit is 1 said receive data received in FIFO */
+
+/* MSR register bit */
+
+#define BIT_MSR_DCD              0x80      /* The bit is 1 said DCD pin  effective  */
+#define BIT_MSR_RI               0x40      /* The bit is 1 said RI pin  effective  */
+#define BIT_MSR_DSR              0x20      /* The bit is 1 said DSR pin  effective  */
+#define BIT_MSR_CTS              0x10      /* The bit is 1 said CTS pin  effective  */
+#define BIT_MSR_DDCD             0x08      /* The bit is 1 said DCD pin The input state has changed */
+#define BIT_MSR_TERI             0x04      /* The bit is 1 said RI pin The input state has changed */
+#define BIT_MSR_DDSR             0x02      /* The bit is 1 said DSR pin The input state has changed */
+#define BIT_MSR_DCTS             0x01      /* The bit is 1 said CTS pin The input state has changed */
+
+/* Interrupt status code */
+
+#define INT_NOINT                    0x01      /* There is no interruption */
+#define INT_THR_EMPTY                0x02      /* THR empty interruption */
+#define INT_RCV_OVERTIME             0x0C      /* Receive timeout interrupt */
+#define INT_RCV_SUCCESS              0x04      /* Interrupts are available to receive data */
+#define INT_RCV_LINES                0x06      /* Receiving line status interrupted */
+#define INT_MODEM_CHANGE             0x00      /* MODEM input changes interrupt */
+
+#define CH438_IIR_FIFOS_ENABLED      0xC0  /* use FIFO */
+
+#define Fpclk                 1843200         /* Define the internal clock frequency  */
+
+#define CH438_D0_PIN	      1
+#define CH438_D1_PIN	      2
+#define CH438_D2_PIN	      3
+#define CH438_D3_PIN	      4
+#define CH438_D4_PIN	      5
+#define CH438_D5_PIN	      18
+#define CH438_D6_PIN	      19
+#define CH438_D7_PIN	      20
+#define CH438_NWR_PIN	      44
+#define CH438_NRD_PIN	      45
+#define CH438_NCS_PIN	      47
+#define CH438_ALE_PIN	      48
+#define CH438_INT_PIN	      7
+#define	DIR_485CH1_PIN	      22	//485ch1 = ext_uart3
+#define	DIR_485CH2_PIN	      21	//485ch2 = ext_uart2
+#define	DIR_485CH3_PIN	      123	//485ch3 = ext_uart7
+
+void CH438RegTest(unsigned char num);
+void Set485Input(uint8 ch_no);
+void Set485Output(uint8 ch_no);
+
+#endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/connect_dac.h

@@ -0,0 +1,37 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_dac.h
+* @brief define aiit-arm32-board adc function and struct
+* @version 2.0
+* @author AIIT XUOS Lab
+* @date 2022-1-10
+*/
+
+#ifndef CONNECT_DAC_H
+#define CONNECT_DAC_H
+
+#include <device.h>
+#include <hardware_dac.h>
+#include <hardware_rcc.h>
+#include <hardware_gpio.h>
+
+struct Stm32HwDac 
+{
+    DAC_TypeDef *DACx;
+    uint16 digital_data;
+};
+
+int Stm32HwDacInit(void);
+
+#endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/connect_extmem.h

@@ -0,0 +1,36 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_extmem.h
+* @brief declare aiit-arm32-board extmem fsmc function
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-05-28
+*/
+
+#ifndef CONNECT_EXTMEM_H
+#define CONNECT_EXTMEM_H
+
+#include <xsconfig.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int HwSramInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/connect_gpio.h

@@ -0,0 +1,88 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_gpio.h
+* @brief define aiit-arm32-board gpio function and struct
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef CONNECT_GPIO_H
+#define CONNECT_GPIO_H
+
+#include <device.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BITBAND(addr, bitnum) ((addr & 0xF0000000)+0x2000000+((addr &0xFFFFF)<<5)+(bitnum<<2)) 
+#define MEM_ADDR(addr)  (*((volatile unsigned long  *)(addr))) 
+#define BIT_ADDR(addr, bitnum)   MEM_ADDR(BITBAND(addr, bitnum)) 
+
+#define GPIOA_ODR_Addr    (GPIOA_BASE+20) //0x40020014
+#define GPIOB_ODR_Addr    (GPIOB_BASE+20) //0x40020414 
+#define GPIOC_ODR_Addr    (GPIOC_BASE+20) //0x40020814 
+#define GPIOD_ODR_Addr    (GPIOD_BASE+20) //0x40020C14 
+#define GPIOE_ODR_Addr    (GPIOE_BASE+20) //0x40021014 
+#define GPIOF_ODR_Addr    (GPIOF_BASE+20) //0x40021414    
+#define GPIOG_ODR_Addr    (GPIOG_BASE+20) //0x40021814   
+#define GPIOH_ODR_Addr    (GPIOH_BASE+20) //0x40021C14    
+#define GPIOI_ODR_Addr    (GPIOI_BASE+20) //0x40022014     
+
+#define GPIOA_IDR_Addr    (GPIOA_BASE+16) //0x40020010 
+#define GPIOB_IDR_Addr    (GPIOB_BASE+16) //0x40020410 
+#define GPIOC_IDR_Addr    (GPIOC_BASE+16) //0x40020810 
+#define GPIOD_IDR_Addr    (GPIOD_BASE+16) //0x40020C10 
+#define GPIOE_IDR_Addr    (GPIOE_BASE+16) //0x40021010 
+#define GPIOF_IDR_Addr    (GPIOF_BASE+16) //0x40021410 
+#define GPIOG_IDR_Addr    (GPIOG_BASE+16) //0x40021810 
+#define GPIOH_IDR_Addr    (GPIOH_BASE+16) //0x40021C10 
+#define GPIOI_IDR_Addr    (GPIOI_BASE+16) //0x40022010 
+ 
+
+#define PAout(n)   BIT_ADDR(GPIOA_ODR_Addr,n)  //output 
+#define PAin(n)      BIT_ADDR(GPIOA_IDR_Addr,n)  //input 
+
+#define PBout(n)   BIT_ADDR(GPIOB_ODR_Addr,n)  //output 
+#define PBin(n)      BIT_ADDR(GPIOB_IDR_Addr,n)  //input 
+
+#define PCout(n)   BIT_ADDR(GPIOC_ODR_Addr,n)  //output 
+#define PCin(n)      BIT_ADDR(GPIOC_IDR_Addr,n)  //input 
+
+#define PDout(n)   BIT_ADDR(GPIOD_ODR_Addr,n)  //output 
+#define PDin(n)      BIT_ADDR(GPIOD_IDR_Addr,n)  //input 
+
+#define PEout(n)   BIT_ADDR(GPIOE_ODR_Addr,n)  //output 
+#define PEin(n)      BIT_ADDR(GPIOE_IDR_Addr,n)  //input
+
+#define PFout(n)   BIT_ADDR(GPIOF_ODR_Addr,n)  //output 
+#define PFin(n)      BIT_ADDR(GPIOF_IDR_Addr,n)  //input
+
+#define PGout(n)   BIT_ADDR(GPIOG_ODR_Addr,n)  //output 
+#define PGin(n)      BIT_ADDR(GPIOG_IDR_Addr,n)  //input
+
+#define PHout(n)   BIT_ADDR(GPIOH_ODR_Addr,n)  //output 
+#define PHin(n)      BIT_ADDR(GPIOH_IDR_Addr,n)  //input
+
+#define PIout(n)   BIT_ADDR(GPIOI_ODR_Addr,n)  //output 
+#define PIin(n)      BIT_ADDR(GPIOI_IDR_Addr,n)  //input
+
+int Stm32HwGpioInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/connect_hwtimer.h

@@ -0,0 +1,36 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_hwtimer.h
+* @brief define aiit-arm32-board hwtimer function and struct
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef CONNECT_HWTIMER_H
+#define CONNECT_HWTIMER_H
+
+#include <device.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int Stm32HwtimerInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/connect_i2c.h

@@ -0,0 +1,37 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_i2c.h
+* @brief define aiit-arm32-board i2c function and struct
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef CONNECT_I2C_H
+#define CONNECT_I2C_H
+
+#include <device.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int Stm32Udelay(uint32 us);
+int Stm32HwI2cInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/connect_lcd.h

@@ -0,0 +1,164 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_lcd.h
+* @brief declare aiit-arm32-board lcd fsmc function
+* @version 2.0 
+* @author AIIT XUOS Lab
+* @date 2022-1-12
+*/
+
+#ifndef CONNECT_LCD_H
+#define CONNECT_LCD_H
+
+#include <device.h>
+#include <font.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ILI9341 0x9341
+
+#define NO_OPERATION                  0x00
+#define SOFTWARE_RESET                0x01
+#define READ_ID                       0x04
+#define READ_STATUS                   0x09
+#define READ_POWER_MODE               0x0A
+#define READ_MADCTL                   0x0B
+#define READ_PIXEL_FORMAT             0x0C
+#define READ_IMAGE_FORMAT             0x0D
+#define READ_SIGNAL_MODE              0x0E
+#define READ_SELT_DIAG_RESULT         0x0F
+#define SLEEP_ON                      0x10
+#define SLEEP_OFF                     0x11
+#define PARTIAL_DISPALY_ON            0x12
+#define NORMAL_DISPALY_ON             0x13
+#define INVERSION_DISPALY_OFF         0x20
+#define INVERSION_DISPALY_ON          0x21
+#define GAMMA_SET                     0x26
+#define DISPALY_OFF                   0x28
+#define DISPALY_ON                    0x29
+#define HORIZONTAL_ADDRESS_SET        0x2A
+#define VERTICAL_ADDRESS_SET          0x2B
+#define MEMORY_WRITE                  0x2C
+#define COLOR_SET                     0x2D
+#define MEMORY_READ                   0x2E
+#define PARTIAL_AREA                  0x30
+#define VERTICAL_SCROL_DEFINE         0x33
+#define TEAR_EFFECT_LINE_OFF          0x34
+#define TEAR_EFFECT_LINE_ON           0x35
+#define MEMORY_ACCESS_CTL             0x36
+#define VERTICAL_SCROL_S_ADD          0x37
+#define IDLE_MODE_OFF                 0x38
+#define IDLE_MODE_ON                  0x39
+#define PIXEL_FORMAT_SET              0x3A
+#define WRITE_MEMORY_CONTINUE         0x3C
+#define READ_MEMORY_CONTINUE          0x3E
+#define SET_TEAR_SCANLINE             0x44
+#define GET_SCANLINE                  0x45
+#define WRITE_BRIGHTNESS              0x51
+#define READ_BRIGHTNESS               0x52
+#define WRITE_CTRL_DISPALY            0x53
+#define READ_CTRL_DISPALY             0x54
+#define WRITE_BRIGHTNESS_CTL          0x55
+#define READ_BRIGHTNESS_CTL           0x56
+#define WRITE_MIN_BRIGHTNESS          0x5E
+#define READ_MIN_BRIGHTNESS           0x5F
+#define READ_ID1                      0xDA
+#define READ_ID2                      0xDB
+#define READ_ID3                      0xDC
+#define RGB_IF_SIGNAL_CTL             0xB0
+#define NORMAL_FRAME_CTL              0xB1
+#define IDLE_FRAME_CTL                0xB2
+#define PARTIAL_FRAME_CTL             0xB3
+#define INVERSION_CTL                 0xB4
+#define BLANK_PORCH_CTL               0xB5
+#define DISPALY_FUNCTION_CTL          0xB6
+#define ENTRY_MODE_SET                0xB7
+#define BACKLIGHT_CTL1                0xB8
+#define BACKLIGHT_CTL2                0xB9
+#define BACKLIGHT_CTL3                0xBA
+#define BACKLIGHT_CTL4                0xBB
+#define BACKLIGHT_CTL5                0xBC
+#define BACKLIGHT_CTL7                0xBE
+#define BACKLIGHT_CTL8                0xBF
+#define POWER_CTL1                    0xC0
+#define POWER_CTL2                    0xC1
+#define VCOM_CTL1                     0xC5
+#define VCOM_CTL2                     0xC7
+#define NV_MEMORY_WRITE               0xD0
+#define NV_MEMORY_PROTECT_KEY         0xD1
+#define NV_MEMORY_STATUS_READ         0xD2
+#define READ_ID4                      0xD3
+#define POSITIVE_GAMMA_CORRECT        0xE0
+#define NEGATIVE_GAMMA_CORRECT        0xE1
+#define DIGITAL_GAMMA_CTL1            0xE2
+#define DIGITAL_GAMMA_CTL2            0xE3
+#define INTERFACE_CTL                 0xF6
+
+#define LCD_VERTICAL_SCEEN 0
+#define LCD_HORIZONTAL_SCEEN 1
+
+//LCD Scan Direction
+#define L2R_U2D  0 //from left to right , from up to down
+#define L2R_D2U  1 
+#define R2L_U2D  2 
+#define R2L_D2U  3 
+
+#define U2D_L2R  4 
+#define U2D_R2L  5 
+#define D2U_L2R  6 
+#define D2U_R2L  7 	 
+
+#define DFT_SCAN_DIR  U2D_R2L  //default scan direction
+
+#define FSMC_BANK1_NORSRAM4_START_ADDRESS 0x6C000000
+#define FSMC_BANK1_NORSRAM4_DATA_WIDTH 16
+#define STM32_FSMC_OFFSET 0x0000007E
+
+typedef struct
+{
+	volatile uint16_t LCD_REG_CMD;//0x6C00007E, ADDR_A6 = 0, RS =0, write CMD
+	volatile uint16_t LCD_RAM_DATA;//0x6C000080, ADDR_A6 =1, RS = 1, write DATA
+} LCD_TypeDef;
+		    
+#ifndef AIIT_BOARD_LCD_BASE            
+#define AIIT_BOARD_LCD_BASE  ((uint32_t)(FSMC_BANK1_NORSRAM4_START_ADDRESS | STM32_FSMC_OFFSET))
+#define AIIT_BOARD_LCD       ((LCD_TypeDef *) AIIT_BOARD_LCD_BASE)
+#endif
+
+typedef struct 
+{ 
+    uint16_t width;
+    uint16_t height;
+    uint16_t lcd_id;
+    uint8_t lcd_direction; //0，Vertical screen；1，Horizontal screen
+    uint16_t write_ram_cmd;
+    uint16_t set_x_cmd;
+    uint16_t set_y_cmd;
+} LCD_PARAM;
+
+struct Stm32HwLcd
+{
+    LCD_TypeDef *LCD;
+    LCD_PARAM lcd_param;
+};
+
+int Stm32HwLcdInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/connect_rtc.h

@@ -0,0 +1,38 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_i2c.h
+* @brief define aiit-arm32-board i2c function and struct
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef CONNECT_RTC_H
+#define CONNECT_RTC_H
+
+#include <device.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RTC_CLOCK_SOURCE_LSI
+
+int Stm32HwRtcInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/connect_sdio.h

@@ -0,0 +1,38 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_sdio.h
+* @brief define aiit-arm32-board sdio function and struct
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+ 
+#ifndef CONNECT_SDIO_H
+#define CONNECT_SDIO_H
+
+#include <device.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SDIO_DMA_MODE 1
+
+int HwSdioInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/connect_spi.h

@@ -0,0 +1,78 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_spi.h
+* @brief define aiit-arm32-board spi function and struct
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef CONNECT_SPI_H
+#define CONNECT_SPI_H
+
+#include <device.h>
+#include <hardware_spi.h>
+#include <hardware_dma.h>
+#include <stm32f4xx.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SPI_USING_RX_DMA_FLAG   (1<<0)
+#define SPI_USING_TX_DMA_FLAG   (1<<1)
+
+struct Stm32HwSpiCs
+{
+    GPIO_TypeDef* GPIOx;
+    uint16_t GPIO_Pin;
+};
+
+struct Stm32SpiDma
+{
+    uint32_t dma_rcc;
+    DMA_Stream_TypeDef *instance;
+    uint32 channel;
+    IRQn_Type dma_irq;
+    DMA_InitTypeDef init;
+    x_size_t setting_len;
+    x_size_t last_index;
+};
+
+struct Stm32Spi
+{
+    SPI_TypeDef *instance;
+
+    char *bus_name;
+
+    SPI_InitTypeDef init;
+
+    struct
+    {
+        struct Stm32SpiDma dma_rx;
+        struct Stm32SpiDma dma_tx;
+    }dma;
+
+    uint8 spi_dma_flag;
+    struct SpiBus spi_bus;
+};
+
+int Stm32HwSpiInit(void);
+x_err_t HwSpiDeviceAttach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/connect_spi_lora.h

@@ -0,0 +1,63 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_spi_lora.h
+* @brief define spi lora dev function and struct using bus driver framework
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-24
+*/
+
+#ifndef CONNECT_SPI_LORA_H
+#define CONNECT_SPI_LORA_H
+
+#include <bus.h>
+#include <connect_spi.h>
+#include <device.h>
+#include <radio.h>
+#include <hardware_gpio.h>
+#include <stm32f4xx.h>
+#include <spi_lora_sx12xx.h>
+#include <sx1276.h>
+#include <sx1276-Hal.h>
+#include <sx1276-LoRa.h>
+#include <sx1276-LoRaMisc.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SPI_LORA_FREQUENCY 10000000
+#define SPI_LORA_BUFFER_SIZE 256
+
+typedef struct SpiLoraDevice *SpiLoraDeviceType;
+
+struct LoraDevDone
+{
+    uint32 (*open) (void *dev);
+    uint32 (*close) (void *dev);
+    uint32 (*write) (void *dev, struct BusBlockWriteParam *write_param);
+    uint32 (*read) (void *dev, struct BusBlockReadParam *read_param);
+};
+
+struct SpiLoraDevice
+{
+    struct SpiHardwareDevice *spi_dev;
+    struct SpiHardwareDevice lora_dev;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/connect_touch.h

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) Guangzhou Xingyi Electronic  Technology Co., Ltd
+ *
+ * Change Logs:
+ * Date                     Author              Notes
+ * 2014-5-7        alientek team   first version
+ */
+
+/**
+* @file connect_touch.c
+* @brief support aiit-arm32-board touch function and register to bus framework
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+#ifndef CONNECT_TOUCH_H
+#define CONNECT_TOUCH_H
+
+#include <device.h>
+#include <stm32f4xx.h>
+
+#define TP_PRES_DOWN 0x80  
+#define TP_CATH_PRES   0x40  
+
+//touch screen control struct
+typedef struct
+{
+	u16 x; 	
+	u16 y;					
+	u8  sta;								
+	float xfac;					
+	float yfac;
+	short xoff;
+	short yoff;	   
+	u8 touchtype;
+}touch_device_info;
+
+extern touch_device_info tp_dev;	 	
+
+//save data struct
+typedef struct 
+{
+	s32  ty_xfac;
+	s32  ty_yfac;
+	short  x_pos;
+	short  y_pos;
+	u8  iic_touchtype;        
+	u8  iic_flag;              
+}TP_modify_save;
+
+//io pin define
+#define PEN  	    	          PDin(6)  	
+#define  T_MISO	              PBin(4)   	
+#define T_MOSI 	        	  PBout(5)  
+#define T_CLK 	         	    PBout(3)  	
+#define TCS  	 	               PGout(13)  	
+   
+int Stm32HwTouchBusInit(void);
+
+#endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/connect_usart.h

@@ -0,0 +1,63 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_usart.h
+* @brief define aiit-arm32-board usart function and struct
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef CONNECT_USART_H
+#define CONNECT_USART_H
+
+#include <device.h>
+#include <hardware_dma.h>
+#include <hardware_usart.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define KERNEL_CONSOLE_BUS_NAME       SERIAL_BUS_NAME_1
+#define KERNEL_CONSOLE_DRV_NAME        SERIAL_DRV_NAME_1
+#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_1_DEVICE_NAME_0
+
+struct UsartHwCfg
+{
+    USART_TypeDef *uart_device;
+    IRQn_Type irq;
+};
+
+struct Stm32Usart
+{
+    struct Stm32UsartDma
+    {
+        DMA_Stream_TypeDef *RxStream;
+        uint32 RxCh;
+        uint32 RxFlag;
+        uint8 RxIrqCh;
+        x_size_t SettingRecvLen;
+        x_size_t LastRecvIndex;
+    } dma;
+
+    struct SerialBus serial_bus;
+};
+
+int Stm32HwUsartInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/connect_usb.h

@@ -0,0 +1,36 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_usb.h
+* @brief define aiit-arm32-board usb function and struct
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef CONNECT_USB_H
+#define CONNECT_USB_H
+
+#include <device.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int Stm32HwUsbInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/connect_wdg.h

@@ -0,0 +1,36 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_wdg.h
+* @brief define aiit-arm32-board watchdog function and struct
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef CONNECT_WDG_H
+#define CONNECT_WDG_H
+
+#include <device.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int HwWdtInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/font.h

@@ -0,0 +1,323 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file font.h
+* @brief support font for lcd
+* @version 2.0 
+* @author AIIT XUOS Lab
+* @date 2022-1-13
+*/
+
+#ifndef FONT_H
+#define FONT_H 	   
+//ASCII char table
+//offset 32
+//ASCII char: !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~
+//3 ASCII char table（12*12、16*16和24*24）。
+//bytes of a single char:(size/8+((size%8)?1:0))*(size/2), size:code table size(12/16/24...)
+ 
+//12*12 ASCII code
+const unsigned char asc2_1206[95][12]={
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*" ",0*/
+{0x00,0x00,0x00,0x00,0x3F,0x40,0x00,0x00,0x00,0x00,0x00,0x00},/*"!",1*/
+{0x00,0x00,0x30,0x00,0x40,0x00,0x30,0x00,0x40,0x00,0x00,0x00},/*""",2*/
+{0x09,0x00,0x0B,0xC0,0x3D,0x00,0x0B,0xC0,0x3D,0x00,0x09,0x00},/*"#",3*/
+{0x18,0xC0,0x24,0x40,0x7F,0xE0,0x22,0x40,0x31,0x80,0x00,0x00},/*"$",4*/
+{0x18,0x00,0x24,0xC0,0x1B,0x00,0x0D,0x80,0x32,0x40,0x01,0x80},/*"%",5*/
+{0x03,0x80,0x1C,0x40,0x27,0x40,0x1C,0x80,0x07,0x40,0x00,0x40},/*"&",6*/
+{0x10,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",7*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x80,0x20,0x40,0x40,0x20},/*"(",8*/
+{0x00,0x00,0x40,0x20,0x20,0x40,0x1F,0x80,0x00,0x00,0x00,0x00},/*")",9*/
+{0x09,0x00,0x06,0x00,0x1F,0x80,0x06,0x00,0x09,0x00,0x00,0x00},/*"*",10*/
+{0x04,0x00,0x04,0x00,0x3F,0x80,0x04,0x00,0x04,0x00,0x00,0x00},/*"+",11*/
+{0x00,0x10,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*",",12*/
+{0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x00,0x00},/*"-",13*/
+{0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*".",14*/
+{0x00,0x20,0x01,0xC0,0x06,0x00,0x38,0x00,0x40,0x00,0x00,0x00},/*"/",15*/
+{0x1F,0x80,0x20,0x40,0x20,0x40,0x20,0x40,0x1F,0x80,0x00,0x00},/*"0",16*/
+{0x00,0x00,0x10,0x40,0x3F,0xC0,0x00,0x40,0x00,0x00,0x00,0x00},/*"1",17*/
+{0x18,0xC0,0x21,0x40,0x22,0x40,0x24,0x40,0x18,0x40,0x00,0x00},/*"2",18*/
+{0x10,0x80,0x20,0x40,0x24,0x40,0x24,0x40,0x1B,0x80,0x00,0x00},/*"3",19*/
+{0x02,0x00,0x0D,0x00,0x11,0x00,0x3F,0xC0,0x01,0x40,0x00,0x00},/*"4",20*/
+{0x3C,0x80,0x24,0x40,0x24,0x40,0x24,0x40,0x23,0x80,0x00,0x00},/*"5",21*/
+{0x1F,0x80,0x24,0x40,0x24,0x40,0x34,0x40,0x03,0x80,0x00,0x00},/*"6",22*/
+{0x30,0x00,0x20,0x00,0x27,0xC0,0x38,0x00,0x20,0x00,0x00,0x00},/*"7",23*/
+{0x1B,0x80,0x24,0x40,0x24,0x40,0x24,0x40,0x1B,0x80,0x00,0x00},/*"8",24*/
+{0x1C,0x00,0x22,0xC0,0x22,0x40,0x22,0x40,0x1F,0x80,0x00,0x00},/*"9",25*/
+{0x00,0x00,0x00,0x00,0x08,0x40,0x00,0x00,0x00,0x00,0x00,0x00},/*":",26*/
+{0x00,0x00,0x00,0x00,0x04,0x60,0x00,0x00,0x00,0x00,0x00,0x00},/*";",27*/
+{0x00,0x00,0x04,0x00,0x0A,0x00,0x11,0x00,0x20,0x80,0x40,0x40},/*"<",28*/
+{0x09,0x00,0x09,0x00,0x09,0x00,0x09,0x00,0x09,0x00,0x00,0x00},/*"=",29*/
+{0x00,0x00,0x40,0x40,0x20,0x80,0x11,0x00,0x0A,0x00,0x04,0x00},/*">",30*/
+{0x18,0x00,0x20,0x00,0x23,0x40,0x24,0x00,0x18,0x00,0x00,0x00},/*"?",31*/
+{0x1F,0x80,0x20,0x40,0x27,0x40,0x29,0x40,0x1F,0x40,0x00,0x00},/*"@",32*/
+{0x00,0x40,0x07,0xC0,0x39,0x00,0x0F,0x00,0x01,0xC0,0x00,0x40},/*"A",33*/
+{0x20,0x40,0x3F,0xC0,0x24,0x40,0x24,0x40,0x1B,0x80,0x00,0x00},/*"B",34*/
+{0x1F,0x80,0x20,0x40,0x20,0x40,0x20,0x40,0x30,0x80,0x00,0x00},/*"C",35*/
+{0x20,0x40,0x3F,0xC0,0x20,0x40,0x20,0x40,0x1F,0x80,0x00,0x00},/*"D",36*/
+{0x20,0x40,0x3F,0xC0,0x24,0x40,0x2E,0x40,0x30,0xC0,0x00,0x00},/*"E",37*/
+{0x20,0x40,0x3F,0xC0,0x24,0x40,0x2E,0x00,0x30,0x00,0x00,0x00},/*"F",38*/
+{0x0F,0x00,0x10,0x80,0x20,0x40,0x22,0x40,0x33,0x80,0x02,0x00},/*"G",39*/
+{0x20,0x40,0x3F,0xC0,0x04,0x00,0x04,0x00,0x3F,0xC0,0x20,0x40},/*"H",40*/
+{0x20,0x40,0x20,0x40,0x3F,0xC0,0x20,0x40,0x20,0x40,0x00,0x00},/*"I",41*/
+{0x00,0x60,0x20,0x20,0x20,0x20,0x3F,0xC0,0x20,0x00,0x20,0x00},/*"J",42*/
+{0x20,0x40,0x3F,0xC0,0x24,0x40,0x0B,0x00,0x30,0xC0,0x20,0x40},/*"K",43*/
+{0x20,0x40,0x3F,0xC0,0x20,0x40,0x00,0x40,0x00,0x40,0x00,0xC0},/*"L",44*/
+{0x3F,0xC0,0x3C,0x00,0x03,0xC0,0x3C,0x00,0x3F,0xC0,0x00,0x00},/*"M",45*/
+{0x20,0x40,0x3F,0xC0,0x0C,0x40,0x23,0x00,0x3F,0xC0,0x20,0x00},/*"N",46*/
+{0x1F,0x80,0x20,0x40,0x20,0x40,0x20,0x40,0x1F,0x80,0x00,0x00},/*"O",47*/
+{0x20,0x40,0x3F,0xC0,0x24,0x40,0x24,0x00,0x18,0x00,0x00,0x00},/*"P",48*/
+{0x1F,0x80,0x21,0x40,0x21,0x40,0x20,0xE0,0x1F,0xA0,0x00,0x00},/*"Q",49*/
+{0x20,0x40,0x3F,0xC0,0x24,0x40,0x26,0x00,0x19,0xC0,0x00,0x40},/*"R",50*/
+{0x18,0xC0,0x24,0x40,0x24,0x40,0x22,0x40,0x31,0x80,0x00,0x00},/*"S",51*/
+{0x30,0x00,0x20,0x40,0x3F,0xC0,0x20,0x40,0x30,0x00,0x00,0x00},/*"T",52*/
+{0x20,0x00,0x3F,0x80,0x00,0x40,0x00,0x40,0x3F,0x80,0x20,0x00},/*"U",53*/
+{0x20,0x00,0x3E,0x00,0x01,0xC0,0x07,0x00,0x38,0x00,0x20,0x00},/*"V",54*/
+{0x38,0x00,0x07,0xC0,0x3C,0x00,0x07,0xC0,0x38,0x00,0x00,0x00},/*"W",55*/
+{0x20,0x40,0x39,0xC0,0x06,0x00,0x39,0xC0,0x20,0x40,0x00,0x00},/*"X",56*/
+{0x20,0x00,0x38,0x40,0x07,0xC0,0x38,0x40,0x20,0x00,0x00,0x00},/*"Y",57*/
+{0x30,0x40,0x21,0xC0,0x26,0x40,0x38,0x40,0x20,0xC0,0x00,0x00},/*"Z",58*/
+{0x00,0x00,0x00,0x00,0x7F,0xE0,0x40,0x20,0x40,0x20,0x00,0x00},/*"[",59*/
+{0x00,0x00,0x70,0x00,0x0C,0x00,0x03,0x80,0x00,0x40,0x00,0x00},/*"\",60*/
+{0x00,0x00,0x40,0x20,0x40,0x20,0x7F,0xE0,0x00,0x00,0x00,0x00},/*"]",61*/
+{0x00,0x00,0x20,0x00,0x40,0x00,0x20,0x00,0x00,0x00,0x00,0x00},/*"^",62*/
+{0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10},/*"_",63*/
+{0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"`",64*/
+{0x00,0x00,0x02,0x80,0x05,0x40,0x05,0x40,0x03,0xC0,0x00,0x40},/*"a",65*/
+{0x20,0x00,0x3F,0xC0,0x04,0x40,0x04,0x40,0x03,0x80,0x00,0x00},/*"b",66*/
+{0x00,0x00,0x03,0x80,0x04,0x40,0x04,0x40,0x06,0x40,0x00,0x00},/*"c",67*/
+{0x00,0x00,0x03,0x80,0x04,0x40,0x24,0x40,0x3F,0xC0,0x00,0x40},/*"d",68*/
+{0x00,0x00,0x03,0x80,0x05,0x40,0x05,0x40,0x03,0x40,0x00,0x00},/*"e",69*/
+{0x00,0x00,0x04,0x40,0x1F,0xC0,0x24,0x40,0x24,0x40,0x20,0x00},/*"f",70*/
+{0x00,0x00,0x02,0xE0,0x05,0x50,0x05,0x50,0x06,0x50,0x04,0x20},/*"g",71*/
+{0x20,0x40,0x3F,0xC0,0x04,0x40,0x04,0x00,0x03,0xC0,0x00,0x40},/*"h",72*/
+{0x00,0x00,0x04,0x40,0x27,0xC0,0x00,0x40,0x00,0x00,0x00,0x00},/*"i",73*/
+{0x00,0x10,0x00,0x10,0x04,0x10,0x27,0xE0,0x00,0x00,0x00,0x00},/*"j",74*/
+{0x20,0x40,0x3F,0xC0,0x01,0x40,0x07,0x00,0x04,0xC0,0x04,0x40},/*"k",75*/
+{0x20,0x40,0x20,0x40,0x3F,0xC0,0x00,0x40,0x00,0x40,0x00,0x00},/*"l",76*/
+{0x07,0xC0,0x04,0x00,0x07,0xC0,0x04,0x00,0x03,0xC0,0x00,0x00},/*"m",77*/
+{0x04,0x40,0x07,0xC0,0x04,0x40,0x04,0x00,0x03,0xC0,0x00,0x40},/*"n",78*/
+{0x00,0x00,0x03,0x80,0x04,0x40,0x04,0x40,0x03,0x80,0x00,0x00},/*"o",79*/
+{0x04,0x10,0x07,0xF0,0x04,0x50,0x04,0x40,0x03,0x80,0x00,0x00},/*"p",80*/
+{0x00,0x00,0x03,0x80,0x04,0x40,0x04,0x50,0x07,0xF0,0x00,0x10},/*"q",81*/
+{0x04,0x40,0x07,0xC0,0x02,0x40,0x04,0x00,0x04,0x00,0x00,0x00},/*"r",82*/
+{0x00,0x00,0x06,0x40,0x05,0x40,0x05,0x40,0x04,0xC0,0x00,0x00},/*"s",83*/
+{0x00,0x00,0x04,0x00,0x1F,0x80,0x04,0x40,0x00,0x40,0x00,0x00},/*"t",84*/
+{0x04,0x00,0x07,0x80,0x00,0x40,0x04,0x40,0x07,0xC0,0x00,0x40},/*"u",85*/
+{0x04,0x00,0x07,0x00,0x04,0xC0,0x01,0x80,0x06,0x00,0x04,0x00},/*"v",86*/
+{0x06,0x00,0x01,0xC0,0x07,0x00,0x01,0xC0,0x06,0x00,0x00,0x00},/*"w",87*/
+{0x04,0x40,0x06,0xC0,0x01,0x00,0x06,0xC0,0x04,0x40,0x00,0x00},/*"x",88*/
+{0x04,0x10,0x07,0x10,0x04,0xE0,0x01,0x80,0x06,0x00,0x04,0x00},/*"y",89*/
+{0x00,0x00,0x04,0x40,0x05,0xC0,0x06,0x40,0x04,0x40,0x00,0x00},/*"z",90*/
+{0x00,0x00,0x00,0x00,0x04,0x00,0x7B,0xE0,0x40,0x20,0x00,0x00},/*"{",91*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xF0,0x00,0x00,0x00,0x00},/*"|",92*/
+{0x00,0x00,0x40,0x20,0x7B,0xE0,0x04,0x00,0x00,0x00,0x00,0x00},/*"}",93*/
+{0x40,0x00,0x80,0x00,0x40,0x00,0x20,0x00,0x20,0x00,0x40,0x00},/*"~",94*/
+};  
+//16*16 ASCII code
+const unsigned char asc2_1608[95][16]={	  
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*" ",0*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xCC,0x00,0x0C,0x00,0x00,0x00,0x00,0x00,0x00},/*"!",1*/
+{0x00,0x00,0x08,0x00,0x30,0x00,0x60,0x00,0x08,0x00,0x30,0x00,0x60,0x00,0x00,0x00},/*""",2*/
+{0x02,0x20,0x03,0xFC,0x1E,0x20,0x02,0x20,0x03,0xFC,0x1E,0x20,0x02,0x20,0x00,0x00},/*"#",3*/
+{0x00,0x00,0x0E,0x18,0x11,0x04,0x3F,0xFF,0x10,0x84,0x0C,0x78,0x00,0x00,0x00,0x00},/*"$",4*/
+{0x0F,0x00,0x10,0x84,0x0F,0x38,0x00,0xC0,0x07,0x78,0x18,0x84,0x00,0x78,0x00,0x00},/*"%",5*/
+{0x00,0x78,0x0F,0x84,0x10,0xC4,0x11,0x24,0x0E,0x98,0x00,0xE4,0x00,0x84,0x00,0x08},/*"&",6*/
+{0x08,0x00,0x68,0x00,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",7*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xE0,0x18,0x18,0x20,0x04,0x40,0x02,0x00,0x00},/*"(",8*/
+{0x00,0x00,0x40,0x02,0x20,0x04,0x18,0x18,0x07,0xE0,0x00,0x00,0x00,0x00,0x00,0x00},/*")",9*/
+{0x02,0x40,0x02,0x40,0x01,0x80,0x0F,0xF0,0x01,0x80,0x02,0x40,0x02,0x40,0x00,0x00},/*"*",10*/
+{0x00,0x80,0x00,0x80,0x00,0x80,0x0F,0xF8,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x00},/*"+",11*/
+{0x00,0x01,0x00,0x0D,0x00,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*",",12*/
+{0x00,0x00,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80},/*"-",13*/
+{0x00,0x00,0x00,0x0C,0x00,0x0C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*".",14*/
+{0x00,0x00,0x00,0x06,0x00,0x18,0x00,0x60,0x01,0x80,0x06,0x00,0x18,0x00,0x20,0x00},/*"/",15*/
+{0x00,0x00,0x07,0xF0,0x08,0x08,0x10,0x04,0x10,0x04,0x08,0x08,0x07,0xF0,0x00,0x00},/*"0",16*/
+{0x00,0x00,0x08,0x04,0x08,0x04,0x1F,0xFC,0x00,0x04,0x00,0x04,0x00,0x00,0x00,0x00},/*"1",17*/
+{0x00,0x00,0x0E,0x0C,0x10,0x14,0x10,0x24,0x10,0x44,0x11,0x84,0x0E,0x0C,0x00,0x00},/*"2",18*/
+{0x00,0x00,0x0C,0x18,0x10,0x04,0x11,0x04,0x11,0x04,0x12,0x88,0x0C,0x70,0x00,0x00},/*"3",19*/
+{0x00,0x00,0x00,0xE0,0x03,0x20,0x04,0x24,0x08,0x24,0x1F,0xFC,0x00,0x24,0x00,0x00},/*"4",20*/
+{0x00,0x00,0x1F,0x98,0x10,0x84,0x11,0x04,0x11,0x04,0x10,0x88,0x10,0x70,0x00,0x00},/*"5",21*/
+{0x00,0x00,0x07,0xF0,0x08,0x88,0x11,0x04,0x11,0x04,0x18,0x88,0x00,0x70,0x00,0x00},/*"6",22*/
+{0x00,0x00,0x1C,0x00,0x10,0x00,0x10,0xFC,0x13,0x00,0x1C,0x00,0x10,0x00,0x00,0x00},/*"7",23*/
+{0x00,0x00,0x0E,0x38,0x11,0x44,0x10,0x84,0x10,0x84,0x11,0x44,0x0E,0x38,0x00,0x00},/*"8",24*/
+{0x00,0x00,0x07,0x00,0x08,0x8C,0x10,0x44,0x10,0x44,0x08,0x88,0x07,0xF0,0x00,0x00},/*"9",25*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x0C,0x03,0x0C,0x00,0x00,0x00,0x00,0x00,0x00},/*":",26*/
+{0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*";",27*/
+{0x00,0x00,0x00,0x80,0x01,0x40,0x02,0x20,0x04,0x10,0x08,0x08,0x10,0x04,0x00,0x00},/*"<",28*/
+{0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x00,0x00},/*"=",29*/
+{0x00,0x00,0x10,0x04,0x08,0x08,0x04,0x10,0x02,0x20,0x01,0x40,0x00,0x80,0x00,0x00},/*">",30*/
+{0x00,0x00,0x0E,0x00,0x12,0x00,0x10,0x0C,0x10,0x6C,0x10,0x80,0x0F,0x00,0x00,0x00},/*"?",31*/
+{0x03,0xE0,0x0C,0x18,0x13,0xE4,0x14,0x24,0x17,0xC4,0x08,0x28,0x07,0xD0,0x00,0x00},/*"@",32*/
+{0x00,0x04,0x00,0x3C,0x03,0xC4,0x1C,0x40,0x07,0x40,0x00,0xE4,0x00,0x1C,0x00,0x04},/*"A",33*/
+{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x04,0x11,0x04,0x0E,0x88,0x00,0x70,0x00,0x00},/*"B",34*/
+{0x03,0xE0,0x0C,0x18,0x10,0x04,0x10,0x04,0x10,0x04,0x10,0x08,0x1C,0x10,0x00,0x00},/*"C",35*/
+{0x10,0x04,0x1F,0xFC,0x10,0x04,0x10,0x04,0x10,0x04,0x08,0x08,0x07,0xF0,0x00,0x00},/*"D",36*/
+{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x04,0x17,0xC4,0x10,0x04,0x08,0x18,0x00,0x00},/*"E",37*/
+{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x00,0x17,0xC0,0x10,0x00,0x08,0x00,0x00,0x00},/*"F",38*/
+{0x03,0xE0,0x0C,0x18,0x10,0x04,0x10,0x04,0x10,0x44,0x1C,0x78,0x00,0x40,0x00,0x00},/*"G",39*/
+{0x10,0x04,0x1F,0xFC,0x10,0x84,0x00,0x80,0x00,0x80,0x10,0x84,0x1F,0xFC,0x10,0x04},/*"H",40*/
+{0x00,0x00,0x10,0x04,0x10,0x04,0x1F,0xFC,0x10,0x04,0x10,0x04,0x00,0x00,0x00,0x00},/*"I",41*/
+{0x00,0x03,0x00,0x01,0x10,0x01,0x10,0x01,0x1F,0xFE,0x10,0x00,0x10,0x00,0x00,0x00},/*"J",42*/
+{0x10,0x04,0x1F,0xFC,0x11,0x04,0x03,0x80,0x14,0x64,0x18,0x1C,0x10,0x04,0x00,0x00},/*"K",43*/
+{0x10,0x04,0x1F,0xFC,0x10,0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x0C,0x00,0x00},/*"L",44*/
+{0x10,0x04,0x1F,0xFC,0x1F,0x00,0x00,0xFC,0x1F,0x00,0x1F,0xFC,0x10,0x04,0x00,0x00},/*"M",45*/
+{0x10,0x04,0x1F,0xFC,0x0C,0x04,0x03,0x00,0x00,0xE0,0x10,0x18,0x1F,0xFC,0x10,0x00},/*"N",46*/
+{0x07,0xF0,0x08,0x08,0x10,0x04,0x10,0x04,0x10,0x04,0x08,0x08,0x07,0xF0,0x00,0x00},/*"O",47*/
+{0x10,0x04,0x1F,0xFC,0x10,0x84,0x10,0x80,0x10,0x80,0x10,0x80,0x0F,0x00,0x00,0x00},/*"P",48*/
+{0x07,0xF0,0x08,0x18,0x10,0x24,0x10,0x24,0x10,0x1C,0x08,0x0A,0x07,0xF2,0x00,0x00},/*"Q",49*/
+{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x00,0x11,0xC0,0x11,0x30,0x0E,0x0C,0x00,0x04},/*"R",50*/
+{0x00,0x00,0x0E,0x1C,0x11,0x04,0x10,0x84,0x10,0x84,0x10,0x44,0x1C,0x38,0x00,0x00},/*"S",51*/
+{0x18,0x00,0x10,0x00,0x10,0x04,0x1F,0xFC,0x10,0x04,0x10,0x00,0x18,0x00,0x00,0x00},/*"T",52*/
+{0x10,0x00,0x1F,0xF8,0x10,0x04,0x00,0x04,0x00,0x04,0x10,0x04,0x1F,0xF8,0x10,0x00},/*"U",53*/
+{0x10,0x00,0x1E,0x00,0x11,0xE0,0x00,0x1C,0x00,0x70,0x13,0x80,0x1C,0x00,0x10,0x00},/*"V",54*/
+{0x1F,0xC0,0x10,0x3C,0x00,0xE0,0x1F,0x00,0x00,0xE0,0x10,0x3C,0x1F,0xC0,0x00,0x00},/*"W",55*/
+{0x10,0x04,0x18,0x0C,0x16,0x34,0x01,0xC0,0x01,0xC0,0x16,0x34,0x18,0x0C,0x10,0x04},/*"X",56*/
+{0x10,0x00,0x1C,0x00,0x13,0x04,0x00,0xFC,0x13,0x04,0x1C,0x00,0x10,0x00,0x00,0x00},/*"Y",57*/
+{0x08,0x04,0x10,0x1C,0x10,0x64,0x10,0x84,0x13,0x04,0x1C,0x04,0x10,0x18,0x00,0x00},/*"Z",58*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFE,0x40,0x02,0x40,0x02,0x40,0x02,0x00,0x00},/*"[",59*/
+{0x00,0x00,0x30,0x00,0x0C,0x00,0x03,0x80,0x00,0x60,0x00,0x1C,0x00,0x03,0x00,0x00},/*"\",60*/
+{0x00,0x00,0x40,0x02,0x40,0x02,0x40,0x02,0x7F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00},/*"]",61*/
+{0x00,0x00,0x00,0x00,0x20,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x00,0x00},/*"^",62*/
+{0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01},/*"_",63*/
+{0x00,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"`",64*/
+{0x00,0x00,0x00,0x98,0x01,0x24,0x01,0x44,0x01,0x44,0x01,0x44,0x00,0xFC,0x00,0x04},/*"a",65*/
+{0x10,0x00,0x1F,0xFC,0x00,0x88,0x01,0x04,0x01,0x04,0x00,0x88,0x00,0x70,0x00,0x00},/*"b",66*/
+{0x00,0x00,0x00,0x70,0x00,0x88,0x01,0x04,0x01,0x04,0x01,0x04,0x00,0x88,0x00,0x00},/*"c",67*/
+{0x00,0x00,0x00,0x70,0x00,0x88,0x01,0x04,0x01,0x04,0x11,0x08,0x1F,0xFC,0x00,0x04},/*"d",68*/
+{0x00,0x00,0x00,0xF8,0x01,0x44,0x01,0x44,0x01,0x44,0x01,0x44,0x00,0xC8,0x00,0x00},/*"e",69*/
+{0x00,0x00,0x01,0x04,0x01,0x04,0x0F,0xFC,0x11,0x04,0x11,0x04,0x11,0x00,0x18,0x00},/*"f",70*/
+{0x00,0x00,0x00,0xD6,0x01,0x29,0x01,0x29,0x01,0x29,0x01,0xC9,0x01,0x06,0x00,0x00},/*"g",71*/
+{0x10,0x04,0x1F,0xFC,0x00,0x84,0x01,0x00,0x01,0x00,0x01,0x04,0x00,0xFC,0x00,0x04},/*"h",72*/
+{0x00,0x00,0x01,0x04,0x19,0x04,0x19,0xFC,0x00,0x04,0x00,0x04,0x00,0x00,0x00,0x00},/*"i",73*/
+{0x00,0x00,0x00,0x03,0x00,0x01,0x01,0x01,0x19,0x01,0x19,0xFE,0x00,0x00,0x00,0x00},/*"j",74*/
+{0x10,0x04,0x1F,0xFC,0x00,0x24,0x00,0x40,0x01,0xB4,0x01,0x0C,0x01,0x04,0x00,0x00},/*"k",75*/
+{0x00,0x00,0x10,0x04,0x10,0x04,0x1F,0xFC,0x00,0x04,0x00,0x04,0x00,0x00,0x00,0x00},/*"l",76*/
+{0x01,0x04,0x01,0xFC,0x01,0x04,0x01,0x00,0x01,0xFC,0x01,0x04,0x01,0x00,0x00,0xFC},/*"m",77*/
+{0x01,0x04,0x01,0xFC,0x00,0x84,0x01,0x00,0x01,0x00,0x01,0x04,0x00,0xFC,0x00,0x04},/*"n",78*/
+{0x00,0x00,0x00,0xF8,0x01,0x04,0x01,0x04,0x01,0x04,0x01,0x04,0x00,0xF8,0x00,0x00},/*"o",79*/
+{0x01,0x01,0x01,0xFF,0x00,0x85,0x01,0x04,0x01,0x04,0x00,0x88,0x00,0x70,0x00,0x00},/*"p",80*/
+{0x00,0x00,0x00,0x70,0x00,0x88,0x01,0x04,0x01,0x04,0x01,0x05,0x01,0xFF,0x00,0x01},/*"q",81*/
+{0x01,0x04,0x01,0x04,0x01,0xFC,0x00,0x84,0x01,0x04,0x01,0x00,0x01,0x80,0x00,0x00},/*"r",82*/
+{0x00,0x00,0x00,0xCC,0x01,0x24,0x01,0x24,0x01,0x24,0x01,0x24,0x01,0x98,0x00,0x00},/*"s",83*/
+{0x00,0x00,0x01,0x00,0x01,0x00,0x07,0xF8,0x01,0x04,0x01,0x04,0x00,0x00,0x00,0x00},/*"t",84*/
+{0x01,0x00,0x01,0xF8,0x00,0x04,0x00,0x04,0x00,0x04,0x01,0x08,0x01,0xFC,0x00,0x04},/*"u",85*/
+{0x01,0x00,0x01,0x80,0x01,0x70,0x00,0x0C,0x00,0x10,0x01,0x60,0x01,0x80,0x01,0x00},/*"v",86*/
+{0x01,0xF0,0x01,0x0C,0x00,0x30,0x01,0xC0,0x00,0x30,0x01,0x0C,0x01,0xF0,0x01,0x00},/*"w",87*/
+{0x00,0x00,0x01,0x04,0x01,0x8C,0x00,0x74,0x01,0x70,0x01,0x8C,0x01,0x04,0x00,0x00},/*"x",88*/
+{0x01,0x01,0x01,0x81,0x01,0x71,0x00,0x0E,0x00,0x18,0x01,0x60,0x01,0x80,0x01,0x00},/*"y",89*/
+{0x00,0x00,0x01,0x84,0x01,0x0C,0x01,0x34,0x01,0x44,0x01,0x84,0x01,0x0C,0x00,0x00},/*"z",90*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x3E,0xFC,0x40,0x02,0x40,0x02},/*"{",91*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00},/*"|",92*/
+{0x00,0x00,0x40,0x02,0x40,0x02,0x3E,0xFC,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"}",93*/
+{0x00,0x00,0x60,0x00,0x80,0x00,0x80,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x20,0x00},/*"~",94*/
+};  
+//24*24 ASICII code
+const unsigned char asc2_2412[95][36]={	  
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*" ",0*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x80,0x38,0x0F,0xFE,0x38,0x0F,0x80,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"!",1*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x06,0x00,0x00,0x0C,0x00,0x00,0x38,0x00,0x00,0x31,0x00,0x00,0x06,0x00,0x00,0x0C,0x00,0x00,0x38,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00},/*""",2*/
+{0x00,0x00,0x00,0x00,0x61,0x80,0x00,0x67,0xF8,0x07,0xF9,0x80,0x00,0x61,0x80,0x00,0x61,0x80,0x00,0x61,0x80,0x00,0x61,0x80,0x00,0x67,0xF8,0x07,0xF9,0x80,0x00,0x61,0x80,0x00,0x00,0x00},/*"#",3*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xC0,0xE0,0x03,0xE0,0xF0,0x06,0x30,0x08,0x04,0x18,0x08,0x1F,0xFF,0xFE,0x04,0x0E,0x08,0x07,0x87,0xF0,0x03,0x81,0xE0,0x00,0x00,0x00,0x00,0x00,0x00},/*"$",4*/
+{0x01,0xF0,0x00,0x06,0x0C,0x00,0x04,0x04,0x08,0x06,0x0C,0x70,0x01,0xF9,0xC0,0x00,0x0E,0x00,0x00,0x3B,0xE0,0x00,0xEC,0x18,0x07,0x08,0x08,0x04,0x0C,0x18,0x00,0x03,0xE0,0x00,0x00,0x00},/*"%",5*/
+{0x00,0x01,0xE0,0x00,0x07,0xF0,0x03,0xF8,0x18,0x04,0x1C,0x08,0x04,0x17,0x08,0x07,0xE1,0xD0,0x03,0xC0,0xE0,0x00,0x23,0xB0,0x00,0x3C,0x08,0x00,0x20,0x08,0x00,0x00,0x10,0x00,0x00,0x00},/*"&",6*/
+{0x00,0x00,0x00,0x01,0x00,0x00,0x31,0x00,0x00,0x32,0x00,0x00,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",7*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0x00,0x01,0xFF,0xC0,0x07,0x80,0xF0,0x0C,0x00,0x18,0x10,0x00,0x04,0x20,0x00,0x02,0x00,0x00,0x00},/*"(",8*/
+{0x00,0x00,0x00,0x20,0x00,0x02,0x10,0x00,0x04,0x0C,0x00,0x18,0x07,0x80,0xF0,0x01,0xFF,0xC0,0x00,0x7F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*")",9*/
+{0x00,0x00,0x00,0x00,0x42,0x00,0x00,0x66,0x00,0x00,0x66,0x00,0x00,0x3C,0x00,0x00,0x18,0x00,0x03,0xFF,0xC0,0x00,0x18,0x00,0x00,0x3C,0x00,0x00,0x66,0x00,0x00,0x66,0x00,0x00,0x42,0x00},/*"*",10*/
+{0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x01,0xFF,0xC0,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00},/*"+",11*/
+{0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x31,0x00,0x00,0x32,0x00,0x00,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*",",12*/
+{0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x00,0x00},/*"-",13*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x38,0x00,0x00,0x38,0x00,0x00,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*".",14*/
+{0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x1C,0x00,0x00,0x70,0x00,0x01,0x80,0x00,0x0E,0x00,0x00,0x38,0x00,0x00,0xC0,0x00,0x07,0x00,0x00,0x1C,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00},/*"/",15*/
+{0x00,0x00,0x00,0x00,0x7F,0x80,0x01,0xFF,0xE0,0x03,0x80,0x70,0x06,0x00,0x18,0x04,0x00,0x08,0x04,0x00,0x08,0x06,0x00,0x18,0x03,0x80,0x70,0x01,0xFF,0xE0,0x00,0x7F,0x80,0x00,0x00,0x00},/*"0",16*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x08,0x01,0x00,0x08,0x01,0x00,0x08,0x03,0xFF,0xF8,0x07,0xFF,0xF8,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00},/*"1",17*/
+{0x00,0x00,0x00,0x01,0xC0,0x38,0x02,0xC0,0x58,0x04,0x00,0x98,0x04,0x01,0x18,0x04,0x02,0x18,0x04,0x04,0x18,0x06,0x1C,0x18,0x03,0xF8,0x18,0x01,0xE0,0xF8,0x00,0x00,0x00,0x00,0x00,0x00},/*"2",18*/
+{0x00,0x00,0x00,0x01,0xC0,0xE0,0x03,0xC0,0xF0,0x04,0x00,0x08,0x04,0x08,0x08,0x04,0x08,0x08,0x06,0x18,0x08,0x03,0xF4,0x18,0x01,0xE7,0xF0,0x00,0x01,0xE0,0x00,0x00,0x00,0x00,0x00,0x00},/*"3",19*/
+{0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x0D,0x00,0x00,0x11,0x00,0x00,0x61,0x00,0x00,0x81,0x08,0x03,0x01,0x08,0x07,0xFF,0xF8,0x0F,0xFF,0xF8,0x00,0x01,0x08,0x00,0x01,0x08,0x00,0x00,0x00},/*"4",20*/
+{0x00,0x00,0x00,0x00,0x00,0xE0,0x07,0xFC,0xD0,0x06,0x08,0x08,0x06,0x10,0x08,0x06,0x10,0x08,0x06,0x10,0x08,0x06,0x18,0x38,0x06,0x0F,0xF0,0x06,0x07,0xC0,0x00,0x00,0x00,0x00,0x00,0x00},/*"5",21*/
+{0x00,0x00,0x00,0x00,0x3F,0x80,0x01,0xFF,0xE0,0x03,0x84,0x30,0x02,0x08,0x18,0x04,0x10,0x08,0x04,0x10,0x08,0x04,0x10,0x08,0x07,0x18,0x10,0x03,0x0F,0xF0,0x00,0x07,0xC0,0x00,0x00,0x00},/*"6",22*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xC0,0x00,0x07,0x00,0x00,0x06,0x00,0x00,0x06,0x00,0xF8,0x06,0x07,0xF8,0x06,0x18,0x00,0x06,0xE0,0x00,0x07,0x00,0x00,0x06,0x00,0x00,0x00,0x00,0x00},/*"7",23*/
+{0x00,0x00,0x00,0x01,0xE1,0xE0,0x03,0xF7,0xF0,0x06,0x34,0x10,0x04,0x18,0x08,0x04,0x18,0x08,0x04,0x0C,0x08,0x04,0x0C,0x08,0x06,0x16,0x18,0x03,0xF3,0xF0,0x01,0xC1,0xE0,0x00,0x00,0x00},/*"8",24*/
+{0x00,0x00,0x00,0x00,0xF8,0x00,0x03,0xFC,0x30,0x03,0x06,0x38,0x04,0x02,0x08,0x04,0x02,0x08,0x04,0x02,0x08,0x04,0x04,0x10,0x03,0x08,0xF0,0x01,0xFF,0xC0,0x00,0x7F,0x00,0x00,0x00,0x00},/*"9",25*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x70,0x38,0x00,0x70,0x38,0x00,0x70,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*":",26*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x1A,0x00,0x30,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*";",27*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x14,0x00,0x00,0x22,0x00,0x00,0x41,0x00,0x00,0x80,0x80,0x01,0x00,0x40,0x02,0x00,0x20,0x04,0x00,0x10,0x08,0x00,0x08,0x00,0x00,0x00},/*"<",28*/
+{0x00,0x00,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x00,0x00},/*"=",29*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x08,0x04,0x00,0x10,0x02,0x00,0x20,0x01,0x00,0x40,0x00,0x80,0x80,0x00,0x41,0x00,0x00,0x22,0x00,0x00,0x14,0x00,0x00,0x08,0x00,0x00,0x00,0x00},/*">",30*/
+{0x00,0x00,0x00,0x03,0xC0,0x00,0x04,0xC0,0x00,0x04,0x00,0x00,0x08,0x00,0x38,0x08,0x0F,0x38,0x08,0x08,0x38,0x08,0x10,0x00,0x0C,0x30,0x00,0x07,0xE0,0x00,0x03,0xC0,0x00,0x00,0x00,0x00},/*"?",31*/
+{0x00,0x00,0x00,0x00,0x3F,0x80,0x00,0xFF,0xE0,0x03,0x80,0x70,0x02,0x0F,0x10,0x06,0x70,0x88,0x04,0xC0,0x88,0x04,0x83,0x08,0x04,0x7F,0x88,0x02,0xC0,0x90,0x03,0x01,0x20,0x00,0xFE,0x40},/*"@",32*/
+{0x00,0x00,0x08,0x00,0x00,0x18,0x00,0x01,0xF8,0x00,0x3E,0x08,0x01,0xC2,0x00,0x07,0x02,0x00,0x07,0xE2,0x00,0x00,0xFE,0x00,0x00,0x1F,0xC8,0x00,0x01,0xF8,0x00,0x00,0x38,0x00,0x00,0x08},/*"A",33*/
+{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x08,0x08,0x04,0x08,0x08,0x04,0x08,0x08,0x04,0x08,0x08,0x06,0x18,0x08,0x03,0xF4,0x18,0x01,0xE7,0xF0,0x00,0x01,0xE0,0x00,0x00,0x00},/*"B",34*/
+{0x00,0x00,0x00,0x00,0x3F,0x80,0x01,0xFF,0xE0,0x03,0x80,0x70,0x02,0x00,0x18,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x10,0x06,0x00,0x20,0x07,0x80,0xC0,0x00,0x00,0x00},/*"C",35*/
+{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x18,0x02,0x00,0x10,0x03,0x80,0x70,0x01,0xFF,0xE0,0x00,0x7F,0x80,0x00,0x00,0x00},/*"D",36*/
+{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x08,0x08,0x04,0x08,0x08,0x04,0x08,0x08,0x04,0x08,0x08,0x04,0x3E,0x08,0x04,0x00,0x08,0x06,0x00,0x18,0x01,0x00,0x60,0x00,0x00,0x00},/*"E",37*/
+{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x08,0x08,0x04,0x08,0x00,0x04,0x08,0x00,0x04,0x08,0x00,0x04,0x3E,0x00,0x06,0x00,0x00,0x06,0x00,0x00,0x01,0x80,0x00,0x00,0x00,0x00},/*"F",38*/
+{0x00,0x00,0x00,0x00,0x3F,0x80,0x01,0xFF,0xE0,0x03,0x80,0x70,0x06,0x00,0x18,0x04,0x00,0x08,0x04,0x02,0x08,0x04,0x02,0x08,0x02,0x03,0xF0,0x07,0x83,0xF0,0x00,0x02,0x00,0x00,0x02,0x00},/*"G",39*/
+{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x08,0x08,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x04,0x08,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08},/*"H",40*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00},/*"I",41*/
+{0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x07,0x00,0x00,0x01,0x04,0x00,0x01,0x04,0x00,0x01,0x04,0x00,0x03,0x07,0xFF,0xFE,0x07,0xFF,0xFC,0x04,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x00},/*"J",42*/
+{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x0C,0x08,0x00,0x18,0x00,0x00,0x3E,0x00,0x04,0xC7,0x80,0x05,0x03,0xC8,0x06,0x00,0xF8,0x04,0x00,0x38,0x04,0x00,0x18,0x00,0x00,0x08},/*"K",43*/
+{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x18,0x00,0x00,0x60,0x00,0x00,0x00},/*"L",44*/
+{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0x80,0x08,0x07,0xFC,0x00,0x00,0x7F,0xC0,0x00,0x03,0xF8,0x00,0x07,0xC0,0x00,0x78,0x00,0x07,0x80,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08},/*"M",45*/
+{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0x00,0x08,0x03,0xC0,0x00,0x00,0xE0,0x00,0x00,0x38,0x00,0x00,0x1E,0x00,0x00,0x07,0x00,0x00,0x01,0xC0,0x04,0x00,0xF0,0x07,0xFF,0xF8,0x04,0x00,0x00},/*"N",46*/
+{0x00,0x00,0x00,0x00,0x7F,0x80,0x01,0xFF,0xE0,0x03,0x80,0x70,0x06,0x00,0x18,0x04,0x00,0x08,0x04,0x00,0x08,0x06,0x00,0x18,0x03,0x00,0x30,0x01,0xFF,0xE0,0x00,0x7F,0x80,0x00,0x00,0x00},/*"O",47*/
+{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x04,0x08,0x04,0x04,0x00,0x04,0x04,0x00,0x04,0x04,0x00,0x04,0x04,0x00,0x06,0x0C,0x00,0x03,0xF8,0x00,0x01,0xF0,0x00,0x00,0x00,0x00},/*"P",48*/
+{0x00,0x00,0x00,0x00,0x7F,0x80,0x01,0xFF,0xE0,0x03,0x80,0x70,0x06,0x00,0x88,0x04,0x00,0x88,0x04,0x00,0xC8,0x06,0x00,0x3C,0x03,0x00,0x3E,0x01,0xFF,0xE6,0x00,0x7F,0x84,0x00,0x00,0x00},/*"Q",49*/
+{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x08,0x08,0x04,0x08,0x00,0x04,0x0C,0x00,0x04,0x0F,0x00,0x04,0x0B,0xC0,0x06,0x10,0xF0,0x03,0xF0,0x38,0x01,0xE0,0x08,0x00,0x00,0x08},/*"R",50*/
+{0x00,0x00,0x00,0x01,0xE0,0xF8,0x03,0xF0,0x30,0x06,0x30,0x10,0x04,0x18,0x08,0x04,0x18,0x08,0x04,0x0C,0x08,0x04,0x0C,0x08,0x02,0x06,0x18,0x02,0x07,0xF0,0x07,0x81,0xE0,0x00,0x00,0x00},/*"S",51*/
+{0x01,0x80,0x00,0x06,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08,0x04,0x00,0x00,0x04,0x00,0x00,0x06,0x00,0x00,0x01,0x80,0x00},/*"T",52*/
+{0x04,0x00,0x00,0x07,0xFF,0xE0,0x07,0xFF,0xF0,0x04,0x00,0x18,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x04,0x00,0x10,0x07,0xFF,0xE0,0x04,0x00,0x00},/*"U",53*/
+{0x04,0x00,0x00,0x06,0x00,0x00,0x07,0xE0,0x00,0x07,0xFE,0x00,0x04,0x1F,0xE0,0x00,0x01,0xF8,0x00,0x00,0x38,0x00,0x01,0xE0,0x04,0x3E,0x00,0x07,0xC0,0x00,0x06,0x00,0x00,0x04,0x00,0x00},/*"V",54*/
+{0x04,0x00,0x00,0x07,0xE0,0x00,0x07,0xFF,0xC0,0x04,0x1F,0xF8,0x00,0x07,0xC0,0x07,0xF8,0x00,0x07,0xFF,0x80,0x04,0x3F,0xF8,0x00,0x07,0xC0,0x04,0xF8,0x00,0x07,0x00,0x00,0x04,0x00,0x00},/*"W",55*/
+{0x00,0x00,0x00,0x04,0x00,0x08,0x06,0x00,0x18,0x07,0xC0,0x78,0x05,0xF1,0xC8,0x00,0x3E,0x00,0x00,0x1F,0x80,0x04,0x63,0xE8,0x07,0x80,0xF8,0x06,0x00,0x18,0x04,0x00,0x08,0x00,0x00,0x00},/*"X",56*/
+{0x04,0x00,0x00,0x06,0x00,0x00,0x07,0x80,0x00,0x07,0xE0,0x08,0x04,0x7C,0x08,0x00,0x1F,0xF8,0x00,0x07,0xF8,0x00,0x18,0x08,0x04,0xE0,0x08,0x07,0x00,0x00,0x06,0x00,0x00,0x04,0x00,0x00},/*"Y",57*/
+{0x00,0x00,0x00,0x01,0x00,0x08,0x06,0x00,0x38,0x04,0x00,0xF8,0x04,0x03,0xE8,0x04,0x0F,0x08,0x04,0x7C,0x08,0x05,0xF0,0x08,0x07,0xC0,0x08,0x07,0x00,0x18,0x04,0x00,0x60,0x00,0x00,0x00},/*"Z",58*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xFE,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x00,0x00,0x00},/*"[",59*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x07,0x00,0x00,0x00,0xC0,0x00,0x00,0x38,0x00,0x00,0x06,0x00,0x00,0x01,0xC0,0x00,0x00,0x30,0x00,0x00,0x0E,0x00,0x00,0x01,0x00,0x00,0x00},/*"\",60*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x3F,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"]",61*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x10,0x00,0x00,0x30,0x00,0x00,0x20,0x00,0x00,0x30,0x00,0x00,0x10,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"^",62*/
+{0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01},/*"_",63*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x20,0x00,0x00,0x10,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"`",64*/
+{0x00,0x00,0x00,0x00,0x00,0xF0,0x00,0x19,0xF8,0x00,0x1B,0x18,0x00,0x22,0x08,0x00,0x26,0x08,0x00,0x24,0x08,0x00,0x24,0x10,0x00,0x3F,0xF8,0x00,0x1F,0xF8,0x00,0x00,0x08,0x00,0x00,0x18},/*"a",65*/
+{0x00,0x00,0x00,0x04,0x00,0x00,0x07,0xFF,0xF8,0x0F,0xFF,0xF0,0x00,0x18,0x18,0x00,0x10,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x30,0x18,0x00,0x1F,0xF0,0x00,0x0F,0xC0,0x00,0x00,0x00},/*"b",66*/
+{0x00,0x00,0x00,0x00,0x07,0xC0,0x00,0x1F,0xF0,0x00,0x18,0x30,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x3C,0x08,0x00,0x1C,0x10,0x00,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00},/*"c",67*/
+{0x00,0x00,0x00,0x00,0x07,0xC0,0x00,0x1F,0xF0,0x00,0x38,0x18,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x04,0x10,0x10,0x07,0xFF,0xF8,0x0F,0xFF,0xF0,0x00,0x00,0x10,0x00,0x00,0x00},/*"d",68*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xC0,0x00,0x1F,0xF0,0x00,0x12,0x30,0x00,0x22,0x18,0x00,0x22,0x08,0x00,0x22,0x08,0x00,0x32,0x08,0x00,0x1E,0x10,0x00,0x0E,0x20,0x00,0x00,0x00},/*"e",69*/
+{0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x20,0x08,0x00,0x20,0x08,0x01,0xFF,0xF8,0x03,0xFF,0xF8,0x06,0x20,0x08,0x04,0x20,0x08,0x04,0x20,0x08,0x07,0x20,0x00,0x03,0x00,0x00,0x00,0x00,0x00},/*"f",70*/
+{0x00,0x00,0x00,0x00,0x00,0x0E,0x00,0x0E,0x6E,0x00,0x1F,0xF3,0x00,0x31,0xB1,0x00,0x20,0xB1,0x00,0x20,0xB1,0x00,0x31,0x91,0x00,0x1F,0x13,0x00,0x2E,0x1E,0x00,0x20,0x0E,0x00,0x30,0x00},/*"g",71*/
+{0x00,0x00,0x00,0x04,0x00,0x08,0x07,0xFF,0xF8,0x0F,0xFF,0xF8,0x00,0x10,0x08,0x00,0x20,0x00,0x00,0x20,0x00,0x00,0x20,0x08,0x00,0x3F,0xF8,0x00,0x1F,0xF8,0x00,0x00,0x08,0x00,0x00,0x00},/*"h",72*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x06,0x3F,0xF8,0x06,0x3F,0xF8,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00},/*"i",73*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x03,0x00,0x20,0x01,0x00,0x20,0x01,0x00,0x20,0x03,0x06,0x3F,0xFE,0x06,0x3F,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"j",74*/
+{0x00,0x00,0x00,0x04,0x00,0x08,0x07,0xFF,0xF8,0x0F,0xFF,0xF8,0x00,0x01,0x88,0x00,0x03,0x00,0x00,0x2F,0xC0,0x00,0x38,0xF8,0x00,0x20,0x38,0x00,0x20,0x08,0x00,0x00,0x08,0x00,0x00,0x00},/*"k",75*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x08,0x07,0xFF,0xF8,0x0F,0xFF,0xF8,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00},/*"l",76*/
+{0x00,0x20,0x08,0x00,0x3F,0xF8,0x00,0x3F,0xF8,0x00,0x10,0x08,0x00,0x20,0x00,0x00,0x3F,0xF8,0x00,0x3F,0xF8,0x00,0x10,0x08,0x00,0x20,0x00,0x00,0x3F,0xF8,0x00,0x3F,0xF8,0x00,0x00,0x08},/*"m",77*/
+{0x00,0x00,0x00,0x00,0x20,0x08,0x00,0x3F,0xF8,0x00,0x3F,0xF8,0x00,0x10,0x08,0x00,0x10,0x00,0x00,0x20,0x00,0x00,0x20,0x08,0x00,0x3F,0xF8,0x00,0x1F,0xF8,0x00,0x00,0x08,0x00,0x00,0x00},/*"n",78*/
+{0x00,0x00,0x00,0x00,0x07,0xC0,0x00,0x0F,0xF0,0x00,0x18,0x30,0x00,0x30,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x30,0x08,0x00,0x18,0x30,0x00,0x0F,0xF0,0x00,0x07,0xC0,0x00,0x00,0x00},/*"o",79*/
+{0x00,0x00,0x00,0x00,0x20,0x01,0x00,0x3F,0xFF,0x00,0x3F,0xFF,0x00,0x10,0x11,0x00,0x20,0x09,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x30,0x38,0x00,0x1F,0xF0,0x00,0x0F,0xC0,0x00,0x00,0x00},/*"p",80*/
+{0x00,0x00,0x00,0x00,0x07,0xC0,0x00,0x1F,0xF0,0x00,0x38,0x18,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x09,0x00,0x10,0x11,0x00,0x1F,0xFF,0x00,0x3F,0xFF,0x00,0x00,0x01,0x00,0x00,0x00},/*"q",81*/
+{0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x3F,0xF8,0x00,0x3F,0xF8,0x00,0x08,0x08,0x00,0x10,0x08,0x00,0x20,0x08,0x00,0x20,0x00,0x00,0x30,0x00,0x00,0x30,0x00,0x00,0x00,0x00},/*"r",82*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0C,0x78,0x00,0x1E,0x18,0x00,0x33,0x08,0x00,0x23,0x08,0x00,0x21,0x08,0x00,0x21,0x88,0x00,0x21,0x98,0x00,0x30,0xF0,0x00,0x38,0x60,0x00,0x00,0x00},/*"s",83*/
+{0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x20,0x00,0x00,0x20,0x00,0x00,0xFF,0xF0,0x03,0xFF,0xF8,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00,0x00},/*"t",84*/
+{0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x3F,0xF0,0x00,0x7F,0xF8,0x00,0x00,0x18,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x20,0x10,0x00,0x3F,0xF8,0x00,0x7F,0xF0,0x00,0x00,0x10,0x00,0x00,0x00},/*"u",85*/
+{0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x30,0x00,0x00,0x3C,0x00,0x00,0x3F,0x80,0x00,0x23,0xF0,0x00,0x00,0x78,0x00,0x00,0x70,0x00,0x23,0x80,0x00,0x3C,0x00,0x00,0x30,0x00,0x00,0x20,0x00},/*"v",86*/
+{0x00,0x20,0x00,0x00,0x3C,0x00,0x00,0x3F,0xE0,0x00,0x23,0xF8,0x00,0x00,0xE0,0x00,0x27,0x00,0x00,0x3E,0x00,0x00,0x3F,0xE0,0x00,0x21,0xF8,0x00,0x01,0xE0,0x00,0x3E,0x00,0x00,0x20,0x00},/*"w",87*/
+{0x00,0x00,0x00,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x38,0x38,0x00,0x3E,0x68,0x00,0x27,0x80,0x00,0x03,0xC8,0x00,0x2C,0xF8,0x00,0x38,0x38,0x00,0x20,0x18,0x00,0x20,0x08,0x00,0x00,0x00},/*"x",88*/
+{0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x30,0x03,0x00,0x3C,0x01,0x00,0x3F,0x83,0x00,0x23,0xEC,0x00,0x00,0x70,0x00,0x23,0x80,0x00,0x3C,0x00,0x00,0x20,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"y",89*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x38,0x08,0x00,0x20,0x38,0x00,0x20,0xF8,0x00,0x23,0xE8,0x00,0x2F,0x88,0x00,0x3E,0x08,0x00,0x38,0x08,0x00,0x20,0x18,0x00,0x00,0x70,0x00,0x00,0x00},/*"z",90*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x14,0x00,0x1F,0xF7,0xFC,0x30,0x00,0x06,0x20,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00},/*"{",91*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"|",92*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x02,0x30,0x00,0x06,0x1F,0xF7,0xFC,0x00,0x14,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"}",93*/
+{0x00,0x00,0x00,0x18,0x00,0x00,0x60,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x20,0x00,0x00,0x10,0x00,0x00,0x08,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x00,0x0C,0x00,0x00,0x10,0x00,0x00},/*"~",94*/
+};      
+#endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/hardware_adc.h

@@ -0,0 +1,675 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_adc.h
+  * @author  MCD Application Team
+  * @version V1.4.0
+  * @date    04-August-2014
+  * @brief   This file contains all the functions prototypes for the ADC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/**
+* @file: hardware_adc.h
+* @brief: define hardware adc function
+* @version: 1.1
+* @author:  AIIT XUOS Lab
+* @date:    2021/12/28
+*/
+
+/*************************************************
+File name: hardware_adc.h
+Description: define hardware adc function
+Others: 
+History: 
+1. Date: 2021-12-28
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_adc.h for XiZi
+*************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HARDWARE_ADC_H__
+#define __HARDWARE_ADC_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stm32f4xx.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief   ADC Init structure definition  
+  */ 
+typedef struct
+{
+  uint32_t ADC_Resolution;                /*!< Configures the ADC resolution dual mode. 
+                                               This parameter can be a value of @ref ADC_resolution */                                   
+  FunctionalState ADC_ScanConvMode;       /*!< Specifies whether the conversion 
+                                               is performed in Scan (multichannels) 
+                                               or Single (one channel) mode.
+                                               This parameter can be set to ENABLE or DISABLE */ 
+  FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion 
+                                               is performed in Continuous or Single mode.
+                                               This parameter can be set to ENABLE or DISABLE. */
+  uint32_t ADC_ExternalTrigConvEdge;      /*!< Select the external trigger edge and
+                                               enable the trigger of a regular group. 
+                                               This parameter can be a value of 
+                                               @ref ADC_external_trigger_edge_for_regular_channels_conversion */
+  uint32_t ADC_ExternalTrigConv;          /*!< Select the external event used to trigger 
+                                               the start of conversion of a regular group.
+                                               This parameter can be a value of 
+                                               @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */
+  uint32_t ADC_DataAlign;                 /*!< Specifies whether the ADC data  alignment
+                                               is left or right. This parameter can be 
+                                               a value of @ref ADC_data_align */
+  uint8_t  ADC_NbrOfConversion;           /*!< Specifies the number of ADC conversions
+                                               that will be done using the sequencer for
+                                               regular channel group.
+                                               This parameter must range from 1 to 16. */
+}ADC_InitTypeDef;
+  
+/** 
+  * @brief   ADC Common Init structure definition  
+  */ 
+typedef struct 
+{
+  uint32_t ADC_Mode;                      /*!< Configures the ADC to operate in 
+                                               independent or multi mode. 
+                                               This parameter can be a value of @ref ADC_Common_mode */                                              
+  uint32_t ADC_Prescaler;                 /*!< Select the frequency of the clock 
+                                               to the ADC. The clock is common for all the ADCs.
+                                               This parameter can be a value of @ref ADC_Prescaler */
+  uint32_t ADC_DMAAccessMode;             /*!< Configures the Direct memory access 
+                                              mode for multi ADC mode.
+                                               This parameter can be a value of 
+                                               @ref ADC_Direct_memory_access_mode_for_multi_mode */
+  uint32_t ADC_TwoSamplingDelay;          /*!< Configures the Delay between 2 sampling phases.
+                                               This parameter can be a value of 
+                                               @ref ADC_delay_between_2_sampling_phases */
+  
+}ADC_CommonInitTypeDef;
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants
+  * @{
+  */ 
+#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
+                                   ((PERIPH) == ADC2) || \
+                                   ((PERIPH) == ADC3))  
+
+/** @defgroup ADC_Common_mode 
+  * @{
+  */ 
+#define ADC_Mode_Independent                       ((uint32_t)0x00000000)       
+#define ADC_DualMode_RegSimult_InjecSimult         ((uint32_t)0x00000001)
+#define ADC_DualMode_RegSimult_AlterTrig           ((uint32_t)0x00000002)
+#define ADC_DualMode_InjecSimult                   ((uint32_t)0x00000005)
+#define ADC_DualMode_RegSimult                     ((uint32_t)0x00000006)
+#define ADC_DualMode_Interl                        ((uint32_t)0x00000007)
+#define ADC_DualMode_AlterTrig                     ((uint32_t)0x00000009)
+#define ADC_TripleMode_RegSimult_InjecSimult       ((uint32_t)0x00000011)
+#define ADC_TripleMode_RegSimult_AlterTrig         ((uint32_t)0x00000012)
+#define ADC_TripleMode_InjecSimult                 ((uint32_t)0x00000015)
+#define ADC_TripleMode_RegSimult                   ((uint32_t)0x00000016)
+#define ADC_TripleMode_Interl                      ((uint32_t)0x00000017)
+#define ADC_TripleMode_AlterTrig                   ((uint32_t)0x00000019)
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
+                           ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \
+                           ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \
+                           ((MODE) == ADC_DualMode_InjecSimult) || \
+                           ((MODE) == ADC_DualMode_RegSimult) || \
+                           ((MODE) == ADC_DualMode_Interl) || \
+                           ((MODE) == ADC_DualMode_AlterTrig) || \
+                           ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \
+                           ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \
+                           ((MODE) == ADC_TripleMode_InjecSimult) || \
+                           ((MODE) == ADC_TripleMode_RegSimult) || \
+                           ((MODE) == ADC_TripleMode_Interl) || \
+                           ((MODE) == ADC_TripleMode_AlterTrig))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_Prescaler 
+  * @{
+  */ 
+#define ADC_Prescaler_Div2                         ((uint32_t)0x00000000)
+#define ADC_Prescaler_Div4                         ((uint32_t)0x00010000)
+#define ADC_Prescaler_Div6                         ((uint32_t)0x00020000)
+#define ADC_Prescaler_Div8                         ((uint32_t)0x00030000)
+#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \
+                                     ((PRESCALER) == ADC_Prescaler_Div4) || \
+                                     ((PRESCALER) == ADC_Prescaler_Div6) || \
+                                     ((PRESCALER) == ADC_Prescaler_Div8))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode 
+  * @{
+  */ 
+#define ADC_DMAAccessMode_Disabled      ((uint32_t)0x00000000)     /* DMA mode disabled */
+#define ADC_DMAAccessMode_1             ((uint32_t)0x00004000)     /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
+#define ADC_DMAAccessMode_2             ((uint32_t)0x00008000)     /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
+#define ADC_DMAAccessMode_3             ((uint32_t)0x0000C000)     /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
+#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
+                                      ((MODE) == ADC_DMAAccessMode_1) || \
+                                      ((MODE) == ADC_DMAAccessMode_2) || \
+                                      ((MODE) == ADC_DMAAccessMode_3))
+                                     
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_delay_between_2_sampling_phases 
+  * @{
+  */ 
+#define ADC_TwoSamplingDelay_5Cycles               ((uint32_t)0x00000000)
+#define ADC_TwoSamplingDelay_6Cycles               ((uint32_t)0x00000100)
+#define ADC_TwoSamplingDelay_7Cycles               ((uint32_t)0x00000200)
+#define ADC_TwoSamplingDelay_8Cycles               ((uint32_t)0x00000300)
+#define ADC_TwoSamplingDelay_9Cycles               ((uint32_t)0x00000400)
+#define ADC_TwoSamplingDelay_10Cycles              ((uint32_t)0x00000500)
+#define ADC_TwoSamplingDelay_11Cycles              ((uint32_t)0x00000600)
+#define ADC_TwoSamplingDelay_12Cycles              ((uint32_t)0x00000700)
+#define ADC_TwoSamplingDelay_13Cycles              ((uint32_t)0x00000800)
+#define ADC_TwoSamplingDelay_14Cycles              ((uint32_t)0x00000900)
+#define ADC_TwoSamplingDelay_15Cycles              ((uint32_t)0x00000A00)
+#define ADC_TwoSamplingDelay_16Cycles              ((uint32_t)0x00000B00)
+#define ADC_TwoSamplingDelay_17Cycles              ((uint32_t)0x00000C00)
+#define ADC_TwoSamplingDelay_18Cycles              ((uint32_t)0x00000D00)
+#define ADC_TwoSamplingDelay_19Cycles              ((uint32_t)0x00000E00)
+#define ADC_TwoSamplingDelay_20Cycles              ((uint32_t)0x00000F00)
+#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_20Cycles))
+                                     
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_resolution 
+  * @{
+  */ 
+#define ADC_Resolution_12b                         ((uint32_t)0x00000000)
+#define ADC_Resolution_10b                         ((uint32_t)0x01000000)
+#define ADC_Resolution_8b                          ((uint32_t)0x02000000)
+#define ADC_Resolution_6b                          ((uint32_t)0x03000000)
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
+                                       ((RESOLUTION) == ADC_Resolution_10b) || \
+                                       ((RESOLUTION) == ADC_Resolution_8b) || \
+                                       ((RESOLUTION) == ADC_Resolution_6b))
+                                      
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion 
+  * @{
+  */ 
+#define ADC_ExternalTrigConvEdge_None          ((uint32_t)0x00000000)
+#define ADC_ExternalTrigConvEdge_Rising        ((uint32_t)0x10000000)
+#define ADC_ExternalTrigConvEdge_Falling       ((uint32_t)0x20000000)
+#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)
+#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
+                             ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
+                             ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
+                             ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion 
+  * @{
+  */ 
+#define ADC_ExternalTrigConv_T1_CC1                ((uint32_t)0x00000000)
+#define ADC_ExternalTrigConv_T1_CC2                ((uint32_t)0x01000000)
+#define ADC_ExternalTrigConv_T1_CC3                ((uint32_t)0x02000000)
+#define ADC_ExternalTrigConv_T2_CC2                ((uint32_t)0x03000000)
+#define ADC_ExternalTrigConv_T2_CC3                ((uint32_t)0x04000000)
+#define ADC_ExternalTrigConv_T2_CC4                ((uint32_t)0x05000000)
+#define ADC_ExternalTrigConv_T2_TRGO               ((uint32_t)0x06000000)
+#define ADC_ExternalTrigConv_T3_CC1                ((uint32_t)0x07000000)
+#define ADC_ExternalTrigConv_T3_TRGO               ((uint32_t)0x08000000)
+#define ADC_ExternalTrigConv_T4_CC4                ((uint32_t)0x09000000)
+#define ADC_ExternalTrigConv_T5_CC1                ((uint32_t)0x0A000000)
+#define ADC_ExternalTrigConv_T5_CC2                ((uint32_t)0x0B000000)
+#define ADC_ExternalTrigConv_T5_CC3                ((uint32_t)0x0C000000)
+#define ADC_ExternalTrigConv_T8_CC1                ((uint32_t)0x0D000000)
+#define ADC_ExternalTrigConv_T8_TRGO               ((uint32_t)0x0E000000)
+#define ADC_ExternalTrigConv_Ext_IT11              ((uint32_t)0x0F000000)
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_data_align 
+  * @{
+  */ 
+#define ADC_DataAlign_Right                        ((uint32_t)0x00000000)
+#define ADC_DataAlign_Left                         ((uint32_t)0x00000800)
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
+                                  ((ALIGN) == ADC_DataAlign_Left))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_channels 
+  * @{
+  */ 
+#define ADC_Channel_0                               ((uint8_t)0x00)
+#define ADC_Channel_1                               ((uint8_t)0x01)
+#define ADC_Channel_2                               ((uint8_t)0x02)
+#define ADC_Channel_3                               ((uint8_t)0x03)
+#define ADC_Channel_4                               ((uint8_t)0x04)
+#define ADC_Channel_5                               ((uint8_t)0x05)
+#define ADC_Channel_6                               ((uint8_t)0x06)
+#define ADC_Channel_7                               ((uint8_t)0x07)
+#define ADC_Channel_8                               ((uint8_t)0x08)
+#define ADC_Channel_9                               ((uint8_t)0x09)
+#define ADC_Channel_10                              ((uint8_t)0x0A)
+#define ADC_Channel_11                              ((uint8_t)0x0B)
+#define ADC_Channel_12                              ((uint8_t)0x0C)
+#define ADC_Channel_13                              ((uint8_t)0x0D)
+#define ADC_Channel_14                              ((uint8_t)0x0E)
+#define ADC_Channel_15                              ((uint8_t)0x0F)
+#define ADC_Channel_16                              ((uint8_t)0x10)
+#define ADC_Channel_17                              ((uint8_t)0x11)
+#define ADC_Channel_18                              ((uint8_t)0x12)
+
+#if defined (STM32F40_41xxx)
+#define ADC_Channel_TempSensor                      ((uint8_t)ADC_Channel_16)
+#endif /* STM32F40_41xxx */
+
+#if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) || defined (STM32F411xE)
+#define ADC_Channel_TempSensor                      ((uint8_t)ADC_Channel_18)
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
+
+#define ADC_Channel_Vrefint                         ((uint8_t)ADC_Channel_17)
+#define ADC_Channel_Vbat                            ((uint8_t)ADC_Channel_18)
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \
+                                 ((CHANNEL) == ADC_Channel_1) || \
+                                 ((CHANNEL) == ADC_Channel_2) || \
+                                 ((CHANNEL) == ADC_Channel_3) || \
+                                 ((CHANNEL) == ADC_Channel_4) || \
+                                 ((CHANNEL) == ADC_Channel_5) || \
+                                 ((CHANNEL) == ADC_Channel_6) || \
+                                 ((CHANNEL) == ADC_Channel_7) || \
+                                 ((CHANNEL) == ADC_Channel_8) || \
+                                 ((CHANNEL) == ADC_Channel_9) || \
+                                 ((CHANNEL) == ADC_Channel_10) || \
+                                 ((CHANNEL) == ADC_Channel_11) || \
+                                 ((CHANNEL) == ADC_Channel_12) || \
+                                 ((CHANNEL) == ADC_Channel_13) || \
+                                 ((CHANNEL) == ADC_Channel_14) || \
+                                 ((CHANNEL) == ADC_Channel_15) || \
+                                 ((CHANNEL) == ADC_Channel_16) || \
+                                 ((CHANNEL) == ADC_Channel_17) || \
+                                 ((CHANNEL) == ADC_Channel_18))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_sampling_times 
+  * @{
+  */ 
+#define ADC_SampleTime_3Cycles                    ((uint8_t)0x00)
+#define ADC_SampleTime_15Cycles                   ((uint8_t)0x01)
+#define ADC_SampleTime_28Cycles                   ((uint8_t)0x02)
+#define ADC_SampleTime_56Cycles                   ((uint8_t)0x03)
+#define ADC_SampleTime_84Cycles                   ((uint8_t)0x04)
+#define ADC_SampleTime_112Cycles                  ((uint8_t)0x05)
+#define ADC_SampleTime_144Cycles                  ((uint8_t)0x06)
+#define ADC_SampleTime_480Cycles                  ((uint8_t)0x07)
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \
+                                  ((TIME) == ADC_SampleTime_15Cycles) || \
+                                  ((TIME) == ADC_SampleTime_28Cycles) || \
+                                  ((TIME) == ADC_SampleTime_56Cycles) || \
+                                  ((TIME) == ADC_SampleTime_84Cycles) || \
+                                  ((TIME) == ADC_SampleTime_112Cycles) || \
+                                  ((TIME) == ADC_SampleTime_144Cycles) || \
+                                  ((TIME) == ADC_SampleTime_480Cycles))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion 
+  * @{
+  */ 
+#define ADC_ExternalTrigInjecConvEdge_None          ((uint32_t)0x00000000)
+#define ADC_ExternalTrigInjecConvEdge_Rising        ((uint32_t)0x00100000)
+#define ADC_ExternalTrigInjecConvEdge_Falling       ((uint32_t)0x00200000)
+#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)
+#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \
+                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \
+                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \
+                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))
+                                            
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion 
+  * @{
+  */ 
+#define ADC_ExternalTrigInjecConv_T1_CC4            ((uint32_t)0x00000000)
+#define ADC_ExternalTrigInjecConv_T1_TRGO           ((uint32_t)0x00010000)
+#define ADC_ExternalTrigInjecConv_T2_CC1            ((uint32_t)0x00020000)
+#define ADC_ExternalTrigInjecConv_T2_TRGO           ((uint32_t)0x00030000)
+#define ADC_ExternalTrigInjecConv_T3_CC2            ((uint32_t)0x00040000)
+#define ADC_ExternalTrigInjecConv_T3_CC4            ((uint32_t)0x00050000)
+#define ADC_ExternalTrigInjecConv_T4_CC1            ((uint32_t)0x00060000)
+#define ADC_ExternalTrigInjecConv_T4_CC2            ((uint32_t)0x00070000)
+#define ADC_ExternalTrigInjecConv_T4_CC3            ((uint32_t)0x00080000)
+#define ADC_ExternalTrigInjecConv_T4_TRGO           ((uint32_t)0x00090000)
+#define ADC_ExternalTrigInjecConv_T5_CC4            ((uint32_t)0x000A0000)
+#define ADC_ExternalTrigInjecConv_T5_TRGO           ((uint32_t)0x000B0000)
+#define ADC_ExternalTrigInjecConv_T8_CC2            ((uint32_t)0x000C0000)
+#define ADC_ExternalTrigInjecConv_T8_CC3            ((uint32_t)0x000D0000)
+#define ADC_ExternalTrigInjecConv_T8_CC4            ((uint32_t)0x000E0000)
+#define ADC_ExternalTrigInjecConv_Ext_IT15          ((uint32_t)0x000F0000)
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_injected_channel_selection 
+  * @{
+  */ 
+#define ADC_InjectedChannel_1                       ((uint8_t)0x14)
+#define ADC_InjectedChannel_2                       ((uint8_t)0x18)
+#define ADC_InjectedChannel_3                       ((uint8_t)0x1C)
+#define ADC_InjectedChannel_4                       ((uint8_t)0x20)
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_2) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_3) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_4))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_analog_watchdog_selection 
+  * @{
+  */ 
+#define ADC_AnalogWatchdog_SingleRegEnable         ((uint32_t)0x00800200)
+#define ADC_AnalogWatchdog_SingleInjecEnable       ((uint32_t)0x00400200)
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable  ((uint32_t)0x00C00200)
+#define ADC_AnalogWatchdog_AllRegEnable            ((uint32_t)0x00800000)
+#define ADC_AnalogWatchdog_AllInjecEnable          ((uint32_t)0x00400000)
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable    ((uint32_t)0x00C00000)
+#define ADC_AnalogWatchdog_None                    ((uint32_t)0x00000000)
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_None))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_interrupts_definition 
+  * @{
+  */ 
+#define ADC_IT_EOC                                 ((uint16_t)0x0205)  
+#define ADC_IT_AWD                                 ((uint16_t)0x0106)  
+#define ADC_IT_JEOC                                ((uint16_t)0x0407)  
+#define ADC_IT_OVR                                 ((uint16_t)0x201A)  
+#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
+                       ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_flags_definition 
+  * @{
+  */ 
+#define ADC_FLAG_AWD                               ((uint8_t)0x01)
+#define ADC_FLAG_EOC                               ((uint8_t)0x02)
+#define ADC_FLAG_JEOC                              ((uint8_t)0x04)
+#define ADC_FLAG_JSTRT                             ((uint8_t)0x08)
+#define ADC_FLAG_STRT                              ((uint8_t)0x10)
+#define ADC_FLAG_OVR                               ((uint8_t)0x20)   
+  
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00))   
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \
+                               ((FLAG) == ADC_FLAG_EOC) || \
+                               ((FLAG) == ADC_FLAG_JEOC) || \
+                               ((FLAG)== ADC_FLAG_JSTRT) || \
+                               ((FLAG) == ADC_FLAG_STRT) || \
+                               ((FLAG)== ADC_FLAG_OVR))     
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_thresholds 
+  * @{
+  */ 
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_injected_offset 
+  * @{
+  */ 
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_injected_length 
+  * @{
+  */ 
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_injected_rank 
+  * @{
+  */ 
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_regular_length 
+  * @{
+  */ 
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_regular_rank 
+  * @{
+  */ 
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_regular_discontinuous_mode_number 
+  * @{
+  */ 
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
+/**
+  * @}
+  */ 
+
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/  
+
+/*  Function used to set the ADC configuration to the default reset state *****/  
+void ADC_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
+void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+
+/* Analog Watchdog configuration functions ************************************/
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
+
+/* Temperature Sensor, Vrefint and VBAT management functions ******************/
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);
+void ADC_VBATCmd(FunctionalState NewState);
+
+/* Regular Channels Configuration functions ***********************************/
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
+void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
+uint32_t ADC_GetMultiModeConversionValue(void);
+
+/* Regular Channels DMA Configuration functions *******************************/
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState);
+
+/* Injected channels Configuration functions **********************************/
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
+void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);
+void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
+
+/* Interrupts and flags management functions **********************************/
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_ADC_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/hardware_can.h

@@ -0,0 +1,657 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_can.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    30-September-2011
+  * @brief   This file contains all the functions prototypes for the CAN firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/**
+* @file: hardware_can.h
+* @brief: define hardware can function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/*************************************************
+File name: hardware_can.h
+Description: define hardware can function
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_can.h for XiZi
+*************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HARDWARE_CAN_H__
+#define __HARDWARE_CAN_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stm32f4xx.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CAN
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
+                                   ((PERIPH) == CAN2))
+
+/** 
+  * @brief  CAN init structure definition
+  */
+typedef struct
+{
+  uint16_t CAN_Prescaler;   /*!< Specifies the length of a time quantum. 
+                                 It ranges from 1 to 1024. */
+  
+  uint8_t CAN_Mode;         /*!< Specifies the CAN operating mode.
+                                 This parameter can be a value of @ref CAN_operating_mode */
+
+  uint8_t CAN_SJW;          /*!< Specifies the maximum number of time quanta 
+                                 the CAN hardware is allowed to lengthen or 
+                                 shorten a bit to perform resynchronization.
+                                 This parameter can be a value of @ref CAN_synchronisation_jump_width */
+
+  uint8_t CAN_BS1;          /*!< Specifies the number of time quanta in Bit 
+                                 Segment 1. This parameter can be a value of 
+                                 @ref CAN_time_quantum_in_bit_segment_1 */
+
+  uint8_t CAN_BS2;          /*!< Specifies the number of time quanta in Bit Segment 2.
+                                 This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+  
+  FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.
+                                This parameter can be set either to ENABLE or DISABLE. */
+  
+  FunctionalState CAN_ABOM;  /*!< Enable or disable the automatic bus-off management.
+                                  This parameter can be set either to ENABLE or DISABLE. */
+
+  FunctionalState CAN_AWUM;  /*!< Enable or disable the automatic wake-up mode. 
+                                  This parameter can be set either to ENABLE or DISABLE. */
+
+  FunctionalState CAN_NART;  /*!< Enable or disable the non-automatic retransmission mode.
+                                  This parameter can be set either to ENABLE or DISABLE. */
+
+  FunctionalState CAN_RFLM;  /*!< Enable or disable the Receive FIFO Locked mode.
+                                  This parameter can be set either to ENABLE or DISABLE. */
+
+  FunctionalState CAN_TXFP;  /*!< Enable or disable the transmit FIFO priority.
+                                  This parameter can be set either to ENABLE or DISABLE. */
+} CAN_InitTypeDef;
+
+/** 
+  * @brief  CAN filter init structure definition
+  */
+typedef struct
+{
+  uint16_t CAN_FilterIdHigh;         /*!< Specifies the filter identification number (MSBs for a 32-bit
+                                              configuration, first one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterIdLow;          /*!< Specifies the filter identification number (LSBs for a 32-bit
+                                              configuration, second one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterMaskIdHigh;     /*!< Specifies the filter mask number or identification number,
+                                              according to the mode (MSBs for a 32-bit configuration,
+                                              first one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterMaskIdLow;      /*!< Specifies the filter mask number or identification number,
+                                              according to the mode (LSBs for a 32-bit configuration,
+                                              second one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+                                              This parameter can be a value of @ref CAN_filter_FIFO */
+  
+  uint8_t CAN_FilterNumber;          /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
+
+  uint8_t CAN_FilterMode;            /*!< Specifies the filter mode to be initialized.
+                                              This parameter can be a value of @ref CAN_filter_mode */
+
+  uint8_t CAN_FilterScale;           /*!< Specifies the filter scale.
+                                              This parameter can be a value of @ref CAN_filter_scale */
+
+  FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
+                                              This parameter can be set either to ENABLE or DISABLE. */
+} CAN_FilterInitTypeDef;
+
+/** 
+  * @brief  CAN Tx message structure definition  
+  */
+typedef struct
+{
+  uint32_t StdId;  /*!< Specifies the standard identifier.
+                        This parameter can be a value between 0 to 0x7FF. */
+
+  uint32_t ExtId;  /*!< Specifies the extended identifier.
+                        This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+  uint8_t IDE;     /*!< Specifies the type of identifier for the message that 
+                        will be transmitted. This parameter can be a value 
+                        of @ref CAN_identifier_type */
+
+  uint8_t RTR;     /*!< Specifies the type of frame for the message that will 
+                        be transmitted. This parameter can be a value of 
+                        @ref CAN_remote_transmission_request */
+
+  uint8_t DLC;     /*!< Specifies the length of the frame that will be 
+                        transmitted. This parameter can be a value between 
+                        0 to 8 */
+
+  uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 
+                        to 0xFF. */
+} CanTxMsg;
+
+/** 
+  * @brief  CAN Rx message structure definition  
+  */
+typedef struct
+{
+  uint32_t StdId;  /*!< Specifies the standard identifier.
+                        This parameter can be a value between 0 to 0x7FF. */
+
+  uint32_t ExtId;  /*!< Specifies the extended identifier.
+                        This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+  uint8_t IDE;     /*!< Specifies the type of identifier for the message that 
+                        will be received. This parameter can be a value of 
+                        @ref CAN_identifier_type */
+
+  uint8_t RTR;     /*!< Specifies the type of frame for the received message.
+                        This parameter can be a value of 
+                        @ref CAN_remote_transmission_request */
+
+  uint8_t DLC;     /*!< Specifies the length of the frame that will be received.
+                        This parameter can be a value between 0 to 8 */
+
+  uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 
+                        0xFF. */
+
+  uint8_t FMI;     /*!< Specifies the index of the filter the message stored in 
+                        the mailbox passes through. This parameter can be a 
+                        value between 0 to 0xFF */
+} CanRxMsg;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CAN_Exported_Constants
+  * @{
+  */
+
+/** @defgroup CAN_InitStatus 
+  * @{
+  */
+
+#define CAN_InitStatus_Failed                 ((uint8_t)0x00) /*!< CAN initialization failed */
+#define CAN_InitStatus_Success             ((uint8_t)0x01) /*!< CAN initialization OK */
+
+
+/* Legacy defines */
+#define CANINITFAILED    CAN_InitStatus_Failed
+#define CANINITOK        CAN_InitStatus_Success
+/**
+  * @}
+  */
+
+/** @defgroup CAN_operating_mode 
+  * @{
+  */
+
+#define CAN_Mode_Normal                        ((uint8_t)0x00)  /*!< normal mode */
+#define CAN_Mode_LoopBack                   ((uint8_t)0x01)  /*!< loopback mode */
+#define CAN_Mode_Silent                            ((uint8_t)0x02)  /*!< silent mode */
+#define CAN_Mode_Silent_LoopBack    ((uint8_t)0x03)  /*!< loopback combined with silent mode */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
+                           ((MODE) == CAN_Mode_LoopBack)|| \
+                           ((MODE) == CAN_Mode_Silent) || \
+                           ((MODE) == CAN_Mode_Silent_LoopBack))
+/**
+  * @}
+  */
+
+
+ /**
+  * @defgroup CAN_operating_mode 
+  * @{
+  */  
+#define CAN_OperatingMode_Initialization  ((uint8_t)0x00) /*!< Initialization mode */
+#define CAN_OperatingMode_Normal          ((uint8_t)0x01) /*!< Normal mode */
+#define CAN_OperatingMode_Sleep           ((uint8_t)0x02) /*!< sleep mode */
+
+
+#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
+                                    ((MODE) == CAN_OperatingMode_Normal)|| \
+																		((MODE) == CAN_OperatingMode_Sleep))
+/**
+  * @}
+  */
+  
+/**
+  * @defgroup CAN_operating_mode_status
+  * @{
+  */  
+
+#define CAN_ModeStatus_Failed    ((uint8_t)0x00)                /*!< CAN entering the specific mode failed */
+#define CAN_ModeStatus_Success   ((uint8_t)!CAN_ModeStatus_Failed)   /*!< CAN entering the specific mode Succeed */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_synchronisation_jump_width 
+  * @{
+  */
+#define CAN_SJW_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_SJW_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_SJW_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_SJW_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
+
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
+                         ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1 
+  * @{
+  */
+#define CAN_BS1_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_BS1_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_BS1_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_BS1_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
+#define CAN_BS1_5tq                 ((uint8_t)0x04)  /*!< 5 time quantum */
+#define CAN_BS1_6tq                 ((uint8_t)0x05)  /*!< 6 time quantum */
+#define CAN_BS1_7tq                 ((uint8_t)0x06)  /*!< 7 time quantum */
+#define CAN_BS1_8tq                 ((uint8_t)0x07)  /*!< 8 time quantum */
+#define CAN_BS1_9tq                 ((uint8_t)0x08)  /*!< 9 time quantum */
+#define CAN_BS1_10tq                ((uint8_t)0x09)  /*!< 10 time quantum */
+#define CAN_BS1_11tq                ((uint8_t)0x0A)  /*!< 11 time quantum */
+#define CAN_BS1_12tq                ((uint8_t)0x0B)  /*!< 12 time quantum */
+#define CAN_BS1_13tq                ((uint8_t)0x0C)  /*!< 13 time quantum */
+#define CAN_BS1_14tq                ((uint8_t)0x0D)  /*!< 14 time quantum */
+#define CAN_BS1_15tq                ((uint8_t)0x0E)  /*!< 15 time quantum */
+#define CAN_BS1_16tq                ((uint8_t)0x0F)  /*!< 16 time quantum */
+
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2 
+  * @{
+  */
+#define CAN_BS2_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_BS2_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_BS2_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_BS2_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
+#define CAN_BS2_5tq                 ((uint8_t)0x04)  /*!< 5 time quantum */
+#define CAN_BS2_6tq                 ((uint8_t)0x05)  /*!< 6 time quantum */
+#define CAN_BS2_7tq                 ((uint8_t)0x06)  /*!< 7 time quantum */
+#define CAN_BS2_8tq                 ((uint8_t)0x07)  /*!< 8 time quantum */
+
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_clock_prescaler 
+  * @{
+  */
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_number 
+  * @{
+  */
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_mode 
+  * @{
+  */
+#define CAN_FilterMode_IdMask       ((uint8_t)0x00)  /*!< identifier/mask mode */
+#define CAN_FilterMode_IdList       ((uint8_t)0x01)  /*!< identifier list mode */
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
+                                  ((MODE) == CAN_FilterMode_IdList))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_scale 
+  * @{
+  */
+#define CAN_FilterScale_16bit       ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_FilterScale_32bit       ((uint8_t)0x01) /*!< One 32-bit filter */
+
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
+                                    ((SCALE) == CAN_FilterScale_32bit))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_FIFO
+  * @{
+  */
+#define CAN_Filter_FIFO0             ((uint8_t)0x00)  /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_Filter_FIFO1             ((uint8_t)0x01)  /*!< Filter FIFO 1 assignment for filter x */
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
+                                  ((FIFO) == CAN_FilterFIFO1))
+
+/* Legacy defines */
+#define CAN_FilterFIFO0  CAN_Filter_FIFO0
+#define CAN_FilterFIFO1  CAN_Filter_FIFO1
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Start_bank_filter_for_slave_CAN 
+  * @{
+  */
+#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Tx 
+  * @{
+  */
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_identifier_type 
+  * @{
+  */
+#define CAN_Id_Standard             ((uint32_t)0x00000000)  /*!< Standard Id */
+#define CAN_Id_Extended             ((uint32_t)0x00000004)  /*!< Extended Id */
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
+                               ((IDTYPE) == CAN_Id_Extended))
+
+/* Legacy defines */
+#define CAN_ID_STD      CAN_Id_Standard           
+#define CAN_ID_EXT      CAN_Id_Extended
+/**
+  * @}
+  */
+
+/** @defgroup CAN_remote_transmission_request 
+  * @{
+  */
+#define CAN_RTR_Data                ((uint32_t)0x00000000)  /*!< Data frame */
+#define CAN_RTR_Remote              ((uint32_t)0x00000002)  /*!< Remote frame */
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
+
+/* Legacy defines */
+#define CAN_RTR_DATA     CAN_RTR_Data         
+#define CAN_RTR_REMOTE   CAN_RTR_Remote
+/**
+  * @}
+  */
+
+/** @defgroup CAN_transmit_constants 
+  * @{
+  */
+#define CAN_TxStatus_Failed         ((uint8_t)0x00)/*!< CAN transmission failed */
+#define CAN_TxStatus_Ok             ((uint8_t)0x01) /*!< CAN transmission succeeded */
+#define CAN_TxStatus_Pending        ((uint8_t)0x02) /*!< CAN transmission pending */
+#define CAN_TxStatus_NoMailBox      ((uint8_t)0x04) /*!< CAN cell did not provide 
+                                                         an empty mailbox */
+/* Legacy defines */	
+#define CANTXFAILED                  CAN_TxStatus_Failed
+#define CANTXOK                      CAN_TxStatus_Ok
+#define CANTXPENDING                 CAN_TxStatus_Pending
+#define CAN_NO_MB                    CAN_TxStatus_NoMailBox
+/**
+  * @}
+  */
+
+/** @defgroup CAN_receive_FIFO_number_constants 
+  * @{
+  */
+#define CAN_FIFO0                 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
+#define CAN_FIFO1                 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
+
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_sleep_constants 
+  * @{
+  */
+#define CAN_Sleep_Failed     ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
+#define CAN_Sleep_Ok         ((uint8_t)0x01) /*!< CAN entered the sleep mode */
+
+/* Legacy defines */	
+#define CANSLEEPFAILED   CAN_Sleep_Failed
+#define CANSLEEPOK       CAN_Sleep_Ok
+/**
+  * @}
+  */
+
+/** @defgroup CAN_wake_up_constants 
+  * @{
+  */
+#define CAN_WakeUp_Failed        ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
+#define CAN_WakeUp_Ok            ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
+
+/* Legacy defines */
+#define CANWAKEUPFAILED   CAN_WakeUp_Failed        
+#define CANWAKEUPOK       CAN_WakeUp_Ok        
+/**
+  * @}
+  */
+
+/**
+  * @defgroup CAN_Error_Code_constants
+  * @{
+  */                                                         
+#define CAN_ErrorCode_NoErr           ((uint8_t)0x00) /*!< No Error */ 
+#define	CAN_ErrorCode_StuffErr        ((uint8_t)0x10) /*!< Stuff Error */ 
+#define	CAN_ErrorCode_FormErr         ((uint8_t)0x20) /*!< Form Error */ 
+#define	CAN_ErrorCode_ACKErr          ((uint8_t)0x30) /*!< Acknowledgment Error */ 
+#define	CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ 
+#define	CAN_ErrorCode_BitDominantErr  ((uint8_t)0x50) /*!< Bit Dominant Error */ 
+#define	CAN_ErrorCode_CRCErr          ((uint8_t)0x60) /*!< CRC Error  */ 
+#define	CAN_ErrorCode_SoftwareSetErr  ((uint8_t)0x70) /*!< Software Set Error */ 
+/**
+  * @}
+  */
+
+/** @defgroup CAN_flags 
+  * @{
+  */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
+   and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with 
+   CAN_GetFlagStatus() function.  */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0             ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
+#define CAN_FLAG_RQCP1             ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
+#define CAN_FLAG_RQCP2             ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FMP0              ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
+#define CAN_FLAG_FF0               ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag            */
+#define CAN_FLAG_FOV0              ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag         */
+#define CAN_FLAG_FMP1              ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
+#define CAN_FLAG_FF1               ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag            */
+#define CAN_FLAG_FOV1              ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag         */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU               ((uint32_t)0x31000008) /*!< Wake up Flag */
+#define CAN_FLAG_SLAK              ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
+/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. 
+         In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWG               ((uint32_t)0x10F00001) /*!< Error Warning Flag   */
+#define CAN_FLAG_EPV               ((uint32_t)0x10F00002) /*!< Error Passive Flag   */
+#define CAN_FLAG_BOF               ((uint32_t)0x10F00004) /*!< Bus-Off Flag         */
+#define CAN_FLAG_LEC               ((uint32_t)0x30F00070) /*!< Last error code Flag */
+
+#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC)  || ((FLAG) == CAN_FLAG_BOF)   || \
+                               ((FLAG) == CAN_FLAG_EPV)  || ((FLAG) == CAN_FLAG_EWG)   || \
+                               ((FLAG) == CAN_FLAG_WKU)  || ((FLAG) == CAN_FLAG_FOV0)  || \
+                               ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FMP0)  || \
+                               ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1)   || \
+                               ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
+                               ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
+                               ((FLAG) == CAN_FLAG_SLAK ))
+
+#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
+                                ((FLAG) == CAN_FLAG_RQCP1)  || ((FLAG) == CAN_FLAG_RQCP0) || \
+                                ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FOV0) ||\
+                                ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
+                                ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
+/**
+  * @}
+  */
+
+  
+/** @defgroup CAN_interrupts 
+  * @{
+  */ 
+#define CAN_IT_TME                  ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
+
+/* Receive Interrupts */
+#define CAN_IT_FMP0                 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
+#define CAN_IT_FF0                  ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
+#define CAN_IT_FOV0                 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
+#define CAN_IT_FMP1                 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
+#define CAN_IT_FF1                  ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
+#define CAN_IT_FOV1                 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WKU                  ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
+#define CAN_IT_SLK                  ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
+
+/* Error Interrupts */
+#define CAN_IT_EWG                  ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
+#define CAN_IT_EPV                  ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
+#define CAN_IT_BOF                  ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
+#define CAN_IT_LEC                  ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
+#define CAN_IT_ERR                  ((uint32_t)0x00008000) /*!< Error Interrupt*/
+
+/* Flags named as Interrupts : kept only for FW compatibility */
+#define CAN_IT_RQCP0   CAN_IT_TME
+#define CAN_IT_RQCP1   CAN_IT_TME
+#define CAN_IT_RQCP2   CAN_IT_TME
+
+
+#define IS_CAN_IT(IT)        (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0)  ||\
+                             ((IT) == CAN_IT_FF0)  || ((IT) == CAN_IT_FOV0)  ||\
+                             ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1)   ||\
+                             ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG)   ||\
+                             ((IT) == CAN_IT_EPV)  || ((IT) == CAN_IT_BOF)   ||\
+                             ((IT) == CAN_IT_LEC)  || ((IT) == CAN_IT_ERR)   ||\
+                             ((IT) == CAN_IT_WKU)  || ((IT) == CAN_IT_SLK))
+
+#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0)    ||\
+                             ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1)    ||\
+                             ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG)    ||\
+                             ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF)    ||\
+                             ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR)    ||\
+                             ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/  
+
+/*  Function used to set the CAN configuration to the default reset state *****/ 
+void CAN_DeInit(CAN_TypeDef* CANx);
+
+/* Initialization and Configuration functions *********************************/ 
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber); 
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
+
+/* CAN Frames Transmission functions ******************************************/
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
+
+/* CAN Frames Reception functions *********************************************/
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
+
+/* Operation modes functions **************************************************/
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
+uint8_t CAN_Sleep(CAN_TypeDef* CANx);
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
+
+/* CAN Bus Error management functions *****************************************/
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
+
+/* Interrupts and flags management functions **********************************/
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HARDWARE_CAN_H__ */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/hardware_conf.h

@@ -0,0 +1,105 @@
+/**
+  ******************************************************************************
+  * @file    IO_Toggle/stm32f4xx_conf.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    19-September-2011
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/**
+* @file: hardware_conf.h
+* @brief: define hardware conf function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/*************************************************
+File name: hardware_conf.h
+Description: define hardware conf function
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_conf.h for XiZi
+*************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HARDWARE_CONF_H__
+#define __HARDWARE_CONF_H__
+
+#if defined  (HSE_VALUE)
+/* Redefine the HSE value; it's equal to 8 MHz on the STM32F4-DISCOVERY Kit */
+ #undef HSE_VALUE
+ #define HSE_VALUE    ((uint32_t)8000000)
+#endif /* HSE_VALUE */
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment the line below to enable peripheral header file inclusion */
+#include "hardware_can.h"
+#include "hardware_dbgmcu.h"
+#include "hardware_dma.h"
+#include "hardware_exti.h"
+#include "hardware_fsmc.h"
+#include "hardware_gpio.h"
+#include "hardware_i2c.h"
+#include "hardware_iwdg.h"
+#include "hardware_pwr.h"
+#include "hardware_rcc.h"
+#include "hardware_rtc.h"
+#include "hardware_sdio.h"
+#include "hardware_spi.h"
+#include "hardware_syscfg.h"
+#include "hardware_tim.h"
+#include "hardware_usart.h"
+#include "hardware_wwdg.h"
+#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* If an external clock source is used, then the value of the following define
+   should be set to the value of the external clock source, else, if no external
+   clock is used, keep this define commented */
+/*#define I2S_EXTERNAL_CLOCK_VAL   12288000 */ /* Value of the external clock in Hz */
+
+
+/* Uncomment the line below to expanse the "assert_param" macro in the
+   Standard Peripheral Library drivers code */
+//#define USE_FULL_ASSERT    1
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *   which reports the name of the source file and the source
+  *   line number of the call that failed.
+  *   If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __HARDWARE_CONF_H__ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/hardware_dac.h

@@ -0,0 +1,323 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_dac.h
+  * @author  MCD Application Team
+  * @version V1.4.0
+  * @date    04-August-2014
+  * @brief   This file contains all the functions prototypes for the DAC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/**
+* @file: hardware_dac.h
+* @brief: define hardware dac function
+* @version: 2.0
+* @author:  AIIT XUOS Lab
+* @date:    2022/1/10
+*/
+
+/*************************************************
+File name: hardware_dac.h
+Description: define hardware dac function
+Others: 
+History: 
+1. Date: 2022-1-10
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_dac.h for XiZi
+*************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HARDWARE_DAC_H__
+#define __HARDWARE_DAC_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DAC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  DAC Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t DAC_Trigger;                      /*!< Specifies the external trigger for the selected DAC channel.
+                                                  This parameter can be a value of @ref DAC_trigger_selection */
+
+  uint32_t DAC_WaveGeneration;               /*!< Specifies whether DAC channel noise waves or triangle waves
+                                                  are generated, or whether no wave is generated.
+                                                  This parameter can be a value of @ref DAC_wave_generation */
+
+  uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
+                                                  the maximum amplitude triangle generation for the DAC channel. 
+                                                  This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
+
+  uint32_t DAC_OutputBuffer;                 /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+                                                  This parameter can be a value of @ref DAC_output_buffer */
+}DAC_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup DAC_trigger_selection 
+  * @{
+  */
+
+#define DAC_Trigger_None                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
+                                                                       has been loaded, and not by external trigger */
+#define DAC_Trigger_T2_TRGO                ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T4_TRGO                ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T5_TRGO                ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T6_TRGO                ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T7_TRGO                ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T8_TRGO                ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */                                                                       
+
+#define DAC_Trigger_Ext_IT9                ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Software               ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
+                                 ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T5_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
+                                 ((TRIGGER) == DAC_Trigger_Software))
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_wave_generation 
+  * @{
+  */
+
+#define DAC_WaveGeneration_None            ((uint32_t)0x00000000)
+#define DAC_WaveGeneration_Noise           ((uint32_t)0x00000040)
+#define DAC_WaveGeneration_Triangle        ((uint32_t)0x00000080)
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
+                                    ((WAVE) == DAC_WaveGeneration_Noise) || \
+                                    ((WAVE) == DAC_WaveGeneration_Triangle))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_lfsrunmask_triangleamplitude
+  * @{
+  */
+
+#define DAC_LFSRUnmask_Bit0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUnmask_Bits1_0             ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits2_0             ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits3_0             ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits4_0             ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits5_0             ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits6_0             ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits7_0             ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits8_0             ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits9_0             ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits10_0            ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits11_0            ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TriangleAmplitude_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TriangleAmplitude_3            ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
+#define DAC_TriangleAmplitude_7            ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
+#define DAC_TriangleAmplitude_15           ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
+#define DAC_TriangleAmplitude_31           ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
+#define DAC_TriangleAmplitude_63           ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
+#define DAC_TriangleAmplitude_127          ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
+#define DAC_TriangleAmplitude_255          ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
+#define DAC_TriangleAmplitude_511          ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
+#define DAC_TriangleAmplitude_1023         ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TriangleAmplitude_2047         ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TriangleAmplitude_4095         ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_1) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_3) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_7) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_15) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_31) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_63) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_127) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_255) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_511) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_1023) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_2047) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_4095))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_output_buffer 
+  * @{
+  */
+
+#define DAC_OutputBuffer_Enable            ((uint32_t)0x00000000)
+#define DAC_OutputBuffer_Disable           ((uint32_t)0x00000002)
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
+                                           ((STATE) == DAC_OutputBuffer_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Channel_selection 
+  * @{
+  */
+
+#define DAC_Channel_1                      ((uint32_t)0x00000000)
+#define DAC_Channel_2                      ((uint32_t)0x00000010)
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
+                                 ((CHANNEL) == DAC_Channel_2))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data_alignement 
+  * @{
+  */
+
+#define DAC_Align_12b_R                    ((uint32_t)0x00000000)
+#define DAC_Align_12b_L                    ((uint32_t)0x00000004)
+#define DAC_Align_8b_R                     ((uint32_t)0x00000008)
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
+                             ((ALIGN) == DAC_Align_12b_L) || \
+                             ((ALIGN) == DAC_Align_8b_R))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_wave_generation 
+  * @{
+  */
+
+#define DAC_Wave_Noise                     ((uint32_t)0x00000040)
+#define DAC_Wave_Triangle                  ((uint32_t)0x00000080)
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
+                           ((WAVE) == DAC_Wave_Triangle))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data 
+  * @{
+  */
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) 
+/**
+  * @}
+  */
+  
+/** @defgroup DAC_interrupts_definition 
+  * @{
+  */   
+#define DAC_IT_DMAUDR                      ((uint32_t)0x00002000)  
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup DAC_flags_definition 
+  * @{
+  */ 
+  
+#define DAC_FLAG_DMAUDR                    ((uint32_t)0x00002000)  
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))  
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/  
+
+/*  Function used to set the DAC configuration to the default reset state *****/  
+void DAC_DeInit(void);
+
+/*  DAC channels configuration: trigger, output buffer, data format functions */
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
+
+/* DMA management functions ***************************************************/
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__HARDWARE_DAC_H__ */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/hardware_dbgmcu.h

@@ -0,0 +1,122 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_dbgmcu.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    30-September-2011
+  * @brief   This file contains all the functions prototypes for the DBGMCU firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/**
+* @file: hardware_dbgmcu.h
+* @brief: define hardware dbgmcu function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/*************************************************
+File name: hardware_dbgmcu.h
+Description: define hardware dbgmcu function
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_dbgmcu.h for XiZi
+*************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HARDWARE_DBGMCU_H__
+#define __HARDWARE_DBGMCU_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stm32f4xx.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DBGMCU
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DBGMCU_Exported_Constants
+  * @{
+  */ 
+#define DBGMCU_SLEEP                 ((uint32_t)0x00000001)
+#define DBGMCU_STOP                  ((uint32_t)0x00000002)
+#define DBGMCU_STANDBY               ((uint32_t)0x00000004)
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
+
+#define DBGMCU_TIM2_STOP             ((uint32_t)0x00000001)
+#define DBGMCU_TIM3_STOP             ((uint32_t)0x00000002)
+#define DBGMCU_TIM4_STOP             ((uint32_t)0x00000004)
+#define DBGMCU_TIM5_STOP             ((uint32_t)0x00000008)
+#define DBGMCU_TIM6_STOP             ((uint32_t)0x00000010)
+#define DBGMCU_TIM7_STOP             ((uint32_t)0x00000020)
+#define DBGMCU_TIM12_STOP            ((uint32_t)0x00000040)
+#define DBGMCU_TIM13_STOP            ((uint32_t)0x00000080)
+#define DBGMCU_TIM14_STOP            ((uint32_t)0x00000100)
+#define DBGMCU_RTC_STOP              ((uint32_t)0x00000400)
+#define DBGMCU_WWDG_STOP             ((uint32_t)0x00000800)
+#define DBGMCU_IWDG_STOP             ((uint32_t)0x00001000)
+#define DBGMCU_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00200000)
+#define DBGMCU_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00400000)
+#define DBGMCU_I2C3_SMBUS_TIMEOUT    ((uint32_t)0x00800000)
+#define DBGMCU_CAN1_STOP             ((uint32_t)0x02000000)
+#define DBGMCU_CAN2_STOP             ((uint32_t)0x04000000)
+#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xF91FE200) == 0x00) && ((PERIPH) != 0x00))
+
+#define DBGMCU_TIM1_STOP             ((uint32_t)0x00000001)
+#define DBGMCU_TIM8_STOP             ((uint32_t)0x00000002)
+#define DBGMCU_TIM9_STOP             ((uint32_t)0x00010000)
+#define DBGMCU_TIM10_STOP            ((uint32_t)0x00020000)
+#define DBGMCU_TIM11_STOP            ((uint32_t)0x00040000)
+#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8FFFC) == 0x00) && ((PERIPH) != 0x00))
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+uint32_t DBGMCU_GetREVID(void);
+uint32_t DBGMCU_GetDEVID(void);
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HARDWARE_DBGMCU_H__ */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/hardware_dma.h

@@ -0,0 +1,622 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_dma.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    30-September-2011
+  * @brief   This file contains all the functions prototypes for the DMA firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+
+/**
+* @file: hardware_dma.h
+* @brief: define hardware dma function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/*************************************************
+File name: hardware_dma.h
+Description: define hardware dma function
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_dma.h for XiZi
+*************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HARDWARE_DMA_H__
+#define __HARDWARE_DMA_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stm32f4xx.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  DMA Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t DMA_Channel;            /*!< Specifies the channel used for the specified stream. 
+                                        This parameter can be a value of @ref DMA_channel */
+ 
+  uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */
+
+  uint32_t DMA_Memory0BaseAddr;    /*!< Specifies the memory 0 base address for DMAy Streamx. 
+                                        This memory is the default memory used when double buffer mode is
+                                        not enabled. */
+
+  uint32_t DMA_DIR;                /*!< Specifies if the data will be transferred from memory to peripheral, 
+                                        from memory to memory or from peripheral to memory.
+                                        This parameter can be a value of @ref DMA_data_transfer_direction */
+
+  uint32_t DMA_BufferSize;         /*!< Specifies the buffer size, in data unit, of the specified Stream. 
+                                        The data unit is equal to the configuration set in DMA_PeripheralDataSize
+                                        or DMA_MemoryDataSize members depending in the transfer direction. */
+
+  uint32_t DMA_PeripheralInc;      /*!< Specifies whether the Peripheral address register should be incremented or not.
+                                        This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+  uint32_t DMA_MemoryInc;          /*!< Specifies whether the memory address register should be incremented or not.
+                                        This parameter can be a value of @ref DMA_memory_incremented_mode */
+
+  uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
+                                        This parameter can be a value of @ref DMA_peripheral_data_size */
+
+  uint32_t DMA_MemoryDataSize;     /*!< Specifies the Memory data width.
+                                        This parameter can be a value of @ref DMA_memory_data_size */
+
+  uint32_t DMA_Mode;               /*!< Specifies the operation mode of the DMAy Streamx.
+                                        This parameter can be a value of @ref DMA_circular_normal_mode
+                                        @note The circular buffer mode cannot be used if the memory-to-memory
+                                              data transfer is configured on the selected Stream */
+
+  uint32_t DMA_Priority;           /*!< Specifies the software priority for the DMAy Streamx.
+                                        This parameter can be a value of @ref DMA_priority_level */
+
+  uint32_t DMA_FIFOMode;          /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream.
+                                        This parameter can be a value of @ref DMA_fifo_direct_mode
+                                        @note The Direct mode (FIFO mode disabled) cannot be used if the 
+                                               memory-to-memory data transfer is configured on the selected Stream */
+
+  uint32_t DMA_FIFOThreshold;      /*!< Specifies the FIFO threshold level.
+                                        This parameter can be a value of @ref DMA_fifo_threshold_level */
+
+  uint32_t DMA_MemoryBurst;        /*!< Specifies the Burst transfer configuration for the memory transfers. 
+                                        It specifies the amount of data to be transferred in a single non interruptable 
+                                        transaction. This parameter can be a value of @ref DMA_memory_burst 
+                                        @note The burst mode is possible only if the address Increment mode is enabled. */
+
+  uint32_t DMA_PeripheralBurst;    /*!< Specifies the Burst transfer configuration for the peripheral transfers. 
+                                        It specifies the amount of data to be transferred in a single non interruptable 
+                                        transaction. This parameter can be a value of @ref DMA_peripheral_burst
+                                        @note The burst mode is possible only if the address Increment mode is enabled. */  
+}DMA_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants
+  * @{
+  */
+
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \
+                                   ((PERIPH) == DMA1_Stream1) || \
+                                   ((PERIPH) == DMA1_Stream2) || \
+                                   ((PERIPH) == DMA1_Stream3) || \
+                                   ((PERIPH) == DMA1_Stream4) || \
+                                   ((PERIPH) == DMA1_Stream5) || \
+                                   ((PERIPH) == DMA1_Stream6) || \
+                                   ((PERIPH) == DMA1_Stream7) || \
+                                   ((PERIPH) == DMA2_Stream0) || \
+                                   ((PERIPH) == DMA2_Stream1) || \
+                                   ((PERIPH) == DMA2_Stream2) || \
+                                   ((PERIPH) == DMA2_Stream3) || \
+                                   ((PERIPH) == DMA2_Stream4) || \
+                                   ((PERIPH) == DMA2_Stream5) || \
+                                   ((PERIPH) == DMA2_Stream6) || \
+                                   ((PERIPH) == DMA2_Stream7))
+
+#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \
+                                           ((CONTROLLER) == DMA2))
+
+/** @defgroup DMA_channel 
+  * @{
+  */ 
+#define DMA_Channel_0                     ((uint32_t)0x00000000)
+#define DMA_Channel_1                     ((uint32_t)0x02000000)
+#define DMA_Channel_2                     ((uint32_t)0x04000000)
+#define DMA_Channel_3                     ((uint32_t)0x06000000)
+#define DMA_Channel_4                     ((uint32_t)0x08000000)
+#define DMA_Channel_5                     ((uint32_t)0x0A000000)
+#define DMA_Channel_6                     ((uint32_t)0x0C000000)
+#define DMA_Channel_7                     ((uint32_t)0x0E000000)
+
+#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \
+                                 ((CHANNEL) == DMA_Channel_1) || \
+                                 ((CHANNEL) == DMA_Channel_2) || \
+                                 ((CHANNEL) == DMA_Channel_3) || \
+                                 ((CHANNEL) == DMA_Channel_4) || \
+                                 ((CHANNEL) == DMA_Channel_5) || \
+                                 ((CHANNEL) == DMA_Channel_6) || \
+                                 ((CHANNEL) == DMA_Channel_7))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_data_transfer_direction 
+  * @{
+  */ 
+#define DMA_DIR_PeripheralToMemory        ((uint32_t)0x00000000)
+#define DMA_DIR_MemoryToPeripheral        ((uint32_t)0x00000040) 
+#define DMA_DIR_MemoryToMemory            ((uint32_t)0x00000080)
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \
+                                     ((DIRECTION) == DMA_DIR_MemoryToPeripheral)  || \
+                                     ((DIRECTION) == DMA_DIR_MemoryToMemory)) 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_data_buffer_size 
+  * @{
+  */ 
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_peripheral_incremented_mode 
+  * @{
+  */ 
+#define DMA_PeripheralInc_Enable          ((uint32_t)0x00000200)
+#define DMA_PeripheralInc_Disable         ((uint32_t)0x00000000)
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
+                                            ((STATE) == DMA_PeripheralInc_Disable))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_memory_incremented_mode 
+  * @{
+  */ 
+#define DMA_MemoryInc_Enable              ((uint32_t)0x00000400)
+#define DMA_MemoryInc_Disable             ((uint32_t)0x00000000)
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
+                                        ((STATE) == DMA_MemoryInc_Disable))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_peripheral_data_size 
+  * @{
+  */ 
+#define DMA_PeripheralDataSize_Byte             ((uint32_t)0x00000000) 
+#define DMA_PeripheralDataSize_HalfWord   ((uint32_t)0x00000800) 
+#define DMA_PeripheralDataSize_Word            ((uint32_t)0x00001000)
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte)  || \
+                                           ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
+                                           ((SIZE) == DMA_PeripheralDataSize_Word))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_memory_data_size 
+  * @{
+  */ 
+#define DMA_MemoryDataSize_Byte                 ((uint32_t)0x00000000) 
+#define DMA_MemoryDataSize_HalfWord       ((uint32_t)0x00002000) 
+#define DMA_MemoryDataSize_Word                ((uint32_t)0x00004000)
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte)  || \
+                                       ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
+                                       ((SIZE) == DMA_MemoryDataSize_Word ))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_circular_normal_mode 
+  * @{
+  */ 
+#define DMA_Mode_Normal                   ((uint32_t)0x00000000) 
+#define DMA_Mode_Circular                 ((uint32_t)0x00000100)
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \
+                           ((MODE) == DMA_Mode_Circular)) 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_priority_level 
+  * @{
+  */ 
+#define DMA_Priority_Low                  ((uint32_t)0x00000000)
+#define DMA_Priority_Medium               ((uint32_t)0x00010000) 
+#define DMA_Priority_High                 ((uint32_t)0x00020000)
+#define DMA_Priority_VeryHigh             ((uint32_t)0x00030000)
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low )   || \
+                                   ((PRIORITY) == DMA_Priority_Medium) || \
+                                   ((PRIORITY) == DMA_Priority_High)   || \
+                                   ((PRIORITY) == DMA_Priority_VeryHigh)) 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_fifo_direct_mode 
+  * @{
+  */ 
+#define DMA_FIFOMode_Disable              ((uint32_t)0x00000000) 
+#define DMA_FIFOMode_Enable               ((uint32_t)0x00000004)
+
+#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \
+                                       ((STATE) == DMA_FIFOMode_Enable)) 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_fifo_threshold_level 
+  * @{
+  */ 
+#define DMA_FIFOThreshold_1QuarterFull    ((uint32_t)0x00000000)
+#define DMA_FIFOThreshold_HalfFull        ((uint32_t)0x00000001) 
+#define DMA_FIFOThreshold_3QuartersFull   ((uint32_t)0x00000002)
+#define DMA_FIFOThreshold_Full            ((uint32_t)0x00000003)
+
+#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \
+                                          ((THRESHOLD) == DMA_FIFOThreshold_HalfFull)      || \
+                                          ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \
+                                          ((THRESHOLD) == DMA_FIFOThreshold_Full)) 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_memory_burst 
+  * @{
+  */ 
+#define DMA_MemoryBurst_Single            ((uint32_t)0x00000000)
+#define DMA_MemoryBurst_INC4              ((uint32_t)0x00800000)  
+#define DMA_MemoryBurst_INC8              ((uint32_t)0x01000000)
+#define DMA_MemoryBurst_INC16             ((uint32_t)0x01800000)
+
+#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \
+                                    ((BURST) == DMA_MemoryBurst_INC4)  || \
+                                    ((BURST) == DMA_MemoryBurst_INC8)  || \
+                                    ((BURST) == DMA_MemoryBurst_INC16))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_peripheral_burst 
+  * @{
+  */ 
+#define DMA_PeripheralBurst_Single        ((uint32_t)0x00000000)
+#define DMA_PeripheralBurst_INC4          ((uint32_t)0x00200000)  
+#define DMA_PeripheralBurst_INC8          ((uint32_t)0x00400000)
+#define DMA_PeripheralBurst_INC16         ((uint32_t)0x00600000)
+
+#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \
+                                        ((BURST) == DMA_PeripheralBurst_INC4)  || \
+                                        ((BURST) == DMA_PeripheralBurst_INC8)  || \
+                                        ((BURST) == DMA_PeripheralBurst_INC16))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_fifo_status_level 
+  * @{
+  */
+#define DMA_FIFOStatus_Less1QuarterFull   ((uint32_t)0x00000000 << 3)
+#define DMA_FIFOStatus_1QuarterFull       ((uint32_t)0x00000001 << 3)
+#define DMA_FIFOStatus_HalfFull           ((uint32_t)0x00000002 << 3) 
+#define DMA_FIFOStatus_3QuartersFull      ((uint32_t)0x00000003 << 3)
+#define DMA_FIFOStatus_Empty              ((uint32_t)0x00000004 << 3)
+#define DMA_FIFOStatus_Full               ((uint32_t)0x00000005 << 3)
+
+#define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \
+                                    ((STATUS) == DMA_FIFOStatus_HalfFull)          || \
+                                    ((STATUS) == DMA_FIFOStatus_1QuarterFull)      || \
+                                    ((STATUS) == DMA_FIFOStatus_3QuartersFull)     || \
+                                    ((STATUS) == DMA_FIFOStatus_Full)              || \
+                                    ((STATUS) == DMA_FIFOStatus_Empty)) 
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_flags_definition 
+  * @{
+  */
+#define DMA_FLAG_FEIF0                    ((uint32_t)0x10800001)
+#define DMA_FLAG_DMEIF0                   ((uint32_t)0x10800004)
+#define DMA_FLAG_TEIF0                    ((uint32_t)0x10000008)
+#define DMA_FLAG_HTIF0                    ((uint32_t)0x10000010)
+#define DMA_FLAG_TCIF0                    ((uint32_t)0x10000020)
+#define DMA_FLAG_FEIF1                    ((uint32_t)0x10000040)
+#define DMA_FLAG_DMEIF1                   ((uint32_t)0x10000100)
+#define DMA_FLAG_TEIF1                    ((uint32_t)0x10000200)
+#define DMA_FLAG_HTIF1                    ((uint32_t)0x10000400)
+#define DMA_FLAG_TCIF1                    ((uint32_t)0x10000800)
+#define DMA_FLAG_FEIF2                    ((uint32_t)0x10010000)
+#define DMA_FLAG_DMEIF2                   ((uint32_t)0x10040000)
+#define DMA_FLAG_TEIF2                    ((uint32_t)0x10080000)
+#define DMA_FLAG_HTIF2                    ((uint32_t)0x10100000)
+#define DMA_FLAG_TCIF2                    ((uint32_t)0x10200000)
+#define DMA_FLAG_FEIF3                    ((uint32_t)0x10400000)
+#define DMA_FLAG_DMEIF3                   ((uint32_t)0x11000000)
+#define DMA_FLAG_TEIF3                    ((uint32_t)0x12000000)
+#define DMA_FLAG_HTIF3                    ((uint32_t)0x14000000)
+#define DMA_FLAG_TCIF3                    ((uint32_t)0x18000000)
+#define DMA_FLAG_FEIF4                    ((uint32_t)0x20000001)
+#define DMA_FLAG_DMEIF4                   ((uint32_t)0x20000004)
+#define DMA_FLAG_TEIF4                    ((uint32_t)0x20000008)
+#define DMA_FLAG_HTIF4                    ((uint32_t)0x20000010)
+#define DMA_FLAG_TCIF4                    ((uint32_t)0x20000020)
+#define DMA_FLAG_FEIF5                    ((uint32_t)0x20000040)
+#define DMA_FLAG_DMEIF5                   ((uint32_t)0x20000100)
+#define DMA_FLAG_TEIF5                    ((uint32_t)0x20000200)
+#define DMA_FLAG_HTIF5                    ((uint32_t)0x20000400)
+#define DMA_FLAG_TCIF5                    ((uint32_t)0x20000800)
+#define DMA_FLAG_FEIF6                    ((uint32_t)0x20010000)
+#define DMA_FLAG_DMEIF6                   ((uint32_t)0x20040000)
+#define DMA_FLAG_TEIF6                    ((uint32_t)0x20080000)
+#define DMA_FLAG_HTIF6                    ((uint32_t)0x20100000)
+#define DMA_FLAG_TCIF6                    ((uint32_t)0x20200000)
+#define DMA_FLAG_FEIF7                    ((uint32_t)0x20400000)
+#define DMA_FLAG_DMEIF7                   ((uint32_t)0x21000000)
+#define DMA_FLAG_TEIF7                    ((uint32_t)0x22000000)
+#define DMA_FLAG_HTIF7                    ((uint32_t)0x24000000)
+#define DMA_FLAG_TCIF7                    ((uint32_t)0x28000000)
+
+#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \
+                                 (((FLAG) & 0xC082F082) == 0x00) && ((FLAG) != 0x00))
+
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0)  || ((FLAG) == DMA_FLAG_HTIF0)  || \
+                               ((FLAG) == DMA_FLAG_TEIF0)  || ((FLAG) == DMA_FLAG_DMEIF0) || \
+                               ((FLAG) == DMA_FLAG_FEIF0)  || ((FLAG) == DMA_FLAG_TCIF1)  || \
+                               ((FLAG) == DMA_FLAG_HTIF1)  || ((FLAG) == DMA_FLAG_TEIF1)  || \
+                               ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1)  || \
+                               ((FLAG) == DMA_FLAG_TCIF2)  || ((FLAG) == DMA_FLAG_HTIF2)  || \
+                               ((FLAG) == DMA_FLAG_TEIF2)  || ((FLAG) == DMA_FLAG_DMEIF2) || \
+                               ((FLAG) == DMA_FLAG_FEIF2)  || ((FLAG) == DMA_FLAG_TCIF3)  || \
+                               ((FLAG) == DMA_FLAG_HTIF3)  || ((FLAG) == DMA_FLAG_TEIF3)  || \
+                               ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3)  || \
+                               ((FLAG) == DMA_FLAG_TCIF4)  || ((FLAG) == DMA_FLAG_HTIF4)  || \
+                               ((FLAG) == DMA_FLAG_TEIF4)  || ((FLAG) == DMA_FLAG_DMEIF4) || \
+                               ((FLAG) == DMA_FLAG_FEIF4)  || ((FLAG) == DMA_FLAG_TCIF5)  || \
+                               ((FLAG) == DMA_FLAG_HTIF5)  || ((FLAG) == DMA_FLAG_TEIF5)  || \
+                               ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5)  || \
+                               ((FLAG) == DMA_FLAG_TCIF6)  || ((FLAG) == DMA_FLAG_HTIF6)  || \
+                               ((FLAG) == DMA_FLAG_TEIF6)  || ((FLAG) == DMA_FLAG_DMEIF6) || \
+                               ((FLAG) == DMA_FLAG_FEIF6)  || ((FLAG) == DMA_FLAG_TCIF7)  || \
+                               ((FLAG) == DMA_FLAG_HTIF7)  || ((FLAG) == DMA_FLAG_TEIF7)  || \
+                               ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_interrupt_enable_definitions 
+  * @{
+  */ 
+#define DMA_IT_TC                         ((uint32_t)0x00000010)
+#define DMA_IT_HT                         ((uint32_t)0x00000008)
+#define DMA_IT_TE                         ((uint32_t)0x00000004)
+#define DMA_IT_DME                        ((uint32_t)0x00000002)
+#define DMA_IT_FE                         ((uint32_t)0x00000080)
+
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_interrupts_definitions 
+  * @{
+  */ 
+#define DMA_IT_FEIF0                      ((uint32_t)0x90000001)
+#define DMA_IT_DMEIF0                     ((uint32_t)0x10001004)
+#define DMA_IT_TEIF0                      ((uint32_t)0x10002008)
+#define DMA_IT_HTIF0                      ((uint32_t)0x10004010)
+#define DMA_IT_TCIF0                      ((uint32_t)0x10008020)
+#define DMA_IT_FEIF1                      ((uint32_t)0x90000040)
+#define DMA_IT_DMEIF1                     ((uint32_t)0x10001100)
+#define DMA_IT_TEIF1                      ((uint32_t)0x10002200)
+#define DMA_IT_HTIF1                      ((uint32_t)0x10004400)
+#define DMA_IT_TCIF1                      ((uint32_t)0x10008800)
+#define DMA_IT_FEIF2                      ((uint32_t)0x90010000)
+#define DMA_IT_DMEIF2                     ((uint32_t)0x10041000)
+#define DMA_IT_TEIF2                      ((uint32_t)0x10082000)
+#define DMA_IT_HTIF2                      ((uint32_t)0x10104000)
+#define DMA_IT_TCIF2                      ((uint32_t)0x10208000)
+#define DMA_IT_FEIF3                      ((uint32_t)0x90400000)
+#define DMA_IT_DMEIF3                     ((uint32_t)0x11001000)
+#define DMA_IT_TEIF3                      ((uint32_t)0x12002000)
+#define DMA_IT_HTIF3                      ((uint32_t)0x14004000)
+#define DMA_IT_TCIF3                      ((uint32_t)0x18008000)
+#define DMA_IT_FEIF4                      ((uint32_t)0xA0000001)
+#define DMA_IT_DMEIF4                     ((uint32_t)0x20001004)
+#define DMA_IT_TEIF4                      ((uint32_t)0x20002008)
+#define DMA_IT_HTIF4                      ((uint32_t)0x20004010)
+#define DMA_IT_TCIF4                      ((uint32_t)0x20008020)
+#define DMA_IT_FEIF5                      ((uint32_t)0xA0000040)
+#define DMA_IT_DMEIF5                     ((uint32_t)0x20001100)
+#define DMA_IT_TEIF5                      ((uint32_t)0x20002200)
+#define DMA_IT_HTIF5                      ((uint32_t)0x20004400)
+#define DMA_IT_TCIF5                      ((uint32_t)0x20008800)
+#define DMA_IT_FEIF6                      ((uint32_t)0xA0010000)
+#define DMA_IT_DMEIF6                     ((uint32_t)0x20041000)
+#define DMA_IT_TEIF6                      ((uint32_t)0x20082000)
+#define DMA_IT_HTIF6                      ((uint32_t)0x20104000)
+#define DMA_IT_TCIF6                      ((uint32_t)0x20208000)
+#define DMA_IT_FEIF7                      ((uint32_t)0xA0400000)
+#define DMA_IT_DMEIF7                     ((uint32_t)0x21001000)
+#define DMA_IT_TEIF7                      ((uint32_t)0x22002000)
+#define DMA_IT_HTIF7                      ((uint32_t)0x24004000)
+#define DMA_IT_TCIF7                      ((uint32_t)0x28008000)
+
+#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \
+                             (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \
+                             (((IT) & 0x40820082) == 0x00))
+
+#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0)  || \
+                           ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \
+                           ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1)  || \
+                           ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1)  || \
+                           ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1)  || \
+                           ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2)  || \
+                           ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \
+                           ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3)  || \
+                           ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3)  || \
+                           ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3)  || \
+                           ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4)  || \
+                           ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \
+                           ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5)  || \
+                           ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5)  || \
+                           ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5)  || \
+                           ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6)  || \
+                           ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \
+                           ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7)  || \
+                           ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7)  || \
+                           ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_peripheral_increment_offset 
+  * @{
+  */ 
+#define DMA_PINCOS_Psize                  ((uint32_t)0x00000000)
+#define DMA_PINCOS_WordAligned            ((uint32_t)0x00008000)
+
+#define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \
+                                  ((SIZE) == DMA_PINCOS_WordAligned))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_flow_controller_definitions 
+  * @{
+  */ 
+#define DMA_FlowCtrl_Memory               ((uint32_t)0x00000000)
+#define DMA_FlowCtrl_Peripheral           ((uint32_t)0x00000020)
+
+#define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \
+                                ((CTRL) == DMA_FlowCtrl_Peripheral))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_memory_targets_definitions 
+  * @{
+  */ 
+#define DMA_Memory_0                      ((uint32_t)0x00000000)
+#define DMA_Memory_1                      ((uint32_t)0x00080000)
+
+#define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1))
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/*  Function used to set the DMA configuration to the default reset state *****/ 
+void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx);
+
+/* Initialization and Configuration functions *********************************/
+void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct);
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
+void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
+
+/* Optional Configuration functions *******************************************/
+void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos);
+void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl);
+
+/* Data Counter functions *****************************************************/
+void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);
+uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);
+
+/* Double Buffer mode functions ***********************************************/
+void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
+                                uint32_t DMA_CurrentMemory);
+void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
+void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
+                            uint32_t DMA_MemoryTarget);
+uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);
+
+/* Interrupts and flags management functions **********************************/
+FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx);
+uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx);
+FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
+void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
+void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
+ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
+void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__HARDWARE_DMA_H__ */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/hardware_exti.h

@@ -0,0 +1,196 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_exti.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    30-September-2011
+  * @brief   This file contains all the functions prototypes for the EXTI firmware
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/**
+* @file: hardware_exti.h
+* @brief: define hardware exti function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/*************************************************
+File name: hardware_exti.h
+Description: define hardware exti function
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_exti.h for XiZi
+*************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HARDWARE_EXTI_H__
+#define __HARDWARE_EXTI_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stm32f4xx.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup EXTI
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  EXTI mode enumeration  
+  */
+
+typedef enum
+{
+  EXTI_Mode_Interrupt = 0x00,
+  EXTI_Mode_Event = 0x04
+}EXTIMode_TypeDef;
+
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
+/** 
+  * @brief  EXTI Trigger enumeration  
+  */
+
+typedef enum
+{
+  EXTI_Trigger_Rising = 0x08,
+  EXTI_Trigger_Falling = 0x0C,  
+  EXTI_Trigger_Rising_Falling = 0x10
+}EXTITrigger_TypeDef;
+
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
+                                  ((TRIGGER) == EXTI_Trigger_Falling) || \
+                                  ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+/** 
+  * @brief  EXTI Init Structure definition  
+  */
+
+typedef struct
+{
+  uint32_t EXTI_Line;               /*!< Specifies the EXTI lines to be enabled or disabled.
+                                         This parameter can be any combination value of @ref EXTI_Lines */
+   
+  EXTIMode_TypeDef EXTI_Mode;       /*!< Specifies the mode for the EXTI lines.
+                                         This parameter can be a value of @ref EXTIMode_TypeDef */
+
+  EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+                                         This parameter can be a value of @ref EXTITrigger_TypeDef */
+
+  FunctionalState EXTI_LineCmd;     /*!< Specifies the new state of the selected EXTI lines.
+                                         This parameter can be set either to ENABLE or DISABLE */ 
+}EXTI_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Constants
+  * @{
+  */
+
+/** @defgroup EXTI_Lines 
+  * @{
+  */
+
+#define EXTI_Line0       ((uint32_t)0x00001)     /*!< External interrupt line 0 */
+#define EXTI_Line1       ((uint32_t)0x00002)     /*!< External interrupt line 1 */
+#define EXTI_Line2       ((uint32_t)0x00004)     /*!< External interrupt line 2 */
+#define EXTI_Line3       ((uint32_t)0x00008)     /*!< External interrupt line 3 */
+#define EXTI_Line4       ((uint32_t)0x00010)     /*!< External interrupt line 4 */
+#define EXTI_Line5       ((uint32_t)0x00020)     /*!< External interrupt line 5 */
+#define EXTI_Line6       ((uint32_t)0x00040)     /*!< External interrupt line 6 */
+#define EXTI_Line7       ((uint32_t)0x00080)     /*!< External interrupt line 7 */
+#define EXTI_Line8       ((uint32_t)0x00100)     /*!< External interrupt line 8 */
+#define EXTI_Line9       ((uint32_t)0x00200)     /*!< External interrupt line 9 */
+#define EXTI_Line10      ((uint32_t)0x00400)     /*!< External interrupt line 10 */
+#define EXTI_Line11      ((uint32_t)0x00800)     /*!< External interrupt line 11 */
+#define EXTI_Line12      ((uint32_t)0x01000)     /*!< External interrupt line 12 */
+#define EXTI_Line13      ((uint32_t)0x02000)     /*!< External interrupt line 13 */
+#define EXTI_Line14      ((uint32_t)0x04000)     /*!< External interrupt line 14 */
+#define EXTI_Line15      ((uint32_t)0x08000)     /*!< External interrupt line 15 */
+#define EXTI_Line16      ((uint32_t)0x10000)     /*!< External interrupt line 16 Connected to the PVD Output */
+#define EXTI_Line17      ((uint32_t)0x20000)     /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define EXTI_Line18      ((uint32_t)0x40000)     /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */                                    
+#define EXTI_Line19      ((uint32_t)0x80000)     /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
+#define EXTI_Line20      ((uint32_t)0x00100000)  /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event  */
+#define EXTI_Line21      ((uint32_t)0x00200000)  /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */                                               
+#define EXTI_Line22      ((uint32_t)0x00400000)  /*!< External interrupt line 22 Connected to the RTC Wakeup event */                                               
+                                          
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))
+
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
+                                ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
+                                ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
+                                ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
+                                ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
+                                ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
+                                ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
+                                ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
+                                ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
+                                ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
+                                ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\
+                                ((LINE) == EXTI_Line22))
+                    
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/*  Function used to set the EXTI configuration to the default reset state *****/
+void EXTI_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+
+/* Interrupts and flags management functions **********************************/
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
+void EXTI_ClearFlag(uint32_t EXTI_Line);
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HARDWARE_EXTI_H__ */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/hardware_fsmc.h

@@ -0,0 +1,694 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_fsmc.h
+  * @author  MCD Application Team
+  * @version V1.4.0
+  * @date    04-August-2014
+  * @brief   This file contains all the functions prototypes for the FSMC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/**
+* @file: hardware_fsmc.h
+* @brief: define hardware fsmc function
+* @version: 2.0
+* @author:  AIIT XUOS Lab
+* @date:    2022/1/12
+*/
+
+/*************************************************
+File name: hardware_fsmc.h
+Description: define hardware fsmc function
+Others: 
+History: 
+1. Date: 2022-1-12
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_fsmc.h for XiZi
+*************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HARDWARE_FSMC_H
+#define __HARDWARE_FSMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stm32f4xx.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup FSMC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  Timing parameters For NOR/SRAM Banks  
+  */
+typedef struct
+{
+  uint32_t FSMC_AddressSetupTime;       /*!< Defines the number of HCLK cycles to configure
+                                             the duration of the address setup time. 
+                                             This parameter can be a value between 0 and 0xF.
+                                             @note This parameter is not used with synchronous NOR Flash memories. */
+
+  uint32_t FSMC_AddressHoldTime;        /*!< Defines the number of HCLK cycles to configure
+                                             the duration of the address hold time.
+                                             This parameter can be a value between 0 and 0xF. 
+                                             @note This parameter is not used with synchronous NOR Flash memories.*/
+
+  uint32_t FSMC_DataSetupTime;          /*!< Defines the number of HCLK cycles to configure
+                                             the duration of the data setup time.
+                                             This parameter can be a value between 0 and 0xFF.
+                                             @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
+
+  uint32_t FSMC_BusTurnAroundDuration;  /*!< Defines the number of HCLK cycles to configure
+                                             the duration of the bus turnaround.
+                                             This parameter can be a value between 0 and 0xF.
+                                             @note This parameter is only used for multiplexed NOR Flash memories. */
+
+  uint32_t FSMC_CLKDivision;            /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+                                             This parameter can be a value between 1 and 0xF.
+                                             @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
+
+  uint32_t FSMC_DataLatency;            /*!< Defines the number of memory clock cycles to issue
+                                             to the memory before getting the first data.
+                                             The parameter value depends on the memory type as shown below:
+                                              - It must be set to 0 in case of a CRAM
+                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses
+                                              - It may assume a value between 0 and 0xF in NOR Flash memories
+                                                with synchronous burst mode enable */
+
+  uint32_t FSMC_AccessMode;             /*!< Specifies the asynchronous access mode. 
+                                             This parameter can be a value of @ref FSMC_Access_Mode */
+}FSMC_NORSRAMTimingInitTypeDef;
+
+/** 
+  * @brief  FSMC NOR/SRAM Init structure definition
+  */
+typedef struct
+{
+  uint32_t FSMC_Bank;                /*!< Specifies the NOR/SRAM memory bank that will be used.
+                                          This parameter can be a value of @ref FSMC_NORSRAM_Bank */
+
+  uint32_t FSMC_DataAddressMux;      /*!< Specifies whether the address and data values are
+                                          multiplexed on the data bus or not. 
+                                          This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
+
+  uint32_t FSMC_MemoryType;          /*!< Specifies the type of external memory attached to
+                                          the corresponding memory bank.
+                                          This parameter can be a value of @ref FSMC_Memory_Type */
+
+  uint32_t FSMC_MemoryDataWidth;     /*!< Specifies the external memory device width.
+                                          This parameter can be a value of @ref FSMC_Data_Width */
+
+  uint32_t FSMC_BurstAccessMode;     /*!< Enables or disables the burst access mode for Flash memory,
+                                          valid only with synchronous burst Flash memories.
+                                          This parameter can be a value of @ref FSMC_Burst_Access_Mode */
+
+  uint32_t FSMC_AsynchronousWait;     /*!< Enables or disables wait signal during asynchronous transfers,
+                                          valid only with asynchronous Flash memories.
+                                          This parameter can be a value of @ref FSMC_AsynchronousWait */                                          
+
+  uint32_t FSMC_WaitSignalPolarity;  /*!< Specifies the wait signal polarity, valid only when accessing
+                                          the Flash memory in burst mode.
+                                          This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
+
+  uint32_t FSMC_WrapMode;            /*!< Enables or disables the Wrapped burst access mode for Flash
+                                          memory, valid only when accessing Flash memories in burst mode.
+                                          This parameter can be a value of @ref FSMC_Wrap_Mode */
+
+  uint32_t FSMC_WaitSignalActive;    /*!< Specifies if the wait signal is asserted by the memory one
+                                          clock cycle before the wait state or during the wait state,
+                                          valid only when accessing memories in burst mode. 
+                                          This parameter can be a value of @ref FSMC_Wait_Timing */
+
+  uint32_t FSMC_WriteOperation;      /*!< Enables or disables the write operation in the selected bank by the FSMC. 
+                                          This parameter can be a value of @ref FSMC_Write_Operation */
+
+  uint32_t FSMC_WaitSignal;          /*!< Enables or disables the wait state insertion via wait
+                                          signal, valid for Flash memory access in burst mode. 
+                                          This parameter can be a value of @ref FSMC_Wait_Signal */
+
+  uint32_t FSMC_ExtendedMode;        /*!< Enables or disables the extended mode.
+                                          This parameter can be a value of @ref FSMC_Extended_Mode */
+
+  uint32_t FSMC_WriteBurst;          /*!< Enables or disables the write burst operation.
+                                          This parameter can be a value of @ref FSMC_Write_Burst */ 
+
+  FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the  Extended Mode is not used*/  
+
+  FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;     /*!< Timing Parameters for write access if the  Extended Mode is used*/      
+}FSMC_NORSRAMInitTypeDef;
+
+/** 
+  * @brief  Timing parameters For FSMC NAND and PCCARD Banks
+  */
+typedef struct
+{
+  uint32_t FSMC_SetupTime;      /*!< Defines the number of HCLK cycles to setup address before
+                                     the command assertion for NAND Flash read or write access
+                                     to common/Attribute or I/O memory space (depending on
+                                     the memory space timing to be configured).
+                                     This parameter can be a value between 0 and 0xFF.*/
+
+  uint32_t FSMC_WaitSetupTime;  /*!< Defines the minimum number of HCLK cycles to assert the
+                                     command for NAND Flash read or write access to
+                                     common/Attribute or I/O memory space (depending on the
+                                     memory space timing to be configured). 
+                                     This parameter can be a number between 0x00 and 0xFF */
+
+  uint32_t FSMC_HoldSetupTime;  /*!< Defines the number of HCLK clock cycles to hold address
+                                     (and data for write access) after the command de-assertion
+                                     for NAND Flash read or write access to common/Attribute
+                                     or I/O memory space (depending on the memory space timing
+                                     to be configured).
+                                     This parameter can be a number between 0x00 and 0xFF */
+
+  uint32_t FSMC_HiZSetupTime;   /*!< Defines the number of HCLK clock cycles during which the
+                                     data bus is kept in HiZ after the start of a NAND Flash
+                                     write access to common/Attribute or I/O memory space (depending
+                                     on the memory space timing to be configured).
+                                     This parameter can be a number between 0x00 and 0xFF */
+}FSMC_NAND_PCCARDTimingInitTypeDef;
+
+/** 
+  * @brief  FSMC NAND Init structure definition
+  */
+typedef struct
+{
+  uint32_t FSMC_Bank;              /*!< Specifies the NAND memory bank that will be used.
+                                      This parameter can be a value of @ref FSMC_NAND_Bank */
+
+  uint32_t FSMC_Waitfeature;      /*!< Enables or disables the Wait feature for the NAND Memory Bank.
+                                       This parameter can be any value of @ref FSMC_Wait_feature */
+
+  uint32_t FSMC_MemoryDataWidth;  /*!< Specifies the external memory device width.
+                                       This parameter can be any value of @ref FSMC_Data_Width */
+
+  uint32_t FSMC_ECC;              /*!< Enables or disables the ECC computation.
+                                       This parameter can be any value of @ref FSMC_ECC */
+
+  uint32_t FSMC_ECCPageSize;      /*!< Defines the page size for the extended ECC.
+                                       This parameter can be any value of @ref FSMC_ECC_Page_Size */
+
+  uint32_t FSMC_TCLRSetupTime;    /*!< Defines the number of HCLK cycles to configure the
+                                       delay between CLE low and RE low.
+                                       This parameter can be a value between 0 and 0xFF. */
+
+  uint32_t FSMC_TARSetupTime;     /*!< Defines the number of HCLK cycles to configure the
+                                       delay between ALE low and RE low.
+                                       This parameter can be a number between 0x0 and 0xFF */ 
+
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct;   /*!< FSMC Common Space Timing */ 
+
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
+}FSMC_NANDInitTypeDef;
+
+/** 
+  * @brief  FSMC PCCARD Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t FSMC_Waitfeature;    /*!< Enables or disables the Wait feature for the Memory Bank.
+                                    This parameter can be any value of @ref FSMC_Wait_feature */
+
+  uint32_t FSMC_TCLRSetupTime;  /*!< Defines the number of HCLK cycles to configure the
+                                     delay between CLE low and RE low.
+                                     This parameter can be a value between 0 and 0xFF. */
+
+  uint32_t FSMC_TARSetupTime;   /*!< Defines the number of HCLK cycles to configure the
+                                     delay between ALE low and RE low.
+                                     This parameter can be a number between 0x0 and 0xFF */ 
+
+  
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
+
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct;  /*!< FSMC Attribute Space Timing */ 
+  
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */  
+}FSMC_PCCARDInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FSMC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup FSMC_NORSRAM_Bank 
+  * @{
+  */
+#define FSMC_Bank1_NORSRAM1                      ((uint32_t)0x00000000)
+#define FSMC_Bank1_NORSRAM2                      ((uint32_t)0x00000002)
+#define FSMC_Bank1_NORSRAM3                      ((uint32_t)0x00000004)
+#define FSMC_Bank1_NORSRAM4                      ((uint32_t)0x00000006)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_NAND_Bank 
+  * @{
+  */  
+#define FSMC_Bank2_NAND                          ((uint32_t)0x00000010)
+#define FSMC_Bank3_NAND                          ((uint32_t)0x00000100)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_PCCARD_Bank 
+  * @{
+  */    
+#define FSMC_Bank4_PCCARD                        ((uint32_t)0x00001000)
+/**
+  * @}
+  */
+
+#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
+                                    ((BANK) == FSMC_Bank1_NORSRAM2) || \
+                                    ((BANK) == FSMC_Bank1_NORSRAM3) || \
+                                    ((BANK) == FSMC_Bank1_NORSRAM4))
+
+#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+                                 ((BANK) == FSMC_Bank3_NAND))
+
+#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+                                    ((BANK) == FSMC_Bank3_NAND) || \
+                                    ((BANK) == FSMC_Bank4_PCCARD))
+
+#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+                               ((BANK) == FSMC_Bank3_NAND) || \
+                               ((BANK) == FSMC_Bank4_PCCARD))
+
+/** @defgroup FSMC_NOR_SRAM_Controller 
+  * @{
+  */
+
+/** @defgroup FSMC_Data_Address_Bus_Multiplexing 
+  * @{
+  */
+
+#define FSMC_DataAddressMux_Disable                ((uint32_t)0x00000000)
+#define FSMC_DataAddressMux_Enable                 ((uint32_t)0x00000002)
+#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
+                          ((MUX) == FSMC_DataAddressMux_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Memory_Type 
+  * @{
+  */
+
+#define FSMC_MemoryType_SRAM                     ((uint32_t)0x00000000)
+#define FSMC_MemoryType_PSRAM                    ((uint32_t)0x00000004)
+#define FSMC_MemoryType_NOR                      ((uint32_t)0x00000008)
+#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
+                                ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
+                                ((MEMORY) == FSMC_MemoryType_NOR))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Data_Width 
+  * @{
+  */
+
+#define FSMC_MemoryDataWidth_8b                  ((uint32_t)0x00000000)
+#define FSMC_MemoryDataWidth_16b                 ((uint32_t)0x00000010)
+#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
+                                     ((WIDTH) == FSMC_MemoryDataWidth_16b))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Burst_Access_Mode 
+  * @{
+  */
+
+#define FSMC_BurstAccessMode_Disable             ((uint32_t)0x00000000) 
+#define FSMC_BurstAccessMode_Enable              ((uint32_t)0x00000100)
+#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
+                                  ((STATE) == FSMC_BurstAccessMode_Enable))
+/**
+  * @}
+  */
+    
+/** @defgroup FSMC_AsynchronousWait 
+  * @{
+  */
+#define FSMC_AsynchronousWait_Disable            ((uint32_t)0x00000000)
+#define FSMC_AsynchronousWait_Enable             ((uint32_t)0x00008000)
+#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
+                                 ((STATE) == FSMC_AsynchronousWait_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_Signal_Polarity 
+  * @{
+  */
+#define FSMC_WaitSignalPolarity_Low              ((uint32_t)0x00000000)
+#define FSMC_WaitSignalPolarity_High             ((uint32_t)0x00000200)
+#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
+                                         ((POLARITY) == FSMC_WaitSignalPolarity_High))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wrap_Mode 
+  * @{
+  */
+#define FSMC_WrapMode_Disable                    ((uint32_t)0x00000000)
+#define FSMC_WrapMode_Enable                     ((uint32_t)0x00000400) 
+#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
+                                 ((MODE) == FSMC_WrapMode_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_Timing 
+  * @{
+  */
+#define FSMC_WaitSignalActive_BeforeWaitState    ((uint32_t)0x00000000)
+#define FSMC_WaitSignalActive_DuringWaitState    ((uint32_t)0x00000800) 
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
+                                            ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Write_Operation 
+  * @{
+  */
+#define FSMC_WriteOperation_Disable                     ((uint32_t)0x00000000)
+#define FSMC_WriteOperation_Enable                      ((uint32_t)0x00001000)
+#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
+                                            ((OPERATION) == FSMC_WriteOperation_Enable))                         
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_Signal 
+  * @{
+  */
+#define FSMC_WaitSignal_Disable                  ((uint32_t)0x00000000)
+#define FSMC_WaitSignal_Enable                   ((uint32_t)0x00002000) 
+#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
+                                      ((SIGNAL) == FSMC_WaitSignal_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Extended_Mode 
+  * @{
+  */
+#define FSMC_ExtendedMode_Disable                ((uint32_t)0x00000000)
+#define FSMC_ExtendedMode_Enable                 ((uint32_t)0x00004000)
+
+#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
+                                     ((MODE) == FSMC_ExtendedMode_Enable)) 
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Write_Burst 
+  * @{
+  */
+
+#define FSMC_WriteBurst_Disable                  ((uint32_t)0x00000000)
+#define FSMC_WriteBurst_Enable                   ((uint32_t)0x00080000) 
+#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
+                                    ((BURST) == FSMC_WriteBurst_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Address_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Address_Hold_Time 
+  * @{
+  */
+#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Data_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Bus_Turn_around_Duration 
+  * @{
+  */
+#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_CLK_Division 
+  * @{
+  */
+#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Data_Latency 
+  * @{
+  */
+#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Access_Mode 
+  * @{
+  */
+#define FSMC_AccessMode_A                        ((uint32_t)0x00000000)
+#define FSMC_AccessMode_B                        ((uint32_t)0x10000000) 
+#define FSMC_AccessMode_C                        ((uint32_t)0x20000000)
+#define FSMC_AccessMode_D                        ((uint32_t)0x30000000)
+#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
+                                   ((MODE) == FSMC_AccessMode_B) || \
+                                   ((MODE) == FSMC_AccessMode_C) || \
+                                   ((MODE) == FSMC_AccessMode_D))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/** @defgroup FSMC_NAND_PCCARD_Controller 
+  * @{
+  */
+
+/** @defgroup FSMC_Wait_feature 
+  * @{
+  */
+#define FSMC_Waitfeature_Disable                 ((uint32_t)0x00000000)
+#define FSMC_Waitfeature_Enable                  ((uint32_t)0x00000002)
+#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
+                                       ((FEATURE) == FSMC_Waitfeature_Enable))
+/**
+  * @}
+  */
+
+
+/** @defgroup FSMC_ECC 
+  * @{
+  */
+#define FSMC_ECC_Disable                         ((uint32_t)0x00000000)
+#define FSMC_ECC_Enable                          ((uint32_t)0x00000040)
+#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
+                                  ((STATE) == FSMC_ECC_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_ECC_Page_Size 
+  * @{
+  */
+#define FSMC_ECCPageSize_256Bytes                ((uint32_t)0x00000000)
+#define FSMC_ECCPageSize_512Bytes                ((uint32_t)0x00020000)
+#define FSMC_ECCPageSize_1024Bytes               ((uint32_t)0x00040000)
+#define FSMC_ECCPageSize_2048Bytes               ((uint32_t)0x00060000)
+#define FSMC_ECCPageSize_4096Bytes               ((uint32_t)0x00080000)
+#define FSMC_ECCPageSize_8192Bytes               ((uint32_t)0x000A0000)
+#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
+                                    ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
+                                    ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
+                                    ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
+                                    ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
+                                    ((SIZE) == FSMC_ECCPageSize_8192Bytes))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_TCLR_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_TAR_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Hold_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_HiZ_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Interrupt_sources 
+  * @{
+  */
+#define FSMC_IT_RisingEdge                       ((uint32_t)0x00000008)
+#define FSMC_IT_Level                            ((uint32_t)0x00000010)
+#define FSMC_IT_FallingEdge                      ((uint32_t)0x00000020)
+#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
+#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
+                            ((IT) == FSMC_IT_Level) || \
+                            ((IT) == FSMC_IT_FallingEdge)) 
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Flags 
+  * @{
+  */
+#define FSMC_FLAG_RisingEdge                     ((uint32_t)0x00000001)
+#define FSMC_FLAG_Level                          ((uint32_t)0x00000002)
+#define FSMC_FLAG_FallingEdge                    ((uint32_t)0x00000004)
+#define FSMC_FLAG_FEMPT                          ((uint32_t)0x00000040)
+#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
+                                ((FLAG) == FSMC_FLAG_Level) || \
+                                ((FLAG) == FSMC_FLAG_FallingEdge) || \
+                                ((FLAG) == FSMC_FLAG_FEMPT))
+
+#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/* NOR/SRAM Controller functions **********************************************/
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+
+/* NAND Controller functions **************************************************/
+void FSMC_NANDDeInit(uint32_t FSMC_Bank);
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
+
+/* PCCARD Controller functions ************************************************/
+void FSMC_PCCARDDeInit(void);
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
+void FSMC_PCCARDCmd(FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_FSMC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/hardware_gpio.h

@@ -0,0 +1,425 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_gpio.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    30-September-2011
+  * @brief   This file contains all the functions prototypes for the GPIO firmware
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/**
+* @file: hardware_gpio.h
+* @brief: define hardware gpio function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/*************************************************
+File name: hardware_gpio.h
+Description: define hardware gpio function
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_gpio.h for XiZi
+*************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HARDWARE_GPIO_H__
+#define __HARDWARE_GPIO_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stm32f4xx.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+                                    ((PERIPH) == GPIOB) || \
+                                    ((PERIPH) == GPIOC) || \
+                                    ((PERIPH) == GPIOD) || \
+                                    ((PERIPH) == GPIOE) || \
+                                    ((PERIPH) == GPIOF) || \
+                                    ((PERIPH) == GPIOG) || \
+                                    ((PERIPH) == GPIOH) || \
+                                    ((PERIPH) == GPIOI))
+                                                                
+/** 
+  * @brief  GPIO Configuration Mode enumeration 
+  */   
+typedef enum
+{ 
+  GPIO_Mode_IN   = 0x00, /*!< GPIO Input Mode */
+  GPIO_Mode_OUT  = 0x01, /*!< GPIO Output Mode */
+  GPIO_Mode_AF   = 0x02, /*!< GPIO Alternate function Mode */
+  GPIO_Mode_AN   = 0x03  /*!< GPIO Analog Mode */
+}GPIOMode_TypeDef;
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)  || ((MODE) == GPIO_Mode_OUT) || \
+                            ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
+
+/** 
+  * @brief  GPIO Output type enumeration 
+  */  
+typedef enum
+{ 
+  GPIO_OType_PP = 0x00,
+  GPIO_OType_OD = 0x01
+}GPIOOType_TypeDef;
+#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
+
+
+/** 
+  * @brief  GPIO Output Maximum frequency enumeration 
+  */  
+typedef enum
+{ 
+  GPIO_Speed_2MHz   = 0x00, /*!< Low speed */
+  GPIO_Speed_25MHz  = 0x01, /*!< Medium speed */
+  GPIO_Speed_50MHz  = 0x02, /*!< Fast speed */
+  GPIO_Speed_100MHz = 0x03  /*!< High speed on 30 pF (80 MHz Output max speed on 15 pF) */
+}GPIOSpeed_TypeDef;
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_2MHz) || ((SPEED) == GPIO_Speed_25MHz) || \
+                              ((SPEED) == GPIO_Speed_50MHz)||  ((SPEED) == GPIO_Speed_100MHz)) 
+
+/** 
+  * @brief  GPIO Configuration PullUp PullDown enumeration 
+  */ 
+typedef enum
+{ 
+  GPIO_PuPd_NOPULL = 0x00,
+  GPIO_PuPd_UP     = 0x01,
+  GPIO_PuPd_DOWN   = 0x02
+}GPIOPuPd_TypeDef;
+#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
+                            ((PUPD) == GPIO_PuPd_DOWN))
+
+/** 
+  * @brief  GPIO Bit SET and Bit RESET enumeration 
+  */ 
+typedef enum
+{ 
+  Bit_RESET = 0,
+  Bit_SET
+}BitAction;
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
+
+
+/** 
+  * @brief   GPIO Init structure definition  
+  */ 
+typedef struct
+{
+  uint32_t GPIO_Pin;              /*!< Specifies the GPIO pins to be configured.
+                                       This parameter can be any value of @ref GPIO_pins_define */
+
+  GPIOMode_TypeDef GPIO_Mode;     /*!< Specifies the operating mode for the selected pins.
+                                       This parameter can be a value of @ref GPIOMode_TypeDef */
+
+  GPIOSpeed_TypeDef GPIO_Speed;   /*!< Specifies the speed for the selected pins.
+                                       This parameter can be a value of @ref GPIOSpeed_TypeDef */
+
+  GPIOOType_TypeDef GPIO_OType;   /*!< Specifies the operating output type for the selected pins.
+                                       This parameter can be a value of @ref GPIOOType_TypeDef */
+
+  GPIOPuPd_TypeDef GPIO_PuPd;     /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+                                       This parameter can be a value of @ref GPIOPuPd_TypeDef */
+}GPIO_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants
+  * @{
+  */ 
+
+/** @defgroup GPIO_pins_define 
+  * @{
+  */ 
+#define GPIO_Pin_0                 ((uint16_t)0x0001)  /* Pin 0 selected */
+#define GPIO_Pin_1                 ((uint16_t)0x0002)  /* Pin 1 selected */
+#define GPIO_Pin_2                 ((uint16_t)0x0004)  /* Pin 2 selected */
+#define GPIO_Pin_3                 ((uint16_t)0x0008)  /* Pin 3 selected */
+#define GPIO_Pin_4                 ((uint16_t)0x0010)  /* Pin 4 selected */
+#define GPIO_Pin_5                 ((uint16_t)0x0020)  /* Pin 5 selected */
+#define GPIO_Pin_6                 ((uint16_t)0x0040)  /* Pin 6 selected */
+#define GPIO_Pin_7                 ((uint16_t)0x0080)  /* Pin 7 selected */
+#define GPIO_Pin_8                 ((uint16_t)0x0100)  /* Pin 8 selected */
+#define GPIO_Pin_9                 ((uint16_t)0x0200)  /* Pin 9 selected */
+#define GPIO_Pin_10                ((uint16_t)0x0400)  /* Pin 10 selected */
+#define GPIO_Pin_11                ((uint16_t)0x0800)  /* Pin 11 selected */
+#define GPIO_Pin_12                ((uint16_t)0x1000)  /* Pin 12 selected */
+#define GPIO_Pin_13                ((uint16_t)0x2000)  /* Pin 13 selected */
+#define GPIO_Pin_14                ((uint16_t)0x4000)  /* Pin 14 selected */
+#define GPIO_Pin_15                ((uint16_t)0x8000)  /* Pin 15 selected */
+#define GPIO_Pin_All               ((uint16_t)0xFFFF)  /* All pins selected */
+
+#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
+                              ((PIN) == GPIO_Pin_1) || \
+                              ((PIN) == GPIO_Pin_2) || \
+                              ((PIN) == GPIO_Pin_3) || \
+                              ((PIN) == GPIO_Pin_4) || \
+                              ((PIN) == GPIO_Pin_5) || \
+                              ((PIN) == GPIO_Pin_6) || \
+                              ((PIN) == GPIO_Pin_7) || \
+                              ((PIN) == GPIO_Pin_8) || \
+                              ((PIN) == GPIO_Pin_9) || \
+                              ((PIN) == GPIO_Pin_10) || \
+                              ((PIN) == GPIO_Pin_11) || \
+                              ((PIN) == GPIO_Pin_12) || \
+                              ((PIN) == GPIO_Pin_13) || \
+                              ((PIN) == GPIO_Pin_14) || \
+                              ((PIN) == GPIO_Pin_15))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup GPIO_Pin_sources 
+  * @{
+  */ 
+#define GPIO_PinSource0            ((uint8_t)0x00)
+#define GPIO_PinSource1            ((uint8_t)0x01)
+#define GPIO_PinSource2            ((uint8_t)0x02)
+#define GPIO_PinSource3            ((uint8_t)0x03)
+#define GPIO_PinSource4            ((uint8_t)0x04)
+#define GPIO_PinSource5            ((uint8_t)0x05)
+#define GPIO_PinSource6            ((uint8_t)0x06)
+#define GPIO_PinSource7            ((uint8_t)0x07)
+#define GPIO_PinSource8            ((uint8_t)0x08)
+#define GPIO_PinSource9            ((uint8_t)0x09)
+#define GPIO_PinSource10           ((uint8_t)0x0A)
+#define GPIO_PinSource11           ((uint8_t)0x0B)
+#define GPIO_PinSource12           ((uint8_t)0x0C)
+#define GPIO_PinSource13           ((uint8_t)0x0D)
+#define GPIO_PinSource14           ((uint8_t)0x0E)
+#define GPIO_PinSource15           ((uint8_t)0x0F)
+
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
+                                       ((PINSOURCE) == GPIO_PinSource1) || \
+                                       ((PINSOURCE) == GPIO_PinSource2) || \
+                                       ((PINSOURCE) == GPIO_PinSource3) || \
+                                       ((PINSOURCE) == GPIO_PinSource4) || \
+                                       ((PINSOURCE) == GPIO_PinSource5) || \
+                                       ((PINSOURCE) == GPIO_PinSource6) || \
+                                       ((PINSOURCE) == GPIO_PinSource7) || \
+                                       ((PINSOURCE) == GPIO_PinSource8) || \
+                                       ((PINSOURCE) == GPIO_PinSource9) || \
+                                       ((PINSOURCE) == GPIO_PinSource10) || \
+                                       ((PINSOURCE) == GPIO_PinSource11) || \
+                                       ((PINSOURCE) == GPIO_PinSource12) || \
+                                       ((PINSOURCE) == GPIO_PinSource13) || \
+                                       ((PINSOURCE) == GPIO_PinSource14) || \
+                                       ((PINSOURCE) == GPIO_PinSource15))
+/**
+  * @}
+  */ 
+
+/** @defgroup GPIO_Alternat_function_selection_define 
+  * @{
+  */ 
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping */
+#define GPIO_AF_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping */
+#define GPIO_AF_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping */
+#define GPIO_AF_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 6 selection  
+  */ 
+#define GPIO_AF_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping */
+
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping */
+#define GPIO_AF_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping */
+#define GPIO_AF_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping */
+#define GPIO_AF_I2S3ext       ((uint8_t)0x07)  /* I2S3ext Alternate Function mapping */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping */
+#define GPIO_AF_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping */
+#define GPIO_AF_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping */
+#define GPIO_AF_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping */
+#define GPIO_AF_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping */
+#define GPIO_AF_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping */
+#define GPIO_AF_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF_OTG_FS         ((uint8_t)0xA)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF_OTG_HS         ((uint8_t)0xA)  /* OTG_HS Alternate Function mapping */
+
+/** 
+  * @brief   AF 11 selection  
+  */ 
+#define GPIO_AF_ETH             ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
+
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF_FSMC            ((uint8_t)0xC)  /* FSMC Alternate Function mapping */
+#define GPIO_AF_OTG_HS_FS       ((uint8_t)0xC)  /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF_SDIO            ((uint8_t)0xC)  /* SDIO Alternate Function mapping */
+
+/** 
+  * @brief   AF 13 selection  
+  */ 
+#define GPIO_AF_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_RTC_50Hz)  || ((AF) == GPIO_AF_TIM14)  || \
+                          ((AF) == GPIO_AF_MCO)       || ((AF) == GPIO_AF_TAMPER) || \
+                          ((AF) == GPIO_AF_SWJ)       || ((AF) == GPIO_AF_TRACE)  || \
+                          ((AF) == GPIO_AF_TIM1)      || ((AF) == GPIO_AF_TIM2)   || \
+                          ((AF) == GPIO_AF_TIM3)      || ((AF) == GPIO_AF_TIM4)   || \
+                          ((AF) == GPIO_AF_TIM5)      || ((AF) == GPIO_AF_TIM8)   || \
+                          ((AF) == GPIO_AF_I2C1)      || ((AF) == GPIO_AF_I2C2)   || \
+                          ((AF) == GPIO_AF_I2C3)      || ((AF) == GPIO_AF_SPI1)   || \
+                          ((AF) == GPIO_AF_SPI2)      || ((AF) == GPIO_AF_TIM13)  || \
+                          ((AF) == GPIO_AF_SPI3)      || ((AF) == GPIO_AF_TIM14)  || \
+                          ((AF) == GPIO_AF_USART1)    || ((AF) == GPIO_AF_USART2) || \
+                          ((AF) == GPIO_AF_USART3)    || ((AF) == GPIO_AF_UART4)  || \
+                          ((AF) == GPIO_AF_UART5)     || ((AF) == GPIO_AF_USART6) || \
+                          ((AF) == GPIO_AF_CAN1)      || ((AF) == GPIO_AF_CAN2)   || \
+                          ((AF) == GPIO_AF_OTG_FS)    || ((AF) == GPIO_AF_OTG_HS) || \
+                          ((AF) == GPIO_AF_ETH)       || ((AF) == GPIO_AF_FSMC)   || \
+                          ((AF) == GPIO_AF_OTG_HS_FS) || ((AF) == GPIO_AF_SDIO)   || \
+                          ((AF) == GPIO_AF_DCMI)      || ((AF) == GPIO_AF_EVENTOUT))
+/**
+  * @}
+  */ 
+
+/** @defgroup GPIO_Legacy 
+  * @{
+  */
+    
+#define GPIO_Mode_AIN           GPIO_Mode_AN
+
+#define GPIO_AF_OTG1_FS         GPIO_AF_OTG_FS
+#define GPIO_AF_OTG2_HS         GPIO_AF_OTG_HS
+#define GPIO_AF_OTG2_FS         GPIO_AF_OTG_HS_FS
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/*  Function used to set the GPIO configuration to the default reset state ****/
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+
+/* Initialization and Configuration functions *********************************/
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+
+/* GPIO Read and Write functions **********************************************/
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
+void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+
+/* GPIO Alternate functions configuration function ****************************/
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__HARDWARE_GPIO_H__ */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/hardware_i2c.h

@@ -0,0 +1,711 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_i2c.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    30-September-2011
+  * @brief   This file contains all the functions prototypes for the I2C firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+
+/**
+* @file: hardware_i2c.h
+* @brief: define hardware i2c function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/*************************************************
+File name: hardware_i2c.h
+Description: define hardware i2c function
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_i2c.h for XiZi
+*************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HARDWARE_I2C_H__
+#define __HARDWARE_I2C_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stm32f4xx.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup I2C
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  I2C Init structure definition  
+  */
+
+typedef struct
+{
+  uint32_t I2C_ClockSpeed;          /*!< Specifies the clock frequency.
+                                         This parameter must be set to a value lower than 400kHz */
+
+  uint16_t I2C_Mode;                /*!< Specifies the I2C mode.
+                                         This parameter can be a value of @ref I2C_mode */
+
+  uint16_t I2C_DutyCycle;           /*!< Specifies the I2C fast mode duty cycle.
+                                         This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+  uint16_t I2C_OwnAddress1;         /*!< Specifies the first device own address.
+                                         This parameter can be a 7-bit or 10-bit address. */
+
+  uint16_t I2C_Ack;                 /*!< Enables or disables the acknowledgement.
+                                         This parameter can be a value of @ref I2C_acknowledgement */
+
+  uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
+                                         This parameter can be a value of @ref I2C_acknowledged_address */
+}I2C_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+
+/** @defgroup I2C_Exported_Constants
+  * @{
+  */
+
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
+                                   ((PERIPH) == I2C2) || \
+                                   ((PERIPH) == I2C3))
+/** @defgroup I2C_mode 
+  * @{
+  */
+
+#define I2C_Mode_I2C                    ((uint16_t)0x0000)
+#define I2C_Mode_SMBusDevice            ((uint16_t)0x0002)  
+#define I2C_Mode_SMBusHost              ((uint16_t)0x000A)
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
+                           ((MODE) == I2C_Mode_SMBusDevice) || \
+                           ((MODE) == I2C_Mode_SMBusHost))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_duty_cycle_in_fast_mode 
+  * @{
+  */
+
+#define I2C_DutyCycle_16_9              ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
+#define I2C_DutyCycle_2                 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
+                                  ((CYCLE) == I2C_DutyCycle_2))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_acknowledgement
+  * @{
+  */
+
+#define I2C_Ack_Enable                  ((uint16_t)0x0400)
+#define I2C_Ack_Disable                 ((uint16_t)0x0000)
+#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
+                                 ((STATE) == I2C_Ack_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_transfer_direction 
+  * @{
+  */
+
+#define  I2C_Direction_Transmitter      ((uint8_t)0x00)
+#define  I2C_Direction_Receiver         ((uint8_t)0x01)
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
+                                     ((DIRECTION) == I2C_Direction_Receiver))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_acknowledged_address 
+  * @{
+  */
+
+#define I2C_AcknowledgedAddress_7bit    ((uint16_t)0x4000)
+#define I2C_AcknowledgedAddress_10bit   ((uint16_t)0xC000)
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
+                                             ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_registers 
+  * @{
+  */
+
+#define I2C_Register_CR1                ((uint8_t)0x00)
+#define I2C_Register_CR2                ((uint8_t)0x04)
+#define I2C_Register_OAR1               ((uint8_t)0x08)
+#define I2C_Register_OAR2               ((uint8_t)0x0C)
+#define I2C_Register_DR                 ((uint8_t)0x10)
+#define I2C_Register_SR1                ((uint8_t)0x14)
+#define I2C_Register_SR2                ((uint8_t)0x18)
+#define I2C_Register_CCR                ((uint8_t)0x1C)
+#define I2C_Register_TRISE              ((uint8_t)0x20)
+#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
+                                   ((REGISTER) == I2C_Register_CR2) || \
+                                   ((REGISTER) == I2C_Register_OAR1) || \
+                                   ((REGISTER) == I2C_Register_OAR2) || \
+                                   ((REGISTER) == I2C_Register_DR) || \
+                                   ((REGISTER) == I2C_Register_SR1) || \
+                                   ((REGISTER) == I2C_Register_SR2) || \
+                                   ((REGISTER) == I2C_Register_CCR) || \
+                                   ((REGISTER) == I2C_Register_TRISE))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_NACK_position 
+  * @{
+  */
+
+#define I2C_NACKPosition_Next           ((uint16_t)0x0800)
+#define I2C_NACKPosition_Current        ((uint16_t)0xF7FF)
+#define IS_I2C_NACK_POSITION(POSITION)  (((POSITION) == I2C_NACKPosition_Next) || \
+                                         ((POSITION) == I2C_NACKPosition_Current))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_SMBus_alert_pin_level 
+  * @{
+  */
+
+#define I2C_SMBusAlert_Low              ((uint16_t)0x2000)
+#define I2C_SMBusAlert_High             ((uint16_t)0xDFFF)
+#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
+                                   ((ALERT) == I2C_SMBusAlert_High))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_PEC_position 
+  * @{
+  */
+
+#define I2C_PECPosition_Next            ((uint16_t)0x0800)
+#define I2C_PECPosition_Current         ((uint16_t)0xF7FF)
+#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
+                                       ((POSITION) == I2C_PECPosition_Current))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_interrupts_definition 
+  * @{
+  */
+
+#define I2C_IT_BUF                      ((uint16_t)0x0400)
+#define I2C_IT_EVT                      ((uint16_t)0x0200)
+#define I2C_IT_ERR                      ((uint16_t)0x0100)
+#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_interrupts_definition 
+  * @{
+  */
+
+#define I2C_IT_SMBALERT                 ((uint32_t)0x01008000)
+#define I2C_IT_TIMEOUT                  ((uint32_t)0x01004000)
+#define I2C_IT_PECERR                   ((uint32_t)0x01001000)
+#define I2C_IT_OVR                      ((uint32_t)0x01000800)
+#define I2C_IT_AF                       ((uint32_t)0x01000400)
+#define I2C_IT_ARLO                     ((uint32_t)0x01000200)
+#define I2C_IT_BERR                     ((uint32_t)0x01000100)
+#define I2C_IT_TXE                      ((uint32_t)0x06000080)
+#define I2C_IT_RXNE                     ((uint32_t)0x06000040)
+#define I2C_IT_STOPF                    ((uint32_t)0x02000010)
+#define I2C_IT_ADD10                    ((uint32_t)0x02000008)
+#define I2C_IT_BTF                      ((uint32_t)0x02000004)
+#define I2C_IT_ADDR                     ((uint32_t)0x02000002)
+#define I2C_IT_SB                       ((uint32_t)0x02000001)
+
+#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
+
+#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
+                           ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
+                           ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
+                           ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
+                           ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
+                           ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
+                           ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_flags_definition 
+  * @{
+  */
+
+/** 
+  * @brief  SR2 register flags  
+  */
+
+#define I2C_FLAG_DUALF                  ((uint32_t)0x00800000)
+#define I2C_FLAG_SMBHOST                ((uint32_t)0x00400000)
+#define I2C_FLAG_SMBDEFAULT             ((uint32_t)0x00200000)
+#define I2C_FLAG_GENCALL                ((uint32_t)0x00100000)
+#define I2C_FLAG_TRA                    ((uint32_t)0x00040000)
+#define I2C_FLAG_BUSY                   ((uint32_t)0x00020000)
+#define I2C_FLAG_MSL                    ((uint32_t)0x00010000)
+
+/** 
+  * @brief  SR1 register flags  
+  */
+
+#define I2C_FLAG_SMBALERT               ((uint32_t)0x10008000)
+#define I2C_FLAG_TIMEOUT                ((uint32_t)0x10004000)
+#define I2C_FLAG_PECERR                 ((uint32_t)0x10001000)
+#define I2C_FLAG_OVR                    ((uint32_t)0x10000800)
+#define I2C_FLAG_AF                     ((uint32_t)0x10000400)
+#define I2C_FLAG_ARLO                   ((uint32_t)0x10000200)
+#define I2C_FLAG_BERR                   ((uint32_t)0x10000100)
+#define I2C_FLAG_TXE                    ((uint32_t)0x10000080)
+#define I2C_FLAG_RXNE                   ((uint32_t)0x10000040)
+#define I2C_FLAG_STOPF                  ((uint32_t)0x10000010)
+#define I2C_FLAG_ADD10                  ((uint32_t)0x10000008)
+#define I2C_FLAG_BTF                    ((uint32_t)0x10000004)
+#define I2C_FLAG_ADDR                   ((uint32_t)0x10000002)
+#define I2C_FLAG_SB                     ((uint32_t)0x10000001)
+
+#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
+                               ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
+                               ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
+                               ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
+                               ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
+                               ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
+                               ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
+                               ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
+                               ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
+                               ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
+                               ((FLAG) == I2C_FLAG_SB))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Events 
+  * @{
+  */
+
+/**
+ ===============================================================================
+               I2C Master Events (Events grouped in order of communication)
+ ===============================================================================
+ */
+
+/** 
+  * @brief  Communication start
+  * 
+  * After sending the START condition (I2C_GenerateSTART() function) the master 
+  * has to wait for this event. It means that the Start condition has been correctly 
+  * released on the I2C bus (the bus is free, no other devices is communicating).
+  * 
+  */
+/* --EV5 */
+#define  I2C_EVENT_MASTER_MODE_SELECT                      ((uint32_t)0x00030001)  /* BUSY, MSL and SB flag */
+
+/** 
+  * @brief  Address Acknowledge
+  * 
+  * After checking on EV5 (start condition correctly released on the bus), the 
+  * master sends the address of the slave(s) with which it will communicate 
+  * (I2C_Send7bitAddress() function, it also determines the direction of the communication: 
+  * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges 
+  * his address. If an acknowledge is sent on the bus, one of the following events will 
+  * be set:
+  * 
+  *  1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED 
+  *     event is set.
+  *  
+  *  2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED 
+  *     is set
+  *  
+  *  3) In case of 10-Bit addressing mode, the master (just after generating the START 
+  *  and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() 
+  *  function). Then master should wait on EV9. It means that the 10-bit addressing 
+  *  header has been correctly sent on the bus. Then master should send the second part of 
+  *  the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master 
+  *  should wait for event EV6. 
+  *     
+  */
+
+/* --EV6 */
+#define  I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED        ((uint32_t)0x00070082)  /* BUSY, MSL, ADDR, TXE and TRA flags */
+#define  I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED           ((uint32_t)0x00030002)  /* BUSY, MSL and ADDR flags */
+/* --EV9 */
+#define  I2C_EVENT_MASTER_MODE_ADDRESS10                   ((uint32_t)0x00030008)  /* BUSY, MSL and ADD10 flags */
+
+/** 
+  * @brief Communication events
+  * 
+  * If a communication is established (START condition generated and slave address 
+  * acknowledged) then the master has to check on one of the following events for 
+  * communication procedures:
+  *  
+  * 1) Master Receiver mode: The master has to wait on the event EV7 then to read 
+  *    the data received from the slave (I2C_ReceiveData() function).
+  * 
+  * 2) Master Transmitter mode: The master has to send data (I2C_SendData() 
+  *    function) then to wait on event EV8 or EV8_2.
+  *    These two events are similar: 
+  *     - EV8 means that the data has been written in the data register and is 
+  *       being shifted out.
+  *     - EV8_2 means that the data has been physically shifted out and output 
+  *       on the bus.
+  *     In most cases, using EV8 is sufficient for the application.
+  *     Using EV8_2 leads to a slower communication but ensure more reliable test.
+  *     EV8_2 is also more suitable than EV8 for testing on the last data transmission 
+  *     (before Stop condition generation).
+  *     
+  *  @note In case the  user software does not guarantee that this event EV7 is 
+  *        managed before the current byte end of transfer, then user may check on EV7 
+  *        and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
+  *        In this case the communication may be slower.
+  * 
+  */
+
+/* Master RECEIVER mode -----------------------------*/ 
+/* --EV7 */
+#define  I2C_EVENT_MASTER_BYTE_RECEIVED                    ((uint32_t)0x00030040)  /* BUSY, MSL and RXNE flags */
+
+/* Master TRANSMITTER mode --------------------------*/
+/* --EV8 */
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING                 ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
+/* --EV8_2 */
+#define  I2C_EVENT_MASTER_BYTE_TRANSMITTED                 ((uint32_t)0x00070084)  /* TRA, BUSY, MSL, TXE and BTF flags */
+
+
+/**
+ ===============================================================================
+               I2C Slave Events (Events grouped in order of communication)
+ ===============================================================================
+ */
+
+
+/** 
+  * @brief  Communication start events
+  * 
+  * Wait on one of these events at the start of the communication. It means that 
+  * the I2C peripheral detected a Start condition on the bus (generated by master 
+  * device) followed by the peripheral address. The peripheral generates an ACK 
+  * condition on the bus (if the acknowledge feature is enabled through function 
+  * I2C_AcknowledgeConfig()) and the events listed above are set :
+  *  
+  * 1) In normal case (only one address managed by the slave), when the address 
+  *   sent by the master matches the own address of the peripheral (configured by 
+  *   I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set 
+  *   (where XXX could be TRANSMITTER or RECEIVER).
+  *    
+  * 2) In case the address sent by the master matches the second address of the 
+  *   peripheral (configured by the function I2C_OwnAddress2Config() and enabled 
+  *   by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED 
+  *   (where XXX could be TRANSMITTER or RECEIVER) are set.
+  *   
+  * 3) In case the address sent by the master is General Call (address 0x00) and 
+  *   if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) 
+  *   the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.   
+  * 
+  */
+
+/* --EV1  (all the events below are variants of EV1) */   
+/* 1) Case of One Single Address managed by the slave */
+#define  I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED          ((uint32_t)0x00020002) /* BUSY and ADDR flags */
+#define  I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED       ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
+
+/* 2) Case of Dual address managed by the slave */
+#define  I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED    ((uint32_t)0x00820000)  /* DUALF and BUSY flags */
+#define  I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080)  /* DUALF, TRA, BUSY and TXE flags */
+
+/* 3) Case of General Call enabled for the slave */
+#define  I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED        ((uint32_t)0x00120000)  /* GENCALL and BUSY flags */
+
+/** 
+  * @brief  Communication events
+  * 
+  * Wait on one of these events when EV1 has already been checked and: 
+  * 
+  * - Slave RECEIVER mode:
+  *     - EV2: When the application is expecting a data byte to be received. 
+  *     - EV4: When the application is expecting the end of the communication: master 
+  *       sends a stop condition and data transmission is stopped.
+  *    
+  * - Slave Transmitter mode:
+  *    - EV3: When a byte has been transmitted by the slave and the application is expecting 
+  *      the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
+  *      I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be 
+  *      used when the user software doesn't guarantee the EV3 is managed before the
+  *      current byte end of transfer.
+  *    - EV3_2: When the master sends a NACK in order to tell slave that data transmission 
+  *      shall end (before sending the STOP condition). In this case slave has to stop sending 
+  *      data bytes and expect a Stop condition on the bus.
+  *      
+  *  @note In case the  user software does not guarantee that the event EV2 is 
+  *        managed before the current byte end of transfer, then user may check on EV2 
+  *        and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
+  *        In this case the communication may be slower.
+  *
+  */
+
+/* Slave RECEIVER mode --------------------------*/ 
+/* --EV2 */
+#define  I2C_EVENT_SLAVE_BYTE_RECEIVED                     ((uint32_t)0x00020040)  /* BUSY and RXNE flags */
+/* --EV4  */
+#define  I2C_EVENT_SLAVE_STOP_DETECTED                     ((uint32_t)0x00000010)  /* STOPF flag */
+
+/* Slave TRANSMITTER mode -----------------------*/
+/* --EV3 */
+#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTED                  ((uint32_t)0x00060084)  /* TRA, BUSY, TXE and BTF flags */
+#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTING                 ((uint32_t)0x00060080)  /* TRA, BUSY and TXE flags */
+/* --EV3_2 */
+#define  I2C_EVENT_SLAVE_ACK_FAILURE                       ((uint32_t)0x00000400)  /* AF flag */
+
+/*
+ ===============================================================================
+                          End of Events Description
+ ===============================================================================
+ */
+
+#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
+                             ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
+                             ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_own_address1 
+  * @{
+  */
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_clock_speed 
+  * @{
+  */
+
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/*  Function used to set the I2C configuration to the default reset state *****/
+void I2C_DeInit(I2C_TypeDef* I2Cx);
+
+/* Initialization and Configuration functions *********************************/
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
+void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
+/* Data transfers functions ***************************************************/ 
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
+
+/* PEC management functions ***************************************************/ 
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
+
+/* DMA transfers management functions *****************************************/
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
+/* Interrupts, events and flags management functions **************************/
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
+
+/* 
+ ===============================================================================
+                          I2C State Monitoring Functions
+ ===============================================================================
+  This I2C driver provides three different ways for I2C state monitoring
+  depending on the application requirements and constraints:
+         
+   
+     1. Basic state monitoring (Using I2C_CheckEvent() function)
+     -----------------------------------------------------------
+        It compares the status registers (SR1 and SR2) content to a given event
+        (can be the combination of one or more flags).
+        It returns SUCCESS if the current status includes the given flags 
+        and returns ST_ERROR if one or more flags are missing in the current status.
+
+          - When to use
+             - This function is suitable for most applications as well as for startup 
+               activity since the events are fully described in the product reference 
+               manual (RM0090).
+             - It is also suitable for users who need to define their own events.
+
+          - Limitations
+             - If an error occurs (ie. error flags are set besides to the monitored 
+               flags), the I2C_CheckEvent() function may return SUCCESS despite 
+               the communication hold or corrupted real state. 
+               In this case, it is advised to use error interrupts to monitor 
+               the error events and handle them in the interrupt IRQ handler.
+         
+     Note 
+         For error management, it is advised to use the following functions:
+           - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
+           - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+             Where x is the peripheral instance (I2C1, I2C2 ...)
+           - I2C_GetFlagStatus() or I2C_GetITStatus()  to be called into the 
+             I2Cx_ER_IRQHandler() function in order to determine which error occurred.
+           - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() 
+             and/or I2C_GenerateStop() in order to clear the error flag and source 
+             and return to correct  communication status.
+             
+ 
+     2. Advanced state monitoring (Using the function I2C_GetLastEvent())
+     -------------------------------------------------------------------- 
+        Using the function I2C_GetLastEvent() which returns the image of both status 
+        registers in a single word (uint32_t) (Status Register 2 value is shifted left 
+        by 16 bits and concatenated to Status Register 1).
+
+          - When to use
+             - This function is suitable for the same applications above but it 
+               allows to overcome the mentioned limitation of I2C_GetFlagStatus() 
+               function.
+             - The returned value could be compared to events already defined in 
+               this file or to custom values defined by user.
+               This function is suitable when multiple flags are monitored at the 
+               same time.
+             - At the opposite of I2C_CheckEvent() function, this function allows 
+               user to choose when an event is accepted (when all events flags are 
+               set and no other flags are set or just when the needed flags are set 
+               like I2C_CheckEvent() function.
+
+          - Limitations
+             - User may need to define his own events.
+             - Same remark concerning the error management is applicable for this 
+               function if user decides to check only regular communication flags 
+               (and ignores error flags).
+      
+ 
+     3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())
+     -----------------------------------------------------------------------
+     
+      Using the function I2C_GetFlagStatus() which simply returns the status of 
+      one single flag (ie. I2C_FLAG_RXNE ...). 
+
+          - When to use
+             - This function could be used for specific applications or in debug 
+               phase.
+             - It is suitable when only one flag checking is needed (most I2C 
+               events are monitored through multiple flags).
+          - Limitations: 
+             - When calling this function, the Status register is accessed. 
+               Some flags are cleared when the status register is accessed. 
+               So checking the status of one Flag, may clear other ones.
+             - Function may need to be called twice or more in order to monitor 
+               one single event.           
+ */
+
+/*
+ ===============================================================================
+                          1. Basic state monitoring
+ ===============================================================================
+ */
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
+/*
+ ===============================================================================
+                          2. Advanced state monitoring
+ ===============================================================================
+ */
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
+/*
+ ===============================================================================
+                          3. Flag-based state monitoring
+ ===============================================================================
+ */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+
+
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__HARDWARE_I2C_H__ */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/hardware_iwdg.h

@@ -0,0 +1,144 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_iwdg.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    30-September-2011
+  * @brief   This file contains all the functions prototypes for the IWDG 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/**
+* @file: hardware_iwdg.h
+* @brief: define hardware iwdg function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/*************************************************
+File name: hardware_iwdg.h
+Description: define hardware iwdg function
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_iwdg.h for XiZi
+*************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HARDWARE_IWDG_H__
+#define __HARDWARE_IWDG_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stm32f4xx.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup IWDG
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup IWDG_Exported_Constants
+  * @{
+  */
+  
+/** @defgroup IWDG_WriteAccess
+  * @{
+  */
+#define IWDG_WriteAccess_Enable     ((uint16_t)0x5555)
+#define IWDG_WriteAccess_Disable    ((uint16_t)0x0000)
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
+                                      ((ACCESS) == IWDG_WriteAccess_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_prescaler 
+  * @{
+  */
+#define IWDG_Prescaler_4            ((uint8_t)0x00)
+#define IWDG_Prescaler_8            ((uint8_t)0x01)
+#define IWDG_Prescaler_16           ((uint8_t)0x02)
+#define IWDG_Prescaler_32           ((uint8_t)0x03)
+#define IWDG_Prescaler_64           ((uint8_t)0x04)
+#define IWDG_Prescaler_128          ((uint8_t)0x05)
+#define IWDG_Prescaler_256          ((uint8_t)0x06)
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4)  || \
+                                      ((PRESCALER) == IWDG_Prescaler_8)  || \
+                                      ((PRESCALER) == IWDG_Prescaler_16) || \
+                                      ((PRESCALER) == IWDG_Prescaler_32) || \
+                                      ((PRESCALER) == IWDG_Prescaler_64) || \
+                                      ((PRESCALER) == IWDG_Prescaler_128)|| \
+                                      ((PRESCALER) == IWDG_Prescaler_256))
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Flag 
+  * @{
+  */
+#define IWDG_FLAG_PVU               ((uint16_t)0x0001)
+#define IWDG_FLAG_RVU               ((uint16_t)0x0002)
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Prescaler and Counter configuration functions ******************************/
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
+void IWDG_SetReload(uint16_t Reload);
+void IWDG_ReloadCounter(void);
+
+/* IWDG activation function ***************************************************/
+void IWDG_Enable(void);
+
+/* Flag management function ***************************************************/
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HARDWARE_IWDG_H__ */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/hardware_pwr.h

@@ -0,0 +1,198 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_pwr.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    30-September-2011
+  * @brief   This file contains all the functions prototypes for the PWR firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/**
+* @file: hardware_pwr.h
+* @brief: define hardware pwr function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/*************************************************
+File name: hardware_pwr.h
+Description: define hardware pwr function
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_pwr.h for XiZi
+*************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HARDWARE_PWR_H__
+#define __HARDWARE_PWR_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stm32f4xx.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup PWR
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Constants
+  * @{
+  */ 
+
+/** @defgroup PWR_PVD_detection_level 
+  * @{
+  */ 
+
+#define PWR_PVDLevel_0                  PWR_CR_PLS_LEV0
+#define PWR_PVDLevel_1                  PWR_CR_PLS_LEV1
+#define PWR_PVDLevel_2                  PWR_CR_PLS_LEV2
+#define PWR_PVDLevel_3                  PWR_CR_PLS_LEV3
+#define PWR_PVDLevel_4                  PWR_CR_PLS_LEV4
+#define PWR_PVDLevel_5                  PWR_CR_PLS_LEV5
+#define PWR_PVDLevel_6                  PWR_CR_PLS_LEV6
+#define PWR_PVDLevel_7                  PWR_CR_PLS_LEV7
+
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
+                                 ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
+                                 ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
+                                 ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
+/**
+  * @}
+  */
+
+  
+/** @defgroup PWR_Regulator_state_in_STOP_mode 
+  * @{
+  */
+
+#define PWR_Regulator_ON                ((uint32_t)0x00000000)
+#define PWR_Regulator_LowPower          PWR_CR_LPDS
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
+                                     ((REGULATOR) == PWR_Regulator_LowPower))
+/**
+  * @}
+  */
+
+/** @defgroup PWR_STOP_mode_entry 
+  * @{
+  */
+
+#define PWR_STOPEntry_WFI               ((uint8_t)0x01)
+#define PWR_STOPEntry_WFE               ((uint8_t)0x02)
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
+
+/** @defgroup PWR_Regulator_Voltage_Scale 
+  * @{
+  */
+
+#define PWR_Regulator_Voltage_Scale1    ((uint32_t)0x00004000)
+#define PWR_Regulator_Voltage_Scale2    ((uint32_t)0x00000000)
+#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || ((VOLTAGE) == PWR_Regulator_Voltage_Scale2))
+ 
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Flag 
+  * @{
+  */
+
+#define PWR_FLAG_WU                     PWR_CSR_WUF
+#define PWR_FLAG_SB                     PWR_CSR_SBF
+#define PWR_FLAG_PVDO                   PWR_CSR_PVDO
+#define PWR_FLAG_BRR                    PWR_CSR_BRR
+#define PWR_FLAG_VOSRDY                 PWR_CSR_VOSRDY
+
+/** @defgroup PWR_Flag_Legacy 
+  * @{
+  */
+#define PWR_FLAG_REGRDY                  PWR_FLAG_VOSRDY               
+/**
+  * @}
+  */
+
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
+                               ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \
+                               ((FLAG) == PWR_FLAG_VOSRDY))
+
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/* Function used to set the PWR configuration to the default reset state ******/ 
+void PWR_DeInit(void);
+
+/* Backup Domain Access function **********************************************/ 
+void PWR_BackupAccessCmd(FunctionalState NewState);
+
+/* PVD configuration functions ************************************************/ 
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
+void PWR_PVDCmd(FunctionalState NewState);
+
+/* WakeUp pins configuration functions ****************************************/ 
+void PWR_WakeUpPinCmd(FunctionalState NewState);
+
+/* Main and Backup Regulators configuration functions *************************/ 
+void PWR_BackupRegulatorCmd(FunctionalState NewState);
+void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage);
+
+/* FLASH Power Down configuration functions ***********************************/ 
+void PWR_FlashPowerDownCmd(FunctionalState NewState);
+
+/* Low Power modes configuration functions ************************************/ 
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void PWR_EnterSTANDBYMode(void);
+
+/* Flags management functions *************************************************/ 
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HARDWARE_PWR_H__ */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/hardware_rcc.h

@@ -0,0 +1,529 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_rcc.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    30-September-2011
+  * @brief   This file contains all the functions prototypes for the RCC firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/**
+* @file: hardware_rcc.h
+* @brief: define hardware rcc function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/*************************************************
+File name: hardware_rcc.h
+Description: define hardware rcc function
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_rcc.h for XiZi
+*************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HARDWARE_RCC_H__
+#define __HARDWARE_RCC_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stm32f4xx.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup RCC
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+typedef struct
+{
+  uint32_t SYSCLK_Frequency; /*!<  SYSCLK clock frequency expressed in Hz */
+  uint32_t HCLK_Frequency;   /*!<  HCLK clock frequency expressed in Hz */
+  uint32_t PCLK1_Frequency;  /*!<  PCLK1 clock frequency expressed in Hz */
+  uint32_t PCLK2_Frequency;  /*!<  PCLK2 clock frequency expressed in Hz */
+}RCC_ClocksTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Constants
+  * @{
+  */
+  
+/** @defgroup RCC_HSE_configuration 
+  * @{
+  */
+#define RCC_HSE_OFF                      ((uint8_t)0x00)
+#define RCC_HSE_ON                       ((uint8_t)0x01)
+#define RCC_HSE_Bypass                   ((uint8_t)0x05)
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+                         ((HSE) == RCC_HSE_Bypass))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_PLL_Clock_Source 
+  * @{
+  */
+#define RCC_PLLSource_HSI                ((uint32_t)0x00000000)
+#define RCC_PLLSource_HSE                ((uint32_t)0x00400000)
+#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
+                                   ((SOURCE) == RCC_PLLSource_HSE))
+#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
+#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
+#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
+#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
+ 
+#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
+#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))   
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_System_Clock_Source 
+  * @{
+  */
+#define RCC_SYSCLKSource_HSI             ((uint32_t)0x00000000)
+#define RCC_SYSCLKSource_HSE             ((uint32_t)0x00000001)
+#define RCC_SYSCLKSource_PLLCLK          ((uint32_t)0x00000002)
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
+                                      ((SOURCE) == RCC_SYSCLKSource_HSE) || \
+                                      ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_AHB_Clock_Source
+  * @{
+  */
+#define RCC_SYSCLK_Div1                  ((uint32_t)0x00000000)
+#define RCC_SYSCLK_Div2                  ((uint32_t)0x00000080)
+#define RCC_SYSCLK_Div4                  ((uint32_t)0x00000090)
+#define RCC_SYSCLK_Div8                  ((uint32_t)0x000000A0)
+#define RCC_SYSCLK_Div16                 ((uint32_t)0x000000B0)
+#define RCC_SYSCLK_Div64                 ((uint32_t)0x000000C0)
+#define RCC_SYSCLK_Div128                ((uint32_t)0x000000D0)
+#define RCC_SYSCLK_Div256                ((uint32_t)0x000000E0)
+#define RCC_SYSCLK_Div512                ((uint32_t)0x000000F0)
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
+                           ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
+                           ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
+                           ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
+                           ((HCLK) == RCC_SYSCLK_Div512))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_APB1_APB2_Clock_Source
+  * @{
+  */
+#define RCC_HCLK_Div1                    ((uint32_t)0x00000000)
+#define RCC_HCLK_Div2                    ((uint32_t)0x00001000)
+#define RCC_HCLK_Div4                    ((uint32_t)0x00001400)
+#define RCC_HCLK_Div8                    ((uint32_t)0x00001800)
+#define RCC_HCLK_Div16                   ((uint32_t)0x00001C00)
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
+                           ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
+                           ((PCLK) == RCC_HCLK_Div16))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_Interrupt_Source 
+  * @{
+  */
+#define RCC_IT_LSIRDY                    ((uint8_t)0x01)
+#define RCC_IT_LSERDY                    ((uint8_t)0x02)
+#define RCC_IT_HSIRDY                    ((uint8_t)0x04)
+#define RCC_IT_HSERDY                    ((uint8_t)0x08)
+#define RCC_IT_PLLRDY                    ((uint8_t)0x10)
+#define RCC_IT_PLLI2SRDY                 ((uint8_t)0x20)
+#define RCC_IT_CSS                       ((uint8_t)0x80)
+#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
+#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
+                           ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
+                           ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
+                           ((IT) == RCC_IT_PLLI2SRDY))
+#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_LSE_Configuration 
+  * @{
+  */
+#define RCC_LSE_OFF                      ((uint8_t)0x00)
+#define RCC_LSE_ON                       ((uint8_t)0x01)
+#define RCC_LSE_Bypass                   ((uint8_t)0x04)
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+                         ((LSE) == RCC_LSE_Bypass))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_RTC_Clock_Source
+  * @{
+  */
+#define RCC_RTCCLKSource_LSE             ((uint32_t)0x00000100)
+#define RCC_RTCCLKSource_LSI             ((uint32_t)0x00000200)
+#define RCC_RTCCLKSource_HSE_Div2        ((uint32_t)0x00020300)
+#define RCC_RTCCLKSource_HSE_Div3        ((uint32_t)0x00030300)
+#define RCC_RTCCLKSource_HSE_Div4        ((uint32_t)0x00040300)
+#define RCC_RTCCLKSource_HSE_Div5        ((uint32_t)0x00050300)
+#define RCC_RTCCLKSource_HSE_Div6        ((uint32_t)0x00060300)
+#define RCC_RTCCLKSource_HSE_Div7        ((uint32_t)0x00070300)
+#define RCC_RTCCLKSource_HSE_Div8        ((uint32_t)0x00080300)
+#define RCC_RTCCLKSource_HSE_Div9        ((uint32_t)0x00090300)
+#define RCC_RTCCLKSource_HSE_Div10       ((uint32_t)0x000A0300)
+#define RCC_RTCCLKSource_HSE_Div11       ((uint32_t)0x000B0300)
+#define RCC_RTCCLKSource_HSE_Div12       ((uint32_t)0x000C0300)
+#define RCC_RTCCLKSource_HSE_Div13       ((uint32_t)0x000D0300)
+#define RCC_RTCCLKSource_HSE_Div14       ((uint32_t)0x000E0300)
+#define RCC_RTCCLKSource_HSE_Div15       ((uint32_t)0x000F0300)
+#define RCC_RTCCLKSource_HSE_Div16       ((uint32_t)0x00100300)
+#define RCC_RTCCLKSource_HSE_Div17       ((uint32_t)0x00110300)
+#define RCC_RTCCLKSource_HSE_Div18       ((uint32_t)0x00120300)
+#define RCC_RTCCLKSource_HSE_Div19       ((uint32_t)0x00130300)
+#define RCC_RTCCLKSource_HSE_Div20       ((uint32_t)0x00140300)
+#define RCC_RTCCLKSource_HSE_Div21       ((uint32_t)0x00150300)
+#define RCC_RTCCLKSource_HSE_Div22       ((uint32_t)0x00160300)
+#define RCC_RTCCLKSource_HSE_Div23       ((uint32_t)0x00170300)
+#define RCC_RTCCLKSource_HSE_Div24       ((uint32_t)0x00180300)
+#define RCC_RTCCLKSource_HSE_Div25       ((uint32_t)0x00190300)
+#define RCC_RTCCLKSource_HSE_Div26       ((uint32_t)0x001A0300)
+#define RCC_RTCCLKSource_HSE_Div27       ((uint32_t)0x001B0300)
+#define RCC_RTCCLKSource_HSE_Div28       ((uint32_t)0x001C0300)
+#define RCC_RTCCLKSource_HSE_Div29       ((uint32_t)0x001D0300)
+#define RCC_RTCCLKSource_HSE_Div30       ((uint32_t)0x001E0300)
+#define RCC_RTCCLKSource_HSE_Div31       ((uint32_t)0x001F0300)
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_LSI) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div31))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_I2S_Clock_Source
+  * @{
+  */
+#define RCC_I2S2CLKSource_PLLI2S             ((uint8_t)0x00)
+#define RCC_I2S2CLKSource_Ext                ((uint8_t)0x01)
+
+#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext))                                
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_AHB1_Peripherals 
+  * @{
+  */ 
+#define RCC_AHB1Periph_GPIOA             ((uint32_t)0x00000001)
+#define RCC_AHB1Periph_GPIOB             ((uint32_t)0x00000002)
+#define RCC_AHB1Periph_GPIOC             ((uint32_t)0x00000004)
+#define RCC_AHB1Periph_GPIOD             ((uint32_t)0x00000008)
+#define RCC_AHB1Periph_GPIOE             ((uint32_t)0x00000010)
+#define RCC_AHB1Periph_GPIOF             ((uint32_t)0x00000020)
+#define RCC_AHB1Periph_GPIOG             ((uint32_t)0x00000040)
+#define RCC_AHB1Periph_GPIOH             ((uint32_t)0x00000080)
+#define RCC_AHB1Periph_GPIOI             ((uint32_t)0x00000100)
+#define RCC_AHB1Periph_CRC               ((uint32_t)0x00001000)
+#define RCC_AHB1Periph_FLITF             ((uint32_t)0x00008000)
+#define RCC_AHB1Periph_SRAM1             ((uint32_t)0x00010000)
+#define RCC_AHB1Periph_SRAM2             ((uint32_t)0x00020000)
+#define RCC_AHB1Periph_BKPSRAM           ((uint32_t)0x00040000)
+#define RCC_AHB1Periph_CCMDATARAMEN      ((uint32_t)0x00100000)
+#define RCC_AHB1Periph_DMA1              ((uint32_t)0x00200000)
+#define RCC_AHB1Periph_DMA2              ((uint32_t)0x00400000)
+#define RCC_AHB1Periph_ETH_MAC           ((uint32_t)0x02000000)
+#define RCC_AHB1Periph_ETH_MAC_Tx        ((uint32_t)0x04000000)
+#define RCC_AHB1Periph_ETH_MAC_Rx        ((uint32_t)0x08000000)
+#define RCC_AHB1Periph_ETH_MAC_PTP       ((uint32_t)0x10000000)
+#define RCC_AHB1Periph_OTG_HS            ((uint32_t)0x20000000)
+#define RCC_AHB1Periph_OTG_HS_ULPI       ((uint32_t)0x40000000)
+#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x818BEE00) == 0x00) && ((PERIPH) != 0x00))
+#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00))
+#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81986E00) == 0x00) && ((PERIPH) != 0x00))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_AHB2_Peripherals 
+  * @{
+  */  
+#define RCC_AHB2Periph_DCMI              ((uint32_t)0x00000001)
+#define RCC_AHB2Periph_CRYP              ((uint32_t)0x00000010)
+#define RCC_AHB2Periph_HASH              ((uint32_t)0x00000020)
+#define RCC_AHB2Periph_RNG               ((uint32_t)0x00000040)
+#define RCC_AHB2Periph_OTG_FS            ((uint32_t)0x00000080)
+#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_AHB3_Peripherals 
+  * @{
+  */ 
+#define RCC_AHB3Periph_FSMC               ((uint32_t)0x00000001)
+#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_APB1_Peripherals 
+  * @{
+  */ 
+#define RCC_APB1Periph_TIM2              ((uint32_t)0x00000001)
+#define RCC_APB1Periph_TIM3              ((uint32_t)0x00000002)
+#define RCC_APB1Periph_TIM4              ((uint32_t)0x00000004)
+#define RCC_APB1Periph_TIM5              ((uint32_t)0x00000008)
+#define RCC_APB1Periph_TIM6              ((uint32_t)0x00000010)
+#define RCC_APB1Periph_TIM7              ((uint32_t)0x00000020)
+#define RCC_APB1Periph_TIM12             ((uint32_t)0x00000040)
+#define RCC_APB1Periph_TIM13             ((uint32_t)0x00000080)
+#define RCC_APB1Periph_TIM14             ((uint32_t)0x00000100)
+#define RCC_APB1Periph_WWDG              ((uint32_t)0x00000800)
+#define RCC_APB1Periph_SPI2              ((uint32_t)0x00004000)
+#define RCC_APB1Periph_SPI3              ((uint32_t)0x00008000)
+#define RCC_APB1Periph_USART2            ((uint32_t)0x00020000)
+#define RCC_APB1Periph_USART3            ((uint32_t)0x00040000)
+#define RCC_APB1Periph_UART4             ((uint32_t)0x00080000)
+#define RCC_APB1Periph_UART5             ((uint32_t)0x00100000)
+#define RCC_APB1Periph_I2C1              ((uint32_t)0x00200000)
+#define RCC_APB1Periph_I2C2              ((uint32_t)0x00400000)
+#define RCC_APB1Periph_I2C3              ((uint32_t)0x00800000)
+#define RCC_APB1Periph_CAN1              ((uint32_t)0x02000000)
+#define RCC_APB1Periph_CAN2              ((uint32_t)0x04000000)
+#define RCC_APB1Periph_PWR               ((uint32_t)0x10000000)
+#define RCC_APB1Periph_DAC               ((uint32_t)0x20000000)
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC9013600) == 0x00) && ((PERIPH) != 0x00))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_APB2_Peripherals 
+  * @{
+  */ 
+#define RCC_APB2Periph_TIM1              ((uint32_t)0x00000001)
+#define RCC_APB2Periph_TIM8              ((uint32_t)0x00000002)
+#define RCC_APB2Periph_USART1            ((uint32_t)0x00000010)
+#define RCC_APB2Periph_USART6            ((uint32_t)0x00000020)
+#define RCC_APB2Periph_ADC               ((uint32_t)0x00000100)
+#define RCC_APB2Periph_ADC1              ((uint32_t)0x00000100)
+#define RCC_APB2Periph_ADC2              ((uint32_t)0x00000200)
+#define RCC_APB2Periph_ADC3              ((uint32_t)0x00000400)
+#define RCC_APB2Periph_SDIO              ((uint32_t)0x00000800)
+#define RCC_APB2Periph_SPI1              ((uint32_t)0x00001000)
+#define RCC_APB2Periph_SYSCFG            ((uint32_t)0x00004000)
+#define RCC_APB2Periph_TIM9              ((uint32_t)0x00010000)
+#define RCC_APB2Periph_TIM10             ((uint32_t)0x00020000)
+#define RCC_APB2Periph_TIM11             ((uint32_t)0x00040000)
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A0CC) == 0x00) && ((PERIPH) != 0x00))
+#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A6CC) == 0x00) && ((PERIPH) != 0x00))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_MCO1_Clock_Source_Prescaler
+  * @{
+  */
+#define RCC_MCO1Source_HSI               ((uint32_t)0x00000000)
+#define RCC_MCO1Source_LSE               ((uint32_t)0x00200000)
+#define RCC_MCO1Source_HSE               ((uint32_t)0x00400000)
+#define RCC_MCO1Source_PLLCLK            ((uint32_t)0x00600000)
+#define RCC_MCO1Div_1                    ((uint32_t)0x00000000)
+#define RCC_MCO1Div_2                    ((uint32_t)0x04000000)
+#define RCC_MCO1Div_3                    ((uint32_t)0x05000000)
+#define RCC_MCO1Div_4                    ((uint32_t)0x06000000)
+#define RCC_MCO1Div_5                    ((uint32_t)0x07000000)
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \
+                                   ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
+                                   
+#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
+                             ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
+                             ((DIV) == RCC_MCO1Div_5)) 
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_MCO2_Clock_Source_Prescaler
+  * @{
+  */
+#define RCC_MCO2Source_SYSCLK            ((uint32_t)0x00000000)
+#define RCC_MCO2Source_PLLI2SCLK         ((uint32_t)0x40000000)
+#define RCC_MCO2Source_HSE               ((uint32_t)0x80000000)
+#define RCC_MCO2Source_PLLCLK            ((uint32_t)0xC0000000)
+#define RCC_MCO2Div_1                    ((uint32_t)0x00000000)
+#define RCC_MCO2Div_2                    ((uint32_t)0x20000000)
+#define RCC_MCO2Div_3                    ((uint32_t)0x28000000)
+#define RCC_MCO2Div_4                    ((uint32_t)0x30000000)
+#define RCC_MCO2Div_5                    ((uint32_t)0x38000000)
+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
+                                   ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))
+                                   
+#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
+                             ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
+                             ((DIV) == RCC_MCO2Div_5))                             
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_Flag 
+  * @{
+  */
+#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
+#define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
+#define RCC_FLAG_PLLI2SRDY               ((uint8_t)0x3B)
+#define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
+#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
+#define RCC_FLAG_BORRST                  ((uint8_t)0x79)
+#define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
+#define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
+#define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
+#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
+#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
+#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
+                           ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
+                           ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
+                           ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
+                           ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
+                           ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
+                           ((FLAG) == RCC_FLAG_PLLI2SRDY))
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/* Function used to set the RCC clock configuration to the default reset state */
+void RCC_DeInit(void);
+
+/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
+void RCC_HSEConfig(uint8_t RCC_HSE);
+ErrorStatus RCC_WaitForHSEStartUp(void);
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
+void RCC_HSICmd(FunctionalState NewState);
+void RCC_LSEConfig(uint8_t RCC_LSE);
+void RCC_LSICmd(FunctionalState NewState);
+
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
+void RCC_PLLCmd(FunctionalState NewState);
+void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
+void RCC_PLLI2SCmd(FunctionalState NewState);
+
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
+void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
+void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
+
+/* System, AHB and APB busses clocks configuration functions ******************/
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
+uint8_t RCC_GetSYSCLKSource(void);
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
+void RCC_PCLK1Config(uint32_t RCC_HCLK);
+void RCC_PCLK2Config(uint32_t RCC_HCLK);
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
+
+/* Peripheral clocks configuration functions **********************************/
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
+void RCC_RTCCLKCmd(FunctionalState NewState);
+void RCC_BackupResetCmd(FunctionalState NewState);
+void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); 
+
+void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
+void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
+void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+
+void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
+void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
+void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+
+void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
+void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
+void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
+void RCC_ClearFlag(void);
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);
+void RCC_ClearITPendingBit(uint8_t RCC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HARDWARE_RCC_H__ */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/hardware_rtc.h

@@ -0,0 +1,894 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_rtc.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    30-September-2011
+  * @brief   This file contains all the functions prototypes for the RTC firmware
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ****************************************************************************** 
+  */
+
+/**
+* @file: hardware_rtc.h
+* @brief: define hardware rtc function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/*************************************************
+File name: hardware_rtc.h
+Description: define hardware rtc function
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_rtc.h for XiZi
+*************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HARDWARE_RTC_H__
+#define __HARDWARE_RTC_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stm32f4xx.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup RTC
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  RTC Init structures definition  
+  */ 
+typedef struct
+{
+  uint32_t RTC_HourFormat;   /*!< Specifies the RTC Hour Format.
+                             This parameter can be a value of @ref RTC_Hour_Formats */
+  
+  uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
+                             This parameter must be set to a value lower than 0x7F */
+  
+  uint32_t RTC_SynchPrediv;  /*!< Specifies the RTC Synchronous Predivider value.
+                             This parameter must be set to a value lower than 0x7FFF */
+}RTC_InitTypeDef;
+
+/** 
+  * @brief  RTC Time structure definition  
+  */
+typedef struct
+{
+  uint8_t RTC_Hours;    /*!< Specifies the RTC Time Hour.
+                        This parameter must be set to a value in the 0-12 range
+                        if the RTC_HourFormat_12 is selected or 0-23 range if
+                        the RTC_HourFormat_24 is selected. */
+
+  uint8_t RTC_Minutes;  /*!< Specifies the RTC Time Minutes.
+                        This parameter must be set to a value in the 0-59 range. */
+  
+  uint8_t RTC_Seconds;  /*!< Specifies the RTC Time Seconds.
+                        This parameter must be set to a value in the 0-59 range. */
+
+  uint8_t RTC_H12;      /*!< Specifies the RTC AM/PM Time.
+                        This parameter can be a value of @ref RTC_AM_PM_Definitions */
+}RTC_TimeTypeDef; 
+
+/** 
+  * @brief  RTC Date structure definition  
+  */
+typedef struct
+{
+  uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.
+                        This parameter can be a value of @ref RTC_WeekDay_Definitions */
+  
+  uint8_t RTC_Month;   /*!< Specifies the RTC Date Month (in BCD format).
+                        This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+  uint8_t RTC_Date;     /*!< Specifies the RTC Date.
+                        This parameter must be set to a value in the 1-31 range. */
+  
+  uint8_t RTC_Year;     /*!< Specifies the RTC Date Year.
+                        This parameter must be set to a value in the 0-99 range. */
+}RTC_DateTypeDef;
+
+/** 
+  * @brief  RTC Alarm structure definition  
+  */
+typedef struct
+{
+  RTC_TimeTypeDef RTC_AlarmTime;     /*!< Specifies the RTC Alarm Time members. */
+
+  uint32_t RTC_AlarmMask;            /*!< Specifies the RTC Alarm Masks.
+                                     This parameter can be a value of @ref RTC_AlarmMask_Definitions */
+
+  uint32_t RTC_AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
+                                     This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+  
+  uint8_t RTC_AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
+                                     If the Alarm Date is selected, this parameter
+                                     must be set to a value in the 1-31 range.
+                                     If the Alarm WeekDay is selected, this 
+                                     parameter can be a value of @ref RTC_WeekDay_Definitions */
+}RTC_AlarmTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RTC_Exported_Constants
+  * @{
+  */ 
+
+
+/** @defgroup RTC_Hour_Formats 
+  * @{
+  */ 
+#define RTC_HourFormat_24              ((uint32_t)0x00000000)
+#define RTC_HourFormat_12              ((uint32_t)0x00000040)
+#define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HourFormat_12) || \
+                                        ((FORMAT) == RTC_HourFormat_24))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Asynchronous_Predivider 
+  * @{
+  */ 
+#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= 0x7F)
+ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_Synchronous_Predivider 
+  * @{
+  */ 
+#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= 0x7FFF)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Time_Definitions 
+  * @{
+  */ 
+#define IS_RTC_HOUR12(HOUR)            (((HOUR) > 0) && ((HOUR) <= 12))
+#define IS_RTC_HOUR24(HOUR)            ((HOUR) <= 23)
+#define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= 59)
+#define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= 59)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_AM_PM_Definitions 
+  * @{
+  */ 
+#define RTC_H12_AM                     ((uint8_t)0x00)
+#define RTC_H12_PM                     ((uint8_t)0x40)
+#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Year_Date_Definitions 
+  * @{
+  */ 
+#define IS_RTC_YEAR(YEAR)              ((YEAR) <= 99)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Month_Date_Definitions 
+  * @{
+  */ 
+
+/* Coded in BCD format */
+#define RTC_Month_January              ((uint8_t)0x01)
+#define RTC_Month_February             ((uint8_t)0x02)
+#define RTC_Month_March                ((uint8_t)0x03)
+#define RTC_Month_April                ((uint8_t)0x04)
+#define RTC_Month_May                  ((uint8_t)0x05)
+#define RTC_Month_June                 ((uint8_t)0x06)
+#define RTC_Month_July                 ((uint8_t)0x07)
+#define RTC_Month_August               ((uint8_t)0x08)
+#define RTC_Month_September            ((uint8_t)0x09)
+#define RTC_Month_October              ((uint8_t)0x10)
+#define RTC_Month_November             ((uint8_t)0x11)
+#define RTC_Month_December             ((uint8_t)0x12)
+#define IS_RTC_MONTH(MONTH)            (((MONTH) >= 1) && ((MONTH) <= 12))
+#define IS_RTC_DATE(DATE)              (((DATE) >= 1) && ((DATE) <= 31))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_WeekDay_Definitions 
+  * @{
+  */ 
+  
+#define RTC_Weekday_Monday             ((uint8_t)0x01)
+#define RTC_Weekday_Tuesday            ((uint8_t)0x02)
+#define RTC_Weekday_Wednesday          ((uint8_t)0x03)
+#define RTC_Weekday_Thursday           ((uint8_t)0x04)
+#define RTC_Weekday_Friday             ((uint8_t)0x05)
+#define RTC_Weekday_Saturday           ((uint8_t)0x06)
+#define RTC_Weekday_Sunday             ((uint8_t)0x07)
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Tuesday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Wednesday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Thursday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Friday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Saturday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Sunday))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_Alarm_Definitions
+  * @{
+  */ 
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Tuesday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Wednesday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Thursday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Friday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Saturday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Sunday))
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_AlarmDateWeekDay_Definitions 
+  * @{
+  */ 
+#define RTC_AlarmDateWeekDaySel_Date      ((uint32_t)0x00000000)
+#define RTC_AlarmDateWeekDaySel_WeekDay   ((uint32_t)0x40000000)
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
+                                            ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_AlarmMask_Definitions 
+  * @{
+  */ 
+#define RTC_AlarmMask_None                ((uint32_t)0x00000000)
+#define RTC_AlarmMask_DateWeekDay         ((uint32_t)0x80000000)
+#define RTC_AlarmMask_Hours               ((uint32_t)0x00800000)
+#define RTC_AlarmMask_Minutes             ((uint32_t)0x00008000)
+#define RTC_AlarmMask_Seconds             ((uint32_t)0x00000080)
+#define RTC_AlarmMask_All                 ((uint32_t)0x80808080)
+#define IS_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Alarms_Definitions 
+  * @{
+  */ 
+#define RTC_Alarm_A                       ((uint32_t)0x00000100)
+#define RTC_Alarm_B                       ((uint32_t)0x00000200)
+#define IS_RTC_ALARM(ALARM)     (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))
+#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)
+
+/**
+  * @}
+  */ 
+
+  /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions
+  * @{
+  */ 
+#define RTC_AlarmSubSecondMask_All         ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. 
+                                                                       There is no comparison on sub seconds 
+                                                                       for Alarm */
+#define RTC_AlarmSubSecondMask_SS14_1      ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm 
+                                                                       comparison. Only SS[0] is compared. */
+#define RTC_AlarmSubSecondMask_SS14_2      ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm 
+                                                                       comparison. Only SS[1:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_3      ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm 
+                                                                       comparison. Only SS[2:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_4      ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm 
+                                                                       comparison. Only SS[3:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_5      ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm 
+                                                                       comparison. Only SS[4:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_6      ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm 
+                                                                       comparison. Only SS[5:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_7      ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm 
+                                                                       comparison. Only SS[6:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_8      ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm 
+                                                                       comparison. Only SS[7:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_9      ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm 
+                                                                       comparison. Only SS[8:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_10     ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm 
+                                                                       comparison. Only SS[9:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_11     ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm 
+                                                                       comparison. Only SS[10:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_12     ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm 
+                                                                       comparison.Only SS[11:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_13     ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm 
+                                                                       comparison. Only SS[12:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14        ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm 
+                                                                       comparison.Only SS[13:0] are compared */
+#define RTC_AlarmSubSecondMask_None        ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match 
+                                                                       to activate alarm. */
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)   (((MASK) == RTC_AlarmSubSecondMask_All) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_None))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Alarm_Sub_Seconds_Value
+  * @{
+  */ 
+
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Wakeup_Timer_Definitions 
+  * @{
+  */ 
+#define RTC_WakeUpClock_RTCCLK_Div16        ((uint32_t)0x00000000)
+#define RTC_WakeUpClock_RTCCLK_Div8         ((uint32_t)0x00000001)
+#define RTC_WakeUpClock_RTCCLK_Div4         ((uint32_t)0x00000002)
+#define RTC_WakeUpClock_RTCCLK_Div2         ((uint32_t)0x00000003)
+#define RTC_WakeUpClock_CK_SPRE_16bits      ((uint32_t)0x00000004)
+#define RTC_WakeUpClock_CK_SPRE_17bits      ((uint32_t)0x00000006)
+#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
+                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
+                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
+                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
+                                    ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
+                                    ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
+#define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= 0xFFFF)
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Time_Stamp_Edges_definitions 
+  * @{
+  */ 
+#define RTC_TimeStampEdge_Rising          ((uint32_t)0x00000000)
+#define RTC_TimeStampEdge_Falling         ((uint32_t)0x00000008)
+#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \
+                                     ((EDGE) == RTC_TimeStampEdge_Falling))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Output_selection_Definitions 
+  * @{
+  */ 
+#define RTC_Output_Disable             ((uint32_t)0x00000000)
+#define RTC_Output_AlarmA              ((uint32_t)0x00200000)
+#define RTC_Output_AlarmB              ((uint32_t)0x00400000)
+#define RTC_Output_WakeUp              ((uint32_t)0x00600000)
+ 
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
+                               ((OUTPUT) == RTC_Output_AlarmA) || \
+                               ((OUTPUT) == RTC_Output_AlarmB) || \
+                               ((OUTPUT) == RTC_Output_WakeUp))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Output_Polarity_Definitions 
+  * @{
+  */ 
+#define RTC_OutputPolarity_High           ((uint32_t)0x00000000)
+#define RTC_OutputPolarity_Low            ((uint32_t)0x00100000)
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
+                                ((POL) == RTC_OutputPolarity_Low))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_Digital_Calibration_Definitions 
+  * @{
+  */ 
+#define RTC_CalibSign_Positive            ((uint32_t)0x00000000) 
+#define RTC_CalibSign_Negative            ((uint32_t)0x00000080)
+#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \
+                                 ((SIGN) == RTC_CalibSign_Negative))
+#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
+
+/**
+  * @}
+  */ 
+
+ /** @defgroup RTC_Calib_Output_selection_Definitions 
+  * @{
+  */ 
+#define RTC_CalibOutput_512Hz            ((uint32_t)0x00000000) 
+#define RTC_CalibOutput_1Hz              ((uint32_t)0x00080000)
+#define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CalibOutput_512Hz) || \
+                                      ((OUTPUT) == RTC_CalibOutput_1Hz))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Smooth_calib_period_Definitions 
+  * @{
+  */ 
+#define RTC_SmoothCalibPeriod_32sec   ((uint32_t)0x00000000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation
+                                                             period is 32s,  else 2exp20 RTCCLK seconds */
+#define RTC_SmoothCalibPeriod_16sec   ((uint32_t)0x00002000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation 
+                                                             period is 16s, else 2exp19 RTCCLK seconds */
+#define RTC_SmoothCalibPeriod_8sec    ((uint32_t)0x00004000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation 
+                                                             period is 8s, else 2exp18 RTCCLK seconds */
+#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
+                                             ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
+                                             ((PERIOD) == RTC_SmoothCalibPeriod_8sec))
+                                          
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions 
+  * @{
+  */ 
+#define RTC_SmoothCalibPlusPulses_Set    ((uint32_t)0x00008000) /*!<  The number of RTCCLK pulses added  
+                                                                during a X -second window = Y - CALM[8:0]. 
+                                                                 with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define RTC_SmoothCalibPlusPulses_Reset  ((uint32_t)0x00000000) /*!<  The number of RTCCLK pulses subbstited
+                                                                 during a 32-second window =   CALM[8:0]. */
+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
+                                         ((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions 
+  * @{
+  */ 
+#define  IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_DayLightSaving_Definitions 
+  * @{
+  */ 
+#define RTC_DayLightSaving_SUB1H   ((uint32_t)0x00020000)
+#define RTC_DayLightSaving_ADD1H   ((uint32_t)0x00010000)
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \
+                                      ((SAVE) == RTC_DayLightSaving_ADD1H))
+
+#define RTC_StoreOperation_Reset        ((uint32_t)0x00000000)
+#define RTC_StoreOperation_Set          ((uint32_t)0x00040000)
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
+                                           ((OPERATION) == RTC_StoreOperation_Set))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Tamper_Trigger_Definitions 
+  * @{
+  */ 
+#define RTC_TamperTrigger_RisingEdge            ((uint32_t)0x00000000)
+#define RTC_TamperTrigger_FallingEdge           ((uint32_t)0x00000001)
+#define RTC_TamperTrigger_LowLevel              ((uint32_t)0x00000000)
+#define RTC_TamperTrigger_HighLevel             ((uint32_t)0x00000001)
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
+                                        ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
+                                        ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
+                                        ((TRIGGER) == RTC_TamperTrigger_HighLevel)) 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Tamper_Filter_Definitions 
+  * @{
+  */ 
+#define RTC_TamperFilter_Disable   ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
+
+#define RTC_TamperFilter_2Sample   ((uint32_t)0x00000800) /*!< Tamper is activated after 2 
+                                                          consecutive samples at the active level */
+#define RTC_TamperFilter_4Sample   ((uint32_t)0x00001000) /*!< Tamper is activated after 4 
+                                                          consecutive samples at the active level */
+#define RTC_TamperFilter_8Sample   ((uint32_t)0x00001800) /*!< Tamper is activated after 8 
+                                                          consecutive samples at the active leve. */
+#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
+                                      ((FILTER) == RTC_TamperFilter_2Sample) || \
+                                      ((FILTER) == RTC_TamperFilter_4Sample) || \
+                                      ((FILTER) == RTC_TamperFilter_8Sample))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions 
+  * @{
+  */ 
+#define RTC_TamperSamplingFreq_RTCCLK_Div32768  ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 32768 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div16384  ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled
+                                                                            with a frequency =  RTCCLK / 16384 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div8192   ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 8192  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div4096   ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 4096  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div2048   ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 2048  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div1024   ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 1024  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div512    ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 512   */
+#define RTC_TamperSamplingFreq_RTCCLK_Div256    ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 256   */
+#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
+
+/**
+  * @}
+  */
+
+  /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions 
+  * @{
+  */ 
+#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 1 RTCCLK cycle */
+#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 2 RTCCLK cycles */
+#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 4 RTCCLK cycles */
+#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 8 RTCCLK cycles */
+
+#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
+                                                    ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
+                                                    ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
+                                                    ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Tamper_Pins_Definitions 
+  * @{
+  */ 
+#define RTC_Tamper_1                    RTC_TAFCR_TAMP1E
+#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1))
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Tamper_Pin_Selection 
+  * @{
+  */ 
+#define RTC_TamperPin_PC13                 ((uint32_t)0x00000000)
+#define RTC_TamperPin_PI8                  ((uint32_t)0x00010000)
+#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_PC13) || \
+                                ((PIN) == RTC_TamperPin_PI8))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_TimeStamp_Pin_Selection 
+  * @{
+  */ 
+#define RTC_TimeStampPin_PC13              ((uint32_t)0x00000000)
+#define RTC_TimeStampPin_PI8               ((uint32_t)0x00020000)
+#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) || \
+                                   ((PIN) == RTC_TimeStampPin_PI8))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Output_Type_ALARM_OUT 
+  * @{
+  */ 
+#define RTC_OutputType_OpenDrain           ((uint32_t)0x00000000)
+#define RTC_OutputType_PushPull            ((uint32_t)0x00040000)
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \
+                                  ((TYPE) == RTC_OutputType_PushPull))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Add_1_Second_Parameter_Definitions
+  * @{
+  */ 
+#define RTC_ShiftAdd1S_Reset      ((uint32_t)0x00000000)
+#define RTC_ShiftAdd1S_Set        ((uint32_t)0x80000000)
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \
+                                 ((SEL) == RTC_ShiftAdd1S_Set))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Substract_Fraction_Of_Second_Value
+  * @{
+  */ 
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Backup_Registers_Definitions 
+  * @{
+  */
+
+#define RTC_BKP_DR0                       ((uint32_t)0x00000000)
+#define RTC_BKP_DR1                       ((uint32_t)0x00000001)
+#define RTC_BKP_DR2                       ((uint32_t)0x00000002)
+#define RTC_BKP_DR3                       ((uint32_t)0x00000003)
+#define RTC_BKP_DR4                       ((uint32_t)0x00000004)
+#define RTC_BKP_DR5                       ((uint32_t)0x00000005)
+#define RTC_BKP_DR6                       ((uint32_t)0x00000006)
+#define RTC_BKP_DR7                       ((uint32_t)0x00000007)
+#define RTC_BKP_DR8                       ((uint32_t)0x00000008)
+#define RTC_BKP_DR9                       ((uint32_t)0x00000009)
+#define RTC_BKP_DR10                      ((uint32_t)0x0000000A)
+#define RTC_BKP_DR11                      ((uint32_t)0x0000000B)
+#define RTC_BKP_DR12                      ((uint32_t)0x0000000C)
+#define RTC_BKP_DR13                      ((uint32_t)0x0000000D)
+#define RTC_BKP_DR14                      ((uint32_t)0x0000000E)
+#define RTC_BKP_DR15                      ((uint32_t)0x0000000F)
+#define RTC_BKP_DR16                      ((uint32_t)0x00000010)
+#define RTC_BKP_DR17                      ((uint32_t)0x00000011)
+#define RTC_BKP_DR18                      ((uint32_t)0x00000012)
+#define RTC_BKP_DR19                      ((uint32_t)0x00000013)
+#define IS_RTC_BKP(BKP)                   (((BKP) == RTC_BKP_DR0) || \
+                                           ((BKP) == RTC_BKP_DR1) || \
+                                           ((BKP) == RTC_BKP_DR2) || \
+                                           ((BKP) == RTC_BKP_DR3) || \
+                                           ((BKP) == RTC_BKP_DR4) || \
+                                           ((BKP) == RTC_BKP_DR5) || \
+                                           ((BKP) == RTC_BKP_DR6) || \
+                                           ((BKP) == RTC_BKP_DR7) || \
+                                           ((BKP) == RTC_BKP_DR8) || \
+                                           ((BKP) == RTC_BKP_DR9) || \
+                                           ((BKP) == RTC_BKP_DR10) || \
+                                           ((BKP) == RTC_BKP_DR11) || \
+                                           ((BKP) == RTC_BKP_DR12) || \
+                                           ((BKP) == RTC_BKP_DR13) || \
+                                           ((BKP) == RTC_BKP_DR14) || \
+                                           ((BKP) == RTC_BKP_DR15) || \
+                                           ((BKP) == RTC_BKP_DR16) || \
+                                           ((BKP) == RTC_BKP_DR17) || \
+                                           ((BKP) == RTC_BKP_DR18) || \
+                                           ((BKP) == RTC_BKP_DR19))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Input_parameter_format_definitions 
+  * @{
+  */ 
+#define RTC_Format_BIN                    ((uint32_t)0x000000000)
+#define RTC_Format_BCD                    ((uint32_t)0x000000001)
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Flags_Definitions 
+  * @{
+  */ 
+#define RTC_FLAG_RECALPF                  ((uint32_t)0x00010000)
+#define RTC_FLAG_TAMP1F                   ((uint32_t)0x00002000)
+#define RTC_FLAG_TSOVF                    ((uint32_t)0x00001000)
+#define RTC_FLAG_TSF                      ((uint32_t)0x00000800)
+#define RTC_FLAG_WUTF                     ((uint32_t)0x00000400)
+#define RTC_FLAG_ALRBF                    ((uint32_t)0x00000200)
+#define RTC_FLAG_ALRAF                    ((uint32_t)0x00000100)
+#define RTC_FLAG_INITF                    ((uint32_t)0x00000040)
+#define RTC_FLAG_RSF                      ((uint32_t)0x00000020)
+#define RTC_FLAG_INITS                    ((uint32_t)0x00000010)
+#define RTC_FLAG_SHPF                     ((uint32_t)0x00000008)
+#define RTC_FLAG_WUTWF                    ((uint32_t)0x00000004)
+#define RTC_FLAG_ALRBWF                   ((uint32_t)0x00000002)
+#define RTC_FLAG_ALRAWF                   ((uint32_t)0x00000001)
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \
+                               ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \
+                               ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \
+                               ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
+                               ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
+                               ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_RECALPF) || \
+                                ((FLAG) == RTC_FLAG_SHPF))
+#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Interrupts_Definitions 
+  * @{
+  */ 
+#define RTC_IT_TS                         ((uint32_t)0x00008000)
+#define RTC_IT_WUT                        ((uint32_t)0x00004000)
+#define RTC_IT_ALRB                       ((uint32_t)0x00002000)
+#define RTC_IT_ALRA                       ((uint32_t)0x00001000)
+#define RTC_IT_TAMP                       ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
+#define RTC_IT_TAMP1                      ((uint32_t)0x00020000)
+
+#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
+#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \
+                           ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \
+                           ((IT) == RTC_IT_TAMP1))
+#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Legacy 
+  * @{
+  */ 
+#define RTC_DigitalCalibConfig  RTC_CoarseCalibConfig
+#define RTC_DigitalCalibCmd     RTC_CoarseCalibCmd
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/*  Function used to set the RTC configuration to the default reset state *****/
+ErrorStatus RTC_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
+void RTC_WriteProtectionCmd(FunctionalState NewState);
+ErrorStatus RTC_EnterInitMode(void);
+void RTC_ExitInitMode(void);
+ErrorStatus RTC_WaitForSynchro(void);
+ErrorStatus RTC_RefClockCmd(FunctionalState NewState);
+void RTC_BypassShadowCmd(FunctionalState NewState);
+
+/* Time and Date configuration functions **************************************/
+ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
+uint32_t RTC_GetSubSecond(void);
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
+
+/* Alarms (Alarm A and Alarm B) configuration functions  **********************/
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
+ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);
+void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
+
+/* WakeUp Timer configuration functions ***************************************/
+void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock);
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);
+uint32_t RTC_GetWakeUpCounter(void);
+ErrorStatus RTC_WakeUpCmd(FunctionalState NewState);
+
+/* Daylight Saving configuration functions ************************************/
+void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
+uint32_t RTC_GetStoreOperation(void);
+
+/* Output pin Configuration function ******************************************/
+void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
+
+/* Digital Calibration configuration functions *********************************/
+ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value);
+ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState);
+void RTC_CalibOutputCmd(FunctionalState NewState);
+void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);
+ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, 
+                                  uint32_t RTC_SmoothCalibPlusPulses,
+                                  uint32_t RTC_SmouthCalibMinusPulsesValue);
+
+/* TimeStamp configuration functions ******************************************/
+void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,
+                                      RTC_DateTypeDef* RTC_StampDateStruct);
+uint32_t RTC_GetTimeStampSubSecond(void);
+
+/* Tampers configuration functions ********************************************/
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
+void RTC_TamperPullUpCmd(FunctionalState NewState);
+
+/* Backup Data Registers configuration functions ******************************/
+void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);
+uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);
+
+/* RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration
+   functions ******************************************************************/
+void RTC_TamperPinSelection(uint32_t RTC_TamperPin);
+void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin);
+void RTC_OutputTypeConfig(uint32_t RTC_OutputType);
+
+/* RTC_Shift_control_synchonisation_functions *********************************/
+ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
+
+/* Interrupts and flags management functions **********************************/
+void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
+void RTC_ClearFlag(uint32_t RTC_FLAG);
+ITStatus RTC_GetITStatus(uint32_t RTC_IT);
+void RTC_ClearITPendingBit(uint32_t RTC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__HARDWARE_RTC_H__ */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/hardware_sdio.h

@@ -0,0 +1,549 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_sdio.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    30-September-2011
+  * @brief   This file contains all the functions prototypes for the SDIO firmware
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/**
+* @file: hardware_sdio.h
+* @brief: define hardware sdio function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/*************************************************
+File name: hardware_sdio.h
+Description: define hardware sdio function
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_sdio.h for XiZi
+*************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HARDWARE_SDIO_H__
+#define __HARDWARE_SDIO_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stm32f4xx.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup SDIO
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+typedef struct
+{
+  uint32_t SDIO_ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
+                                           This parameter can be a value of @ref SDIO_Clock_Edge */
+
+  uint32_t SDIO_ClockBypass;          /*!< Specifies whether the SDIO Clock divider bypass is
+                                           enabled or disabled.
+                                           This parameter can be a value of @ref SDIO_Clock_Bypass */
+
+  uint32_t SDIO_ClockPowerSave;       /*!< Specifies whether SDIO Clock output is enabled or
+                                           disabled when the bus is idle.
+                                           This parameter can be a value of @ref SDIO_Clock_Power_Save */
+
+  uint32_t SDIO_BusWide;              /*!< Specifies the SDIO bus width.
+                                           This parameter can be a value of @ref SDIO_Bus_Wide */
+
+  uint32_t SDIO_HardwareFlowControl;  /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
+                                           This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
+
+  uint8_t SDIO_ClockDiv;              /*!< Specifies the clock frequency of the SDIO controller.
+                                           This parameter can be a value between 0x00 and 0xFF. */
+                                           
+} SDIO_InitTypeDef;
+
+typedef struct
+{
+  uint32_t SDIO_Argument;  /*!< Specifies the SDIO command argument which is sent
+                                to a card as part of a command message. If a command
+                                contains an argument, it must be loaded into this register
+                                before writing the command to the command register */
+
+  uint32_t SDIO_CmdIndex;  /*!< Specifies the SDIO command index. It must be lower than 0x40. */
+
+  uint32_t SDIO_Response;  /*!< Specifies the SDIO response type.
+                                This parameter can be a value of @ref SDIO_Response_Type */
+
+  uint32_t SDIO_Wait;      /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
+                                This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
+
+  uint32_t SDIO_CPSM;      /*!< Specifies whether SDIO Command path state machine (CPSM)
+                                is enabled or disabled.
+                                This parameter can be a value of @ref SDIO_CPSM_State */
+} SDIO_CmdInitTypeDef;
+
+typedef struct
+{
+  uint32_t SDIO_DataTimeOut;    /*!< Specifies the data timeout period in card bus clock periods. */
+
+  uint32_t SDIO_DataLength;     /*!< Specifies the number of data bytes to be transferred. */
+ 
+  uint32_t SDIO_DataBlockSize;  /*!< Specifies the data block size for block transfer.
+                                     This parameter can be a value of @ref SDIO_Data_Block_Size */
+ 
+  uint32_t SDIO_TransferDir;    /*!< Specifies the data transfer direction, whether the transfer
+                                     is a read or write.
+                                     This parameter can be a value of @ref SDIO_Transfer_Direction */
+ 
+  uint32_t SDIO_TransferMode;   /*!< Specifies whether data transfer is in stream or block mode.
+                                     This parameter can be a value of @ref SDIO_Transfer_Type */
+ 
+  uint32_t SDIO_DPSM;           /*!< Specifies whether SDIO Data path state machine (DPSM)
+                                     is enabled or disabled.
+                                     This parameter can be a value of @ref SDIO_DPSM_State */
+} SDIO_DataInitTypeDef;
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SDIO_Exported_Constants
+  * @{
+  */
+
+/** @defgroup SDIO_Clock_Edge 
+  * @{
+  */
+
+#define SDIO_ClockEdge_Rising               ((uint32_t)0x00000000)
+#define SDIO_ClockEdge_Falling              ((uint32_t)0x00002000)
+#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
+                                  ((EDGE) == SDIO_ClockEdge_Falling))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Clock_Bypass 
+  * @{
+  */
+
+#define SDIO_ClockBypass_Disable             ((uint32_t)0x00000000)
+#define SDIO_ClockBypass_Enable              ((uint32_t)0x00000400)    
+#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
+                                     ((BYPASS) == SDIO_ClockBypass_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup SDIO_Clock_Power_Save 
+  * @{
+  */
+
+#define SDIO_ClockPowerSave_Disable         ((uint32_t)0x00000000)
+#define SDIO_ClockPowerSave_Enable          ((uint32_t)0x00000200) 
+#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
+                                        ((SAVE) == SDIO_ClockPowerSave_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Bus_Wide 
+  * @{
+  */
+
+#define SDIO_BusWide_1b                     ((uint32_t)0x00000000)
+#define SDIO_BusWide_4b                     ((uint32_t)0x00000800)
+#define SDIO_BusWide_8b                     ((uint32_t)0x00001000)
+#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
+                                ((WIDE) == SDIO_BusWide_8b))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Hardware_Flow_Control 
+  * @{
+  */
+
+#define SDIO_HardwareFlowControl_Disable    ((uint32_t)0x00000000)
+#define SDIO_HardwareFlowControl_Enable     ((uint32_t)0x00004000)
+#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
+                                                ((CONTROL) == SDIO_HardwareFlowControl_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Power_State 
+  * @{
+  */
+
+#define SDIO_PowerState_OFF                 ((uint32_t)0x00000000)
+#define SDIO_PowerState_ON                  ((uint32_t)0x00000003)
+#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup SDIO_Interrupt_sources
+  * @{
+  */
+
+#define SDIO_IT_CCRCFAIL                    ((uint32_t)0x00000001)
+#define SDIO_IT_DCRCFAIL                    ((uint32_t)0x00000002)
+#define SDIO_IT_CTIMEOUT                    ((uint32_t)0x00000004)
+#define SDIO_IT_DTIMEOUT                    ((uint32_t)0x00000008)
+#define SDIO_IT_TXUNDERR                    ((uint32_t)0x00000010)
+#define SDIO_IT_RXOVERR                     ((uint32_t)0x00000020)
+#define SDIO_IT_CMDREND                     ((uint32_t)0x00000040)
+#define SDIO_IT_CMDSENT                     ((uint32_t)0x00000080)
+#define SDIO_IT_DATAEND                     ((uint32_t)0x00000100)
+#define SDIO_IT_STBITERR                    ((uint32_t)0x00000200)
+#define SDIO_IT_DBCKEND                     ((uint32_t)0x00000400)
+#define SDIO_IT_CMDACT                      ((uint32_t)0x00000800)
+#define SDIO_IT_TXACT                       ((uint32_t)0x00001000)
+#define SDIO_IT_RXACT                       ((uint32_t)0x00002000)
+#define SDIO_IT_TXFIFOHE                    ((uint32_t)0x00004000)
+#define SDIO_IT_RXFIFOHF                    ((uint32_t)0x00008000)
+#define SDIO_IT_TXFIFOF                     ((uint32_t)0x00010000)
+#define SDIO_IT_RXFIFOF                     ((uint32_t)0x00020000)
+#define SDIO_IT_TXFIFOE                     ((uint32_t)0x00040000)
+#define SDIO_IT_RXFIFOE                     ((uint32_t)0x00080000)
+#define SDIO_IT_TXDAVL                      ((uint32_t)0x00100000)
+#define SDIO_IT_RXDAVL                      ((uint32_t)0x00200000)
+#define SDIO_IT_SDIOIT                      ((uint32_t)0x00400000)
+#define SDIO_IT_CEATAEND                    ((uint32_t)0x00800000)
+#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
+/**
+  * @}
+  */ 
+
+/** @defgroup SDIO_Command_Index
+  * @{
+  */
+
+#define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40)
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Response_Type
+  * @{
+  */
+
+#define SDIO_Response_No                    ((uint32_t)0x00000000)
+#define SDIO_Response_Short                 ((uint32_t)0x00000040)
+#define SDIO_Response_Long                  ((uint32_t)0x000000C0)
+#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
+                                    ((RESPONSE) == SDIO_Response_Short) || \
+                                    ((RESPONSE) == SDIO_Response_Long))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Wait_Interrupt_State
+  * @{
+  */
+
+#define SDIO_Wait_No                        ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
+#define SDIO_Wait_IT                        ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
+#define SDIO_Wait_Pend                      ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
+#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
+                            ((WAIT) == SDIO_Wait_Pend))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_CPSM_State
+  * @{
+  */
+
+#define SDIO_CPSM_Disable                    ((uint32_t)0x00000000)
+#define SDIO_CPSM_Enable                     ((uint32_t)0x00000400)
+#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup SDIO_Response_Registers
+  * @{
+  */
+
+#define SDIO_RESP1                          ((uint32_t)0x00000000)
+#define SDIO_RESP2                          ((uint32_t)0x00000004)
+#define SDIO_RESP3                          ((uint32_t)0x00000008)
+#define SDIO_RESP4                          ((uint32_t)0x0000000C)
+#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
+                            ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Data_Length 
+  * @{
+  */
+
+#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Data_Block_Size 
+  * @{
+  */
+
+#define SDIO_DataBlockSize_1b               ((uint32_t)0x00000000)
+#define SDIO_DataBlockSize_2b               ((uint32_t)0x00000010)
+#define SDIO_DataBlockSize_4b               ((uint32_t)0x00000020)
+#define SDIO_DataBlockSize_8b               ((uint32_t)0x00000030)
+#define SDIO_DataBlockSize_16b              ((uint32_t)0x00000040)
+#define SDIO_DataBlockSize_32b              ((uint32_t)0x00000050)
+#define SDIO_DataBlockSize_64b              ((uint32_t)0x00000060)
+#define SDIO_DataBlockSize_128b             ((uint32_t)0x00000070)
+#define SDIO_DataBlockSize_256b             ((uint32_t)0x00000080)
+#define SDIO_DataBlockSize_512b             ((uint32_t)0x00000090)
+#define SDIO_DataBlockSize_1024b            ((uint32_t)0x000000A0)
+#define SDIO_DataBlockSize_2048b            ((uint32_t)0x000000B0)
+#define SDIO_DataBlockSize_4096b            ((uint32_t)0x000000C0)
+#define SDIO_DataBlockSize_8192b            ((uint32_t)0x000000D0)
+#define SDIO_DataBlockSize_16384b           ((uint32_t)0x000000E0)
+#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_2b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_4b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_8b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_16b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_32b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_64b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_128b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_256b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_512b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_1024b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_2048b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_4096b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_8192b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_16384b)) 
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Transfer_Direction 
+  * @{
+  */
+
+#define SDIO_TransferDir_ToCard             ((uint32_t)0x00000000)
+#define SDIO_TransferDir_ToSDIO             ((uint32_t)0x00000002)
+#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
+                                   ((DIR) == SDIO_TransferDir_ToSDIO))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Transfer_Type 
+  * @{
+  */
+
+#define SDIO_TransferMode_Block             ((uint32_t)0x00000000)
+#define SDIO_TransferMode_Stream            ((uint32_t)0x00000004)
+#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
+                                     ((MODE) == SDIO_TransferMode_Block))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_DPSM_State 
+  * @{
+  */
+
+#define SDIO_DPSM_Disable                    ((uint32_t)0x00000000)
+#define SDIO_DPSM_Enable                     ((uint32_t)0x00000001)
+#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Flags 
+  * @{
+  */
+
+#define SDIO_FLAG_CCRCFAIL                  ((uint32_t)0x00000001)
+#define SDIO_FLAG_DCRCFAIL                  ((uint32_t)0x00000002)
+#define SDIO_FLAG_CTIMEOUT                  ((uint32_t)0x00000004)
+#define SDIO_FLAG_DTIMEOUT                  ((uint32_t)0x00000008)
+#define SDIO_FLAG_TXUNDERR                  ((uint32_t)0x00000010)
+#define SDIO_FLAG_RXOVERR                   ((uint32_t)0x00000020)
+#define SDIO_FLAG_CMDREND                   ((uint32_t)0x00000040)
+#define SDIO_FLAG_CMDSENT                   ((uint32_t)0x00000080)
+#define SDIO_FLAG_DATAEND                   ((uint32_t)0x00000100)
+#define SDIO_FLAG_STBITERR                  ((uint32_t)0x00000200)
+#define SDIO_FLAG_DBCKEND                   ((uint32_t)0x00000400)
+#define SDIO_FLAG_CMDACT                    ((uint32_t)0x00000800)
+#define SDIO_FLAG_TXACT                     ((uint32_t)0x00001000)
+#define SDIO_FLAG_RXACT                     ((uint32_t)0x00002000)
+#define SDIO_FLAG_TXFIFOHE                  ((uint32_t)0x00004000)
+#define SDIO_FLAG_RXFIFOHF                  ((uint32_t)0x00008000)
+#define SDIO_FLAG_TXFIFOF                   ((uint32_t)0x00010000)
+#define SDIO_FLAG_RXFIFOF                   ((uint32_t)0x00020000)
+#define SDIO_FLAG_TXFIFOE                   ((uint32_t)0x00040000)
+#define SDIO_FLAG_RXFIFOE                   ((uint32_t)0x00080000)
+#define SDIO_FLAG_TXDAVL                    ((uint32_t)0x00100000)
+#define SDIO_FLAG_RXDAVL                    ((uint32_t)0x00200000)
+#define SDIO_FLAG_SDIOIT                    ((uint32_t)0x00400000)
+#define SDIO_FLAG_CEATAEND                  ((uint32_t)0x00800000)
+#define IS_SDIO_FLAG(FLAG) (((FLAG)  == SDIO_FLAG_CCRCFAIL) || \
+                            ((FLAG)  == SDIO_FLAG_DCRCFAIL) || \
+                            ((FLAG)  == SDIO_FLAG_CTIMEOUT) || \
+                            ((FLAG)  == SDIO_FLAG_DTIMEOUT) || \
+                            ((FLAG)  == SDIO_FLAG_TXUNDERR) || \
+                            ((FLAG)  == SDIO_FLAG_RXOVERR) || \
+                            ((FLAG)  == SDIO_FLAG_CMDREND) || \
+                            ((FLAG)  == SDIO_FLAG_CMDSENT) || \
+                            ((FLAG)  == SDIO_FLAG_DATAEND) || \
+                            ((FLAG)  == SDIO_FLAG_STBITERR) || \
+                            ((FLAG)  == SDIO_FLAG_DBCKEND) || \
+                            ((FLAG)  == SDIO_FLAG_CMDACT) || \
+                            ((FLAG)  == SDIO_FLAG_TXACT) || \
+                            ((FLAG)  == SDIO_FLAG_RXACT) || \
+                            ((FLAG)  == SDIO_FLAG_TXFIFOHE) || \
+                            ((FLAG)  == SDIO_FLAG_RXFIFOHF) || \
+                            ((FLAG)  == SDIO_FLAG_TXFIFOF) || \
+                            ((FLAG)  == SDIO_FLAG_RXFIFOF) || \
+                            ((FLAG)  == SDIO_FLAG_TXFIFOE) || \
+                            ((FLAG)  == SDIO_FLAG_RXFIFOE) || \
+                            ((FLAG)  == SDIO_FLAG_TXDAVL) || \
+                            ((FLAG)  == SDIO_FLAG_RXDAVL) || \
+                            ((FLAG)  == SDIO_FLAG_SDIOIT) || \
+                            ((FLAG)  == SDIO_FLAG_CEATAEND))
+
+#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
+
+#define IS_SDIO_GET_IT(IT) (((IT)  == SDIO_IT_CCRCFAIL) || \
+                            ((IT)  == SDIO_IT_DCRCFAIL) || \
+                            ((IT)  == SDIO_IT_CTIMEOUT) || \
+                            ((IT)  == SDIO_IT_DTIMEOUT) || \
+                            ((IT)  == SDIO_IT_TXUNDERR) || \
+                            ((IT)  == SDIO_IT_RXOVERR) || \
+                            ((IT)  == SDIO_IT_CMDREND) || \
+                            ((IT)  == SDIO_IT_CMDSENT) || \
+                            ((IT)  == SDIO_IT_DATAEND) || \
+                            ((IT)  == SDIO_IT_STBITERR) || \
+                            ((IT)  == SDIO_IT_DBCKEND) || \
+                            ((IT)  == SDIO_IT_CMDACT) || \
+                            ((IT)  == SDIO_IT_TXACT) || \
+                            ((IT)  == SDIO_IT_RXACT) || \
+                            ((IT)  == SDIO_IT_TXFIFOHE) || \
+                            ((IT)  == SDIO_IT_RXFIFOHF) || \
+                            ((IT)  == SDIO_IT_TXFIFOF) || \
+                            ((IT)  == SDIO_IT_RXFIFOF) || \
+                            ((IT)  == SDIO_IT_TXFIFOE) || \
+                            ((IT)  == SDIO_IT_RXFIFOE) || \
+                            ((IT)  == SDIO_IT_TXDAVL) || \
+                            ((IT)  == SDIO_IT_RXDAVL) || \
+                            ((IT)  == SDIO_IT_SDIOIT) || \
+                            ((IT)  == SDIO_IT_CEATAEND))
+
+#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Read_Wait_Mode 
+  * @{
+  */
+
+#define SDIO_ReadWaitMode_CLK               ((uint32_t)0x00000000)
+#define SDIO_ReadWaitMode_DATA2             ((uint32_t)0x00000001)
+#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
+                                     ((MODE) == SDIO_ReadWaitMode_DATA2))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/*  Function used to set the SDIO configuration to the default reset state ****/
+void SDIO_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_ClockCmd(FunctionalState NewState);
+void SDIO_SetPowerState(uint32_t SDIO_PowerState);
+uint32_t SDIO_GetPowerState(void);
+
+/* Command path state machine (CPSM) management functions *********************/
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
+uint8_t SDIO_GetCommandResponse(void);
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
+
+/* Data path state machine (DPSM) management functions ************************/
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+uint32_t SDIO_GetDataCounter(void);
+uint32_t SDIO_ReadData(void);
+void SDIO_WriteData(uint32_t Data);
+uint32_t SDIO_GetFIFOCount(void);
+
+/* SDIO IO Cards mode management functions ************************************/
+void SDIO_StartSDIOReadWait(FunctionalState NewState);
+void SDIO_StopSDIOReadWait(FunctionalState NewState);
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
+void SDIO_SetSDIOOperation(FunctionalState NewState);
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
+
+/* CE-ATA mode management functions *******************************************/
+void SDIO_CommandCompletionCmd(FunctionalState NewState);
+void SDIO_CEATAITCmd(FunctionalState NewState);
+void SDIO_SendCEATACmd(FunctionalState NewState);
+
+/* DMA transfers management functions *****************************************/
+void SDIO_DMACmd(FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
+void SDIO_ClearFlag(uint32_t SDIO_FLAG);
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HARDWARE_SDIO_H__ */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/hardware_spi.h

@@ -0,0 +1,556 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_spi.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    30-September-2011
+  * @brief   This file contains all the functions prototypes for the SPI 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+
+/**
+* @file: hardware_spi.h
+* @brief: define hardware spi function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/*************************************************
+File name: hardware_spi.h
+Description: define hardware spi function
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_spi.h for XiZi
+*************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HARDWARE_SPI_H__
+#define __HARDWARE_SPI_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stm32f4xx.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup SPI
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  SPI Init structure definition  
+  */
+
+typedef struct
+{
+  uint16_t SPI_Direction;           /*!< Specifies the SPI unidirectional or bidirectional data mode.
+                                         This parameter can be a value of @ref SPI_data_direction */
+
+  uint16_t SPI_Mode;                /*!< Specifies the SPI operating mode.
+                                         This parameter can be a value of @ref SPI_mode */
+
+  uint16_t SPI_DataSize;            /*!< Specifies the SPI data size.
+                                         This parameter can be a value of @ref SPI_data_size */
+
+  uint16_t SPI_CPOL;                /*!< Specifies the serial clock steady state.
+                                         This parameter can be a value of @ref SPI_Clock_Polarity */
+
+  uint16_t SPI_CPHA;                /*!< Specifies the clock active edge for the bit capture.
+                                         This parameter can be a value of @ref SPI_Clock_Phase */
+
+  uint16_t SPI_NSS;                 /*!< Specifies whether the NSS signal is managed by
+                                         hardware (NSS pin) or by software using the SSI bit.
+                                         This parameter can be a value of @ref SPI_Slave_Select_management */
+ 
+  uint16_t SPI_BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
+                                         used to configure the transmit and receive SCK clock.
+                                         This parameter can be a value of @ref SPI_BaudRate_Prescaler
+                                         @note The communication clock is derived from the master
+                                               clock. The slave clock does not need to be set. */
+
+  uint16_t SPI_FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                         This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+  uint16_t SPI_CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation. */
+}SPI_InitTypeDef;
+
+/** 
+  * @brief  I2S Init structure definition  
+  */
+
+typedef struct
+{
+
+  uint16_t I2S_Mode;         /*!< Specifies the I2S operating mode.
+                                  This parameter can be a value of @ref I2S_Mode */
+
+  uint16_t I2S_Standard;     /*!< Specifies the standard used for the I2S communication.
+                                  This parameter can be a value of @ref I2S_Standard */
+
+  uint16_t I2S_DataFormat;   /*!< Specifies the data format for the I2S communication.
+                                  This parameter can be a value of @ref I2S_Data_Format */
+
+  uint16_t I2S_MCLKOutput;   /*!< Specifies whether the I2S MCLK output is enabled or not.
+                                  This parameter can be a value of @ref I2S_MCLK_Output */
+
+  uint32_t I2S_AudioFreq;    /*!< Specifies the frequency selected for the I2S communication.
+                                  This parameter can be a value of @ref I2S_Audio_Frequency */
+
+  uint16_t I2S_CPOL;         /*!< Specifies the idle state of the I2S clock.
+                                  This parameter can be a value of @ref I2S_Clock_Polarity */
+}I2S_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SPI_Exported_Constants
+  * @{
+  */
+
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
+                                   ((PERIPH) == SPI2) || \
+                                   ((PERIPH) == SPI3))
+
+#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \
+                                       ((PERIPH) == SPI2) || \
+                                       ((PERIPH) == SPI3) || \
+                                       ((PERIPH) == I2S2ext) || \
+                                       ((PERIPH) == I2S3ext))
+
+#define IS_SPI_23_PERIPH(PERIPH)  (((PERIPH) == SPI2) || \
+                                   ((PERIPH) == SPI3))
+
+#define IS_SPI_23_PERIPH_EXT(PERIPH)  (((PERIPH) == SPI2) || \
+                                       ((PERIPH) == SPI3) || \
+                                       ((PERIPH) == I2S2ext) || \
+                                       ((PERIPH) == I2S3ext))
+
+#define IS_I2S_EXT_PERIPH(PERIPH)  (((PERIPH) == I2S2ext) || \
+                                    ((PERIPH) == I2S3ext))
+
+
+/** @defgroup SPI_data_direction 
+  * @{
+  */
+  
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
+#define SPI_Direction_2Lines_RxOnly     ((uint16_t)0x0400)
+#define SPI_Direction_1Line_Rx          ((uint16_t)0x8000)
+#define SPI_Direction_1Line_Tx          ((uint16_t)0xC000)
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
+                                     ((MODE) == SPI_Direction_2Lines_RxOnly) || \
+                                     ((MODE) == SPI_Direction_1Line_Rx) || \
+                                     ((MODE) == SPI_Direction_1Line_Tx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_mode 
+  * @{
+  */
+
+#define SPI_Mode_Master                 ((uint16_t)0x0104)
+#define SPI_Mode_Slave                  ((uint16_t)0x0000)
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
+                           ((MODE) == SPI_Mode_Slave))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_data_size 
+  * @{
+  */
+
+#define SPI_DataSize_16b                ((uint16_t)0x0800)
+#define SPI_DataSize_8b                 ((uint16_t)0x0000)
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
+                                   ((DATASIZE) == SPI_DataSize_8b))
+/**
+  * @}
+  */ 
+
+/** @defgroup SPI_Clock_Polarity 
+  * @{
+  */
+
+#define SPI_CPOL_Low                    ((uint16_t)0x0000)
+#define SPI_CPOL_High                   ((uint16_t)0x0002)
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
+                           ((CPOL) == SPI_CPOL_High))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Phase 
+  * @{
+  */
+
+#define SPI_CPHA_1Edge                  ((uint16_t)0x0000)
+#define SPI_CPHA_2Edge                  ((uint16_t)0x0001)
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
+                           ((CPHA) == SPI_CPHA_2Edge))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Slave_Select_management 
+  * @{
+  */
+
+#define SPI_NSS_Soft                    ((uint16_t)0x0200)
+#define SPI_NSS_Hard                    ((uint16_t)0x0000)
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
+                         ((NSS) == SPI_NSS_Hard))
+/**
+  * @}
+  */ 
+
+/** @defgroup SPI_BaudRate_Prescaler 
+  * @{
+  */
+
+#define SPI_BaudRatePrescaler_2         ((uint16_t)0x0000)
+#define SPI_BaudRatePrescaler_4         ((uint16_t)0x0008)
+#define SPI_BaudRatePrescaler_8         ((uint16_t)0x0010)
+#define SPI_BaudRatePrescaler_16        ((uint16_t)0x0018)
+#define SPI_BaudRatePrescaler_32        ((uint16_t)0x0020)
+#define SPI_BaudRatePrescaler_64        ((uint16_t)0x0028)
+#define SPI_BaudRatePrescaler_128       ((uint16_t)0x0030)
+#define SPI_BaudRatePrescaler_256       ((uint16_t)0x0038)
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_256))
+/**
+  * @}
+  */ 
+
+/** @defgroup SPI_MSB_LSB_transmission 
+  * @{
+  */
+
+#define SPI_FirstBit_MSB                ((uint16_t)0x0000)
+#define SPI_FirstBit_LSB                ((uint16_t)0x0080)
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
+                               ((BIT) == SPI_FirstBit_LSB))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_Mode 
+  * @{
+  */
+
+#define I2S_Mode_SlaveTx                ((uint16_t)0x0000)
+#define I2S_Mode_SlaveRx                ((uint16_t)0x0100)
+#define I2S_Mode_MasterTx               ((uint16_t)0x0200)
+#define I2S_Mode_MasterRx               ((uint16_t)0x0300)
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
+                           ((MODE) == I2S_Mode_SlaveRx) || \
+                           ((MODE) == I2S_Mode_MasterTx)|| \
+                           ((MODE) == I2S_Mode_MasterRx))
+/**
+  * @}
+  */
+  
+
+/** @defgroup SPI_I2S_Standard 
+  * @{
+  */
+
+#define I2S_Standard_Phillips           ((uint16_t)0x0000)
+#define I2S_Standard_MSB                ((uint16_t)0x0010)
+#define I2S_Standard_LSB                ((uint16_t)0x0020)
+#define I2S_Standard_PCMShort           ((uint16_t)0x0030)
+#define I2S_Standard_PCMLong            ((uint16_t)0x00B0)
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
+                                   ((STANDARD) == I2S_Standard_MSB) || \
+                                   ((STANDARD) == I2S_Standard_LSB) || \
+                                   ((STANDARD) == I2S_Standard_PCMShort) || \
+                                   ((STANDARD) == I2S_Standard_PCMLong))
+/**
+  * @}
+  */
+  
+/** @defgroup SPI_I2S_Data_Format 
+  * @{
+  */
+
+#define I2S_DataFormat_16b              ((uint16_t)0x0000)
+#define I2S_DataFormat_16bextended      ((uint16_t)0x0001)
+#define I2S_DataFormat_24b              ((uint16_t)0x0003)
+#define I2S_DataFormat_32b              ((uint16_t)0x0005)
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
+                                    ((FORMAT) == I2S_DataFormat_16bextended) || \
+                                    ((FORMAT) == I2S_DataFormat_24b) || \
+                                    ((FORMAT) == I2S_DataFormat_32b))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_MCLK_Output 
+  * @{
+  */
+
+#define I2S_MCLKOutput_Enable           ((uint16_t)0x0200)
+#define I2S_MCLKOutput_Disable          ((uint16_t)0x0000)
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
+                                    ((OUTPUT) == I2S_MCLKOutput_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_Audio_Frequency 
+  * @{
+  */
+
+#define I2S_AudioFreq_192k               ((uint32_t)192000)
+#define I2S_AudioFreq_96k                ((uint32_t)96000)
+#define I2S_AudioFreq_48k                ((uint32_t)48000)
+#define I2S_AudioFreq_44k                ((uint32_t)44100)
+#define I2S_AudioFreq_32k                ((uint32_t)32000)
+#define I2S_AudioFreq_22k                ((uint32_t)22050)
+#define I2S_AudioFreq_16k                ((uint32_t)16000)
+#define I2S_AudioFreq_11k                ((uint32_t)11025)
+#define I2S_AudioFreq_8k                 ((uint32_t)8000)
+#define I2S_AudioFreq_Default            ((uint32_t)2)
+
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
+                                 ((FREQ) <= I2S_AudioFreq_192k)) || \
+                                 ((FREQ) == I2S_AudioFreq_Default))
+/**
+  * @}
+  */
+            
+/** @defgroup SPI_I2S_Clock_Polarity 
+  * @{
+  */
+
+#define I2S_CPOL_Low                    ((uint16_t)0x0000)
+#define I2S_CPOL_High                   ((uint16_t)0x0008)
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
+                           ((CPOL) == I2S_CPOL_High))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_DMA_transfer_requests 
+  * @{
+  */
+
+#define SPI_I2S_DMAReq_Tx               ((uint16_t)0x0002)
+#define SPI_I2S_DMAReq_Rx               ((uint16_t)0x0001)
+#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_NSS_internal_software_management 
+  * @{
+  */
+
+#define SPI_NSSInternalSoft_Set         ((uint16_t)0x0100)
+#define SPI_NSSInternalSoft_Reset       ((uint16_t)0xFEFF)
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
+                                       ((INTERNAL) == SPI_NSSInternalSoft_Reset))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_Transmit_Receive 
+  * @{
+  */
+
+#define SPI_CRC_Tx                      ((uint8_t)0x00)
+#define SPI_CRC_Rx                      ((uint8_t)0x01)
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_direction_transmit_receive 
+  * @{
+  */
+
+#define SPI_Direction_Rx                ((uint16_t)0xBFFF)
+#define SPI_Direction_Tx                ((uint16_t)0x4000)
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
+                                     ((DIRECTION) == SPI_Direction_Tx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_interrupts_definition 
+  * @{
+  */
+
+#define SPI_I2S_IT_TXE                  ((uint8_t)0x71)
+#define SPI_I2S_IT_RXNE                 ((uint8_t)0x60)
+#define SPI_I2S_IT_ERR                  ((uint8_t)0x50)
+#define I2S_IT_UDR                      ((uint8_t)0x53)
+#define SPI_I2S_IT_TIFRFE               ((uint8_t)0x58)
+
+#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
+                                  ((IT) == SPI_I2S_IT_RXNE) || \
+                                  ((IT) == SPI_I2S_IT_ERR))
+
+#define SPI_I2S_IT_OVR                  ((uint8_t)0x56)
+#define SPI_IT_MODF                     ((uint8_t)0x55)
+#define SPI_IT_CRCERR                   ((uint8_t)0x54)
+
+#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
+
+#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \
+                               ((IT) == SPI_IT_CRCERR)  || ((IT) == SPI_IT_MODF) || \
+                               ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\
+                               ((IT) == SPI_I2S_IT_TIFRFE))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_flags_definition 
+  * @{
+  */
+
+#define SPI_I2S_FLAG_RXNE               ((uint16_t)0x0001)
+#define SPI_I2S_FLAG_TXE                ((uint16_t)0x0002)
+#define I2S_FLAG_CHSIDE                 ((uint16_t)0x0004)
+#define I2S_FLAG_UDR                    ((uint16_t)0x0008)
+#define SPI_FLAG_CRCERR                 ((uint16_t)0x0010)
+#define SPI_FLAG_MODF                   ((uint16_t)0x0020)
+#define SPI_I2S_FLAG_OVR                ((uint16_t)0x0040)
+#define SPI_I2S_FLAG_BSY                ((uint16_t)0x0080)
+#define SPI_I2S_FLAG_TIFRFE             ((uint16_t)0x0100)
+
+#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
+#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
+                                   ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
+                                   ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
+                                   ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
+                                   ((FLAG) == SPI_I2S_FLAG_TIFRFE))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_polynomial 
+  * @{
+  */
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_Legacy 
+  * @{
+  */
+
+#define SPI_DMAReq_Tx                SPI_I2S_DMAReq_Tx
+#define SPI_DMAReq_Rx                SPI_I2S_DMAReq_Rx
+#define SPI_IT_TXE                   SPI_I2S_IT_TXE
+#define SPI_IT_RXNE                  SPI_I2S_IT_RXNE
+#define SPI_IT_ERR                   SPI_I2S_IT_ERR
+#define SPI_IT_OVR                   SPI_I2S_IT_OVR
+#define SPI_FLAG_RXNE                SPI_I2S_FLAG_RXNE
+#define SPI_FLAG_TXE                 SPI_I2S_FLAG_TXE
+#define SPI_FLAG_OVR                 SPI_I2S_FLAG_OVR
+#define SPI_FLAG_BSY                 SPI_I2S_FLAG_BSY
+#define SPI_DeInit                   SPI_I2S_DeInit
+#define SPI_ITConfig                 SPI_I2S_ITConfig
+#define SPI_DMACmd                   SPI_I2S_DMACmd
+#define SPI_SendData                 SPI_I2S_SendData
+#define SPI_ReceiveData              SPI_I2S_ReceiveData
+#define SPI_GetFlagStatus            SPI_I2S_GetFlagStatus
+#define SPI_ClearFlag                SPI_I2S_ClearFlag
+#define SPI_GetITStatus              SPI_I2S_GetITStatus
+#define SPI_ClearITPendingBit        SPI_I2S_ClearITPendingBit
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/*  Function used to set the SPI configuration to the default reset state *****/ 
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
+
+/* Initialization and Configuration functions *********************************/
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+
+void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct);
+
+/* Data transfers functions ***************************************************/ 
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
+
+/* Hardware CRC Calculation functions *****************************************/
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
+
+/* DMA transfers management functions *****************************************/
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__HARDWARE_SPI_H__ */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/hardware_syscfg.h

@@ -0,0 +1,192 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_syscfg.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    30-September-2011
+  * @brief   This file contains all the functions prototypes for the SYSCFG firmware
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/**
+* @file: hardware_syscfg.h
+* @brief: define hardware syscfg function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/*************************************************
+File name: hardware_syscfg.h
+Description: define hardware syscfg function
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_syscfg.h for XiZi
+*************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HARDWARE_SYSCFG_H__
+#define __HARDWARE_SYSCFG_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stm32f4xx.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup SYSCFG
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+  
+/** @defgroup SYSCFG_Exported_Constants 
+  * @{
+  */ 
+
+/** @defgroup SYSCFG_EXTI_Port_Sources 
+  * @{
+  */ 
+#define EXTI_PortSourceGPIOA       ((uint8_t)0x00)
+#define EXTI_PortSourceGPIOB       ((uint8_t)0x01)
+#define EXTI_PortSourceGPIOC       ((uint8_t)0x02)
+#define EXTI_PortSourceGPIOD       ((uint8_t)0x03)
+#define EXTI_PortSourceGPIOE       ((uint8_t)0x04)
+#define EXTI_PortSourceGPIOF       ((uint8_t)0x05)
+#define EXTI_PortSourceGPIOG       ((uint8_t)0x06)
+#define EXTI_PortSourceGPIOH       ((uint8_t)0x07)
+#define EXTI_PortSourceGPIOI       ((uint8_t)0x08)
+                                      
+#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
+                                        ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
+                                        ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
+                                        ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
+                                        ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
+                                        ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \
+                                        ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \
+                                        ((PORTSOURCE) == EXTI_PortSourceGPIOH) || \
+                                        ((PORTSOURCE) == EXTI_PortSourceGPIOI)) 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup SYSCFG_EXTI_Pin_Sources 
+  * @{
+  */ 
+#define EXTI_PinSource0            ((uint8_t)0x00)
+#define EXTI_PinSource1            ((uint8_t)0x01)
+#define EXTI_PinSource2            ((uint8_t)0x02)
+#define EXTI_PinSource3            ((uint8_t)0x03)
+#define EXTI_PinSource4            ((uint8_t)0x04)
+#define EXTI_PinSource5            ((uint8_t)0x05)
+#define EXTI_PinSource6            ((uint8_t)0x06)
+#define EXTI_PinSource7            ((uint8_t)0x07)
+#define EXTI_PinSource8            ((uint8_t)0x08)
+#define EXTI_PinSource9            ((uint8_t)0x09)
+#define EXTI_PinSource10           ((uint8_t)0x0A)
+#define EXTI_PinSource11           ((uint8_t)0x0B)
+#define EXTI_PinSource12           ((uint8_t)0x0C)
+#define EXTI_PinSource13           ((uint8_t)0x0D)
+#define EXTI_PinSource14           ((uint8_t)0x0E)
+#define EXTI_PinSource15           ((uint8_t)0x0F)
+#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
+                                       ((PINSOURCE) == EXTI_PinSource1) || \
+                                       ((PINSOURCE) == EXTI_PinSource2) || \
+                                       ((PINSOURCE) == EXTI_PinSource3) || \
+                                       ((PINSOURCE) == EXTI_PinSource4) || \
+                                       ((PINSOURCE) == EXTI_PinSource5) || \
+                                       ((PINSOURCE) == EXTI_PinSource6) || \
+                                       ((PINSOURCE) == EXTI_PinSource7) || \
+                                       ((PINSOURCE) == EXTI_PinSource8) || \
+                                       ((PINSOURCE) == EXTI_PinSource9) || \
+                                       ((PINSOURCE) == EXTI_PinSource10) || \
+                                       ((PINSOURCE) == EXTI_PinSource11) || \
+                                       ((PINSOURCE) == EXTI_PinSource12) || \
+                                       ((PINSOURCE) == EXTI_PinSource13) || \
+                                       ((PINSOURCE) == EXTI_PinSource14) || \
+                                       ((PINSOURCE) == EXTI_PinSource15))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup SYSCFG_Memory_Remap_Config 
+  * @{
+  */ 
+#define SYSCFG_MemoryRemap_Flash       ((uint8_t)0x00)
+#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)
+#define SYSCFG_MemoryRemap_FSMC        ((uint8_t)0x02)
+#define SYSCFG_MemoryRemap_SRAM        ((uint8_t)0x03)
+   
+#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
+                                                     ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
+                                                     ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \
+                                                     ((REMAP) == SYSCFG_MemoryRemap_FSMC))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup SYSCFG_ETHERNET_Media_Interface 
+  * @{
+  */ 
+#define SYSCFG_ETH_MediaInterface_MII    ((uint32_t)0x00000000) 
+#define SYSCFG_ETH_MediaInterface_RMII   ((uint32_t)0x00000001)                                       
+
+#define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \
+                                                ((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII))
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+ 
+void SYSCFG_DeInit(void);
+void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
+void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface); 
+void SYSCFG_CompensationCellCmd(FunctionalState NewState); 
+FlagStatus SYSCFG_GetCompensationCellStatus(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__HARDWARE_SYSCFG_H__ */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/hardware_usart.h

@@ -0,0 +1,442 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_usart.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    30-September-2011
+  * @brief   This file contains all the functions prototypes for the USART 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+
+/**
+* @file: hardware_usart.h
+* @brief: define hardware usart function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/*************************************************
+File name: hardware_usart.h
+Description: define hardware usart function
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_usart.h for XiZi
+*************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HARDWARE_USART_H__
+#define __HARDWARE_USART_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stm32f4xx.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup USART
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+
+/** 
+  * @brief  USART Init Structure definition  
+  */ 
+  
+typedef struct
+{
+  uint32_t USART_BaudRate;            /*!< This member configures the USART communication baud rate.
+                                           The baud rate is computed using the following formula:
+                                            - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate)))
+                                            - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 
+                                           Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
+
+  uint16_t USART_WordLength;          /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref USART_Word_Length */
+
+  uint16_t USART_StopBits;            /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref USART_Stop_Bits */
+
+  uint16_t USART_Parity;              /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref USART_Parity
+                                           @note When parity is enabled, the computed parity is inserted
+                                                 at the MSB position of the transmitted data (9th bit when
+                                                 the word length is set to 9 data bits; 8th bit when the
+                                                 word length is set to 8 data bits). */
+ 
+  uint16_t USART_Mode;                /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_Mode */
+
+  uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
+                                           or disabled.
+                                           This parameter can be a value of @ref USART_Hardware_Flow_Control */
+} USART_InitTypeDef;
+
+/** 
+  * @brief  USART Clock Init Structure definition  
+  */ 
+  
+typedef struct
+{
+
+  uint16_t USART_Clock;   /*!< Specifies whether the USART clock is enabled or disabled.
+                               This parameter can be a value of @ref USART_Clock */
+
+  uint16_t USART_CPOL;    /*!< Specifies the steady state of the serial clock.
+                               This parameter can be a value of @ref USART_Clock_Polarity */
+
+  uint16_t USART_CPHA;    /*!< Specifies the clock transition on which the bit capture is made.
+                               This parameter can be a value of @ref USART_Clock_Phase */
+
+  uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                               data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                               This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup USART_Exported_Constants
+  * @{
+  */ 
+  
+#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+                                     ((PERIPH) == USART2) || \
+                                     ((PERIPH) == USART3) || \
+                                     ((PERIPH) == UART4)  || \
+                                     ((PERIPH) == UART5)  || \
+                                     ((PERIPH) == USART6))
+
+#define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+                                      ((PERIPH) == USART2) || \
+                                      ((PERIPH) == USART3) || \
+                                      ((PERIPH) == USART6))
+
+/** @defgroup USART_Word_Length 
+  * @{
+  */ 
+  
+#define USART_WordLength_8b                  ((uint16_t)0x0000)
+#define USART_WordLength_9b                  ((uint16_t)0x1000)
+                                    
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
+                                      ((LENGTH) == USART_WordLength_9b))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Stop_Bits 
+  * @{
+  */ 
+  
+#define USART_StopBits_1                     ((uint16_t)0x0000)
+#define USART_StopBits_0_5                   ((uint16_t)0x1000)
+#define USART_StopBits_2                     ((uint16_t)0x2000)
+#define USART_StopBits_1_5                   ((uint16_t)0x3000)
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
+                                     ((STOPBITS) == USART_StopBits_0_5) || \
+                                     ((STOPBITS) == USART_StopBits_2) || \
+                                     ((STOPBITS) == USART_StopBits_1_5))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Parity 
+  * @{
+  */ 
+  
+#define USART_Parity_No                      ((uint16_t)0x0000)
+#define USART_Parity_Even                    ((uint16_t)0x0400)
+#define USART_Parity_Odd                     ((uint16_t)0x0600) 
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
+                                 ((PARITY) == USART_Parity_Even) || \
+                                 ((PARITY) == USART_Parity_Odd))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Mode 
+  * @{
+  */ 
+  
+#define USART_Mode_Rx                        ((uint16_t)0x0004)
+#define USART_Mode_Tx                        ((uint16_t)0x0008)
+#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Hardware_Flow_Control 
+  * @{
+  */ 
+#define USART_HardwareFlowControl_None       ((uint16_t)0x0000)
+#define USART_HardwareFlowControl_RTS        ((uint16_t)0x0100)
+#define USART_HardwareFlowControl_CTS        ((uint16_t)0x0200)
+#define USART_HardwareFlowControl_RTS_CTS    ((uint16_t)0x0300)
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
+                              (((CONTROL) == USART_HardwareFlowControl_None) || \
+                               ((CONTROL) == USART_HardwareFlowControl_RTS) || \
+                               ((CONTROL) == USART_HardwareFlowControl_CTS) || \
+                               ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Clock 
+  * @{
+  */ 
+#define USART_Clock_Disable                  ((uint16_t)0x0000)
+#define USART_Clock_Enable                   ((uint16_t)0x0800)
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
+                               ((CLOCK) == USART_Clock_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Clock_Polarity 
+  * @{
+  */
+  
+#define USART_CPOL_Low                       ((uint16_t)0x0000)
+#define USART_CPOL_High                      ((uint16_t)0x0400)
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Clock_Phase
+  * @{
+  */
+
+#define USART_CPHA_1Edge                     ((uint16_t)0x0000)
+#define USART_CPHA_2Edge                     ((uint16_t)0x0200)
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Last_Bit
+  * @{
+  */
+
+#define USART_LastBit_Disable                ((uint16_t)0x0000)
+#define USART_LastBit_Enable                 ((uint16_t)0x0100)
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
+                                   ((LASTBIT) == USART_LastBit_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Interrupt_definition 
+  * @{
+  */
+  
+#define USART_IT_PE                          ((uint16_t)0x0028)
+#define USART_IT_TXE                         ((uint16_t)0x0727)
+#define USART_IT_TC                          ((uint16_t)0x0626)
+#define USART_IT_RXNE                        ((uint16_t)0x0525)
+#define USART_IT_ORE_RX                      ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */
+#define USART_IT_IDLE                        ((uint16_t)0x0424)
+#define USART_IT_LBD                         ((uint16_t)0x0846)
+#define USART_IT_CTS                         ((uint16_t)0x096A)
+#define USART_IT_ERR                         ((uint16_t)0x0060)
+#define USART_IT_ORE_ER                      ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */
+#define USART_IT_NE                          ((uint16_t)0x0260)
+#define USART_IT_FE                          ((uint16_t)0x0160)
+
+/** @defgroup USART_Legacy 
+  * @{
+  */
+#define USART_IT_ORE                          USART_IT_ORE_ER               
+/**
+  * @}
+  */
+
+#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+                                ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+                                ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+                                ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
+#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+                             ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+                             ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+                             ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
+                             ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \
+                             ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+                               ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
+/**
+  * @}
+  */
+
+/** @defgroup USART_DMA_Requests 
+  * @{
+  */
+
+#define USART_DMAReq_Tx                      ((uint16_t)0x0080)
+#define USART_DMAReq_Rx                      ((uint16_t)0x0040)
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_WakeUp_methods
+  * @{
+  */
+
+#define USART_WakeUp_IdleLine                ((uint16_t)0x0000)
+#define USART_WakeUp_AddressMark             ((uint16_t)0x0800)
+#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
+                                 ((WAKEUP) == USART_WakeUp_AddressMark))
+/**
+  * @}
+  */
+
+/** @defgroup USART_LIN_Break_Detection_Length 
+  * @{
+  */
+  
+#define USART_LINBreakDetectLength_10b      ((uint16_t)0x0000)
+#define USART_LINBreakDetectLength_11b      ((uint16_t)0x0020)
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
+                               (((LENGTH) == USART_LINBreakDetectLength_10b) || \
+                                ((LENGTH) == USART_LINBreakDetectLength_11b))
+/**
+  * @}
+  */
+
+/** @defgroup USART_IrDA_Low_Power 
+  * @{
+  */
+
+#define USART_IrDAMode_LowPower              ((uint16_t)0x0004)
+#define USART_IrDAMode_Normal                ((uint16_t)0x0000)
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
+                                  ((MODE) == USART_IrDAMode_Normal))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Flags 
+  * @{
+  */
+
+#define USART_FLAG_CTS                       ((uint16_t)0x0200)
+#define USART_FLAG_LBD                       ((uint16_t)0x0100)
+#define USART_FLAG_TXE                       ((uint16_t)0x0080)
+#define USART_FLAG_TC                        ((uint16_t)0x0040)
+#define USART_FLAG_RXNE                      ((uint16_t)0x0020)
+#define USART_FLAG_IDLE                      ((uint16_t)0x0010)
+#define USART_FLAG_ORE                       ((uint16_t)0x0008)
+#define USART_FLAG_NE                        ((uint16_t)0x0004)
+#define USART_FLAG_FE                        ((uint16_t)0x0002)
+#define USART_FLAG_PE                        ((uint16_t)0x0001)
+#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
+                             ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
+                             ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
+                             ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
+                             ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
+                              
+#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 7500001))
+#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/  
+
+/*  Function used to set the USART configuration to the default reset state ***/ 
+void USART_DeInit(USART_TypeDef* USARTx);
+
+/* Initialization and Configuration functions *********************************/
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* Data transfers functions ***************************************************/ 
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
+
+/* Multi-Processor Communication functions ************************************/
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* LIN mode functions *********************************************************/
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SendBreak(USART_TypeDef* USARTx);
+
+/* Half-duplex mode function **************************************************/
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* Smartcard mode functions ***************************************************/
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
+
+/* IrDA mode functions ********************************************************/
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* DMA transfers management functions *****************************************/
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HARDWARE_USART_H__ */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/hardware_wwdg.h

@@ -0,0 +1,124 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_wwdg.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    30-September-2011
+  * @brief   This file contains all the functions prototypes for the WWDG firmware
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/**
+* @file: hardware_wwdg.h
+* @brief: define hardware wwdg function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/*************************************************
+File name: hardware_wwdg.h
+Description: define hardware wwdg function
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32f4xx_wwdg.h for XiZi
+*************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HARDWARE_WWDG_H__
+#define __HARDWARE_WWDG_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stm32f4xx.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup WWDG
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Constants
+  * @{
+  */ 
+  
+/** @defgroup WWDG_Prescaler 
+  * @{
+  */
+  
+#define WWDG_Prescaler_1    ((uint32_t)0x00000000)
+#define WWDG_Prescaler_2    ((uint32_t)0x00000080)
+#define WWDG_Prescaler_4    ((uint32_t)0x00000100)
+#define WWDG_Prescaler_8    ((uint32_t)0x00000180)
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
+                                      ((PRESCALER) == WWDG_Prescaler_2) || \
+                                      ((PRESCALER) == WWDG_Prescaler_4) || \
+                                      ((PRESCALER) == WWDG_Prescaler_8))
+#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+  
+/*  Function used to set the WWDG configuration to the default reset state ****/  
+void WWDG_DeInit(void);
+
+/* Prescaler, Refresh window and Counter configuration functions **************/
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
+void WWDG_SetWindowValue(uint8_t WindowValue);
+void WWDG_EnableIT(void);
+void WWDG_SetCounter(uint8_t Counter);
+
+/* WWDG activation function ***************************************************/
+void WWDG_Enable(uint8_t Counter);
+
+/* Interrupts and flags management functions **********************************/
+FlagStatus WWDG_GetFlagStatus(void);
+void WWDG_ClearFlag(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HARDWARE_WWDG_H__ */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/misc.h

@@ -0,0 +1,180 @@
+/**
+  ******************************************************************************
+  * @file    misc.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    30-September-2011
+  * @brief   This file contains all the functions prototypes for the miscellaneous
+  *          firmware library functions (add-on to CMSIS functions).
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/**
+* @file: misc.h
+* @brief: define misc function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MISC_H__
+#define __MISC_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stm32f4xx.h>
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup MISC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  NVIC Init Structure definition  
+  */
+
+typedef struct
+{
+  uint8_t NVIC_IRQChannel;                    /*!< Specifies the IRQ channel to be enabled or disabled.
+                                                   This parameter can be an enumerator of @ref IRQn_Type 
+                                                   enumeration (For the complete STM32 Devices IRQ Channels
+                                                   list, please refer to stm32f4xx.h file) */
+
+  uint8_t NVIC_IRQChannelPreemptionPriority;  /*!< Specifies the pre-emption priority for the IRQ channel
+                                                   specified in NVIC_IRQChannel. This parameter can be a value
+                                                   between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
+                                                   A lower priority value indicates a higher priority */
+
+  uint8_t NVIC_IRQChannelSubPriority;         /*!< Specifies the subpriority level for the IRQ channel specified
+                                                   in NVIC_IRQChannel. This parameter can be a value
+                                                   between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
+                                                   A lower priority value indicates a higher priority */
+
+  FunctionalState NVIC_IRQChannelCmd;         /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+                                                   will be enabled or disabled. 
+                                                   This parameter can be set either to ENABLE or DISABLE */   
+} NVIC_InitTypeDef;
+ 
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup MISC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup MISC_Vector_Table_Base 
+  * @{
+  */
+
+#define NVIC_VectTab_RAM             ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH           ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
+                                  ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+  * @}
+  */
+
+/** @defgroup MISC_System_Low_Power 
+  * @{
+  */
+
+#define NVIC_LP_SEVONPEND            ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
+                        ((LP) == NVIC_LP_SLEEPDEEP) || \
+                        ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Preemption_Priority_Group 
+  * @{
+  */
+
+#define NVIC_PriorityGroup_0         ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
+                                                            4 bits for subpriority */
+#define NVIC_PriorityGroup_1         ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
+                                                            3 bits for subpriority */
+#define NVIC_PriorityGroup_2         ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
+                                                            2 bits for subpriority */
+#define NVIC_PriorityGroup_3         ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
+                                                            1 bits for subpriority */
+#define NVIC_PriorityGroup_4         ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
+                                                            0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
+                                       ((GROUP) == NVIC_PriorityGroup_1) || \
+                                       ((GROUP) == NVIC_PriorityGroup_2) || \
+                                       ((GROUP) == NVIC_PriorityGroup_3) || \
+                                       ((GROUP) == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET)  ((OFFSET) < 0x000FFFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_SysTick_clock_source 
+  * @{
+  */
+
+#define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
+                                       ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MISC_H__ */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/include/stm32_assert_template.h

@@ -0,0 +1,92 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @author  MCD Application Team
+  * @brief   STM32 CHECK template file.
+  *          This file should be copied to the application folder and renamed
+  *          to stm32_assert.h.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/**
+* @file: stm32_assert_template.h
+* @brief: define hardware assert function
+* @version: 1.0
+* @author:  AIIT XUOS Lab
+* @date:    2021/4/25
+*/
+
+/*************************************************
+File name: stm32_assert_template.h
+Description: define hardware assert function
+Others: 
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. rename stm32_assert.h for XiZi
+*************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_TEMPLATE_H__
+#define __STM32_ASSERT_TEMPLATE_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_TEMPLATE_H__ */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/lcd/Kconfig

@@ -0,0 +1,17 @@
+if BSP_USING_LCD
+    config LCD_BUS_NAME
+        string "lcd bus name"
+        default "lcd"
+    config LCD_DRV_NAME
+        string "lcd bus driver name"
+        default "lcd_drv"
+    config LCD_DEVICE_NAME
+        string "lcd bus device name"
+        default "lcd_dev"   
+    config BSP_LCD_X_MAX
+        int "LCD Height"
+        default 240
+    config BSP_LCD_Y_MAX
+        int "LCD Width"
+        default 320
+endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/lcd/Makefile

@@ -0,0 +1,4 @@
+SRC_FILES := connect_lcd.c
+
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/lcd/connect_lcd.c

@@ -0,0 +1,657 @@
+/*
+ * Copyright (c) Guangzhou Xingyi Electronic Technology Co., Ltd
+ *
+ * Change Logs:
+ * Date          Author     Notes
+ * 2014-7-4      alientek   first version
+ */
+
+/**
+* @file connect_lcd.c
+* @brief support aiit-arm32-board lcd function and register to bus framework
+* @version 2.0 
+* @author AIIT XUOS Lab
+* @date 2022-1-12
+*/
+
+/*************************************************
+File name: connect_lcd.c
+Description: support aiit-arm32-board lcd configure and lcd bus register function
+Others: take hardware/lcd/lcd.c for references
+History: 
+1. Date: 2022-1-12
+Author: AIIT XUOS Lab
+Modification: 
+1. support aiit-arm32-board lcd configure, write by FSMC function
+2. support aiit-arm32-board lcd bus device and driver register
+*************************************************/
+
+#include <connect_lcd.h>
+#include <connect_gpio.h>
+#include <hardware_fsmc.h>
+#include <hardware_gpio.h>
+#include <hardware_rcc.h>
+
+static int Stm32LcdUdelay(uint32 us)
+{
+    uint32 ticks;
+    uint32 told, tnow, tcnt = 0;
+    uint32 reload = SysTick->LOAD;
+
+    ticks = us * reload / (1000000 / TICK_PER_SECOND);
+    told = SysTick->VAL;
+    while (1) {
+        tnow = SysTick->VAL;
+        if (tnow != told) {
+            if (tnow < told) {
+                tcnt += told - tnow;
+            } else {
+                tcnt += reload - tnow + told;
+            }
+            told = tnow;
+            if (tcnt >= ticks) {
+                return 0;
+                break;
+            }
+        }
+    }
+}
+
+static void HwFsmcInit()
+{
+    GPIO_InitTypeDef GPIO_InitStructure;
+    FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
+    FSMC_NORSRAMTimingInitTypeDef readWriteTiming; 
+    FSMC_NORSRAMTimingInitTypeDef writeTiming;
+
+    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD|RCC_AHB1Periph_GPIOE|RCC_AHB1Periph_GPIOF|RCC_AHB1Periph_GPIOG, ENABLE); 
+    RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); 
+
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;//PD3, LCD back light
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+	GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+	GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+    GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
+    GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+    GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+    GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
+    GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+    GPIO_Init(GPIOE, &GPIO_InitStructure);
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;//PF12, FSMC_A6
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+    GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
+    GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+    GPIO_Init(GPIOF, &GPIO_InitStructure);
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;//PG12, FSMC_NE4
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+    GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
+    GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+    GPIO_Init(GPIOG, &GPIO_InitStructure);
+
+    GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FSMC);//PD0,AF12
+    GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FSMC);//PD1,AF12
+    GPIO_PinAFConfig(GPIOD, GPIO_PinSource4, GPIO_AF_FSMC);//PD4,AF12
+    GPIO_PinAFConfig(GPIOD, GPIO_PinSource5, GPIO_AF_FSMC);//PD5,AF12
+    GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FSMC);//PD8,AF12 
+    GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FSMC);//PD9,AF12
+    GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FSMC);//PD10,AF12
+    GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FSMC);//PD14,AF12
+    GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FSMC);//PD15,AF12
+
+    GPIO_PinAFConfig(GPIOE, GPIO_PinSource7, GPIO_AF_FSMC);//PE7,AF12
+    GPIO_PinAFConfig(GPIOE, GPIO_PinSource8, GPIO_AF_FSMC);//PE8,AF12
+    GPIO_PinAFConfig(GPIOE, GPIO_PinSource9, GPIO_AF_FSMC);//PE9,AF12
+    GPIO_PinAFConfig(GPIOE, GPIO_PinSource10, GPIO_AF_FSMC);//PE10,AF12
+    GPIO_PinAFConfig(GPIOE, GPIO_PinSource11, GPIO_AF_FSMC);//PE11,AF12
+    GPIO_PinAFConfig(GPIOE, GPIO_PinSource12, GPIO_AF_FSMC);//PE12,AF12
+    GPIO_PinAFConfig(GPIOE, GPIO_PinSource13, GPIO_AF_FSMC);//PE13,AF12
+    GPIO_PinAFConfig(GPIOE, GPIO_PinSource14, GPIO_AF_FSMC);//PE14,AF12
+    GPIO_PinAFConfig(GPIOE, GPIO_PinSource15, GPIO_AF_FSMC);//PE15,AF12
+
+    GPIO_PinAFConfig(GPIOF, GPIO_PinSource12, GPIO_AF_FSMC);//PF12,AF12
+    GPIO_PinAFConfig(GPIOG, GPIO_PinSource12, GPIO_AF_FSMC);//PG12,AF12
+
+    readWriteTiming.FSMC_AddressSetupTime = 0xF;//16 HCLK 1/168M=6ns*16=96ns	
+    readWriteTiming.FSMC_AddressHoldTime = 0x00;	
+    readWriteTiming.FSMC_DataSetupTime = 60;//60 HCLK 6*60=360ns
+    readWriteTiming.FSMC_BusTurnAroundDuration = 0x00;
+    readWriteTiming.FSMC_CLKDivision = 0x00;
+    readWriteTiming.FSMC_DataLatency = 0x00;
+    readWriteTiming.FSMC_AccessMode = FSMC_AccessMode_A;//mode A
+
+    writeTiming.FSMC_AddressSetupTime = 9;//9 HCLK =54ns 
+    writeTiming.FSMC_AddressHoldTime = 0x00;		
+    writeTiming.FSMC_DataSetupTime = 8;//9 HCLK=54ns
+    writeTiming.FSMC_BusTurnAroundDuration = 0x00;
+    writeTiming.FSMC_CLKDivision = 0x00;
+    writeTiming.FSMC_DataLatency = 0x00;
+    writeTiming.FSMC_AccessMode = FSMC_AccessMode_A;//mode A 
+
+    FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM4;//FSMC_NE4, register BTCR[6],[7]。
+    FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+    FSMC_NORSRAMInitStructure.FSMC_MemoryType =FSMC_MemoryType_SRAM;   
+    FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;//data bit width 16bit   
+    FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode =FSMC_BurstAccessMode_Disable; 
+    FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+    FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait=FSMC_AsynchronousWait_Disable; 
+    FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;   
+    FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;  
+    FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+    FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;   
+    FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Enable;
+    FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; 
+    FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &readWriteTiming;
+    FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &writeTiming;
+
+    FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);//init FSMC init
+
+    FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE);//enable BANK1 
+}
+
+static void LcdWriteCmd(LCD_TypeDef *LCD, uint16_t cmd)
+{
+	LCD->LCD_REG_CMD = cmd;
+}
+
+static void LcdWriteData(LCD_TypeDef *LCD, uint16_t data)
+{
+	LCD->LCD_RAM_DATA = data;
+}
+
+static void LcdWriteReg(LCD_TypeDef *LCD, uint16_t cmd, uint16_t data)
+{
+	LCD->LCD_REG_CMD = cmd;
+    LCD->LCD_RAM_DATA = data;
+}
+
+static uint16_t LcdReadData(LCD_TypeDef *LCD)
+{
+	uint16_t data;
+    data = LCD->LCD_RAM_DATA;
+    return data;
+}
+
+static uint16_t LcdReadReg(LCD_TypeDef *LCD, uint16_t cmd)
+{
+	LcdWriteCmd(LCD, cmd);
+    Stm32LcdUdelay(1000);
+    return LcdReadData(LCD);
+}
+
+static void LcdDisplayOn(LCD_TypeDef *LCD)
+{
+    LcdWriteCmd(LCD, DISPALY_ON);
+}
+
+static void LcdDisplayOff(LCD_TypeDef *LCD)
+{
+    LcdWriteCmd(LCD, DISPALY_OFF);
+}
+
+static void LcdWriteRamCmd(struct Stm32HwLcd *hw_lcd)
+{
+ 	LcdWriteCmd(hw_lcd->LCD, hw_lcd->lcd_param.write_ram_cmd);	  
+}	 
+
+static void LcdWriteRamColor(struct Stm32HwLcd *hw_lcd, uint16_t color)
+{
+ 	LcdWriteData(hw_lcd->LCD, color);	  
+}
+
+static void LcdSetCursor(struct Stm32HwLcd *hw_lcd, uint16_t x_pos, uint16_t y_pos)
+{
+    LcdWriteCmd(hw_lcd->LCD, hw_lcd->lcd_param.set_x_cmd);
+    LcdWriteData(hw_lcd->LCD, x_pos >> 8);
+    LcdWriteData(hw_lcd->LCD, x_pos & 0xFF);
+    LcdWriteCmd(hw_lcd->LCD, hw_lcd->lcd_param.set_y_cmd);
+    LcdWriteData(hw_lcd->LCD, y_pos >> 8);
+    LcdWriteData(hw_lcd->LCD, y_pos & 0xFF);
+}
+
+static void LcdDrawPoint(struct Stm32HwLcd *hw_lcd, uint16_t x, uint16_t y, uint16_t color)
+{
+    LcdSetCursor(hw_lcd, x, y);
+    LcdWriteRamCmd(hw_lcd);
+    LcdWriteRamColor(hw_lcd, color);
+}
+
+//(start_x,start_y),(end_x,end_y), area: (end_x-start_x+1)*(end_y-start_y+1)
+static void LcdDrawArea(struct Stm32HwLcd *hw_lcd, uint16_t start_x, uint16_t start_y, uint16_t end_x, uint16_t end_y, uint16_t *color)
+{
+    uint16_t height, width;
+    uint16_t i, j;
+    width = end_x - start_x + 1;
+    height = end_y - start_y + 1;
+
+    for (i = 0; i < height; i++) {
+        LcdSetCursor(hw_lcd, start_x, start_y + i);
+        LcdWriteRamCmd(hw_lcd);
+
+        for (j = 0; j < width; j++) {
+            LcdWriteRamColor(hw_lcd, color[i * width + j]);
+        }
+    }
+}
+
+//mode 0 : draw char, default configure ; 1 : draw char over background
+static void LcdDrawChar(struct Stm32HwLcd *hw_lcd, uint16_t x, uint16_t y, uint8_t char_data, uint8_t size, uint8_t mode, uint16_t color,uint16_t back_color)
+{  							  
+    uint8_t temp, t1, t;
+	uint16_t y0 = y;
+	uint8_t csize = (size / 8 + ((size % 8) ? 1 : 0)) * (size / 2);	
+ 	char_data = char_data - ' ';
+	for(t = 0;t < csize;t ++) {   
+		if(12 == size)
+            temp = asc2_1206[char_data][t];
+		else if(16 == size)
+            temp = asc2_1608[char_data][t];
+		else if(24 == size)
+            temp = asc2_2412[char_data][t];
+		else 
+            return;
+
+		for(t1 = 0;t1 < 8;t1 ++) {			    
+			if(temp & 0x80)
+                LcdDrawPoint(hw_lcd, x, y, color);
+			else if(mode == 0)
+                LcdDrawPoint(hw_lcd, x, y, back_color);
+
+			temp <<= 1;
+			y++;
+
+			if(y >= hw_lcd->lcd_param.height)
+                return;//over height
+
+			if((y - y0) == size) {
+				y = y0;
+				x++;
+				if(x >= hw_lcd->lcd_param.width)
+                    return;//over width
+				break;
+			}
+		}  	 
+	}  	    	   	 	  
+}  
+
+static void LcdDrawString(struct Stm32HwLcd *hw_lcd, uint16_t x, uint16_t y, uint16_t width, uint16_t height, uint8_t size, uint8_t *p, uint16_t color, uint16_t back_color)
+{
+    uint8_t x0 = x;
+    width += x;
+    height += y;
+
+    while ((*p <= '~') && (*p >= ' ')) {
+        if (x >= width) {
+            x = x0;
+            y += size;
+        }
+
+        if (y >= height)
+            break;
+
+        LcdDrawChar(hw_lcd, x, y, *p, size, 0, color, back_color);
+        x += size / 2;
+        p++;
+    }  
+}
+
+static void LcdClear(struct Stm32HwLcd *hw_lcd, uint16_t color)
+{
+    uint32_t dot_index = 0;
+    uint32_t totalpoint = hw_lcd->lcd_param.width * hw_lcd->lcd_param.height;
+
+    LcdSetCursor(hw_lcd, 0x00, 0x00);
+    LcdWriteRamCmd(hw_lcd);
+
+    for (dot_index = 0; dot_index < totalpoint; dot_index ++) {
+        LcdWriteRamColor(hw_lcd, color);
+    }
+}
+
+static void LcdScanDirection(struct Stm32HwLcd *hw_lcd, uint8_t scan_direction)
+{
+    uint16_t cmd = 0;
+    uint16_t temp;
+
+    switch (scan_direction) {
+        case L2R_U2D:
+            cmd |= (0 << 7) | (0 << 6) | (0 << 5);
+            break;
+        case L2R_D2U:
+            cmd |= (1 << 7) | (0 << 6) | (0 << 5);
+            break;
+        case R2L_U2D:
+            cmd |= (0 << 7) | (1 << 6) | (0 << 5);
+            break;
+        case R2L_D2U:
+            cmd |= (1 << 7) | (1 << 6) | (0 << 5);
+            break;
+        case U2D_L2R:
+            cmd |= (0 << 7) | (0 << 6) | (1 << 5);
+            break;
+        case U2D_R2L:
+            cmd |= (0 << 7) | (1 << 6) | (1 << 5);
+            break;
+        case D2U_L2R:
+            cmd |= (1 << 7) | (0 << 6) | (1 << 5);
+            break;
+        case D2U_R2L:
+            cmd |= (1 << 7) | (1 << 6) | (1 << 5);
+            break;
+    }
+
+    cmd |= 0X08;//set BGR bit
+
+    LcdWriteReg(hw_lcd->LCD, MEMORY_ACCESS_CTL, cmd);
+
+    if (cmd & INVERSION_DISPALY_OFF) {//reverse x、y
+        if (hw_lcd->lcd_param.width < hw_lcd->lcd_param.height) {
+                temp = hw_lcd->lcd_param.width;
+                hw_lcd->lcd_param.width = hw_lcd->lcd_param.height;
+                hw_lcd->lcd_param.height = temp;
+        }
+    } else {
+        if (hw_lcd->lcd_param.width > hw_lcd->lcd_param.height) {
+            temp = hw_lcd->lcd_param.width;
+            hw_lcd->lcd_param.width = hw_lcd->lcd_param.height;
+            hw_lcd->lcd_param.height = temp;
+        }
+    }
+
+    LcdWriteCmd(hw_lcd->LCD, hw_lcd->lcd_param.set_x_cmd);
+    LcdWriteData(hw_lcd->LCD, 0);
+    LcdWriteData(hw_lcd->LCD, 0);
+    LcdWriteData(hw_lcd->LCD, (hw_lcd->lcd_param.width - 1) >> 8);
+    LcdWriteData(hw_lcd->LCD, (hw_lcd->lcd_param.width - 1) & 0xFF);
+    LcdWriteCmd(hw_lcd->LCD, hw_lcd->lcd_param.set_y_cmd);
+    LcdWriteData(hw_lcd->LCD, 0);
+    LcdWriteData(hw_lcd->LCD, 0);
+    LcdWriteData(hw_lcd->LCD, (hw_lcd->lcd_param.height - 1) >> 8);
+    LcdWriteData(hw_lcd->LCD, (hw_lcd->lcd_param.height - 1) & 0xFF);
+}
+
+static void LcdDisplayDirection(struct Stm32HwLcd *hw_lcd)
+{
+    hw_lcd->lcd_param.write_ram_cmd = MEMORY_WRITE;
+    hw_lcd->lcd_param.set_x_cmd = HORIZONTAL_ADDRESS_SET;
+    hw_lcd->lcd_param.set_y_cmd = VERTICAL_ADDRESS_SET;
+
+    LcdScanDirection(hw_lcd, DFT_SCAN_DIR);
+}
+
+static void HwLcdInit(struct Stm32HwLcd *hw_lcd)
+{
+    LcdWriteCmd(hw_lcd->LCD, READ_ID4);				   
+	hw_lcd->lcd_param.lcd_id = LcdReadData(hw_lcd->LCD);//dummy read 	
+	hw_lcd->lcd_param.lcd_id = LcdReadData(hw_lcd->LCD);//0x00
+	hw_lcd->lcd_param.lcd_id = LcdReadData(hw_lcd->LCD);//93								   
+	hw_lcd->lcd_param.lcd_id <<= 8;
+	hw_lcd->lcd_param.lcd_id |= LcdReadData(hw_lcd->LCD);//41 
+
+    KPrintf("HwLcdInit lcd id 0x%x\n", hw_lcd->lcd_param.lcd_id);
+
+    if (ILI9341 == hw_lcd->lcd_param.lcd_id) {
+        FSMC_Bank1E->BWTR[6] &= ~(0xF << 0);
+		FSMC_Bank1E->BWTR[6] &= ~(0xF << 8);
+		FSMC_Bank1E->BWTR[6] |= 3 << 0;	 
+        FSMC_Bank1E->BWTR[6] |= 2 << 8;
+
+		LcdWriteCmd(hw_lcd->LCD, 0xCF);  
+		LcdWriteData(hw_lcd->LCD, 0x00); 
+		LcdWriteData(hw_lcd->LCD, 0xC1); 
+		LcdWriteData(hw_lcd->LCD, 0x30); 
+		LcdWriteCmd(hw_lcd->LCD, 0xED);  
+		LcdWriteData(hw_lcd->LCD, 0x64); 
+		LcdWriteData(hw_lcd->LCD, 0x03); 
+		LcdWriteData(hw_lcd->LCD, 0X12); 
+		LcdWriteData(hw_lcd->LCD, 0X81); 
+		LcdWriteCmd(hw_lcd->LCD, 0xE8);  
+		LcdWriteData(hw_lcd->LCD, 0x85); 
+		LcdWriteData(hw_lcd->LCD, 0x10); 
+		LcdWriteData(hw_lcd->LCD, 0x7A); 
+		LcdWriteCmd(hw_lcd->LCD, 0xCB);  
+		LcdWriteData(hw_lcd->LCD, 0x39); 
+		LcdWriteData(hw_lcd->LCD, 0x2C); 
+		LcdWriteData(hw_lcd->LCD, 0x00); 
+		LcdWriteData(hw_lcd->LCD, 0x34); 
+		LcdWriteData(hw_lcd->LCD, 0x02); 
+		LcdWriteCmd(hw_lcd->LCD, 0xF7);  
+		LcdWriteData(hw_lcd->LCD, 0x20); 
+		LcdWriteCmd(hw_lcd->LCD, 0xEA);  
+		LcdWriteData(hw_lcd->LCD, 0x00); 
+		LcdWriteData(hw_lcd->LCD, 0x00); 
+		LcdWriteCmd(hw_lcd->LCD, POWER_CTL1);//Power control 
+		LcdWriteData(hw_lcd->LCD, 0x1B);//VRH[5:0] 
+		LcdWriteCmd(hw_lcd->LCD, POWER_CTL2);//Power control 
+		LcdWriteData(hw_lcd->LCD, 0x01);//SAP[2:0];BT[3:0] 
+		LcdWriteCmd(hw_lcd->LCD, VCOM_CTL1);//VCM control 
+		LcdWriteData(hw_lcd->LCD, 0x30);
+		LcdWriteData(hw_lcd->LCD, 0x30);
+		LcdWriteCmd(hw_lcd->LCD, VCOM_CTL2);//VCM control2 
+		LcdWriteData(hw_lcd->LCD, 0xB7); 
+		LcdWriteCmd(hw_lcd->LCD, MEMORY_ACCESS_CTL);// Memory Access Control 
+		LcdWriteData(hw_lcd->LCD, 0x48); 
+		LcdWriteCmd(hw_lcd->LCD, PIXEL_FORMAT_SET);   
+		LcdWriteData(hw_lcd->LCD, 0x55); 
+		LcdWriteCmd(hw_lcd->LCD, NORMAL_FRAME_CTL);   
+		LcdWriteData(hw_lcd->LCD, 0x00);   
+		LcdWriteData(hw_lcd->LCD, 0x1A); 
+		LcdWriteCmd(hw_lcd->LCD, DISPALY_FUNCTION_CTL);// Display Function Control 
+		LcdWriteData(hw_lcd->LCD, 0x0A); 
+		LcdWriteData(hw_lcd->LCD, 0xA2); 
+		LcdWriteCmd(hw_lcd->LCD, 0xF2);// 3Gamma Function Disable 
+		LcdWriteData(hw_lcd->LCD, 0x00); 
+		LcdWriteCmd(hw_lcd->LCD, GAMMA_SET);//Gamma curve selected 
+		LcdWriteData(hw_lcd->LCD, 0x01); 
+		LcdWriteCmd(hw_lcd->LCD, POSITIVE_GAMMA_CORRECT);//Set Gamma 
+		LcdWriteData(hw_lcd->LCD, 0x0F); 
+		LcdWriteData(hw_lcd->LCD, 0x2A); 
+		LcdWriteData(hw_lcd->LCD, 0x28); 
+		LcdWriteData(hw_lcd->LCD, 0x08); 
+		LcdWriteData(hw_lcd->LCD, 0x0E); 
+		LcdWriteData(hw_lcd->LCD, 0x08); 
+		LcdWriteData(hw_lcd->LCD, 0x54); 
+		LcdWriteData(hw_lcd->LCD, 0xA9); 
+		LcdWriteData(hw_lcd->LCD, 0x43); 
+		LcdWriteData(hw_lcd->LCD, 0x0A); 
+		LcdWriteData(hw_lcd->LCD, 0x0F); 
+		LcdWriteData(hw_lcd->LCD, 0x00); 
+		LcdWriteData(hw_lcd->LCD, 0x00); 
+		LcdWriteData(hw_lcd->LCD, 0x00); 
+		LcdWriteData(hw_lcd->LCD, 0x00); 		 
+		LcdWriteCmd(hw_lcd->LCD, NEGATIVE_GAMMA_CORRECT);//Set Gamma 
+		LcdWriteData(hw_lcd->LCD, 0x00); 
+		LcdWriteData(hw_lcd->LCD, 0x15); 
+		LcdWriteData(hw_lcd->LCD, 0x17); 
+		LcdWriteData(hw_lcd->LCD, 0x07); 
+		LcdWriteData(hw_lcd->LCD, 0x11); 
+		LcdWriteData(hw_lcd->LCD, 0x06); 
+		LcdWriteData(hw_lcd->LCD, 0x2B); 
+		LcdWriteData(hw_lcd->LCD, 0x56); 
+		LcdWriteData(hw_lcd->LCD, 0x3C); 
+		LcdWriteData(hw_lcd->LCD, 0x05); 
+		LcdWriteData(hw_lcd->LCD, 0x10); 
+		LcdWriteData(hw_lcd->LCD, 0x0F); 
+		LcdWriteData(hw_lcd->LCD, 0x3F); 
+		LcdWriteData(hw_lcd->LCD, 0x3F); 
+		LcdWriteData(hw_lcd->LCD, 0x0F); 
+		LcdWriteCmd(hw_lcd->LCD, VERTICAL_ADDRESS_SET); 
+		LcdWriteData(hw_lcd->LCD, 0x00);
+		LcdWriteData(hw_lcd->LCD, 0x00);
+		LcdWriteData(hw_lcd->LCD, 0x01);
+		LcdWriteData(hw_lcd->LCD, 0x3f);
+		LcdWriteCmd(hw_lcd->LCD, HORIZONTAL_ADDRESS_SET); 
+		LcdWriteData(hw_lcd->LCD, 0x00);
+		LcdWriteData(hw_lcd->LCD, 0x00);
+		LcdWriteData(hw_lcd->LCD, 0x00);
+		LcdWriteData(hw_lcd->LCD, 0xef);	 
+		LcdWriteCmd(hw_lcd->LCD, SLEEP_OFF);//Exit Sleep
+		Stm32LcdUdelay(120000);
+		LcdWriteCmd(hw_lcd->LCD, DISPALY_ON);//display on	
+
+        LcdDisplayDirection(hw_lcd);
+        PDout(3) = 1;
+        LcdClear(hw_lcd, WHITE);
+    }
+}
+
+static uint32 LcdWrite(void *dev, struct BusBlockWriteParam *write_param)
+{
+    x_err_t ret = EOK;
+
+    struct LcdHardwareDevice *lcd_dev = (struct LcdHardwareDevice *)dev;
+    struct Stm32HwLcd *hw_lcd = (struct Stm32HwLcd *)lcd_dev->haldev.private_data;
+
+    if (write_param->buffer) {
+        LcdWriteParam *show = (LcdWriteParam *)write_param->buffer;
+    
+        //output string
+        if(0 == show->type) {
+            LcdDrawString(hw_lcd, show->string_info.x_pos, show->string_info.y_pos, show->string_info.width, show->string_info.height,
+                show->string_info.font_size, show->string_info.addr, show->string_info.font_color, show->string_info.back_color);  
+        } 
+        //output dot
+        else if (1 == show->type) {
+            LcdDrawArea(hw_lcd, show->pixel_info.x_startpos, show->pixel_info.y_startpos, show->pixel_info.x_endpos, show->pixel_info.y_endpos,
+                (uint16_t *)show->pixel_info.pixel_color);
+        } else {
+            KPrintf("LcdWrite donnot support show type(0 string; 1 dot) %u\n", show->type);
+            ret = ERROR;
+        }
+    }
+
+    return ret;
+}
+
+static uint32 LcdControl(void* drv, struct BusConfigureInfo *configure_info)
+{
+    x_err_t ret = EOK;
+
+    return ret;
+}
+
+static const struct LcdDevDone dev_done  = 
+{
+    NONE,
+    NONE,
+    LcdWrite,
+    NONE,
+};
+
+static int BoardLcdBusInit(struct LcdBus * lcd_bus, struct LcdDriver * lcd_driver,const char *bus_name, const char *drv_name)
+{
+    x_err_t ret = EOK;
+
+    /*Init the lcd bus */
+    ret = LcdBusInit( lcd_bus, bus_name);
+    if (EOK != ret) {
+        KPrintf("Board_lcd_init LcdBusInit error %d\n", ret);
+        return -ERROR;
+    }
+
+    /*Init the lcd driver*/
+    ret = LcdDriverInit( lcd_driver, drv_name);
+    if (EOK != ret) {
+        KPrintf("Board_LCD_init LcdDriverInit error %d\n", ret);
+        return -ERROR;
+    }
+
+    /*Attach the lcd driver to the lcd bus*/
+    ret = LcdDriverAttachToBus(drv_name, bus_name);
+    if (EOK != ret) {
+        KPrintf("Board_LCD_init LcdDriverAttachToBus error %d\n", ret);
+        return -ERROR;
+    } 
+
+    return ret;
+}
+
+/*Attach the lcd device to the lcd bus*/
+static int BoardLcdDevBend(struct LcdHardwareDevice *lcd_device, void *param, const char *bus_name, const char *dev_name)
+{
+    x_err_t ret = EOK;
+
+    ret = LcdDeviceRegister(lcd_device, param, dev_name);
+    if (EOK != ret) {
+        KPrintf("Board_LCD_init LcdDeviceInit device %s error %d\n", dev_name, ret);
+        return -ERROR;
+    }  
+
+    ret = LcdDeviceAttachToBus(dev_name, bus_name);
+    if (EOK != ret) {
+        KPrintf("Board_LCD_init LcdDeviceAttachToBus device %s error %d\n", dev_name, ret);
+        return -ERROR;
+    }  
+
+    return  ret;
+}
+
+int Stm32HwLcdInit(void)
+{
+    x_err_t ret = EOK;
+
+#ifdef BSP_USING_LCD
+    static struct LcdBus lcd_bus;
+    static struct LcdDriver lcd_drv;
+    static struct LcdHardwareDevice lcd_dev;
+    static struct Stm32HwLcd hw_lcd;
+
+    memset(&lcd_bus, 0, sizeof(struct LcdBus));
+    memset(&lcd_drv, 0, sizeof(struct LcdDriver));
+    memset(&lcd_dev, 0, sizeof(struct LcdHardwareDevice));
+    memset(&hw_lcd, 0, sizeof(struct Stm32HwLcd));
+
+    lcd_drv.configure = LcdControl;
+
+    ret = BoardLcdBusInit(&lcd_bus, &lcd_drv, LCD_BUS_NAME, LCD_DRV_NAME);
+    if (EOK != ret) {
+        KPrintf("HwLcdInit BoardLcdBusInit error ret %u\n", ret);
+        return ERROR;
+    }
+
+    lcd_dev.dev_done = &dev_done;
+    hw_lcd.LCD = AIIT_BOARD_LCD;
+
+    /*depends on the LCD hardware*/
+    hw_lcd.lcd_param.lcd_direction = LCD_HORIZONTAL_SCEEN;//Horizontal screen
+    if (LCD_HORIZONTAL_SCEEN == hw_lcd.lcd_param.lcd_direction) {
+        hw_lcd.lcd_param.width = 320;
+        hw_lcd.lcd_param.height = 240;
+    } else if (LCD_VERTICAL_SCEEN == hw_lcd.lcd_param.lcd_direction) {
+        hw_lcd.lcd_param.width = 240;
+        hw_lcd.lcd_param.height = 320;
+    } else {
+        hw_lcd.lcd_param.width = 320;
+        hw_lcd.lcd_param.height = 240;
+    }
+
+    ret = BoardLcdDevBend(&lcd_dev, (void *)&hw_lcd, LCD_BUS_NAME, LCD_DEVICE_NAME);                             //init  lcd device
+    if (EOK != ret) {
+        KPrintf("HwLcdInit BoardLcdDevBend error ret %u\n", ret);
+        return ERROR;
+    }
+
+    Stm32LcdUdelay(5000000);
+
+    HwFsmcInit();
+
+    Stm32LcdUdelay(20000);
+
+    HwLcdInit(&hw_lcd);
+#endif
+
+    return ret;
+}

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/rtc/Kconfig

@@ -0,0 +1,11 @@
+if BSP_USING_RTC
+    config RTC_BUS_NAME
+        string "rtc bus name"
+        default "rtc"
+    config RTC_DRV_NAME
+        string "rtc bus driver name"
+        default "rtc_drv"
+    config RTC_DEVICE_NAME
+            string "rtc bus device name"
+            default "rtc_dev"     
+endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/rtc/Makefile

@@ -0,0 +1,3 @@
+SRC_FILES := hardware_rtc.c connect_rtc.c
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/rtc/connect_rtc.c

@@ -0,0 +1,269 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_rtc.c
+* @brief support aiit-arm32-board rtc function and register to bus framework
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#include <connect_rtc.h>
+#include <hardware_rtc.h>
+#include <hardware_rcc.h>
+#include <hardware_pwr.h>
+#include <stm32f4xx.h>
+#include <time.h>
+
+#define RTC_BACKUP_REGISTER 0x32F2
+
+static int GetWeekDay(int year, int month, int day)
+{
+	if (month==1||month==2) {
+		year -=1;
+		month +=12;
+	}
+	return (day+1+2*month+3*(month+1)/5+year+(year/4)-year/100+year/400)%7+1;
+}
+
+static uint32 RtcConfigure(void *drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(drv);
+
+	struct RtcDriver *rtc_drv = (struct RtcDriver *)drv;
+    struct RtcDrvConfigureParam *drv_param = (struct RtcDrvConfigureParam *)configure_info->private_data;
+
+    int cmd = drv_param->rtc_operation_cmd;
+    time_t *time = drv_param->time;
+
+    switch (cmd)
+    {
+		case OPER_RTC_GET_TIME:
+		{
+			struct tm ct;
+			RTC_TimeTypeDef	t;
+			RTC_DateTypeDef	d;
+
+			memset(&ct,0,sizeof(struct tm));
+			RTC_GetTime(RTC_Format_BIN,&t);
+			RTC_GetDate(RTC_Format_BIN,&d);
+
+			ct.tm_year = d.RTC_Year + 100;
+			ct.tm_mon = d.RTC_Month - 1;
+			ct.tm_mday = d.RTC_Date;
+			ct.tm_wday = d.RTC_WeekDay;
+
+			ct.tm_hour = t.RTC_Hours;
+			ct.tm_min = t.RTC_Minutes;
+			ct.tm_sec = t.RTC_Seconds;
+
+			*time = mktime(&ct);
+		}
+		break;
+
+    	case OPER_RTC_SET_TIME:
+		{
+			struct tm *ct;
+			struct tm tm_new;
+			x_base lock;
+			RTC_TimeTypeDef  rtc_time_structure;
+			RTC_InitTypeDef  rtc_init_structure;
+			RTC_DateTypeDef  rtc_date_structure;
+
+			lock = CriticalAreaLock();
+			ct = localtime(time);
+			memcpy(&tm_new, ct, sizeof(struct tm));
+			CriticalAreaUnLock(lock);
+			RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
+			PWR_BackupAccessCmd(ENABLE);
+			rtc_init_structure.RTC_AsynchPrediv = 0x7F;
+			rtc_init_structure.RTC_SynchPrediv = 0xFF;
+			rtc_init_structure.RTC_HourFormat = RTC_HourFormat_24;
+			RTC_Init(&rtc_init_structure);
+			rtc_date_structure.RTC_Year = tm_new.tm_year - 100;
+			rtc_date_structure.RTC_Month = tm_new.tm_mon + 1;
+			rtc_date_structure.RTC_Date = tm_new.tm_mday;
+			rtc_date_structure.RTC_WeekDay = GetWeekDay(tm_new.tm_year+1900,tm_new.tm_mon+1,tm_new.tm_mday);
+			RTC_SetDate(RTC_Format_BIN, &rtc_date_structure);
+			if (tm_new.tm_hour > 11) {
+				rtc_time_structure.RTC_H12 = RTC_H12_PM;
+			}
+			else{
+				rtc_time_structure.RTC_H12 = RTC_H12_AM;
+			}		
+			rtc_time_structure.RTC_Hours   = tm_new.tm_hour;
+			rtc_time_structure.RTC_Minutes = tm_new.tm_min;
+			rtc_time_structure.RTC_Seconds = tm_new.tm_sec; 
+
+			RTC_SetTime(RTC_Format_BIN, &rtc_time_structure); 		
+
+			RTC_WriteBackupRegister(RTC_BKP_DR0, 0x32F2);        
+		}
+		break;
+    }
+
+    return EOK;
+}
+
+int RtcConfiguration(void)
+{
+	RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
+
+	PWR_BackupAccessCmd(ENABLE);
+
+#if defined (RTC_CLOCK_SOURCE_LSI)
+	RCC_LSICmd(ENABLE);
+
+	while(RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET);
+
+	RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI);
+
+	/* ck_spre(1Hz) = RTCCLK(LSI) /(uwAsynchPrediv + 1)*(uwSynchPrediv + 1)*/
+	//uwSynchPrediv = 0xFF;
+	//uwAsynchPrediv = 0x7F;
+
+#elif defined (RTC_CLOCK_SOURCE_LSE)
+	RCC_LSEConfig(RCC_LSE_ON);
+
+	while(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET);
+
+	RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
+
+#else
+#error Please select the RTC Clock source inside the main.c file
+#endif
+
+	RCC_RTCCLKCmd(ENABLE);
+
+	RTC_WaitForSynchro();
+
+	return 0;
+}
+
+/*manage the rtc device operations*/
+static const struct RtcDevDone dev_done =
+{
+    .open = NONE,
+    .close = NONE,
+    .write = NONE,
+    .read = NONE,
+};
+
+static int BoardRtcBusInit(struct RtcBus *rtc_bus, struct RtcDriver *rtc_driver)
+{
+    x_err_t ret = EOK;
+
+    /*Init the rtc bus */
+    ret = RtcBusInit(rtc_bus, RTC_BUS_NAME);
+    if (EOK != ret) {
+        KPrintf("hw_rtc_init RtcBusInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Init the rtc driver*/
+    ret = RtcDriverInit(rtc_driver, RTC_DRV_NAME);
+    if (EOK != ret) {
+        KPrintf("hw_rtc_init RtcDriverInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Attach the rtc driver to the rtc bus*/
+    ret = RtcDriverAttachToBus(RTC_DRV_NAME, RTC_BUS_NAME);
+    if (EOK != ret) {
+        KPrintf("hw_rtc_init RtcDriverAttachToBus error %d\n", ret);
+        return ERROR;
+    } 
+
+    return ret;
+}
+
+/*Attach the rtc device to the rtc bus*/
+static int BoardRtcDevBend(void)
+{
+    x_err_t ret = EOK;
+
+    static struct RtcHardwareDevice rtc_device;
+    memset(&rtc_device, 0, sizeof(struct RtcHardwareDevice));
+
+    rtc_device.dev_done = &(dev_done);
+
+    ret = RtcDeviceRegister(&rtc_device, NONE, RTC_DEVICE_NAME);
+    if (EOK != ret) {
+        KPrintf("hw_rtc_init RtcDeviceInit device %s error %d\n", RTC_DEVICE_NAME, ret);
+        return ERROR;
+    }  
+
+    ret = RtcDeviceAttachToBus(RTC_DEVICE_NAME, RTC_BUS_NAME);
+    if (EOK != ret) {
+        KPrintf("hw_rtc_init RtcDeviceAttachToBus device %s error %d\n", RTC_DEVICE_NAME, ret);
+        return ERROR;
+    }  
+
+    return  ret;
+}
+
+int Stm32HwRtcInit(void)
+{
+    x_err_t ret = EOK;
+
+    static struct RtcBus rtc_bus;
+    memset(&rtc_bus, 0, sizeof(struct RtcBus));
+
+    static struct RtcDriver rtc_driver;
+    memset(&rtc_driver, 0, sizeof(struct RtcDriver));
+    
+	rtc_driver.configure = &(RtcConfigure);
+
+    ret = BoardRtcBusInit(&rtc_bus, &rtc_driver);
+    if (EOK != ret) {
+        KPrintf("hw_rtc_init error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardRtcDevBend();
+    if (EOK != ret) {
+        KPrintf("hw_rtc_init error ret %u\n", ret);
+        return ERROR;
+    }    
+
+    if (RTC_BACKUP_REGISTER != RTC_ReadBackupRegister(RTC_BKP_DR0)) {
+        if (0 != RtcConfiguration()) {
+            KPrintf("hw_rtc_init RtcConfiguration error...\n");
+            return ERROR;
+        }
+    } else {
+        RTC_WaitForSynchro();
+    }
+
+    return ret;
+}
+
+#ifdef TOOL_SHELL
+void ShowTime(void)
+{
+	RTC_TimeTypeDef	time;
+	RTC_DateTypeDef	date;
+	RTC_GetDate(RTC_Format_BIN,&date);
+	RTC_GetTime(RTC_Format_BIN, &time);
+	KPrintf("Now Time = %d %02d %02d[%02d]-%0.2d:%0.2d:%0.2d \r\n", \
+		date.RTC_Year, 
+		date.RTC_Month,
+		date.RTC_Date,
+		date.RTC_WeekDay,
+		time.RTC_Hours,
+		time.RTC_Minutes,
+		time.RTC_Seconds);
+}
+SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0),
+												ShowTime, ShowTime, Arm test rtc function show time);
+#endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/sdio/Kconfig

@@ -0,0 +1,13 @@
+if BSP_USING_SDIO
+config SDIO_BUS_NAME
+    string "sdio bus name"
+    default "sdio"
+
+config SDIO_DRIVER_NAME
+    string "sdio driver name"
+    default "sdio_drv"
+
+config SDIO_DEVICE_NAME
+    string "sdio device name"
+    default "sdio_dev"
+endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/sdio/Makefile

@@ -0,0 +1,4 @@
+SRC_FILES := connect_sdio.c sdio_sd.c hardware_sdio.c
+
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/sdio/connect_sdio.c

@@ -0,0 +1,239 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_sdio.c
+* @brief support sdio function using bus driver framework
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-22
+*/
+
+/*************************************************
+File name: connect_sdio.c
+Description: support sdio function using bus driver framework
+Others: hardware/sdio/sdio.c for references
+History: 
+1. Date: 2021-04-22
+Author: AIIT XUOS Lab
+Modification: Support aiit-arm32-board sdio configure, write and read functions
+*************************************************/
+
+#include <connect_sdio.h>
+#include "sdio_sd.h"
+
+#ifndef SDCARD_SECTOR_SIZE
+#define SDCARD_SECTOR_SIZE 512
+#endif
+
+static uint32 SdioConfigure(void *drv, struct BusConfigureInfo *ConfigureInfo)
+{
+    NULL_PARAM_CHECK(drv);
+    NULL_PARAM_CHECK(ConfigureInfo);
+
+    if (ConfigureInfo->configure_cmd == OPER_BLK_GETGEOME) {
+        NULL_PARAM_CHECK(ConfigureInfo->private_data);
+        struct DeviceBlockArrange *args = (struct DeviceBlockArrange *)ConfigureInfo->private_data;
+        SD_GetCardInfo(&SDCardInfo);
+
+        args->size_perbank = SDCardInfo.CardBlockSize;
+        args->block_size = SDCardInfo.CardBlockSize;
+        if (SDCardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD)
+            args->bank_num = (SDCardInfo.SD_csd.DeviceSize + 1)  * 1024;
+        else
+            args->bank_num = SDCardInfo.CardCapacity;
+    }
+
+    return EOK;
+}
+
+static int SDLock = -1;
+static uint32 SDBuffer[512/sizeof(uint32_t)];
+
+static uint32 SdioOpen(void *dev)
+{
+    NULL_PARAM_CHECK(dev);
+
+    if (SDLock >= 0) {
+        KSemaphoreDelete(SDLock);
+    }
+    SDLock = KSemaphoreCreate(1);
+    if (SDLock < 0) {
+        return ERROR;
+    }
+
+    return EOK;
+}
+
+static uint32 SdioClose(void *dev)
+{
+    NULL_PARAM_CHECK(dev);
+
+    KSemaphoreDelete(SDLock);
+
+    return EOK;
+}
+
+static uint32 SdioRead(void *dev, struct BusBlockReadParam *read_param)
+{
+    uint8 ret = SD_OK;
+
+    KSemaphoreObtain(SDLock, WAITING_FOREVER);
+
+    if (((uint32)read_param->buffer & 0x03) != 0) {
+        uint64_t sector;
+        uint8_t* temp;
+
+        sector = (uint64_t)read_param->pos * SDCARD_SECTOR_SIZE;
+        temp = (uint8_t*)read_param->buffer;
+
+        for (uint8 i = 0; i < read_param->size; i++) {
+            ret = SD_ReadBlock((uint8_t *)SDBuffer, sector, 1);
+            if (ret != SD_OK) {
+                KPrintf("read failed: %d, buffer 0x%08x\n", ret, temp);
+                return 0;
+            }
+#if defined (SD_DMA_MODE)
+            ret = SD_WaitReadOperation();
+            if (ret != SD_OK) {
+                KPrintf("read failed: %d, buffer 0x%08x\n", ret, temp);
+                return 0;
+            }
+#endif
+            memcpy(temp, SDBuffer, SDCARD_SECTOR_SIZE);
+
+            sector += SDCARD_SECTOR_SIZE;
+            temp += SDCARD_SECTOR_SIZE;
+        }
+    } else {
+        ret = SD_ReadBlock((uint8_t *)read_param->buffer, (uint64_t)read_param->pos * SDCARD_SECTOR_SIZE, read_param->size);
+        if (ret != SD_OK) {
+            KPrintf("read failed: %d, buffer 0x%08x\n", ret, (uint8_t *)read_param->buffer);
+            return 0;
+        }
+#if defined (SD_DMA_MODE)
+        ret = SD_WaitReadOperation();
+        if (ret != SD_OK) {
+            KPrintf("read failed: %d, buffer 0x%08x\n", ret, (uint8_t *)read_param->buffer);
+            return 0;
+        }
+#endif
+    }
+
+    KSemaphoreAbandon(SDLock);
+
+    return read_param->size;
+}
+
+static uint32 SdioWrite(void *dev, struct BusBlockWriteParam *write_param)
+{
+    uint8 ret = SD_OK;
+
+    KSemaphoreObtain(SDLock, WAITING_FOREVER);
+
+    if (((uint32)write_param->buffer & 0x03) != 0) {
+        uint64_t sector;
+        uint8_t* temp;
+
+        sector = (uint64_t)write_param->pos * SDCARD_SECTOR_SIZE;
+        temp = (uint8_t*)write_param->buffer;
+
+        for (uint8 i = 0; i < write_param->size; i++) {
+            memcpy(SDBuffer, temp, SDCARD_SECTOR_SIZE);
+
+            ret = SD_WriteBlock((uint8_t *)SDBuffer, sector, 1);
+            if (ret != SD_OK) {
+                KPrintf("write failed: %d, buffer 0x%08x\n", ret, temp);
+                return 0;
+            }
+#if defined (SD_DMA_MODE)
+            ret = SD_WaitWriteOperation();
+            if (ret != SD_OK) {
+                KPrintf("write failed: %d, buffer 0x%08x\n", ret, temp);
+                return 0;
+            }
+#endif
+            sector += SDCARD_SECTOR_SIZE;
+            temp += SDCARD_SECTOR_SIZE;
+        }
+    } else {
+        ret = SD_WriteBlock((uint8_t *)write_param->buffer, (uint64_t)write_param->pos * SDCARD_SECTOR_SIZE, write_param->size);
+        if (ret != SD_OK) {
+            KPrintf("write failed: %d, buffer 0x%08x\n", ret, (uint8_t *)write_param->buffer);
+            return 0;
+        }
+#if defined (SD_DMA_MODE)
+        ret = SD_WaitWriteOperation();
+        if (ret != SD_OK) {
+            KPrintf("write failed: %d, buffer 0x%08x\n", ret, (uint8_t *)write_param->buffer);
+            return 0;
+        }
+#endif
+    }
+
+    KSemaphoreAbandon(SDLock);
+
+    return write_param->size;
+}
+
+static struct SdioDevDone dev_done = 
+{
+    SdioOpen,
+    SdioClose,
+    SdioWrite,
+    SdioRead,
+};
+
+int HwSdioInit(void)
+{
+    static struct SdioBus bus;
+    static struct SdioDriver drv;
+    static struct SdioHardwareDevice dev;
+
+    x_err_t ret = EOK;
+    ret = SD_Init();
+    if (ret != SD_OK) {
+        KPrintf("SD init failed!"); 
+        return ERROR;
+    }
+    
+    ret = SdioBusInit(&bus, SDIO_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("Sdio bus init error %d\n", ret);
+        return ERROR;
+    }
+
+    ret = SdioDriverInit(&drv, SDIO_DRIVER_NAME);
+    if (ret != EOK) {
+        KPrintf("Sdio driver init error %d\n", ret);
+        return ERROR;
+    }
+    ret = SdioDriverAttachToBus(SDIO_DRIVER_NAME, SDIO_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("Sdio driver attach error %d\n", ret);
+        return ERROR;
+    }
+
+    dev.dev_done = &dev_done;
+    ret = SdioDeviceRegister(&dev, SDIO_DEVICE_NAME);
+    if (ret != EOK) {
+        KPrintf("Sdio device register error %d\n", ret);
+        return ERROR;
+    }
+    ret = SdioDeviceAttachToBus(SDIO_DEVICE_NAME, SDIO_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("Sdio device register error %d\n", ret);
+        return ERROR;
+    }
+
+    return ret;
+}

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/sdio/sdio_sd.h

@@ -0,0 +1,399 @@
+/*
+ * Copyright (c) Guangzhou Xingyi Electronic  Technology Co., Ltd
+ *
+ * Change Logs:
+ * Date               Author       Notes
+ * 2014-7-4      alientek   first version
+ */
+
+/**
+* @file sdio_sd.h
+* @brief define std sdio function and struct
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-22
+*/
+
+/*************************************************
+File name: sdio_sd.h
+Description: define std sdio function and struct
+Others: hardware/sdio/sdio.h for references
+History: 
+1. Date: 2021-04-22
+Author: AIIT XUOS Lab
+Modification: Support aiit-arm32-board sdio using source files
+*************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __SDIO_SDCARD_H
+#define __SDIO_SDCARD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+/* Exported types ------------------------------------------------------------*/
+/** 
+  * @brief  SDIO Intialization Frequency (400KHz max)
+  */
+#define SDIO_INIT_CLK_DIV                ((uint8_t)0xB4)
+/** 
+  * @brief  SDIO Data Transfer Frequency (25MHz max) 
+  */
+/*!< SDIOCLK = HCLK, SDIO_CK = HCLK/(2 + SDIO_TRANSFER_CLK_DIV) */
+
+// #define SDIO_TRANSFER_CLK_DIV            ((uint8_t)0x01) 
+#define SDIO_TRANSFER_CLK_DIV            ((uint8_t)0x4) 
+
+
+/* Uncomment the following line to select the SDIO Data transfer mode */  
+#define SD_DMA_MODE                      ((uint32_t)0x00000000)
+//#define SD_POLLING_MODE                  ((uint32_t)0x00000002)
+
+
+typedef enum
+{
+/** 
+  * @brief  SDIO specific error defines  
+  */   
+  SD_CMD_CRC_FAIL                    = (1), /*!< Command response received (but CRC check failed) */
+  SD_DATA_CRC_FAIL                   = (2), /*!< Data bock sent/received (CRC check Failed) */
+  SD_CMD_RSP_TIMEOUT                 = (3), /*!< Command response timeout */
+  SD_DATA_TIMEOUT                    = (4), /*!< Data time out */
+  SD_TX_UNDERRUN                     = (5), /*!< Transmit FIFO under-run */
+  SD_RX_OVERRUN                      = (6), /*!< Receive FIFO over-run */
+  SD_START_BIT_ERR                   = (7), /*!< Start bit not detected on all data signals in widE bus mode */
+  SD_CMD_OUT_OF_RANGE                = (8), /*!< CMD's argument was out of range.*/
+  SD_ADDR_MISALIGNED                 = (9), /*!< Misaligned address */
+  SD_BLOCK_LEN_ERR                   = (10), /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
+  SD_ERASE_SEQ_ERR                   = (11), /*!< An error in the sequence of erase command occurs.*/
+  SD_BAD_ERASE_PARAM                 = (12), /*!< An Invalid selection for erase groups */
+  SD_WRITE_PROT_VIOLATION            = (13), /*!< Attempt to program a write protect block */
+  SD_LOCK_UNLOCK_FAILED              = (14), /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
+  SD_COM_CRC_FAILED                  = (15), /*!< CRC check of the previous command failed */
+  SD_ILLEGAL_CMD                     = (16), /*!< Command is not legal for the card state */
+  SD_CARD_ECC_FAILED                 = (17), /*!< Card internal ECC was applied but failed to correct the data */
+  SD_CC_ERROR                        = (18), /*!< Internal card controller error */
+  SD_GENERAL_UNKNOWN_ERROR           = (19), /*!< General or Unknown error */
+  SD_STREAM_READ_UNDERRUN            = (20), /*!< The card could not sustain data transfer in stream read operation. */
+  SD_STREAM_WRITE_OVERRUN            = (21), /*!< The card could not sustain data programming in stream mode */
+  SD_CID_CSD_OVERWRITE               = (22), /*!< CID/CSD overwrite error */
+  SD_WP_ERASE_SKIP                   = (23), /*!< only partial address space was erased */
+  SD_CARD_ECC_DISABLED               = (24), /*!< Command has been executed without using internal ECC */
+  SD_ERASE_RESET                     = (25), /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
+  SD_AKE_SEQ_ERROR                   = (26), /*!< Error in sequence of authentication. */
+  SD_INVALID_VOLTRANGE               = (27),
+  SD_ADDR_OUT_OF_RANGE               = (28),
+  SD_SWITCH_ERROR                    = (29),
+  SD_SDIO_DISABLED                   = (30),
+  SD_SDIO_FUNCTION_BUSY              = (31),
+  SD_SDIO_FUNCTION_FAILED            = (32),
+  SD_SDIO_UNKNOWN_FUNCTION           = (33),
+
+/** 
+  * @brief  Standard error defines   
+  */ 
+  SD_INTERNAL_ERROR, 
+  SD_NOT_CONFIGURED,
+  SD_REQUEST_PENDING, 
+  SD_REQUEST_NOT_APPLICABLE, 
+  SD_INVALID_PARAMETER,  
+  SD_UNSUPPORTED_FEATURE,  
+  SD_UNSUPPORTED_HW,  
+  SD_ERROR,  
+  SD_OK = 0 
+} SD_Error;
+
+/** 
+  * @brief  SDIO Transfer state  
+  */   
+typedef enum
+{
+  SD_TRANSFER_OK  = 0,
+  SD_TRANSFER_BUSY = 1,
+  SD_TRANSFER_ERROR
+} SDTransferState;
+
+/** 
+  * @brief  SD Card States 
+  */   
+typedef enum
+{
+  SD_CARD_READY                  = ((uint32_t)0x00000001),
+  SD_CARD_IDENTIFICATION         = ((uint32_t)0x00000002),
+  SD_CARD_STANDBY                = ((uint32_t)0x00000003),
+  SD_CARD_TRANSFER               = ((uint32_t)0x00000004),
+  SD_CARD_SENDING                = ((uint32_t)0x00000005),
+  SD_CARD_RECEIVING              = ((uint32_t)0x00000006),
+  SD_CARD_PROGRAMMING            = ((uint32_t)0x00000007),
+  SD_CARD_DISCONNECTED           = ((uint32_t)0x00000008),
+  SD_CARD_ERROR                  = ((uint32_t)0x000000FF)
+}SDCardState;
+
+
+/** 
+  * @brief  Card Specific Data: CSD Register   
+  */ 
+typedef struct
+{
+  __IO uint8_t  CSDStruct;            /*!< CSD structure */
+  __IO uint8_t  SysSpecVersion;       /*!< System specification version */
+  __IO uint8_t  Reserved1;            /*!< Reserved */
+  __IO uint8_t  TAAC;                 /*!< Data read access-time 1 */
+  __IO uint8_t  NSAC;                 /*!< Data read access-time 2 in CLK cycles */
+  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency */
+  __IO uint16_t CardComdClasses;      /*!< Card command classes */
+  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length */
+  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed */
+  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment */
+  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment */
+  __IO uint8_t  DSRImpl;              /*!< DSR implemented */
+  __IO uint8_t  Reserved2;            /*!< Reserved */
+  __IO uint32_t DeviceSize;           /*!< Device Size */
+  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min */
+  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max */
+  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min */
+  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max */
+  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier */
+  __IO uint8_t  EraseGrSize;          /*!< Erase group size */
+  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier */
+  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size */
+  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable */
+  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC */
+  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor */
+  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length */
+  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed */
+  __IO uint8_t  Reserved3;            /*!< Reserded */
+  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application */
+  __IO uint8_t  FileFormatGrouop;     /*!< File format group */
+  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP) */
+  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection */
+  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection */
+  __IO uint8_t  FileFormat;           /*!< File Format */
+  __IO uint8_t  ECC;                  /*!< ECC code */
+  __IO uint8_t  CSD_CRC;              /*!< CSD CRC */
+  __IO uint8_t  Reserved4;            /*!< always 1*/
+} SD_CSD;
+
+/** 
+  * @brief  Card Identification Data: CID Register   
+  */
+typedef struct
+{
+  __IO uint8_t  ManufacturerID;       /*!< ManufacturerID */
+  __IO uint16_t OEM_AppliID;          /*!< OEM/Application ID */
+  __IO uint32_t ProdName1;            /*!< Product Name part1 */
+  __IO uint8_t  ProdName2;            /*!< Product Name part2*/
+  __IO uint8_t  ProdRev;              /*!< Product Revision */
+  __IO uint32_t ProdSN;               /*!< Product Serial Number */
+  __IO uint8_t  Reserved1;            /*!< Reserved1 */
+  __IO uint16_t ManufactDate;         /*!< Manufacturing Date */
+  __IO uint8_t  CID_CRC;              /*!< CID CRC */
+  __IO uint8_t  Reserved2;            /*!< always 1 */
+} SD_CID;
+
+/** 
+  * @brief SD Card Status 
+  */
+typedef struct
+{
+  __IO uint8_t DAT_BUS_WIDTH;
+  __IO uint8_t SECURED_MODE;
+  __IO uint16_t SD_CARD_TYPE;
+  __IO uint32_t SIZE_OF_PROTECTED_AREA;
+  __IO uint8_t SPEED_CLASS;
+  __IO uint8_t PERFORMANCE_MOVE;
+  __IO uint8_t AU_SIZE;
+  __IO uint16_t ERASE_SIZE;
+  __IO uint8_t ERASE_TIMEOUT;
+  __IO uint8_t ERASE_OFFSET;
+} SD_CardStatus;
+
+
+/** 
+  * @brief SD Card information 
+  */
+typedef struct
+{
+  SD_CSD SD_csd;
+  SD_CID SD_cid;
+  uint32_t CardCapacity;  /*!< Card Capacity */
+  uint32_t CardBlockSize; /*!< Card Block Size */
+  uint16_t RCA;
+  uint8_t CardType;
+} SD_CardInfo;
+
+#define SDIO_FIFO_ADDRESS             SDIO_BASE+0x80	 //SDIO_FIOF address =SDIO address+0x80 to SDIO address+0xfc
+
+#define SD_SDIO_DMA                   DMA2
+#define SD_SDIO_DMA_CLK               RCC_AHB1Periph_DMA2
+ 
+//#define SD_SDIO_DMA_STREAM3	          3
+#define SD_SDIO_DMA_STREAM6           6
+
+#ifdef SD_SDIO_DMA_STREAM3
+ #define SD_SDIO_DMA_STREAM            DMA2_Stream3
+ #define SD_SDIO_DMA_CHANNEL           DMA_Channel_4
+ #define SD_SDIO_DMA_FLAG_FEIF         DMA_FLAG_FEIF3
+ #define SD_SDIO_DMA_FLAG_DMEIF        DMA_FLAG_DMEIF3
+ #define SD_SDIO_DMA_FLAG_TEIF         DMA_FLAG_TEIF3
+ #define SD_SDIO_DMA_FLAG_HTIF         DMA_FLAG_HTIF3
+ #define SD_SDIO_DMA_FLAG_TCIF         DMA_FLAG_TCIF3 
+ #define SD_SDIO_DMA_IRQn              DMA2_Stream3_IRQn
+ #define SD_SDIO_DMA_IRQHANDLER        DMA2_Stream3_IRQHandler 
+#elif defined SD_SDIO_DMA_STREAM6
+ #define SD_SDIO_DMA_STREAM            DMA2_Stream6
+ #define SD_SDIO_DMA_CHANNEL           DMA_Channel_4
+ #define SD_SDIO_DMA_FLAG_FEIF         DMA_FLAG_FEIF6
+ #define SD_SDIO_DMA_FLAG_DMEIF        DMA_FLAG_DMEIF6
+ #define SD_SDIO_DMA_FLAG_TEIF         DMA_FLAG_TEIF6
+ #define SD_SDIO_DMA_FLAG_HTIF         DMA_FLAG_HTIF6
+ #define SD_SDIO_DMA_FLAG_TCIF         DMA_FLAG_TCIF6 
+ #define SD_SDIO_DMA_IRQn              DMA2_Stream6_IRQn
+ #define SD_SDIO_DMA_IRQHANDLER        DMA2_Stream6_IRQHandler
+#endif /* SD_SDIO_DMA_STREAM3 */	  
+/** 
+  * @brief SDIO Commands  Index 
+  */
+#define SD_CMD_GO_IDLE_STATE                       ((uint8_t)0)
+#define SD_CMD_SEND_OP_COND                        ((uint8_t)1)
+#define SD_CMD_ALL_SEND_CID                        ((uint8_t)2)
+#define SD_CMD_SET_REL_ADDR                        ((uint8_t)3) /*!< SDIO_SEND_REL_ADDR for SD Card */
+#define SD_CMD_SET_DSR                             ((uint8_t)4)
+#define SD_CMD_SDIO_SEN_OP_COND                    ((uint8_t)5)
+#define SD_CMD_HS_SWITCH                           ((uint8_t)6)
+#define SD_CMD_SEL_DESEL_CARD                      ((uint8_t)7)
+#define SD_CMD_HS_SEND_EXT_CSD                     ((uint8_t)8)
+#define SD_CMD_SEND_CSD                            ((uint8_t)9)
+#define SD_CMD_SEND_CID                            ((uint8_t)10)
+#define SD_CMD_READ_DAT_UNTIL_STOP                 ((uint8_t)11) /*!< SD Card doesn't support it */
+#define SD_CMD_STOP_TRANSMISSION                   ((uint8_t)12)
+#define SD_CMD_SEND_STATUS                         ((uint8_t)13)
+#define SD_CMD_HS_BUSTEST_READ                     ((uint8_t)14)
+#define SD_CMD_GO_INACTIVE_STATE                   ((uint8_t)15)
+#define SD_CMD_SET_BLOCKLEN                        ((uint8_t)16)
+#define SD_CMD_READ_SINGLE_BLOCK                   ((uint8_t)17)
+#define SD_CMD_READ_MULT_BLOCK                     ((uint8_t)18)
+#define SD_CMD_HS_BUSTEST_WRITE                    ((uint8_t)19)
+#define SD_CMD_WRITE_DAT_UNTIL_STOP                ((uint8_t)20) /*!< SD Card doesn't support it */
+#define SD_CMD_SET_BLOCK_COUNT                     ((uint8_t)23) /*!< SD Card doesn't support it */
+#define SD_CMD_WRITE_SINGLE_BLOCK                  ((uint8_t)24)
+#define SD_CMD_WRITE_MULT_BLOCK                    ((uint8_t)25)
+#define SD_CMD_PROG_CID                            ((uint8_t)26) /*!< reserved for manufacturers */
+#define SD_CMD_PROG_CSD                            ((uint8_t)27)
+#define SD_CMD_SET_WRITE_PROT                      ((uint8_t)28)
+#define SD_CMD_CLR_WRITE_PROT                      ((uint8_t)29)
+#define SD_CMD_SEND_WRITE_PROT                     ((uint8_t)30)
+#define SD_CMD_SD_ERASE_GRP_START                  ((uint8_t)32) /*!< To set the address of the first write
+                                                                  block to be erased. (For SD card only) */
+#define SD_CMD_SD_ERASE_GRP_END                    ((uint8_t)33) /*!< To set the address of the last write block of the
+                                                                  continuous range to be erased. (For SD card only) */
+#define SD_CMD_ERASE_GRP_START                     ((uint8_t)35) /*!< To set the address of the first write block to be erased.
+                                                                  (For MMC card only spec 3.31) */
+
+#define SD_CMD_ERASE_GRP_END                       ((uint8_t)36) /*!< To set the address of the last write block of the
+                                                                  continuous range to be erased. (For MMC card only spec 3.31) */
+
+#define SD_CMD_ERASE                               ((uint8_t)38)
+#define SD_CMD_FAST_IO                             ((uint8_t)39) /*!< SD Card doesn't support it */
+#define SD_CMD_GO_IRQ_STATE                        ((uint8_t)40) /*!< SD Card doesn't support it */
+#define SD_CMD_LOCK_UNLOCK                         ((uint8_t)42)
+#define SD_CMD_APP_CMD                             ((uint8_t)55)
+#define SD_CMD_GEN_CMD                             ((uint8_t)56)
+#define SD_CMD_NO_CMD                              ((uint8_t)64)
+
+/** 
+  * @brief Following commands are SD Card Specific commands.
+  *        SDIO_APP_CMD ：CMD55 should be sent before sending these commands. 
+  */
+#define SD_CMD_APP_SD_SET_BUSWIDTH                 ((uint8_t)6)  /*!< For SD Card only */
+#define SD_CMD_SD_APP_STAUS                        ((uint8_t)13) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((uint8_t)22) /*!< For SD Card only */
+#define SD_CMD_SD_APP_OP_COND                      ((uint8_t)41) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT          ((uint8_t)42) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SEND_SCR                     ((uint8_t)51) /*!< For SD Card only */
+#define SD_CMD_SDIO_RW_DIRECT                      ((uint8_t)52) /*!< For SD I/O Card only */
+#define SD_CMD_SDIO_RW_EXTENDED                    ((uint8_t)53) /*!< For SD I/O Card only */
+
+/** 
+  * @brief Following commands are SD Card Specific security commands.
+  *        SDIO_APP_CMD should be sent before sending these commands. 
+  */
+#define SD_CMD_SD_APP_GET_MKB                      ((uint8_t)43) /*!< For SD Card only */
+#define SD_CMD_SD_APP_GET_MID                      ((uint8_t)44) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SET_CER_RN1                  ((uint8_t)45) /*!< For SD Card only */
+#define SD_CMD_SD_APP_GET_CER_RN2                  ((uint8_t)46) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SET_CER_RES2                 ((uint8_t)47) /*!< For SD Card only */
+#define SD_CMD_SD_APP_GET_CER_RES1                 ((uint8_t)48) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   ((uint8_t)18) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  ((uint8_t)25) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SECURE_ERASE                 ((uint8_t)38) /*!< For SD Card only */
+#define SD_CMD_SD_APP_CHANGE_SECURE_AREA           ((uint8_t)49) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SECURE_WRITE_MKB             ((uint8_t)48) /*!< For SD Card only */
+  
+
+/**
+  * @brief  SD detection on its memory slot
+  */
+#define SD_PRESENT                                 ((uint8_t)0x01)
+#define SD_NOT_PRESENT                             ((uint8_t)0x00)
+
+/** 
+  * @brief Supported SD Memory Cards 
+  */
+#define SDIO_STD_CAPACITY_SD_CARD_V1_1             ((uint32_t)0x00000000)
+#define SDIO_STD_CAPACITY_SD_CARD_V2_0             ((uint32_t)0x00000001)
+#define SDIO_HIGH_CAPACITY_SD_CARD                 ((uint32_t)0x00000002)
+#define SDIO_MULTIMEDIA_CARD                       ((uint32_t)0x00000003)
+#define SDIO_SECURE_DIGITAL_IO_CARD                ((uint32_t)0x00000004)
+#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD            ((uint32_t)0x00000005)
+#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD          ((uint32_t)0x00000006)
+#define SDIO_HIGH_CAPACITY_MMC_CARD                ((uint32_t)0x00000007)
+
+
+
+/* Exported functions ------------------------------------------------------- */
+void SD_DeInit(void);
+SD_Error SD_Init(void);
+SDTransferState SD_GetStatus(void);
+SDCardState SD_GetState(void);
+uint8_t SD_Detect(void);
+SD_Error SD_PowerON(void);
+SD_Error SD_PowerOFF(void);
+SD_Error SD_InitializeCards(void);
+SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo);
+SD_Error SD_GetCardStatus(SD_CardStatus *cardstatus);
+SD_Error SD_EnableWideBusOperation(uint32_t WideMode);
+SD_Error SD_SelectDeselect(uint32_t addr);
+SD_Error SD_ReadBlock(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize);
+SD_Error SD_ReadMultiBlocks(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
+SD_Error SD_WriteBlock(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize);
+SD_Error SD_WriteMultiBlocks(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
+SDTransferState SD_GetTransferState(void);
+SD_Error SD_StopTransfer(void);
+SD_Error SD_Erase(uint32_t startaddr, uint32_t endaddr);
+SD_Error SD_SendStatus(uint32_t *pcardstatus);
+SD_Error SD_SendSDStatus(uint32_t *psdstatus);
+SD_Error SD_ProcessIRQSrc(void);
+SD_Error SD_WaitReadOperation(void);
+SD_Error SD_WaitWriteOperation(void);
+void SD_ProcessDMAIRQ(void);
+void NVIC_Configuration(void);
+
+
+
+SD_Error SD_LBA_ReadBlocks(uint8_t *readbuff, uint32_t BlockAddr, uint32_t NumberOfBlocks);
+SD_Error SD_LBA_WriteBlocks(uint8_t *writebuff, uint32_t BlockAddr, uint32_t NumberOfBlocks);
+
+extern SD_CardInfo SDCardInfo;
+
+
+ 
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SDCARD_H */
+

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/spi/Kconfig

@@ -0,0 +1,77 @@
+config BSP_USING_SPI1
+bool "Using spi1  "
+default n
+
+if BSP_USING_SPI1
+    config SPI_BUS_NAME_1
+        string "spi bus 1 name"
+        default "spi1"
+    config SPI_1_DRV_NAME
+        string "spi bus 1 driver name"
+        default "spi1_drv"
+endif
+
+config BSP_USING_SPI2
+bool "Using spi2  "
+default n
+
+if BSP_USING_SPI2
+    config SPI_BUS_NAME_2
+        string "spi bus 2 name"
+        default "spi2"
+    config SPI_2_DRV_NAME
+        string "spi bus 2 driver name"
+        default "spi2_drv"
+    menuconfig RESOURCES_SPI_LORA
+    bool "Using spi lora function"
+    default n
+    if RESOURCES_SPI_LORA
+    config SX12XX_SPI_DEVICE_NAME
+        string "SX1278 lora device spi name"
+        default "spi2_dev0"
+    config SX12XX_DEVICE_NAME
+        string "SX1278 lora device name"
+        default "spi2_lora"
+
+    config SX12XX_DEVICE_RST_PIN
+        int
+        default 10
+
+    config SX12XX_DEVICE_DO0_PIN
+        int
+        default 10
+
+    config SX12XX_DEVICE_DO1_PIN
+        int
+        default 10
+
+    config SX12XX_DEVICE_DO2_PIN
+        int
+        default 10
+    
+    config SX12XX_DEVICE_DO3_PIN
+        int
+        default 10
+    
+    config SX12XX_DEVICE_DO4_PIN
+        int
+        default 10
+    
+    config SX12XX_DEVICE_DO5_PIN
+        int
+        default 10
+    endif
+endif
+
+config BSP_USING_SPI3
+bool "Using spi3  "
+default n
+
+if BSP_USING_SPI3
+    config SPI_BUS_NAME_3
+        string "spi bus 3 name"
+        default "spi3"
+    config SPI_3_DRV_NAME
+        string "spi bus 3 driver name"
+        default "spi3_drv"
+endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/spi/Makefile

@@ -0,0 +1,12 @@
+SRC_FILES := hardware_spi.c connect_spi.c 
+
+ifeq ($(CONFIG_RESOURCES_SPI_SFUD),y)
+	SRC_FILES += connect_flash_spi.c
+endif
+
+ifeq ($(CONFIG_RESOURCES_SPI_LORA),y)
+	SRC_DIR += third_party_spi_lora
+	SRC_FILES += connect_lora_spi.c
+endif
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/spi/connect_flash_spi.c

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2020 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-27     SummerGift   add spi flash port file
+ */
+
+/**
+* @file connect_flash_spi.c
+* @brief support aiit-arm32-board spi flash function and register to bus framework
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+/*************************************************
+File name: connect_flash_spi.c
+Description: support aiit-arm32-board spi flash bus register function
+Others: take RT-Thread v4.0.2/bsp/stm32/stm32f407-atk-explorer/board/ports/spi-flash-init.c
+                https://github.com/RT-Thread/rt-thread/tree/v4.0.2
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. support aiit-arm32-board spi flash register to spi bus
+2. support aiit-arm32-board spi flash init
+*************************************************/
+
+#include <connect_spi.h>
+#include <flash_spi.h>
+#include <hardware_gpio.h>
+
+int FlashW25qxxSpiDeviceInit(void)
+{
+#ifdef BSP_USING_SPI1
+
+    __IO uint32_t tmpreg = 0x00U;
+    RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN;
+    tmpreg = RCC->AHB1ENR & RCC_AHB1ENR_GPIOBEN;
+    (void)tmpreg;
+
+    if (EOK != HwSpiDeviceAttach(SPI_BUS_NAME_1, "spi1_dev0", GPIOB, GPIO_Pin_0)) {
+        return ERROR;
+    }
+
+    if (NONE == SpiFlashInit(SPI_BUS_NAME_1, "spi1_dev0", SPI_1_DRV_NAME, "spi1_W25Q64")) {
+        return ERROR;
+    }
+
+#endif
+
+    return EOK;
+}

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/spi/connect_lora_spi.c

@@ -0,0 +1,562 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_lora_spi.c
+* @brief support to register spi lora pointer and function
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-05-17
+*/
+
+#include <connect_spi_lora.h>
+
+static struct HardwareDev *g_spi_lora_dev;
+static BusType buspin;
+tRadioDriver *Radio = NONE;
+void SX1276InitIo(void)
+{
+    struct PinParam PinCfg;
+	struct PinStat PinStat;
+
+	struct BusConfigureInfo configure_info;
+	struct BusBlockWriteParam write_param;
+
+    write_param.buffer = (void *)&PinStat;
+    configure_info.configure_cmd = OPE_CFG;
+    configure_info.private_data = (void *)&PinCfg;
+
+    buspin = PinBusInitGet();  
+
+    PinCfg.cmd = GPIO_CONFIG_MODE;
+    PinCfg.pin = SX12XX_DEVICE_DO0_PIN;
+    PinCfg.mode = GPIO_CFG_INPUT;
+    BusDrvConfigure(buspin->owner_driver, &configure_info);
+
+    PinCfg.cmd = GPIO_CONFIG_MODE;
+    PinCfg.pin = SX12XX_DEVICE_DO1_PIN;
+    PinCfg.mode = GPIO_CFG_INPUT;
+    BusDrvConfigure(buspin->owner_driver, &configure_info);
+
+    PinCfg.cmd = GPIO_CONFIG_MODE;
+    PinCfg.pin = SX12XX_DEVICE_DO2_PIN;
+    PinCfg.mode = GPIO_CFG_INPUT;
+    BusDrvConfigure(buspin->owner_driver, &configure_info);
+}
+
+inline uint8_t SX1276ReadDio0(void)
+{
+    struct PinStat PinStat;
+
+    struct BusBlockReadParam read_param;
+    read_param.buffer = (void *)&PinStat;
+
+    PinStat.pin = SX12XX_DEVICE_DO0_PIN;
+    
+    return BusDevReadData(buspin->owner_haldev, &read_param);
+}
+
+inline uint8_t SX1276ReadDio1(void)
+{
+    struct PinStat PinStat;
+
+    struct BusBlockReadParam read_param;
+    read_param.buffer = (void *)&PinStat;
+
+    PinStat.pin = SX12XX_DEVICE_DO1_PIN;
+    
+    return BusDevReadData(buspin->owner_haldev, &read_param);
+}
+
+inline uint8_t SX1276ReadDio2(void)
+{
+    struct PinStat PinStat;
+
+    struct BusBlockReadParam read_param;
+    read_param.buffer = (void *)&PinStat;
+
+    PinStat.pin = SX12XX_DEVICE_DO2_PIN;
+    
+    return BusDevReadData(buspin->owner_haldev, &read_param);
+}
+
+inline uint8_t SX1276ReadDio3(void)
+{
+    struct PinStat PinStat;
+
+    struct BusBlockReadParam read_param;
+    read_param.buffer = (void *)&PinStat;
+
+    PinStat.pin = SX12XX_DEVICE_DO3_PIN;
+    
+    return BusDevReadData(buspin->owner_haldev, &read_param);
+}
+
+inline uint8_t SX1276ReadDio4(void)
+{
+    struct PinStat PinStat;
+
+    struct BusBlockReadParam read_param;
+    read_param.buffer = (void *)&PinStat;
+
+    PinStat.pin = SX12XX_DEVICE_DO4_PIN;
+    
+    return BusDevReadData(buspin->owner_haldev, &read_param);
+}
+
+inline uint8_t SX1276ReadDio5(void)
+{
+    struct PinStat PinStat;
+
+    struct BusBlockReadParam read_param;
+    read_param.buffer = (void *)&PinStat;
+
+    PinStat.pin = SX12XX_DEVICE_DO5_PIN;
+    
+    return BusDevReadData(buspin->owner_haldev, &read_param);
+}
+
+inline void SX1276WriteRxTx(uint8_t txEnable)
+{
+    if (txEnable != 0)
+    {
+        /*to do*/
+    }
+    else
+    {
+        /*to do*/
+    }
+}
+
+void SX1276SetReset(uint8_t state)
+{
+    struct PinParam PinCfg;
+	struct PinStat PinStat;
+
+	struct BusConfigureInfo configure_info;
+	struct BusBlockWriteParam write_param;
+
+    configure_info.configure_cmd = OPE_CFG;
+    configure_info.private_data = (void *)&PinCfg;
+    write_param.buffer = (void *)&PinStat;
+
+    if (state == RADIO_RESET_ON)
+    {
+        PinCfg.cmd = GPIO_CONFIG_MODE;
+        PinCfg.pin = SX12XX_DEVICE_RST_PIN;
+        PinCfg.mode = GPIO_CFG_OUTPUT;
+        BusDrvConfigure(buspin->owner_driver, &configure_info);
+
+        PinStat.val = GPIO_LOW;
+        PinStat.pin = SX12XX_DEVICE_RST_PIN;
+        BusDevWriteData(buspin->owner_haldev, &write_param);
+    }
+    else
+    {
+        PinCfg.cmd = GPIO_CONFIG_MODE;
+        PinCfg.pin = SX12XX_DEVICE_RST_PIN;
+        PinCfg.mode = GPIO_CFG_INPUT;
+        BusDrvConfigure(buspin->owner_driver, &configure_info);
+    }
+}
+
+void SX1276Write(uint8_t addr, uint8_t data)
+{
+    SX1276WriteBuffer(addr, &data, 1);
+}
+
+void SX1276Read(uint8_t addr, uint8_t *data)
+{
+    SX1276ReadBuffer(addr, data, 1);
+}
+
+void SX1276WriteBuffer(uint8_t addr, uint8_t *buffer, uint8_t size)
+{
+    struct BusBlockWriteParam write_param;
+    uint8 write_addr = addr | 0x80;
+
+    BusDevOpen(g_spi_lora_dev);
+
+    write_param.buffer = (void *)&write_addr;
+    write_param.size = 1;
+    BusDevWriteData(g_spi_lora_dev, &write_param);
+
+    write_param.buffer = (void *)buffer;
+    write_param.size = size;
+    BusDevWriteData(g_spi_lora_dev, &write_param);
+
+    BusDevClose(g_spi_lora_dev);
+}
+
+void SX1276ReadBuffer(uint8_t addr, uint8_t *buffer, uint8_t size)
+{
+    struct BusBlockWriteParam write_param;
+    struct BusBlockReadParam read_param;
+
+    uint8 write_addr = addr & 0x7F;
+
+    BusDevOpen(g_spi_lora_dev);
+
+    write_param.buffer = (void *)&write_addr;
+    write_param.size = 1;
+    BusDevWriteData(g_spi_lora_dev, &write_param);
+
+    read_param.buffer = (void *)buffer;
+    read_param.size = size;
+    BusDevReadData(g_spi_lora_dev, &read_param);
+
+    BusDevClose(g_spi_lora_dev);
+}
+
+void SX1276WriteFifo(uint8_t *buffer, uint8_t size)
+{
+    SX1276WriteBuffer(0, buffer, size);
+}
+
+void SX1276ReadFifo(uint8_t *buffer, uint8_t size)
+{
+    SX1276ReadBuffer(0, buffer, size);
+}
+
+uint8_t SX1276_Spi_Check()
+{
+    uint8_t test = 0;
+    KPrintf("SX1276_Spi_Check start\n");
+	tLoRaSettings settings;
+	SX1276Read(REG_LR_VERSION,&test);
+	KPrintf("version code of the chip is %x\n",test);
+	settings.RFFrequency = SX1276LoRaGetRFFrequency();
+	KPrintf("SX1278 Lora parameters are :\nRFFrequency is %d\n",settings.RFFrequency);
+	settings.Power = SX1276LoRaGetRFPower();
+	KPrintf("RFPower is %d\n",settings.Power);
+    settings.SignalBw = SX1276LoRaGetSignalBandwidth();	  
+	KPrintf("SignalBw is %d\n",settings.SignalBw);
+	settings.SpreadingFactor = SX1276LoRaGetSpreadingFactor();
+	KPrintf("SpreadingFactor is %d\n",settings.SpreadingFactor);
+    /*SPI confirm*/
+    SX1276Write(REG_LR_HOPPERIOD, 0x91);  
+    SX1276Read(REG_LR_HOPPERIOD, &test);
+    if (test != 0x91) {
+        return 0;
+    }		
+    return test;
+}
+
+/**
+ * This function supports to write data to the lora.
+ *
+ * @param dev lora dev descriptor
+ * @param write_param lora dev write datacfg param
+ */
+static uint32 SpiLoraWrite(void *dev, struct BusBlockWriteParam *write_param)
+{
+    NULL_PARAM_CHECK(dev);
+    NULL_PARAM_CHECK(write_param);
+
+    if (write_param->size > 256) {
+        KPrintf("SpiLoraWrite ERROR:The message is too long!\n");
+        return ERROR;
+    } else {
+        //Radio->SetTxPacket(write_param->buffer, write_param->size);    
+        //while(Radio->Process() != RF_TX_DONE);
+        SX1276SetTxPacket(write_param->buffer, write_param->size);    
+        while(SX1276Process() != RF_TX_DONE);
+        KPrintf("SpiLoraWrite success!\n");
+    }
+
+    return EOK;
+}
+
+/**
+ * This function supports to read data from the lora.
+ *
+ * @param dev lora dev descriptor
+ * @param read_param lora dev read datacfg param
+ */
+static uint32 SpiLoraRead(void *dev, struct BusBlockReadParam *read_param)
+{
+    NULL_PARAM_CHECK(dev);
+    NULL_PARAM_CHECK(read_param);
+
+    int read_times = 100;
+    
+    //Radio->StartRx();
+    SX1276StartRx();
+    KPrintf("SpiLoraRead Ready!\n");
+
+    while (read_times) {
+        if (SX1276Process() != RF_RX_DONE) {
+            read_times --;
+            MdelayKTask(500);
+        } else {
+            break;
+        }
+    }
+
+    if (read_times > 0) {
+        SX1276GetRxPacket(read_param->buffer, (uint16 *)&read_param->read_length);
+    } else {
+        read_param->read_length = 0;
+    }
+    
+    //while(Radio->Process() != RF_RX_DONE);
+    //Radio->GetRxPacket(read_param->buffer, (uint16 *)&read_param->read_length);     
+    // while(SX1276Process() != RF_RX_DONE);
+    // SX1276GetRxPacket(read_param->buffer, (uint16 *)&read_param->read_length);
+
+    return read_param->read_length;
+}
+
+static uint32 SpiLoraOpen(void *dev)
+{
+    NULL_PARAM_CHECK(dev);
+
+    KPrintf("SpiLoraOpen start\n");
+
+    x_err_t ret = EOK;
+    static x_bool lora_init_status = RET_FALSE;
+
+    if (RET_TRUE == lora_init_status) {
+        return EOK;
+    }
+
+    struct HardwareDev *haldev = (struct HardwareDev *)dev;
+
+    struct SpiHardwareDevice *lora_dev = CONTAINER_OF(haldev, struct SpiHardwareDevice, haldev);
+    NULL_PARAM_CHECK(lora_dev);
+
+    SpiLoraDeviceType spi_lora_dev = CONTAINER_OF(lora_dev, struct SpiLoraDevice, lora_dev);    
+    NULL_PARAM_CHECK(spi_lora_dev);
+
+    struct Driver *spi_drv = spi_lora_dev->spi_dev->haldev.owner_bus->owner_driver;
+
+    struct BusConfigureInfo configure_info;
+    struct SpiMasterParam spi_master_param;
+    spi_master_param.spi_data_bit_width = 8;
+    spi_master_param.spi_work_mode = SPI_MODE_0 | SPI_MSB;
+    spi_master_param.spi_maxfrequency = SPI_LORA_FREQUENCY;
+    spi_master_param.spi_data_endian = 0;
+
+    configure_info.configure_cmd = OPE_CFG;
+    configure_info.private_data = (void *)&spi_master_param;
+    ret = BusDrvConfigure(spi_drv, &configure_info);
+    if (ret) {
+        KPrintf("spi drv OPE_CFG error drv %8p cfg %8p\n", spi_drv, &spi_master_param);
+        return ERROR;
+    }
+
+    configure_info.configure_cmd = OPE_INT;
+    ret = BusDrvConfigure(spi_drv, &configure_info);
+    if (ret) {
+        KPrintf("spi drv OPE_INT error drv %8p\n", spi_drv);
+        return ERROR;
+    }
+
+    SX1276Init();
+
+    if (0x91 != SX1276_Spi_Check()) {
+        KPrintf("LoRa check failed!\n!");
+    } else {
+        Radio = RadioDriverInit();
+        KPrintf("LoRa check ok!\nNote: The length of the message that can be sent in a single time is 256 characters\n");
+    }
+
+    lora_init_status = RET_TRUE;
+    
+    return ret;
+}
+
+static uint32 SpiLoraClose(void *dev)
+{
+    NULL_PARAM_CHECK(dev);
+
+    return EOK;
+}
+
+static const struct LoraDevDone lora_done =
+{
+    .open = SpiLoraOpen,
+    .close = SpiLoraClose,
+    .write = SpiLoraWrite,
+    .read = SpiLoraRead,
+};
+
+/**
+ * This function supports to init spi_lora_dev
+ *
+ * @param bus_name spi bus name
+ * @param dev_name spi dev name
+ * @param drv_name spi drv name
+ * @param flash_name flash dev name
+ */
+SpiLoraDeviceType SpiLoraInit(char *bus_name, char *dev_name, char *drv_name, char *lora_name)
+{
+    NULL_PARAM_CHECK(dev_name);
+    NULL_PARAM_CHECK(drv_name);
+    NULL_PARAM_CHECK(lora_name);
+    NULL_PARAM_CHECK(bus_name);
+
+    x_err_t ret;
+    static HardwareDevType haldev;
+
+    haldev = SpiDeviceFind(dev_name, TYPE_SPI_DEV);
+    if (NONE == haldev) {
+        KPrintf("SpiLoraInit find spi haldev %s error! \n", dev_name);
+        return NONE;
+    }
+
+    SpiLoraDeviceType spi_lora_dev = (SpiLoraDeviceType)malloc(sizeof(struct SpiLoraDevice));
+    if (NONE == spi_lora_dev) {
+        KPrintf("SpiLoraInit malloc spi_lora_dev failed\n");
+        free(spi_lora_dev);
+        return NONE;
+    }
+
+    memset(spi_lora_dev, 0, sizeof(struct SpiLoraDevice));
+
+    spi_lora_dev->spi_dev = CONTAINER_OF(haldev, struct SpiHardwareDevice, haldev);
+
+    spi_lora_dev->lora_dev.spi_dev_flag = RET_TRUE;
+    spi_lora_dev->lora_dev.haldev.dev_done = (struct HalDevDone *)&lora_done;
+
+    spi_lora_dev->spi_dev->haldev.owner_bus->owner_driver = SpiDriverFind(drv_name, TYPE_SPI_DRV);
+    if (NONE == spi_lora_dev->spi_dev->haldev.owner_bus->owner_driver) {
+        KPrintf("SpiLoraInit find spi driver %s error! \n", drv_name);
+        free(spi_lora_dev);
+        return NONE;
+    }
+
+    ret = SpiDeviceRegister(&spi_lora_dev->lora_dev, spi_lora_dev->spi_dev->haldev.private_data, lora_name);
+    if (EOK != ret) {
+        KPrintf("SpiLoraInit SpiDeviceRegister device %s error %d\n", lora_name, ret);
+        free(spi_lora_dev);   
+        return NONE;
+    }
+
+    ret = SpiDeviceAttachToBus(lora_name, bus_name);
+    if (EOK != ret) {
+        KPrintf("SpiLoraInit SpiDeviceAttachToBus device %s error %d\n", lora_name, ret);
+        free(spi_lora_dev);
+        return NONE;
+    }
+
+    g_spi_lora_dev = &spi_lora_dev->spi_dev->haldev;
+
+    return spi_lora_dev;
+}
+
+/**
+ * This function supports to release spi_lora_dev
+ *
+ * @param spi_lora_dev spi lora descriptor
+ */
+uint32 SpiLoraRelease(SpiLoraDeviceType spi_lora_dev)
+{
+    NULL_PARAM_CHECK(spi_lora_dev);
+
+    x_err_t ret;
+
+    DeviceDeleteFromBus(spi_lora_dev->lora_dev.haldev.owner_bus, &spi_lora_dev->lora_dev.haldev);
+
+    free(spi_lora_dev);
+
+    return EOK;
+}
+
+int LoraSx12xxSpiDeviceInit(void)
+{
+#ifdef BSP_USING_SPI2
+    __IO uint32_t tmpreg = 0x00U;
+    RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
+    tmpreg = RCC->AHB1ENR & RCC_AHB1ENR_GPIOAEN;
+    (void)tmpreg;
+
+    if (EOK != HwSpiDeviceAttach(SPI_BUS_NAME_2, SX12XX_SPI_DEVICE_NAME, GPIOC, GPIO_Pin_6)) {
+        return ERROR;
+    }
+
+    if (NONE == SpiLoraInit(SPI_BUS_NAME_2, SX12XX_SPI_DEVICE_NAME, SPI_2_DRV_NAME, SX12XX_DEVICE_NAME)) {
+        return ERROR;
+    }
+
+#endif
+
+    return EOK;
+}
+
+//#define LORA_TEST
+#ifdef LORA_TEST
+/*Just for lora test*/
+static struct Bus *bus;
+static struct HardwareDev *dev;
+static struct Driver *drv;
+
+void LoraOpen(void)
+{
+    x_err_t ret = EOK;
+
+    ret = LoraSx12xxSpiDeviceInit();
+    if (EOK != ret) {
+        KPrintf("LoraSx12xxSpiDeviceInit failed\n");
+        return;
+    }
+
+    bus = BusFind(SPI_BUS_NAME_2);
+    dev = BusFindDevice(bus, SX12XX_DEVICE_NAME);
+    drv = BusFindDriver(bus, SPI_2_DRV_NAME);
+
+    bus->match(drv, dev);
+ 
+    ret = SpiLoraOpen(dev);
+    if (EOK != ret) {
+        KPrintf("LoRa init failed\n");
+        return;
+    }
+
+    KPrintf("LoRa init succeed\n");
+
+    return;
+}
+SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN),
+                                                LoraOpen, LoraOpen,  open lora device and read parameters );
+
+static void LoraReceive(void)
+{
+    struct BusBlockReadParam read_param;
+    memset(&read_param, 0, sizeof(struct BusBlockReadParam));
+
+    read_param.buffer = malloc(SPI_LORA_BUFFER_SIZE);
+
+    SpiLoraRead(dev, &read_param);
+
+    free(read_param.buffer);
+}
+SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0),
+LoraReceive, LoraReceive,  lora wait message );
+
+static void LoraSend(int argc, char *argv[])
+{
+    char Msg[SPI_LORA_BUFFER_SIZE] = {0};
+    struct BusBlockWriteParam write_param;
+    memset(&write_param, 0, sizeof(struct BusBlockWriteParam));
+
+    if (argc == 2) {
+        strncpy(Msg, argv[1], SPI_LORA_BUFFER_SIZE);
+        write_param.buffer = Msg;
+        write_param.size = strlen(Msg);
+
+        SpiLoraWrite(dev, &write_param);
+    }
+}
+SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN),
+LoraSend, LoraSend,  lora send message );
+#endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/spi/third_party_spi_lora/Makefile

@@ -0,0 +1,7 @@
+SRC_DIR +=  src
+
+ifeq ($(ARCH), arm)
+	SRC_DIR += ports
+endif
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/spi/third_party_spi_lora/inc/spi_lora_sx12xx.h

@@ -0,0 +1,95 @@
+/*
+ * Original Copyright (c) 2006-2018, RT-Thread Development Team
+ * Modified Copyright (c) 2020 AIIT XUOS Lab
+ * 
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+
+ * http://www.apache.org/licenses/LICENSE-2.0
+
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-02-25     XiaojieFan     the first version
+ */
+
+/* 
+ * Modified by:     AIIT XUOS Lab
+ * Modified date:   2020-09-01
+ * Description:     
+ */
+/*************************************************
+File name: spi_lora_sx12xx.h
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+
+
+#ifndef __SPI_LORA_SX12XX_H_
+#define __SPI_LORA_SX12XX_H_
+
+#include <xizi.h>
+#include <stdbool.h>
+
+/*!
+ * \brief Gets the SX1272 DIO0 hardware pin status
+ *
+ * \retval status Current hardware pin status [1, 0]
+ */
+uint8_t SX1276ReadDio0(void);
+
+/*!
+ * \brief Gets the SX1272 DIO1 hardware pin status
+ *
+ * \retval status Current hardware pin status [1, 0]
+ */
+uint8_t SX1276ReadDio1(void);
+
+/*!
+ * \brief Gets the SX1272 DIO2 hardware pin status
+ *
+ * \retval status Current hardware pin status [1, 0]
+ */
+uint8_t SX1276ReadDio2(void);
+
+/*!
+ * \brief Gets the SX1272 DIO3 hardware pin status
+ *
+ * \retval status Current hardware pin status [1, 0]
+ */
+uint8_t SX1276ReadDio3(void);
+
+/*!
+ * \brief Gets the SX1272 DIO4 hardware pin status
+ *
+ * \retval status Current hardware pin status [1, 0]
+ */
+uint8_t SX1276ReadDio4(void);
+
+/*!
+ * \brief Gets the SX1272 DIO5 hardware pin status
+ *
+ * \retval status Current hardware pin status [1, 0]
+ */
+uint8_t SX1276ReadDio5(void);
+
+void SX1276Write(uint8_t addr, uint8_t data);
+void SX1276Read(uint8_t addr, uint8_t *data);
+void SX1276WriteBuffer(uint8_t addr, uint8_t *buffer, uint8_t size);
+void SX1276ReadBuffer(uint8_t addr, uint8_t *buffer, uint8_t size);
+void SX1276WriteFifo(uint8_t *buffer, uint8_t size);
+void SX1276ReadFifo(uint8_t *buffer, uint8_t size);
+void SX1276SetReset(uint8_t state);
+uint8_t SX1276_Spi_Check(void);
+void SX1276WriteRxTx(uint8_t txEnable);
+#endif

Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/spi/third_party_spi_lora/ports/Makefile

@@ -0,0 +1,3 @@
+SRC_FILES := sx12xx_device.c
+
+include $(KERNEL_ROOT)/compiler.mk