innov
/
xiuos
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

jh7110 uart debug serial port printing

This commit is contained in:
songyanguang 2024-10-18 11:01:43 +08:00
parent bac1ec5b71
commit c97fa52c5f
5 changed files with 332 additions and 197 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S
View File

@ -9,6 +9,8 @@
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details. * See the Mulan PSL v2 for more details.
*/ */
/* #include <asm/csr.h> */
#include "core.h" #include "core.h"
#define HCR_VALUE (1 << 31) #define HCR_VALUE (1 << 31)
@ -21,14 +23,19 @@
_boot_start: _boot_start:
j primary_cpu_init
j primary_cpu_init j .
j .
primary_cpu_init: primary_cpu_init:
la t0, boot_start_addr
la t1, boot_end_addr
li t2, 0
clear_loop:
bge t0, t1, clear_done
sb t2, 0(t0)
addi t0, t0, 4
j clear_loop
clear_done:
j bootmain j bootmain

14
Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds
View File

@ -42,7 +42,7 @@ ENTRY( _boot_start )
BOOT_STACK_SIZE = 0x4000; BOOT_STACK_SIZE = 0x4000;
MEMORY { MEMORY {
phy_ddr3 (rwx) : ORIGIN = 0x10000000, LENGTH = 1024M phy_ddr3 (rwx) : ORIGIN = 0x40200000, LENGTH = 1024M
vir_ddr3 (rwx) : ORIGIN = 0x000000601040E000, LENGTH = 1024M vir_ddr3 (rwx) : ORIGIN = 0x000000601040E000, LENGTH = 1024M
} }
@ -62,21 +62,21 @@ SECTIONS
boot.o(.text) boot.o(.text)
bootmmu.o(.text .text.*) bootmmu.o(.text .text.*)
/* ns16550.o(.text .text.*) */ ns16550.o(.text .text.*)
boot.o(.rodata .rodata.*) boot.o(.rodata .rodata.*)
bootmmu.o(.rodata .rodata.*) bootmmu.o(.rodata .rodata.*)
/* ns16550.o(.rodata .rodata.*) */ ns16550.o(.rodata .rodata.*)
boot.o(.data .data.*) boot.o(.data .data.*)
bootmmu.o(.data .data.*) bootmmu.o(.data .data.*)
/* ns16550.o(.data .data.*) */ ns16550.o(.data .data.*)
PROVIDE(boot_start_addr = .); PROVIDE(boot_start_addr = .);
boot.o(.bss .bss.* COMMON) boot.o(.bss .bss.* COMMON)
bootmmu.o(.bss .bss.* COMMON) bootmmu.o(.bss .bss.* COMMON)
/* ns16550.o(.bss .bss.* COMMON) */ ns16550.o(.bss .bss.* COMMON)
/* stack for booting code. */ /* stack for booting code. */
. = ALIGN(0x1000); . = ALIGN(0x1000);
@ -89,11 +89,11 @@ SECTIONS
PROVIDE(boot_end_addr = .); PROVIDE(boot_end_addr = .);
} > phy_ddr3 } > phy_ddr3
.text : AT(0x1041C000) { /* AT: 0x40200000 + 0x0041C000 */
.text : AT(0x4061C000) {
. = ALIGN(0x1000); . = ALIGN(0x1000);
*(.text .text.* .gnu.linkonce.t.*) *(.text .text.* .gnu.linkonce.t.*)
} }
. = ALIGN(0x1000); . = ALIGN(0x1000);
.data : { .data : {
*(.data .data.*) *(.data .data.*)

5
Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c
View File

@ -32,6 +32,7 @@ Modification:
#include "mmu.h" #include "mmu.h"
#include "pagetable.h" #include "pagetable.h"
#include "registers.h" #include "registers.h"
#include "ns16550.h"
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
@ -134,6 +135,7 @@ extern void main(void);
static bool _bss_inited = false; static bool _bss_inited = false;
void bootmain() void bootmain()
{ {
_debug_uart_init();
#if 0 #if 0
build_boot_pgdir(); build_boot_pgdir();
load_boot_pgdir(); load_boot_pgdir();
@ -142,7 +144,8 @@ void bootmain()
memset(&kernel_data_begin, 0x00, (size_t)((uint64_t)kernel_data_end - (uint64_t)kernel_data_begin)); memset(&kernel_data_begin, 0x00, (size_t)((uint64_t)kernel_data_end - (uint64_t)kernel_data_begin));
_bss_inited = true; _bss_inited = true;
} }
#endif
main(); main();
#endif
} }

234
Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h
View File

@ -21,6 +21,9 @@
* will not allocate storage for arrays of size 0 * will not allocate storage for arrays of size 0
*/ */
#ifndef __ns16550_h
#define __ns16550_h
#include <stdint.h> #include <stdint.h>
/* /*
@ -29,58 +32,58 @@
*/ */
#define CONFIG_SYS_NS16550_REG_SIZE (-1) #define CONFIG_SYS_NS16550_REG_SIZE (-1)
#define UART_REG(x) \ #define UART_REG(x) \
unsigned char x; \ unsigned char x; \
unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1]; unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
/** /**
* struct ns16550_platdata - information about a NS16550 port * struct ns16550_plat - information about a NS16550 port
* *
* @base: Base register address * @base: Base register address
* @reg_width: IO accesses size of registers (in bytes, 1 or 4)
* @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...) * @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...)
* @reg_offset: Offset to start of registers (normally 0)
* @clock: UART base clock speed in Hz * @clock: UART base clock speed in Hz
* @fcr: Offset of FCR register (normally UART_FCR_DEFVAL)
*/ */
struct ns16550_platdata { struct ns16550_plat {
unsigned long base; unsigned long base;
int reg_shift; int reg_width;
int clock; int reg_shift;
int reg_offset; int reg_offset;
uint32_t fcr; int clock;
uint32_t fcr;
}; };
struct udevice; struct ns16550 {
UART_REG(rbr); /* 0 */
struct NS16550 { UART_REG(ier); /* 1 */
UART_REG(rbr); /* 0 */ UART_REG(fcr); /* 2 */
UART_REG(ier); /* 1 */ UART_REG(lcr); /* 3 */
UART_REG(fcr); /* 2 */ UART_REG(mcr); /* 4 */
UART_REG(lcr); /* 3 */ UART_REG(lsr); /* 5 */
UART_REG(mcr); /* 4 */ UART_REG(msr); /* 6 */
UART_REG(lsr); /* 5 */ UART_REG(spr); /* 7 */
UART_REG(msr); /* 6 */
UART_REG(spr); /* 7 */
#ifdef CONFIG_SOC_DA8XX #ifdef CONFIG_SOC_DA8XX
UART_REG(reg8); /* 8 */ UART_REG(reg8); /* 8 */
UART_REG(reg9); /* 9 */ UART_REG(reg9); /* 9 */
UART_REG(revid1); /* A */ UART_REG(revid1); /* A */
UART_REG(revid2); /* B */ UART_REG(revid2); /* B */
UART_REG(pwr_mgmt); /* C */ UART_REG(pwr_mgmt); /* C */
UART_REG(mdr1); /* D */ UART_REG(mdr1); /* D */
#else #else
UART_REG(mdr1); /* 8 */ UART_REG(mdr1); /* 8 */
UART_REG(reg9); /* 9 */ UART_REG(reg9); /* 9 */
UART_REG(regA); /* A */ UART_REG(regA); /* A */
UART_REG(regB); /* B */ UART_REG(regB); /* B */
UART_REG(regC); /* C */ UART_REG(regC); /* C */
UART_REG(regD); /* D */ UART_REG(regD); /* D */
UART_REG(regE); /* E */ UART_REG(regE); /* E */
UART_REG(uasr); /* F */ UART_REG(uasr); /* F */
UART_REG(scr); /* 10*/ UART_REG(scr); /* 10*/
UART_REG(ssr); /* 11*/ UART_REG(ssr); /* 11*/
#endif
#ifdef CONFIG_DM_SERIAL
struct ns16550_platdata* plat;
#endif #endif
struct ns16550_plat *plat;
}; };
#define thr rbr #define thr rbr
@ -88,42 +91,42 @@ struct NS16550 {
#define dll rbr #define dll rbr
#define dlm ier #define dlm ier
typedef struct NS16550* NS16550_t;
/* /*
* These are the definitions for the FIFO Control Register * These are the definitions for the FIFO Control Register
*/ */
#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ #define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
#define UART_FCR_RXSR 0x02 /* Receiver soft reset */ #define UART_FCR_RXSR 0x02 /* Receiver soft reset */
#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ #define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
/* Ingenic JZ47xx specific UART-enable bit. */ /* Ingenic JZ47xx specific UART-enable bit. */
#define UART_FCR_UME 0x10 #define UART_FCR_UME 0x10
/* Clear & enable FIFOs */ /* Clear & enable FIFOs */
#define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR) #define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | \
UART_FCR_RXSR | \
UART_FCR_TXSR)
/* /*
* These are the definitions for the Modem Control Register * These are the definitions for the Modem Control Register
*/ */
#define UART_MCR_DTR 0x01 /* DTR */ #define UART_MCR_DTR 0x01 /* DTR */
#define UART_MCR_RTS 0x02 /* RTS */ #define UART_MCR_RTS 0x02 /* RTS */
#define UART_MCR_OUT1 0x04 /* Out 1 */ #define UART_MCR_OUT1 0x04 /* Out 1 */
#define UART_MCR_OUT2 0x08 /* Out 2 */ #define UART_MCR_OUT2 0x08 /* Out 2 */
#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */ #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */
#define UART_MCR_DMA_EN 0x04 #define UART_MCR_DMA_EN 0x04
#define UART_MCR_TX_DFR 0x08 #define UART_MCR_TX_DFR 0x08
/* /*
* These are the definitions for the Line Control Register * These are the definitions for the Line Control Register
@ -131,68 +134,85 @@ typedef struct NS16550* NS16550_t;
* Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
* UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
*/ */
#define UART_LCR_WLS_MSK 0x03 /* character length select mask */ #define UART_LCR_WLS_MSK 0x03 /* character length select mask */
#define UART_LCR_WLS_5 0x00 /* 5 bit character length */ #define UART_LCR_WLS_5 0x00 /* 5 bit character length */
#define UART_LCR_WLS_6 0x01 /* 6 bit character length */ #define UART_LCR_WLS_6 0x01 /* 6 bit character length */
#define UART_LCR_WLS_7 0x02 /* 7 bit character length */ #define UART_LCR_WLS_7 0x02 /* 7 bit character length */
#define UART_LCR_WLS_8 0x03 /* 8 bit character length */ #define UART_LCR_WLS_8 0x03 /* 8 bit character length */
#define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */ #define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
#define UART_LCR_PEN 0x08 /* Parity eneble */ #define UART_LCR_PEN 0x08 /* Parity eneble */
#define UART_LCR_EPS 0x10 /* Even Parity Select */ #define UART_LCR_EPS 0x10 /* Even Parity Select */
#define UART_LCR_STKP 0x20 /* Stick Parity */ #define UART_LCR_STKP 0x20 /* Stick Parity */
#define UART_LCR_SBRK 0x40 /* Set Break */ #define UART_LCR_SBRK 0x40 /* Set Break */
#define UART_LCR_BKSE 0x80 /* Bank select enable */ #define UART_LCR_BKSE 0x80 /* Bank select enable */
#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
/* /*
* These are the definitions for the Line Status Register * These are the definitions for the Line Status Register
*/ */
#define UART_LSR_DR 0x01 /* Data ready */ #define UART_LSR_DR 0x01 /* Data ready */
#define UART_LSR_OE 0x02 /* Overrun */ #define UART_LSR_OE 0x02 /* Overrun */
#define UART_LSR_PE 0x04 /* Parity error */ #define UART_LSR_PE 0x04 /* Parity error */
#define UART_LSR_FE 0x08 /* Framing error */ #define UART_LSR_FE 0x08 /* Framing error */
#define UART_LSR_BI 0x10 /* Break */ #define UART_LSR_BI 0x10 /* Break */
#define UART_LSR_THRE 0x20 /* Xmit holding register empty */ #define UART_LSR_THRE 0x20 /* Xmit holding register empty */
#define UART_LSR_TEMT 0x40 /* Xmitter empty */ #define UART_LSR_TEMT 0x40 /* Xmitter empty */
#define UART_LSR_ERR 0x80 /* Error */ #define UART_LSR_ERR 0x80 /* Error */
#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
#define UART_MSR_RI 0x40 /* Ring Indicator */ #define UART_MSR_RI 0x40 /* Ring Indicator */
#define UART_MSR_DSR 0x20 /* Data Set Ready */ #define UART_MSR_DSR 0x20 /* Data Set Ready */
#define UART_MSR_CTS 0x10 /* Clear to Send */ #define UART_MSR_CTS 0x10 /* Clear to Send */
#define UART_MSR_DDCD 0x08 /* Delta DCD */ #define UART_MSR_DDCD 0x08 /* Delta DCD */
#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
#define UART_MSR_DDSR 0x02 /* Delta DSR */ #define UART_MSR_DDSR 0x02 /* Delta DSR */
#define UART_MSR_DCTS 0x01 /* Delta CTS */ #define UART_MSR_DCTS 0x01 /* Delta CTS */
/* /*
* These are the definitions for the Interrupt Identification Register * These are the definitions for the Interrupt Identification Register
*/ */
#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
#define UART_IIR_MSI 0x00 /* Modem status interrupt */ #define UART_IIR_MSI 0x00 /* Modem status interrupt */
#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
/* /*
* These are the definitions for the Interrupt Enable Register * These are the definitions for the Interrupt Enable Register
*/ */
#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
/* useful defaults for LCR */ /* useful defaults for LCR */
#define UART_LCR_8N1 0x03 #define UART_LCR_8N1 0x03
void ns16550_init(struct ns16550 *com_port, int baud_divisor);
void ns16550_putc(struct ns16550 *com_port, char c);
char ns16550_getc(struct ns16550 *com_port);
int ns16550_tstc(struct ns16550 *com_port);
void ns16550_reinit(struct ns16550 *com_port, int baud_divisor);
/**
* ns16550_calc_divisor() - calculate the divisor given clock and baud rate
*
* Given the UART input clock and required baudrate, calculate the divisor
* that should be used.
*
* @port: UART port
* @clock: UART input clock speed in Hz
* @baudrate: Required baud rate
* @return baud rate divisor that should be used
*/
int ns16550_calc_divisor(struct ns16550 *port, int clock, int baudrate);
void NS16550_init(NS16550_t com_port, int baud_divisor);
void NS16550_putc(NS16550_t com_port, char c);
char NS16550_getc(NS16550_t com_port);
int NS16550_tstc(NS16550_t com_port);
void NS16550_reinit(NS16550_t com_port, int baud_divisor);
void _debug_uart_init(void); void _debug_uart_init(void);
void _debug_uart_putc(int ch); void _debug_uart_putc(int ch);
int _debug_uart_getc(void); int _debug_uart_getc(void);
void _debug_uart_printascii(const char *str);
#endif /* __ns16550_h */

255
Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c
View File

@ -4,108 +4,213 @@
* modified to use CONFIG_SYS_ISA_MEM and new defines * modified to use CONFIG_SYS_ISA_MEM and new defines
*/ */
#include <stdint.h> #include <ns16550.h>
#include "mmio_access.h" struct ns16550 g_ns16550_com_port = {0};
#include "ns16550.h" struct ns16550_plat g_ns16550_plat = {0};
//#define UART_ADDR MMIO_P2V_WO(0xFE660000) #define CONFIG_SYS_NS16550_UART_BASE 0x10000000
//#define UART_ADDR (0xFE660000) #define CONFIG_BAUDRATE 115200
#define UART_ADDR MMIO_P2V_WO (10000000) #define CONFIG_SYS_NS16550_CLK 24000000
#define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */
#define UART_MCRVAL (UART_MCR_DTR | UART_MCR_RTS) /* RTS/DTR */
#define out_le32(a, v) (*(volatile uint32_t*)(a) = (v)) #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */
#define in_le32(a) (*(volatile uint32_t*)(a)) #define UART_MCRVAL (UART_MCR_DTR | \
UART_MCR_RTS) /* RTS/DTR */
#ifndef CONFIG_SYS_NS16550_IER #ifndef CONFIG_SYS_NS16550_IER
#define CONFIG_SYS_NS16550_IER 0x00 #define CONFIG_SYS_NS16550_IER 0x00
#endif /* CONFIG_SYS_NS16550_IER */ #endif /* CONFIG_SYS_NS16550_IER */
#define serial_dout(reg, value) \ #define CONFIG_SYS_NS16550_PORT_MAPPED
serial_out_shift((char*)com_port + ((char*)reg - (char*)com_port) * (1 << 2), \
2, value)
#define serial_din(reg) \
serial_in_shift((char*)com_port + ((char*)reg - (char*)com_port) * (1 << 2), \
2)
static inline void serial_out_shift(void* addr, int shift, int value) #define readb(addr) \
({ unsigned char __v = (*(volatile unsigned char *)(addr)); __v; })
#define writeb(b, addr) (void)((*(volatile unsigned char *)(addr)) = (b))
static inline void serial_out_shift(void *addr, int shift, int value)
{ {
out_le32(addr, value); writeb(value, addr);
} }
static inline int serial_in_shift(void* addr, int shift) static inline int serial_in_shift(void *addr, int shift)
{ {
return in_le32(addr); return readb(addr);
} }
#ifndef CONFIG_SYS_NS16550_CLK
#define CONFIG_SYS_NS16550_CLK 0 static void ns16550_writeb(struct ns16550 *port, int offset, int value)
{
struct ns16550_plat *plat = port->plat;
unsigned char *addr;
offset *= 1 << plat->reg_shift;
addr = (unsigned char *)plat->base + offset + plat->reg_offset;
serial_out_shift(addr, plat->reg_shift, value);
}
static int ns16550_readb(struct ns16550 *port, int offset)
{
struct ns16550_plat *plat = port->plat;
unsigned char *addr;
offset *= 1 << plat->reg_shift;
addr = (unsigned char *)plat->base + offset + plat->reg_offset;
return serial_in_shift(addr, plat->reg_shift);
}
static uint32_t ns16550_getfcr(struct ns16550 *port)
{
struct ns16550_plat *plat = port->plat;
return plat->fcr;
}
/* We can clean these up once everything is moved to driver model */
#define serial_out(value, addr) \
ns16550_writeb(com_port, \
(unsigned char *)addr - (unsigned char *)com_port, value)
#define serial_in(addr) \
ns16550_readb(com_port, \
(unsigned char *)addr - (unsigned char *)com_port)
/* Divide positive dividend by positive divisor and round to closest integer. */
#define DIV_ROUND_CLOSEST(x, divisor) \
(((x) + ((divisor) / 2)) / (divisor))
int ns16550_calc_divisor(struct ns16550 *port, int clock, int baudrate)
{
const unsigned int mode_x_div = 16;
return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate);
}
static void ns16550_setbrg(struct ns16550 *com_port, int baud_divisor)
{
/* to keep serial format, read lcr before writing BKSE */
int lcr_val = serial_in(&com_port->lcr) & ~UART_LCR_BKSE;
serial_out(UART_LCR_BKSE | lcr_val, &com_port->lcr);
serial_out(baud_divisor & 0xff, &com_port->dll);
serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
serial_out(lcr_val, &com_port->lcr);
}
void ns16550_init(struct ns16550 *com_port, int baud_divisor)
{
while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT))
;
serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
serial_out(UART_MCRVAL, &com_port->mcr);
serial_out(ns16550_getfcr(com_port), &com_port->fcr);
/* initialize serial config to 8N1 before writing baudrate */
serial_out(UART_LCRVAL, &com_port->lcr);
if (baud_divisor != -1)
ns16550_setbrg(com_port, baud_divisor);
}
void ns16550_putc(struct ns16550 *com_port, char c)
{
while ((serial_in(&com_port->lsr) & UART_LSR_THRE) == 0)
;
serial_out(c, &com_port->thr);
}
char ns16550_getc(struct ns16550 *com_port)
{
while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0)
;
return serial_in(&com_port->rbr);
}
int ns16550_tstc(struct ns16550 *com_port)
{
return (serial_in(&com_port->lsr) & UART_LSR_DR) != 0;
}
static int ns16550_serial_assign_base(struct ns16550_plat *plat, unsigned long base)
{
#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
plat->base = base;
#else
plat->base = (unsigned long)map_physmem(base, 0, MAP_NOCACHE);
#endif #endif
return 0;
#if 0
#define DIV_ROUND_CLOSEST(x, divisor) ( \
{ \
typeof(x) __x = x; \
typeof(divisor) __d = divisor; \
(((typeof(x))-1) > 0 || ((typeof(divisor))-1) > 0 || (__x) > 0) ? (((__x) + ((__d) / 2)) / (__d)) : (((__x) - ((__d) / 2)) / (__d)); \
})
#endif
#define DIV_ROUND_CLOSEST(x, divisor) ( \
{ \
((x) > 0) ? (((x) + ((divisor) / 2)) / (divisor)) : (((x) - ((divisor) / 2)) / (divisor)); \
})
int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate)
{
const unsigned int mode_x_div = 16;
return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate);
} }
static void ns16550_plat_init(void)
{
struct ns16550_plat *plat = &g_ns16550_plat;
unsigned long addr;
addr = CONFIG_SYS_NS16550_UART_BASE;
ns16550_serial_assign_base(plat, addr);
/* refer jh7110 u-boot/arch/riscv/dts/jh7110.dtsi */
plat->reg_offset = 0;
plat->reg_shift = 2;
plat->reg_width = 4;
plat->clock = CONFIG_SYS_NS16550_CLK;
plat->fcr = UART_FCR_DEFVAL;
}
static void ns16550_serial_init(void)
{
struct ns16550_plat *plat = &g_ns16550_plat;
struct ns16550 *com_port = &g_ns16550_com_port;
ns16550_plat_init();
com_port->plat = plat;
ns16550_init(com_port, -1);
}
static void ns16550_serial_setbrg(int baudrate)
{
struct ns16550 *const com_port = &g_ns16550_com_port;
struct ns16550_plat *plat = com_port->plat;
int clock_divisor;
clock_divisor = ns16550_calc_divisor(com_port, plat->clock, baudrate);
ns16550_setbrg(com_port, clock_divisor);
}
void _debug_uart_init(void) void _debug_uart_init(void)
{ {
struct NS16550* com_port = (struct NS16550*)UART_ADDR; int baudrate = CONFIG_BAUDRATE;
/* ns16550_serial_init();
* We copy the code from above because it is already horribly messy. ns16550_serial_setbrg(baudrate);
* Trying to refactor to nicely remove the duplication doesn't seem _debug_uart_printascii("_debug_uart_init success.\n");
* feasible. The better fix is to move all users of this driver to
* driver model.
*/
int baud_divisor = ns16550_calc_divisor(com_port, 24000000,
115200);
serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER);
serial_dout(&com_port->mcr, UART_MCRVAL);
serial_dout(&com_port->fcr, UART_FCR_DEFVAL);
serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
serial_dout(&com_port->dll, baud_divisor & 0xff);
serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff);
serial_dout(&com_port->lcr, UART_LCRVAL);
} }
void _debug_uart_putc(int ch) void _debug_uart_putc(int ch)
{ {
static struct NS16550* com_port = (struct NS16550*)UART_ADDR; struct ns16550* com_port = &g_ns16550_com_port;
ns16550_putc(com_port, ch);
if (ch == '\n') {
_debug_uart_putc('\r');
}
while (!(serial_din(&com_port->lsr) & UART_LSR_THRE))
;
serial_dout(&com_port->thr, ch);
} }
int _debug_uart_getc(void) int _debug_uart_getc(void)
{ {
static struct NS16550* com_port = (struct NS16550*)UART_ADDR; struct ns16550* com_port = &g_ns16550_com_port;
return ns16550_getc(com_port);
while (!(serial_din(&com_port->lsr) & UART_LSR_DR)) }
;
static void _printch(int ch)
return serial_din(&com_port->rbr); {
if (ch == '\n')
_debug_uart_putc('\r');
_debug_uart_putc(ch);
}
void _debug_uart_printascii(const char *str)
{
while (*str)
_printch(*str++);
} }