info stack systick

This commit is contained in:
zhangjin1996 2025-03-28 18:04:55 +08:00
parent 2ac05161bb
commit c8ca531b2d
7 changed files with 74 additions and 199 deletions

View File

@ -41,164 +41,47 @@ Modification:
.text .text
.thumb .thumb
/* Reset Handler */ .word _sidata
.word __data_start__
.word __data_end__
.word __bss_start__
.word __bss_end__
.thumb_func .section .text.Reset_Handler
.align 2 .weak Reset_Handler
.globl Reset_Handler .type Reset_Handler, %function
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler: Reset_Handler:
#ifdef __BOOTLOADER /* BOOT */ ldr sp, =__StackTop
cpsid i /* Mask interrupts */ movs r1, #0
.equ VTOR, 0xE000ED08
ldr r0, =VTOR
ldr r1, =__isr_vector
str r1, [r0]
ldr r2, [r1]
msr msp, r2
ldr r0,=SystemInit /* Copy the data segment initializers from flash to SRAM */
blx r0 DataInit:
ldr r0, =__data_start__
ldr r3, =__data_end__
adds r2, r0, r1
cmp r2, r3
bcs DataInitEnd
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
b DataInit
/* Loop to copy data from read only memory to RAM. The ranges DataInitEnd:
* of copy from/to are specified by following symbols evaluated in ldr r2, =__bss_start__
* linker script.
* __bootloader_end: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* __noncachedata_start__/__noncachedata_end__ : none cachable region
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext /* Zero fill the bss segment. */
ldr r2, =__data_start__ BSSInit:
ldr r3, =__data_end__ ldr r3, = __bss_end__
cmp r2, r3
bcs BSSInitEnd
movs r3, #0
str r3, [r2], #4
b BSSInit
/* Here are two copies of loop implemenations. First one favors code size BSSInitEnd:
* and the second one favors performance. Default uses the first one. bl SystemInit
* Change to "#if 0" to use the second one */
.LoopCopy0:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LoopCopy0
/* This part of work usually is done in C library startup code. Otherwise, bl entry
* define this macro to enable it in this startup. bx lr
* .size Reset_Handler, .-Reset_Handler
* Loop to zero out BSS section, which uses following symbols
* in linker script:
* __bss_start__: start of BSS section. Must align to 4
* __bss_end__: end of BSS section. Must align to 4
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.LoopCopy1:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .LoopCopy1
ldr r0,=ota_entry
blx r0
#else /* APP */
cpsid i /* Mask interrupts */
.equ VTOR, 0xE000ED08
ldr r0, =VTOR
ldr r1, =__isr_vector
str r1, [r0]
ldr r2, [r1]
msr msp, r2
#ifndef __NO_SYSTEM_INIT
ldr r0,=SystemInit
blx r0
#endif
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* __noncachedata_start__/__noncachedata_end__ : none cachable region
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
#if 1
/* Here are two copies of loop implemenations. First one favors code size
* and the second one favors performance. Default uses the first one.
* Change to "#if 0" to use the second one */
.LC0:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LC0
#else
subs r3, r2
ble .LC1
.LC0:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .LC0
.LC1:
#endif
#ifdef __STARTUP_INITIALIZE_NONCACHEDATA
ldr r2, =__noncachedata_start__
ldr r3, =__noncachedata_init_end__
#if 1
.LC2:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LC2
#else
subs r3, r2
ble .LC3
.LC2:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .LC2
.LC3:
#endif
/* zero inited ncache section initialization */
ldr r3, =__noncachedata_end__
movs r0,0
.LC4:
cmp r2,r3
itt lt
strlt r0,[r2],#4
blt .LC4
#endif /* __STARTUP_INITIALIZE_NONCACHEDATA */
#if 1
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* Loop to zero out BSS section, which uses following symbols
* in linker script:
* __bss_start__: start of BSS section. Must align to 4
* __bss_end__: end of BSS section. Must align to 4
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.LC5:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .LC5
#endif /* __STARTUP_CLEAR_BSS */
ldr r0,=entry
blx r0
#endif /* MCUBOOT_BOOTLOADER */
.size Reset_Handler, . - Reset_Handler

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@ -33,11 +33,11 @@
void InitBoardHardware() void InitBoardHardware()
{ {
sys_cache_enable();
HAL_Init(); HAL_Init();
sys_stm32_clock_init(192, 5, 2, 4); sys_stm32_clock_init(192, 5, 2, 4);
delay_init(480); //delay_init(480);
InitHwUart(); InitHwUart();
InitBoardMemory((void*)HEAP_START, (void*)HEAP_END); InitBoardMemory((void*)HEAP_START, (void*)HEAP_END);

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@ -24,11 +24,10 @@
void InitBoardHardware(); void InitBoardHardware();
extern void *__bss_end__;
extern void *_heap_end;
#define HEAP_START ((void *)&__bss_end__)
#define HEAP_END ((void *)&_heap_end) #define HEAP_START 0x24030000
#define HEAP_END 0x24060000

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@ -11,7 +11,7 @@ MEMORY
OUTPUT_ARCH(arm) OUTPUT_ARCH(arm)
ENTRY(Reset_Handler) ENTRY(Reset_Handler)
_system_stack_size = 0x200; _system_stack_size = 0x10000;
SECTIONS SECTIONS
{ {
@ -42,9 +42,6 @@ SECTIONS
__isrtbl_end = .; __isrtbl_end = .;
. = ALIGN(4); . = ALIGN(4);
PROVIDE(g_service_table_start = ABSOLUTE(.));
KEEP(*(.g_service_table))
PROVIDE(g_service_table_end = ABSOLUTE(.));
PROVIDE(_etext = ABSOLUTE(.)); PROVIDE(_etext = ABSOLUTE(.));
@ -78,11 +75,12 @@ SECTIONS
__data_end__ = . ; __data_end__ = . ;
} >sram } >sram
__bss_start__ = .;
.bss : .bss :
{ {
. = ALIGN(4); . = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */ /* This is used by the startup in order to initialize the .bss secion */
__bss_start__ = .;
_sbss = .; _sbss = .;
*(.bss) *(.bss)
@ -92,16 +90,16 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */ /* This is used by the startup in order to initialize the .bss secion */
_ebss = . ; _ebss = . ;
__bss_end__ = .;
} > sram
.stack :
{
. = ALIGN(8);
/* cpu stack */
. = . + _system_stack_size;
__StackTop = .;
} > sram } > sram
__bss_end__ = .;
_end = .; _end = .;
.stack ORIGIN(sram) + LENGTH(sram) - _system_stack_size :
{
PROVIDE( _heap_end = . );
. = _system_stack_size;
PROVIDE( __StackTop = . );
} >sram
} }

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@ -1,7 +1,7 @@
SRC_DIR := libraries SRC_DIR := libraries
ifeq ($(CONFIG_BSP_USING_UART),y) ifeq ($(CONFIG_BSP_USING_UART),y)
SRC_DIR += usart sys delay SRC_DIR += usart sys
endif endif
include $(KERNEL_ROOT)/compiler.mk include $(KERNEL_ROOT)/compiler.mk

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@ -31,7 +31,12 @@ RCC_PeriphCLKInitTypeDef rcc_periph_clk_init_struct = {0};
void sys_cache_enable(void)
{
SCB_EnableICache(); /* ʹÄÜI-Cache */
SCB_EnableDCache(); /* ʹÄÜD-Cache */
SCB->CACR |= SCB_CACR_FORCEWT_Msk; /* ʹÄÜD-CacheÇ¿ÖÆÍ¸Ð´ */
}
/** /**

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@ -22,6 +22,7 @@
#include <connect_uart.h> #include <connect_uart.h>
#include <usart.h> #include <usart.h>
#include <stm32h7xx_hal_cortex.h> #include <stm32h7xx_hal_cortex.h>
#include <stm32h7xx_hal_uart.h>
static struct SerialBus serial_bus_1; static struct SerialBus serial_bus_1;
static struct SerialDriver serial_driver_1; static struct SerialDriver serial_driver_1;
static struct SerialHardwareDevice serial_device_1; static struct SerialHardwareDevice serial_device_1;
@ -75,31 +76,19 @@ static void UartHandler(struct SerialBus *serial_bus, struct SerialDriver *seria
{ {
SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND); SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND);
} }
else HAL_UART_IRQHandler(&(serial_hw_cfg->uart_handle));
{
if (__HAL_UART_GET_FLAG(&(serial_hw_cfg->uart_handle), UART_FLAG_ORE) != RESET)
{
__HAL_UART_CLEAR_OREFLAG(&serial_hw_cfg->uart_handle);
}
if (__HAL_UART_GET_FLAG(&(serial_hw_cfg->uart_handle), UART_FLAG_NE) != RESET)
{
__HAL_UART_CLEAR_NEFLAG(&serial_hw_cfg->uart_handle);
}
if (__HAL_UART_GET_FLAG(&(serial_hw_cfg->uart_handle), UART_FLAG_FE) != RESET)
{
__HAL_UART_CLEAR_FEFLAG(&serial_hw_cfg->uart_handle);
}
if (__HAL_UART_GET_FLAG(&(serial_hw_cfg->uart_handle), UART_FLAG_PE) != RESET)
{
__HAL_UART_CLEAR_PEFLAG(&serial_hw_cfg->uart_handle);
}
}
} }
void UartIsr1(int vector, void *param) void UartIsr1(int vector, void *param)
{ {
/* get serial bus 1 */ /* get serial bus 1 */
UartHandler(&serial_bus_1, &serial_driver_1); x_base lock = 0;
lock = DISABLE_INTERRUPT();
UartHandler(&serial_bus_1, &serial_driver_1);
ENABLE_INTERRUPT(lock);
} }
DECLARE_HW_IRQ(USART1_IRQn, UartIsr1, NONE); DECLARE_HW_IRQ(USART1_IRQn, UartIsr1, NONE);
@ -240,11 +229,12 @@ static int SerialPutChar(struct SerialHardwareDevice *serial_dev, char c)
{ {
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
struct Stm32UartHwCfg *serial_hw_cfg = (struct Stm32UartHwCfg *)serial_cfg->hw_cfg.private_data; struct Stm32UartHwCfg *serial_hw_cfg = (struct Stm32UartHwCfg *)serial_cfg->hw_cfg.private_data;
/* Polling mode. */
HAL_UART_Transmit(&(serial_hw_cfg->uart_handle), (uint8_t *)&c, 1, 100);
// UART_INSTANCE_CLEAR_FUNCTION(&(serial_hw_cfg->uart_handle), UART_FLAG_TC);
UART_INSTANCE_CLEAR_FUNCTION(&(serial_hw_cfg->uart_handle), UART_FLAG_TC); // serial_hw_cfg->uart_handle.Instance->TDR = c;
// while (__HAL_UART_GET_FLAG(&(serial_hw_cfg->uart_handle), UART_FLAG_TC) == RESET);
serial_hw_cfg->uart_handle.Instance->RDR = c;
while (__HAL_UART_GET_FLAG(&(serial_hw_cfg->uart_handle), UART_FLAG_TC) == RESET);
return EOK; return EOK;
} }