info stack systick
This commit is contained in:
parent
2ac05161bb
commit
c8ca531b2d
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@ -41,164 +41,47 @@ Modification:
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.text
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.text
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.thumb
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.thumb
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/* Reset Handler */
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.word _sidata
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.word __data_start__
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.word __data_end__
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.word __bss_start__
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.word __bss_end__
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.thumb_func
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.section .text.Reset_Handler
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.align 2
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.globl Reset_Handler
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.weak Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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.type Reset_Handler, %function
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Reset_Handler:
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Reset_Handler:
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#ifdef __BOOTLOADER /* BOOT */
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ldr sp, =__StackTop
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cpsid i /* Mask interrupts */
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movs r1, #0
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.equ VTOR, 0xE000ED08
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ldr r0, =VTOR
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ldr r1, =__isr_vector
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str r1, [r0]
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ldr r2, [r1]
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msr msp, r2
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ldr r0,=SystemInit
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/* Copy the data segment initializers from flash to SRAM */
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blx r0
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DataInit:
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ldr r0, =__data_start__
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/* Loop to copy data from read only memory to RAM. The ranges
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* of copy from/to are specified by following symbols evaluated in
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* linker script.
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* __bootloader_end: End of code section, i.e., begin of data sections to copy from.
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* __data_start__/__data_end__: RAM address range that data should be
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* __noncachedata_start__/__noncachedata_end__ : none cachable region
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* copied to. Both must be aligned to 4 bytes boundary. */
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ldr r1, =__etext
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ldr r2, =__data_start__
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ldr r3, =__data_end__
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ldr r3, =__data_end__
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adds r2, r0, r1
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/* Here are two copies of loop implemenations. First one favors code size
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* and the second one favors performance. Default uses the first one.
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* Change to "#if 0" to use the second one */
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.LoopCopy0:
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cmp r2, r3
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cmp r2, r3
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ittt lt
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bcs DataInitEnd
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ldrlt r0, [r1], #4
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ldr r3, =_sidata
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strlt r0, [r2], #4
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ldr r3, [r3, r1]
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blt .LoopCopy0
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str r3, [r0, r1]
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adds r1, r1, #4
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b DataInit
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/* This part of work usually is done in C library startup code. Otherwise,
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DataInitEnd:
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* define this macro to enable it in this startup.
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ldr r2, =__bss_start__
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*
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* Loop to zero out BSS section, which uses following symbols
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* in linker script:
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* __bss_start__: start of BSS section. Must align to 4
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* __bss_end__: end of BSS section. Must align to 4
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*/
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ldr r1, =__bss_start__
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ldr r2, =__bss_end__
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movs r0, 0
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/* Zero fill the bss segment. */
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.LoopCopy1:
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BSSInit:
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cmp r1, r2
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ldr r3, = __bss_end__
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itt lt
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strlt r0, [r1], #4
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blt .LoopCopy1
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ldr r0,=ota_entry
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blx r0
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#else /* APP */
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cpsid i /* Mask interrupts */
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.equ VTOR, 0xE000ED08
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ldr r0, =VTOR
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ldr r1, =__isr_vector
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str r1, [r0]
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ldr r2, [r1]
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msr msp, r2
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#ifndef __NO_SYSTEM_INIT
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ldr r0,=SystemInit
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blx r0
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#endif
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/* Loop to copy data from read only memory to RAM. The ranges
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* of copy from/to are specified by following symbols evaluated in
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* linker script.
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* __etext: End of code section, i.e., begin of data sections to copy from.
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* __data_start__/__data_end__: RAM address range that data should be
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* __noncachedata_start__/__noncachedata_end__ : none cachable region
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* copied to. Both must be aligned to 4 bytes boundary. */
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ldr r1, =__etext
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ldr r2, =__data_start__
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ldr r3, =__data_end__
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#if 1
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/* Here are two copies of loop implemenations. First one favors code size
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* and the second one favors performance. Default uses the first one.
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* Change to "#if 0" to use the second one */
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.LC0:
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cmp r2, r3
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cmp r2, r3
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ittt lt
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bcs BSSInitEnd
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ldrlt r0, [r1], #4
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movs r3, #0
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strlt r0, [r2], #4
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str r3, [r2], #4
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blt .LC0
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b BSSInit
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#else
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subs r3, r2
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ble .LC1
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.LC0:
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subs r3, #4
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ldr r0, [r1, r3]
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str r0, [r2, r3]
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bgt .LC0
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.LC1:
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#endif
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#ifdef __STARTUP_INITIALIZE_NONCACHEDATA
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ldr r2, =__noncachedata_start__
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ldr r3, =__noncachedata_init_end__
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#if 1
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.LC2:
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cmp r2, r3
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ittt lt
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ldrlt r0, [r1], #4
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strlt r0, [r2], #4
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blt .LC2
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#else
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subs r3, r2
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ble .LC3
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.LC2:
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subs r3, #4
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ldr r0, [r1, r3]
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str r0, [r2, r3]
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bgt .LC2
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.LC3:
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#endif
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/* zero inited ncache section initialization */
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ldr r3, =__noncachedata_end__
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movs r0,0
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.LC4:
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cmp r2,r3
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itt lt
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strlt r0,[r2],#4
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blt .LC4
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#endif /* __STARTUP_INITIALIZE_NONCACHEDATA */
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#if 1
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BSSInitEnd:
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/* This part of work usually is done in C library startup code. Otherwise,
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bl SystemInit
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* define this macro to enable it in this startup.
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*
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* Loop to zero out BSS section, which uses following symbols
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* in linker script:
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* __bss_start__: start of BSS section. Must align to 4
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* __bss_end__: end of BSS section. Must align to 4
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*/
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ldr r1, =__bss_start__
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ldr r2, =__bss_end__
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movs r0, 0
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.LC5:
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cmp r1, r2
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itt lt
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strlt r0, [r1], #4
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blt .LC5
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#endif /* __STARTUP_CLEAR_BSS */
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ldr r0,=entry
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blx r0
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#endif /* MCUBOOT_BOOTLOADER */
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bl entry
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bx lr
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.size Reset_Handler, .-Reset_Handler
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.size Reset_Handler, .-Reset_Handler
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@ -33,11 +33,11 @@
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void InitBoardHardware()
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void InitBoardHardware()
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{
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{
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sys_cache_enable();
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HAL_Init();
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HAL_Init();
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sys_stm32_clock_init(192, 5, 2, 4);
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sys_stm32_clock_init(192, 5, 2, 4);
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delay_init(480);
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//delay_init(480);
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InitHwUart();
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InitHwUart();
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InitBoardMemory((void*)HEAP_START, (void*)HEAP_END);
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InitBoardMemory((void*)HEAP_START, (void*)HEAP_END);
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void InitBoardHardware();
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void InitBoardHardware();
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extern void *__bss_end__;
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extern void *_heap_end;
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#define HEAP_START ((void *)&__bss_end__)
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#define HEAP_END ((void *)&_heap_end)
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#define HEAP_START 0x24030000
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#define HEAP_END 0x24060000
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@ -11,7 +11,7 @@ MEMORY
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OUTPUT_ARCH(arm)
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OUTPUT_ARCH(arm)
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ENTRY(Reset_Handler)
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ENTRY(Reset_Handler)
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_system_stack_size = 0x200;
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_system_stack_size = 0x10000;
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SECTIONS
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SECTIONS
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{
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{
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__isrtbl_end = .;
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__isrtbl_end = .;
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. = ALIGN(4);
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. = ALIGN(4);
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PROVIDE(g_service_table_start = ABSOLUTE(.));
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KEEP(*(.g_service_table))
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PROVIDE(g_service_table_end = ABSOLUTE(.));
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PROVIDE(_etext = ABSOLUTE(.));
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PROVIDE(_etext = ABSOLUTE(.));
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@ -78,11 +75,12 @@ SECTIONS
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__data_end__ = . ;
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__data_end__ = . ;
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} >sram
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} >sram
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__bss_start__ = .;
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.bss :
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.bss :
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{
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{
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. = ALIGN(4);
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .bss secion */
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/* This is used by the startup in order to initialize the .bss secion */
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__bss_start__ = .;
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_sbss = .;
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_sbss = .;
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*(.bss)
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*(.bss)
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@ -92,16 +90,16 @@ SECTIONS
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. = ALIGN(4);
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .bss secion */
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/* This is used by the startup in order to initialize the .bss secion */
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_ebss = . ;
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_ebss = . ;
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} > sram
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__bss_end__ = .;
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__bss_end__ = .;
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} > sram
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.stack :
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{
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. = ALIGN(8);
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/* cpu stack */
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. = . + _system_stack_size;
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__StackTop = .;
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} > sram
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_end = .;
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_end = .;
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.stack ORIGIN(sram) + LENGTH(sram) - _system_stack_size :
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{
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PROVIDE( _heap_end = . );
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. = _system_stack_size;
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PROVIDE( __StackTop = . );
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} >sram
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}
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}
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@ -1,7 +1,7 @@
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SRC_DIR := libraries
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SRC_DIR := libraries
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ifeq ($(CONFIG_BSP_USING_UART),y)
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ifeq ($(CONFIG_BSP_USING_UART),y)
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SRC_DIR += usart sys delay
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SRC_DIR += usart sys
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endif
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endif
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include $(KERNEL_ROOT)/compiler.mk
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include $(KERNEL_ROOT)/compiler.mk
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@ -31,7 +31,12 @@ RCC_PeriphCLKInitTypeDef rcc_periph_clk_init_struct = {0};
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void sys_cache_enable(void)
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{
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SCB_EnableICache(); /* ʹÄÜI-Cache */
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SCB_EnableDCache(); /* ʹÄÜD-Cache */
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SCB->CACR |= SCB_CACR_FORCEWT_Msk; /* ʹÄÜD-CacheÇ¿ÖÆÍ¸Ð´ */
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}
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/**
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/**
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@ -22,6 +22,7 @@
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#include <connect_uart.h>
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#include <connect_uart.h>
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#include <usart.h>
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#include <usart.h>
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#include <stm32h7xx_hal_cortex.h>
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#include <stm32h7xx_hal_cortex.h>
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#include <stm32h7xx_hal_uart.h>
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static struct SerialBus serial_bus_1;
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static struct SerialBus serial_bus_1;
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static struct SerialDriver serial_driver_1;
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static struct SerialDriver serial_driver_1;
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static struct SerialHardwareDevice serial_device_1;
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static struct SerialHardwareDevice serial_device_1;
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@ -75,32 +76,20 @@ static void UartHandler(struct SerialBus *serial_bus, struct SerialDriver *seria
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{
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{
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SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND);
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SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND);
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}
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}
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else
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HAL_UART_IRQHandler(&(serial_hw_cfg->uart_handle));
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{
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if (__HAL_UART_GET_FLAG(&(serial_hw_cfg->uart_handle), UART_FLAG_ORE) != RESET)
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{
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__HAL_UART_CLEAR_OREFLAG(&serial_hw_cfg->uart_handle);
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}
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if (__HAL_UART_GET_FLAG(&(serial_hw_cfg->uart_handle), UART_FLAG_NE) != RESET)
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{
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__HAL_UART_CLEAR_NEFLAG(&serial_hw_cfg->uart_handle);
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}
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if (__HAL_UART_GET_FLAG(&(serial_hw_cfg->uart_handle), UART_FLAG_FE) != RESET)
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{
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__HAL_UART_CLEAR_FEFLAG(&serial_hw_cfg->uart_handle);
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}
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if (__HAL_UART_GET_FLAG(&(serial_hw_cfg->uart_handle), UART_FLAG_PE) != RESET)
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{
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__HAL_UART_CLEAR_PEFLAG(&serial_hw_cfg->uart_handle);
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}
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}
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}
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}
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void UartIsr1(int vector, void *param)
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void UartIsr1(int vector, void *param)
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{
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{
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/* get serial bus 1 */
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/* get serial bus 1 */
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x_base lock = 0;
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lock = DISABLE_INTERRUPT();
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UartHandler(&serial_bus_1, &serial_driver_1);
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UartHandler(&serial_bus_1, &serial_driver_1);
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ENABLE_INTERRUPT(lock);
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}
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}
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DECLARE_HW_IRQ(USART1_IRQn, UartIsr1, NONE);
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DECLARE_HW_IRQ(USART1_IRQn, UartIsr1, NONE);
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@ -240,11 +229,12 @@ static int SerialPutChar(struct SerialHardwareDevice *serial_dev, char c)
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{
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{
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struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
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struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
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struct Stm32UartHwCfg *serial_hw_cfg = (struct Stm32UartHwCfg *)serial_cfg->hw_cfg.private_data;
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struct Stm32UartHwCfg *serial_hw_cfg = (struct Stm32UartHwCfg *)serial_cfg->hw_cfg.private_data;
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/* Polling mode. */
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HAL_UART_Transmit(&(serial_hw_cfg->uart_handle), (uint8_t *)&c, 1, 100);
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// UART_INSTANCE_CLEAR_FUNCTION(&(serial_hw_cfg->uart_handle), UART_FLAG_TC);
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UART_INSTANCE_CLEAR_FUNCTION(&(serial_hw_cfg->uart_handle), UART_FLAG_TC);
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// serial_hw_cfg->uart_handle.Instance->TDR = c;
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// while (__HAL_UART_GET_FLAG(&(serial_hw_cfg->uart_handle), UART_FLAG_TC) == RESET);
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serial_hw_cfg->uart_handle.Instance->RDR = c;
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while (__HAL_UART_GET_FLAG(&(serial_hw_cfg->uart_handle), UART_FLAG_TC) == RESET);
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return EOK;
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return EOK;
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}
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}
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