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Support armv8 smp

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This commit is contained in:
TXuian
2024-05-28 15:11:38 +08:00
parent 6114b4618f
commit bd7966c5a3
9 changed files with 26 additions and 76 deletions
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Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/core.h
+1 -1
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@@ -73,7 +73,7 @@ Modification:
#include "cortex_a72.h"
#define NR_CPU 1 // maximum number of CPUs
#define NR_CPU 4 // maximum number of CPUs
__attribute__((always_inline)) static inline uint64_t EL0_mode() // Set ARM mode to EL0
{
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/Makefile
+2 -3
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@@ -1,6 +1,5 @@
SRC_FILES := boot.S \
start.c \
smp.c \
cortexA72.S
smp.c \
cortexA72.S
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/config.mk
+1 -1
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@@ -1,6 +1,6 @@
export CROSS_COMPILE ?= aarch64-none-elf-
export DEVICE = -mtune=cortex-a72 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie
export CFLAGS := $(DEVICE) -Wall -Werror -O0 -g -fno-omit-frame-pointer -fPIC
export CFLAGS := $(DEVICE) -Wall -Werror -O2 -g -fno-omit-frame-pointer -fPIC
# export AFLAGS := -c $(DEVICE) -x assembler-with-cpp -D__ASSEMBLY__ -gdwarf-2
export LFLAGS := $(DEVICE) -Wl,-T -Wl,$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/nxp_ls1028.lds -Wl,--start-group,-lgcc,-lc,--end-group
export CXXFLAGS :=
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/cortexA72.S
+4 -39
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@@ -14,35 +14,6 @@ Modification:
1. No modifications
*************************************************/
.section ".text","ax"
/*
* bool arm_set_interrupt_state(bool enable)
*/
.global arm_set_interrupt_state
.func arm_set_interrupt_state
arm_set_interrupt_state:
mrs x2, spsr_el1
cmp x0, #0
b.eq disable_interrupts
bic x1, x2, #0xc0 // disable IRQ and FIQ
b set_interrupt_state_end
disable_interrupts:
orr x1, x2, #0xc0 // enable IRQ and FIQ
set_interrupt_state_end:
msr spsr_el1, x1
// 测试x2的第7位（FIQ位）
tst x2, #0x80
mov x0, #1 //
b.eq fiq_set_to_0 //
ret
fiq_set_to_0:
mov x0, #0 // 如果FIQ位被设置，则设置x0为0
ret
.endfunc
.global cpu_get_current
# int cpu_get_current(void)@
@@ -54,17 +25,11 @@ cpu_get_current:
ret
.endfunc
.global get_arm_private_peripheral_base
# uint32_t get_arm_private_peripheral_base(void)
.func get_arm_private_peripheral_base
get_arm_private_peripheral_base:
.global psci_call
psci_call:
hvc #0
ret
# Get base address of private perpherial space
# mrc p15, 4, r0, c15, c0, 0 Read periph base address
mov x0, #0x00A00000
ret
.endfunc
# ------------------------------------------------------------
# End of cortexA72.s
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/smp.c
+5 -2
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@@ -45,12 +45,15 @@ Author: AIIT XUOS Lab
Modification:
1. No modifications
*************************************************/
#include "cortex_a72.h"
#include <stdint.h>
#define PSCI_CPUON 0xc4000003
extern void _boot_start();
void psci_call(uint64_t fn, uint8_t cpuid, uint64_t entry, uint64_t ctxid);
void cpu_start_secondary(uint8_t cpu_id)
{
return;
psci_call(PSCI_CPUON, cpu_id, (uintptr_t)&_boot_start, 0);
}
void start_smp_cache_broadcast(int cpu_id)
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/start.c
-18
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@@ -1,18 +0,0 @@
#include "core.h"
#include "cortex_a72.h"
#include "memlayout.h"
// void _entry();
void _boot_start();
void main();
extern char end[];
// entry.S needs one stack per CPU.
__attribute__((aligned(16))) char stack0[4096 * NR_CPU];
// entry.S jumps here in supervisor mode (EL1) on stack0.
// in qemu-system-aarch64, default EL (Exeception Level) is 1.
void start()
{
main();
}