From bac1ec5b717377f8866ebcd7c0a6994f2a5c734d Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 15 Oct 2024 10:35:00 +0800 Subject: [PATCH] Add xiuos jh7110 code can be compiled. --- Ubiquitous/XiZi_AIoT/.config | 18 -- Ubiquitous/XiZi_AIoT/Makefile | 8 +- Ubiquitous/XiZi_AIoT/hardkernel/arch/Makefile | 5 + .../XiZi_AIoT/hardkernel/arch/riscv/Makefile | 5 + .../hardkernel/arch/riscv/rv64gc/Makefile | 4 + .../arch/riscv/rv64gc/context_switch.S | 30 ++ .../hardkernel/arch/riscv/rv64gc/core.c | 74 +++++ .../hardkernel/arch/riscv/rv64gc/core.h | 218 +++++++++++++++ .../riscv/rv64gc/preboot_for_jh7110/Makefile | 6 + .../riscv/rv64gc/preboot_for_jh7110/boot.S | 34 +++ .../riscv/rv64gc/preboot_for_jh7110/config.mk | 17 ++ .../riscv/rv64gc/preboot_for_jh7110/cortex.S | 34 +++ .../preboot_for_jh7110/include/cortex.h | 241 ++++++++++++++++ .../preboot_for_jh7110/include/registers.h | 110 ++++++++ .../rv64gc/preboot_for_jh7110/jh7110.lds | 136 +++++++++ .../riscv/rv64gc/preboot_for_jh7110/smp.c | 84 ++++++ .../rv64gc/preboot_for_jh7110/xizi_smp.S | 17 ++ .../XiZi_AIoT/hardkernel/cache/L1/Makefile | 5 + .../hardkernel/cache/L1/riscv/Makefile | 5 + .../hardkernel/cache/L1/riscv/rv64gc/Makefile | 3 + .../hardkernel/cache/L1/riscv/rv64gc/cache.S | 184 +++++++++++++ .../cache/L1/riscv/rv64gc/l1_cache.c | 81 ++++++ .../cache/L1/riscv/rv64gc/l1_cache.h | 76 +++++ .../XiZi_AIoT/hardkernel/clock/Makefile | 7 +- .../XiZi_AIoT/hardkernel/clock/riscv/Makefile | 5 + .../hardkernel/clock/riscv/rv64gc/Makefile | 4 + .../hardkernel/clock/riscv/rv64gc/clock.c | 95 +++++++ .../clock/riscv/rv64gc/jh7110/Makefile | 4 + .../clock/riscv/rv64gc/jh7110/clock.c | 95 +++++++ .../rv64gc/jh7110/include/generic_timer.h | 54 ++++ Ubiquitous/XiZi_AIoT/hardkernel/intr/Makefile | 6 + .../XiZi_AIoT/hardkernel/intr/riscv/Makefile | 5 + .../hardkernel/intr/riscv/rv64gc/Makefile | 9 + .../intr/riscv/rv64gc/error_debug.c | 67 +++++ .../intr/riscv/rv64gc/gicv3/Makefile | 3 + .../intr/riscv/rv64gc/gicv3/gicv3.c | 260 ++++++++++++++++++ .../riscv/rv64gc/gicv3/gicv3_common_opa.h | 140 ++++++++++ .../intr/riscv/rv64gc/gicv3/gicv3_registers.h | 59 ++++ .../intr/riscv/rv64gc/hard_spinlock.S | 72 +++++ .../riscv/rv64gc/jh7110/exception_registers.h | 68 +++++ .../intr/riscv/rv64gc/jh7110/irq_numbers.h | 110 ++++++++ .../intr/riscv/rv64gc/jh7110/trap.c | 121 ++++++++ .../intr/riscv/rv64gc/jh7110/trap_common.c | 137 +++++++++ .../hardkernel/intr/riscv/rv64gc/trampoline.S | 112 ++++++++ Ubiquitous/XiZi_AIoT/hardkernel/mmu/Makefile | 5 + .../XiZi_AIoT/hardkernel/mmu/riscv/Makefile | 4 + .../hardkernel/mmu/riscv/rv64gc/Makefile | 3 + .../hardkernel/mmu/riscv/rv64gc/bootmmu.c | 148 ++++++++++ .../hardkernel/mmu/riscv/rv64gc/include/mmu.h | 118 ++++++++ .../mmu/riscv/rv64gc/jh7110/memlayout.h | 85 ++++++ .../hardkernel/mmu/riscv/rv64gc/mmu.c | 93 +++++++ .../mmu/riscv/rv64gc/pagetable_attr.c | 80 ++++++ Ubiquitous/XiZi_AIoT/hardkernel/uart/Makefile | 6 + .../XiZi_AIoT/hardkernel/uart/riscv/Makefile | 5 + .../hardkernel/uart/riscv/rv64gc/Makefile | 3 + .../riscv/rv64gc/uart_io_for_jh7110/Makefile | 3 + .../uart_io_for_jh7110/include/ns16550.h | 198 +++++++++++++ .../rv64gc/uart_io_for_jh7110/include/uart.h | 29 ++ .../riscv/rv64gc/uart_io_for_jh7110/ns16550.c | 111 ++++++++ .../riscv/rv64gc/uart_io_for_jh7110/uart.c | 45 +++ Ubiquitous/XiZi_AIoT/path_kernel.mk | 15 + Ubiquitous/XiZi_AIoT/softkernel/load_apps.S | 6 +- .../XiZi_AIoT/softkernel/memory/Makefile | 3 + 63 files changed, 3764 insertions(+), 24 deletions(-) delete mode 100644 Ubiquitous/XiZi_AIoT/.config create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/context_switch.S create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/config.mk create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/cortex.S create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/cortex.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/registers.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/smp.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/xizi_smp.S create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/cache.S create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/l1_cache.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/l1_cache.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/clock.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/clock.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/include/generic_timer.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/error_debug.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_common_opa.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_registers.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/exception_registers.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/irq_numbers.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/include/mmu.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/pagetable_attr.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/uart.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/uart.c diff --git a/Ubiquitous/XiZi_AIoT/.config b/Ubiquitous/XiZi_AIoT/.config deleted file mode 100644 index a40a1d2b4..000000000 --- a/Ubiquitous/XiZi_AIoT/.config +++ /dev/null @@ -1,18 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# XiZi_AIoT Project Configuration -# -CONFIG_BOARD_IMX6Q_SABRELITE=y -CONFIG_ARCH_ARM=y - -# -# imx6q sabrelite feature -# - -# -# Lib -# -CONFIG_LIB=y -CONFIG_LIB_POSIX=y -CONFIG_LIB_NEWLIB=y -# CONFIG_LIB_MUSLLIB is not set diff --git a/Ubiquitous/XiZi_AIoT/Makefile b/Ubiquitous/XiZi_AIoT/Makefile index 4bc6e3b00..c78e94350 100755 --- a/Ubiquitous/XiZi_AIoT/Makefile +++ b/Ubiquitous/XiZi_AIoT/Makefile @@ -3,7 +3,7 @@ MAKEFLAGS += --no-print-directory .PHONY:all clean distclean show_info menuconfig .PHONY:COMPILE_APP COMPILE_KERNEL -riscv_support := +riscv_support := jh7110 arm_support += imx6q-sabrelite zynq7000-zc702 3568 emulator_support += support := $(riscv_support) $(arm_support) $(emulator_support) @@ -37,13 +37,17 @@ endif ifneq ($(findstring $(BOARD), 3568), ) include $(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_$(BOARD)/config.mk endif +ifneq ($(findstring $(BOARD), jh7110), ) +include $(KERNEL_ROOT)/hardkernel/arch/riscv/rv64gc/preboot_for_$(BOARD)/config.mk +endif export BSP_BUILD_DIR := $(KERNEL_ROOT) export HOSTTOOLS_DIR ?= $(KERNEL_ROOT)/services/tools/hosttools export CONFIG2H_EXE ?= $(HOSTTOOLS_DIR)/xsconfig.sh export CPPPATHS export SRC_APP_DIR := ../../APP_Framework -export SRC_KERNEL_DIR := hardkernel kernel_actracer services softkernel +# export SRC_KERNEL_DIR := hardkernel kernel_actracer services softkernel +export SRC_KERNEL_DIR := hardkernel kernel_actracer softkernel export SRC_DIR := $(SRC_KERNEL_DIR) export LIBCC diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/arch/Makefile index 2765b4d99..4972e6661 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/Makefile @@ -1,3 +1,8 @@ +ifneq ($(findstring $(BOARD), 3568 imx6q-sabrelite zynq7000-zc702), ) SRC_DIR := arm +endif +ifneq ($(findstring $(BOARD), jh7110), ) +SRC_DIR := riscv +endif include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/Makefile new file mode 100644 index 000000000..dd587adc4 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/Makefile @@ -0,0 +1,5 @@ +ifneq ($(findstring $(BOARD), jh7110), ) +SRC_DIR := rv64gc +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/Makefile new file mode 100644 index 000000000..f4cbabfc4 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/Makefile @@ -0,0 +1,4 @@ +SRC_DIR := preboot_for_$(BOARD) +SRC_FILES := context_switch.S core.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/context_switch.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/context_switch.S new file mode 100644 index 000000000..681c13524 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/context_switch.S @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file context_switch.S + * @brief task context switch functions + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.4.10 + */ + +/************************************************* +File name: context_switch.S +Description: task context switch functions +Others: +History: +*************************************************/ +.global context_switch + +context_switch: + nop + ret \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.c b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.c new file mode 100644 index 000000000..e677d92d6 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.c @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file core.c + * @brief spl boot function + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.04.23 + */ + +/************************************************* +File name: core.c +Description: cortex-a9 core function, include cpu registers operations、core boot +Others: +History: +1. Date: 2024-04-23 +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ + +/*********cortex-a55 general register************ + EL0 | EL1 | EL2 | EL3 + + x0; + x1; + x2; + x3; + x4; + x5; + x6; + x7; + x8; + x9; + x10; + x11; + x12; + x13; + x14; + x15; + x16; + x17; + x18; + x19; + x20; + x21; + x22; + x23; + x24; + x25; + x26; + x27; + x28; + x29; + x30; +*********cortex-a55 special register************ + XZR + PC + SP_EL0 SP_EL1 SP_EL2 SP_EL3 + SPSR_EL1 SPSR_EL2 SPSR_EL3 + ELR_EL1 ELR_EL2 ELR_EL3 +************************************************/ + +#include "core.h" \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h new file mode 100644 index 000000000..9267f1f04 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file core.h + * @brief cortex-a55 core function + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.04.11 + */ + +/************************************************* +File name: core.h +Description: cortex-a55 core function +Others: +History: +Author: AIIT XUOS Lab +Modification: +*************************************************/ + +#pragma once + +// Interrupt control bits +#define NO_INT 0x80 // disable IRQ. +#define DIS_INT 0xc0 // disable both IRQ and FIQ. + +#define MODE_STACK_SIZE 0x1000 + +//! @name SPSR fields +//@{ +#define SPSR_EL1_N (1 << 31) //!< Negative +#define SPSR_EL1_Z (1 << 30) //!< Zero +#define SPSR_EL1_C (1 << 29) //!< Carry +#define SPSR_EL1_V (1 << 28) //!< Overflow +#define SPSR_EL1_SS (1 << 21) //!< Software Step +#define SPSR_EL1_IL (1 << 20) //!< Illegal Exception +#define SPSR_EL1_D (1 << 9) //!< Debug mask +#define SPSR_EL1_A (1 << 8) //!< SError mask +#define SPSR_EL1_I (1 << 7) //!< IRQ mask +#define SPSR_EL1_F (1 << 6) //!< FIQ mask +#define SPSR_EL1_M (1 << 4) //!< Execution state 0=64-bit 1=32-bit +#define SPSR_EL1_MODE (0x7) //!< Current processor mode +//@} + +//! @name Interrupt enable bits in SPSR +//@{ +#define I_BIT 0x80 //!< When I bit is set, IRQ is disabled +#define F_BIT 0x40 //!< When F bit is set, FIQ is disabled +//@} + +// ARM Modes t indicates selecting sp_el0 pointer, h indicates selecting sp_eln pointer +#define SPSR_MODE_MASK 0x0f +#define ARM_MODE_EL0_t 0x00 +#define ARM_MODE_EL1_t 0x04 +#define ARM_MODE_EL1_h 0x05 +#define ARM_MODE_EL2_t 0x08 +#define ARM_MODE_EL2_h 0x09 +#define ARM_MODE_EL3_t 0x0c +#define ARM_MODE_EL3_h 0x0d + +#ifndef __ASSEMBLER__ +#include +#include + +#include "cortex.h" + +#define NR_CPU 4 // maximum number of CPUs + +__attribute__((always_inline)) static inline uint64_t EL0_mode() // Set ARM mode to EL0 +{ + uint64_t val = 0; + + return val; +} + +__attribute__((always_inline, optimize("O0"))) static inline void cpu_into_low_power() +{ + WFE(); +} + +__attribute__((always_inline, optimize("O0"))) static inline void cpu_leave_low_power() +{ + SEV(); +} + +struct context { + uint64_t sp; + + /* callee register */ + uint64_t x18; + uint64_t x19; + uint64_t x20; + uint64_t x21; + uint64_t x22; + uint64_t x23; + uint64_t x24; + uint64_t x25; + uint64_t x26; + uint64_t x27; + uint64_t x28; + uint64_t x29; + uint64_t x30; +}; + +/// @brief init task context, set return address to trap return +/// @param ctx +extern void task_prepare_enter(void); +__attribute__((__always_inline__)) static inline void arch_init_context(struct context* ctx) +{ + memset(ctx, 0, sizeof(*ctx)); + ctx->x30 = (uintptr_t)(task_prepare_enter + 4); +} + +struct trapframe { + uint64_t x0; + uint64_t x1; + uint64_t x2; + uint64_t x3; + uint64_t x4; + uint64_t x5; + uint64_t x6; + uint64_t x7; + uint64_t x8; + uint64_t x9; + uint64_t x10; + uint64_t x11; + uint64_t x12; + uint64_t x13; + uint64_t x14; + uint64_t x15; + uint64_t x16; + uint64_t x17; + uint64_t x18; + uint64_t x19; + uint64_t x20; + uint64_t x21; + uint64_t x22; + uint64_t x23; + uint64_t x24; + uint64_t x25; + uint64_t x26; + uint64_t x27; + uint64_t x28; + uint64_t x29; + uint64_t x30; + uint64_t pc; + uint64_t spsr; + uint64_t sp; +}; + +/// @brief init task trapframe +/// @param tf +/// @param sp +/// @param pc +__attribute__((__always_inline__)) static inline void arch_init_trapframe(struct trapframe* tf, uintptr_t sp, uintptr_t pc) +{ + memset(tf, 0, sizeof(*tf)); + tf->sp = sp; + tf->spsr = EL0_mode(); + tf->pc = pc; +} + +/// @brief set pc and sp to trapframe +/// @param tf +/// @param sp +/// @param pc +__attribute__((__always_inline__)) static inline void arch_trapframe_set_sp_pc(struct trapframe* tf, uintptr_t sp, uintptr_t pc) +{ + tf->sp = sp; + tf->pc = pc; +} + +/// @brief set params of main(int argc, char** argv) to trapframe (argc, argv) +/// @param tf +/// @param argc +/// @param argv +__attribute__((__always_inline__)) static inline void arch_set_main_params(struct trapframe* tf, int argc, uintptr_t argv) +{ + tf->x0 = (uint64_t)argc; + tf->x1 = (uint64_t)argv; +} + +/// @brief retrieve params to trapframe (up to max number of 6) and pass it to syscall() +/// @param sys_num +/// @param param1 +/// @param param2 +/// @param param3 +/// @param param4 +/// @param param5 +/// @return +extern int syscall(int sys_num, uintptr_t param1, uintptr_t param2, uintptr_t param3, uintptr_t param4); +__attribute__((__always_inline__)) static inline int arch_syscall(struct trapframe* tf, int* syscall_num) +{ + // call syscall + *syscall_num = tf->x0; + return syscall(*syscall_num, tf->x1, tf->x2, tf->x3, tf->x4); +} + +/// @brief set return reg to trapframe +/// @param tf +/// @param ret +__attribute__((__always_inline__)) static inline void arch_set_return(struct trapframe* tf, int ret) +{ + tf->x0 = (uint64_t)ret; +} + +void cpu_start_secondary(uint8_t cpu_id); +void start_smp_cache_broadcast(int cpu_id); +#endif diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/Makefile new file mode 100644 index 000000000..aed0b41a7 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/Makefile @@ -0,0 +1,6 @@ +SRC_FILES := boot.S \ + xizi_smp.S \ + smp.c \ + cortex.S + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S new file mode 100644 index 000000000..e50d8d63d --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +#include "core.h" + +#define HCR_VALUE (1 << 31) +#define SPSR_EL2_VALUE (7 << 6) | (5 << 0) +#define SCTLR_EL1_VALUE (0x30D00800) + +.section ".text", "ax" +.globl _boot_start +.globl primary_cpu_init + + +_boot_start: + + j primary_cpu_init + + j . + +primary_cpu_init: + + j bootmain + + + diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/config.mk b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/config.mk new file mode 100644 index 000000000..62bfef792 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/config.mk @@ -0,0 +1,17 @@ +# export CROSS_COMPILE ?= riscv64-linux-gnu- +export CROSS_COMPILE ?= riscv64-unknown-elf- +export ARCH = riscv + +# export KBUILD_CFLAGS := -Wall -Wundef -Werror=strict-prototypes -Wno-trigraphs -fno-strict-aliasing -fno-common -fshort-wchar -fno-PIE -Werror=implicit-function-declaration -Werror=implicit-int -Werror=return-type -Wno-format-security -std=gnu89 -Wno-sign-compare -fno-asynchronous-unwind-tables -fno-delete-null-pointer-checks -fno-stack-protector -Wno-main -fomit-frame-pointer -Wdeclaration-after-statement -Wvla -Wno-pointer-sign -Wno-array-bounds -fno-strict-overflow -fno-stack-check -Werror=date-time +export KBUILD_CFLAGS := -Wall -Wundef -Wno-trigraphs -fno-strict-aliasing -fno-common -fshort-wchar -fno-PIE -Werror=implicit-function-declaration -Werror=implicit-int -Werror=return-type -Wno-format-security -std=gnu89 -Wno-sign-compare -fno-asynchronous-unwind-tables -fno-delete-null-pointer-checks -fno-stack-protector -Wno-main -fomit-frame-pointer -Wvla -Wno-pointer-sign -Wno-array-bounds -fno-strict-overflow -fno-stack-check -Werror=date-time +export KBUILD_CPPFLAGS := -D__KERNEL__ +export KBUILD_AFLAGS := -D__ASSEMBLY__ -fno-PIE -m64 + +export DEVICE := +export CFLAGS := $(KBUILD_CFLAGS) -std=c11 +# .vmlinux.cmd:1:cmd_vmlinux := sh scripts/link-vmlinux.sh "riscv64-linux-gnu-ld" " -melf64lriscv" " --build-id=sha1"; +#export LFLAGS := -melf64lriscv --build-id=sha1 $(KERNEL_ROOT)/hardkernel/arch/riscv/preboot_for_jh7110/jh7110.lds +export LFLAGS := -T $(KERNEL_ROOT)/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds +export CXXFLAGS := + +export DEFINES := diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/cortex.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/cortex.S new file mode 100644 index 000000000..7fb1e6dcc --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/cortex.S @@ -0,0 +1,34 @@ +/*! + * @file cortexA55.s + * @brief This file contains cortexA55 functions + * + */ +/************************************************* +File name: cortexA55.S +Description: This file contains cortexA9 functions +Others: +History: +1. Date: 2024-05-08 +Author: AIIT XUOS Lab +Modification: +1. No modifications +*************************************************/ + .section ".text","ax" + + .global cpu_get_current + # int cpu_get_current(void)@ + # get current CPU ID + .func cpu_get_current +cpu_get_current: + ret + .endfunc + + .global psci_call +psci_call: + ret + + +# ------------------------------------------------------------ +# End of cortexA55.s +# ------------------------------------------------------------ + .end \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/cortex.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/cortex.h new file mode 100644 index 000000000..494fe7a6f --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/cortex.h @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * @file cortex_a55.h + * @brief some cortex A55 core functions + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.04.24 + */ + +/************************************************* +File name: cortex_a55.h +Description: some cortex A55 core functions +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. No modifications +*************************************************/ + +#if !defined(__CORTEX_A55_H__) +#define __CORTEX_A55_H__ + +#include +#include +#include + +//! @name Instruction macros +//@{ +//#define NOP() __asm__ volatile("nop\n\t") +//#define WFI() __asm__ volatile("wfi\n\t") +//#define WFE() __asm__ volatile("wfe\n\t") +//#define SEV() __asm__ volatile("sev\n\t") +//#define DMB() __asm__ volatile("dmb ish\n\t") +//#define DSB() __asm__ volatile("dsb ish\n\t") +//#define ISB() __asm__ volatile("isb\n\t") +#define NOP() __asm__ volatile("nop\n\t") +#define WFI() __asm__ volatile("nop\n\t") +#define WFE() __asm__ volatile("nop\n\t") +#define SEV() __asm__ volatile("nop\n\t") +#define DMB() __asm__ volatile("nop\n\t") +#define DSB() __asm__ volatile("nop\n\t") +#define ISB() __asm__ volatile("nop\n\t") + +#define _ARM_MRS(coproc, opcode1, Rt, CRn, CRm, opcode2) \ + __asm__ volatile("mrc p" #coproc ", " #opcode1 ", %[output], c" #CRn ", c" #CRm ", " #opcode2 "\n" : [output] "=r"(Rt)) + +#define _ARM_MSR(coproc, opcode1, Rt, CRn, CRm, opcode2) \ + __asm__ volatile("mcr p" #coproc ", " #opcode1 ", %[input], c" #CRn ", c" #CRm ", " #opcode2 "\n" ::[input] "r"(Rt)) + +// #define WriteReg(value, address) (*(volatile unsigned int*)(address) = (value)) +// #define ReadReg(address) (*(volatile unsigned int*)(address)) + +#if defined(__cplusplus) +extern "C" { +#endif + +//! @name Misc +//@{ +//! @brief Enable or disable the IRQ and FIQ state. +bool arm_set_interrupt_state(bool enable); + +//! @brief Get current CPU ID. +int cpu_get_current(void); + +//! @brief Enable the NEON MPE. +void enable_neon_fpu(void); + +//! @brief Disable aborts on unaligned accesses. +void disable_strict_align_check(void); + +//! @brief Get base address of private perpherial space. +//! +//! @return The address of the ARM CPU's private peripherals. +// uint32_t get_arm_private_peripheral_base(void); +//@} + +//! @name Data cache operations +//@{ + +//! @brief Check if dcache is enabled or disabled. +int arm_dcache_state_query(); + +//! @brief Enables data cache at any available cache level. +//! +//! Works only if MMU is enabled! +void arm_dcache_enable(); + +//! @brief Disables the data cache at any available cache level. +void arm_dcache_disable(); + +//! @brief Invalidates the entire data cache. +void arm_dcache_invalidate(); + +//! @brief Invalidate a line of data cache. +void arm_dcache_invalidate_line(const void* addr); + +//! @brief Invalidate a number of lines of data cache. +//! +//! Number of lines depends on length parameter and size of line. +//! Size of line for A9 L1 cache is 32B. +void arm_dcache_invalidate_mlines(const void* addr, size_t length); + +//! @brief Flush (clean) all lines of cache (all sets in all ways). +void arm_dcache_flush(); + +//! @brief Flush (clean) one line of cache. +void arm_dcache_flush_line(const void* addr); + +// @brief Flush (clean) multiple lines of cache. +//! +//! Number of lines depends on length parameter and size of line. +void arm_dcache_flush_mlines(const void* addr, size_t length); +//@} + +//! @name Instrution cache operations +//@{ + +//! @brief Check if icache is enabled or disabled. +int arm_icache_state_query(); + +//! @brief Enables instruction cache at any available cache level. +//! +//! Works without enabled MMU too! +void arm_icache_enable(); + +//! @brief Disables the instruction cache at any available cache level. +void arm_icache_disable(); + +//! @brief Invalidates the entire instruction cache. +void arm_icache_invalidate(); + +//! @brief Invalidates the entire instruction cache inner shareable. +void arm_icache_invalidate_is(); + +//! @brief Invalidate a line of the instruction cache. +void arm_icache_invalidate_line(const void* addr); + +//! @brief Invalidate a number of lines of instruction cache. +//! +//! Number of lines depends on length parameter and size of line. +void arm_icache_invalidate_mlines(const void* addr, size_t length); +//@} + +//! @name TLB operations +//@{ +//! @brief Invalidate entire unified TLB. +void arm_unified_tlb_invalidate(void); + +//! @brief Invalidate entire unified TLB Inner Shareable. +void arm_unified_tlb_invalidate_is(void); +//@} + +//! @name Branch predictor operations +//@{ +//! @brief Enable branch prediction. +void arm_branch_prediction_enable(void); + +//! @brief Disable branch prediction. +void arm_branch_prediction_disable(void); + +//! @brief Invalidate entire branch predictor array. +void arm_branch_target_cache_invalidate(void); + +//! @brief Invalidate entire branch predictor array Inner Shareable +void arm_branch_target_cache_invalidate_is(void); +//@} + +//! @name SCU +//@{ +//! @brief Enables the SCU. +void scu_enable(void); + +//! @brief Set this CPU as participating in SMP. +void scu_join_smp(void); + +//! @brief Set this CPU as not participating in SMP. +void scu_leave_smp(void); + +//! @brief Determine which CPUs are participating in SMP. +//! +//! The return value is 1 bit per core: +//! - bit 0 - CPU 0 +//! - bit 1 - CPU 1 +//! - etc... +unsigned int scu_get_cpus_in_smp(void); + +//! @brief Enable the broadcasting of cache & TLB maintenance operations. +//! +//! When enabled AND in SMP, broadcast all "inner sharable" +//! cache and TLM maintenance operations to other SMP cores +void scu_enable_maintenance_broadcast(void); + +//! @brief Disable the broadcasting of cache & TLB maintenance operations. +void scu_disable_maintenance_broadcast(void); + +//! @brief Invalidates the SCU copy of the tag rams for the specified core. +//! +//! Typically only done at start-up. +//! Possible flow: +//! - Invalidate L1 caches +//! - Invalidate SCU copy of TAG RAMs +//! - Join SMP +//! +//! @param cpu 0x0=CPU 0, 0x1=CPU 1, etc... +//! @param ways The ways to invalidate. Pass 0xf to invalidate all ways. +void scu_secure_invalidate(unsigned int cpu, unsigned int ways); +//@} + +#if defined(__cplusplus) +} +#endif + +#endif //__CORTEX_A55_H__ \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/registers.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/registers.h new file mode 100644 index 000000000..d3c08b923 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/registers.h @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +#ifndef INC_SYSREGS_H_ +#define INC_SYSREGS_H_ + +/* SCTLR_EL1, System Control Register (EL1). */ +#define SCTLR_RESERVED \ + ((3 << 28) | (3 << 22) | (1 << 20) | (1 << 11) | (1 << 8) | (1 << 7)) +#define SCTLR_EE_LITTLE_ENDIAN (0 << 25) +#define SCTLR_E0E_LITTLE_ENDIAN (0 << 24) +#define SCTLR_I_CACHE (1 << 12) +#define SCTLR_D_CACHE (1 << 2) +#define SCTLR_MMU_DISABLED (0 << 0) +#define SCTLR_MMU_ENABLED (1 << 0) + +#define SCTLR_VALUE_MMU_DISABLED \ + (SCTLR_RESERVED | SCTLR_EE_LITTLE_ENDIAN | SCTLR_E0E_LITTLE_ENDIAN \ + | SCTLR_I_CACHE | SCTLR_D_CACHE | SCTLR_MMU_DISABLED) + +/* HCR_EL2, Hypervisor Configuration Register (EL2). */ +#define HCR_RW (1 << 31) +#define HCR_VALUE HCR_RW + +/* CPACR_EL1, Architectural Feature Access Control Register. */ +#define CPACR_FP_EN (3 << 20) +#define CPACR_TRACE_EN (0 << 28) +#define CPACR_VALUE (CPACR_FP_EN | CPACR_TRACE_EN) + +/* SCR_EL3, Secure Configuration Register (EL3). */ +#define SCR_RESERVED (3 << 4) +#define SCR_RW (1 << 10) +#define SCR_HCE (1 << 8) +#define SCR_SMD (1 << 7) +#define SCR_NS (1 << 0) +#define SCR_VALUE (SCR_RESERVED | SCR_RW | SCR_HCE | SCR_SMD | SCR_NS) + +/* SPSR_EL1/2/3, Saved Program Status Register. */ +#define SPSR_MASK_ALL (7 << 6) +#define SPSR_EL1h (5 << 0) +#define SPSR_EL2h (9 << 0) +#define SPSR_EL3_VALUE (SPSR_MASK_ALL | SPSR_EL2h) +#define SPSR_EL2_VALUE (SPSR_MASK_ALL | SPSR_EL1h) + +/* Exception Class in ESR_EL1. */ +#define EC_SHIFT 26 +#define EC_UNKNOWN 0x00 +#define EC_SVC64 0x15 +#define EC_DABORT 0x24 +#define EC_IABORT 0x20 + +#define PTE_VALID 1 // level 0,1,2 descriptor: valid +#define PTE_TABLE 2 // level 0,1,2 descriptor: table +#define PTE_V 3 // level 3 descriptor: valid +// PTE_AF(Access Flag) +// +// 0 -- this block entry has not yet. +// 1 -- this block entry has been used. +#define PTE_AF (1 << 10) +// PTE_AP(Access Permission) is 2bit field. +// EL0 EL1 +// 00 -- x RW +// 01 -- RW RW +// 10 -- x RO +// 11 -- RO RO +#define PTE_AP(ap) (((ap) & 3) << 6) +#define PTE_U PTE_AP(1) +#define PTE_RO PTE_AP(2) +#define PTE_URO PTE_AP(3) +#define PTE_PXN (1UL << 53) // Privileged eXecute Never +#define PTE_UXN (1UL << 54) // Unprivileged(user) eXecute Never +#define PTE_XN (PTE_PXN | PTE_UXN) // eXecute Never + +// attribute index +// index is set by mair_el1 +#define AI_DEVICE_nGnRnE_IDX 0x0 +#define AI_NORMAL_NC_IDX 0x1 + +// memory type +#define MT_DEVICE_nGnRnE 0x0 +#define MT_NORMAL_NC 0x44 + +#define PTE_INDX(i) (((i) & 7) << 2) +#define PTE_DEVICE PTE_INDX(AI_DEVICE_nGnRnE_IDX) +#define PTE_NORMAL PTE_INDX(AI_NORMAL_NC_IDX) + +// shift a physical address to the right place for a PTE. +#define PA2PTE(pa) ((uint64_t)(pa) & 0xfffffffff000) +#define PTE2PA(pte) ((uint64_t)(pte) & 0xfffffffff000) + +#define PTE_FLAGS(pte) ((pte) & (0x600000000003ff)) + +// translation control register +// #define TCR_T0SZ(n) ((n) & 0x3f) +// #define TCR_TG0(n) (((n) & 0x3) << 14) +// #define TCR_T1SZ(n) (((n) & 0x3f) << 16) +// #define TCR_TG1(n) (((n) & 0x3) << 30) +// #define TCR_IPS(n) (((n) & 0x7) << 32) + +#define ISS_MASK 0xFFFFFF + +#endif // INC_SYSREGS_H_ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds new file mode 100644 index 000000000..fa95d5271 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2010-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @file jh7110.lds + * @brief + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.10.10 + */ + +OUTPUT_ARCH(riscv) +/* ENTRY(_start) */ +ENTRY( _boot_start ) + +BOOT_STACK_SIZE = 0x4000; +MEMORY { + phy_ddr3 (rwx) : ORIGIN = 0x10000000, LENGTH = 1024M + vir_ddr3 (rwx) : ORIGIN = 0x000000601040E000, LENGTH = 1024M +} + + +SECTIONS +{ +/* . = ((((-1))) - 0x80000000 + 1); + _start = .; + .head.text : AT(ADDR(.head.text) - ((((-1))) - 0x80000000 + 1)) { KEEP(*(.head.text)) } +*/ + + .start_sec : { + . = ORIGIN(phy_ddr3); + /* initialization start checkpoint. */ + + _start_image_addr = .; + + boot.o(.text) + bootmmu.o(.text .text.*) + /* ns16550.o(.text .text.*) */ + + boot.o(.rodata .rodata.*) + bootmmu.o(.rodata .rodata.*) + /* ns16550.o(.rodata .rodata.*) */ + + boot.o(.data .data.*) + bootmmu.o(.data .data.*) + /* ns16550.o(.data .data.*) */ + + PROVIDE(boot_start_addr = .); + + boot.o(.bss .bss.* COMMON) + bootmmu.o(.bss .bss.* COMMON) + /* ns16550.o(.bss .bss.* COMMON) */ + + /* stack for booting code. */ + . = ALIGN(0x1000); + PROVIDE(stacks_start = .); + . += BOOT_STACK_SIZE; + PROVIDE(stacks_end = .); + PROVIDE(stacks_top = .); + + /* initialization end checkpoint. */ + PROVIDE(boot_end_addr = .); + } > phy_ddr3 + + .text : AT(0x1041C000) { + . = ALIGN(0x1000); + *(.text .text.* .gnu.linkonce.t.*) + } + + . = ALIGN(0x1000); + .data : { + *(.data .data.*) + + . = ALIGN(0x1000); + PROVIDE(_binary_fs_img_start = .); + *(.rawdata_fs_img*) + PROVIDE(_binary_fs_img_end = .); + . = ALIGN(0x1000); + PROVIDE(_binary_init_start = .); + *(.rawdata_init*) + PROVIDE(_binary_init_end = .); + . = ALIGN(0x1000); + PROVIDE(_binary_default_fs_start = .); + *(.rawdata_memfs*) + PROVIDE(_binary_default_fs_end = .); + PROVIDE(__init_array_start = .); + PROVIDE(__init_array_end = .); + } + + . = ALIGN(0x1000); + .bss : { + PROVIDE(kernel_data_begin = .); + PROVIDE(__bss_start__ = .); + *(.bss .bss.* COMMON) + . = ALIGN(0x1000); + PROVIDE(__bss_end__ = .); + PROVIDE(kernel_data_end = .); + } + + . = ALIGN((1 << 21)); + .sdata : { + __global_pointer$ = . + 0x800; + *(.sdata*) + } + + _edata = .; + _end = .; + +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/smp.c b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/smp.c new file mode 100644 index 000000000..395b3e32e --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/smp.c @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2010-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @file smp.c + * @brief start multicore + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.04.10 + */ + +/************************************************* +File name: smp.c +Description: +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. No modifications +*************************************************/ +#include + +#define PSCI_CPUON 0xc4000003 +struct xizi_smccc_res { + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; +}; + +extern void _boot_start(); +extern void __print(); + +extern void __xizi_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2, + unsigned long a3, unsigned long a4, unsigned long a5, + unsigned long a6, unsigned long a7, struct xizi_smccc_res* res); + +static struct xizi_smccc_res __invoke_sip_fn_smc(unsigned long function_id, + unsigned long arg0, + unsigned long arg1, + unsigned long arg2) +{ + struct xizi_smccc_res res; + + __xizi_smccc_smc(function_id, arg0, arg1, arg2, 0, 0, 0, 0, &res); + return res; +} + +void cpu_start_secondary(uint8_t cpu_id) +{ + __invoke_sip_fn_smc(PSCI_CPUON, cpu_id, (uintptr_t)0xa00000, 0); +} + +void start_smp_cache_broadcast(int cpu_id) +{ + return; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/xizi_smp.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/xizi_smp.S new file mode 100644 index 000000000..a729c8e04 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/xizi_smp.S @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +.global __xizi_smccc_smc + +.func __xizi_smccc_smc +__xizi_smccc_smc: +1: ret +.endfunc \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/Makefile index 80385afc3..596b31fca 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/Makefile @@ -1,3 +1,8 @@ +ifneq ($(findstring $(BOARD), 3568 imx6q-sabrelite zynq7000-zc702), ) SRC_DIR := arm +endif +ifneq ($(findstring $(BOARD), jh7110), ) +SRC_DIR := riscv +endif include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/Makefile new file mode 100644 index 000000000..dd587adc4 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/Makefile @@ -0,0 +1,5 @@ +ifneq ($(findstring $(BOARD), jh7110), ) +SRC_DIR := rv64gc +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/Makefile new file mode 100644 index 000000000..11407977e --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := l1_cache.c cache.S + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/cache.S b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/cache.S new file mode 100644 index 000000000..84df60ab4 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/cache.S @@ -0,0 +1,184 @@ +/* + * (C) Copyright 2013 + * David Feng + * + * This file is based on sample code from ARMv8 ARM. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#define ASM_NL ; + +#define SYMBOL_NAME(X) X + +// #define SYMBOL_NAME_LABEL(X) X##: + +#define SYMBOL_NAME_LABEL(X) X: + +#ifndef __ALIGN +#define __ALIGN .align 4 +#endif + +#ifndef __ALIGN_STR +#define __ALIGN_STR ".align 4" +#endif + +#define ALIGN __ALIGN +#define ALIGN_STR __ALIGN_STR + +#define LENTRY(name) \ + ALIGN ASM_NL \ + SYMBOL_NAME_LABEL(name) + +#define ENTRY(name) \ + .globl SYMBOL_NAME(name) ASM_NL \ + LENTRY(name) + +#define WEAK(name) \ + .weak SYMBOL_NAME(name) ASM_NL \ + LENTRY(name) + + +#define END(name) \ + .size name, .-name + +#define ENDPROC(name) \ + .type name STT_FUNC ASM_NL \ + END(name) + +#define CR_M (1 << 0) /* MMU enable */ +#define CR_A (1 << 1) /* Alignment abort enable */ +#define CR_C (1 << 2) /* Dcache enable */ +#define CR_SA (1 << 3) /* Stack Alignment Check Enable */ +#define CR_I (1 << 12) /* Icache enable */ +#define CR_WXN (1 << 19) /* Write Permision Imply XN */ +#define CR_EE (1 << 25) /* Exception (Big) Endian */ + +.macro switch_el, xreg, el3_label, el2_label, el1_label + nop +.endm + + +/* + * void __asm_dcache_level(level) + * flush or invalidate one level cache. + * + * x0: cache level + * x1: 0 clean & invalidate, 1 invalidate only + * x2~x9: clobbered + */ +ENTRY(__asm_dcache_level) + nop + +loop_set: + nop +loop_way: + nop + ret +ENDPROC(__asm_dcache_level) + + +/* + * void __asm_flush_dcache_all(int invalidate_only) + * + * x0: 0 clean & invalidate, 1 invalidate only + * + * flush or invalidate all data cache by SET/WAY. + */ + +ENTRY(__asm_dcache_all) + nop + ret +ENDPROC(__asm_dcache_all) + + +ENTRY(__asm_flush_dcache_all) + j __asm_dcache_all +ENDPROC(__asm_flush_dcache_all) + + +ENTRY(__asm_invalidate_dcache_all) + j __asm_dcache_all +ENDPROC(__asm_invalidate_dcache_all) + + +/* + * void __asm_flush_dcache_range(start, end) + * + * clean & invalidate data cache in the range + * + * x0: start address + * x1: end address + */ + +ENTRY(__asm_flush_dcache_range) + nop + ret +ENDPROC(__asm_flush_dcache_range) + +/* + * void __asm_invalidate_dcache_range(start, end) + * + * invalidate data cache in the range + * + * x0: start address + * x1: end address + */ + +ENTRY(__asm_invalidate_dcache_range) + nop + ret +ENDPROC(__asm_invalidate_dcache_range) + + +/* + * void __asm_invalidate_icache_all(void) + * + * invalidate all tlb entries. + */ + +ENTRY(__asm_invalidate_icache_all) + nop + ret +ENDPROC(__asm_invalidate_icache_all) + + + +ENTRY(__asm_invalidate_l3_dcache) + nop + ret +ENDPROC(__asm_invalidate_l3_dcache) + .weak __asm_invalidate_l3_dcache + + + +ENTRY(__asm_flush_l3_dcache) + nop + ret +ENDPROC(__asm_flush_l3_dcache) + .weak __asm_flush_l3_dcache + + + +ENTRY(__asm_invalidate_l3_icache) + nop + ret +ENDPROC(__asm_invalidate_l3_icache) + .weak __asm_invalidate_l3_icache + + +/* + * void __asm_switch_ttbr(ulong new_ttbr) + * + * Safely switches to a new page table. + */ + +ENTRY(__asm_switch_ttbr) + nop + ret +ENDPROC(__asm_switch_ttbr) + +ENTRY(__asm_invalidate_tlb_all) + ret +ENDPROC(__asm_invalidate_tlb_all) \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/l1_cache.c b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/l1_cache.c new file mode 100644 index 000000000..229558fc4 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/l1_cache.c @@ -0,0 +1,81 @@ +/** + * @file: l1_cache.c + * @brief: the general management of L1 cache + * @version: 1.0 + * @author: AIIT XUOS Lab + * @date: 2024/04/23 + * + */ + +/************************************************* +File name: l1_cache.c +Description: the general management of L1 cache +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. implement the l1 cache operations +2. function names are modified to apply softkernel developement +3. function implementations are from modifications of imx6 SDK package +*************************************************/ + +#include "l1_cache.h" +extern void __asm_flush_dcache_all(); +extern void __asm_flush_l3_dcache(); +extern void __asm_invalidate_icache_all(); +extern void __asm_invalidate_l3_icache(); + +void InvalidateL1Dcache(uintptr_t start, uintptr_t end) +{ +} + +void InvalidateL1DcacheAll(void) +{ +} + +void CleanL1Dcache(uintptr_t start, uintptr_t end) +{ +} + +void CleanL1DcacheAll(void) +{ +} + +void FlushL1Dcache(uintptr_t start, uintptr_t end) +{ +} + +void FlushL1DcacheAll(void) +{ + +} + +void InvalidateL1IcacheAll() +{ + +} + +void InvalidateL1Icache(uintptr_t start, uintptr_t end) +{ + +} + +void EnableL1Dcache() +{ + +} + +void DisableL1Dcache() +{ + +} + +void EnableL1Icache() +{ + +} + +void DisableL1Icache() +{ + +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/l1_cache.h b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/l1_cache.h new file mode 100644 index 000000000..c1cddb488 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/l1_cache.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file: l1_cache.h + * @brief: the general management of L1 cache + * @version: 1.0 + * @author: AIIT XUOS Lab + * @date: 2024/4/23 + * + */ + +/************************************************* +File name: l1_cache.h +Description: the general management of L1 cache +Others: +History: +Author: AIIT XUOS Lab +Modification: +1、define the l1 cache operations +*************************************************/ +#include "core.h" +#include + +/* + * L1 Cache Operation: + * + * IVAC -Invalidate by Virtual Address, to Point of Coherency AArch32Equivalent :DCIMVAC + * + * ISW -Invalidate by Set/Way AArch32Equivalent :DCISW + * + *CVAC -Clean by Virtual Address to Point of Coherency AArch32Equivalent :DCCMVAC + * + *CSW -Clean by Set/Way AArch32Equivalent :DCCSW + * + *CVAU -Clean by Virtual Address to Point of Unification AArch32Equivalent :DCCMVAU + * + *CIVAC -Clean and invalidate data cache line by VA to PoC. AArch32Equivalent :DCCIMVAC + * + *ISW -Clean and invalidate data cache line by Set/Way. AArch32Equivalent :DCCISW + */ + +#define SCTLR_EL1_ICACHE_ENABLE (1 << 12) //!< Instruction cache enable +#define SCTLR_EL1_DCACHE_ENABLE (1 << 2) //!< Data cache enable + +void InvalidateL1Dcache(uintptr_t start, uintptr_t end); + +void InvalidateL1DcacheAll(void); + +void CleanL1Dcache(uintptr_t start, uintptr_t end); + +void CleanL1DcacheAll(void); + +void FlushL1Dcache(uintptr_t start, uintptr_t end); + +void FlushL1DcacheAll(void); + +void InvalidateL1IcacheAll(void); + +void InvalidateL1Icache(uintptr_t start, uintptr_t end); + +void EnableL1Icache(void); +void DisableL1Icache(); + +void EnableL1Dcache(); + +void DisableL1Dcache(); \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/clock/Makefile index 5ccf8946b..596b31fca 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/clock/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/Makefile @@ -1,3 +1,8 @@ -SRC_DIR:= arm +ifneq ($(findstring $(BOARD), 3568 imx6q-sabrelite zynq7000-zc702), ) +SRC_DIR := arm +endif +ifneq ($(findstring $(BOARD), jh7110), ) +SRC_DIR := riscv +endif include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/Makefile new file mode 100644 index 000000000..dd587adc4 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/Makefile @@ -0,0 +1,5 @@ +ifneq ($(findstring $(BOARD), jh7110), ) +SRC_DIR := rv64gc +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/Makefile new file mode 100644 index 000000000..c87074a06 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/Makefile @@ -0,0 +1,4 @@ +SRC_FILES := clock.c + + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/clock.c b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/clock.c new file mode 100644 index 000000000..39d2995d6 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/clock.c @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +#include "actracer.h" +#include "core.h" +#include "generic_timer.h" + +#include "clock_common_op.h" + +// armv8 generic timer driver +#define CNTV_CTL_ENABLE (1 << 0) +#define CNTV_CTL_IMASK (1 << 1) +#define CNTV_CTL_ISTATUS (1 << 2) + +static void enable_timer() +{ + uint32_t c = r_cntp_ctl_el0(); + c |= CNTV_CTL_ENABLE; + c &= ~CNTV_CTL_IMASK; + w_cntp_ctl_el0(c); +} + +static void disable_timer() +{ + uint32_t c = r_cntp_ctl_el0(); + c |= CNTV_CTL_IMASK; + c &= ~CNTV_CTL_ENABLE; + w_cntp_ctl_el0(c); +} + +static void reload_timer() +{ + // interval 1ms + static uint32_t ms = 1; + uint32_t interval = ms * 1000; + uint32_t interval_clk = interval * (r_cntfrq_el0() / 1000000); + w_cntp_tval_el0(interval_clk); +} + +void _sys_clock_init() +{ + disable_timer(); + reload_timer(); + enable_timer(); +} + +static uint32_t _get_clock_int() +{ + return 30; +} + +static uint64_t _get_tick() +{ + return r_cntvct_el0(); +} + +static uint64_t _get_second() +{ + return _get_tick() / r_cntfrq_el0(); +} + +static bool _is_timer_expired() +{ + return true; +} + +static void _clear_clock_intr() +{ + disable_timer(); + reload_timer(); + enable_timer(); +} + +static struct XiziClockDriver hardkernel_clock_driver = { + .sys_clock_init = _sys_clock_init, + .get_clock_int = _get_clock_int, + .get_tick = _get_tick, + .get_second = _get_second, + .is_timer_expired = _is_timer_expired, + .clear_clock_intr = _clear_clock_intr, +}; + +struct XiziClockDriver* hardkernel_clock_init(struct TraceTag* hardkernel_tag) +{ + hardkernel_clock_driver.sys_clock_init(); + return &hardkernel_clock_driver; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/Makefile new file mode 100644 index 000000000..c87074a06 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/Makefile @@ -0,0 +1,4 @@ +SRC_FILES := clock.c + + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/clock.c b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/clock.c new file mode 100644 index 000000000..39d2995d6 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/clock.c @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +#include "actracer.h" +#include "core.h" +#include "generic_timer.h" + +#include "clock_common_op.h" + +// armv8 generic timer driver +#define CNTV_CTL_ENABLE (1 << 0) +#define CNTV_CTL_IMASK (1 << 1) +#define CNTV_CTL_ISTATUS (1 << 2) + +static void enable_timer() +{ + uint32_t c = r_cntp_ctl_el0(); + c |= CNTV_CTL_ENABLE; + c &= ~CNTV_CTL_IMASK; + w_cntp_ctl_el0(c); +} + +static void disable_timer() +{ + uint32_t c = r_cntp_ctl_el0(); + c |= CNTV_CTL_IMASK; + c &= ~CNTV_CTL_ENABLE; + w_cntp_ctl_el0(c); +} + +static void reload_timer() +{ + // interval 1ms + static uint32_t ms = 1; + uint32_t interval = ms * 1000; + uint32_t interval_clk = interval * (r_cntfrq_el0() / 1000000); + w_cntp_tval_el0(interval_clk); +} + +void _sys_clock_init() +{ + disable_timer(); + reload_timer(); + enable_timer(); +} + +static uint32_t _get_clock_int() +{ + return 30; +} + +static uint64_t _get_tick() +{ + return r_cntvct_el0(); +} + +static uint64_t _get_second() +{ + return _get_tick() / r_cntfrq_el0(); +} + +static bool _is_timer_expired() +{ + return true; +} + +static void _clear_clock_intr() +{ + disable_timer(); + reload_timer(); + enable_timer(); +} + +static struct XiziClockDriver hardkernel_clock_driver = { + .sys_clock_init = _sys_clock_init, + .get_clock_int = _get_clock_int, + .get_tick = _get_tick, + .get_second = _get_second, + .is_timer_expired = _is_timer_expired, + .clear_clock_intr = _clear_clock_intr, +}; + +struct XiziClockDriver* hardkernel_clock_init(struct TraceTag* hardkernel_tag) +{ + hardkernel_clock_driver.sys_clock_init(); + return &hardkernel_clock_driver; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/include/generic_timer.h b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/include/generic_timer.h new file mode 100644 index 000000000..58cfd1b07 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/include/generic_timer.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +#pragma once + +#include +#include + +// armv8 generic timer +static inline uint32_t r_cntp_ctl_el0() +{ + uint32_t x; +// __asm__ volatile("mrs %0, cntp_ctl_el0" : "=r"(x)); + return x; +} + +static inline void w_cntp_ctl_el0(uint32_t x) +{ +// __asm__ volatile("msr cntp_ctl_el0, %0" : : "r"(x)); +} + +static inline uint32_t r_cntp_tval_el0() +{ + uint32_t x; +// __asm__ volatile("mrs %0, cntp_tval_el0" : "=r"(x)); + return x; +} + +static inline void w_cntp_tval_el0(uint32_t x) +{ +// __asm__ volatile("msr cntp_tval_el0, %0" : : "r"(x)); +} + +static inline uint64_t r_cntvct_el0() +{ + uint64_t x; +// __asm__ volatile("mrs %0, cntvct_el0" : "=r"(x)); + return x; +} + +static inline uint32_t r_cntfrq_el0() +{ + uint32_t x; +// __asm__ volatile("mrs %0, cntfrq_el0" : "=r"(x)); + return x; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/intr/Makefile index bd7075f60..4fcd6940b 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/Makefile @@ -1,4 +1,10 @@ +ifneq ($(findstring $(BOARD), 3568 imx6q-sabrelite zynq7000-zc702), ) SRC_DIR := arm +endif +ifneq ($(findstring $(BOARD), jh7110), ) +SRC_DIR := riscv +endif + SRC_FILES := spinlock.c include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/Makefile new file mode 100644 index 000000000..dd587adc4 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/Makefile @@ -0,0 +1,5 @@ +ifneq ($(findstring $(BOARD), jh7110), ) +SRC_DIR := rv64gc +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile new file mode 100644 index 000000000..6fd2fb6d5 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile @@ -0,0 +1,9 @@ +SRC_FILES := trampoline.S $(BOARD)/trap_common.c $(BOARD)/trap.c error_debug.c hard_spinlock.S + +ifeq ($(BOARD), jh7110) +SRC_DIR := gicv3 +SRC_FILES += $(BOARD)/ +endif + + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/error_debug.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/error_debug.c new file mode 100644 index 000000000..3e2c2a1ec --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/error_debug.c @@ -0,0 +1,67 @@ +/* Copyright (c) 2006-2018 Frans Kaashoek, Robert Morris, Russ Cox, + * Massachusetts Institute of Technology + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +/** + * @file error_debug.c + * @brief handle program abort + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.4.25 + */ + +/************************************************* +File name: error_debug.c +Description: handle program abort +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. Take only armv8 abort reason part(_abort_reason). +2. Modify iabort and dabort handler(in dabort_handler() and iabort_handler()) +*************************************************/ +#include +#include + +#include "exception_registers.h" + +#include "assert.h" +#include "core.h" +#include "log.h" +#include "multicores.h" +#include "task.h" +#include "trap_common.h" + +void dump_tf(struct trapframe* tf) +{ + +} + +void dabort_reason(struct trapframe* r) +{ + + return; +} + +void iabort_reason(struct trapframe* r) +{ + return; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/Makefile new file mode 100644 index 000000000..c5085627e --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := gicv3.c + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3.c new file mode 100644 index 000000000..f299f4966 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3.c @@ -0,0 +1,260 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file gicv3.c + * @brief gicv3 operation + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.05.10 + */ + +/************************************************* +File name: gicv3.c +Description: gicv3 operation +Others: +History: +Author: AIIT XUOS Lab +Modification: +*************************************************/ +#include + +#include "core.h" +#include "gicv3_common_opa.h" +#include "gicv3_registers.h" + +static struct { + char* gicd; + char* rdist_addrs[NR_CPU]; +} gicv3; + +static inline uint32_t icc_igrpen1_el1() +{ + uint32_t x; +// __asm__ volatile("mrs %0, S3_0_C12_C12_7" : "=r"(x)); + return x; +} + +static inline void w_icc_igrpen1_el1(uint32_t x) +{ +// __asm__ volatile("msr S3_0_C12_C12_7, %0" : : "r"(x)); +} + +static inline uint32_t icc_pmr_el1() +{ + uint32_t x; +// __asm__ volatile("mrs %0, S3_0_C4_C6_0" : "=r"(x)); + return x; +} + +static inline void w_icc_pmr_el1(uint32_t x) +{ +// __asm__ volatile("msr S3_0_C4_C6_0, %0" : : "r"(x)); +} + +inline uint32_t gic_read_irq_ack() +{ + uint32_t x; +// __asm__ volatile("mrs %0, S3_0_C12_C12_0" : "=r"(x)); + return x; +} + +inline void +gic_write_end_of_irq(uint32_t x) +{ +// __asm__ volatile("msr S3_0_C12_C12_1, %0" : : "r"(x)); +} + +static inline uint32_t icc_sre_el1() +{ + uint32_t x; +// __asm__ volatile("mrs %0, S3_0_C12_C12_5" : "=r"(x)); + return x; +} + +static inline void w_icc_sre_el1(uint32_t x) +{ +// __asm__ volatile("msr S3_0_C12_C12_5, %0" : : "r"(x)); +} + +static void gicd_write(uint32_t off, uint32_t val) +{ +// *(volatile uint32_t*)(gicv3.gicd + off) = val; +} + +static uint32_t gicd_read(uint32_t off) +{ +// return *(volatile uint32_t*)(gicv3.gicd + off); + return 0; +} + +static void gicr_write(uint32_t cpuid, uint32_t off, uint32_t val) +{ +// *(volatile uint32_t*)(gicv3.rdist_addrs[cpuid] + off) = val; +} + +static uint32_t gicr_read(uint32_t cpuid, uint32_t off) +{ +// return *(volatile uint32_t*)(gicv3.rdist_addrs[cpuid] + off); + return 0; +} + +static void giccinit() +{ + w_icc_igrpen1_el1(0); + w_icc_pmr_el1(0xff); +} + +static void gicdinit() +{ + gicd_write(D_CTLR, 0); + + uint32_t typer = gicd_read(D_TYPER); + uint32_t lines = typer & 0x1f; + + for (int i = 0; i < lines; i++) + gicd_write(D_IGROUPR(i), ~0); +} + +static void gicrinit(uint32_t cpuid) +{ + gicr_write(cpuid, R_CTLR, 0); + + w_icc_sre_el1(icc_sre_el1() | 1); + + gicr_write(cpuid, R_IGROUPR0, ~0); + gicr_write(cpuid, R_IGRPMODR0, 0); + + uint32_t waker = gicr_read(cpuid, R_WAKER); + gicr_write(cpuid, R_WAKER, waker & ~(1 << 1)); + while (gicr_read(cpuid, R_WAKER) & (1 << 2)) + ; +} + +void gic_enable() +{ + gicd_write(D_CTLR, (1 << 1)); + w_icc_igrpen1_el1(1); +} + +void gic_init() +{ + gicv3.gicd = (char*)GICV3; + for (int i = 0; i < NR_CPU; i++) { + gicv3.rdist_addrs[i] = (char*)(GICV3_REDIST + (i) * 0x20000); + } + + gicdinit(); +} + +void gicv3inithart(uint32_t cpu_id) +{ + giccinit(); + gicrinit(cpu_id); + + gic_enable(); +} + +static void +gic_enable_int(uint32_t intid) +{ + uint32_t is = gicd_read(D_ISENABLER(intid / 32)); + is |= 1 << (intid % 32); + gicd_write(D_ISENABLER(intid / 32), is); +} + +int gic_int_enabled(uint32_t intid) +{ + uint32_t is = gicd_read(D_ISENABLER(intid / 32)); + return is & (1 << (intid % 32)); +} + +static void +gic_clear_pending(uint32_t intid) +{ + uint32_t ic = gicd_read(D_ICPENDR(intid / 32)); + ic |= 1 << (intid % 32); + gicd_write(D_ICPENDR(intid / 32), ic); +} + +static void +gic_set_prio0(uint32_t intid) +{ + // set priority to 0 + uint32_t p = gicd_read(D_IPRIORITYR(intid / 4)); + p &= ~((uint32_t)0xff << (intid % 4 * 8)); // set prio 0 + gicd_write(D_IPRIORITYR(intid / 4), p); +} + +static void gic_set_target(uint32_t intid, uint32_t cpuid) +{ + uint32_t itargetsr = gicd_read(D_ITARGETSR(intid / 4)); + itargetsr &= ~((uint32_t)0xff << (intid % 4 * 8)); + gicd_write(D_ITARGETSR(intid / 4), itargetsr | ((uint32_t)(1 << cpuid) << (intid % 4 * 8))); +} + +static void +gicr_enable_int(uint32_t cpuid, uint32_t intid) +{ + uint32_t is = gicr_read(cpuid, R_ISENABLER0); + is |= 1 << (intid % 32); + gicr_write(cpuid, R_ISENABLER0, is); +} + +static void +gicr_clear_pending(uint32_t cpuid, uint32_t intid) +{ + uint32_t ic = gicr_read(cpuid, R_ICPENDR0); + ic |= 1 << (intid % 32); + gicr_write(cpuid, R_ICPENDR0, ic); +} + +static void +gicr_set_prio0(uint32_t cpuid, uint32_t intid) +{ + uint32_t p = gicr_read(cpuid, R_IPRIORITYR(intid / 4)); + p &= ~((uint32_t)0xff << (intid % 4 * 8)); // set prio 0 + gicr_write(cpuid, R_IPRIORITYR(intid / 4), p); +} + +void gic_setup_ppi(uint32_t cpuid, uint32_t intid) +{ + gicr_set_prio0(cpuid, intid); + gicr_clear_pending(cpuid, intid); + gicr_enable_int(cpuid, intid); +} + +void gic_setup_spi(uint32_t cpuid, uint32_t intid) +{ + gic_set_prio0(intid); + gic_set_target(intid, cpuid); + gic_clear_pending(intid); + gic_enable_int(intid); +} + +// irq from iar +int gic_iar_irq(uint32_t iar) +{ + return iar & 0x3ff; +} + +// interrupt acknowledge register: +// ask GIC what interrupt we should serve. +uint32_t gic_iar() +{ + return gic_read_irq_ack(); +} + +// tell GIC we've served this IRQ. +void gic_eoi(uint32_t iar) +{ + gic_write_end_of_irq(iar); +} diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_common_opa.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_common_opa.h new file mode 100644 index 000000000..17e3632eb --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_common_opa.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file gicv3_common_opa.h + * @brief gicv3 operation + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.05.07 + */ +/************************************************* +File name: gicv3_common_opa.h +Description: gicv3 operation +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. Rename file +*************************************************/ +#pragma once + +#include +#include + +#include + +//! @name Initialization +//@{ +//! @brief Init interrupt handling. +//! +//! This function is intended to be called only by the primary CPU init code, so it will +//! only be called once during system bootup. +//! +//! Also inits the current CPU. You don't need to call gic_init_cpu() separately. +//! +//! @post The interrupt distributor and the current CPU interface are enabled. All interrupts +//! that were pending are cleared, and all interrupts are made secure (group 0). +void gic_init(void); + +//! @name GIC Interrupt Distributor Functions +//@{ +//! @brief Enable or disable the GIC Distributor. +//! +//! Enables or disables the GIC distributor passing both secure (group 0) and non-secure +//! (group 1) interrupts to the CPU interfaces. +//! +//! @param enableIt Pass true to enable or false to disable. +void gic_enable(); + +//! @brief Set the security mode for an interrupt. +//! +//! @param irqID The interrupt number. +//! @param isSecure Whether the interrupt is taken to secure mode. +void gic_set_irq_security(uint32_t irqID, bool isSecure); + +//! @brief Enable or disable an interrupt. +//! +//! @param irqID The number of the interrupt to control. +//! @param isEnabled Pass true to enable or false to disable. +void gic_enable_irq(uint32_t irqID, bool isEnabled); + +//! @brief Set whether a CPU will receive a particular interrupt. +//! +//! @param irqID The interrupt number. +//! @param cpuNumber The CPU number. The first CPU core is 0. +//! @param enableIt Whether to send the interrupt to the specified CPU. Pass true to enable +//! or false to disable. +void gic_set_cpu_target(uint32_t irqID, unsigned cpuNumber, bool enableIt); + +//! @brief Set an interrupt's priority. +//! +//! @param irq_id The interrupt number. +//! @param priority The priority for the interrupt. In the range of 0 through 0xff, with +//! 0 being the highest priority. +void gic_set_irq_priority(uint32_t irq_id, uint32_t priority); + +void gic_setup_spi(uint32_t cpuid, uint32_t intid); +void gic_setup_ppi(uint32_t cpuid, uint32_t intid); + +void gicv3inithart(uint32_t cpu_id); +//! @brief Send a software generated interrupt to a specific CPU. +//! +//! @param irq_id The interrupt number to send. +//! @param target_list Each bit indicates a CPU to which the interrupt will be forwarded. +//! Bit 0 is CPU 0, bit 1 is CPU 1, and so on. If the value is 0, then the interrupt +//! will not be forwarded to any CPUs. This parameter is only used if @a filter_list +//! is set to #kGicSgiFilter_UseTargetList. +//! @param filter_list One of the enums of the #_gicd_sgi_filter enumeration. The selected +//! option determines which CPUs the interrupt will be sent to. If the value +//! is #kGicSgiFilter_UseTargetList, then the @a target_list parameter is used. +void gic_send_sgi(uint32_t irq_id, uint32_t target_list, uint32_t filter_list); +//@} + +//! @name GIC CPU Interface Functions +//@{ +//! @brief Enable or disable the interface to the GIC for the current CPU. +//! +//! @param enableIt Pass true to enable or false to disable. +void gic_cpu_enable(bool enableIt); + +//! @brief Set the mask of which interrupt priorities the CPU will receive. +//! +//! @param priority The lowest priority that will be passed to the current CPU. Pass 0xff to +//! allow all priority interrupts to signal the CPU. +void gic_set_cpu_priority_mask(uint32_t priority); + +//! @brief Acknowledge starting of interrupt handling and get the interrupt number. +//! +//! Normally, this function is called at the beginning of the IRQ handler. It tells the GIC +//! that you are starting to handle an interupt, and returns the number of the interrupt you +//! need to handle. After the interrupt is handled, you should call gic_write_end_of_irq() +//! to signal that the interrupt is completely handled. +//! +//! In some cases, a spurious interrupt might happen. One possibility is if another CPU handles +//! the interrupt. When a spurious interrupt occurs, the end of the interrupt should be indicated +//! but nothing else. +//! +//! @return The number for the highest priority interrupt available for the calling CPU. If +//! the return value is 1022 or 1023, a spurious interrupt has occurred. +uint32_t gic_read_irq_ack(void); + +//! @brief Signal the end of handling an interrupt. +//! +//! @param irq_id The number of the interrupt for which handling has finished. +void gic_write_end_of_irq(uint32_t irq_id); +//@} + +//! @} + +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_registers.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_registers.h new file mode 100644 index 000000000..389d6a5b1 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_registers.h @@ -0,0 +1,59 @@ +/* + * + * Copyright (C) 2002 ARM Limited, All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/** + * @file gicv3_registers.h + * @brief gicv3 registers + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.05.09 + */ + +/************************************************* +File name: gicv3_registers.c +Description: gicv3 registers +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. Rename the file +*************************************************/ + +#pragma once + +#include "memlayout.h" + +// clang-format off +// interrupt controller GICv3 +#define GICV3 MMIO_P2V_WO(0xFD400000ULL) +#define GICV3_REDIST MMIO_P2V_WO(0xFD460000ULL) + +#define D_CTLR 0x0 +#define D_TYPER 0x4 +#define D_IGROUPR(n) (0x80 + (uint64_t)(n) * 4) +#define D_ISENABLER(n) (0x100 + (uint64_t)(n) * 4) +#define D_ICENABLER(n) (0x180 + (uint64_t)(n) * 4) +#define D_ISPENDR(n) (0x200 + (uint64_t)(n) * 4) +#define D_ICPENDR(n) (0x280 + (uint64_t)(n) * 4) +#define D_IPRIORITYR(n) (0x400 + (uint64_t)(n) * 4) +#define D_ITARGETSR(n) (0x800 + (uint64_t)(n) * 4) +#define D_ICFGR(n) (0xc00 + (uint64_t)(n) * 4) + +#define R_CTLR 0x0 +#define R_WAKER 0x14 + +#define SGI_BASE 0x10000 +#define R_IGROUPR0 (SGI_BASE + 0x80) +#define R_ISENABLER0 (SGI_BASE + 0x100) +#define R_ICENABLER0 (SGI_BASE + 0x180) +#define R_ICPENDR0 (SGI_BASE + 0x280) +#define R_IPRIORITYR(n) (SGI_BASE + 0x400 + (n) * 4) +#define R_ICFGR0 (SGI_BASE + 0xc00) +#define R_ICFGR1 (SGI_BASE + 0xc04) +#define R_IGRPMODR0 (SGI_BASE + 0xd00) +// clang-format on diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S new file mode 100644 index 000000000..b26cf30f3 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2013, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * Portions Copyright (c) 2011-2012 ARM Ltd. All rights reserved. + */ +/** + * @file hard_spinlock.S + * @brief spinlock implementation + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.04.11 + */ + +/************************************************* +File name: hard_spinlock.S +Description: spinlock implementation +Others: +History: +Author: AIIT XUOS Lab +Modification: +*************************************************/ + +// .arch armv8-a + .section ".text","ax" + + .global cpu_get_current + +#define UNLOCKED 0xFF +// int spinlock_lock(spinlock_t * lock, uint64_t timeout) + .global _spinlock_lock +.func _spinlock_lock +_spinlock_lock: + ret +.endfunc + + +// void spinlock_unlock(spinlock_t * lock) + .global _spinlock_unlock + .func _spinlock_unlock +_spinlock_unlock: + ret +.endfunc + +.end + diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/exception_registers.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/exception_registers.h new file mode 100644 index 000000000..aae7e28c8 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/exception_registers.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file exception_registers.h + * @brief exception registers + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.05.09 + */ + +static inline void w_vbar_el1(uint64_t x) +{ +// __asm__ volatile("msr vbar_el1, %0" : : "r"(x)); +} + +static inline uint64_t r_esr_el1() +{ + uint64_t x; +// __asm__ volatile("mrs %0, esr_el1" : "=r"(x)); + return x; +} + +static inline void w_esr_el1(uint64_t x) +{ +// __asm__ volatile("msr esr_el1, %0" : : "r"(x)); +} + +static inline uint64_t r_elr_el1() +{ + uint64_t x; +// __asm__ volatile("mrs %0, elr_el1" : "=r"(x)); + return x; +} + +static inline uint64_t r_far_el1() +{ + uint64_t x; +// __asm__ volatile("mrs %0, far_el1" : "=r"(x)); + return x; +} + +static inline uint64_t daif() +{ + uint64_t x; +// __asm__ volatile("mrs %0, daif" : "=r"(x)); + return x; +} + +// enable interrupts(irq) +static inline void intr_on() +{ +// __asm__ volatile("msr daifclr, #0xf" ::: "memory"); +} + +// disable interrupts(irq) +static inline void intr_off() +{ +// __asm__ volatile("msr daifset, #0xf" ::: "memory"); +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/irq_numbers.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/irq_numbers.h new file mode 100644 index 000000000..c7d5e8ca3 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/irq_numbers.h @@ -0,0 +1,110 @@ +/** + * @file irq_numbers.c + * @brief irq numbers + * @version 3.0 + * @author AIIT XUOS Lab + * @date 2023.08.25 + */ + +/************************************************* +File name: irq_numbers.c +Description: irq numbers +Others: +History: +1. Date: 2023-08-28 +Author: AIIT XUOS Lab +Modification: +1. Add HW_NR_IRQS +*************************************************/ +#if !defined(__IRQ_NUMBERS_H__) +#define __IRQ_NUMBERS_H__ + +#define HW_NR_IRQS NR_OK1028_INTRS + +//////////////////////////////////////////////////////////////////////////////// +// Definitions +//////////////////////////////////////////////////////////////////////////////// + +//! @brief i.MX6 interrupt numbers. +//! +//! This enumeration lists the numbers for all of the interrupts available on the i.MX6 series. +//! Use these numbers when specifying an interrupt to the GIC. +//! +//! The first 16 interrupts are special in that they are reserved for software interrupts generated +//! by the SWI instruction. + +enum _ls_interrupts { + SW_INTERRUPT_0 = 0, //!< Software interrupt 0. + SW_INTERRUPT_1 = 1, //!< Software interrupt 1. + SW_INTERRUPT_2 = 2, //!< Software interrupt 2. + SW_INTERRUPT_3 = 3, //!< Software interrupt 3. + SW_INTERRUPT_4 = 4, //!< Software interrupt 4. + SW_INTERRUPT_5 = 5, //!< Software interrupt 5. + SW_INTERRUPT_6 = 6, //!< Software interrupt 6. + SW_INTERRUPT_7 = 7, //!< Software interrupt 7. + SW_INTERRUPT_8 = 8, //!< Software interrupt 8. + SW_INTERRUPT_9 = 9, //!< Software interrupt 9. + SW_INTERRUPT_10 = 10, //!< Software interrupt 10. + SW_INTERRUPT_11 = 11, //!< Software interrupt 11. + SW_INTERRUPT_12 = 12, //!< Software interrupt 12. + SW_INTERRUPT_13 = 13, //!< Software interrupt 13. + SW_INTERRUPT_14 = 14, //!< Software interrupt 14. + SW_INTERRUPT_15 = 15, //!< Software interrupt 15. + RSVD_INTERRUPT_16 = 16, //!< Reserved. + RSVD_INTERRUPT_17 = 17, //!< Reserved. + RSVD_INTERRUPT_18 = 18, //!< Reserved. + RSVD_INTERRUPT_19 = 19, //!< Reserved. + RSVD_INTERRUPT_20 = 20, //!< Reserved. + RSVD_INTERRUPT_21 = 21, //!< Reserved. + + LS_INT_DEBUG_CC = 22, //!<(cluster-internal) COMMIRQ - Debug communications channel + LS_INT_PMU = 23, //!<(cluster-internal) PMUIRQ - Perfmon* + LS_INT_CTI = 24, //!<(cluster-internal) CTIIRQ - Cross-trigger interface* + LS_INT_VMI = 25, //!<(cluster-internal) VCPUMNTIRQ -Virtual maintenance interface* + + LS_INT_WDOG = 28, //!< Watchdog timer + LS_INT_SEC_PHY_TIMER = 29, //!<(cluster-internal) CNTPSIRQ - EL1 Secure physical timer event* + LS_INT_NON_SEC_PHY_TIMER = 30, //!<(cluster-internal) CNTPNSIRQ - EL1 Non-secure physical timer event* + RSVD_INTERRUPT_31 = 31, //!< Reserved. + RSVD_INTERRUPT_32 = 32, //!< Reserved. + RSVD_INTERRUPT_33 = 33, //!< Reserved. + RSVD_INTERRUPT_34 = 34, //!< Reserved. + RSVD_INTERRUPT_35 = 35, //!< Reserved. + RSVD_INTERRUPT_36 = 36, //!< Reserved. + RSVD_INTERRUPT_37 = 37, //!< Reserved. + RSVD_INTERRUPT_38 = 38, //!< Reserved. + RSVD_INTERRUPT_39 = 39, //!< Reserved. + RSVD_INTERRUPT_40 = 40, //!< Reserved. + RSVD_INTERRUPT_41 = 41, //!< Reserved. + RSVD_INTERRUPT_42 = 42, //!< Reserved. + + LS_INT_DUART1 = 64, // Logical OR of DUART1 interrupt requests. + + LS_INT_I2C1_2 = 66, //!< I2C1 and I2C2 ORed + LS_INT_I2C3_4 = 67, //!< I2C3 and I2C4 ORed + LS_INT_GPIO1_2 = 68, //!< GPIO1 and GPIO2 ORed + LS_INT_GPIO3 = 69, //!< GPIO3 + + LS_INT_FLETIMER1 = 76, //!< ORed all Flextimer 1 interrupt signals + LS_INT_FLETIMER2 = 77, //!< ORed all Flextimer 2 interrupt signals + LS_INT_FLETIMER3 = 78, //!< ORed all Flextimer 3 interrupt signals + LS_INT_FLETIMER4 = 79, //!< ORed all Flextimer 4 interrupt signals + + LS_INT_I2C5_6 = 106, //!< I2C5 and I2C6 ORed + LS_INT_I2C7_8 = 107, //!< I2C7 and I2C8 ORed + + LS_INT_USB3_1 = 112, //!< USB1 ORed INT + LS_INT_USB3_2 = 113, //!< USB2 ORed INT + + LS_INT_LPUART1 = 264, //!< LPUART1 interrupt request. + LS_INT_LPUART2 = 265, //!< LPUART1 interrupt request. + LS_INT_LPUART3 = 266, //!< LPUART1 interrupt request. + LS_INT_LPUART4 = 267, //!< LPUART1 interrupt request. + LS_INT_LPUART5 = 268, //!< LPUART1 interrupt request. + LS_INT_LPUART6 = 269, //!< LPUART1 interrupt request. + + NR_OK1028_INTRS, + +}; + +#endif //__IRQ_NUMBERS_H__ \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c new file mode 100644 index 000000000..f28c7a6a3 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file trap.c + * @brief trap interface of hardkernel + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2023.05.06 + */ + +/************************************************* +File name: trap.c +Description: trap interface of hardkernel +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#include + +#include "exception_registers.h" + +#include "assert.h" +#include "core.h" +#include "multicores.h" +#include "syscall.h" +#include "task.h" + +#include "mmu.h" + +extern void dabort_handler(struct trapframe* r); +extern void iabort_handler(struct trapframe* r); + +void kernel_abort_handler(struct trapframe* tf) +{ + uint64_t esr = r_esr_el1(); + switch ((esr >> 0x1A) & 0x3F) { + case 0b100100: + case 0b100101: + dabort_handler(tf); + break; + case 0b100000: + case 0b100001: + iabort_handler(tf); + break; + default: { + uint64_t ec = (esr >> 26) & 0x3f; + uint64_t iss = esr & 0x1ffffff; + ERROR("esr: %016lx %016lx %016lx\n", esr, ec, iss); + ERROR("elr = %016lx far = %016lx\n", r_elr_el1(), r_far_el1()); + ERROR("Current Task: %s.\n", cur_cpu()->task->name); + panic("Unimplemented Error Occured.\n"); + } + } + panic("Return from abort handler.\n"); +} + +void kernel_intr_handler(struct trapframe* tf) +{ + panic("Intr at kernel mode should never happen by design.\n"); +} + +extern void context_switch(struct context**, struct context*); +void syscall_arch_handler(struct trapframe* tf) +{ + + uint64_t esr = r_esr_el1(); + uint64_t ec = (esr >> 0x1A) & 0x3F; + switch (ec) { + case 0B010101: + software_irq_dispatch(tf); + break; + case 0b100100: + case 0b100101: + dabort_handler(tf); + break; + case 0b100000: + case 0b100001: + iabort_handler(tf); + break; + default: { + ERROR("USYSCALL: unexpected\n"); + ERROR(" esr: %016lx\n", esr); + ERROR(" elr = %016lx far = %016lx\n", r_elr_el1(), r_far_el1()); + w_esr_el1(0); + extern void dump_tf(struct trapframe * tf); + dump_tf(tf); + + uint32_t sctlr = 0; + SCTLR_R(sctlr); + DEBUG("SCTLR: %x\n", sctlr); + uint32_t spsr = 0; +// __asm__ volatile("mrs %0, spsr_el1" : "=r"(spsr)::"memory"); + DEBUG("SPSR: %x\n", spsr); + uint64_t tcr = 0; +// __asm__ volatile("mrs %0, tcr_el1" : "=r"(tcr)::"memory"); + DEBUG("TCR: %x\n", tcr); + uint64_t mair = 0; +// __asm__ volatile("mrs %0, mair_el1" : "=r"(mair)::"memory"); + DEBUG("MAIR: %x\n", mair); + + // kill error task + xizi_enter_kernel(); + assert(cur_cpu()->task != NULL); + ERROR("Error Task: %s\n", cur_cpu()->task->name); + sys_exit(cur_cpu()->task); + context_switch(&cur_cpu()->task->thread_context.context, cur_cpu()->scheduler); + panic("dabort end should never be reashed.\n"); + } + } +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c new file mode 100644 index 000000000..003c64acc --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file trap_common.c + * @brief trap interface of hardkernel + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2023.05.06 + */ + +/************************************************* +File name: trap_common.c +Description: trap interface of hardkernel +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#include + +#include "core.h" +#include "cortex.h" +#include "exception_registers.h" +#include "gicv3_common_opa.h" +#include "trap_common.h" + +#include "log.h" +#include "multicores.h" + +static struct XiziTrapDriver xizi_trap_driver; + +void panic(char* s) +{ + KPrintf("panic: %s\n", s); + for (;;) + ; +} + +extern void alltraps(); +static void _sys_irq_init(int cpu_id) +{ + // primary core init intr + xizi_trap_driver.switch_hw_irqtbl((uintptr_t*)alltraps); + + if (cpu_id == 0) { + gic_init(); + } + gicv3inithart(cpu_id); +} + +static void _cpu_irq_enable(void) +{ + intr_on(); +} + +static void _cpu_irq_disable(void) +{ + intr_off(); +} + +static void _single_irq_enable(int irq, int cpu, int prio) +{ + gic_setup_ppi((uint32_t)cpu, (uint32_t)irq); +} + +static void _single_irq_disable(int irq, int cpu) +{ + return; +} + +static inline uintptr_t* _switch_hw_irqtbl(uintptr_t* new_tbl_base) +{ + w_vbar_el1((uint64_t)new_tbl_base); + + return NULL; +} + +static void _bind_irq_handler(int irq, irq_handler_t handler) +{ + xizi_trap_driver.sw_irqtbl[irq].handler = handler; +} + +static uint32_t _hw_before_irq() +{ + + uint32_t iar = gic_read_irq_ack(); + return iar; +} + +static uint32_t _hw_cur_int_num(uint32_t int_info) +{ + return int_info & 0x3FF; +} + +static void _hw_after_irq(uint32_t int_info) +{ + gic_write_end_of_irq(int_info); +} + +int _cur_cpu_id() +{ + return cpu_get_current(); +} + +static struct XiziTrapDriver xizi_trap_driver = { + .sys_irq_init = _sys_irq_init, + .cur_cpu_id = _cur_cpu_id, + + .cpu_irq_enable = _cpu_irq_enable, + .cpu_irq_disable = _cpu_irq_disable, + .single_irq_enable = _single_irq_enable, + .single_irq_disable = _single_irq_disable, + .switch_hw_irqtbl = _switch_hw_irqtbl, + + .bind_irq_handler = _bind_irq_handler, + + .hw_before_irq = _hw_before_irq, + .hw_cur_int_num = _hw_cur_int_num, + .hw_after_irq = _hw_after_irq, +}; + +struct XiziTrapDriver* hardkernel_intr_init(struct TraceTag* hardkernel_tag) +{ + xizi_trap_driver.sys_irq_init(0); + xizi_trap_driver.cpu_irq_disable(); + return &xizi_trap_driver; +} diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S new file mode 100644 index 000000000..f89a63bc0 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file trampoline.S + * @brief trap in and out code + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024-04-22 + */ + +/************************************************* +File name: trampoline.S +Description: trap in and out code +Others: +History: +1. Date: 2024-04-22 +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ + +#include "memlayout.h" + +#include "core.h" + +.macro savereg + +.endm + +.macro restorereg + +.endm + +.macro usavereg + +.endm + +.macro urestorereg + +.endm + + +.global alltraps +.balign 0x800 +alltraps: +// Current EL with sp0 + j badtrap +.balign 0x80 + j badtrap +.balign 0x80 + j badtrap +.balign 0x80 + j badtrap + +// Current EL with spx +.balign 0x80 + j el1sync +.balign 0x80 + j el1irq +.balign 0x80 + j badtrap +.balign 0x80 + j badtrap + +// Lower EL using aarch64 +.balign 0x80 + j el0sync +.balign 0x80 + j el0irq +.balign 0x80 + j badtrap +.balign 0x80 + j badtrap + +// Lower EL using aarch32 +.balign 0x80 + j badtrap +.balign 0x80 + j badtrap +.balign 0x80 + j badtrap +.balign 0x80 + j badtrap + +badtrap: + j . + +el1sync: + j . + +el1irq: + ret + +el0sync: + + ret + +el0irq: + jal intr_irq_dispatch + +.global trap_return +trap_return: + ret diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/Makefile index 5a96ab711..aaba3c920 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/Makefile @@ -1,4 +1,9 @@ +ifneq ($(findstring $(BOARD), 3568 imx6q-sabrelite zynq7000-zc702), ) SRC_DIR := arm +endif +ifneq ($(findstring $(BOARD), jh7110), ) +SRC_DIR := riscv +endif include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/Makefile index 8b1378917..dd587adc4 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/Makefile @@ -1 +1,5 @@ +ifneq ($(findstring $(BOARD), jh7110), ) +SRC_DIR := rv64gc +endif +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/Makefile new file mode 100644 index 000000000..6b8df00e5 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := bootmmu.c mmu.c pagetable_attr.c + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c new file mode 100644 index 000000000..ba391ff25 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file bootmmu.c + * @brief build pagetable and enable mmu in boot time + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.04.26 + */ + +/************************************************* +File name: bootmmu.c +Description: build pagetable and enable mmu in boot time +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#include "core.h" +#include "memlayout.h" +#include "mmio_access.h" +#include "mmu.h" +#include "pagetable.h" +#include "registers.h" + +#include +#include + +extern uint64_t kernel_data_end[]; +extern uint64_t kernel_data_begin[]; + +// clang-format off +#define L2_TYPE_TAB 2 +#define L2_PTE_VALID 1 + +#define L3_TYPE_TAB 2 +#define L3_PTE_VALID 1 + +#define L4_TYPE_PAGE (3 << 0) +#define L4_PTE_DEV ((0b00) << 2) // Device memory +#define L4_PTE_NORMAL ((0b01) << 2) // Device memory +#define L4_PTE_AF (1 << 10) // Data Access Permissions + +#define L4_PTE_PXN (1UL << 53) // Privileged eXecute Never +#define L4_PTE_UXN (1UL << 54) // Unprivileged(user) eXecute Never +#define L4_PTE_XN (PTE_PXN|PTE_UXN) // eXecute Never + +#define IDX_MASK (0b111111111) +#define L3_PDE_INDEX(idx) ((idx << LEVEL3_PDE_SHIFT) & L3_IDX_MASK) +// clang-format on + +uint64_t boot_l2pgdir[NUM_LEVEL2_PDE] __attribute__((aligned(0x1000))) = { 0 }; + +uint64_t boot_dev_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 }; +uint64_t boot_kern_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 }; + +uint64_t boot_dev_l4pgdirs[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 }; +uint64_t boot_kern_l4pgdirs[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 }; + +static void build_boot_pgdir() +{ + static bool built = false; + if (!built) { + uint64_t dev_phy_mem_base = DEV_PHYMEM_BASE; + + // dev mem + boot_l2pgdir[(dev_phy_mem_base >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID; + boot_l2pgdir[(MMIO_P2V_WO(dev_phy_mem_base) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID; + + uint64_t cur_mem_paddr = ALIGNDOWN((uint64_t)DEV_PHYMEM_BASE, LEVEL2_PDE_SIZE); + for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) { + boot_dev_l3pgdir[i] = (uint64_t)boot_dev_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID; + + for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) { + boot_dev_l4pgdirs[i][j] = cur_mem_paddr | L4_TYPE_PAGE | L4_PTE_DEV | L4_PTE_AF | L4_PTE_XN; + if (cur_mem_paddr >= DEV_PHYMEM_BASE && cur_mem_paddr < DEV_PHYMEM_BASE + DEV_MEM_SIZE) { + boot_dev_l4pgdirs[i][j] = cur_mem_paddr | 0x403; + } else { + boot_dev_l4pgdirs[i][j] = cur_mem_paddr | 0x403; + } + + cur_mem_paddr += PAGE_SIZE; + } + } + + // identical mem + boot_l2pgdir[(PHY_MEM_BASE >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID; + boot_l2pgdir[(P2V_WO(PHY_MEM_BASE) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID; + + cur_mem_paddr = ALIGNDOWN((uint64_t)0x00000000ULL, PAGE_SIZE); + for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) { + boot_kern_l3pgdir[i] = (uint64_t)boot_kern_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID; + + for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) { + boot_kern_l4pgdirs[i][j] = cur_mem_paddr | 0x713; + + cur_mem_paddr += PAGE_SIZE; + } + } + + built = true; + } +} + +static void load_boot_pgdir() +{ + + TTBR0_W((uintptr_t)boot_l2pgdir); + TTBR1_W(0); + +#define TCR_TRUE_VALUE (0x0000000080813519ULL) + uint64_t tcr = 0; + TCR_R(tcr); + tcr &= (uint64_t)~0xFF; + tcr |= 0x19; + TCR_W(tcr); + + CLEARTLB(0); + ISB(); +} + + +extern void main(void); +static bool _bss_inited = false; +void bootmain() +{ +#if 0 + build_boot_pgdir(); + load_boot_pgdir(); +// __asm__ __volatile__("add sp, sp, %0" ::"r"(KERN_OFFSET)); + if (!_bss_inited) { + memset(&kernel_data_begin, 0x00, (size_t)((uint64_t)kernel_data_end - (uint64_t)kernel_data_begin)); + _bss_inited = true; + } +#endif + main(); +} + diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/include/mmu.h b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/include/mmu.h new file mode 100644 index 000000000..034a5ddf8 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/include/mmu.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file mmu.h + * @brief mmu related configure and registers + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024-04-26 + */ +/************************************************* +File name: mmu.h +Description: mmu related configure and registers +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#pragma once + +#include + +#include "memlayout.h" + +// #define TCR_SH1_INNER (0b11 << 28) +// #define TCR_ORGN1_IRGN1_WRITEBACK_WRITEALLOC ((0b01 << 26) | (0b01 << 24)) +// #define TCR_SH0_INNER (0b11 << 12) +// #define TCR_ORGN0_IRGN0_WRITEBACK_WRITEALLOC ((0b01 << 10) | (0b01 << 8)) +#define TCR_IPS (0 << 0) +#define TCR_TG1_4K (0b10 << 30) +#define TCR_TOSZ (0b11001 << 0) +#define TCR_T1SZ (0b11001 << 16) +#define TCR_TG0_4K (0 << 14) + +#define TCR_VALUE \ + (TCR_IPS | TCR_TG1_4K | TCR_TG0_4K | TCR_TOSZ | TCR_T1SZ) + +enum AccessPermission { + AccessPermission_NoAccess = 0, + AccessPermission_KernelOnly = 1, // EL1 + AccessPermission_Reserved = 2, + AccessPermission_KernelUser = 3, // EL1&EL0 +}; + +void GetDevPteAttr(uintptr_t* attr); +void GetUsrPteAttr(uintptr_t* attr); +void GetUsrDevPteAttr(uintptr_t* attr); +void GetKernPteAttr(uintptr_t* attr); +void GetPdeAttr(uintptr_t* attr); + +/* +Enable MMU, cache, write buffer, etc. +*/ +//#define SCTLR_R(val) __asm__ volatile("mrs %0, sctlr_el1" : "=r"(val)::"memory") +//#define SCTLR_W(val) __asm__ volatile("msr sctlr_el1, %0" ::"r"(val) : "memory") +#define SCTLR_R(val) 0 +#define SCTLR_W(val) 0 + +/* +Read and write mmu pagetable register base addr +*/ +//#define TTBR0_R(val) __asm__ volatile("mrs %0, ttbr0_el1" : "=r"(val)::"memory") +//#define TTBR0_W(val) __asm__ volatile("msr ttbr0_el1, %0" ::"r"(val) : "memory") +#define TTBR0_R(val) 0 +#define TTBR0_W(val) 0 + +/* +Read and write mmu pagetable register base addr +*/ +//#define TTBR1_R(val) __asm__ volatile("mrs %0, ttbr1_el1" : "=r"(val)::"memory") +//#define TTBR1_W(val) __asm__ volatile("msr ttbr1_el1, %0" ::"r"(val) : "memory") +#define TTBR1_R(val) 0 +#define TTBR1_W(val) 0 + +/* +Translation Control Register（TCR） +*/ +//#define TCR_R(val) __asm__ volatile("mrs %0, tcr_el1" : "=r"(val)::"memory") +//#define TCR_W(val) __asm__ volatile("msr tcr_el1, %0" ::"r"(val) : "memory") +#define TCR_R(val) 0 +#define TCR_W(val) 0 + +//#define MAIR_R(val) __asm__ volatile("mrs %0, mair_el1" : "=r"(val)::"memory") +//#define MAIR_W(val) __asm__ volatile("msr mair_el1, %0" ::"r"(val) : "memory") +#define MAIR_R(val) 0 +#define MAIR_W(val) 0 +/* +Flush TLB when loading a new page table. +@note If nG is not set in the pte attribute, process switching need flush tlb. +*/ +// #define CLEARTLB(val) __asm__ volatile("tlbi vmalle1" ::: "memory") +//#define CLEARTLB(val) __asm__ volatile("tlbi vmalle1is" ::: "memory") +#define CLEARTLB(val) 0 + +/* +When nG is set in the pte attribute, the process is assigned an ASID, which is stored in the lower 8 bits of the CONTEXTIDR register. +When the process switches, the flush TLB is no longer required anymore. +*/ +//#define CONTEXTIDR_R(val) __asm__ volatile("mrs %0, contextidr_el1" : "=r"(val)) +//#define CONTEXTIDR_W(val) __asm__ volatile("msr contextidr_el1, %0" ::"r"(val)) +#define CONTEXTIDR_R(val) 0 +#define CONTEXTIDR_W(val) 0 + +#ifndef __ASSEMBLER__ +#include +__attribute__((always_inline)) static inline uint64_t v2p(void* a) { return ((uint64_t)(a)) - KERN_MEM_BASE; } +__attribute__((always_inline)) static inline void* p2v(uint64_t a) { return (void*)((a) + KERN_MEM_BASE); } +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h new file mode 100644 index 000000000..ef7e8ef24 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file memlayout.h + * @brief virtual memory and physical memory layout + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024-04-25 + */ +/************************************************* +File name: memlayout.h +Description: virtual memory and physical memory layout +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#pragma once + +// Memory layout +// clang-format off + +#define ARCH_BIT 64 + +/* A55 physical memory layout */ +#define PHY_MEM_BASE (0x0000000010000000ULL) +#define PHY_USER_FREEMEM_BASE (0x0000000040000000ULL) +#define PHY_USER_FREEMEM_TOP (0x00000000e0000000ULL) +#define PHY_MEM_STOP (0x00000000e0000000ULL) + +/* PTE-PAGE_SIZE */ +#define LEVEL4_PTE_SHIFT 12 +#define LEVEL4_PTE_SIZE (1 << LEVEL4_PTE_SHIFT) + +/* PDE-SECTION_SIZE */ +#define LEVEL3_PDE_SHIFT 21 +#define LEVEL3_PDE_SIZE (1 << LEVEL3_PDE_SHIFT) + +#define LEVEL2_PDE_SHIFT 30 +#define LEVEL2_PDE_SIZE (1 << LEVEL2_PDE_SHIFT) + +#define LEVEL1_PTE_SHIFT 39 + +#define NUM_LEVEL2_PDE (1 << (LEVEL1_PTE_SHIFT - LEVEL2_PDE_SHIFT)) +#define NUM_LEVEL3_PDE (1 << (LEVEL2_PDE_SHIFT - LEVEL3_PDE_SHIFT)) // how many PDE in a PT +#define NUM_LEVEL4_PTE (1 << (LEVEL3_PDE_SHIFT - LEVEL4_PTE_SHIFT)) // how many PTE in a PT +#define NUM_TOPLEVEL_PDE NUM_LEVEL2_PDE + +#define PAGE_SIZE LEVEL4_PTE_SIZE +#define MAX_NR_FREE_PAGES ((PHY_USER_FREEMEM_BASE - PHY_MEM_BASE) >> LEVEL4_PTE_SHIFT) + +/* Deivce memory layout */ +#define DEV_PHYMEM_BASE (0x00000000F0000000ULL) +#define DEV_VRTMEM_BASE (0x00000040F0000000ULL) +#define DEV_MEM_SIZE (0x0000000010000000ULL) + +/* User memory layout */ +#define USER_STACK_SIZE PAGE_SIZE +#define USER_MEM_BASE (0x0000000000000000ULL) +#define USER_MEM_TOP (0x0000004000000000ULL) +#define USER_IPC_SPACE_BASE (0x0000003000000000ULL) +#define USER_IPC_USE_ALLOCATOR_WATERMARK (0x0000003000010000ULL) +#define USER_IPC_SPACE_TOP (USER_IPC_SPACE_BASE + 0x10000000ULL) + +/* Kernel memory layout */ +#define KERN_MEM_BASE (0x0000006010000000ULL) // First kernel virtual address +#define KERN_OFFSET (KERN_MEM_BASE - PHY_MEM_BASE) + +#define V2P(a) (((uint64_t)(a)) - KERN_OFFSET) +#define P2V(a) ((void *)(((char *)(a)) + KERN_OFFSET)) + +#define V2P_WO(x) ((x) - KERN_OFFSET) // same as V2P, but without casts +#define P2V_WO(x) ((x) + KERN_OFFSET) // same as P2V, but without casts +// clang-format on \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c new file mode 100644 index 000000000..7fcf5a1f6 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file mmu.c + * @brief mmu operations + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.04.26 + */ + +/************************************************* +File name: mmu.c +Description: mmu operations +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ + +#include + +#include "mmu.h" + +#include "cache_common_ope.h" +#include "mmu_common.h" +#include "trap_common.h" + +// extern struct MmuCommonDone mmu_common_done; +static struct MmuDriverRightGroup right_group; + +void load_pgdir(uintptr_t pgdir_paddr) +{ + /* get cache driver */ + struct ICacheDone* p_icache_done = AchieveResource(&right_group.icache_driver_tag); + struct DCacheDone* p_dcache_done = AchieveResource(&right_group.dcache_driver_tag); + + TTBR0_W((uint64_t)pgdir_paddr); + DSB(); + CLEARTLB(0); + ISB(); + p_icache_done->invalidateall(); + p_dcache_done->flushall(); +} + +__attribute__((always_inline)) inline static void _tlb_flush(uintptr_t va) +{ +// __asm__ volatile("tlbi vae1is, %0" ::"r"(va)); +} + +static void tlb_flush_range(uintptr_t vstart, int len) +{ + uintptr_t vaddr = vstart; + uintptr_t vend = vaddr + len; + for (; vaddr < vend; vaddr += PAGE_SIZE) { + _tlb_flush(vaddr); + } +} + +static void tlb_flush_all() +{ + CLEARTLB(0); +} + +static struct MmuCommonDone mmu_common_done = { + .MmuDevPteAttr = GetDevPteAttr, + .MmuPdeAttr = GetPdeAttr, + .MmuUsrPteAttr = GetUsrPteAttr, + .MmuUsrDevPteAttr = GetUsrDevPteAttr, + .MmuKernPteAttr = GetKernPteAttr, + + .LoadPgdir = load_pgdir, + .TlbFlushAll = tlb_flush_all, + .TlbFlush = tlb_flush_range, +}; + +struct MmuCommonDone* hardkernel_mmu_init(struct TraceTag* hardkernel_tag, char* icache_name, char* dcache_name) +{ + /* init right group for mmu driver */ + AchieveResourceTag(&right_group.icache_driver_tag, hardkernel_tag, icache_name); + AchieveResourceTag(&right_group.dcache_driver_tag, hardkernel_tag, dcache_name); + + return &mmu_common_done; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/pagetable_attr.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/pagetable_attr.c new file mode 100644 index 000000000..8085ad036 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/pagetable_attr.c @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file pagetable_attr.c + * @brief mmu entry attributes + * @version 1. + * @author AIIT XUOS Lab + * @date 2023.04.26 + */ + +/************************************************* +File name: pagetable_attr.c +Description: mmu entry attributes +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#include "mmu.h" +#include "mmu_common.h" + +// clang-format off +#define ARMV8_PTE_ATTR_MASK(attr) (((attr) & 0b111) << 2) +#define ARMV8_PTE_DEVICE ARMV8_PTE_ATTR_MASK(0x0) +#define ARMV8_PTE_NORMAL ARMV8_PTE_ATTR_MASK(0x1) + +#define ARMV8_PTE_AP(ap) (((ap) & 0b11) << 6) +#define ARMV8_PTE_AP_U ARMV8_PTE_AP(0x01) +#define ARMV8_PTE_AP_K ARMV8_PTE_AP(0x00) +#define ARMV8_PTE_AP_RO ARMV8_PTE_AP(0b10) +#define ARMV8_PTE_AP_RW ARMV8_PTE_AP(0b00) + +#define ARMV8_PTE_AF (0x1 << 10) +#define ARMV8_PTE_PXN (1ULL << 53) // Privileged eXecute Never +#define ARMV8_PTE_UXN (1ULL << 54) // Unprivileged(user) eXecute Never +#define ARMV8_PTE_XN (ARMV8_PTE_PXN | ARMV8_PTE_UXN) + +#define ARMV8_PTE_VALID (0b11 << 0) +#define ARMV8_PDE_VALID (0b11 << 0) + +// clang-format on + +void GetUsrPteAttr(uintptr_t* attr) +{ + // *attr = ARMV8_PTE_AP_U | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_NORMAL | ARMV8_PTE_VALID; + *attr = 0x713 | ARMV8_PTE_AP_U; +} + +void GetUsrDevPteAttr(uintptr_t* attr) +{ + // *attr = ARMV8_PTE_AP_U | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_DEVICE | ARMV8_PTE_XN | ARMV8_PTE_VALID; + *attr = 0x403 | ARMV8_PTE_AP_U; +} + +void GetDevPteAttr(uintptr_t* attr) +{ + // *attr = ARMV8_PTE_AP_K | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_DEVICE | ARMV8_PTE_XN | ARMV8_PTE_VALID; + *attr = 0x403ULL; +} + +void GetKernPteAttr(uintptr_t* attr) +{ + // *attr = ARMV8_PTE_AP_K | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_NORMAL | ARMV8_PTE_VALID; + *attr = 0x713ULL; +} + +void GetPdeAttr(uintptr_t* attr) +{ + *attr = ARMV8_PDE_VALID; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/uart/Makefile index b555517f4..f18170cb0 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/uart/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/Makefile @@ -1,4 +1,10 @@ +ifneq ($(findstring $(BOARD), 3568 imx6q-sabrelite zynq7000-zc702), ) SRC_DIR := arm +endif +ifneq ($(findstring $(BOARD), jh7110), ) +SRC_DIR := riscv +endif + SRC_FILES := uart_common_ope.c include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/Makefile new file mode 100644 index 000000000..dd587adc4 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/Makefile @@ -0,0 +1,5 @@ +ifneq ($(findstring $(BOARD), jh7110), ) +SRC_DIR := rv64gc +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/Makefile new file mode 100644 index 000000000..42d2e83f3 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/Makefile @@ -0,0 +1,3 @@ +SRC_DIR := uart_io_for_$(BOARD) + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/Makefile new file mode 100644 index 000000000..a8661f85c --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := uart.c ns16550.c + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h new file mode 100644 index 000000000..8847befca --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h @@ -0,0 +1,198 @@ +/* + * NS16550 Serial Port + * originally from linux source (arch/powerpc/boot/ns16550.h) + * + * Cleanup and unification + * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH + * + * modified slightly to + * have addresses as offsets from CONFIG_SYS_ISA_BASE + * added a few more definitions + * added prototypes for ns16550.c + * reduced no of com ports to 2 + * modifications (c) Rob Taylor, Flying Pig Systems. 2000. + * + * added support for port on 64-bit bus + * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems + */ + +/* + * Note that the following macro magic uses the fact that the compiler + * will not allocate storage for arrays of size 0 + */ + +#include + +/* + * For driver model we always use one byte per register, and sort out the + * differences in the driver + */ +#define CONFIG_SYS_NS16550_REG_SIZE (-1) + +#define UART_REG(x) \ + unsigned char x; \ + unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1]; + +/** + * struct ns16550_platdata - information about a NS16550 port + * + * @base: Base register address + * @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...) + * @clock: UART base clock speed in Hz + */ +struct ns16550_platdata { + unsigned long base; + int reg_shift; + int clock; + int reg_offset; + uint32_t fcr; +}; + +struct udevice; + +struct NS16550 { + UART_REG(rbr); /* 0 */ + UART_REG(ier); /* 1 */ + UART_REG(fcr); /* 2 */ + UART_REG(lcr); /* 3 */ + UART_REG(mcr); /* 4 */ + UART_REG(lsr); /* 5 */ + UART_REG(msr); /* 6 */ + UART_REG(spr); /* 7 */ +#ifdef CONFIG_SOC_DA8XX + UART_REG(reg8); /* 8 */ + UART_REG(reg9); /* 9 */ + UART_REG(revid1); /* A */ + UART_REG(revid2); /* B */ + UART_REG(pwr_mgmt); /* C */ + UART_REG(mdr1); /* D */ +#else + UART_REG(mdr1); /* 8 */ + UART_REG(reg9); /* 9 */ + UART_REG(regA); /* A */ + UART_REG(regB); /* B */ + UART_REG(regC); /* C */ + UART_REG(regD); /* D */ + UART_REG(regE); /* E */ + UART_REG(uasr); /* F */ + UART_REG(scr); /* 10*/ + UART_REG(ssr); /* 11*/ +#endif +#ifdef CONFIG_DM_SERIAL + struct ns16550_platdata* plat; +#endif +}; + +#define thr rbr +#define iir fcr +#define dll rbr +#define dlm ier + +typedef struct NS16550* NS16550_t; + +/* + * These are the definitions for the FIFO Control Register + */ +#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ +#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ +#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ +#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ +#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ +#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ + +#define UART_FCR_RXSR 0x02 /* Receiver soft reset */ +#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ + +/* Ingenic JZ47xx specific UART-enable bit. */ +#define UART_FCR_UME 0x10 + +/* Clear & enable FIFOs */ +#define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR) + +/* + * These are the definitions for the Modem Control Register + */ +#define UART_MCR_DTR 0x01 /* DTR */ +#define UART_MCR_RTS 0x02 /* RTS */ +#define UART_MCR_OUT1 0x04 /* Out 1 */ +#define UART_MCR_OUT2 0x08 /* Out 2 */ +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ +#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */ + +#define UART_MCR_DMA_EN 0x04 +#define UART_MCR_TX_DFR 0x08 + +/* + * These are the definitions for the Line Control Register + * + * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting + * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. + */ +#define UART_LCR_WLS_MSK 0x03 /* character length select mask */ +#define UART_LCR_WLS_5 0x00 /* 5 bit character length */ +#define UART_LCR_WLS_6 0x01 /* 6 bit character length */ +#define UART_LCR_WLS_7 0x02 /* 7 bit character length */ +#define UART_LCR_WLS_8 0x03 /* 8 bit character length */ +#define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */ +#define UART_LCR_PEN 0x08 /* Parity eneble */ +#define UART_LCR_EPS 0x10 /* Even Parity Select */ +#define UART_LCR_STKP 0x20 /* Stick Parity */ +#define UART_LCR_SBRK 0x40 /* Set Break */ +#define UART_LCR_BKSE 0x80 /* Bank select enable */ +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ + +/* + * These are the definitions for the Line Status Register + */ +#define UART_LSR_DR 0x01 /* Data ready */ +#define UART_LSR_OE 0x02 /* Overrun */ +#define UART_LSR_PE 0x04 /* Parity error */ +#define UART_LSR_FE 0x08 /* Framing error */ +#define UART_LSR_BI 0x10 /* Break */ +#define UART_LSR_THRE 0x20 /* Xmit holding register empty */ +#define UART_LSR_TEMT 0x40 /* Xmitter empty */ +#define UART_LSR_ERR 0x80 /* Error */ + +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ +#define UART_MSR_RI 0x40 /* Ring Indicator */ +#define UART_MSR_DSR 0x20 /* Data Set Ready */ +#define UART_MSR_CTS 0x10 /* Clear to Send */ +#define UART_MSR_DDCD 0x08 /* Delta DCD */ +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ +#define UART_MSR_DDSR 0x02 /* Delta DSR */ +#define UART_MSR_DCTS 0x01 /* Delta CTS */ + +/* + * These are the definitions for the Interrupt Identification Register + */ +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ +#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ + +#define UART_IIR_MSI 0x00 /* Modem status interrupt */ +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ + +/* + * These are the definitions for the Interrupt Enable Register + */ +#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ +#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ + +/* useful defaults for LCR */ +#define UART_LCR_8N1 0x03 + +void NS16550_init(NS16550_t com_port, int baud_divisor); +void NS16550_putc(NS16550_t com_port, char c); +char NS16550_getc(NS16550_t com_port); +int NS16550_tstc(NS16550_t com_port); +void NS16550_reinit(NS16550_t com_port, int baud_divisor); + +void _debug_uart_init(void); +void _debug_uart_putc(int ch); +int _debug_uart_getc(void); \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/uart.h b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/uart.h new file mode 100644 index 000000000..a168a10e7 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/uart.h @@ -0,0 +1,29 @@ +#pragma once + +#include "memlayout.h" +#include "mmio_access.h" + +#define UART0_BASE (0x09000000ULL) +#define UART0_REG(reg) ((volatile uint32_t*)(MMIO_P2V_WO(UART0_BASE + reg))) + +// the UART control registers. +// pl011 +#define DR 0x00 +#define FR 0x18 +#define FR_RXFE (1 << 4) // recieve fifo empty +#define FR_TXFF (1 << 5) // transmit fifo full +#define FR_RXFF (1 << 6) // recieve fifo full +#define FR_TXFE (1 << 7) // transmit fifo empty +#define IBRD 0x24 +#define FBRD 0x28 +#define LCRH 0x2c +#define LCRH_FEN (1 << 4) +#define LCRH_WLEN_8BIT (3 << 5) +#define CR 0x30 +#define IMSC 0x38 +#define INT_RX_ENABLE (1 << 4) +#define INT_TX_ENABLE (1 << 5) +#define ICR 0x44 + +#define UART_READ_REG(reg) (*(UART0_REG(reg))) +#define UART_WRITE_REG(reg, v) (*(UART0_REG(reg)) = (v)) \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c new file mode 100644 index 000000000..d9a607d2b --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c @@ -0,0 +1,111 @@ +/* + * COM1 NS16550 support + * originally from linux source (arch/powerpc/boot/ns16550.c) + * modified to use CONFIG_SYS_ISA_MEM and new defines + */ + +#include + +#include "mmio_access.h" +#include "ns16550.h" + +//#define UART_ADDR MMIO_P2V_WO(0xFE660000) +//#define UART_ADDR (0xFE660000) +#define UART_ADDR MMIO_P2V_WO (10000000) + +#define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ +#define UART_MCRVAL (UART_MCR_DTR | UART_MCR_RTS) /* RTS/DTR */ + +#define out_le32(a, v) (*(volatile uint32_t*)(a) = (v)) +#define in_le32(a) (*(volatile uint32_t*)(a)) + +#ifndef CONFIG_SYS_NS16550_IER +#define CONFIG_SYS_NS16550_IER 0x00 +#endif /* CONFIG_SYS_NS16550_IER */ + +#define serial_dout(reg, value) \ + serial_out_shift((char*)com_port + ((char*)reg - (char*)com_port) * (1 << 2), \ + 2, value) +#define serial_din(reg) \ + serial_in_shift((char*)com_port + ((char*)reg - (char*)com_port) * (1 << 2), \ + 2) + +static inline void serial_out_shift(void* addr, int shift, int value) +{ + out_le32(addr, value); +} + +static inline int serial_in_shift(void* addr, int shift) +{ + return in_le32(addr); +} + +#ifndef CONFIG_SYS_NS16550_CLK +#define CONFIG_SYS_NS16550_CLK 0 +#endif + +#if 0 +#define DIV_ROUND_CLOSEST(x, divisor) ( \ + { \ + typeof(x) __x = x; \ + typeof(divisor) __d = divisor; \ + (((typeof(x))-1) > 0 || ((typeof(divisor))-1) > 0 || (__x) > 0) ? (((__x) + ((__d) / 2)) / (__d)) : (((__x) - ((__d) / 2)) / (__d)); \ + }) +#endif +#define DIV_ROUND_CLOSEST(x, divisor) ( \ + { \ + ((x) > 0) ? (((x) + ((divisor) / 2)) / (divisor)) : (((x) - ((divisor) / 2)) / (divisor)); \ + }) + + +int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate) +{ + const unsigned int mode_x_div = 16; + + return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate); +} + +void _debug_uart_init(void) +{ + struct NS16550* com_port = (struct NS16550*)UART_ADDR; + + /* + * We copy the code from above because it is already horribly messy. + * Trying to refactor to nicely remove the duplication doesn't seem + * feasible. The better fix is to move all users of this driver to + * driver model. + */ + int baud_divisor = ns16550_calc_divisor(com_port, 24000000, + 115200); + serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER); + serial_dout(&com_port->mcr, UART_MCRVAL); + serial_dout(&com_port->fcr, UART_FCR_DEFVAL); + + serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL); + serial_dout(&com_port->dll, baud_divisor & 0xff); + serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff); + serial_dout(&com_port->lcr, UART_LCRVAL); +} + +void _debug_uart_putc(int ch) +{ + static struct NS16550* com_port = (struct NS16550*)UART_ADDR; + + if (ch == '\n') { + _debug_uart_putc('\r'); + } + + while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) + ; + serial_dout(&com_port->thr, ch); +} + +int _debug_uart_getc(void) +{ + static struct NS16550* com_port = (struct NS16550*)UART_ADDR; + + while (!(serial_din(&com_port->lsr) & UART_LSR_DR)) + ; + + return serial_din(&com_port->rbr); +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/uart.c b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/uart.c new file mode 100644 index 000000000..de03611a2 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/uart.c @@ -0,0 +1,45 @@ +// +// low-level driver routines for pl011 UART. +// + +#include "uart.h" +#include "actracer.h" +#include "ns16550.h" +#include "uart_common_ope.h" + +// the UART control registers are memory-mapped +// at address UART0. this macro returns the +// address of one of the registers. + +void uartinit(void) +{ + _debug_uart_init(); +} + +void uartputc(uint8_t c) +{ + _debug_uart_putc((int)c); +} + +static uint8_t uartgetc(void) +{ + return (uint8_t)_debug_uart_getc(); +} + +static uint32_t UartGetIrqnum() +{ + return 0; +} + +static struct XiziSerialDriver hardkernel_serial_driver = { + .sys_serial_init = uartinit, + .get_serial_irqnum = UartGetIrqnum, + .putc = uartputc, + .getc = uartgetc, +}; + +struct XiziSerialDriver* hardkernel_uart_init(struct TraceTag* hardkernel_tag) +{ + hardkernel_serial_driver.sys_serial_init(); + return &hardkernel_serial_driver; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/path_kernel.mk b/Ubiquitous/XiZi_AIoT/path_kernel.mk index 2a8bca965..da097bfc9 100755 --- a/Ubiquitous/XiZi_AIoT/path_kernel.mk +++ b/Ubiquitous/XiZi_AIoT/path_kernel.mk @@ -54,6 +54,21 @@ KERNELPATHS += \ -I$(KERNEL_ROOT)/hardkernel/cache/L1/arm/cortex-a55/ endif +ifeq ($(BOARD), jh7110) +KERNELPATHS += \ + -I$(KERNEL_ROOT)/hardkernel/arch/riscv/rv64gc/preboot_for_$(BOARD)/include \ + -I$(KERNEL_ROOT)/hardkernel/arch/riscv/rv64gc/ \ + -I$(KERNEL_ROOT)/hardkernel/cache/L1/riscv/rv64gc/ \ + -I$(KERNEL_ROOT)/hardkernel/clock/riscv/rv64gc/$(BOARD)/include \ + -I$(KERNEL_ROOT)/hardkernel/intr/riscv/rv64gc/ \ + -I$(KERNEL_ROOT)/hardkernel/intr/riscv/rv64gc/$(BOARD) \ + -I$(KERNEL_ROOT)/hardkernel/intr/riscv/rv64gc/gicv3 \ + -I$(KERNEL_ROOT)/hardkernel/mmu/riscv/rv64gc/include \ + -I$(KERNEL_ROOT)/hardkernel/mmu/riscv/rv64gc/$(BOARD) \ + -I$(KERNEL_ROOT)/hardkernel/uart/riscv/rv64gc/uart_io_for_$(BOARD)/include \ + -I$(KERNEL_ROOT)/hardkernel/uart/riscv/rv64gc/ +endif + KERNELPATHS += \ -I$(KERNEL_ROOT)/hardkernel \ -I$(KERNEL_ROOT)/hardkernel/clock/ \ diff --git a/Ubiquitous/XiZi_AIoT/softkernel/load_apps.S b/Ubiquitous/XiZi_AIoT/softkernel/load_apps.S index 597d60af0..a12911287 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/load_apps.S +++ b/Ubiquitous/XiZi_AIoT/softkernel/load_apps.S @@ -30,16 +30,16 @@ Modification: .section .rawdata_fs_img .globl user_apps user_apps: - .incbin "../services/app/fs.img" +// .incbin "../services/app/fs.img" .section .rawdata_init .globl initapp initapp: - .incbin "../services/app/bin/shell" +// .incbin "../services/app/bin/shell" .section .rawdata_memfs .globl memfs memfs: - .incbin "../services/app/bin/fs_server" +// .incbin "../services/app/bin/fs_server" .end diff --git a/Ubiquitous/XiZi_AIoT/softkernel/memory/Makefile b/Ubiquitous/XiZi_AIoT/softkernel/memory/Makefile index 67cd1ed69..35bd24a90 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/memory/Makefile +++ b/Ubiquitous/XiZi_AIoT/softkernel/memory/Makefile @@ -8,6 +8,9 @@ endif ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), ) SRC_FILES:= kalloc.c pagetable.c pagetable_level2.c buddy.c object_allocator.c share_page.c endif +ifneq ($(findstring $(BOARD), jh7110), ) +SRC_FILES := kalloc.c pagetable.c pagetable_level3.c buddy.c object_allocator.c share_page.c +endif include $(KERNEL_ROOT)/compiler.mk