format the codes with ok1052-c board

2022-03-21 14:48:57 +08:00
parent c61c6dafea 9ffd8fcbbb
commit a52854efb6
685 changed files with 203920 additions and 2293 deletions
@@ -6,7 +6,8 @@ MAKEFLAGS += --no-print-directory


 support :=kd233 stm32f407-st-discovery maix-go stm32f407zgt6 aiit-riscv64-board aiit-arm32-board hifive1-rev-B hifive1-emulator k210-emulator cortex-m3-emulator cortex-m4-emulator ok1052-c gapuino stm32f103-nano gd32vf103_rvstar cortex-m0-emulator rv32m1_vega nuvoton-m2354
-SRC_DIR:=
+support += xidatong
+SRC_DIR :=

 export BOARD ?=kd233
 # This is the environment variable for kconfig-mconf
@@ -6,11 +6,11 @@

 | 名称 | 说明 |
 | -- | -- |
-| application | 应用代码 |
+| arch | 架构代码 |
 | board | 板级支持包 |
-| framework | 应用框架 |
 | fs | 文件系统 |
 | kernel | 内核源码 |
+| lib | 第三方库源码 |
 | resources | 驱动文件 |
 | tool | 系统工具 |
 | | |
@@ -23,13 +23,13 @@

 ARM架构系列的开发板有

-	aiit-arm32-board	stm32f407-st-discovery		stm32f407zgt6
+	aiit-arm32-board nuvoton-m2354 ok1052-c stm32f103-nano stm32f407-st-discovery stm32f407zgt6

 ### RISC-V

 RISC-V架构系列的开发板有

-	aiit-riscv64-board		hifive1-rev-B		kd233		maix-go
+	aiit-riscv64-board gapuino gd32vf103_rvstar hifive1-rev-B kd233 maix-go rv32m1_vega

 ## 开发环境

@@ -61,7 +61,7 @@ $ tar -zxvf gnu-mcu-eclipse-riscv-none-gcc-8.2.0-2.1-20190425-1021-centos64.tgz

 ### 烧写工具

-ARM：ST-LINK
+ARM：ST-LINK NU-LINK

 RISC-V：K-FLash

@@ -1,3 +1,11 @@
+/**
+* @file arch_interrupt.h
+* @brief support rv32m1_vega interrupt
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2022-02-16
+*/
+
 #ifndef ARCH_INTERRUPT_H__
 #define ARCH_INTERRUPT_H__

@@ -33,7 +33,7 @@ History:
 Author: AIIT XUOS Lab
 Modification:  
 *************************************************/
-
+.extern Rv32m1VgeaStart
 #define EXCEPTION_STACK_SIZE 0x58

    .text
@@ -108,7 +108,7 @@ Reset_Handler:
    # Enable global interrupt. */
    csrsi mstatus, 8

-    jal main
+    jal Rv32m1VgeaStart
    ebreak

    .size Reset_Handler, . - Reset_Handler
@@ -5,7 +5,7 @@
 | 硬件 | 描述 |
 | -- | -- |
 |芯片型号| Stm32F407zgt6|
-|CPU|arm cortex-m|
+|CPU|arm cortex-m4|
 |主频| 168MHz |
 |片内SRAM| 192KB |
 |扩展SRAM| 1MB |
@@ -30,23 +30,25 @@ sudo apt-get install gcc-arm-none-eabi
 >2.在代码根目录下执行以下命令，生成配置文件

 ```
+cd ./Ubiquitous/XiZi
+make BOARD=aiit-arm32-board distclean
 make BOARD=aiit-arm32-board menuconfig
 ```
 >3.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出

-![img](menu.png )
+![img](./img/menu.png )

 >4.继续执行以下命令，进行编译
 ```
 make BOARD=aiit-arm32-board
 ```
->5.如果编译正确无误，会产生XiUOS_aiit-arm32-board.elf、XiUOS_aiit-arm32-board.bin文件。其中XiUOS_aiit-arm32-board.bin需要烧写到设备中进行运行。
+>5.如果编译正确无误，会产生XiZi_aiit-arm32-board.elf、XiZi_aiit-arm32-board.bin文件。其中XiZi_aiit-arm32-board.bin需要烧写到设备中进行运行。
 ```
-sudo write build/XiUOS_aiit-arm32-board.bin 0x8000000
+sudo write build/XiZi_aiit-arm32-board.bin 0x8000000
 ```
 >6.最后可以执行以下命令，清除配置文件和编译生成的文件
 ```
-make  BOARD=aiit-arm32-board distclean
+make BOARD=aiit-arm32-board distclean
 ```

 ## 3. 烧写及执行
@@ -56,7 +58,7 @@ make  BOARD=aiit-arm32-board distclean
 st-link 图片如下：

 <div align= "center"> 
-<img src = st-link.png>
+<img src = ./img/st-link.png>
  </div>


@@ -66,15 +68,15 @@ git clone https://github.com/texane/stlink.git
 ```
 aiit-arm32-board下载连接示意图如下：
 <div align= "center"> 
-<img src = aiit.jpg>
+<img src = ./img/aiit.jpg>
  </div>

 代码根目录下执行st-flash工具烧录
 ```
-sudo st-flash  write  build/XiUOS_aiit-arm32-board.bin 0x8000000
+sudo st-flash write build/XiZi_aiit-arm32-board.bin 0x8000000
 ```
 ### 3.1 运行结果

 如果编译 & 烧写无误，将会在串口终端上看到信息打印输出，(终端串口引脚为PA9、PA10)。

-![img](shell.png )
+![img](./img/shell.png )
@@ -27,6 +27,8 @@ export CROSS_COMPILE ?=/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.1-20190425-10
 ```
 >2.在代码根目录下执行以下命令，生成配置文件
 ```
+cd ./Ubiquitous/XiZi
+make BOARD=aiit-riscv64-board distclean
 make BOARD=aiit-riscv64-board menuconfig
 ```
 >3.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后选择Exit保存并退出
@@ -34,7 +36,7 @@ make BOARD=aiit-riscv64-board menuconfig
 ```
 make BOARD=aiit-riscv64-board
 ```
->5.如果编译正确无误，会产生XiUOS_aiit-riscv64-board.elf、XiUOS_aiit-riscv64-board.bin文件。其中XiUOS_aiit-riscv64-board.bin需要烧写到设备中进行运行。
+>5.如果编译正确无误，会产生XiZi_aiit-riscv64-board.elf、XiZi_aiit-riscv64-board.bin文件。其中XiZi_aiit-riscv64-board.bin需要烧写到设备中进行运行。
 >注：最后可以执行以下命令，清除配置文件和编译生成的文件
 ```
 make BOARD=aiit-riscv64-board distclean
@@ -62,7 +64,7 @@ sudo pip2 install kflash
 ```
 代码根目录下执行K-Flash工具烧录，-p为USB端口号，视实际情况而定
 ```
-kflash -t build/XiUOS_aiit-riscv64-board.bin -p /dev/ttyUSB0
+kflash -t build/XiZi_aiit-riscv64-board.bin -p /dev/ttyUSB0
 ```
 ### 3.1 运行结果

@@ -63,23 +63,29 @@ $ sudo apt install build-essential pkg-config  git
 $ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev
 ```

-**XiUOS操作系统源码下载：** XiUOS [https://forgeplus.trustie.net/projects/xuos/xiuos](https://forgeplus.trustie.net/projects/xuos/xiuos)
+**XiUOS操作系统源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos)

 新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下：

 ```c
 mkdir test  &&  cd test
-git clone https://git.trustie.net/xuos/xiuos.git
+git clone https://gitlink.org.cn/xuos/xiuos.git
 ```

-打开源码文件包可以看到以下目录：
+1、打开XiUOS源码文件包可以看到以下目录：
 | 名称 | 说明 |
 | -- | -- |
-| application | 应用代码 |
+| APP_Framework | 应用代码 |
+| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 |
+
+2、打开XiZi内核源码文件包可以看到以下目录：
+| 名称 | 说明 |
+| -- | -- |
+| arch | 架构代码 |
 | board | 板级支持包 |
-| framework | 应用框架 |
 | fs | 文件系统 |
 | kernel | 内核源码 |
+| lib | 第三方库源码 |
 | resources | 驱动文件 |
 | tool | 系统工具 |

@@ -93,18 +99,18 @@ git clone https://git.trustie.net/xuos/xiuos.git

 裁减配置工具：

-**工具地址：** kconfig-frontends [https://forgeplus.trustie.net/projects/xuos/kconfig-frontends](https://forgeplus.trustie.net/projects/xuos/kconfig-frontends)，下载与安装的具体命令如下：
+**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)，下载与安装的具体命令如下：

 ```c
 mkdir kfrontends  && cd kfrontends
-git  clone https://git.trustie.net/xuos/kconfig-frontends.git
+git clone https://gitlink.org.cn/xuos/kconfig-frontends.git
 ```

 下载源码后按以下步骤执行软件安装：

 ```c
 cd kconfig-frontends
- ./xs_build.sh
+./xs_build.sh
 ```

 ### 编译工具链：
@@ -128,7 +134,9 @@ $ sudo apt install gcc-arm-none-eabi
 1.在VScode命令终端中执行以下命令，生成配置文件

 ```c
-   make BOARD=cortex-m0-emulator menuconfig
+cd ./Ubiquitous/XiZi
+make BOARD=cortex-m0-emulator distclean
+make BOARD=cortex-m0-emulator menuconfig
 ```

 2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置）
@@ -145,7 +153,7 @@ $ sudo apt install gcc-arm-none-eabi
 make BOARD=cortex-m0-emulator
 ```

-4.如果编译正确无误，会产生XiUOS_cortex-m0-emulator.elf、XiUOS_cortex-m0-emulator.bin文件。
+4.如果编译正确无误，会产生XiZi_cortex-m0-emulator.elf、XiZi_cortex-m0-emulator.bin文件。

 ## 3. 运行

@@ -160,7 +168,7 @@ sudo apt install qemu-system-arm
 通过以下命令启动Q‎EMU并加载XiUOS ELF文件

 ```
-qemu-system-arm -machine microbit -nographic -kernel build/XiUOS_cortex-m0-emulator.elf
+qemu-system-arm -machine microbit -nographic -kernel build/XiZi_cortex-m0-emulator.elf
 ```

 QEMU运行起来后将会在终端上看到信息打印输出
@@ -177,11 +185,11 @@ sudo apt install gdb-multiarch
 并通过以下命令启动Q‎EMU

 ```
-qemu-system-arm -machine microbit -nographic -kernel build/XiUOS_cortex-m0-emulator.elf -s -S
+qemu-system-arm -machine microbit -nographic -kernel build/XiZi_cortex-m0-emulator.elf -s -S
 ```

 然后要重新开启另一个linux系统终端一个终端，执行命令

 ```
-gdb-multiarch build/XiUOS_cortex-m0-emulator.elf -ex "target remote localhost:1234" 
+gdb-multiarch build/XiZi_cortex-m0-emulator.elf -ex "target remote localhost:1234" 
 ```
@@ -63,23 +63,29 @@ $ sudo apt install build-essential pkg-config  git
 $ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev
 ```

-**XiUOS操作系统源码下载：** XiUOS [https://forgeplus.trustie.net/projects/xuos/xiuos](https://forgeplus.trustie.net/projects/xuos/xiuos)
+**XiUOS操作系统源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos)

 新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下：

 ```c
 mkdir test  &&  cd test
-git clone https://git.trustie.net/xuos/xiuos.git
+git clone https://gitlink.org.cn/xuos/xiuos.git
 ```

-打开源码文件包可以看到以下目录：
+1、打开XiUOS源码文件包可以看到以下目录：
 | 名称 | 说明 |
 | -- | -- |
-| application | 应用代码 |
+| APP_Framework | 应用代码 |
+| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 |
+
+2、打开XiZi内核源码文件包可以看到以下目录：
+| 名称 | 说明 |
+| -- | -- |
+| arch | 架构代码 |
 | board | 板级支持包 |
-| framework | 应用框架 |
 | fs | 文件系统 |
 | kernel | 内核源码 |
+| lib | 第三方库源码 |
 | resources | 驱动文件 |
 | tool | 系统工具 |

@@ -93,18 +99,18 @@ git clone https://git.trustie.net/xuos/xiuos.git

 裁减配置工具：

-**工具地址：** kconfig-frontends [https://forgeplus.trustie.net/projects/xuos/kconfig-frontends](https://forgeplus.trustie.net/projects/xuos/kconfig-frontends)，下载与安装的具体命令如下：
+**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)，下载与安装的具体命令如下：

 ```c
 mkdir kfrontends  && cd kfrontends
-git  clone https://git.trustie.net/xuos/kconfig-frontends.git
+git clone https://gitlink.org.cn/xuos/kconfig-frontends.git
 ```

 下载源码后按以下步骤执行软件安装：

 ```c
 cd kconfig-frontends
- ./xs_build.sh
+./xs_build.sh
 ```

 ### 编译工具链：
@@ -128,7 +134,9 @@ $ sudo apt install gcc-arm-none-eabi
 1.在VScode命令终端中执行以下命令，生成配置文件

 ```c
-   make BOARD=cortex-m3-emulator menuconfig
+cd ./Ubiquitous/XiZi
+make BOARD=cortex-m3-emulator distclean
+make BOARD=cortex-m3-emulator menuconfig
 ```

 2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置）
@@ -145,7 +153,7 @@ $ sudo apt install gcc-arm-none-eabi
 make BOARD=cortex-m3-emulator
 ```

-4.如果编译正确无误，会产生XiUOS_cortex-m3-emulator.elf、XiUOS_cortex-m3-emulator.bin文件。
+4.如果编译正确无误，会产生XiZi_cortex-m3-emulator.elf、XiZi_cortex-m3-emulator.bin文件。

 ## 3. 运行

@@ -160,7 +168,7 @@ sudo apt install qemu-system-arm
 通过以下命令启动Q‎EMU并加载XiUOS ELF文件

 ```
-qemu-system-arm -machine  lm3s6965evb -nographic -kernel build/XiUOS_cortex-m3-emulator.elf
+qemu-system-arm -machine  lm3s6965evb -nographic -kernel build/XiZi_cortex-m3-emulator.elf
 ```

 QEMU运行起来后将会在终端上看到信息打印输出
@@ -177,11 +185,11 @@ sudo apt install gdb-multiarch
 并通过以下命令启动Q‎EMU

 ```
-qemu-system-arm -machine  lm3s6965evb -nographic -kernel build/XiUOS_cortex-m3-emulator.elf -s -S
+qemu-system-arm -machine  lm3s6965evb -nographic -kernel build/XiZi_cortex-m3-emulator.elf -s -S
 ```

 然后要重新开启另一个linux系统终端一个终端，执行`riscv-none-embed-gdb`命令

 ```
-gdb-multiarch build/XiUOS_cortex-m3-emulator.elf -ex "target remote localhost:1234" 
+gdb-multiarch build/XiZi_cortex-m3-emulator.elf -ex "target remote localhost:1234" 
 ```
@@ -63,26 +63,31 @@ $ sudo apt install build-essential pkg-config  git
 $ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev
 ```

-**XiUOS操作系统源码下载：** XiUOS [https://forgeplus.trustie.net/projects/xuos/xiuos](https://forgeplus.trustie.net/projects/xuos/xiuos)
+**XiUOS操作系统源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos)

 新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下：

 ```c
 mkdir test  &&  cd test
-git clone https://git.trustie.net/xuos/xiuos.git
+git clone https://gitlink.org.cn/xuos/xiuos.git
 ```

-打开源码文件包可以看到以下目录：
+1、打开XiUOS源码文件包可以看到以下目录：
+| 名称 | 说明 |
+| -- | -- |
+| APP_Framework | 应用代码 |
+| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 |

-| 名称        | 说明       |
-| ----------- | ---------- |
-| application | 应用代码   |
-| board       | 板级支持包 |
-| framework   | 应用框架   |
-| fs          | 文件系统   |
-| kernel      | 内核源码   |
-| resources   | 驱动文件   |
-| tool        | 系统工具   |
+2、打开XiZi内核源码文件包可以看到以下目录：
+| 名称 | 说明 |
+| -- | -- |
+| arch | 架构代码 |
+| board | 板级支持包 |
+| fs | 文件系统 |
+| kernel | 内核源码 |
+| lib | 第三方库源码 |
+| resources | 驱动文件 |
+| tool | 系统工具 |

 使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示：

@@ -95,18 +100,18 @@ git clone https://git.trustie.net/xuos/xiuos.git

 裁减配置工具：

-**工具地址：** kconfig-frontends [https://forgeplus.trustie.net/projects/xuos/kconfig-frontends](https://forgeplus.trustie.net/projects/xuos/kconfig-frontends)，下载与安装的具体命令如下：
+**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)，下载与安装的具体命令如下：

 ```c
 mkdir kfrontends  && cd kfrontends
-git  clone https://git.trustie.net/xuos/kconfig-frontends.git
+git clone https://gitlink.org.cn/xuos/kconfig-frontends.git
 ```

 下载源码后按以下步骤执行软件安装：

 ```c
 cd kconfig-frontends
- ./xs_build.sh
+./xs_build.sh
 ```

 ### 编译工具链：
@@ -133,7 +138,9 @@ $ sudo apt install gcc-arm-none-eabi
 1.在VScode命令终端中执行以下命令，生成配置文件

 ```c
-   make BOARD=cortex-m4-emulator menuconfig
+cd ./Ubiquitous/XiZi
+make BOARD=cortex-m4-emulator distclean
+make BOARD=cortex-m4-emulator menuconfig
 ```

 2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置）
@@ -154,7 +161,7 @@ $ sudo apt install gcc-arm-none-eabi
 make BOARD=cortex-m4-emulator
 ```

-4.如果编译正确无误，会产生XiUOS_cortex-m4-emulator.elf、XiUOS_cortex-m4-emulator.bin文件。
+4.如果编译正确无误，会产生XiZi_cortex-m4-emulator.elf、XiZi_cortex-m4-emulator.bin文件。



@@ -171,7 +178,7 @@ sudo apt install qemu-system-arm
 通过以下命令启动Q‎EMU并加载XiUOS ELF文件

 ```
-qemu-system-arm -machine netduinoplus2  -nographic -kernel build/XiUOS_cortex-m4-emulator.elf
+qemu-system-arm -machine netduinoplus2  -nographic -kernel build/XiZi_cortex-m4-emulator.elf
 ```

 QEMU运行起来后将会在终端上看到信息打印输出
@@ -191,11 +198,11 @@ sudo apt install gdb-multiarch
 并通过以下命令启动Q‎EMU

 ```
-qemu-system-arm -machine netduinoplus2  -nographic -kernel build/XiUOS_cortex-m4-emulator.elf -s -S
+qemu-system-arm -machine netduinoplus2  -nographic -kernel build/XiZi_cortex-m4-emulator.elf -s -S
 ```

 然后要重新开启另一个linux系统终端一个终端，执行`riscv-none-embed-gdb`命令

 ```
-gdb-multiarch build/XiUOS_cortex-m4-emulator.elf -ex "target remote localhost:1234" 
+gdb-multiarch build/XiZi_cortex-m4-emulator.elf -ex "target remote localhost:1234" 
 ```
@@ -71,26 +71,31 @@ $ sudo apt install build-essential pkg-config  git
 $ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev
 ```

-**XiUOS操作系统源码下载：** XiZi [https://forgeplus.trustie.net/projects/xuos/xiuos](https://forgeplus.trustie.net/projects/xuos/xiuos)
+**XiUOS操作系统源码下载：** XiZi [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos)

 新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下：

 ```c
 mkdir test  &&  cd test
-git clone https://git.trustie.net/xuos/xiuos.git
+git clone https://gitlink.org.cn/xuos/xiuos.git
 ```

-打开源码文件包可以看到以下目录：
+1、打开XiUOS源码文件包可以看到以下目录：
+| 名称 | 说明 |
+| -- | -- |
+| APP_Framework | 应用代码 |
+| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 |

-| 名称        | 说明       |
-| ----------- | ---------- |
-| application | 应用代码   |
-| board       | 板级支持包 |
-| framework   | 应用框架   |
-| fs          | 文件系统   |
-| kernel      | 内核源码   |
-| resources   | 驱动文件   |
-| tool        | 系统工具   |
+2、打开XiZi内核源码文件包可以看到以下目录：
+| 名称 | 说明 |
+| -- | -- |
+| arch | 架构代码 |
+| board | 板级支持包 |
+| fs | 文件系统 |
+| kernel | 内核源码 |
+| lib | 第三方库源码 |
+| resources | 驱动文件 |
+| tool | 系统工具 |

 使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示：

@@ -102,18 +107,18 @@ git clone https://git.trustie.net/xuos/xiuos.git

 裁减配置工具：

-**工具地址：** kconfig-frontends [https://forgeplus.trustie.net/projects/xuos/kconfig-frontends](https://forgeplus.trustie.net/projects/xuos/kconfig-frontends)，下载与安装的具体命令如下：
+**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)，下载与安装的具体命令如下：

 ```c
 mkdir kfrontends  && cd kfrontends
-git  clone https://git.trustie.net/xuos/kconfig-frontends.git
+git clone https://gitlink.org.cn/xuos/kconfig-frontends.git
 ```

 下载源码后按以下步骤执行软件安装：

 ```c
 cd kconfig-frontends
- ./xs_build.sh
+./xs_build.sh
 ```

 #### 编译工具链：
@@ -140,7 +145,9 @@ $ sudo apt install gcc-arm-none-eabi
 1.在VScode命令终端中执行以下命令，生成配置文件

 ```c
-   make BOARD=cortex-m4-emulator menuconfig
+cd ./Ubiquitous/XiZi
+make BOARD=cortex-m4-emulator distclean
+make BOARD=cortex-m4-emulator menuconfig
 ```

 2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置）
@@ -163,7 +170,7 @@ $ sudo apt install gcc-arm-none-eabi
 make BOARD=cortex-m4-emulator
 ```

-4.如果编译正确无误，会产生XiUOS_cortex-m4-emulator.elf、XiUOS_cortex-m4-emulator.bin文件。
+4.如果编译正确无误，会产生XiZi_cortex-m4-emulator.elf、XiZi_cortex-m4-emulator.bin文件。



@@ -196,7 +203,7 @@ sudo apt install qemu-system-arm
 通过以下命令启动Q‎EMU并加载XiUOS ELF文件

 ```
-qemu-system-arm -machine netduinoplus2  -nographic -kernel build/XiUOS_cortex-m4-emulator.elf
+qemu-system-arm -machine netduinoplus2  -nographic -kernel build/XiZi_cortex-m4-emulator.elf
 ```

 QEMU运行起来后将会在终端上看到信息打印输出
@@ -217,13 +224,13 @@ sudo apt install gdb-multiarch
 并通过以下命令启动Q‎EMU

 ```
-qemu-system-arm -machine netduinoplus2  -nographic -kernel build/XiUOS_cortex-m4-emulator.elf -s -S
+qemu-system-arm -machine netduinoplus2  -nographic -kernel build/XiZi_cortex-m4-emulator.elf -s -S
 ```

 然后要重新开启另一个linux系统终端一个终端，执行`riscv-none-embed-gdb`命令

 ```
-gdb-multiarch build/XiUOS_cortex-m4-emulator.elf -ex "target remote localhost:1234" 
+gdb-multiarch build/XiZi_cortex-m4-emulator.elf -ex "target remote localhost:1234" 
 ```


@@ -18,23 +18,29 @@ $ sudo apt install build-essential pkg-config
 $ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev  git
 ```

-**源码下载：** XiUOS [https://forgeplus.trustie.net/projects/xuos/xiuos](https://forgeplus.trustie.net/projects/xuos/xiuos)
+**源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos)

 新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下：

 ```c
 mkdir test  &&  cd test
-git clone https://git.trustie.net/xuos/xiuos.git
+git clone https://gitlink.org.cn/xuos/xiuos.git
 ```

-打开源码文件包可以看到以下目录：
+1、打开XiUOS源码文件包可以看到以下目录：
 | 名称 | 说明 |
 | -- | -- |
-| application | 应用代码 |
+| APP_Framework | 应用代码 |
+| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 |
+
+2、打开XiZi内核源码文件包可以看到以下目录：
+| 名称 | 说明 |
+| -- | -- |
+| arch | 架构代码 |
 | board | 板级支持包 |
-| framework | 应用框架 |
 | fs | 文件系统 |
 | kernel | 内核源码 |
+| lib | 第三方库源码 |
 | resources | 驱动文件 |
 | tool | 系统工具 |

@@ -46,18 +52,18 @@ git clone https://git.trustie.net/xuos/xiuos.git

 裁减配置工具：

-**工具地址：** kconfig-frontends [https://forgeplus.trustie.net/projects/xuos/kconfig-frontends](https://forgeplus.trustie.net/projects/xuos/kconfig-frontends)
+**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)

 ```c
 mkdir kfrontends  && cd kfrontends
-git  clone https://git.trustie.net/xuos/kconfig-frontends.git
+git clone https://gitlink.org.cn/xuos/kconfig-frontends.git
 ```

 下载源码后按以下步骤执行软件安装：

 ```c
 cd kconfig-frontends
- ./xs_build.sh
+./xs_build.sh
 ```

 ### 编译工具链：
@@ -98,7 +104,7 @@ XiUOS板级当前支持使用UART。

 使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入终端即可打开目标项目

-修改`applications`文件夹下`main.c`
+修改`APP_Framework/Applications`文件夹下`main.c`

 在输出函数中写入  Hello, world! \n 完成代码编辑。

@@ -108,6 +114,8 @@ XiUOS板级当前支持使用UART。
 1.在VScode终端下执行以下命令，生成配置文件

 ```
+cd ./Ubiquitous/XiZi
+make BOARD=gapuino distclean
 make BOARD=gapuino menuconfig
 ```

@@ -121,7 +129,7 @@ make BOARD=gapuino menuconfig
 make BOARD=gapuino
 ```

-4.如果编译正确无误，build文件夹下会产生XiUOS_gapuino.elf、XiUOS_gapuino.bin文件。
+4.如果编译正确无误，build文件夹下会产生XiZi_gapuino.elf、XiZi_gapuino.bin文件。

 >注：最后可以执行以下命令，清除配置文件和编译生成的文件

@@ -164,7 +172,7 @@ screen /dev/ttyUSB0 115200

 5、打开一个新的终端，进入编译生成的elf路径,输入例如：
 ```
-riscv32-unknown-elf-gdb build/XiUOS_gapuino.elf -ex "target remote localhost:3333"
+riscv32-unknown-elf-gdb build/XiZi_gapuino.elf -ex "target remote localhost:3333"
 ```
 结果如下图所示：
 ![gdb](./img/gdb_load.png)
@@ -18,23 +18,29 @@ $ sudo apt install build-essential pkg-config
 $ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev  git
 ```

-**源码下载：** XiUOS [https://forgeplus.trustie.net/projects/xuos/xiuos](https://forgeplus.trustie.net/projects/xuos/xiuos)
+**源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos)

 新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下：

 ```c
 mkdir test  &&  cd test
-git clone https://git.trustie.net/xuos/xiuos.git
+git clone https://gitlink.org.cn/xuos/xiuos.git
 ```

-打开源码文件包可以看到以下目录：
+1、打开XiUOS源码文件包可以看到以下目录：
 | 名称 | 说明 |
 | -- | -- |
-| application | 应用代码 |
+| APP_Framework | 应用代码 |
+| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 |
+
+2、打开XiZi内核源码文件包可以看到以下目录：
+| 名称 | 说明 |
+| -- | -- |
+| arch | 架构代码 |
 | board | 板级支持包 |
-| framework | 应用框架 |
 | fs | 文件系统 |
 | kernel | 内核源码 |
+| lib | 第三方库源码 |
 | resources | 驱动文件 |
 | tool | 系统工具 |

@@ -46,18 +52,18 @@ git clone https://git.trustie.net/xuos/xiuos.git

 裁减配置工具：

-**工具地址：** kconfig-frontends [https://forgeplus.trustie.net/projects/xuos/kconfig-frontends](https://forgeplus.trustie.net/projects/xuos/kconfig-frontends)
+**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)

 ```c
 mkdir kfrontends  && cd kfrontends
-git  clone https://git.trustie.net/xuos/kconfig-frontends.git
+git clone https://gitlink.org.cn/xuos/kconfig-frontends.git
 ```

 下载源码后按以下步骤执行软件安装：

 ```c
 cd kconfig-frontends
- ./xs_build.sh
+./xs_build.sh
 ```

 ### 编译工具链：
@@ -99,7 +105,7 @@ XiUOS板级当前支持使用UART。

 使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入终端即可打开目标项目

-修改`applications`文件夹下`main.c`
+修改`APP_Framework/Applications`文件夹下`main.c`

 在输出函数中写入  Hello, world! \n 完成代码编辑。

@@ -109,6 +115,8 @@ XiUOS板级当前支持使用UART。
 1.在VScode终端下执行以下命令，生成配置文件

 ```
+cd ./Ubiquitous/XiZi
+make BOARD=gd32vf103_rvstar distclean
 make BOARD=gd32vf103_rvstar menuconfig
 ```

@@ -122,7 +130,7 @@ make BOARD=gd32vf103_rvstar menuconfig
 make BOARD=gd32vf103_rvstar
 ```

-4.如果编译正确无误，build文件夹下会产生XiUOS_gd32vf103_rvstar.elf、XiUOS_gd32vf103_rvstar.bin文件。
+4.如果编译正确无误，build文件夹下会产生XiZi_gd32vf103_rvstar.elf、XiZi_gd32vf103_rvstar.bin文件。

 >注：最后可以执行以下命令，清除配置文件和编译生成的文件

@@ -146,7 +154,7 @@ openocd安装完成以后，按照如下步骤进行调试：

 1、进入xiuos目录路径下
 ```
-cd ~/xiuos/Ubiquitous/XiUOS 
+cd ~/xiuos/Ubiquitous/XiZi 
 ```

 2、编译生成elf文件
@@ -169,7 +177,7 @@ screen /dev/ttyUSB0 115200

 5、打开一个新的终端，进入编译生成的elf路径,输入例如：
 ```
-riscv-nuclei-elf-gdb build/XiUOS_gd32vf103_rvstar.elf -ex "target remote localhost:3333"
+riscv-nuclei-elf-gdb build/XiZi_gd32vf103_rvstar.elf -ex "target remote localhost:3333"
 ```
 结果如下图所示：
 ![gdb](./img/gdb_load.png)
@@ -33,23 +33,29 @@ $ sudo apt install build-essential pkg-config
 $ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev  git
 ```

-**XiUOS操作系统源码下载：** XiUOS [https://forgeplus.trustie.net/projects/xuos/xiuos](https://forgeplus.trustie.net/projects/xuos/xiuos)
+**XiUOS操作系统源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos)

 新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下：

 ```c
 mkdir test  &&  cd test
-git clone https://git.trustie.net/xuos/xiuos.git
+git clone https://gitlink.org.cn/xuos/xiuos.git
 ```

-打开源码文件包可以看到以下目录：
+1、打开XiUOS源码文件包可以看到以下目录：
 | 名称 | 说明 |
 | -- | -- |
-| application | 应用代码 |
+| APP_Framework | 应用代码 |
+| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 |
+
+2、打开XiZi内核源码文件包可以看到以下目录：
+| 名称 | 说明 |
+| -- | -- |
+| arch | 架构代码 |
 | board | 板级支持包 |
-| framework | 应用框架 |
 | fs | 文件系统 |
 | kernel | 内核源码 |
+| lib | 第三方库源码 |
 | resources | 驱动文件 |
 | tool | 系统工具 |

@@ -61,19 +67,19 @@ git clone https://git.trustie.net/xuos/xiuos.git

 ### 裁减配置工具的下载

-**裁减配置工具：** kconfig-frontends [https://forgeplus.trustie.net/projects/xuos/kconfig-frontends](https://forgeplus.trustie.net/projects/xuos/kconfig-frontends)
+**裁减配置工具：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)
 执行以下命令下载配置工具：

 ```c
 mkdir kfrontends  && cd kfrontends
-git  clone https://git.trustie.net/xuos/kconfig-frontends.git
+git clone https://gitlink.org.cn/xuos/kconfig-frontends.git
 ```

 下载源码后按以下步骤执行软件安装：

 ```c
 cd kconfig-frontends
- ./xs_build.sh
+./xs_build.sh
 ```

 ### 编译工具链：
@@ -81,7 +87,7 @@ cd kconfig-frontends
 RISC-V: riscv-none-embed-，默认安装到Ubuntu的/opt/，下载源码并解压。[下载网址 http://101.36.126.201:8011/gnu-mcu-eclipse.tar.bz2](http://101.36.126.201:8011/gnu-mcu-eclipse.tar.bz2)，下载完成后，执行以下命令：

 ```c
- sudo tar -xvjf gnu-mcu-eclipse.tar.bz2 -C /opt/
+sudo tar -xvjf gnu-mcu-eclipse.tar.bz2 -C /opt/
 ```

 在VScode中将上述解压的编译工具链的路径添加到board/hifive1-emulator/config.mk文件当中，操作如下：
@@ -97,6 +103,8 @@ export CROSS_COMPILE ?=/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.1-20190425-10
 1.在`VScode`的“命令终端”中执行以下命令，生成配置文件

 ```
+cd ./Ubiquitous/XiZi
+make BOARD=hifive1-emulator distclean
 make BOARD=hifive1-emulator menuconfig
 ```

@@ -122,7 +130,7 @@ make BOARD=hifive1-emulator menuconfig
 make BOARD=hifive1-emulator
 ```

-4.如果编译正确无误，会在build目录下产生XiUOS_hifive1-emulator.elf、XiUOS_hifive1-emulator.bin文件。
+4.如果编译正确无误，会在build目录下产生XiZi_hifive1-emulator.elf、XiZi_hifive1-emulator.bin文件。

 ## 3. 运行

@@ -145,7 +153,7 @@ sudo make install
 通过以下命令启动Q‎EMU并加载XiUOS ELF文件

 ```
-qemu-system-riscv32 -nographic -machine sifive_e -kernel build/XiUOS_hifive1-emulator.elf
+qemu-system-riscv32 -nographic -machine sifive_e -kernel build/XiZi_hifive1-emulator.elf
 ```

 QEMU运行起来后将会在终端上看到信息打印输出
@@ -157,11 +165,11 @@ QEMU运行起来后将会在终端上看到信息打印输出
 利用Q‎EMU可以方便的对XiUOS进行调试，首先通过以下命令启动Q‎EMU

 ```
-qemu-system-riscv32 -nographic -machine sifive_e -kernel build/XiUOS_hifive1-emulator.elf -s -S
+qemu-system-riscv32 -nographic -machine sifive_e -kernel build/XiZi_hifive1-emulator.elf -s -S
 ```

 然后要重新开启另一个linux系统终端一个终端，执行`riscv-none-embed-gdb`命令

 ```
-riscv-none-embed-gdb build/XiUOS_hifive1-emulator.elf -ex "target remote localhost:1234"
+riscv-none-embed-gdb build/XiZi_hifive1-emulator.elf -ex "target remote localhost:1234"
 ```
@@ -19,23 +19,29 @@ $ sudo apt install build-essential pkg-config
 $ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev  git
 ```

-**源码下载：** XiUOS [https://forgeplus.trustie.net/projects/xuos/xiuos](https://forgeplus.trustie.net/projects/xuos/xiuos)
+**源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos)

 新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下：

 ```c
 mkdir test  &&  cd test
-git clone https://git.trustie.net/xuos/xiuos.git
+git clone https://gitlink.org.cn/xuos/xiuos.git
 ```

-打开源码文件包可以看到以下目录：
+1、打开XiUOS源码文件包可以看到以下目录：
 | 名称 | 说明 |
 | -- | -- |
-| application | 应用代码 |
+| APP_Framework | 应用代码 |
+| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 |
+
+2、打开XiZi内核源码文件包可以看到以下目录：
+| 名称 | 说明 |
+| -- | -- |
+| arch | 架构代码 |
 | board | 板级支持包 |
-| framework | 应用框架 |
 | fs | 文件系统 |
 | kernel | 内核源码 |
+| lib | 第三方库源码 |
 | resources | 驱动文件 |
 | tool | 系统工具 |

@@ -49,11 +55,11 @@ git clone https://git.trustie.net/xuos/xiuos.git

 裁减配置工具：

-**工具地址：** kconfig-frontends [https://forgeplus.trustie.net/projects/xuos/kconfig-frontends](https://forgeplus.trustie.net/projects/xuos/kconfig-frontends)
+**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)

 ```c
 mkdir kfrontends  && cd kfrontends
-git  clone https://git.trustie.net/xuos/kconfig-frontends.git
+git clone https://gitlink.org.cn/xuos/kconfig-frontends.git
 ```

 下载源码后按以下步骤执行软件安装：
@@ -101,7 +107,7 @@ XiUOS板级当前支持使用UART。

 使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入终端即可打开目标项目

-修改`applications`文件夹下`main.c`
+修改`APP_Framework/Applications`文件夹下`main.c`

 在输出函数中写入  Hello, world!  \n running on Hifive1 Rev B  board完成代码编辑。

@@ -112,6 +118,8 @@ XiUOS板级当前支持使用UART。
 1.在VScode终端下执行以下命令，生成配置文件

 ```
+cd ./Ubiquitous/XiZi
+make BOARD=hifive1-rev-B distclean
 make BOARD=hifive1-rev-B menuconfig
 ```

@@ -125,7 +133,7 @@ make BOARD=hifive1-rev-B menuconfig
 make BOARD=hifive1-rev-B
 ```

-4.如果编译正确无误，build文件夹下会产生XiUOS_hifive1-rev-B.elf、XiUOS_hifive1-rev-B.bin文件。其中XiUOS_hifive1-rev-B.bin需要烧写到设备中进行运行。
+4.如果编译正确无误，build文件夹下会产生XiZi_hifive1-rev-B.elf、XiZi_hifive1-rev-B.bin文件。其中XiZi_hifive1-rev-B.bin需要烧写到设备中进行运行。

 >注：最后可以执行以下命令，清除配置文件和编译生成的文件

@@ -33,23 +33,29 @@ $ sudo apt install build-essential pkg-config
 $ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev  git
 ```

-**XiUOS操作系统源码下载：** XiUOS [https://forgeplus.trustie.net/projects/xuos/xiuos](https://forgeplus.trustie.net/projects/xuos/xiuos)
+**XiUOS操作系统源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos)

 新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下：

 ```c
 mkdir test  &&  cd test
-git clone https://git.trustie.net/xuos/xiuos.git
+git clone https://gitlink.org.cn/xuos/xiuos.git
 ```

-打开源码文件包可以看到以下目录：
+1、打开XiUOS源码文件包可以看到以下目录：
 | 名称 | 说明 |
 | -- | -- |
-| application | 应用代码 |
+| APP_Framework | 应用代码 |
+| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 |
+
+2、打开XiZi内核源码文件包可以看到以下目录：
+| 名称 | 说明 |
+| -- | -- |
+| arch | 架构代码 |
 | board | 板级支持包 |
-| framework | 应用框架 |
 | fs | 文件系统 |
 | kernel | 内核源码 |
+| lib | 第三方库源码 |
 | resources | 驱动文件 |
 | tool | 系统工具 |

@@ -59,12 +65,12 @@ git clone https://git.trustie.net/xuos/xiuos.git

 ### 裁减配置工具的下载

-**裁减配置工具：** kconfig-frontends [https://forgeplus.trustie.net/projects/xuos/kconfig-frontends](https://forgeplus.trustie.net/projects/xuos/kconfig-frontends)
+**裁减配置工具：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)
 执行以下命令下载配置工具：

 ```c
 mkdir kfrontends  && cd kfrontends
-git  clone https://git.trustie.net/xuos/kconfig-frontends.git
+git clone https://gitlink.org.cn/xuos/kconfig-frontends.git
 ```

 下载源码后按以下步骤执行软件安装：
@@ -95,6 +101,8 @@ export CROSS_COMPILE ?=/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.1-20190425-10
 1.在`VScode`的“命令终端”中执行以下命令，生成配置文件

 ```
+cd ./Ubiquitous/XiZi
+make BOARD=k210-emulator distclean
 make BOARD=k210-emulator menuconfig
 ```

@@ -120,7 +128,7 @@ make BOARD=k210-emulator menuconfig
 make BOARD=k210-emulator
 ```

-4.如果编译正确无误，会在build目录下产生XiUOS_k210-emulator.elf、XiUOS_k210-emulator.bin文件。
+4.如果编译正确无误，会在build目录下产生XiZi_k210-emulator.elf、XiZi_k210-emulator.bin文件。

 ## 3. 运行

@@ -142,7 +150,7 @@ sudo make install
 通过以下命令启动Q‎EMU并加载XiUOS ELF文件

 ```
-qemu-system-riscv64 -nographic -machine sifive_u -bios build/XiUOS_k210-emulator.elf
+qemu-system-riscv64 -nographic -machine sifive_u -bios build/XiZi_k210-emulator.elf
 ```

 QEMU运行起来后将会在终端上看到信息打印输出
@@ -154,11 +162,11 @@ QEMU运行起来后将会在终端上看到信息打印输出
 利用Q‎EMU可以方便的对XiUOS进行调试，首先通过以下命令启动Q‎EMU

 ```
-qemu-system-riscv64 -nographic -machine sifive_u -bios build/XiUOS_k210-emulator.elf -s -S
+qemu-system-riscv64 -nographic -machine sifive_u -bios build/XiZi_k210-emulator.elf -s -S
 ```

 然后要重新开启另一个linux系统终端一个终端，执行`riscv-none-embed-gdb`命令

 ```
-riscv-none-embed-gdb build/XiUOS_k210-emulator.elf -ex "target remote localhost:1234"
+riscv-none-embed-gdb build/XiZi_k210-emulator.elf -ex "target remote localhost:1234"
 ```
@@ -18,22 +18,28 @@ $ sudo apt install build-essential pkg-config
 $ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev  git
 ```

-**源码下载：** XiUOS [https://forgeplus.trustie.net/projects/xuos/xiuos](https://forgeplus.trustie.net/projects/xuos/xiuos)
+**源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos)
 新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下：

 ```c
 mkdir test  &&  cd test
-git clone https://git.trustie.net/xuos/xiuos.git
+git clone https://gitlink.org.cn/xuos/xiuos.git
 ```

-打开源码文件包可以看到以下目录：
+1、打开XiUOS源码文件包可以看到以下目录：
 | 名称 | 说明 |
 | -- | -- |
-| application | 应用代码 |
+| APP_Framework | 应用代码 |
+| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 |
+
+2、打开XiZi内核源码文件包可以看到以下目录：
+| 名称 | 说明 |
+| -- | -- |
+| arch | 架构代码 |
 | board | 板级支持包 |
-| framework | 应用框架 |
 | fs | 文件系统 |
 | kernel | 内核源码 |
+| lib | 第三方库源码 |
 | resources | 驱动文件 |
 | tool | 系统工具 |

@@ -44,19 +50,19 @@ git clone https://git.trustie.net/xuos/xiuos.git
  </div>

 ### 裁减配置工具的下载
-**裁减配置工具：** kconfig-frontends [https://forgeplus.trustie.net/projects/xuos/kconfig-frontends](https://forgeplus.trustie.net/projects/xuos/kconfig-frontends)
+**裁减配置工具：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)
 执行以下命令下载配置工具：

 ```c
 mkdir kfrontends  && cd kfrontends
-git  clone https://git.trustie.net/xuos/kconfig-frontends.git
+git clone https://gitlink.org.cn/xuos/kconfig-frontends.git
 ```

 下载源码后按以下步骤执行软件安装：

 ```c
 cd kconfig-frontends
- ./xs_build.sh
+./xs_build.sh
 ```

 ### 编译工具链：
@@ -98,7 +104,7 @@ XiUOS板级当前支持使用GPIO、I2C、LCD、RTC、SPI、Timer、UART、watch
 编译工具链：`riscv-none-embed-gcc`
 使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入终端即可打开目标项目

-修改`applications`文件夹下`main.c`
+修改`APP_Framework/Applications`文件夹下`main.c`
 在输出函数中写入  Hello, world!!!  \n Running on KD233完成代码编辑。

 ![main](img/main.png)
@@ -108,7 +114,9 @@ XiUOS板级当前支持使用GPIO、I2C、LCD、RTC、SPI、Timer、UART、watch
 1.在`VScode`的“命令终端”下执行以下命令，生成配置文件

 ```c
-    make BOARD=kd233 menuconfig
+cd ./Ubiquitous/XiZi
+make BOARD=kd233 distclean
+make BOARD=kd233 menuconfig
 ```

 2.在`menuconfig`界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后选择Exit保存并退出（本实验无需选择任何选项，所以双击ESC结束选择，继续操作即可）。
@@ -132,15 +140,15 @@ XiUOS板级当前支持使用GPIO、I2C、LCD、RTC、SPI、Timer、UART、watch
 3.继续在`VScode`的“命令终端”中执行以下命令，进行编译

 ```c
-   make BOARD=kd233
+make BOARD=kd233
 ```

-4.如果编译正确无误，会在build文件夹下生成XiUOS_kd233.elf、XiUOS_kd233.bin文件。其中XiUOS_kd233.bin需要烧写到设备中进行运行。
+4.如果编译正确无误，会在build文件夹下生成XiZi_kd233.elf、XiZi_kd233.bin文件。其中XiZi_kd233.bin需要烧写到设备中进行运行。

 >注：最后可以执行以下命令，清除配置文件和编译生成的文件

 ```c
-   make BOARD=kd233 distclean
+make BOARD=kd233 distclean
 ```

 ## 3. 烧写及执行
@@ -170,7 +178,7 @@ sudo pip2 install kflash
 代码根目录下执行K-Flash工具烧录，-p为USB端口号，视实际情况而定

 ```
-sudo kflash -t build/XiUOS_kd233.bin -p /dev/ttyUSB0
+sudo kflash -t build/XiZi_kd233.bin -p /dev/ttyUSB0
 ```

 ### 3.1 运行结果
@@ -27,6 +27,8 @@ export CROSS_COMPILE ?=/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.1-20190425-10
 ```
 >2.在代码根目录下执行以下命令，生成配置文件
 ```
+cd ./Ubiquitous/XiZi
+make BOARD=maix-go distclean
 make BOARD=maix-go menuconfig
 ```
 >3.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后选择Exit保存并退出
@@ -34,7 +36,7 @@ make BOARD=maix-go menuconfig
 ```
 make BOARD=maix-go
 ```
->5.如果编译正确无误，会产生XiUOS_maix-go.elf、XiUOS_maix-go.bin文件。其中XiUOS_maix-go.bin需要烧写到设备中进行运行。
+>5.如果编译正确无误，会产生XiZi_maix-go.elf、XiZi_maix-go.bin文件。其中XiZi_maix-go.bin需要烧写到设备中进行运行。
 >注：最后可以执行以下命令，清除配置文件和编译生成的文件
 ```
 make BOARD=maix-go distclean
@@ -62,7 +64,7 @@ sudo pip2 install kflash
 ```
 代码根目录下执行K-Flash工具烧录，此时ls /dev/ttyUSB*会发现新增2个USB端口，烧录时选择后一个，例如此时新增的是/dev/ttyUSB0和/dev/ttyUSB1，选择/dev/ttyUSB1
 ```
-kflash -t build/XiUOS_kd233.bin -p /dev/ttyUSB1
+kflash -t build/XiZi_kd233.bin -p /dev/ttyUSB1
 ```
 ### 3.1 运行结果

@@ -1,6 +1,6 @@
 # 从零开始构建矽璓工业物联操作系统：使用ARM架构的nuvoton-m2354

-# ok1052-c
+# nuvoton-m2354

 [XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓XiUOS是一款面向智慧车间的工业物联网操作系统，主要由一个极简的微型实时操作系统内核和其上的工业物联框架构成，通过高效管理工业物联网设备、支撑工业物联应用，在生产车间内实现智能化的“感知环境、联网传输、知悉识别、控制调整”，促进以工业设备和工业控制系统为核心的人、机、物深度互联，帮助提升生产线的数字化和智能化水平。

@@ -71,12 +71,23 @@ mkdir test  &&  cd test
 git clone https://gitlink.org.cn/xuos/xiuos.git
 ```

-打开源码文件包可以看到以下目录：
+1、打开XiUOS源码文件包可以看到以下目录：
 | 名称 | 说明 |
 | -- | -- |
 | APP_Framework | 应用代码 |
 | Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 |

+2、打开XiZi内核源码文件包可以看到以下目录：
+| 名称 | 说明 |
+| -- | -- |
+| arch | 架构代码 |
+| board | 板级支持包 |
+| fs | 文件系统 |
+| kernel | 内核源码 |
+| lib | 第三方库源码 |
+| resources | 驱动文件 |
+| tool | 系统工具 |
+
 使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示：

 <div align= "center"> 
@@ -87,7 +98,7 @@ git clone https://gitlink.org.cn/xuos/xiuos.git

 裁减配置工具：

-**工具地址：** kconfig-frontends [https://forgeplus.trustie.net/projects/xuos/kconfig-frontends](https://forgeplus.trustie.net/projects/xuos/kconfig-frontends)，下载与安装的具体命令如下：
+**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)，下载与安装的具体命令如下：

 ```c
 mkdir kfrontends  && cd kfrontends
@@ -122,9 +133,9 @@ ARM： gcc-arm-none-eabi-6-2017-q1-update/bin/arm-none-eabi(`gcc 6.3.1 20170215
 1.在VScode命令终端中执行以下命令，生成配置文件

 ```c
-   cd ./Ubiquitous/XiZi
-   make BOARD=nuvoton-m2354 distclean
-   make BOARD=nuvoton-m2354 menuconfig
+cd ./Ubiquitous/XiZi
+make BOARD=nuvoton-m2354 distclean
+make BOARD=nuvoton-m2354 menuconfig
 ```

 2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置）
@@ -61,23 +61,29 @@ $ sudo apt install build-essential pkg-config  git
 $ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev
 ```

-**XiUOS操作系统源码下载：** XiUOS [https://forgeplus.trustie.net/projects/xuos/xiuos](https://forgeplus.trustie.net/projects/xuos/xiuos)
+**XiUOS操作系统源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos)

 新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下：

 ```c
 mkdir test  &&  cd test
-git clone https://git.trustie.net/xuos/xiuos.git
+git clone https://gitlink.org.cn/xuos/xiuos.git
 ```

-打开源码文件包可以看到以下目录：
+1、打开XiUOS源码文件包可以看到以下目录：
 | 名称 | 说明 |
 | -- | -- |
-| application | 应用代码 |
+| APP_Framework | 应用代码 |
+| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 |
+
+2、打开XiZi内核源码文件包可以看到以下目录：
+| 名称 | 说明 |
+| -- | -- |
+| arch | 架构代码 |
 | board | 板级支持包 |
-| framework | 应用框架 |
 | fs | 文件系统 |
 | kernel | 内核源码 |
+| lib | 第三方库源码 |
 | resources | 驱动文件 |
 | tool | 系统工具 |

@@ -91,18 +97,18 @@ git clone https://git.trustie.net/xuos/xiuos.git

 裁减配置工具：

-**工具地址：** kconfig-frontends [https://forgeplus.trustie.net/projects/xuos/kconfig-frontends](https://forgeplus.trustie.net/projects/xuos/kconfig-frontends)，下载与安装的具体命令如下：
+**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)，下载与安装的具体命令如下：

 ```c
 mkdir kfrontends  && cd kfrontends
-git  clone https://git.trustie.net/xuos/kconfig-frontends.git
+git clone https://gitlink.org.cn/xuos/kconfig-frontends.git
 ```

 下载源码后按以下步骤执行软件安装：

 ```c
 cd kconfig-frontends
- ./xs_build.sh
+./xs_build.sh
 ```

 ### 编译工具链：
@@ -126,7 +132,9 @@ $ sudo apt install gcc-arm-none-eabi
 1.在VScode命令终端中执行以下命令，生成配置文件

 ```c
-   make BOARD=ok1052-c menuconfig
+cd ./Ubiquitous/XiZi
+make BOARD=ok1052-c distclean
+make BOARD=ok1052-c menuconfig
 ```

 2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置）
@@ -143,7 +151,7 @@ $ sudo apt install gcc-arm-none-eabi
 make BOARD=ok1052-c
 ```

-4.如果编译正确无误，会产生XiUOS_ok1052-c.elf、XiUOS_ok1052-c.bin文件。
+4.如果编译正确无误，会产生XiZi_ok1052-c.elf、XiZi_ok1052-c.bin文件。

 ## 3. 烧写及运行

@@ -153,7 +161,7 @@ make BOARD=ok1052-c
 2、ok1052-c开发板支持micro usb口烧写程序，打开NXP MCU Boot Utility后，选择好芯片类型为i.MXRT105x，开发板上电，使用usb线将开发板和PC连接，拨码开关设置为1 on 2 on 3 off 4 off，按下复位键K1后，若连接成功，可见Vendor ID和Product ID均有数字显示，点击reconnect，等待NXP MCU Boot Utility中红色显示变成蓝色显示，则表示已正确识别并连接到了开发板。如下图所示：
 ![NXPBootUtility_1](./img/NXPBootUtility_1.png)

-3、选择编译生成的XiUOS_ok1052-c.elf文件路径，并选择.out(elf) from GCC ARM烧写选项，最后点击ALL-In-One Action即可烧写程序，若烧写无误，则下列绿色进度条会执行到底。如下图所示：
+3、选择编译生成的XiZi_ok1052-c.elf文件路径，并选择.out(elf) from GCC ARM烧写选项，最后点击ALL-In-One Action即可烧写程序，若烧写无误，则下列绿色进度条会执行到底。如下图所示：
 ![NXPBootUtility_2](./img/NXPBootUtility_2.png)

 ### 3.2 运行结果
@@ -7,7 +7,7 @@

 /**
 * @file board.c
- * @brief relative configure for ok1052-c
+ * @brief relative configure for ok1052-c board
 * @version 1.0
 * @author AIIT XUOS Lab
 * @date 2021.11.11
@@ -15,15 +15,15 @@

 /*************************************************
 File name: board.c
-Description: support imxrt1052-board init function
+Description: support ok1052-c board init function
 Others: take SDK_2.6.1_MIMXRT1052xxxxB for references
 History:
-1. Date: 2022-01-25
+1. Date: 2021-11-11
 Author: AIIT XUOS Lab
 Modification:
-1. support imxrt1052-board MPU、clock、memory init
-2. support imxrt1052-board uart、semc、sdio driver init
-3. support imxrt1052-board I2C, SPI, ADC, RTC driver init
+1. support ok1052-c board MPU, Clock, Memory init
+2. support ok1052-c board uart, semc, sdio driver init
+3. support ok1052-c board I2C, SPI, ADC, RTC driver init
 *************************************************/

 #include "fsl_common.h"
@@ -44,6 +44,9 @@ extern int ExtSramInit(void);
 #if defined(FS_VFS) && defined(MOUNT_SDCARD)
 #include <iot-vfs.h>

+// SD card mount flag 1: OK
+int sd_mount_flag = 0;
+
 /**
 * @description: Mount SD card
 * @return 0
@@ -51,10 +54,13 @@ extern int ExtSramInit(void);
 int MountSDCard(void)
 {
    if (MountFilesystem(SDIO_BUS_NAME, SDIO_DEVICE_NAME, SDIO_DRIVER_NAME, FSTYPE_FATFS, "/") == 0)
+    {
+        sd_mount_flag = 1;
        KPrintf("sd card mount to '/'");
+    }
    else
        KPrintf("sd card mount to '/' failed!");
-    
+
    return 0;
 }
 #endif
@@ -69,12 +75,10 @@ int MountSDCard(void)
 #ifdef BSP_USING_LWIP
 #include <connect_ethernet.h>
 #endif
+
 #ifdef BSP_USING_LPUART
 #include <connect_uart.h>
-<<<<<<< HEAD
 #endif
-=======
->>>>>>> e5d124231c72798f7f77b842cc8c631b79043914

 #ifdef BSP_USING_ADC
 #include <connect_adc.h>
@@ -7,7 +7,7 @@

 /**
 * @file board.h
-* @brief define imxrt1052-board init configure and start-up function
+* @brief define ok1052-c init configure and start-up function
 * @version 1.0
 * @author AIIT XUOS Lab
 * @date 2021-05-28
@@ -15,7 +15,7 @@

 /*************************************************
 File name: board.h
-Description: define imxrt1052-board board init function and struct
+Description: define ok1052-c board init function and struct
 Others:
 History:
 1. Date: 2021-05-28
@@ -7,8 +7,8 @@

 /**
 * @file clock_config.h
-* @brief define imxrt1052-board clock configure
-* @version 1.0 
+* @brief define ok1052-c board clock configure
+* @version 1.0
 * @author AIIT XUOS Lab
 * @date 2021-05-29
 */
@@ -7,7 +7,7 @@

 /**
 * @file pin_mux.h
-* @brief define imxrt1052-board pin configure
+* @brief define ok1052-c board pin configure
 * @version 1.0
 * @author AIIT XUOS Lab
 * @date 2021-05-29
@@ -28,7 +28,7 @@

 /**
 * @file link.lds
-* @brief ok1052-c Linker script
+* @brief ok1052-c board Linker script
 * @version 1.0
 * @author AIIT XUOS Lab
 * @date 2021-05-28
@@ -36,7 +36,7 @@

 /*************************************************
 File name: link.lds
-Description: ok1052-c Linker script
+Description: ok1052-c board Linker script
 Others: take MIMXRT1052xxxxx_flexspi_nor.ld for references
 History:
 1. Date: 2021-05-28
@@ -28,7 +28,7 @@

 /**
 * @file link.lds
-* @brief ok1052-c Linker script
+* @brief ok1052-c board Linker script
 * @version 1.0
 * @author AIIT XUOS Lab
 * @date 2021-05-28
@@ -36,7 +36,7 @@

 /*************************************************
 File name: link.lds
-Description: ok1052-c Linker script
+Description: ok1052-c board Linker script
 Others: take MIMXRT1052xxxxx_flexspi_nor.ld for references
 History:
 1. Date: 2021-05-28
@@ -28,7 +28,6 @@ ifeq ($(CONFIG_BSP_USING_RTC),y)
  SRC_DIR += rtc
 endif

-
 ifeq ($(CONFIG_BSP_USING_SDIO),y)
  SRC_DIR += sdio
 endif
@@ -7,8 +7,8 @@

 /**
 * @file clock_config.c
-* @brief support imxrt1052-board clock configure
-* @version 1.0 
+* @brief support ok1052-c board clock configure
+* @version 1.0
 * @author AIIT XUOS Lab
 * @date 2021-05-29
 */
@@ -7,7 +7,7 @@

 /**
 * @file pin_mux.c
-* @brief support imxrt1052-board pin configure
+* @brief support ok1052-c board pin configure
 * @version 1.0
 * @author AIIT XUOS Lab
 * @date 2021-05-29
@@ -271,7 +271,7 @@ void SemcPinmuxConfig(void)
  IOMUXC_SetPinMux(
      IOMUXC_GPIO_EMC_41_SEMC_CSX00,          /* GPIO_EMC_41 is configured as SEMC_CSX00 */
      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-  
+
  IOMUXC_SetPinConfig(
      IOMUXC_GPIO_EMC_00_SEMC_DATA00,         /* GPIO_EMC_00 PAD functional properties : */
      0x0110F9u);                             /* Slew Rate Field: Fast Slew Rate
@@ -1,43 +1,28 @@
 /*
- * Copyright (c) 2020 RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author        Notes
- * 2012-04-25     weety         first version
- */
+* Copyright (c) 2022 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/

 /**
 * @file connect_i2c.c
-* @brief support ok1052-c i2c function and register to bus framework
+* @brief support ok1052-c board i2c function and register to bus framework
 * @version 1.0
 * @author AIIT XUOS Lab
 * @date 2022-03-01
 */

-/*************************************************
-File name: connect_i2c.c
-Description: support ok1052-c i2c configure and i2c bus register function
-Others: take RT-Thread v4.0.2/components/drivers/i2c/i2c-bit-ops.c for references
-                https://github.com/RT-Thread/rt-thread/tree/v4.0.2
-History:
-1. Date: 2022-03-01
-Author: AIIT XUOS Lab
-Modification:
-1. support ok1052-c i2c bit configure, write and read
-2. support ok1052-c i2c bus device and driver register
-*************************************************/
-
 #include <board.h>
 #include "bus_serial.h"
 #include "connect_i2c.h"
 #include "fsl_lpi2c.h"

-#ifndef BSP_USING_I2C1
-#define BSP_USING_I2C1
-#endif
-
 static uint32 I2cWriteData(struct I2cHardwareDevice *i2c_dev, struct I2cDataStandard *msg)
 {
    status_t ret;
@@ -174,7 +159,7 @@ int Stm32HwI2cInit(void)
    static struct I2cDriver i2c_driver;
    memset(&i2c_driver, 0, sizeof(struct I2cDriver));

-#ifdef  BSP_USING_I2C1
+#ifdef BSP_USING_I2C
    i2c_driver.configure = I2cDrvConfigure;

    ret = BoardI2cBusInit(&i2c_bus, &i2c_driver);
@@ -1,40 +1,18 @@
 /*
- * The Clear BSD License
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted (subject to the limitations in the disclaimer below) provided
- *  that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
+* Copyright (c) 2022 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/

 /**
 * @file connect_i2c_eeprom.h
-* @brief ok1052-c eeprom relative codes
+* @brief ok1052-c board eeprom relative codes
 * @version 1.0
 * @author AIIT XUOS Lab
 * @date 2022-03-01
@@ -34,7 +34,7 @@

 /**
 * @file hardware_i2c.c
-* @brief ok1052-c i2c relative codes
+* @brief ok1052-c i2c board relative codes
 * @version 1.0
 * @author AIIT XUOS Lab
 * @date 2022-03-01
@@ -1,5 +1,5 @@
 /*
-* Copyright (c) 2020 AIIT XUOS Lab
+* Copyright (c) 2021 AIIT XUOS Lab
 * XiUOS is licensed under Mulan PSL v2.
 * You can use this software according to the terms and conditions of the Mulan PSL v2.
 * You may obtain a copy of Mulan PSL v2 at:
@@ -12,8 +12,8 @@

 /**
 * @file connect_adc.h
-* @brief define stm32f407-st-discovery adc function and struct
-* @version 1.1
+* @brief define ok1052-c board adc function and struct
+* @version 1.0
 * @author AIIT XUOS Lab
 * @date 2021-12-28
 */
@@ -12,7 +12,7 @@

 /**
 * @file connect_gpio.h
-* @brief define ok1052-c gpio function and struct
+* @brief define ok1052-c board gpio function and struct
 * @version 1.0
 * @author AIIT XUOS Lab
 * @date 2022-03-01
@@ -1,5 +1,5 @@
 /*
-* Copyright (c) 2020 AIIT XUOS Lab
+* Copyright (c) 2021 AIIT XUOS Lab
 * XiUOS is licensed under Mulan PSL v2.
 * You can use this software according to the terms and conditions of the Mulan PSL v2.
 * You may obtain a copy of Mulan PSL v2 at:
@@ -12,7 +12,7 @@

 /**
 * @file connect_i2c.h
-* @brief define stm32f407-st-discovery-board i2c function and struct
+* @brief define ok1052-c board i2c function and struct
 * @version 1.0
 * @author AIIT XUOS Lab
 * @date 2021-04-25
@@ -12,7 +12,7 @@

 /**
 * @file connect_rtc.h
-* @brief define ok1052-c rtc function and structure
+* @brief define ok1052-c board rtc function and struct
 * @version 1.0
 * @author AIIT XUOS Lab
 * @date 2022-03-01
@@ -9,15 +9,15 @@
 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
 * See the Mulan PSL v2 for more details.
 */
- 
+
 /**
 * @file connect_sdio.h
-* @brief define OK1052-board sdio function and struct
-* @version 2.0 
+* @brief define ok1052-c board sdio function and struct
+* @version 2.0
 * @author AIIT XUOS Lab
 * @date 2022-01-24
 */
- 
+
 #ifndef CONNECT_SDIO_H
 #define CONNECT_SDIO_H

@@ -1,5 +1,5 @@
 /*
-* Copyright (c) 2020 AIIT XUOS Lab
+* Copyright (c) 2021 AIIT XUOS Lab
 * XiUOS is licensed under Mulan PSL v2.
 * You can use this software according to the terms and conditions of the Mulan PSL v2.
 * You may obtain a copy of Mulan PSL v2 at:
@@ -12,7 +12,7 @@

 /**
 * @file connect_spi.h
-* @brief define stm32f407-st-discovery-board spi function and struct
+* @brief define ok1052-c board spi function and struct
 * @version 1.0
 * @author AIIT XUOS Lab
 * @date 2021-04-25
@@ -1,5 +1,5 @@
 /*
-* Copyright (c) 2020 AIIT XUOS Lab
+* Copyright (c) 2021 AIIT XUOS Lab
 * XiUOS is licensed under Mulan PSL v2.
 * You can use this software according to the terms and conditions of the Mulan PSL v2.
 * You may obtain a copy of Mulan PSL v2 at:
@@ -9,11 +9,11 @@
 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
 * See the Mulan PSL v2 for more details.
 */
- 
+
 /**
 * @file connect_uart.h
-* @brief define imxrt1052-board usart function and struct
-* @version 1.0 
+* @brief define ok1052-c board usart function and struct
+* @version 1.0
 * @author AIIT XUOS Lab
 * @date 2021-05-28
 */
@@ -27,10 +27,8 @@
 extern "C" {
 #endif

-
-
-#define KERNEL_CONSOLE_BUS_NAME       SERIAL_BUS_NAME_1
-#define KERNEL_CONSOLE_DRV_NAME        SERIAL_DRV_NAME_1
+#define KERNEL_CONSOLE_BUS_NAME    SERIAL_BUS_NAME_1
+#define KERNEL_CONSOLE_DRV_NAME    SERIAL_DRV_NAME_1
 #define KERNEL_CONSOLE_DEVICE_NAME SERIAL_1_DEVICE_NAME_0

 int Imrt1052HwUartInit(void);
@@ -1,5 +1,5 @@
 /*
-* Copyright (c) 2020 AIIT XUOS Lab
+* Copyright (c) 2022 AIIT XUOS Lab
 * XiUOS is licensed under Mulan PSL v2.
 * You can use this software according to the terms and conditions of the Mulan PSL v2.
 * You may obtain a copy of Mulan PSL v2 at:
@@ -9,11 +9,11 @@
 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
 * See the Mulan PSL v2 for more details.
 */
- 
+
 /**
 * @file connect_usb.h
-* @brief define ok1052-board usb function and struct
-* @version 2.0 
+* @brief define ok1052-c board usb function and struct
+* @version 2.0
 * @author AIIT XUOS Lab
 * @date 2022-02-09
 */
@@ -8,7 +8,7 @@

 /**
 * @file fsl_lpi2c.h
-* @brief support ok1052-c i2c driver
+* @brief support ok1052-c board i2c driver
 * @version 1.0
 * @author AIIT XUOS Lab
 * @date 2022-03-01
@@ -16,7 +16,7 @@

 /*************************************************
 File name: fsl_lpi2c.h
-Description: support ok1052-c i2c driver
+Description: support ok1052-c board i2c driver

 History:
 1. Date: 2022-03-01
@@ -1,548 +0,0 @@
-/*
- * Copyright 2018 NXP
- * All rights reserved.
- *
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __SERIAL_MANAGER_H__
-#define __SERIAL_MANAGER_H__
-
-/*!
- * @addtogroup serialmanager
- * @{
- */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
-/*! @brief Enable or disable serial manager non-blocking mode (1 - enable, 0 - disable) */
-#define SERIAL_MANAGER_NON_BLOCKING_MODE (1U)
-#else
-#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE
-#define SERIAL_MANAGER_NON_BLOCKING_MODE (0U)
-#endif
-#endif
-
-/*! @brief Enable or disable uart port (1 - enable, 0 - disable) */
-#ifndef SERIAL_PORT_TYPE_UART
-#define SERIAL_PORT_TYPE_UART (1U)
-#endif
-
-/*! @brief Enable or disable USB CDC port (1 - enable, 0 - disable) */
-#ifndef SERIAL_PORT_TYPE_USBCDC
-#define SERIAL_PORT_TYPE_USBCDC (0U)
-#endif
-
-/*! @brief Enable or disable SWO port (1 - enable, 0 - disable) */
-#ifndef SERIAL_PORT_TYPE_SWO
-#define SERIAL_PORT_TYPE_SWO (0U)
-#endif
-
-/*! @brief Enable or disable USB CDC virtual port (1 - enable, 0 - disable) */
-#ifndef SERIAL_PORT_TYPE_USBCDC_VIRTUAL
-#define SERIAL_PORT_TYPE_USBCDC_VIRTUAL (0U)
-#endif
-
-/*! @brief Set serial manager write handle size */
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (44U)
-#define SERIAL_MANAGER_READ_HANDLE_SIZE (44U)
-#else
-#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (4U)
-#define SERIAL_MANAGER_READ_HANDLE_SIZE (4U)
-#endif
-
-#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
-#include "serial_port_uart.h"
-#endif
-
-#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
-
-#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-#error The serial manager blocking mode cannot be supported for USB CDC.
-#endif
-
-#include "serial_port_usb.h"
-#endif
-
-#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
-#include "serial_port_swo.h"
-#endif
-
-#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
-
-#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-#error The serial manager blocking mode cannot be supported for USB CDC.
-#endif
-
-#include "serial_port_usb_virtual.h"
-#endif
-
-#define SERIAL_MANAGER_HANDLE_SIZE_TEMP 0U
-#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
-
-#if (SERIAL_PORT_UART_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
-#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
-#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_UART_HANDLE_SIZE
-#endif
-
-#endif
-
-#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
-
-#if (SERIAL_PORT_USB_CDC_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
-#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
-#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_CDC_HANDLE_SIZE
-#endif
-
-#endif
-
-#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
-
-#if (SERIAL_PORT_SWO_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
-#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
-#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SWO_HANDLE_SIZE
-#endif
-
-#endif
-
-#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
-
-#if (SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
-#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
-#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE
-#endif
-
-#endif
-
-/*! @brief SERIAL_PORT_UART_HANDLE_SIZE/SERIAL_PORT_USB_CDC_HANDLE_SIZE + serial manager dedicated size */
-#if ((defined(SERIAL_MANAGER_HANDLE_SIZE_TEMP) && (SERIAL_MANAGER_HANDLE_SIZE_TEMP > 0U)))
-#else
-#error SERIAL_PORT_TYPE_UART, SERIAL_PORT_TYPE_USBCDC, SERIAL_PORT_TYPE_SWO and SERIAL_PORT_TYPE_USBCDC_VIRTUAL should not be cleared at same time.
-#endif
-
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 120U)
-#else
-#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 12U)
-#endif
-
-#define SERIAL_MANAGER_USE_COMMON_TASK (1U)
-#define SERIAL_MANAGER_TASK_PRIORITY (2U)
-#define SERIAL_MANAGER_TASK_STACK_SIZE (1000U)
-
-typedef void *serial_handle_t;
-typedef void *serial_write_handle_t;
-typedef void *serial_read_handle_t;
-
-/*! @brief serial port type*/
-typedef enum _serial_port_type
-{
-    kSerialPort_Uart = 1U,     /*!< Serial port UART */
-    kSerialPort_UsbCdc,        /*!< Serial port USB CDC */
-    kSerialPort_Swo,           /*!< Serial port SWO */
-    kSerialPort_UsbCdcVirtual, /*!< Serial port USB CDC Virtual */
-} serial_port_type_t;
-
-/*! @brief serial manager config structure*/
-typedef struct _serial_manager_config
-{
-    uint8_t *ringBuffer;     /*!< Ring buffer address, it is used to buffer data received by the hardware.
-                                  Besides, the memory space cannot be free during the lifetime of the serial
-                                  manager module. */
-    uint32_t ringBufferSize; /*!< The size of the ring buffer */
-    serial_port_type_t type; /*!< Serial port type */
-    void *portConfig;        /*!< Serial port configuration */
-} serial_manager_config_t;
-
-/*! @brief serial manager error code*/
-typedef enum _serial_manager_status
-{
-    kStatus_SerialManager_Success = kStatus_Success,                            /*!< Success */
-    kStatus_SerialManager_Error   = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 1), /*!< Failed */
-    kStatus_SerialManager_Busy    = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 2), /*!< Busy */
-    kStatus_SerialManager_Notify  = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 3), /*!< Ring buffer is not empty */
-    kStatus_SerialManager_Canceled =
-        MAKE_STATUS(kStatusGroup_SERIALMANAGER, 4), /*!< the non-blocking request is canceled */
-    kStatus_SerialManager_HandleConflict = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 5), /*!< The handle is opened */
-    kStatus_SerialManager_RingBufferOverflow =
-        MAKE_STATUS(kStatusGroup_SERIALMANAGER, 6), /*!< The ring buffer is overflowed */
-} serial_manager_status_t;
-
-/*! @brief Callback message structure */
-typedef struct _serial_manager_callback_message
-{
-    uint8_t *buffer; /*!< Transferred buffer */
-    uint32_t length; /*!< Transferred data length */
-} serial_manager_callback_message_t;
-
-/*! @brief callback function */
-typedef void (*serial_manager_callback_t)(void *callbackParam,
-                                          serial_manager_callback_message_t *message,
-                                          serial_manager_status_t status);
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* _cplusplus */
-
-/*!
- * @brief Initializes a serial manager module with the serial manager handle and the user configuration structure.
- *
- * This function configures the Serial Manager module with user-defined settings. The user can configure the
- * configuration
- * structure. The parameter serialHandle is a pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE
- * allocated by the caller.
- * The Serial Manager module supports two types of serial port, UART (includes UART, USART, LPSCI, LPUART, etc) and USB
- * CDC.
- * Please refer to #serial_port_type_t for serial port setting. These two types can be set by using
- * #serial_manager_config_t.
- *
- * Example below shows how to use this API to configure the Serial Manager.
- * For UART,
- *  @code
- *   #define SERIAL_MANAGER_RING_BUFFER_SIZE          (256U)
- *   static uint8_t s_serialHandleBuffer[SERIAL_MANAGER_HANDLE_SIZE];
- *   static serial_handle_t s_serialHandle = &s_serialHandleBuffer[0];
- *   static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];
- *
- *   serial_manager_config_t config;
- *   serial_port_uart_config_t uartConfig;
- *   config.type = kSerialPort_Uart;
- *   config.ringBuffer = &s_ringBuffer[0];
- *   config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;
- *   uartConfig.instance = 0;
- *   uartConfig.clockRate = 24000000;
- *   uartConfig.baudRate = 115200;
- *   uartConfig.parityMode = kSerialManager_UartParityDisabled;
- *   uartConfig.stopBitCount = kSerialManager_UartOneStopBit;
- *   uartConfig.enableRx = 1;
- *   uartConfig.enableTx = 1;
- *   config.portConfig = &uartConfig;
- *   SerialManager_Init(s_serialHandle, &config);
- *  @endcode
- * For USB CDC,
- *  @code
- *   #define SERIAL_MANAGER_RING_BUFFER_SIZE          (256U)
- *   static uint8_t s_serialHandleBuffer[SERIAL_MANAGER_HANDLE_SIZE];
- *   static serial_handle_t s_serialHandle = &s_serialHandleBuffer[0];
- *   static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];
- *
- *   serial_manager_config_t config;
- *   serial_port_usb_cdc_config_t usbCdcConfig;
- *   config.type = kSerialPort_UsbCdc;
- *   config.ringBuffer = &s_ringBuffer[0];
- *   config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;
- *   usbCdcConfig.controllerIndex = kSerialManager_UsbControllerKhci0;
- *   config.portConfig = &usbCdcConfig;
- *   SerialManager_Init(s_serialHandle, &config);
- *  @endcode
- *
- * @param serialHandle Pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE allocated by the caller.
- * @param config Pointer to user-defined configuration structure.
- * @retval kStatus_SerialManager_Error An error occurred.
- * @retval kStatus_SerialManager_Success The Serial Manager module initialization succeed.
- */
-serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, serial_manager_config_t *config);
-
-/*!
- * @brief De-initializes the serial manager module instance.
- *
- * This function de-initializes the serial manager module instance. If the opened writing or
- * reading handle is not closed, the function will return kStatus_SerialManager_Busy.
- *
- * @param serialHandle The serial manager module handle pointer.
- * @retval kStatus_SerialManager_Success The serial manager de-initialization succeed.
- * @retval kStatus_SerialManager_Busy Opened reading or writing handle is not closed.
- */
-serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle);
-
-/*!
- * @brief Opens a writing handle for the serial manager module.
- *
- * This function Opens a writing handle for the serial manager module. If the serial manager needs to
- * be used in different tasks, the task should open a dedicated write handle for itself by calling
- * #SerialManager_OpenWriteHandle. Since there can only one buffer for transmission for the writing
- * handle at the same time, multiple writing handles need to be opened when the multiple transmission
- * is needed for a task.
- *
- * @param serialHandle The serial manager module handle pointer.
- * @param writeHandle The serial manager module writing handle pointer.
- * @retval kStatus_SerialManager_Error An error occurred.
- * @retval kStatus_SerialManager_HandleConflict The writing handle was opened.
- * @retval kStatus_SerialManager_Success The writing handle is opened.
- *
- * Example below shows how to use this API to write data.
- * For task 1,
- *  @code
- *   static uint8_t s_serialWriteHandleBuffer1[SERIAL_MANAGER_WRITE_HANDLE_SIZE];
- *   static serial_write_handle_t s_serialWriteHandle1 = &s_serialWriteHandleBuffer1[0];
- *   static uint8_t s_nonBlockingWelcome1[] = "This is non-blocking writing log for task1!\r\n";
- *   SerialManager_OpenWriteHandle(serialHandle, s_serialWriteHandle1);
- *   SerialManager_InstallTxCallback(s_serialWriteHandle1, Task1_SerialManagerTxCallback, s_serialWriteHandle1);
- *   SerialManager_WriteNonBlocking(s_serialWriteHandle1, s_nonBlockingWelcome1, sizeof(s_nonBlockingWelcome1) - 1);
- *  @endcode
- * For task 2,
- *  @code
- *   static uint8_t s_serialWriteHandleBuffer2[SERIAL_MANAGER_WRITE_HANDLE_SIZE];
- *   static serial_write_handle_t s_serialWriteHandle2 = &s_serialWriteHandleBuffer2[0];
- *   static uint8_t s_nonBlockingWelcome2[] = "This is non-blocking writing log for task2!\r\n";
- *   SerialManager_OpenWriteHandle(serialHandle, s_serialWriteHandle2);
- *   SerialManager_InstallTxCallback(s_serialWriteHandle2, Task2_SerialManagerTxCallback, s_serialWriteHandle2);
- *   SerialManager_WriteNonBlocking(s_serialWriteHandle2, s_nonBlockingWelcome2, sizeof(s_nonBlockingWelcome2) - 1);
- *  @endcode
- */
-serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle);
-
-/*!
- * @brief Closes a writing handle for the serial manager module.
- *
- * This function Closes a writing handle for the serial manager module.
- *
- * @param writeHandle The serial manager module writing handle pointer.
- * @retval kStatus_SerialManager_Success The writing handle is closed.
- */
-serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle);
-
-/*!
- * @brief Opens a reading handle for the serial manager module.
- *
- * This function Opens a reading handle for the serial manager module. The reading handle can not be
- * opened multiple at the same time. The error code kStatus_SerialManager_Busy would be returned when
- * the previous reading handle is not closed. And There can only be one buffer for receiving for the
- * reading handle at the same time.
- *
- * @param serialHandle The serial manager module handle pointer.
- * @param readHandle The serial manager module reading handle pointer.
- * @retval kStatus_SerialManager_Error An error occurred.
- * @retval kStatus_SerialManager_Success The reading handle is opened.
- * @retval kStatus_SerialManager_Busy Previous reading handle is not closed.
- *
- * Example below shows how to use this API to read data.
- *  @code
- *   static uint8_t s_serialReadHandleBuffer[SERIAL_MANAGER_READ_HANDLE_SIZE];
- *   static serial_read_handle_t s_serialReadHandle = &s_serialReadHandleBuffer[0];
- *   SerialManager_OpenReadHandle(serialHandle, s_serialReadHandle);
- *   static uint8_t s_nonBlockingBuffer[64];
- *   SerialManager_InstallRxCallback(s_serialReadHandle, APP_SerialManagerRxCallback, s_serialReadHandle);
- *   SerialManager_ReadNonBlocking(s_serialReadHandle, s_nonBlockingBuffer, sizeof(s_nonBlockingBuffer));
- *  @endcode
- */
-serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle);
-
-/*!
- * @brief Closes a reading for the serial manager module.
- *
- * This function Closes a reading for the serial manager module.
- *
- * @param readHandle The serial manager module reading handle pointer.
- * @retval kStatus_SerialManager_Success The reading handle is closed.
- */
-serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle);
-
-/*!
- * @brief Transmits data with the blocking mode.
- *
- * This is a blocking function, which polls the sending queue, waits for the sending queue to be empty.
- * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled.
- * And There can only one buffer for transmission for the writing handle at the same time.
- *
- * @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking
- * cannot be used at the same time.
- * And, the function #SerialManager_CancelWriting cannot be used to abort the transmission of this function.
- *
- * @param writeHandle The serial manager module handle pointer.
- * @param buffer Start address of the data to write.
- * @param length Length of the data to write.
- * @retval kStatus_SerialManager_Success Successfully sent all data.
- * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet.
- * @retval kStatus_SerialManager_Error An error occurred.
- */
-serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle,
-                                                    uint8_t *buffer,
-                                                    uint32_t length);
-
-/*!
- * @brief Reads data with the blocking mode.
- *
- * This is a blocking function, which polls the receiving buffer, waits for the receiving buffer to be full.
- * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled.
- * And There can only one buffer for receiving for the reading handle at the same time.
- *
- * @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking
- * cannot be used at the same time.
- * And, the function #SerialManager_CancelReading cannot be used to abort the transmission of this function.
- *
- * @param readHandle The serial manager module handle pointer.
- * @param buffer Start address of the data to store the received data.
- * @param length The length of the data to be received.
- * @retval kStatus_SerialManager_Success Successfully received all data.
- * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
- * @retval kStatus_SerialManager_Error An error occurred.
- */
-serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length);
-
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-/*!
- * @brief Transmits data with the non-blocking mode.
- *
- * This is a non-blocking function, which returns directly without waiting for all data to be sent.
- * When all data is sent, the module notifies the upper layer through a TX callback function and passes
- * the status parameter @ref kStatus_SerialManager_Success.
- * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled.
- * And There can only one buffer for transmission for the writing handle at the same time.
- *
- * @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking
- * cannot be used at the same time. And, the TX callback is mandatory before the function could be used.
- *
- * @param writeHandle The serial manager module handle pointer.
- * @param buffer Start address of the data to write.
- * @param length Length of the data to write.
- * @retval kStatus_SerialManager_Success Successfully sent all data.
- * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet.
- * @retval kStatus_SerialManager_Error An error occurred.
- */
-serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle,
-                                                       uint8_t *buffer,
-                                                       uint32_t length);
-
-/*!
- * @brief Reads data with the non-blocking mode.
- *
- * This is a non-blocking function, which returns directly without waiting for all data to be received.
- * When all data is received, the module driver notifies the upper layer
- * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Success.
- * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled.
- * And There can only one buffer for receiving for the reading handle at the same time.
- *
- * @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking
- * cannot be used at the same time. And, the RX callback is mandatory before the function could be used.
- *
- * @param readHandle The serial manager module handle pointer.
- * @param buffer Start address of the data to store the received data.
- * @param length The length of the data to be received.
- * @retval kStatus_SerialManager_Success Successfully received all data.
- * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
- * @retval kStatus_SerialManager_Error An error occurred.
- */
-serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle,
-                                                      uint8_t *buffer,
-                                                      uint32_t length);
-
-/*!
- * @brief Tries to read data.
- *
- * The function tries to read data from internal ring buffer. If the ring buffer is not empty, the data will be
- * copied from ring buffer to up layer buffer. The copied length is the minimum of the ring buffer and up layer length.
- * After the data is copied, the actual data length is passed by the parameter length.
- * And There can only one buffer for receiving for the reading handle at the same time.
- *
- * @param readHandle The serial manager module handle pointer.
- * @param buffer Start address of the data to store the received data.
- * @param length The length of the data to be received.
- * @param receivedLength Length received from the ring buffer directly.
- * @retval kStatus_SerialManager_Success Successfully received all data.
- * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
- * @retval kStatus_SerialManager_Error An error occurred.
- */
-serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle,
-                                              uint8_t *buffer,
-                                              uint32_t length,
-                                              uint32_t *receivedLength);
-
-/*!
- * @brief Cancels unfinished send transmission.
- *
- * The function cancels unfinished send transmission. When the transfer is canceled, the module notifies the upper layer
- * through a TX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled.
- *
- * @note The function #SerialManager_CancelWriting cannot be used to abort the transmission of
- * the function #SerialManager_WriteBlocking.
- *
- * @param writeHandle The serial manager module handle pointer.
- * @retval kStatus_SerialManager_Success Get successfully abort the sending.
- * @retval kStatus_SerialManager_Error An error occurred.
- */
-serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle);
-
-/*!
- * @brief Cancels unfinished receive transmission.
- *
- * The function cancels unfinished receive transmission. When the transfer is canceled, the module notifies the upper
- * layer
- * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled.
- *
- * @note The function #SerialManager_CancelReading cannot be used to abort the transmission of
- * the function #SerialManager_ReadBlocking.
- *
- * @param readHandle The serial manager module handle pointer.
- * @retval kStatus_SerialManager_Success Get successfully abort the receiving.
- * @retval kStatus_SerialManager_Error An error occurred.
- */
-serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle);
-
-/*!
- * @brief Installs a TX callback and callback parameter.
- *
- * This function is used to install the TX callback and callback parameter for the serial manager module.
- * When any status of TX transmission changed, the driver will notify the upper layer by the installed callback
- * function. And the status is also passed as status parameter when the callback is called.
- *
- * @param writeHandle The serial manager module handle pointer.
- * @param callback The callback function.
- * @param callbackParam The parameter of the callback function.
- * @retval kStatus_SerialManager_Success Successfully install the callback.
- */
-serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle,
-                                                        serial_manager_callback_t callback,
-                                                        void *callbackParam);
-
-/*!
- * @brief Installs a RX callback and callback parameter.
- *
- * This function is used to install the RX callback and callback parameter for the serial manager module.
- * When any status of RX transmission changed, the driver will notify the upper layer by the installed callback
- * function. And the status is also passed as status parameter when the callback is called.
- *
- * @param readHandle The serial manager module handle pointer.
- * @param callback The callback function.
- * @param callbackParam The parameter of the callback function.
- * @retval kStatus_SerialManager_Success Successfully install the callback.
- */
-serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle,
-                                                        serial_manager_callback_t callback,
-                                                        void *callbackParam);
-
-#endif
-
-/*!
- * @brief Prepares to enter low power consumption.
- *
- * This function is used to prepare to enter low power consumption.
- *
- * @param serialHandle The serial manager module handle pointer.
- * @retval kStatus_SerialManager_Success Successful operation.
- */
-serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle);
-
-/*!
- * @brief Restores from low power consumption.
- *
- * This function is used to restore from low power consumption.
- *
- * @param serialHandle The serial manager module handle pointer.
- * @retval kStatus_SerialManager_Success Successful operation.
- */
-serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle);
-
-#if defined(__cplusplus)
-}
-#endif
-/*! @} */
-#endif /* __SERIAL_MANAGER_H__ */
@@ -1,55 +0,0 @@
-/*
- * Copyright 2018 NXP
- * All rights reserved.
- *
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __SERIAL_PORT_UART_H__
-#define __SERIAL_PORT_UART_H__
-
-/*!
- * @addtogroup serial_port_uart
- * @{
- */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-/*! @brief serial port uart handle size*/
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-#define SERIAL_PORT_UART_HANDLE_SIZE (166U)
-#else
-#define SERIAL_PORT_UART_HANDLE_SIZE (4U)
-#endif
-
-/*! @brief serial port uart parity mode*/
-typedef enum _serial_port_uart_parity_mode
-{
-    kSerialManager_UartParityDisabled = 0x0U, /*!< Parity disabled */
-    kSerialManager_UartParityEven     = 0x1U, /*!< Parity even enabled */
-    kSerialManager_UartParityOdd      = 0x2U, /*!< Parity odd enabled */
-} serial_port_uart_parity_mode_t;
-
-/*! @brief serial port uart stop bit count*/
-typedef enum _serial_port_uart_stop_bit_count
-{
-    kSerialManager_UartOneStopBit = 0U, /*!< One stop bit */
-    kSerialManager_UartTwoStopBit = 1U, /*!< Two stop bits */
-} serial_port_uart_stop_bit_count_t;
-
-/*! @brief serial port uart config struct*/
-typedef struct _serial_port_uart_config
-{
-    uint32_t clockRate;                             /*!< clock rate  */
-    uint32_t baudRate;                              /*!< baud rate  */
-    serial_port_uart_parity_mode_t parityMode;      /*!< Parity mode, disabled (default), even, odd */
-    serial_port_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits  */
-    uint8_t instance;                               /*!< Instance (0 - UART0, 1 - UART1, ...), detail information
-                                                         please refer to the SOC corresponding RM. */
-    uint8_t enableRx;                               /*!< Enable RX */
-    uint8_t enableTx;                               /*!< Enable TX */
-} serial_port_uart_config_t;
-/*! @} */
-#endif /* __SERIAL_PORT_UART_H__ */
@@ -1,76 +0,0 @@
-/*
- * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
- * Copyright 2016 - 2018 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __SERIAL_PORT_USB_H__
-#define __SERIAL_PORT_USB_H__
-
-#if defined(FSL_RTOS_FREE_RTOS)
-#include "FreeRTOS.h"
-#endif
-
-/*!
- * @addtogroup serial_port_usb
- * @{
- */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-/*! @brief serial port usb handle size*/
-#define SERIAL_PORT_USB_CDC_HANDLE_SIZE (72)
-
-/*! @brief USB interrupt priority*/
-#if defined(__GIC_PRIO_BITS)
-#define USB_DEVICE_INTERRUPT_PRIORITY (25U)
-#else
-#if defined(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
-#define USB_DEVICE_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
-#else
-/* The default value 3 is used to support different ARM Core, such as CM0P, CM4, CM7, and CM33, etc.
- * The minimum number of priority bits implemented in the NVIC is 2 on these SOCs. The value of mininum
- * priority is 3 (2^2 - 1). So, the default value is 3.
- */
-#define USB_DEVICE_INTERRUPT_PRIORITY (3U)
-#endif
-#endif
-
-/*! @brief USB controller ID */
-typedef enum _serial_port_usb_cdc_controller_index
-{
-    kSerialManager_UsbControllerKhci0 = 0U, /*!< KHCI 0U */
-    kSerialManager_UsbControllerKhci1 = 1U, /*!< KHCI 1U, Currently, there are no platforms which have two KHCI IPs,
-                                  this is reserved to be used in the future. */
-    kSerialManager_UsbControllerEhci0 = 2U, /*!< EHCI 0U */
-    kSerialManager_UsbControllerEhci1 = 3U, /*!< EHCI 1U, Currently, there are no platforms which have two EHCI IPs,
-                                  this is reserved to be used in the future. */
-
-    kSerialManager_UsbControllerLpcIp3511Fs0 = 4U, /*!< LPC USB IP3511 FS controller 0 */
-    kSerialManager_UsbControllerLpcIp3511Fs1 = 5U, /*!< LPC USB IP3511 FS controller 1, there are no platforms which
-                                                     have two IP3511 IPs, this is reserved to be used in the future. */
-
-    kSerialManager_UsbControllerLpcIp3511Hs0 = 6U, /*!< LPC USB IP3511 HS controller 0 */
-    kSerialManager_UsbControllerLpcIp3511Hs1 = 7U, /*!< LPC USB IP3511 HS controller 1, there are no platforms which
-                                                     have two IP3511 IPs, this is reserved to be used in the future. */
-
-    kSerialManager_UsbControllerOhci0 = 8U, /*!< OHCI 0U */
-    kSerialManager_UsbControllerOhci1 = 9U, /*!< OHCI 1U, Currently, there are no platforms which have two OHCI IPs,
-                                  this is reserved to be used in the future. */
-
-    kSerialManager_UsbControllerIp3516Hs0 = 10U, /*!< IP3516HS 0U */
-    kSerialManager_UsbControllerIp3516Hs1 = 11U, /*!< IP3516HS 1U, Currently, there are no platforms which have two
-                                               IP3516HS IPs, this is reserved to be used in the future. */
-} serial_port_usb_cdc_controller_index_t;
-
-/*! @brief serial port usb config struct*/
-typedef struct _serial_port_usb_cdc_config
-{
-    serial_port_usb_cdc_controller_index_t controllerIndex; /*!< controller index */
-} serial_port_usb_cdc_config_t;
-
-/*! @} */
-#endif /* __SERIAL_PORT_USB_H__ */
@@ -34,7 +34,7 @@

 /**
 * @file connect_rtc.c
-* @brief ok1052-c rtc function and structure
+* @brief ok1052-c board rtc function and structure
 * @version 1.0
 * @author AIIT XUOS Lab
 * @date 2022-03-01
@@ -42,13 +42,14 @@

 /*************************************************
 File name: connect_rtc.c
-Description: support ok1052-c rtc configure and spi bus register function
+Description: support ok1052-c board rtc configure and spi bus register function

 History:
 1. Date: 2022-03-01
 Author: AIIT XUOS Lab
 Modification:
 1. change command for XUOS
+2. add module codes for XUOS
 *************************************************/

 #include "board.h"
@@ -42,13 +42,13 @@

 /*************************************************
 File name: hardware_rtc.c
-Description: support ok1052-c rtc driver I2C function
+Description: support ok1052-c board rtc hardware driver I2C function

 History:
 1. Date: 2022-01-18
 Author: AIIT XUOS Lab
 Modification:
-1. support ok1052-c rtc
+1. support ok1052-c board rtc
 *************************************************/

 #include "connect_rtc.h"
@@ -9,21 +9,21 @@
 /**
 * @file connect_sdio.c
 * @brief support sdio function using bus driver framework on OK1052 board
-* @version 2.0 
+* @version 2.0
 * @author AIIT XUOS Lab
 * @date 2022-01-24
 */

 /*************************************************
 File name: connect_sdio.c
-Description: support imxrt1052-board sd card configure and sdio bus register function
+Description: support ok1052-c board sd card configure and sdio bus register function
 Others: take SDK_2.6.1_MIMXRT1052xxxxB/boards/evkbimxrt1050/driver_examples/sdcard/polling/sdcard_polling.c for references
-History: 
+History:
 1. Date: 2022-01-24
 Author: AIIT XUOS Lab
-Modification: 
-1. support imxrt1052-board sdio configure, write and read
-2. support imxrt1052-board sdio bus device and driver register
+Modification:
+1. support ok1052-c board sdio configure, write and read
+2. support ok1052-c board sdio bus device and driver register
 *************************************************/

 #include <connect_sdio.h>
@@ -261,7 +261,7 @@ static uint32 SdioWrite(void *dev, struct BusBlockWriteParam *write_param)
    return write_param->size;
 }

-static struct SdioDevDone dev_done = 
+static struct SdioDevDone dev_done =
 {
    SdioOpen,
    SdioClose,
@@ -273,7 +273,7 @@ int Imrt1052HwSdioInit(void)
 {
    x_err_t ret = EOK;
    bool is_read_only;
-    
+
    static struct SdioBus sdio_bus;
    static struct SdioDriver sdio_drv;
    static struct SdioHardwareDevice sdio_dev;
@@ -333,7 +333,7 @@ int Imrt1052HwSdioInit(void)

    /* Check if card is readonly. */
    is_read_only = SD_CheckReadOnly(card);
-    
+
    ret = SdioBusInit(&sdio_bus, SDIO_BUS_NAME);
    if (ret != EOK) {
        KPrintf("Sdio bus init error %d\n", ret);
@@ -10,7 +10,7 @@

 /**
 * @file connect_flash_spi.c
-* @brief support ok1052-c-board spi flash function and register to bus framework
+* @brief support ok1052-c board spi flash function and register to bus framework
 * @version 1.0
 * @author AIIT XUOS Lab
 * @date 2022-03-01
@@ -18,14 +18,14 @@

 /*************************************************
 File name: connect_flash_spi.c
-Description: support ok1052-c-board spi flash bus register function
+Description: support ok1052-c board spi flash bus register function
 Others: take RT-Thread v4.0.2/bsp/stm32/stm32f407-atk-explorer/board/ports/spi-flash-init.c
                https://github.com/RT-Thread/rt-thread/tree/v4.0.2
 History:
 1. Date: 2022-03-01
 Author: AIIT XUOS Lab
 Modification:
-1. for ok1052-c compilation
+1. for ok1052-c board compilation
 *************************************************/

 #include "flash_spi.h"
@@ -15,7 +15,7 @@

 /**
 * @file connect_spi.c
-* @brief support ok1052-c spi function and register to bus framework
+* @brief support ok1052-c board spi function and register to bus framework
 * @version 1.0
 * @author AIIT XUOS Lab
 * @date 2022-03-01
@@ -23,16 +23,16 @@

 /*************************************************
 File name: connect_spi.c
-Description: support ok1052-c spi configure and spi bus register function
+Description: support ok1052-c board spi configure and spi bus register function
 Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_spi.c for references
                https://github.com/RT-Thread/rt-thread/tree/v4.0.2
 History:
 1. Date: 2022-03-01
 Author: AIIT XUOS Lab
 Modification:
-1. support ok1052-c spi configure, write and read
-2. support ok1052-c spi bus device and driver register
-3. add ok1052-c spi test letter command
+1. support ok1052-c board spi configure, write and read
+2. support ok1052-c board spi bus device and driver register
+3. add ok1052-c board spi test letter command
 *************************************************/

 #include "board.h"
@@ -58,7 +58,6 @@ Modification:
 #define TRANSFER_BAUDRATE (500000U) /*! Transfer baudrate - 500k */

 #define spi_print KPrintf
-#define spi_trace() KPrintf("lw: [%s][%d] passed!\n", __func__, __LINE__)

 typedef struct __spi_transfer_t
 {
@@ -8,22 +8,22 @@

 /**
 * @file connect_uart.c
-* @brief support imxrt1052-board uart function and register to bus framework
-* @version 1.0 
+* @brief support ok1052-c board uart function and register to bus framework
+* @version 1.0
 * @author AIIT XUOS Lab
 * @date 2021-05-28
 */

 /*************************************************
 File name: connect_uart.c
-Description: support imxrt1052-board uart configure and uart bus register function
+Description: support ok1052-c board uart configure and uart bus register function
 Others: take SDK_2.6.1_MIMXRT1052xxxxB/components/uart/lpuart_adapter.c for references
-History: 
+History:
 1. Date: 2021-05-28
 Author: AIIT XUOS Lab
-Modification: 
-1. support imxrt1052-board uart configure, write and read
-2. support imxrt1052-board uart bus device and driver register
+Modification:
+1. support ok1052-c board uart configure, write and read
+2. support ok1052-c board uart bus device and driver register
 *************************************************/

 #include <board.h>
@@ -105,7 +105,7 @@ static void UartIsr(struct SerialBus *serial, struct SerialDriver *serial_drv, s
 {
    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
    LPUART_Type *uart_base = (LPUART_Type *)serial_cfg->hw_cfg.private_data;
-    
+
    /* kLPUART_RxDataRegFullFlag can only cleared or set by hardware */
    if (LPUART_GetStatusFlags(uart_base) & kLPUART_RxDataRegFullFlag) {
        SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND);
@@ -262,7 +262,7 @@ static uint32 SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_i
    return ret;
 }

-static const struct SerialDataCfg data_cfg_init = 
+static const struct SerialDataCfg data_cfg_init =
 {
    .serial_baud_rate = BAUD_RATE_115200,
    .serial_data_bits = DATA_BITS_8,
@@ -310,7 +310,7 @@ static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver
    if (EOK != ret) {
        KPrintf("Imrt1052HwUartInit SerialDriverAttachToBus error %d\n", ret);
        return ERROR;
-    } 
+    }

    return ret;
 }
@@ -324,13 +324,13 @@ static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *
    if (EOK != ret) {
        KPrintf("Imrt1052HwUartInit SerialDeviceInit device %s error %d\n", dev_name, ret);
        return ERROR;
-    }  
+    }

    ret = SerialDeviceAttachToBus(dev_name, bus_name);
    if (EOK != ret) {
        KPrintf("Imrt1052HwUartInit SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
        return ERROR;
-    }  
+    }

    return  ret;
 }
@@ -345,7 +345,7 @@ int Imrt1052HwUartInit(void)

    static struct SerialDevParam serial_dev_param_1;
    memset(&serial_dev_param_1, 0, sizeof(struct SerialDevParam));
-    
+
    serial_driver_1.drv_done = &drv_done;
    serial_driver_1.configure = &SerialDrvConfigure;
    serial_device_1.hwdev_done = &hwdev_done;
@@ -369,7 +369,7 @@ int Imrt1052HwUartInit(void)
    if (EOK != ret) {
        KPrintf("Imrt1052HwUartInit uart error ret %u\n", ret);
        return ERROR;
-    }    
+    }
 #endif

 #ifdef BSP_USING_LPUART2
@@ -378,7 +378,7 @@ int Imrt1052HwUartInit(void)

    static struct SerialDevParam serial_dev_param_2;
    memset(&serial_dev_param_2, 0, sizeof(struct SerialDevParam));
-    
+
    serial_driver_2.drv_done = &drv_done;
    serial_driver_2.configure = &SerialDrvConfigure;
    serial_device_2.hwdev_done = &hwdev_done;
@@ -402,7 +402,7 @@ int Imrt1052HwUartInit(void)
    if (EOK != ret) {
        KPrintf("Imrt1052HwUartInit uart error ret %u\n", ret);
        return ERROR;
-    }  
+    }
 #endif

    return ret;
@@ -9,21 +9,21 @@
 /**
 * @file connect_usb.c
 * @brief support usb host function using bus driver framework on OK1052 board
-* @version 2.0 
+* @version 2.0
 * @author AIIT XUOS Lab
 * @date 2022-02-09
 */

 /*************************************************
 File name: connect_usb.c
-Description: support imxrt1052-board usb host configure and sdio bus register function
+Description: support ok1052-c board usb host configure and sdio bus register function
 Others: take SDK_2.6.1_MIMXRT1052xxxxB/boards/evkbimxrt1050/usb_examples/usb_host_msd_command for references
-History: 
+History:
 1. Date: 2022-02-09
 Author: AIIT XUOS Lab
-Modification: 
-1. support imxrt1052-board usb host configure, write and read
-2. support imxrt1052-board usb host bus device and driver register
+Modification:
+1. support ok1052-c board usb host configure, write and read
+2. support ok1052-c board usb host bus device and driver register
 *************************************************/
 #include <board.h>
 #include <connect_usb.h>
@@ -202,7 +202,7 @@ static void UsbHostTask(void* parameter)
    }
 }

-/*Init usb host bus、driver*/
+/*Init usb host bus driver*/
 static int BoardUsbBusInit(struct UsbBus *usb_bus, struct UsbDriver *usb_driver)
 {
    x_err_t ret = EOK;
@@ -255,7 +255,7 @@ static int BoardUsbDevBend(void)
    return ret;
 }

-/*RT1052 BOARD USB INIT*/
+/*OK1052-C BOARD USB INIT*/
 int Imrt1052HwUsbHostInit(void)
 {
    x_err_t ret = EOK;
@@ -283,7 +283,7 @@ int Imrt1052HwUsbHostInit(void)

    usb_host_task = KTaskCreate("usbh", UsbHostTask, NONE,
                           USB_HOST_STACK_SIZE, 8);
-    if(usb_host_task < 0) {		
+    if(usb_host_task < 0) {
 		KPrintf("usb_host_task create failed ...%s %d.\n", __FUNCTION__,__LINE__);
 		return ERROR;
 	}
@@ -18,23 +18,29 @@ $ sudo apt install build-essential pkg-config
 $ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev  git
 ```

-**源码下载：** XiUOS [https://forgeplus.trustie.net/projects/xuos/xiuos](https://forgeplus.trustie.net/projects/xuos/xiuos)
+**源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos)

 新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下：

 ```c
 mkdir test  &&  cd test
-git clone https://git.trustie.net/xuos/xiuos.git
+git clone https://gitlink.org.cn/xuos/xiuos.git
 ```

-打开源码文件包可以看到以下目录：
+1、打开XiUOS源码文件包可以看到以下目录：
 | 名称 | 说明 |
 | -- | -- |
-| application | 应用代码 |
+| APP_Framework | 应用代码 |
+| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 |
+
+2、打开XiZi内核源码文件包可以看到以下目录：
+| 名称 | 说明 |
+| -- | -- |
+| arch | 架构代码 |
 | board | 板级支持包 |
-| framework | 应用框架 |
 | fs | 文件系统 |
 | kernel | 内核源码 |
+| lib | 第三方库源码 |
 | resources | 驱动文件 |
 | tool | 系统工具 |

@@ -46,18 +52,18 @@ git clone https://git.trustie.net/xuos/xiuos.git

 裁减配置工具：

-**工具地址：** kconfig-frontends [https://forgeplus.trustie.net/projects/xuos/kconfig-frontends](https://forgeplus.trustie.net/projects/xuos/kconfig-frontends)
+**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)

 ```c
 mkdir kfrontends  && cd kfrontends
-git  clone https://git.trustie.net/xuos/kconfig-frontends.git
+git clone https://gitlink.org.cn/xuos/kconfig-frontends.git
 ```

 下载源码后按以下步骤执行软件安装：

 ```c
 cd kconfig-frontends
- ./xs_build.sh
+./xs_build.sh
 ```

 ### 编译工具链：
@@ -97,7 +103,7 @@ XiUOS板级当前支持使用UART。

 使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入终端即可打开目标项目

-修改`applications`文件夹下`main.c`
+修改`APP_Framework/Applications`文件夹下`main.c`

 在输出函数中写入  Hello, world! \n 完成代码编辑。

@@ -107,6 +113,8 @@ XiUOS板级当前支持使用UART。
 1.在VScode终端下执行以下命令，生成配置文件

 ```
+cd ./Ubiquitous/XiZi
+make BOARD=rm32v1_vega distclean
 make BOARD=rm32v1_vega menuconfig
 ```

@@ -120,7 +128,7 @@ make BOARD=rm32v1_vega menuconfig
 make BOARD=rv32m1_vega
 ```

-4.如果编译正确无误，build文件夹下会产生XiUOS_rv32m1_vega.elf、XiUOS_rv32m1_vega.bin文件。
+4.如果编译正确无误，build文件夹下会产生XiZi_rv32m1_vega.elf、XiZi_rv32m1_vega.bin文件。

 >注：最后可以执行以下命令，清除配置文件和编译生成的文件

@@ -168,7 +176,7 @@ screen /dev/ttyUSB0 115200

 5、打开一个新的终端，进入编译生成的elf路径,输入例如：
 ```
-riscv-none-embed-gdb build/XiUOS_rv32m1_vega.elf -ex "target remote localhost:3333"
+riscv-none-embed-gdb build/XiZi_rv32m1_vega.elf -ex "target remote localhost:3333"
 ```
 结果如下图所示：
 ![gdb](./img/gdb_load.png)
@@ -47,23 +47,29 @@ $ sudo apt install build-essential pkg-config  git
 $ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev
 ```

-**XiUOS操作系统源码下载：** XiUOS [https://forgeplus.trustie.net/projects/xuos/xiuos](https://forgeplus.trustie.net/projects/xuos/xiuos)
+**XiUOS操作系统源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos)

 新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下：

 ```c
 mkdir test  &&  cd test
-git clone https://git.trustie.net/xuos/xiuos.git
+git clone https://gitlink.org.cn/xuos/xiuos.git
 ```

-打开源码文件包可以看到以下目录：
+1、打开XiUOS源码文件包可以看到以下目录：
 | 名称 | 说明 |
 | -- | -- |
-| application | 应用代码 |
+| APP_Framework | 应用代码 |
+| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 |
+
+2、打开XiZi内核源码文件包可以看到以下目录：
+| 名称 | 说明 |
+| -- | -- |
+| arch | 架构代码 |
 | board | 板级支持包 |
-| framework | 应用框架 |
 | fs | 文件系统 |
 | kernel | 内核源码 |
+| lib | 第三方库源码 |
 | resources | 驱动文件 |
 | tool | 系统工具 |

@@ -77,18 +83,18 @@ git clone https://git.trustie.net/xuos/xiuos.git

 裁减配置工具：

-**工具地址：** kconfig-frontends [https://forgeplus.trustie.net/projects/xuos/kconfig-frontends](https://forgeplus.trustie.net/projects/xuos/kconfig-frontends)，下载与安装的具体命令如下：
+**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)，下载与安装的具体命令如下：

 ```c
 mkdir kfrontends  && cd kfrontends
-git  clone https://git.trustie.net/xuos/kconfig-frontends.git
+git clone https://gitlink.org.cn/xuos/kconfig-frontends.git
 ```

 下载源码后按以下步骤执行软件安装：

 ```c
 cd kconfig-frontends
- ./xs_build.sh
+./xs_build.sh
 ```

 ### 编译工具链：
@@ -132,8 +138,9 @@ XiUOS板级驱动当前支持使用GPIO、UART。
 1.在VScode命令终端中执行以下命令，生成配置文件。

 ```c
-   make BOARD=stm32f103-nano distclean
-   make BOARD=stm32f103-nano menuconfig
+cd ./Ubiquitous/XiZi
+make BOARD=stm32f103-nano distclean
+make BOARD=stm32f103-nano menuconfig
 ```

 2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置）。
@@ -184,7 +191,7 @@ XiUOS板级驱动当前支持使用GPIO、UART。
 make BOARD=stm32f103-nano
 ```

-5.如果编译正确无误，会产生XiUOS_stm32f103-nano.elf、XiUOS_stm32f103-nano.bin文件。其中XiUOS_stm32f103-nano.bin需要烧写到设备中进行运行。
+5.如果编译正确无误，会产生XiZi_stm32f103-nano.elf、XiZi_stm32f103-nano.bin文件。其中XiZi_stm32f103-nano.bin需要烧写到设备中进行运行。

 ## 3. 烧写及执行

@@ -212,7 +219,7 @@ cd build/Release && make install DESTDIR=_install
 代码根目录下执行st-flash工具烧录

 ```
-sudo st-flash write build/XiUOS_stm32f103-nano.bin 0x8000000
+sudo st-flash write build/XiZi_stm32f103-nano.bin 0x8000000
 ```

 ### 3.1 运行结果
@@ -49,23 +49,29 @@ $ sudo apt install build-essential pkg-config  git
 $ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev
 ```

-**XiUOS操作系统源码下载：** XiUOS [https://forgeplus.trustie.net/projects/xuos/xiuos](https://forgeplus.trustie.net/projects/xuos/xiuos)
+**XiUOS操作系统源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos)

 新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下：

 ```c
 mkdir test  &&  cd test
-git clone https://git.trustie.net/xuos/xiuos.git
+git clone https://gitlink.org.cn/xuos/xiuos.git
 ```

-打开源码文件包可以看到以下目录：
+1、打开XiUOS源码文件包可以看到以下目录：
 | 名称 | 说明 |
 | -- | -- |
-| application | 应用代码 |
+| APP_Framework | 应用代码 |
+| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 |
+
+2、打开XiZi内核源码文件包可以看到以下目录：
+| 名称 | 说明 |
+| -- | -- |
+| arch | 架构代码 |
 | board | 板级支持包 |
-| framework | 应用框架 |
 | fs | 文件系统 |
 | kernel | 内核源码 |
+| lib | 第三方库源码 |
 | resources | 驱动文件 |
 | tool | 系统工具 |

@@ -79,18 +85,18 @@ git clone https://git.trustie.net/xuos/xiuos.git

 裁减配置工具：

-**工具地址：** kconfig-frontends [https://forgeplus.trustie.net/projects/xuos/kconfig-frontends](https://forgeplus.trustie.net/projects/xuos/kconfig-frontends)，下载与安装的具体命令如下：
+**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)，下载与安装的具体命令如下：

 ```c
 mkdir kfrontends  && cd kfrontends
-git  clone https://git.trustie.net/xuos/kconfig-frontends.git
+git clone https://gitlink.org.cn/xuos/kconfig-frontends.git
 ```

 下载源码后按以下步骤执行软件安装：

 ```c
 cd kconfig-frontends
- ./xs_build.sh
+./xs_build.sh
 ```

 ### 编译工具链：
@@ -124,7 +130,7 @@ XiUOS板级驱动当前支持使用GPIO、I2C、LCD、USB、RTC、SPI、Timer、
 ### 编译工具链：`arm-none-eabi-gcc`
 使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入linux系统命令终端即可打开目标项目

-修改`applications`文件夹下`main.c`
+修改`APP_Framework/Applications`文件夹下`main.c`
 在输出函数中写入 `Hello, world!!! \n   Running on stm32f407-st-discovery`完成代码编辑。

 ![main](img/main.png)
@@ -134,7 +140,9 @@ XiUOS板级驱动当前支持使用GPIO、I2C、LCD、USB、RTC、SPI、Timer、
 1.在VScode命令终端中执行以下命令，生成配置文件

 ```c
-   make BOARD=stm32f407-st-discovery menuconfig
+cd ./Ubiquitous/XiZi
+make BOARD=stm32f407-st-discovery distclean
+make BOARD=stm32f407-st-discovery menuconfig
 ```

 2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置）
@@ -151,7 +159,7 @@ XiUOS板级驱动当前支持使用GPIO、I2C、LCD、USB、RTC、SPI、Timer、
 make BOARD=stm32f407-st-discovery
 ```

-4.如果编译正确无误，会产生XiUOS_stm32f407-st-discovery.elf、XiUOS_stm32f407-st-discovery.bin文件。其中XiUOS_stm32f407-st-discovery.bin需要烧写到设备中进行运行。
+4.如果编译正确无误，会产生XiZi_stm32f407-st-discovery.elf、XiZi_stm32f407-st-discovery.bin文件。其中XiZi_stm32f407-st-discovery.bin需要烧写到设备中进行运行。

 ## 3. 烧写及执行

@@ -170,7 +178,7 @@ ARM：ST-LINK（ST-LINK V2实物如图，可在购物网站搜索关键字购买
 ```
 sudo apt install libusb-dev
 sudo apt install libusb-1.0-0-dev
-sudo apt  install cmake
+sudo apt install cmake
 cd stlink
 make
 cd build/Release && make install DESTDIR=_install
@@ -181,13 +189,13 @@ cd build/Release && make install DESTDIR=_install
 代码根目录下执行st-flash工具烧录

 ```
-sudo st-flash  write  build/XiUOS_stm32f407-st-discovery.bin 0x8000000
+sudo st-flash write build/XiZi_stm32f407-st-discovery.bin 0x8000000
 ```

 此外，推荐用户使用putty作为终端工具，安装命令如下：

 ```c
-sudo apt install  putty
+sudo apt install putty
 ```

 打开putty配置串口信息
@@ -203,7 +211,7 @@ sudo puty
 注意：选择正确的终端端口号，最后可以执行以下命令，清除配置文件和编译生成的文件

 ```c
-make  BOARD=stm32f407-st-discovery distclean
+make BOARD=stm32f407-st-discovery distclean
 ```

 ### 3.1 运行结果
@@ -12,7 +12,7 @@

 /**
 * @file connect_gpio.h
-* @brief define ok1052-c gpio function and struct
+* @brief define stm32f407-st-discovery-board gpio function and struct
 * @version 1.0
 * @author AIIT XUOS Lab
 * @date 2022-03-01
@@ -29,23 +29,25 @@ sudo apt-get install gcc-arm-none-eabi
 >2.在代码根目录下执行以下命令，生成配置文件

 ```
+cd ./Ubiquitous/XiZi
+make BOARD=stm32f407zgt6 distclean
 make BOARD=stm32f407zgt6 menuconfig
 ```
 >3.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出

-![img](menu.png )
+![img](./img/menu.png )

 >4.继续执行以下命令，进行编译
 ```
 make BOARD=stm32f407zgt6
 ```
->5.如果编译正确无误，会产生XiUOS_stm32f407zgt6.elf、XiUOS_stm32f407zgt6.bin文件。其中XiUOS_stm32f407zgt6.bin需要烧写到设备中进行运行。
+>5.如果编译正确无误，会产生XiZi_stm32f407zgt6.elf、XiZi_stm32f407zgt6.bin文件。其中XiZi_stm32f407zgt6.bin需要烧写到设备中进行运行。
 ```
-sudo write build/XiUOS_stm32f407zgt6.bin 0x8000000
+sudo write build/XiZi_stm32f407zgt6.bin 0x8000000
 ```
 >6.最后可以执行以下命令，清除配置文件和编译生成的文件
 ```
-make  BOARD=stm32f407zgt6 distclean
+make BOARD=stm32f407zgt6 distclean
 ```

 ## 3. 烧写及执行
@@ -59,21 +61,21 @@ git clone https://github.com/texane/stlink.git

 开发板接口如下：
 <div align= "center"> 
-<img src = interface.jpg   width =50%>
+<img src = ./img/interface.jpg   width =50%>
  </div>

  实际连接图为：
  <div align= "center"> 
-<img src = total.jpg   width =50%>
+<img src = ./img/total.jpg   width =50%>
  </div>

 在代码根目录下执行st-flash工具烧录
 ```
-sudo st-flash  write  build/XiUOS_stm32f407zgt6.bin 0x8000000
+sudo st-flash write build/XiZi_stm32f407zgt6.bin 0x8000000
 ```
 ### 3.1 运行结果

 如果编译 & 烧写无误，将会在串口终端上看到信息打印输出，(终端串口引脚为PB6、PB7)。
  <div align= "center"> 
-<img src = shell.png   >
+<img src = ./img/shell.png   >
  </div>
@@ -0,0 +1,59 @@
+mainmenu "XiZi Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config KERNEL_DIR
+    string
+    option env="KERNEL_ROOT"
+    default "../.."
+
+config BOARD_CORTEX_M7_EVB
+    bool
+    select  ARCH_ARM
+    default y
+
+
+source "$KERNEL_DIR/arch/Kconfig"
+
+menu "xidatong feature"
+    source "$BSP_DIR/third_party_driver/Kconfig"
+
+    menu "config default board resources"
+        menu "config board app name"
+            config BOARD_APP_NAME
+                string "config board app name"
+                default "/XiUOS_xidatong_app.bin"
+        endmenu
+
+        menu "config board service table"
+            config SERVICE_TABLE_ADDRESS
+                hex "board service table address"
+                default 0x2007F0000
+        endmenu
+
+    endmenu
+
+    config __STACKSIZE__
+        int "stack size for interrupt"
+        default 4096
+
+    menu "config board peripheral"
+        config MOUNT_SDCARD
+            bool "mount cd card"
+            default n
+            select BSP_USING_SDIO
+    endmenu
+
+endmenu
+
+
+menu "Hardware feature"
+source "$KERNEL_DIR/resources/Kconfig"
+endmenu
+
+source "$KERNEL_DIR/Kconfig"
+
+
@@ -0,0 +1,5 @@
+SRC_DIR := third_party_driver
+
+SRC_FILES := board.c
+
+include $(KERNEL_ROOT)/compiler.mk
@@ -0,0 +1,163 @@
+# 从零开始构建矽璓工业物联操作系统：使用ARM架构的矽达通
+
+# xidatong
+
+[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓XiUOS是一款面向智慧车间的工业物联网操作系统，主要由一个极简的微型实时操作系统内核和其上的工业物联框架构成，通过高效管理工业物联网设备、支撑工业物联应用，在生产车间内实现智能化的“感知环境、联网传输、知悉识别、控制调整”，促进以工业设备和工业控制系统为核心的人、机、物深度互联，帮助提升生产线的数字化和智能化水平。
+
+## 1. 简介
+
+| 硬件 | 描述 |
+| -- | -- |
+|芯片型号| MIMXRT1052DVL6A |
+|架构| cortex-m7 |
+|主频| 600MHz |
+|片内SRAM| 512KB shared with TCM |
+|外设支持| UART |
+
+XiUOS板级当前支持使用UART。
+
+## 2. 开发环境搭建
+
+### 推荐使用：
+
+**操作系统：** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop)
+
+更新`ubuntu 18.04`源的方法:（根据自身情况而定，可以不更改）
+
+第一步:打开sources.list文件
+
+```c
+sudo vim /etc/apt/sources.list
+```
+
+第二步:将以下内容复制到sources.list文件
+
+```c
+deb http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse
+deb http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse
+deb http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse
+deb http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse
+deb http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse
+deb-src http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse
+deb-src http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse
+deb-src http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse
+deb-src http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse
+deb-src http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse
+```
+
+第三步:更新源和系统软件
+
+```c
+sudo apt-get update
+sudo apt-get upgrade
+```
+
+**开发工具推荐使用 VSCode   ，VScode下载地址为：** VSCode  [https://code.visualstudio.com/](https://code.visualstudio.com/)，推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb)
+
+### 依赖包安装：
+
+```
+$ sudo apt install build-essential pkg-config  git
+$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev
+```
+
+**XiUOS操作系统源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos)
+
+新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下：
+
+```c
+mkdir test  &&  cd test
+git clone https://gitlink.org.cn/xuos/xiuos.git
+```
+
+1、打开XiUOS源码文件包可以看到以下目录：
+| 名称 | 说明 |
+| -- | -- |
+| APP_Framework | 应用代码 |
+| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 |
+
+2、打开XiZi内核源码文件包可以看到以下目录：
+| 名称 | 说明 |
+| -- | -- |
+| arch | 架构代码 |
+| board | 板级支持包 |
+| fs | 文件系统 |
+| kernel | 内核源码 |
+| lib | 第三方库源码 |
+| resources | 驱动文件 |
+| tool | 系统工具 |
+
+使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示：
+
+<div align= "center"> 
+<img src = ./img/vscode.jpg  width =1000>
+  </div>
+
+### 裁减配置工具的下载
+
+裁减配置工具：
+
+**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)，下载与安装的具体命令如下：
+
+```c
+mkdir kfrontends  && cd kfrontends
+git clone https://gitlink.org.cn/xuos/kconfig-frontends.git
+```
+
+下载源码后按以下步骤执行软件安装：
+
+```c
+cd kconfig-frontends
+./xs_build.sh
+```
+
+### 编译工具链：
+
+ARM： arm-none-eabi(`gcc version 6.3.1`)，默认安装到Ubuntu的/usr/bin/arm-none-eabi-，使用如下命令行下载和安装。
+
+```shell
+$ sudo apt install gcc-arm-none-eabi
+```
+
+## 编译说明
+
+### 编辑环境：`Ubuntu18.04`
+
+### 编译工具链：`arm-none-eabi-gcc`
+使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入linux系统命令终端即可打开目标项目
+
+
+编译步骤：
+
+1.在VScode命令终端中执行以下命令，生成配置文件
+
+```c
+cd ./Ubiquitous/XiZi
+make BOARD=xidatong distclean
+make BOARD=xidatong menuconfig
+```
+
+2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置）
+
+![menuconfig](./img/menuconfig.png)
+
+退出时选择`yes`保存上面所配置的内容，如下图所示：
+
+![menuconfig1](./img/menuconfig1.png)
+
+3.继续执行以下命令，进行编译
+
+```
+make BOARD=xidatong
+```
+
+4.如果编译正确无误，会产生XiZi_xidatong.elf、XiZi_xidatong.bin文件。
+
+## 3. 烧写及运行
+
+### 3.1 烧写
+
+
+### 3.2 运行结果
+
+
@@ -0,0 +1,683 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/**
+ * @file board.c
+ * @brief relative configure for xidatong
+ * @version 1.0
+ * @author AIIT XUOS Lab
+ * @date 2021.11.11
+ */
+
+/*************************************************
+File name: board.c
+Description: support imxrt1052-board init function
+Others: take SDK_2.6.1_MIMXRT1052xxxxB for references
+History: 
+1. Date: 2022-01-25
+Author: AIIT XUOS Lab
+Modification: 
+1. support imxrt1052-board MPU、clock、memory init
+2. support imxrt1052-board uart、semc、sdio driver init
+*************************************************/
+
+#include "fsl_common.h"
+#include "board.h"
+#include "pin_mux.h"
+
+#ifdef BSP_USING_SDIO
+extern int Imrt1052HwSdioInit(void);
+#endif
+
+#ifdef BSP_USING_SEMC
+extern status_t BOARD_InitSEMC(void);
+#ifdef BSP_USING_EXTSRAM
+extern int ExtSramInit(void);
+#endif
+#endif
+
+#if defined(FS_VFS) && defined(MOUNT_SDCARD)
+#include <iot-vfs.h>
+
+/**
+ * @description: Mount SD card
+ * @return 0
+ */
+int MountSDCard(void)
+{
+    if (MountFilesystem(SDIO_BUS_NAME, SDIO_DEVICE_NAME, SDIO_DRIVER_NAME, FSTYPE_FATFS, "/") == 0)
+        KPrintf("sd card mount to '/'");
+    else
+        KPrintf("sd card mount to '/' failed!");
+    
+    return 0;
+}
+#endif
+
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+#include "fsl_lpi2c.h"
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+#include "fsl_iomuxc.h"
+#include "fsl_gpio.h"
+#include "fsl_lpuart.h"
+
+#ifdef BSP_USING_LPUART
+#include <connect_uart.h>
+#endif
+
+#define NVIC_PRIORITYGROUP_0         0x00000007U /*!< 0 bits for pre-emption priority
+                                                      4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         0x00000006U /*!< 1 bits for pre-emption priority
+                                                      3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         0x00000005U /*!< 2 bits for pre-emption priority
+                                                      2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         0x00000004U /*!< 3 bits for pre-emption priority
+                                                      1 bits for subpriority */
+#define NVIC_PRIORITYGROUP_4         0x00000003U /*!< 4 bits for pre-emption priority
+
+
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if 0
+/* Get debug console frequency. */
+uint32_t BOARD_DebugConsoleSrcFreq(void)
+{
+    uint32_t freq;
+
+    /* To make it simple, we assume default PLL and divider settings, and the only variable
+       from application is use PLL3 source or OSC source */
+    if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
+    {
+        freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
+    }
+    else
+    {
+        freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
+    }
+
+    return freq;
+}
+
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+    uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
+
+    DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
+
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
+{
+    lpi2c_master_config_t lpi2cConfig = {0};
+
+    /*
+     * lpi2cConfig.debugEnable = false;
+     * lpi2cConfig.ignoreAck = false;
+     * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
+     * lpi2cConfig.baudRate_Hz = 100000U;
+     * lpi2cConfig.busIdleTimeout_ns = 0;
+     * lpi2cConfig.pinLowTimeout_ns = 0;
+     * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
+     * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
+     */
+    LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
+    LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
+}
+
+status_t BOARD_LPI2C_Send(LPI2C_Type *base,
+                          uint8_t deviceAddress,
+                          uint32_t subAddress,
+                          uint8_t subAddressSize,
+                          uint8_t *txBuff,
+                          uint8_t txBuffSize)
+{
+    status_t reVal;
+
+    /* Send master blocking data to slave */
+    reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write);
+    if (kStatus_Success == reVal)
+    {
+        while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag)
+        {
+        }
+
+        reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize);
+        if (reVal != kStatus_Success)
+        {
+            return reVal;
+        }
+
+        reVal = LPI2C_MasterSend(base, txBuff, txBuffSize);
+        if (reVal != kStatus_Success)
+        {
+            return reVal;
+        }
+
+        reVal = LPI2C_MasterStop(base);
+        if (reVal != kStatus_Success)
+        {
+            return reVal;
+        }
+    }
+
+    return reVal;
+}
+
+status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
+                             uint8_t deviceAddress,
+                             uint32_t subAddress,
+                             uint8_t subAddressSize,
+                             uint8_t *rxBuff,
+                             uint8_t rxBuffSize)
+{
+    status_t reVal;
+
+    reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write);
+    if (kStatus_Success == reVal)
+    {
+        while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag)
+        {
+        }
+
+        reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize);
+        if (reVal != kStatus_Success)
+        {
+            return reVal;
+        }
+
+        reVal = LPI2C_MasterRepeatedStart(base, deviceAddress, kLPI2C_Read);
+
+        if (reVal != kStatus_Success)
+        {
+            return reVal;
+        }
+
+        reVal = LPI2C_MasterReceive(base, rxBuff, rxBuffSize);
+        if (reVal != kStatus_Success)
+        {
+            return reVal;
+        }
+
+        reVal = LPI2C_MasterStop(base);
+        if (reVal != kStatus_Success)
+        {
+            return reVal;
+        }
+    }
+    return reVal;
+}
+
+status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
+                              uint8_t deviceAddress,
+                              uint32_t subAddress,
+                              uint8_t subAddressSize,
+                              uint8_t *txBuff,
+                              uint8_t txBuffSize)
+{
+    return BOARD_LPI2C_Send(base, deviceAddress, subAddress, subAddressSize, txBuff, txBuffSize);
+}
+
+status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
+                                 uint8_t deviceAddress,
+                                 uint32_t subAddress,
+                                 uint8_t subAddressSize,
+                                 uint8_t *rxBuff,
+                                 uint8_t rxBuffSize)
+{
+    status_t reVal;
+
+    reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write);
+    if (kStatus_Success == reVal)
+    {
+        while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag)
+        {
+        }
+
+        reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize);
+        if (reVal != kStatus_Success)
+        {
+            return reVal;
+        }
+
+        /* SCCB does not support LPI2C repeat start, must stop then start. */
+        reVal = LPI2C_MasterStop(base);
+
+        if (reVal != kStatus_Success)
+        {
+            return reVal;
+        }
+
+        reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Read);
+
+        if (reVal != kStatus_Success)
+        {
+            return reVal;
+        }
+
+        reVal = LPI2C_MasterReceive(base, rxBuff, rxBuffSize);
+        if (reVal != kStatus_Success)
+        {
+            return reVal;
+        }
+
+        reVal = LPI2C_MasterStop(base);
+        if (reVal != kStatus_Success)
+        {
+            return reVal;
+        }
+    }
+    return reVal;
+}
+
+void BOARD_Accel_I2C_Init(void)
+{
+    BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
+{
+    uint8_t data = (uint8_t)txBuff;
+
+    return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
+}
+
+status_t BOARD_Accel_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+    return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
+}
+
+void BOARD_Codec_I2C_Init(void)
+{
+    BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Codec_I2C_Send(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
+{
+    return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
+                            txBuffSize);
+}
+
+status_t BOARD_Codec_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+    return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
+}
+
+void BOARD_Camera_I2C_Init(void)
+{
+    CLOCK_SetMux(kCLOCK_Lpi2cMux, BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT);
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER);
+    BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Camera_I2C_Send(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
+{
+    return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
+                            txBuffSize);
+}
+
+status_t BOARD_Camera_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+    return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
+                               rxBuffSize);
+}
+
+status_t BOARD_Camera_I2C_SendSCCB(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
+{
+    return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
+                                txBuffSize);
+}
+
+status_t BOARD_Camera_I2C_ReceiveSCCB(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+    return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
+                                   rxBuffSize);
+}
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+#endif
+
+
+void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength)
+{
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD,
+                        IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
+                            IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK,
+                        IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
+                            IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0,
+                        IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
+                            IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1,
+                        IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
+                            IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2,
+                        IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
+                            IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3,
+                        IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
+                            IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
+}
+
+void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength)
+{
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_05_USDHC2_CMD,
+                        IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
+                            IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_04_USDHC2_CLK,
+                        IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
+                            IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0,
+                        IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
+                            IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1,
+                        IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
+                            IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2,
+                        IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
+                            IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3,
+                        IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
+                            IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4,
+                        IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
+                            IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5,
+                        IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
+                            IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6,
+                        IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
+                            IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7,
+                        IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+                            IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
+                            IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
+}
+
+/* MPU configuration. */
+void BOARD_ConfigMPU(void)
+{
+    /* Disable I cache and D cache */
+    if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
+    {
+        SCB_DisableICache();
+    }
+    if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
+    {
+        SCB_DisableDCache();
+    }
+
+    /* Disable MPU */
+    ARM_MPU_Disable();
+
+    /* MPU configure:
+     * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
+     * SubRegionDisable, Size)
+     * API in mpu_armv7.h.
+     * param DisableExec       Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
+     * disabled.
+     * param AccessPermission  Data access permissions, allows you to configure read/write access for User and
+     * Privileged mode.
+     *      Use MACROS defined in mpu_armv7.h:
+     * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
+     * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
+     *  TypeExtField  IsShareable  IsCacheable  IsBufferable   Memory Attribtue    Shareability        Cache
+     *     0             x           0           0             Strongly Ordered    shareable
+     *     0             x           0           1              Device             shareable
+     *     0             0           1           0              Normal             not shareable   Outer and inner write
+     * through no write allocate
+     *     0             0           1           1              Normal             not shareable   Outer and inner write
+     * back no write allocate
+     *     0             1           1           0              Normal             shareable       Outer and inner write
+     * through no write allocate
+     *     0             1           1           1              Normal             shareable       Outer and inner write
+     * back no write allocate
+     *     1             0           0           0              Normal             not shareable   outer and inner
+     * noncache
+     *     1             1           0           0              Normal             shareable       outer and inner
+     * noncache
+     *     1             0           1           1              Normal             not shareable   outer and inner write
+     * back write/read acllocate
+     *     1             1           1           1              Normal             shareable       outer and inner write
+     * back write/read acllocate
+     *     2             x           0           0              Device              not shareable
+     *  Above are normal use settings, if your want to see more details or want to config different inner/outter cache
+     * policy.
+     *  please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
+     * param SubRegionDisable  Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
+     * param Size              Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
+     * mpu_armv7.h.
+     */
+
+    /* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */
+    MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
+
+    /* Region 1 setting: Memory with Device type, not shareable,  non-cacheable. */
+    MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
+
+/* Region 2 setting */
+#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
+    /* Setting Memory with Normal type, not shareable, outer/inner write back. */
+    MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
+#else
+    /* Setting Memory with Device type, not shareable, non-cacheable. */
+    MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_64MB);
+#endif
+
+    /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
+    MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
+
+    /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
+    MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
+
+    /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
+    MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
+
+    /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
+    MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
+
+/* The define sets the cacheable memory to shareable,
+ * this suggestion is referred from chapter 2.2.1 Memory regions,
+ * types and attributes in Cortex-M7 Devices, Generic User Guide */
+#if defined(SDRAM_IS_SHAREABLE)
+    /* Region 7 setting: Memory with Normal type, shareable, outer/inner write back */
+    MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
+#else
+    /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
+    MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
+#endif
+
+    /* Region 8 setting, set last 2MB of SDRAM can't be accessed by cache, glocal variables which are not expected to be
+     * accessed by cache can be put here */
+    /* Memory with Normal type, not shareable, non-cacheable */
+    MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
+
+    /* Enable MPU */
+    ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
+
+    /* Enable I cache and D cache */
+    SCB_EnableDCache();
+    SCB_EnableICache();
+}
+
+
+/* This is the timer interrupt service routine. */
+void SysTick_Handler(int irqn, void *arg)
+{
+    TickAndTaskTimesliceUpdate();
+}
+DECLARE_HW_IRQ(SYSTICK_IRQN, SysTick_Handler, NONE);
+
+#ifdef BSP_USING_LPUART
+void imxrt_uart_pins_init(void)
+{
+#ifdef BSP_USING_LPUART1
+
+        IOMUXC_SetPinMux(
+            IOMUXC_GPIO_AD_B0_12_LPUART1_TX,        /* GPIO_AD_B0_12 is configured as LPUART1_TX */
+            0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+        IOMUXC_SetPinMux(
+            IOMUXC_GPIO_AD_B0_13_LPUART1_RX,        /* GPIO_AD_B0_13 is configured as LPUART1_RX */
+            0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+        IOMUXC_SetPinConfig(
+            IOMUXC_GPIO_AD_B0_12_LPUART1_TX,        /* GPIO_AD_B0_12 PAD functional properties : */
+            0x10B0u);                               /* Slew Rate Field: Slow Slew Rate
+                                                     Drive Strength Field: R0/6
+                                                     Speed Field: medium(100MHz)
+                                                     Open Drain Enable Field: Open Drain Disabled
+                                                     Pull / Keep Enable Field: Pull/Keeper Enabled
+                                                     Pull / Keep Select Field: Keeper
+                                                     Pull Up / Down Config. Field: 100K Ohm Pull Down
+                                                     Hyst. Enable Field: Hysteresis Disabled */
+        IOMUXC_SetPinConfig(
+            IOMUXC_GPIO_AD_B0_13_LPUART1_RX,        /* GPIO_AD_B0_13 PAD functional properties : */
+            0x10B0u);                               /* Slew Rate Field: Slow Slew Rate
+                                                     Drive Strength Field: R0/6
+                                                     Speed Field: medium(100MHz)
+                                                     Open Drain Enable Field: Open Drain Disabled
+                                                     Pull / Keep Enable Field: Pull/Keeper Enabled
+                                                     Pull / Keep Select Field: Keeper
+                                                     Pull Up / Down Config. Field: 100K Ohm Pull Down
+                                                     Hyst. Enable Field: Hysteresis Disabled */
+#endif
+#ifdef BSP_USING_LPUART2
+
+        IOMUXC_SetPinMux(
+            IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
+            0U);
+        IOMUXC_SetPinMux(
+            IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
+            0U);
+        IOMUXC_SetPinConfig(
+            IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
+            0x10B0u);
+        IOMUXC_SetPinConfig(
+            IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
+            0x10B0u);
+
+#endif
+
+}
+#endif /* BSP_USING_LPUART */
+
+/**
+ * This function will initial rt1050 board.
+ */
+void InitBoardHardware()
+{
+    BOARD_ConfigMPU();
+    BOARD_InitPins();
+    BOARD_BootClockRUN();
+
+#ifndef BSP_USING_LWIP
+    NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+    SysTick_Config(SystemCoreClock / TICK_PER_SECOND);
+#endif
+
+#ifdef BSP_USING_LPUART
+    imxrt_uart_pins_init();
+#endif
+
+    InitBoardMemory((void *)HEAP_BEGIN, (void *)HEAP_END);
+#ifdef BSP_USING_SEMC
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 29);
+    /* Set semc clock to 163.86 MHz */
+    CLOCK_SetMux(kCLOCK_SemcMux, 1);
+    CLOCK_SetDiv(kCLOCK_SemcDiv, 1);
+
+    if (BOARD_InitSEMC() != kStatus_Success) {
+        KPrintf("\r\n SEMC Init Failed\r\n");
+    }
+#ifdef MEM_EXTERN_SRAM
+    else {
+        ExtSramInit();
+    }
+#endif
+#endif
+
+#ifdef BSP_USING_LWIP
+    ETH_BSP_Config();
+#endif
+
+#ifdef BSP_USING_LPUART
+    Imrt1052HwUartInit();
+#endif
+
+#ifdef BSP_USING_ADC
+    Imrt1052HwAdcInit();
+#endif
+
+#ifdef BSP_USING_SPI
+    Imrt1052HwSpiInit();
+#endif
+
+#ifdef BSP_USING_RTC
+    Imrt1052HwRtcInit();
+#endif
+
+    InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
+
+#ifdef BSP_USING_SDIO
+    Imrt1052HwSdioInit();
+#endif
+
+}
+
@@ -0,0 +1,22 @@
+export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
+
+export CFLAGS := -mcpu=cortex-m7 -mthumb  -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb
+export AFLAGS := -c -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb  -gdwarf-2
+
+### if use USB function, use special lds file because USB uses ITCM
+
+ifeq ($(CONFIG_BSP_USING_USB),y)
+export LFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi_xidatong.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link-usb.lds
+else
+export LFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi_xidatong.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
+endif
+
+export CXXFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g
+
+export APPLFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
+
+
+export DEFINES := -DHAVE_CCONFIG_H  -DCPU_MIMXRT1052CVL5B -DSKIP_SYSCLK_INIT -DEVK_MCIMXRM -DFSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1 -DXIP_EXTERNAL_FLASH=1 -D__STARTUP_INITIALIZE_NONCACHEDATA -D__STARTUP_CLEAR_BSS
+
+export ARCH = arm
+export MCU = cortex-m7
@@ -0,0 +1,309 @@
+/*
+ * Copyright 2017-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/**
+* @file board.h
+* @brief define imxrt1052-board init configure and start-up function
+* @version 1.0
+* @author AIIT XUOS Lab
+* @date 2021-05-28
+*/
+
+/*************************************************
+File name: board.h
+Description: define imxrt1052-board board init function and struct
+Others:
+History:
+1. Date: 2021-05-28
+Author: AIIT XUOS Lab
+Modification:
+1. define imxrt-board InitBoardHardware
+2. define imxrt-board heap struct
+*************************************************/
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "fsl_common.h"
+#include "fsl_gpio.h"
+#include "fsl_clock.h"
+#include "fsl_enet.h"
+#include "clock_config.h"
+#include <xizi.h>
+#include <arch_interrupt.h>
+
+extern int heap_start;
+extern int heap_end;
+#define HEAP_BEGIN          (&heap_start)
+#define HEAP_END            (&heap_end)
+
+#define HEAP_SIZE           ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN)
+
+void InitBoardHardware(void);
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "IMXRT1050-EVKB"
+
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
+#define BOARD_DEBUG_UART_INSTANCE 1U
+
+#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
+
+#define BOARD_UART_IRQ LPUART1_IRQn
+#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
+
+#ifndef BOARD_DEBUG_UART_BAUDRATE
+#define BOARD_DEBUG_UART_BAUDRATE (115200U)
+#endif /* BOARD_DEBUG_UART_BAUDRATE */
+
+/*! @brief The USER_LED used for board */
+#define LOGIC_LED_ON (0U)
+#define LOGIC_LED_OFF (1U)
+#ifndef BOARD_USER_LED_GPIO
+#define BOARD_USER_LED_GPIO GPIO1
+#endif
+#ifndef BOARD_USER_LED_GPIO_PIN
+#define BOARD_USER_LED_GPIO_PIN (9U)
+#endif
+
+#define USER_LED_INIT(output)                                            \
+    GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
+    BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
+#define USER_LED_ON() \
+    GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN)                  /*!< Turn off target USER_LED */
+#define USER_LED_OFF() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!<Turn on target USER_LED*/
+#define USER_LED_TOGGLE()                                       \
+    GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, \
+                  0x1 ^ GPIO_PinRead(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN)) /*!< Toggle target USER_LED */
+
+/*! @brief Define the port interrupt number for the board switches */
+#ifndef BOARD_USER_BUTTON_GPIO
+#define BOARD_USER_BUTTON_GPIO GPIO5
+#endif
+#ifndef BOARD_USER_BUTTON_GPIO_PIN
+#define BOARD_USER_BUTTON_GPIO_PIN (0U)
+#endif
+#define BOARD_USER_BUTTON_IRQ GPIO5_Combined_0_15_IRQn
+#define BOARD_USER_BUTTON_IRQ_HANDLER GPIO5_Combined_0_15_IRQHandler
+#define BOARD_USER_BUTTON_NAME "SW8"
+
+/*! @brief The hyper flash size */
+#define BOARD_FLASH_SIZE (0x4000000U)
+
+/*! @brief The ENET PHY address. */
+#define BOARD_ENET0_PHY_ADDRESS (0x02U) /* Phy address of enet port 0. */
+
+/* USB PHY condfiguration */
+#define BOARD_USB_PHY_D_CAL (0x0CU)
+#define BOARD_USB_PHY_TXCAL45DP (0x06U)
+#define BOARD_USB_PHY_TXCAL45DM (0x06U)
+
+#define BOARD_ARDUINO_INT_IRQ (GPIO1_INT3_IRQn)
+#define BOARD_ARDUINO_I2C_IRQ (LPI2C1_IRQn)
+#define BOARD_ARDUINO_I2C_INDEX (1)
+#define BOARD_USDHC1_BASEADDR USDHC1
+#define BOARD_USDHC2_BASEADDR USDHC2
+#define BOARD_USDHC_CD_GPIO_BASE GPIO2
+#define BOARD_USDHC_CD_GPIO_PIN 28
+#define BOARD_USDHC_CD_PORT_IRQ GPIO2_Combined_16_31_IRQn
+#define BOARD_USDHC_CD_PORT_IRQ_HANDLER GPIO2_Combined_16_31_IRQHandler
+
+#define BOARD_USDHC_CD_STATUS() (GPIO_PinRead(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN))
+
+#define BOARD_USDHC_CD_INTERRUPT_STATUS() (GPIO_PortGetInterruptFlags(BOARD_USDHC_CD_GPIO_BASE))
+#define BOARD_USDHC_CD_CLEAR_INTERRUPT(flag) (GPIO_PortClearInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, flag))
+
+#define BOARD_USDHC_CD_GPIO_INIT()                                                          \
+    {                                                                                       \
+        gpio_pin_config_t sw_config = {                                                     \
+            kGPIO_DigitalInput,                                                             \
+            0,                                                                              \
+            kGPIO_IntRisingOrFallingEdge,                                                   \
+        };                                                                                  \
+        GPIO_PinInit(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN, &sw_config);        \
+        GPIO_PortEnableInterrupts(BOARD_USDHC_CD_GPIO_BASE, 1U << BOARD_USDHC_CD_GPIO_PIN); \
+        GPIO_PortClearInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, ~0);                         \
+    }
+#define BOARD_HAS_SDCARD (1U)
+#define BOARD_SD_POWER_RESET_GPIO (GPIO1)
+#define BOARD_SD_POWER_RESET_GPIO_PIN (5U)
+
+#define BOARD_USDHC_CARD_INSERT_CD_LEVEL (0U)
+
+#define BOARD_USDHC_MMCCARD_POWER_CONTROL(state)
+
+#define BOARD_USDHC_MMCCARD_POWER_CONTROL_INIT()                                            \
+    {                                                                                       \
+        gpio_pin_config_t sw_config = {                                                     \
+            kGPIO_DigitalOutput,                                                            \
+            0,                                                                              \
+            kGPIO_NoIntmode,                                                                \
+        };                                                                                  \
+        GPIO_PinInit(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, &sw_config); \
+        GPIO_PinWrite(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, true);      \
+    }
+
+#define BOARD_USDHC_SDCARD_POWER_CONTROL_INIT()                                             \
+    {                                                                                       \
+        gpio_pin_config_t sw_config = {                                                     \
+            kGPIO_DigitalOutput,                                                            \
+            0,                                                                              \
+            kGPIO_NoIntmode,                                                                \
+        };                                                                                  \
+        GPIO_PinInit(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, &sw_config); \
+    }
+
+#define BOARD_USDHC_SDCARD_POWER_CONTROL(state) \
+    (GPIO_PinWrite(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, state))
+
+#define BOARD_USDHC1_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) / (CLOCK_GetDiv(kCLOCK_Usdhc1Div) + 1U))
+#define BOARD_USDHC2_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) / (CLOCK_GetDiv(kCLOCK_Usdhc2Div) + 1U))
+
+#define BOARD_SD_HOST_BASEADDR BOARD_USDHC1_BASEADDR
+#define BOARD_SD_HOST_CLK_FREQ BOARD_USDHC1_CLK_FREQ
+#define BOARD_SD_HOST_IRQ USDHC1_IRQn
+
+#define BOARD_MMC_HOST_BASEADDR BOARD_USDHC2_BASEADDR
+#define BOARD_MMC_HOST_CLK_FREQ BOARD_USDHC2_CLK_FREQ
+#define BOARD_MMC_HOST_IRQ USDHC2_IRQn
+#define BOARD_MMC_VCCQ_SUPPLY kMMC_VoltageWindow170to195
+#define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360
+/* we are using the BB SD socket to DEMO the MMC example,but the
+ * SD socket provide 4bit bus only, so we define this macro to avoid
+ * 8bit data bus test
+ */
+#define BOARD_MMC_SUPPORT_8BIT_BUS (1U)
+
+#define BOARD_SD_HOST_SUPPORT_SDR104_FREQ (200000000U)
+#define BOARD_SD_HOST_SUPPORT_HS200_FREQ (180000000U)
+
+/*! @brief The WIFI-QCA shield pin. */
+#define BOARD_INITGT202SHIELD_PWRON_GPIO GPIO1                    /*!< GPIO device name: GPIO */
+#define BOARD_INITGT202SHIELD_PWRON_PORT 1U                       /*!< PORT device index: 1 */
+#define BOARD_INITGT202SHIELD_PWRON_GPIO_PIN 3U                   /*!< PIO4 pin index: 3 */
+#define BOARD_INITGT202SHIELD_PWRON_PIN_NAME GPIO1_3              /*!< Pin name */
+#define BOARD_INITGT202SHIELD_PWRON_LABEL "PWRON"                 /*!< Label */
+#define BOARD_INITGT202SHIELD_PWRON_NAME "PWRON"                  /*!< Identifier name */
+#define BOARD_INITGT202SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
+
+#define BOARD_INITGT202SHIELD_IRQ_GPIO GPIO1                   /*!< GPIO device name: GPIO */
+#define BOARD_INITGT202SHIELD_IRQ_PORT 1U                      /*!< PORT device index: 1 */
+#define BOARD_INITGT202SHIELD_IRQ_GPIO_PIN 19U                 /*!< PIO1 pin index: 19 */
+#define BOARD_INITGT202SHIELD_IRQ_PIN_NAME GPIO1_19            /*!< Pin name */
+#define BOARD_INITGT202SHIELD_IRQ_LABEL "IRQ"                  /*!< Label */
+#define BOARD_INITGT202SHIELD_IRQ_NAME "IRQ"                   /*!< Identifier name */
+#define BOARD_INITGT202SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
+
+/*! @brief The WIFI-QCA Silex 2401 shield pin. */
+#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO GPIO1                    /*!< GPIO device name: GPIO */
+#define BOARD_INITSILEX2401SHIELD_PWRON_PORT 1U                       /*!< PORT device index: 1 */
+#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO_PIN 9U                   /*!< PIO4 pin index: 9 */
+#define BOARD_INITSILEX2401SHIELD_PWRON_PIN_NAME GPIO1_9              /*!< Pin name */
+#define BOARD_INITSILEX2401SHIELD_PWRON_LABEL "PWRON"                 /*!< Label */
+#define BOARD_INITSILEX2401SHIELD_PWRON_NAME "PWRON"                  /*!< Identifier name */
+#define BOARD_INITSILEX2401SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
+
+#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO GPIO1                   /*!< GPIO device name: GPIO */
+#define BOARD_INITSILEX2401SHIELD_IRQ_PORT 1U                      /*!< PORT device index: 1 */
+#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO_PIN 11U                 /*!< PIO1 pin index: 11 */
+#define BOARD_INITSILEX2401SHIELD_IRQ_PIN_NAME GPIO1_11            /*!< Pin name */
+#define BOARD_INITSILEX2401SHIELD_IRQ_LABEL "IRQ"                  /*!< Label */
+#define BOARD_INITSILEX2401SHIELD_IRQ_NAME "IRQ"                   /*!< Identifier name */
+#define BOARD_INITSILEX2401SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
+
+/* @Brief Board accelerator sensor configuration */
+#define BOARD_ACCEL_I2C_BASEADDR LPI2C1
+/* Select USB1 PLL (480 MHz) as LPI2C's clock source */
+#define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U)
+/* Clock divider for LPI2C clock source */
+#define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U)
+#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U))
+
+#define BOARD_CODEC_I2C_BASEADDR LPI2C1
+#define BOARD_CODEC_I2C_INSTANCE 1U
+#define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U)
+#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U)
+#define BOARD_CODEC_I2C_CLOCK_FREQ (10000000U)
+
+/* @Brief Board CAMERA configuration */
+#define BOARD_CAMERA_I2C_BASEADDR LPI2C1
+#define BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER (5U)
+#define BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT (0U) /* Select USB1 PLL (480 MHz) as LPI2C's clock source */
+#define BOARD_CAMERA_I2C_CLOCK_FREQ \
+    (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER + 1U))
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+uint32_t BOARD_DebugConsoleSrcFreq(void);
+
+void BOARD_InitDebugConsole(void);
+
+void BOARD_ConfigMPU(void);
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
+status_t BOARD_LPI2C_Send(LPI2C_Type *base,
+                          uint8_t deviceAddress,
+                          uint32_t subAddress,
+                          uint8_t subaddressSize,
+                          uint8_t *txBuff,
+                          uint8_t txBuffSize);
+status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
+                             uint8_t deviceAddress,
+                             uint32_t subAddress,
+                             uint8_t subaddressSize,
+                             uint8_t *rxBuff,
+                             uint8_t rxBuffSize);
+status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
+                              uint8_t deviceAddress,
+                              uint32_t subAddress,
+                              uint8_t subaddressSize,
+                              uint8_t *txBuff,
+                              uint8_t txBuffSize);
+status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
+                                 uint8_t deviceAddress,
+                                 uint32_t subAddress,
+                                 uint8_t subaddressSize,
+                                 uint8_t *rxBuff,
+                                 uint8_t rxBuffSize);
+void BOARD_Accel_I2C_Init(void);
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
+status_t BOARD_Accel_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+void BOARD_Codec_I2C_Init(void);
+status_t BOARD_Codec_I2C_Send(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
+status_t BOARD_Codec_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+void BOARD_Camera_I2C_Init(void);
+status_t BOARD_Camera_I2C_Send(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
+status_t BOARD_Camera_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+
+status_t BOARD_Camera_I2C_SendSCCB(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
+status_t BOARD_Camera_I2C_ReceiveSCCB(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength);
+void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
@@ -0,0 +1,81 @@
+/*
+ * Copyright 2017-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/**
+* @file clock_config.h
+* @brief define imxrt1052-board clock configure
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-05-29
+*/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             600000000U  /*!< Core clock frequency: 600000000Hz */
+
+/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
+
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2017-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/**
+* @file pin_mux.h
+* @brief define imxrt1052-board pin configure
+* @version 1.0
+* @author AIIT XUOS Lab
+* @date 2021-05-29
+*/
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*! @brief Direction type  */
+typedef enum _pin_mux_direction
+{
+  kPIN_MUX_DirectionInput = 0U,         /* Input direction */
+  kPIN_MUX_DirectionOutput = 1U,        /* Output direction */
+  kPIN_MUX_DirectionInputOrOutput = 2U  /* Input or output direction */
+} pin_mux_direction_t;
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/* GPIO_AD_B0_13 (coord L14), UART1_RXD */
+#define BOARD_INITPINS_UART1_RXD_PERIPHERAL                              LPUART1   /*!< Device name: LPUART1 */
+#define BOARD_INITPINS_UART1_RXD_SIGNAL                                       RX   /*!< LPUART1 signal: RX */
+
+/* GPIO_AD_B0_12 (coord K14), UART1_TXD */
+#define BOARD_INITPINS_UART1_TXD_PERIPHERAL                              LPUART1   /*!< Device name: LPUART1 */
+#define BOARD_INITPINS_UART1_TXD_SIGNAL                                       TX   /*!< LPUART1 signal: TX */
+
+/* GPIO_AD_B0_09 (coord F14), BSP_LED */
+#define BOARD_INITPINS_BSP_LED_GPIO                                        GPIO1   /*!< GPIO device name: GPIO1 */
+#define BOARD_INITPINS_BSP_LED_PORT                                        GPIO1   /*!< PORT device name: GPIO1 */
+#define BOARD_INITPINS_BSP_LED_PIN                                            9U   /*!< GPIO1 pin index: 9 */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+void BOARD_InitI2C1Pins(void);
+void BOARD_InitSPIPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
@@ -0,0 +1,248 @@
+/*
+** ###################################################################
+**     Processors:          MIMXRT1052CVJ5B
+**                          MIMXRT1052CVL5B
+**                          MIMXRT1052DVJ6B
+**                          MIMXRT1052DVL6B
+**
+**     Compiler:            GNU C Compiler
+**     Reference manual:    IMXRT1050RM Rev.1, 03/2018
+**     Version:             rev. 1.0, 2018-09-21
+**     Build:               b180921
+**
+**     Abstract:
+**         Linker file for the GNU C Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2018 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+
+/**
+* @file link.lds
+* @brief xidatong Linker script
+* @version 1.0
+* @author AIIT XUOS Lab
+* @date 2021-05-28
+*/
+
+/*************************************************
+File name: link.lds
+Description: xidatong Linker script
+Others: take MIMXRT1052xxxxx_flexspi_nor.ld for references
+History:
+1. Date: 2021-05-28
+Author: AIIT XUOS Lab
+Modification:
+1. add shell cmd table and g_service_table
+*************************************************/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_interrupts          (RX)  : ORIGIN = 0x60002000, LENGTH = 0x00000400
+  m_text                (RX)  : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00
+  m_data                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00020000
+  m_data2               (RW)  : ORIGIN = 0x20200000, LENGTH = 0x00060000
+}
+
+/* Define output sections */
+SECTIONS
+{
+
+  /* The startup code goes first into internal RAM */
+  .interrupts :
+  {
+    __VECTOR_TABLE = .;
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))     /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+
+  __VECTOR_RAM = __VECTOR_TABLE;
+  __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;
+
+  /* The program code and other data goes into internal RAM */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)                 /* .text sections (code) */
+    *(.text*)                /* .text* sections (code) */
+    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)               /* glue arm to thumb code */
+    *(.glue_7t)              /* glue thumb to arm code */
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+
+
+    /* section information for  shell */
+        . = ALIGN(4);
+        _shell_command_start = .;
+        KEEP (*(shellCommand))
+        _shell_command_end = .;
+        . = ALIGN(4);
+
+        __isrtbl_idx_start = .;
+        KEEP(*(.isrtbl.idx))
+        __isrtbl_start = .;
+        KEEP(*(.isrtbl))
+        __isrtbl_end = .;
+        . = ALIGN(4);
+
+        PROVIDE(g_service_table_start = ABSOLUTE(.));
+        KEEP(*(.g_service_table))
+        PROVIDE(g_service_table_end = ABSOLUTE(.));
+  } > m_text
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > m_text
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } > m_text
+
+ .ctors :
+  {
+    __CTOR_LIST__ = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __CTOR_END__ = .;
+  } > m_text
+
+  .dtors :
+  {
+    __DTOR_LIST__ = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    __DTOR_END__ = .;
+  } > m_text
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > m_text
+
+  __etext = .;    /* define a global symbol at end of code */
+  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+  .data : AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    __DATA_RAM = .;
+    __data_start__ = .;      /* create a global symbol at data start */
+    *(.data)                 /* .data sections */
+    *(.data*)                /* .data* sections */
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);
+  .ncache.init : AT(__NDATA_ROM)
+  {
+    __noncachedata_start__ = .;   /* create a global symbol at ncache data start */
+    *(NonCacheable.init)
+    . = ALIGN(4);
+    __noncachedata_init_end__ = .;   /* create a global symbol at initialized ncache data end */
+  } > m_data
+  . = __noncachedata_init_end__;
+  .ncache :
+  {
+    *(NonCacheable)
+    . = ALIGN(4);
+    __noncachedata_end__ = .;     /* define a global symbol at ncache data end */
+  } > m_data
+
+  __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
+  text_end = ORIGIN(m_text) + LENGTH(m_text);
+  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+  /* Uninitialized data section */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    . = ALIGN(4);
+    __START_BSS = .;
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+    __END_BSS = .;
+  } > m_data
+
+  .stack :
+  {
+    . = ALIGN(8);
+    stack_start = .;
+    . += STACK_SIZE;
+    stack_end = .;
+    __StackTop = .;
+    heap_start = .;
+  } > m_data
+
+  PROVIDE(heap_end = ORIGIN(m_data) + LENGTH(m_data));
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+
@@ -0,0 +1,248 @@
+/*
+** ###################################################################
+**     Processors:          MIMXRT1052CVJ5B
+**                          MIMXRT1052CVL5B
+**                          MIMXRT1052DVJ6B
+**                          MIMXRT1052DVL6B
+**
+**     Compiler:            GNU C Compiler
+**     Reference manual:    IMXRT1050RM Rev.1, 03/2018
+**     Version:             rev. 1.0, 2018-09-21
+**     Build:               b180921
+**
+**     Abstract:
+**         Linker file for the GNU C Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2018 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+
+/**
+* @file link.lds
+* @brief xidatong Linker script
+* @version 1.0
+* @author AIIT XUOS Lab
+* @date 2021-05-28
+*/
+
+/*************************************************
+File name: link.lds
+Description: xidatong Linker script
+Others: take MIMXRT1052xxxxx_flexspi_nor.ld for references
+History:
+1. Date: 2021-05-28
+Author: AIIT XUOS Lab
+Modification:
+1. add shell cmd table and g_service_table
+*************************************************/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_interrupts          (RX)  : ORIGIN = 0x60002000, LENGTH = 0x00000400
+  m_text                (RX)  : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00
+  m_data                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00020000
+  m_data2               (RW)  : ORIGIN = 0x20200000, LENGTH = 0x00060000
+}
+
+/* Define output sections */
+SECTIONS
+{
+
+  /* The startup code goes first into internal RAM */
+  .interrupts :
+  {
+    __VECTOR_TABLE = .;
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))     /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+
+  __VECTOR_RAM = __VECTOR_TABLE;
+  __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;
+
+  /* The program code and other data goes into internal RAM */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)                 /* .text sections (code) */
+    *(.text*)                /* .text* sections (code) */
+    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)               /* glue arm to thumb code */
+    *(.glue_7t)              /* glue thumb to arm code */
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+
+
+    /* section information for  shell */
+        . = ALIGN(4);
+        _shell_command_start = .;
+        KEEP (*(shellCommand))
+        _shell_command_end = .;
+        . = ALIGN(4);
+
+        __isrtbl_idx_start = .;
+        KEEP(*(.isrtbl.idx))
+        __isrtbl_start = .;
+        KEEP(*(.isrtbl))
+        __isrtbl_end = .;
+        . = ALIGN(4);
+
+        PROVIDE(g_service_table_start = ABSOLUTE(.));
+        KEEP(*(.g_service_table))
+        PROVIDE(g_service_table_end = ABSOLUTE(.));
+  } > m_text
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > m_text
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } > m_text
+
+ .ctors :
+  {
+    __CTOR_LIST__ = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __CTOR_END__ = .;
+  } > m_text
+
+  .dtors :
+  {
+    __DTOR_LIST__ = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    __DTOR_END__ = .;
+  } > m_text
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > m_text
+
+  __etext = .;    /* define a global symbol at end of code */
+  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+  .data : AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    __DATA_RAM = .;
+    __data_start__ = .;      /* create a global symbol at data start */
+    *(.data)                 /* .data sections */
+    *(.data*)                /* .data* sections */
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);
+  .ncache.init : AT(__NDATA_ROM)
+  {
+    __noncachedata_start__ = .;   /* create a global symbol at ncache data start */
+    *(NonCacheable.init)
+    . = ALIGN(4);
+    __noncachedata_init_end__ = .;   /* create a global symbol at initialized ncache data end */
+  } > m_data
+  . = __noncachedata_init_end__;
+  .ncache :
+  {
+    *(NonCacheable)
+    . = ALIGN(4);
+    __noncachedata_end__ = .;     /* define a global symbol at ncache data end */
+  } > m_data
+
+  __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
+  text_end = ORIGIN(m_text) + LENGTH(m_text);
+  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+  /* Uninitialized data section */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    . = ALIGN(4);
+    __START_BSS = .;
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+    __END_BSS = .;
+  } > m_data
+
+  .stack :
+  {
+    . = ALIGN(8);
+    stack_start = .;
+    . += STACK_SIZE;
+    stack_end = .;
+    __StackTop = .;
+    heap_start = .;
+  } > m_data2
+
+  PROVIDE(heap_end = ORIGIN(m_data2) + LENGTH(m_data2));
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+
@@ -0,0 +1,266 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif
@@ -0,0 +1,197 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U)
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U)
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U)
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U)
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U)
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U)
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU)
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU)
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU)
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU)
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU)
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU)
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U)
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U)
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U)
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U)
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U)
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U)
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U)
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U)
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U)
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U)
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU)
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU)
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU)
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU)
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU)
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU)
+
+#define ARM_MPU_AP_NONE 0U 
+#define ARM_MPU_AP_PRIV 1U
+#define ARM_MPU_AP_URO  2U
+#define ARM_MPU_AP_FULL 3U
+#define ARM_MPU_AP_PRO  5U
+#define ARM_MPU_AP_RO   6U
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ((((DisableExec     ) << MPU_RASR_XN_Pos)     & MPU_RASR_XN_Msk)     | \
+   (((AccessPermission) << MPU_RASR_AP_Pos)     & MPU_RASR_AP_Msk)     | \
+   (((TypeExtField    ) << MPU_RASR_TEX_Pos)    & MPU_RASR_TEX_Msk)    | \
+   (((IsShareable     ) << MPU_RASR_S_Pos)      & MPU_RASR_S_Msk)      | \
+   (((IsCacheable     ) << MPU_RASR_C_Pos)      & MPU_RASR_C_Msk)      | \
+   (((IsBufferable    ) << MPU_RASR_B_Pos)      & MPU_RASR_B_Msk)      | \
+   (((SubRegionDisable) << MPU_RASR_SRD_Pos)    & MPU_RASR_SRD_Msk)    | \
+   (((Size            ) << MPU_RASR_SIZE_Pos)   & MPU_RASR_SIZE_Msk)   | \
+   (MPU_RASR_ENABLE_Msk))
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
@@ -0,0 +1,201 @@
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+   1. Definitions.
+
+      "License" shall mean the terms and conditions for use, reproduction,
+      and distribution as defined by Sections 1 through 9 of this document.
+
+      "Licensor" shall mean the copyright owner or entity authorized by
+      the copyright owner that is granting the License.
+
+      "Legal Entity" shall mean the union of the acting entity and all
+      other entities that control, are controlled by, or are under common
+      control with that entity. For the purposes of this definition,
+      "control" means (i) the power, direct or indirect, to cause the
+      direction or management of such entity, whether by contract or
+      otherwise, or (ii) ownership of fifty percent (50%) or more of the
+      outstanding shares, or (iii) beneficial ownership of such entity.
+
+      "You" (or "Your") shall mean an individual or Legal Entity
+      exercising permissions granted by this License.
+
+      "Source" form shall mean the preferred form for making modifications,
+      including but not limited to software source code, documentation
+      source, and configuration files.
+
+      "Object" form shall mean any form resulting from mechanical
+      transformation or translation of a Source form, including but
+      not limited to compiled object code, generated documentation,
+      and conversions to other media types.
+
+      "Work" shall mean the work of authorship, whether in Source or
+      Object form, made available under the License, as indicated by a
+      copyright notice that is included in or attached to the work
+      (an example is provided in the Appendix below).
+
+      "Derivative Works" shall mean any work, whether in Source or Object
+      form, that is based on (or derived from) the Work and for which the
+      editorial revisions, annotations, elaborations, or other modifications
+      represent, as a whole, an original work of authorship. For the purposes
+      of this License, Derivative Works shall not include works that remain
+      separable from, or merely link (or bind by name) to the interfaces of,
+      the Work and Derivative Works thereof.
+
+      "Contribution" shall mean any work of authorship, including
+      the original version of the Work and any modifications or additions
+      to that Work or Derivative Works thereof, that is intentionally
+      submitted to Licensor for inclusion in the Work by the copyright owner
+      or by an individual or Legal Entity authorized to submit on behalf of
+      the copyright owner. For the purposes of this definition, "submitted"
+      means any form of electronic, verbal, or written communication sent
+      to the Licensor or its representatives, including but not limited to
+      communication on electronic mailing lists, source code control systems,
+      and issue tracking systems that are managed by, or on behalf of, the
+      Licensor for the purpose of discussing and improving the Work, but
+      excluding communication that is conspicuously marked or otherwise
+      designated in writing by the copyright owner as "Not a Contribution."
+
+      "Contributor" shall mean Licensor and any individual or Legal Entity
+      on behalf of whom a Contribution has been received by Licensor and
+      subsequently incorporated within the Work.
+
+   2. Grant of Copyright License. Subject to the terms and conditions of
+      this License, each Contributor hereby grants to You a perpetual,
+      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+      copyright license to reproduce, prepare Derivative Works of,
+      publicly display, publicly perform, sublicense, and distribute the
+      Work and such Derivative Works in Source or Object form.
+
+   3. Grant of Patent License. Subject to the terms and conditions of
+      this License, each Contributor hereby grants to You a perpetual,
+      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+      (except as stated in this section) patent license to make, have made,
+      use, offer to sell, sell, import, and otherwise transfer the Work,
+      where such license applies only to those patent claims licensable
+      by such Contributor that are necessarily infringed by their
+      Contribution(s) alone or by combination of their Contribution(s)
+      with the Work to which such Contribution(s) was submitted. If You
+      institute patent litigation against any entity (including a
+      cross-claim or counterclaim in a lawsuit) alleging that the Work
+      or a Contribution incorporated within the Work constitutes direct
+      or contributory patent infringement, then any patent licenses
+      granted to You under this License for that Work shall terminate
+      as of the date such litigation is filed.
+
+   4. Redistribution. You may reproduce and distribute copies of the
+      Work or Derivative Works thereof in any medium, with or without
+      modifications, and in Source or Object form, provided that You
+      meet the following conditions:
+
+      (a) You must give any other recipients of the Work or
+          Derivative Works a copy of this License; and
+
+      (b) You must cause any modified files to carry prominent notices
+          stating that You changed the files; and
+
+      (c) You must retain, in the Source form of any Derivative Works
+          that You distribute, all copyright, patent, trademark, and
+          attribution notices from the Source form of the Work,
+          excluding those notices that do not pertain to any part of
+          the Derivative Works; and
+
+      (d) If the Work includes a "NOTICE" text file as part of its
+          distribution, then any Derivative Works that You distribute must
+          include a readable copy of the attribution notices contained
+          within such NOTICE file, excluding those notices that do not
+          pertain to any part of the Derivative Works, in at least one
+          of the following places: within a NOTICE text file distributed
+          as part of the Derivative Works; within the Source form or
+          documentation, if provided along with the Derivative Works; or,
+          within a display generated by the Derivative Works, if and
+          wherever such third-party notices normally appear. The contents
+          of the NOTICE file are for informational purposes only and
+          do not modify the License. You may add Your own attribution
+          notices within Derivative Works that You distribute, alongside
+          or as an addendum to the NOTICE text from the Work, provided
+          that such additional attribution notices cannot be construed
+          as modifying the License.
+
+      You may add Your own copyright statement to Your modifications and
+      may provide additional or different license terms and conditions
+      for use, reproduction, or distribution of Your modifications, or
+      for any such Derivative Works as a whole, provided Your use,
+      reproduction, and distribution of the Work otherwise complies with
+      the conditions stated in this License.
+
+   5. Submission of Contributions. Unless You explicitly state otherwise,
+      any Contribution intentionally submitted for inclusion in the Work
+      by You to the Licensor shall be under the terms and conditions of
+      this License, without any additional terms or conditions.
+      Notwithstanding the above, nothing herein shall supersede or modify
+      the terms of any separate license agreement you may have executed
+      with Licensor regarding such Contributions.
+
+   6. Trademarks. This License does not grant permission to use the trade
+      names, trademarks, service marks, or product names of the Licensor,
+      except as required for reasonable and customary use in describing the
+      origin of the Work and reproducing the content of the NOTICE file.
+
+   7. Disclaimer of Warranty. Unless required by applicable law or
+      agreed to in writing, Licensor provides the Work (and each
+      Contributor provides its Contributions) on an "AS IS" BASIS,
+      WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+      implied, including, without limitation, any warranties or conditions
+      of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
+      PARTICULAR PURPOSE. You are solely responsible for determining the
+      appropriateness of using or redistributing the Work and assume any
+      risks associated with Your exercise of permissions under this License.
+
+   8. Limitation of Liability. In no event and under no legal theory,
+      whether in tort (including negligence), contract, or otherwise,
+      unless required by applicable law (such as deliberate and grossly
+      negligent acts) or agreed to in writing, shall any Contributor be
+      liable to You for damages, including any direct, indirect, special,
+      incidental, or consequential damages of any character arising as a
+      result of this License or out of the use or inability to use the
+      Work (including but not limited to damages for loss of goodwill,
+      work stoppage, computer failure or malfunction, or any and all
+      other commercial damages or losses), even if such Contributor
+      has been advised of the possibility of such damages.
+
+   9. Accepting Warranty or Additional Liability. While redistributing
+      the Work or Derivative Works thereof, You may choose to offer,
+      and charge a fee for, acceptance of support, warranty, indemnity,
+      or other liability obligations and/or rights consistent with this
+      License. However, in accepting such obligations, You may act only
+      on Your own behalf and on Your sole responsibility, not on behalf
+      of any other Contributor, and only if You agree to indemnify,
+      defend, and hold each Contributor harmless for any liability
+      incurred by, or claims asserted against, such Contributor by reason
+      of your accepting any such warranty or additional liability.
+
+   END OF TERMS AND CONDITIONS
+
+   APPENDIX: How to apply the Apache License to your work.
+
+      To apply the Apache License to your work, attach the following
+      boilerplate notice, with the fields enclosed by brackets "{}"
+      replaced with your own identifying information. (Don't include
+      the brackets!)  The text should be enclosed in the appropriate
+      comment syntax for the file format. We also recommend that a
+      file or class name and description of purpose be included on the
+      same "printed page" as the copyright notice for easier
+      identification within third-party archives.
+
+   Copyright {yyyy} {name of copyright owner}
+
+   Licensed under the Apache License, Version 2.0 (the "License");
+   you may not use this file except in compliance with the License.
+   You may obtain a copy of the License at
+
+       http://www.apache.org/licenses/LICENSE-2.0
+
+   Unless required by applicable law or agreed to in writing, software
+   distributed under the License is distributed on an "AS IS" BASIS,
+   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+   See the License for the specific language governing permissions and
+   limitations under the License.
@@ -0,0 +1,32 @@
+menuconfig BSP_USING_LPUART
+    bool "Using UART device"
+    default y
+    select RESOURCES_SERIAL
+    if BSP_USING_LPUART
+        source "$BSP_DIR/third_party_driver/uart/Kconfig"
+    endif
+
+menuconfig BSP_USING_GPIO
+    bool "Using GPIO device "
+    default y
+    select RESOURCES_PIN
+
+    if BSP_USING_GPIO
+        source "$BSP_DIR/third_party_driver/gpio/Kconfig"
+    endif
+
+menuconfig BSP_USING_SDIO
+    bool "Using SD card device"
+    default n
+    select RESOURCES_SDIO
+    if BSP_USING_SDIO
+        source "$BSP_DIR/third_party_driver/sdio/Kconfig"
+    endif
+
+menuconfig BSP_USING_USB
+    bool "Using USB device"
+    default n
+    select RESOURCES_USB
+    if BSP_USING_USB
+        source "$BSP_DIR/third_party_driver/usb/Kconfig"
+    endif
@@ -0,0 +1,15 @@
+SRC_DIR := common gpio
+
+ifeq ($(CONFIG_BSP_USING_LPUART),y)
+  SRC_DIR += uart
+endif
+
+ifeq ($(CONFIG_BSP_USING_SDIO),y)
+  SRC_DIR += sdio
+endif
+
+ifeq ($(CONFIG_BSP_USING_USB),y)
+  SRC_DIR += usb
+endif
+
+include $(KERNEL_ROOT)/compiler.mk
@@ -0,0 +1,7 @@
+SRC_FILES := system_MIMXRT1052.c fsl_cache.c fsl_clock.c fsl_common.c pin_mux.c clock_config.c
+
+ifeq ($(CONFIG_BSP_USING_SDIO),y)
+  SRC_FILES += fsl_usdhc.c
+endif
+
+include $(KERNEL_ROOT)/compiler.mk
@@ -0,0 +1,479 @@
+/*
+ * Copyright 2017-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/**
+* @file clock_config.c
+* @brief support imxrt1052-board clock configure
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-05-29
+*/
+
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v5.0
+processor: MIMXRT1052xxxxB
+package_id: MIMXRT1052DVL6B
+mcu_data: ksdk2_0
+processor_version: 5.0.2
+board: IMXRT1050-EVKB
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
+- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
+- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
+- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
+- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 2880/11 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
+- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5/7 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
+settings:
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI_PODF.scale, value: '1', locked: true}
+- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.LCDIF_PODF.scale, value: '8', locked: true}
+- {id: CCM.LCDIF_PRED.scale, value: '7', locked: true}
+- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.SEMC_PODF.scale, value: '8'}
+- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
+- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
+- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL4.denom, value: '50'}
+- {id: CCM_ANALOG.PLL4.div, value: '47'}
+- {id: CCM_ANALOG.PLL5.denom, value: '1'}
+- {id: CCM_ANALOG.PLL5.div, value: '40'}
+- {id: CCM_ANALOG.PLL5.num, value: '0'}
+- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+sources:
+- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 100,                       /* PLL loop divider, Fout = Fin * 50 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 1,                         /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Init RTC OSC clock frequency. */
+    CLOCK_SetRtcXtalFreq(32768U);
+    /* Enable 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+    /* Use free 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+    /* Set XTAL 24MHz clock frequency. */
+    CLOCK_SetXtalFreq(24000000U);
+    /* Enable XTAL 24MHz clock source. */
+    CLOCK_InitExternalClk(0);
+    /* Enable internal RC. */
+    CLOCK_InitRcOsc24M();
+    /* Switch clock source to external OSC. */
+    CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+    /* Set Oscillator ready counter value. */
+    CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+    /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 1);     /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+    /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
+    DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
+    /* Waiting for DCDC_STS_DC_OK bit is asserted */
+    while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+    {
+    }
+    /* Set AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+    /* Disable IPG clock gate. */
+    CLOCK_DisableClock(kCLOCK_Adc1);
+    CLOCK_DisableClock(kCLOCK_Adc2);
+    CLOCK_DisableClock(kCLOCK_Xbar1);
+    CLOCK_DisableClock(kCLOCK_Xbar2);
+    CLOCK_DisableClock(kCLOCK_Xbar3);
+    /* Set IPG_PODF. */
+    CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+    /* Set ARM_PODF. */
+    CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
+    /* Set PERIPH_CLK2_PODF. */
+    CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+    /* Disable PERCLK clock gate. */
+    CLOCK_DisableClock(kCLOCK_Gpt1);
+    CLOCK_DisableClock(kCLOCK_Gpt1S);
+    CLOCK_DisableClock(kCLOCK_Gpt2);
+    CLOCK_DisableClock(kCLOCK_Gpt2S);
+    CLOCK_DisableClock(kCLOCK_Pit);
+    /* Set PERCLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+    /* Disable USDHC1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc1);
+    /* Set USDHC1_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
+    /* Set Usdhc1 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+    /* Disable USDHC2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc2);
+    /* Set USDHC2_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
+    /* Set Usdhc2 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+    /* Disable Semc clock gate. */
+    CLOCK_DisableClock(kCLOCK_Semc);
+    /* Set SEMC_PODF. */
+    CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+    /* Set Semc alt clock source. */
+    CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+    /* Set Semc clock source. */
+    CLOCK_SetMux(kCLOCK_SemcMux, 0);
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Disable Flexspi clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi);
+    /* Set FLEXSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0);
+    /* Set Flexspi clock source. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
+#endif
+    /* Disable CSI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Csi);
+    /* Set CSI_PODF. */
+    CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
+    /* Set Csi clock source. */
+    CLOCK_SetMux(kCLOCK_CsiMux, 0);
+    /* Disable LPSPI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpspi1);
+    CLOCK_DisableClock(kCLOCK_Lpspi2);
+    CLOCK_DisableClock(kCLOCK_Lpspi3);
+    CLOCK_DisableClock(kCLOCK_Lpspi4);
+    /* Set LPSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+    /* Set Lpspi clock source. */
+    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    /* Disable TRACE clock gate. */
+    CLOCK_DisableClock(kCLOCK_Trace);
+    /* Set TRACE_PODF. */
+    CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
+    /* Set Trace clock source. */
+    CLOCK_SetMux(kCLOCK_TraceMux, 2);
+    /* Disable SAI1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai1);
+    /* Set SAI1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+    /* Set SAI1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+    /* Set Sai1 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+    /* Disable SAI2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai2);
+    /* Set SAI2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+    /* Set SAI2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+    /* Set Sai2 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+    /* Disable SAI3 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai3);
+    /* Set SAI3_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+    /* Set SAI3_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+    /* Set Sai3 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+    /* Disable Lpi2c clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpi2c1);
+    CLOCK_DisableClock(kCLOCK_Lpi2c2);
+    CLOCK_DisableClock(kCLOCK_Lpi2c3);
+    /* Set LPI2C_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+    /* Set Lpi2c clock source. */
+    CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+    /* Disable CAN clock gate. */
+    CLOCK_DisableClock(kCLOCK_Can1);
+    CLOCK_DisableClock(kCLOCK_Can2);
+    CLOCK_DisableClock(kCLOCK_Can1S);
+    CLOCK_DisableClock(kCLOCK_Can2S);
+    /* Set CAN_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+    /* Set Can clock source. */
+    CLOCK_SetMux(kCLOCK_CanMux, 2);
+    /* Disable UART clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpuart1);
+    CLOCK_DisableClock(kCLOCK_Lpuart2);
+    CLOCK_DisableClock(kCLOCK_Lpuart3);
+    CLOCK_DisableClock(kCLOCK_Lpuart4);
+    CLOCK_DisableClock(kCLOCK_Lpuart5);
+    CLOCK_DisableClock(kCLOCK_Lpuart6);
+    CLOCK_DisableClock(kCLOCK_Lpuart7);
+    CLOCK_DisableClock(kCLOCK_Lpuart8);
+    /* Set UART_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+    /* Set Uart clock source. */
+    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    /* Disable LCDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_LcdPixel);
+    /* Set LCDIF_PRED. */
+    CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 6);
+    /* Set LCDIF_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_LcdifDiv, 7);
+    /* Set Lcdif pre clock source. */
+    CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
+    /* Disable SPDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_Spdif);
+    /* Set SPDIF0_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+    /* Set SPDIF0_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+    /* Set Spdif clock source. */
+    CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+    /* Disable Flexio1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio1);
+    /* Set FLEXIO1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+    /* Set FLEXIO1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+    /* Set Flexio1 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+    /* Disable Flexio2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio2);
+    /* Set FLEXIO2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
+    /* Set FLEXIO2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
+    /* Set Flexio2 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
+    /* Set Pll3 sw clock source. */
+    CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+    /* Init ARM PLL. */
+    CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+    /* Init System PLL. */
+    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
+    /* Disable pfd offset. */
+    CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK;
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Init Usb1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
+    /* Disable Usb1 PLL output for USBPHY1. */
+    CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
+#endif
+    /* DeInit Audio PLL. */
+    CLOCK_DeinitAudioPll();
+    /* Bypass Audio PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+    /* Set divider for Audio PLL. */
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+    /* Enable Audio PLL output. */
+    CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    /* DeInit Video PLL. */
+    CLOCK_DeinitVideoPll();
+    /* Bypass Video PLL. */
+    CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
+    /* Set divider for Video PLL. */
+    CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0);
+    /* Enable Video PLL output. */
+    CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+    /* DeInit Enet PLL. */
+    CLOCK_DeinitEnetPll();
+    /* Bypass Enet PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
+    /* Set Enet output divider. */
+    CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
+    /* Enable Enet output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
+    /* Enable Enet25M output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
+    /* DeInit Usb2 PLL. */
+    CLOCK_DeinitUsb2Pll();
+    /* Bypass Usb2 PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
+    /* Enable Usb2 PLL output. */
+    CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
+    /* Set preperiph clock source. */
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+    /* Set periph clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+    /* Set periph clock2 clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set per clock source. */
+    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    /* Set lvds1 clock source. */
+    CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
+    /* Set clock out1 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+    /* Set clock out1 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+    /* Set clock out2 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+    /* Set clock out2 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+    /* Set clock out1 drives clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+    /* Disable clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+    /* Disable clock out2. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI2 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set ENET Tx clock source. */
+    IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
+
@@ -0,0 +1,611 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/**
+ * @file fsl_cache.c
+ * @brief cache drivers
+ * @version 1.0
+ * @author AIIT XUOS Lab
+ * @date 2021.11.11
+ */
+
+#include "fsl_cache.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.cache_armv7_m7"
+#endif
+
+#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
+#define L2CACHE_OPERATION_TIMEOUT 0xFFFFFU
+#define L2CACHE_8WAYS_MASK 0xFFU
+#define L2CACHE_16WAYS_MASK 0xFFFFU
+#define L2CACHE_SMALLWAYS_NUM 8U
+#define L2CACHE_1KBCOVERTOB 1024U
+#define L2CACHE_SAMLLWAYS_SIZE 16U
+#define L2CACHE_LOCKDOWN_REGNUM 8 /*!< Lock down register numbers.*/
+/*******************************************************************************
+* Prototypes
+******************************************************************************/
+/*!
+ * @brief Set for all ways and waiting for the operation finished.
+ *  This is provided for all the background operations.
+ *
+ * @param auxCtlReg  The auxiliary control register.
+ * @param regAddr The register address to be operated.
+ */
+static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t regAddr);
+
+/*!
+ * @brief Invalidates the Level 2 cache line by physical address.
+ * This function invalidates a cache line by physcial address.
+ *
+ * @param address  The physical addderss of the cache.
+ *        The format of the address shall be :
+ *        bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0
+ *              Tag        |    index    |      0
+ *  Note: the physical address shall be aligned to the line size - 32B (256 bit).
+ *  so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero.
+ *  If the input address is not aligned, it will be changed to 32-byte aligned address.
+ *  The n is varies according to the index width.
+ * @return The actual 32-byte aligned physical address be operated.
+ */
+static uint32_t L2CACHE_InvalidateLineByAddr(uint32_t address);
+
+/*!
+ * @brief Cleans the Level 2 cache line based on the physical address.
+ * This function cleans a cache line based on a physcial address.
+ *
+ * @param address  The physical addderss of the cache.
+ *        The format of the address shall be :
+ *        bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0
+ *              Tag        |    index    |      0
+ *  Note: the physical address shall be aligned to the line size - 32B (256 bit).
+ *  so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero.
+ *  If the input address is not aligned, it will be changed to 32-byte aligned address.
+ *  The n is varies according to the index width.
+ * @return The actual 32-byte aligned physical address be operated.
+ */
+static uint32_t L2CACHE_CleanLineByAddr(uint32_t address);
+
+/*!
+ * @brief Cleans and invalidates the Level 2 cache line based on the physical address.
+ * This function cleans and invalidates a cache line based on a physcial address.
+ *
+ * @param address  The physical addderss of the cache.
+ *        The format of the address shall be :
+ *        bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0
+ *              Tag        |    index    |      0
+ *  Note: the physical address shall be aligned to the line size - 32B (256 bit).
+ *  so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero.
+ *  If the input address is not aligned, it will be changed to 32-byte aligned address.
+ *  The n is varies according to the index width.
+ * @return The actual 32-byte aligned physical address be operated.
+ */
+static uint32_t L2CACHE_CleanInvalidateLineByAddr(uint32_t address);
+
+/*!
+ * @brief Gets the number of the Level 2 cache and the way size.
+ * This function cleans and invalidates a cache line based on a physcial address.
+ *
+ * @param num_ways  The number of the cache way.
+ * @param size_way  The way size.
+ */
+static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way);
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t regAddr)
+{
+    uint16_t mask    = L2CACHE_8WAYS_MASK;
+    uint32_t timeout = L2CACHE_OPERATION_TIMEOUT;
+
+    /* Check the ways used at first. */
+    if (auxCtlReg & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK)
+    {
+        mask = L2CACHE_16WAYS_MASK;
+    }
+
+    /* Set the opeartion for all ways/entries of the cache. */
+    *(uint32_t *)regAddr = mask;
+    /* Waiting for until the operation is complete. */
+    while ((*(volatile uint32_t *)regAddr & mask) && timeout)
+    {
+        __ASM("nop");
+        timeout--;
+    }
+}
+
+static uint32_t L2CACHE_InvalidateLineByAddr(uint32_t address)
+{
+    /* Align the address first. */
+    address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1);
+    /* Invalidate the cache line by physical address. */
+    L2CACHEC->REG7_INV_PA = address;
+
+    return address;
+}
+
+static uint32_t L2CACHE_CleanLineByAddr(uint32_t address)
+{
+    /* Align the address first. */
+    address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1);
+    /* Invalidate the cache line by physical address. */
+    L2CACHEC->REG7_CLEAN_PA = address;
+
+    return address;
+}
+
+static uint32_t L2CACHE_CleanInvalidateLineByAddr(uint32_t address)
+{
+    /* Align the address first. */
+    address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1);
+    /* Clean and invalidate the cache line by physical address. */
+    L2CACHEC->REG7_CLEAN_INV_PA = address;
+
+    return address;
+}
+
+static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way)
+{
+    assert(num_ways);
+    assert(size_way);
+
+    uint32_t number = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
+                      L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT;
+    uint32_t size = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_MASK) >>
+                    L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_SHIFT;
+
+    *num_ways = (number + 1) * L2CACHE_SMALLWAYS_NUM;
+    if (!size)
+    {
+        /* 0 internally mapped to the same size as 1 - 16KB.*/
+        size += 1;
+    }
+    *size_way = (1 << (size - 1)) * L2CACHE_SAMLLWAYS_SIZE * L2CACHE_1KBCOVERTOB;
+}
+
+/*!
+ * brief Initializes the level 2 cache controller module.
+ *
+ * param config Pointer to configuration structure. See "l2cache_config_t".
+ */
+void L2CACHE_Init(l2cache_config_t *config)
+{
+    assert(config);
+
+    uint16_t waysNum = 0xFFU; /* Default use the 8-way mask. */
+    uint8_t count;
+    uint32_t auxReg = 0;
+
+    /*The aux register must be configured when the cachec is disabled
+     * So disable first if the cache controller is enabled.
+     */
+    if (L2CACHEC->REG1_CONTROL & L2CACHEC_REG1_CONTROL_CE_MASK)
+    {
+        L2CACHE_Disable();
+    }
+
+    /* Unlock all entries. */
+    if (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK)
+    {
+        waysNum = 0xFFFFU;
+    }
+
+    for (count = 0; count < L2CACHE_LOCKDOWN_REGNUM; count++)
+    {
+        L2CACHE_LockdownByWayEnable(count, waysNum, false);
+    }
+
+    /* Set the ways and way-size etc. */
+    auxReg = L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY(config->wayNum) |
+             L2CACHEC_REG1_AUX_CONTROL_WAYSIZE(config->waySize) | L2CACHEC_REG1_AUX_CONTROL_CRP(config->repacePolicy) |
+             L2CACHEC_REG1_AUX_CONTROL_IPE(config->istrPrefetchEnable) |
+             L2CACHEC_REG1_AUX_CONTROL_DPE(config->dataPrefetchEnable) |
+             L2CACHEC_REG1_AUX_CONTROL_NLE(config->nsLockdownEnable) |
+             L2CACHEC_REG1_AUX_CONTROL_FWA(config->writeAlloc) | L2CACHEC_REG1_AUX_CONTROL_HPSDRE(config->writeAlloc);
+    L2CACHEC->REG1_AUX_CONTROL = auxReg;
+
+    /* Set the tag/data ram latency. */
+    if (config->lateConfig)
+    {
+        uint32_t data = 0;
+        /* Tag latency. */
+        data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) |
+               L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) |
+               L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate) |
+               L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
+        L2CACHEC->REG1_TAG_RAM_CONTROL = data;
+        /* Data latency. */
+        data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) |
+               L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) |
+               L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate) |
+               L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
+        L2CACHEC->REG1_DATA_RAM_CONTROL = data;
+    }
+}
+
+/*!
+ * brief Gets an available default settings for the cache controller.
+ *
+ * This function initializes the cache controller configuration structure with default settings.
+ * The default values are:
+ * code
+ *   config->waysNum = kL2CACHE_8ways;
+ *   config->waySize = kL2CACHE_32KbSize;
+ *   config->repacePolicy = kL2CACHE_Roundrobin;
+ *   config->lateConfig = NULL;
+ *   config->istrPrefetchEnable = false;
+ *   config->dataPrefetchEnable = false;
+ *   config->nsLockdownEnable = false;
+ *   config->writeAlloc = kL2CACHE_UseAwcache;
+ * endcode
+ * param config Pointer to the configuration structure.
+ */
+void L2CACHE_GetDefaultConfig(l2cache_config_t *config)
+{
+    assert(config);
+
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
+    uint32_t number = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
+                      L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT;
+    uint32_t size = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_MASK) >>
+                    L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_SHIFT;
+
+    /* Get the default value */
+    config->wayNum             = (l2cache_way_num_t)number;
+    config->waySize            = (l2cache_way_size)size;
+    config->repacePolicy       = kL2CACHE_Roundrobin;
+    config->lateConfig         = NULL;
+    config->istrPrefetchEnable = false;
+    config->dataPrefetchEnable = false;
+    config->nsLockdownEnable   = false;
+    config->writeAlloc         = kL2CACHE_UseAwcache;
+}
+
+/*!
+ * brief Enables the level 2 cache controller.
+ * This function enables the cache controller. Must be written using a secure access.
+ * If write with a Non-secure access will cause a DECERR response.
+ *
+ */
+void L2CACHE_Enable(void)
+{
+    /* Invalidate first. */
+    L2CACHE_Invalidate();
+    /* Enable the level 2 cache controller. */
+    L2CACHEC->REG1_CONTROL = L2CACHEC_REG1_CONTROL_CE_MASK;
+}
+
+/*!
+ * brief Disables the level 2 cache controller.
+ * This function disables the cache controller. Must be written using a secure access.
+ * If write with a Non-secure access will cause a DECERR response.
+ *
+ */
+void L2CACHE_Disable(void)
+{
+    /* First CleanInvalidate all enties in the cache. */
+    L2CACHE_CleanInvalidate();
+    /* Disable the level 2 cache controller. */
+    L2CACHEC->REG1_CONTROL &= ~L2CACHEC_REG1_CONTROL_CE_MASK;
+    /* DSB - data sync barrier.*/
+    __DSB();
+}
+
+/*!
+ * brief Invalidates the Level 2 cache.
+ * This function invalidates all entries in cache.
+ *
+ */
+void L2CACHE_Invalidate(void)
+{
+    /* Invalidate all entries in cache. */
+    L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_INV_WAY);
+    /* Cache sync. */
+    L2CACHEC->REG7_CACHE_SYNC = 0;
+}
+
+/*!
+ * brief Cleans the level 2 cache controller.
+ * This function cleans all entries in the level 2 cache controller.
+ *
+ */
+void L2CACHE_Clean(void)
+{
+    /* Clean all entries of the cache. */
+    L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_CLEAN_WAY);
+    /* Cache sync. */
+    L2CACHEC->REG7_CACHE_SYNC = 0;
+}
+
+/*!
+ * brief Cleans and invalidates the level 2 cache controller.
+ * This function cleans and invalidates all entries in the level 2 cache controller.
+ *
+ */
+void L2CACHE_CleanInvalidate(void)
+{
+    /* Clean all entries of the cache. */
+    L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_CLEAN_INV_WAY);
+    /* Cache sync. */
+    L2CACHEC->REG7_CACHE_SYNC = 0;
+}
+
+/*!
+ * brief Invalidates the Level 2 cache lines in the range of two physical addresses.
+ * This function invalidates all cache lines between two physical addresses.
+ *
+ * param address  The start address of the memory to be invalidated.
+ * param size_byte  The memory size.
+ * note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
+ * The startAddr here will be forced to align to L2 line size if startAddr
+ * is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
+{
+    uint32_t endAddr = address + size_byte;
+
+    /* Invalidate addresses in the range. */
+    while (address < endAddr)
+    {
+        address = L2CACHE_InvalidateLineByAddr(address);
+        /* Update the size. */
+        address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE;
+    }
+
+    /* Cache sync. */
+    L2CACHEC->REG7_CACHE_SYNC = 0;
+}
+
+/*!
+ * brief Cleans the Level 2 cache lines in the range of two physical addresses.
+ * This function cleans all cache lines between two physical addresses.
+ *
+ * param address  The start address of the memory to be cleaned.
+ * param size_byte  The memory size.
+ * note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
+ * The startAddr here will be forced to align to L2 line size if startAddr
+ * is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte)
+{
+    uint32_t num_ways = 0;
+    uint32_t size_way = 0;
+    uint32_t endAddr  = address + size_byte;
+
+    /* Get the number and size of the cache way. */
+    L2CACHE_GetWayNumSize(&num_ways, &size_way);
+
+    /* Check if the clean size is over the cache size. */
+    if ((endAddr - address) > num_ways * size_way)
+    {
+        L2CACHE_Clean();
+        return;
+    }
+
+    /* Clean addresses in the range. */
+    while ((address & ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1)) < endAddr)
+    {
+        /* Clean the address in the range. */
+        address = L2CACHE_CleanLineByAddr(address);
+        address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE;
+    }
+
+    L2CACHEC->REG7_CACHE_SYNC = 0;
+}
+
+/*!
+ * brief Cleans and invalidates the Level 2 cache lines in the range of two physical addresses.
+ * This function cleans and invalidates all cache lines between two physical addresses.
+ *
+ * param address  The start address of the memory to be cleaned and invalidated.
+ * param size_byte  The memory size.
+ * note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
+ * The startAddr here will be forced to align to L2 line size if startAddr
+ * is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
+{
+    uint32_t num_ways = 0;
+    uint32_t size_way = 0;
+    uint32_t endAddr  = address + size_byte;
+
+    /* Get the number and size of the cache way. */
+    L2CACHE_GetWayNumSize(&num_ways, &size_way);
+
+    /* Check if the clean size is over the cache size. */
+    if ((endAddr - address) > num_ways * size_way)
+    {
+        L2CACHE_CleanInvalidate();
+        return;
+    }
+
+    /* Clean addresses in the range. */
+    while ((address & ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1)) < endAddr)
+    {
+        /* Clean the address in the range. */
+        address = L2CACHE_CleanInvalidateLineByAddr(address);
+        address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE;
+    }
+
+    L2CACHEC->REG7_CACHE_SYNC = 0;
+}
+
+/*!
+ * brief Enables or disables to lock down the data and instruction by way.
+ * This function locks down the cached instruction/data by way and prevent the adresses from
+ * being allocated and prevent dara from being evicted out of the level 2 cache.
+ * But the normal cache maintenance operations that invalidate, clean or clean
+ * and validate cache contents affect the locked-down cache lines as normal.
+ *
+ * param masterId  The master id, range from 0 ~ 7.
+ * param mask  The ways to be enabled or disabled to lockdown.
+ *               each bit in value is related to each way of the cache. for example:
+ *               value: bit 0  ------ way 0.
+ *               value: bit 1  ------ way 1.
+ *               --------------------------
+ *               value: bit 15 ------ way 15.
+ * Note: please make sure the value setting is align with your supported ways.
+ * param enable  True enable the lockdown, false to disable the lockdown.
+ */
+void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable)
+{
+    uint8_t num_ways = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
+                       L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT;
+    num_ways = (num_ways + 1) * L2CACHE_SMALLWAYS_NUM;
+
+    assert(mask < (1U << num_ways));
+    assert(masterId < L2CACHE_LOCKDOWN_REGNUM);
+
+    uint32_t dataReg = L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN;
+    uint32_t istrReg = L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN;
+
+    if (enable)
+    {
+        /* Data lockdown. */
+        L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg | mask;
+        /* Instruction lockdown. */
+        L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg | mask;
+    }
+    else
+    {
+        /* Data lockdown. */
+        L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg & ~mask;
+        /* Instruction lockdown. */
+        L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask;
+    }
+}
+#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
+
+/*!
+ * brief Invalidate cortex-m7 L1 instruction cache by range.
+ *
+ * param address  The start address of the memory to be invalidated.
+ * param size_byte  The memory size.
+ * note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.
+ * The startAddr here will be forced to align to L1 I-cache line size if
+ * startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
+{
+#if (__DCACHE_PRESENT == 1U)
+    uint32_t addr     = address & (uint32_t) ~(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE - 1);
+    int32_t size      = size_byte + address - addr;
+    uint32_t linesize = 32U;
+
+    __DSB();
+    while (size > 0)
+    {
+        SCB->ICIMVAU = addr;
+        addr += linesize;
+        size -= linesize;
+    }
+    __DSB();
+    __ISB();
+#endif
+}
+
+/*!
+ * brief Invalidates all instruction caches by range.
+ *
+ * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
+ *
+ * param address The physical address.
+ * param size_byte size of the memory to be invalidated.
+ * note address and size should be aligned to cache line size
+ *  32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
+ * to align to the cache line size if startAddr is not aligned. For the size_byte, application should
+ * make sure the alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
+{
+#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
+#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
+    L2CACHE_InvalidateByRange(address, size_byte);
+#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
+#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
+
+    L1CACHE_InvalidateICacheByRange(address, size_byte);
+}
+
+/*!
+ * brief Invalidates all data caches by range.
+ *
+ * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
+ *
+ * param address The physical address.
+ * param size_byte size of the memory to be invalidated.
+ * note address and size should be aligned to cache line size
+ *  32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
+ * to align to the cache line size if startAddr is not aligned. For the size_byte, application should
+ * make sure the alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
+{
+#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
+#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
+    L2CACHE_InvalidateByRange(address, size_byte);
+#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
+#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
+    L1CACHE_InvalidateDCacheByRange(address, size_byte);
+}
+
+/*!
+ * brief Cleans all data caches by range.
+ *
+ * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
+ *
+ * param address The physical address.
+ * param size_byte size of the memory to be cleaned.
+ * note address and size should be aligned to cache line size
+ *  32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
+ * to align to the cache line size if startAddr is not aligned. For the size_byte, application should
+ * make sure the alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
+{
+    L1CACHE_CleanDCacheByRange(address, size_byte);
+#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
+#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
+    L2CACHE_CleanByRange(address, size_byte);
+#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
+#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
+}
+
+/*!
+ * brief Cleans and Invalidates all data caches by range.
+ *
+ * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
+ *
+ * param address The physical address.
+ * param size_byte size of the memory to be cleaned and invalidated.
+ * note address and size should be aligned to cache line size
+ *  32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
+ * to align to the cache line size if startAddr is not aligned. For the size_byte, application should
+ * make sure the alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
+{
+    L1CACHE_CleanInvalidateDCacheByRange(address, size_byte);
+#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
+#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
+    L2CACHE_CleanInvalidateByRange(address, size_byte);
+#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
+#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
+}
@@ -0,0 +1,155 @@
+/*
+* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+* All rights reserved.
+*
+*
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+/**
+ * @file fsl_common.c
+ * @brief common drivers
+ * @version 1.0
+ * @author AIIT XUOS Lab
+ * @date 2021.11.11
+ */
+
+#include "fsl_common.h"
+#define SDK_MEM_MAGIC_NUMBER 12345U
+
+typedef struct _mem_align_control_block
+{
+    uint16_t identifier; /*!< Identifier for the memory control block. */
+    uint16_t offset;     /*!< offset from aligned address to real address */
+} mem_align_cb_t;
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.common"
+#endif
+
+#ifndef __GIC_PRIO_BITS
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
+{
+/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+    extern uint32_t Image$$VECTOR_ROM$$Base[];
+    extern uint32_t Image$$VECTOR_RAM$$Base[];
+    extern uint32_t Image$$RW_m_data$$Base[];
+
+#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
+#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
+#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
+#elif defined(__ICCARM__)
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+#elif defined(__GNUC__)
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
+    uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
+#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */
+    uint32_t n;
+    uint32_t ret;
+    uint32_t irqMaskValue;
+
+    irqMaskValue = DisableGlobalIRQ();
+    if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
+    {
+        /* Copy the vector table from ROM to RAM */
+        for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
+        {
+            __VECTOR_RAM[n] = __VECTOR_TABLE[n];
+        }
+        /* Point the VTOR to the position of vector table */
+        SCB->VTOR = (uint32_t)__VECTOR_RAM;
+    }
+
+    ret = __VECTOR_RAM[irq + 16];
+    /* make sure the __VECTOR_RAM is noncachable */
+    __VECTOR_RAM[irq + 16] = irqHandler;
+
+    EnableGlobalIRQ(irqMaskValue);
+
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+
+    return ret;
+}
+#endif /* ENABLE_RAM_VECTOR_TABLE. */
+#endif /* __GIC_PRIO_BITS. */
+
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)
+
+void EnableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t intNumber = (uint32_t)interrupt;
+
+    uint32_t index = 0;
+
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    SYSCON->STARTERSET[index] = 1u << intNumber;
+    EnableIRQ(interrupt); /* also enable interrupt at NVIC */
+}
+
+void DisableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t intNumber = (uint32_t)interrupt;
+
+    DisableIRQ(interrupt); /* also disable interrupt at NVIC */
+    uint32_t index = 0;
+
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    SYSCON->STARTERCLR[index] = 1u << intNumber;
+}
+#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+
+void *SDK_Malloc(size_t size, size_t alignbytes)
+{
+    mem_align_cb_t *p_cb = NULL;
+    uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t);
+    void *p_align_addr, *p_addr = malloc(alignedsize);
+
+    if (!p_addr)
+    {
+        return NULL;
+    }
+
+    p_align_addr = (void *)SDK_SIZEALIGN((uint32_t)p_addr + sizeof(mem_align_cb_t), alignbytes);
+
+    p_cb = (mem_align_cb_t *)((uint32_t)p_align_addr - 4);
+    p_cb->identifier = SDK_MEM_MAGIC_NUMBER;
+    p_cb->offset = (uint32_t)p_align_addr - (uint32_t)p_addr;
+
+    return (void *)p_align_addr;
+}
+
+void SDK_Free(void *ptr)
+{
+    mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4);
+
+    if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)
+    {
+        return;
+    }
+
+    free((void *)((uint32_t)ptr - p_cb->offset));
+}
@@ -0,0 +1,236 @@
+/*
+** ###################################################################
+**     Processors:          MIMXRT1052CVJ5B
+**                          MIMXRT1052CVL5B
+**                          MIMXRT1052DVJ6B
+**                          MIMXRT1052DVL6B
+**
+**     Compilers:           Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    IMXRT1050RM Rev.2.1, 12/2018
+**     Version:             rev. 1.2, 2018-11-27
+**     Build:               b181205
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2018 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 0.1 (2017-01-10)
+**         Initial version.
+**     - rev. 1.0 (2018-09-21)
+**         Update interrupt vector table and dma request source.
+**         Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
+**         Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
+**     - rev. 1.1 (2018-11-16)
+**         Update header files to align with IMXRT1050RM Rev.1.
+**     - rev. 1.2 (2018-11-27)
+**         Update header files to align with IMXRT1050RM Rev.2.1.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MIMXRT1052
+ * @version 1.2
+ * @date 2018-11-27
+ * @brief Device specific configuration file for MIMXRT1052 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+
+#if defined(__MCUXPRESSO)
+    extern uint32_t g_pfnVectors[];  // Vector table defined in startup code
+    SCB->VTOR = (uint32_t)g_pfnVectors;
+#endif
+
+/* Disable Watchdog Power Down Counter */
+WDOG1->WMCR &= ~WDOG_WMCR_PDE_MASK;
+WDOG2->WMCR &= ~WDOG_WMCR_PDE_MASK;
+
+/* Watchdog disable */
+
+#if (DISABLE_WDOG)
+    if (WDOG1->WCR & WDOG_WCR_WDE_MASK)
+    {
+        WDOG1->WCR &= ~WDOG_WCR_WDE_MASK;
+    }
+    if (WDOG2->WCR & WDOG_WCR_WDE_MASK)
+    {
+        WDOG2->WCR &= ~WDOG_WCR_WDE_MASK;
+    }
+    RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
+    RTWDOG->TOVAL = 0xFFFF;
+    RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
+#endif /* (DISABLE_WDOG) */
+
+    /* Disable Systick which might be enabled by bootrom */
+    if (SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)
+    {
+        SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+    }
+
+/* Enable instruction and data caches */
+#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
+    if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) {
+        SCB_EnableICache();
+    }
+#endif
+#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
+    if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) {
+        SCB_EnableDCache();
+    }
+#endif
+
+  SystemInitHook();
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+
+    uint32_t freq;
+    uint32_t PLL1MainClock;
+    uint32_t PLL2MainClock;
+
+    /* Periph_clk2_clk ---> Periph_clk */
+    if (CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK)
+    {
+        switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
+        {
+            /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */
+            case CCM_CBCMR_PERIPH_CLK2_SEL(0U):
+                if(CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK)
+                {
+                    freq = (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) == 0U) ?
+                           CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
+                }
+                else
+                {
+                    freq = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U));
+                }
+                break;
+
+            /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */
+            case CCM_CBCMR_PERIPH_CLK2_SEL(1U):
+                freq = CPU_XTAL_CLK_HZ;
+                break;
+
+            case CCM_CBCMR_PERIPH_CLK2_SEL(2U):
+                freq = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ?
+                   CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
+                break;
+
+            case CCM_CBCMR_PERIPH_CLK2_SEL(3U):
+            default:
+                freq = 0U;
+                break;
+        }
+
+        freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U);
+    }
+    /* Pre_Periph_clk ---> Periph_clk */
+    else
+    {
+        /* check if pll is bypassed */
+        if(CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
+        {
+            PLL1MainClock = (((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) == 0U) ?
+                   CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
+        }
+        else
+        {
+            PLL1MainClock = ((CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
+                                             CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U);
+        }
+
+        /* check if pll is bypassed */
+        if(CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK)
+        {
+            PLL2MainClock = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ?
+                   CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
+        }
+        else
+        {
+            PLL2MainClock = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) ? 22U : 20U));
+        }
+        PLL2MainClock += ((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM));
+
+
+        switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
+        {
+            /* PLL2 ---> Pre_Periph_clk ---> Periph_clk */
+            case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U):
+                freq = PLL2MainClock;
+                break;
+
+            /* PLL2 PFD2 ---> Pre_Periph_clk ---> Periph_clk */
+            case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U):
+                freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT) * 18U;
+                break;
+
+            /* PLL2 PFD0 ---> Pre_Periph_clk ---> Periph_clk */
+            case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U):
+                freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) * 18U;
+                break;
+
+            /* PLL1 divided(/2) ---> Pre_Periph_clk ---> Periph_clk */
+            case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U):
+                freq = PLL1MainClock / (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U);
+                break;
+
+            default:
+                freq = 0U;
+                break;
+        }
+    }
+
+    SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U));
+
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemInitHook()
+   ---------------------------------------------------------------------------- */
+
+__attribute__ ((weak)) void SystemInitHook (void) {
+  /* Void implementation of the weak function. */
+}
@@ -0,0 +1,12 @@
+
+config PIN_BUS_NAME
+    string "pin bus name"
+    default "pin"
+
+config PIN_DRIVER_NAME
+    string "pin driver name"
+    default "pin_drv"
+
+config PIN_DEVICE_NAME
+    string "pin device name"
+    default "pin_dev"
@@ -0,0 +1,3 @@
+SRC_FILES := connect_gpio.c fsl_gpio.c
+
+include $(KERNEL_ROOT)/compiler.mk
@@ -0,0 +1,544 @@
+/*
+ * Copyright (c) 2020 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2018-11-06     balanceTWK        first version
+ * 2019-04-23     WillianChan       Fix GPIO serial number disorder
+*/
+
+/**
+* @file connect_gpio.c
+* @brief support gpio function using bus driver framework
+* @version 1.0
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+/*************************************************
+File name: connect_gpio.c
+Description: support  gpio configure and register to bus framework
+Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_gpio.c for references
+                https://github.com/RT-Thread/rt-thread/tree/v4.0.2
+History:
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: add bus driver framework support for gpio
+*************************************************/
+
+#include <device.h>
+#include <board.h>
+
+#define STM32_PIN_NUMBERS 100 // [48, 64, 100, 144]
+
+#define ITEM_NUM(items) sizeof(items)/sizeof(items[0])
+
+struct PinIndex
+{
+    int index;
+    GPIO_Type *gpio;
+    uint32_t pin;
+};
+
+struct PinIrq
+{
+    uint8 port_source;
+    uint8 pin_source;
+    enum IRQn irq_exti_channel;
+    uint32 exti_line;
+};
+
+static const struct PinIndex pins[] = {
+    {0, GPIO1, 0},
+    {1, GPIO1, 1},
+    {2, GPIO1, 2},
+    {3, GPIO1, 3},
+    {4, GPIO1, 4},
+    {5, GPIO1, 5},
+    {6, GPIO1, 6},
+    {7, GPIO1, 7},
+    {8, GPIO1, 8},
+    {9, GPIO1, 9},
+    {10, GPIO1, 10},
+    {11, GPIO1, 11},
+    {12, GPIO1, 12},
+    {13, GPIO1, 13},
+    {14, GPIO1, 14},
+    {15, GPIO1, 15},
+    {16, GPIO2, 0},
+    {17, GPIO2, 1},
+    {18, GPIO2, 2},
+    {19, GPIO2, 3},
+    {20, GPIO2, 4},
+    {21, GPIO2, 5},
+    {22, GPIO2, 6},
+    {23, GPIO2, 7},
+    {24, GPIO2, 8},
+    {25, GPIO2, 9},
+    {26, GPIO2, 10},
+    {27, GPIO2, 11},
+    {28, GPIO2, 12},
+    {29, GPIO2, 13},
+    {30, GPIO2, 14},
+    {31, GPIO2, 15},
+    {32, GPIO3, 0},
+    {33, GPIO3, 1},
+    {34, GPIO3, 2},
+    {35, GPIO3, 3},
+    {36, GPIO3, 4},
+    {37, GPIO3, 5},
+    {38, GPIO3, 6},
+    {39, GPIO3, 7},
+    {40, GPIO3, 8},
+    {41, GPIO3, 9},
+    {42, GPIO3, 10},
+    {43, GPIO3, 11},
+    {44, GPIO3, 12},
+    {45, GPIO3, 13},
+    {46, GPIO3, 14},
+    {47, GPIO3, 15},
+    {-1, 0u, -1}
+};
+
+struct PinIrqHdr pin_irq_hdr_tab[] = {};
+
+const struct PinIndex *GetPin(uint8_t pin)
+{
+    const struct PinIndex *index;
+
+    if (pin < ITEM_NUM(pins)){
+        index = &pins[pin];
+        if (index->index == -1)
+            index = NONE;
+    }
+    else{
+        index = NONE;
+    }
+
+    return index;
+}
+
+static int32 GpioConfigMode(int mode, const struct PinIndex* index)
+{
+    gpio_pin_config_t gpio_config;
+    NULL_PARAM_CHECK(index);
+
+    switch (mode)
+    {
+        case GPIO_CFG_OUTPUT:
+            gpio_config.direction = kGPIO_DigitalOutput;
+            gpio_config.interruptMode = kGPIO_NoIntmode;
+            break;
+        case GPIO_CFG_INPUT:
+            gpio_config.direction = kGPIO_DigitalInput;
+            gpio_config.interruptMode = kGPIO_NoIntmode;
+            break;
+        case GPIO_CFG_INPUT_PULLUP:
+            gpio_config.direction = kGPIO_DigitalInput;
+            gpio_config.interruptMode = kGPIO_IntRisingEdge;
+            break;
+        case GPIO_CFG_INPUT_PULLDOWN:
+            gpio_config.direction = kGPIO_DigitalInput;
+            gpio_config.interruptMode = kGPIO_IntFallingEdge;
+            break;
+        case GPIO_CFG_OUTPUT_OD:
+            gpio_config.direction = kGPIO_DigitalOutput;
+            break;
+        default:
+            break;
+    }
+    GPIO_PinInit(index->gpio, index->pin, &gpio_config);
+    return EOK;
+}
+
+static __inline int32 Bit2Bitnum(uint32 bit)
+{
+    for (int i = 0; i < 32; i++){
+        if ((1UL << i) == bit){
+            return i;
+        }
+    }
+    return -1;
+}
+
+static __inline int32 Bitno2Bit(uint32 bitno)
+{
+    if (bitno <= 32) {
+        return 1UL << bitno;
+    }
+    else {
+        return 0;
+    }
+}
+static const struct PinIrq *GetPinIrq(uint16_t pin)
+{
+    static struct PinIrq irq;
+    const struct PinIndex* index = GetPin(pin);
+
+    if (index == NONE) {
+        return NONE;
+    }
+
+    irq.exti_line = index->pin;
+    irq.pin_source = Bit2Bitnum(index->pin);
+    irq.port_source = ((uint32_t)index->gpio - GPIO1_BASE) / (GPIO2_BASE - GPIO1_BASE);
+    switch (irq.pin_source)
+    {
+        case 0 :
+            irq.irq_exti_channel = GPIO1_INT0_IRQn;
+            break;
+        case 1 :
+            irq.irq_exti_channel = GPIO1_INT1_IRQn;
+            break;
+        case 2 :
+            irq.irq_exti_channel = GPIO1_INT2_IRQn;
+            break;
+        case 3 :
+            irq.irq_exti_channel = GPIO1_INT3_IRQn;
+            break;
+        case 4 :
+            irq.irq_exti_channel = GPIO1_INT4_IRQn;
+            break;
+        case 5 :
+            irq.irq_exti_channel = GPIO1_INT5_IRQn;
+            break;
+        case 6 :
+            irq.irq_exti_channel = GPIO1_INT6_IRQn;
+            break;
+        case 7 :
+            irq.irq_exti_channel = GPIO1_INT7_IRQn;
+            break;
+        default :
+            return NONE;
+    }
+
+    return &irq;
+};
+static int32 GpioIrqRegister(int32 pin, int32 mode, void (*hdr)(void *args), void *args)
+{
+    const struct PinIndex* index = GetPin(pin);
+    int32 irqindex = -1;
+
+    irqindex = Bit2Bitnum(index->pin);
+    if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)) {
+        return -ENONESYS;
+    }
+
+    x_base level = CriticalAreaLock();
+    if (pin_irq_hdr_tab[irqindex].pin == pin   &&
+        pin_irq_hdr_tab[irqindex].hdr == hdr   &&
+        pin_irq_hdr_tab[irqindex].mode == mode &&
+        pin_irq_hdr_tab[irqindex].args == args
+    )
+    {
+        CriticalAreaUnLock(level);
+        return EOK;
+    }
+    if (pin_irq_hdr_tab[irqindex].pin != -1) {
+        CriticalAreaUnLock(level);
+        return -EDEV_BUSY;
+    }
+    pin_irq_hdr_tab[irqindex].pin = pin;
+    pin_irq_hdr_tab[irqindex].hdr = hdr;
+    pin_irq_hdr_tab[irqindex].mode = mode;
+    pin_irq_hdr_tab[irqindex].args = args;
+    CriticalAreaUnLock(level);
+
+    return EOK;
+}
+
+static uint32 GpioIrqFree(int32 pin)
+{
+    const struct PinIndex* index = GetPin(pin);
+    int32 irqindex = -1;
+
+    irqindex = Bit2Bitnum(index->pin);
+    if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)) {
+        return -ENONESYS;
+    }
+
+    x_base level = CriticalAreaLock();
+    if (pin_irq_hdr_tab[irqindex].pin == -1){
+        CriticalAreaUnLock(level);
+        return EOK;
+    }
+    pin_irq_hdr_tab[irqindex].pin  = -1;
+    pin_irq_hdr_tab[irqindex].hdr  = NONE;
+    pin_irq_hdr_tab[irqindex].mode = 0;
+    pin_irq_hdr_tab[irqindex].args = NONE;
+    CriticalAreaUnLock(level);
+
+    return EOK;
+}
+
+static int32 GpioIrqEnable(x_base pin)
+{
+    const struct PinIndex* index = GetPin(pin);
+    int32 irqindex = -1;
+    const struct PinIrq *irq;
+    gpio_pin_config_t gpio_config;
+
+    irqindex = Bit2Bitnum(index->pin);
+    if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)){
+        return -ENONESYS;
+    }
+    x_base level = CriticalAreaLock();
+    if (pin_irq_hdr_tab[irqindex].pin == -1) {
+        CriticalAreaUnLock(level);
+        return -ENONESYS;
+    }
+
+    irq = GetPinIrq(pin);
+    if (irq == NONE){
+        CriticalAreaUnLock(level);
+        return -ENONESYS;
+    }
+
+    switch (pin_irq_hdr_tab[irqindex].mode)
+    {
+    case GPIO_IRQ_EDGE_RISING:
+        gpio_config.direction = kGPIO_DigitalInput;
+        gpio_config.interruptMode = kGPIO_IntRisingEdge;
+        break;
+    case GPIO_IRQ_EDGE_FALLING:
+        gpio_config.direction = kGPIO_DigitalInput;
+        gpio_config.interruptMode = kGPIO_IntFallingEdge;
+        break;
+    case GPIO_IRQ_EDGE_BOTH:
+        gpio_config.direction = kGPIO_DigitalInput;
+        gpio_config.interruptMode = kGPIO_IntRisingOrFallingEdge;
+        break;
+    }
+
+    GPIO_PinInit(index->gpio, index->pin, &gpio_config);
+    GPIO_PortEnableInterrupts(index->gpio, index->pin);
+    CriticalAreaUnLock(level);
+    return EOK;
+}
+
+static int32 GpioIrqDisable(x_base pin)
+{
+    const struct PinIndex* index = GetPin(pin);
+    const struct PinIrq *irq;
+
+    irq = GetPinIrq(index->pin);
+    NULL_PARAM_CHECK(irq);
+
+    GPIO_PortDisableInterrupts(index->gpio, index->pin);
+    return EOK;
+}
+
+static uint32 Stm32PinConfigure(struct PinParam *param)
+{
+    NULL_PARAM_CHECK(param);
+    int ret = EOK;
+
+    const struct PinIndex *index = GetPin(param->pin);
+    switch(param->cmd)
+    {
+        case GPIO_CONFIG_MODE:
+            GpioConfigMode(param->mode, index);
+            break;
+        case GPIO_IRQ_REGISTER:
+            ret = GpioIrqRegister(param->pin,param->irq_set.irq_mode,param->irq_set.hdr,param->irq_set.args);
+            break;
+        case GPIO_IRQ_FREE:
+            ret = GpioIrqFree(param->pin);
+            break;
+        case GPIO_IRQ_ENABLE:
+            ret = GpioIrqEnable(param->pin);
+            break;
+        case GPIO_IRQ_DISABLE:
+            ret = GpioIrqDisable(param->pin);
+            break;
+        default:
+            ret = -EINVALED;
+            break;
+    }
+
+    return ret;
+}
+
+static uint32 Stm32PinInit(void)
+{
+    static x_bool pin_init_flag = RET_FALSE;
+
+    if (!pin_init_flag) {
+        pin_init_flag = RET_TRUE;
+    }
+
+    return EOK;
+}
+
+static uint32 Stm32GpioDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(drv);
+    NULL_PARAM_CHECK(configure_info);
+
+    x_err_t ret = EOK;
+    struct PinParam *param;
+
+    switch (configure_info->configure_cmd)
+    {
+        case OPE_INT:
+            ret = Stm32PinInit();
+            break;
+        case OPE_CFG:
+            param = (struct PinParam *)configure_info->private_data;
+            ret = Stm32PinConfigure(param);
+            break;
+        default:
+            break;
+    }
+
+    return ret;
+}
+
+uint32 Stm32PinWrite(void *dev, struct BusBlockWriteParam *write_param)
+{
+    NULL_PARAM_CHECK(dev);
+    NULL_PARAM_CHECK(write_param);
+    struct PinStat *pinstat = (struct PinStat *)write_param->buffer;
+    const struct PinIndex* index = GetPin(pinstat->pin);
+    NULL_PARAM_CHECK(index);
+
+    if (GPIO_LOW == pinstat->val) {
+        GPIO_PinWrite(index->gpio, index->pin, 0);
+    } else {
+        GPIO_PinWrite(index->gpio, index->pin, 1);
+    }
+    return EOK;
+}
+
+uint32 Stm32PinRead(void *dev, struct BusBlockReadParam *read_param)
+{
+    NULL_PARAM_CHECK(dev);
+    NULL_PARAM_CHECK(read_param);
+    struct PinStat *pinstat = (struct PinStat *)read_param->buffer;
+    const struct PinIndex* index = GetPin(pinstat->pin);
+    NULL_PARAM_CHECK(index);
+
+    if(GPIO_PinRead(index->gpio, index->pin) == GPIO_LOW) {
+        pinstat->val = GPIO_LOW;
+    } else {
+        pinstat->val = GPIO_HIGH;
+    }
+    return pinstat->val;
+}
+
+static const struct PinDevDone dev_done =
+{
+    .open  = NONE,
+    .close = NONE,
+    .write = Stm32PinWrite,
+    .read  = Stm32PinRead,
+};
+
+int Stm32HwGpioInit(void)
+{
+    x_err_t ret = EOK;
+
+    static struct PinBus pin;
+
+    ret = PinBusInit(&pin, PIN_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("gpio bus init error %d\n", ret);
+        return ERROR;
+    }
+
+    static struct PinDriver drv;
+    drv.configure = &Stm32GpioDrvConfigure;
+
+    ret = PinDriverInit(&drv, PIN_DRIVER_NAME, NONE);
+    if (ret != EOK) {
+        KPrintf("pin driver init error %d\n", ret);
+        return ERROR;
+    }
+    ret = PinDriverAttachToBus(PIN_DRIVER_NAME, PIN_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("pin driver attach error %d\n", ret);
+        return ERROR;
+    }
+
+    static struct PinHardwareDevice dev;
+    dev.dev_done = &dev_done;
+
+    ret = PinDeviceRegister(&dev, NONE, PIN_DEVICE_NAME);
+    if (ret != EOK) {
+        KPrintf("pin device register error %d\n", ret);
+        return ERROR;
+    }
+    ret = PinDeviceAttachToBus(PIN_DEVICE_NAME, PIN_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("pin device register error %d\n", ret);
+        return ERROR;
+    }
+
+    return ret;
+}
+
+static __inline void PinIrqHdr(int irqno)
+{
+    const struct PinIndex* index = GetPin(irqno);
+    const struct PinIrq *irq;
+
+    irq = GetPinIrq(index->pin);
+    NULL_PARAM_CHECK(irq);
+
+    GPIO_ClearPinsInterruptFlags(index->gpio, index->pin);
+
+    if (pin_irq_hdr_tab[irqno].hdr){
+       pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
+    }
+}
+
+void EXTI0_IRQHandler(int irq_num, void *arg)
+{
+    PinIrqHdr(0);
+}
+DECLARE_HW_IRQ(GPIO1_INT0_IRQn, EXTI0_IRQHandler, NONE);
+
+void EXTI1_IRQHandler(int irq_num, void *arg)
+{
+    PinIrqHdr(1);
+}
+DECLARE_HW_IRQ(GPIO1_INT1_IRQn, EXTI1_IRQHandler, NONE);
+
+void EXTI2_IRQHandler(int irq_num, void *arg)
+{
+    PinIrqHdr(2);
+}
+DECLARE_HW_IRQ(GPIO1_INT2_IRQn, EXTI2_IRQHandler, NONE);
+
+void EXTI3_IRQHandler(int irq_num, void *arg)
+{
+    PinIrqHdr(3);
+}
+DECLARE_HW_IRQ(GPIO1_INT3_IRQn, EXTI3_IRQHandler, NONE);
+
+void EXTI4_IRQHandler(int irq_num, void *arg)
+{
+    PinIrqHdr(4);
+}
+DECLARE_HW_IRQ(GPIO1_INT4_IRQn, EXTI4_IRQHandler, NONE);
+
+void EXTI5_IRQHandler(int irq_num, void *arg)
+{
+    PinIrqHdr(5);
+}
+DECLARE_HW_IRQ(GPIO1_INT5_IRQn, EXTI5_IRQHandler, NONE);
+
+void EXTI6_IRQHandler(int irq_num, void *arg)
+{
+    PinIrqHdr(6);
+}
+DECLARE_HW_IRQ(GPIO1_INT6_IRQn, EXTI6_IRQHandler, NONE);
+
+void EXTI7_IRQHandler(int irq_num, void *arg)
+{
+    PinIrqHdr(7);
+}
+DECLARE_HW_IRQ(GPIO1_INT7_IRQn, EXTI7_IRQHandler, NONE);
+
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_gpio.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.igpio"
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Array of GPIO peripheral base address. */
+static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/* Array of GPIO clock name. */
+static const clock_ip_name_t s_gpioClock[] = GPIO_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Gets the GPIO instance according to the GPIO base
+ *
+ * @param base    GPIO peripheral base pointer(PTA, PTB, PTC, etc.)
+ * @retval GPIO instance
+ */
+static uint32_t GPIO_GetInstance(GPIO_Type *base);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t GPIO_GetInstance(GPIO_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_gpioBases); instance++)
+    {
+        if (s_gpioBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_gpioBases));
+
+    return instance;
+}
+
+/*!
+ * brief Initializes the GPIO peripheral according to the specified
+ *        parameters in the initConfig.
+ *
+ * param base GPIO base pointer.
+ * param pin Specifies the pin number
+ * param initConfig pointer to a ref gpio_pin_config_t structure that
+ *        contains the configuration information.
+ */
+void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable GPIO clock. */
+    uint32_t instance = GPIO_GetInstance(base);
+
+    /* If The clock IP is valid, enable the clock gate. */
+    if ((instance < ARRAY_SIZE(s_gpioClock)) && (kCLOCK_IpInvalid != s_gpioClock[instance]))
+    {
+        CLOCK_EnableClock(s_gpioClock[instance]);
+    }
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Register reset to default value */
+    base->IMR &= ~(1U << pin);
+
+    /* Configure GPIO pin direction */
+    if (Config->direction == kGPIO_DigitalInput)
+    {
+        base->GDIR &= ~(1U << pin);
+    }
+    else
+    {
+        GPIO_PinWrite(base, pin, Config->outputLogic);
+        base->GDIR |= (1U << pin);
+    }
+
+    /* Configure GPIO pin interrupt mode */
+    GPIO_SetPinInterruptConfig(base, pin, Config->interruptMode);
+}
+
+/*!
+ * brief Sets the output level of the individual GPIO pin to logic 1 or 0.
+ *
+ * param base GPIO base pointer.
+ * param pin GPIO port pin number.
+ * param output GPIOpin output logic level.
+ *        - 0: corresponding pin output low-logic level.
+ *        - 1: corresponding pin output high-logic level.
+ */
+void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output)
+{
+    assert(pin < 32);
+    if (output == 0U)
+    {
+        base->DR &= ~(1U << pin); /* Set pin output to low level.*/
+    }
+    else
+    {
+        base->DR |= (1U << pin); /* Set pin output to high level.*/
+    }
+}
+
+/*!
+ * brief Sets the current pin interrupt mode.
+ *
+ * param base GPIO base pointer.
+ * param pin GPIO port pin number.
+ * param pininterruptMode pointer to a ref gpio_interrupt_mode_t structure
+ *        that contains the interrupt mode information.
+ */
+void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode)
+{
+    volatile uint32_t *icr;
+    uint32_t icrShift;
+
+    icrShift = pin;
+
+    /* Register reset to default value */
+    base->EDGE_SEL &= ~(1U << pin);
+
+    if (pin < 16)
+    {
+        icr = &(base->ICR1);
+    }
+    else
+    {
+        icr = &(base->ICR2);
+        icrShift -= 16;
+    }
+    switch (pinInterruptMode)
+    {
+        case (kGPIO_IntLowLevel):
+            *icr &= ~(3U << (2 * icrShift));
+            break;
+        case (kGPIO_IntHighLevel):
+            *icr = (*icr & (~(3U << (2 * icrShift)))) | (1U << (2 * icrShift));
+            break;
+        case (kGPIO_IntRisingEdge):
+            *icr = (*icr & (~(3U << (2 * icrShift)))) | (2U << (2 * icrShift));
+            break;
+        case (kGPIO_IntFallingEdge):
+            *icr |= (3U << (2 * icrShift));
+            break;
+        case (kGPIO_IntRisingOrFallingEdge):
+            base->EDGE_SEL |= (1U << pin);
+            break;
+        default:
+            break;
+    }
+}
--- a/Show More
+++ b/Show More