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feat add third_party_driver/sdio for hc32f4a0 board

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This commit is contained in:
Liu_Weichao
2022-10-18 17:27:30 +08:00
parent 700a07bc84
commit 9802c89fd6
23 changed files with 2586 additions and 42 deletions
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Ubiquitous/XiZi_IIoT/board/hc32f4a0/board.c
+31 -27
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@@ -34,6 +34,10 @@ Modification:
#include <hc32_ll.h>
#include <connect_usart.h>
#ifdef BSP_USING_SDIO
#include <connect_sdio.h>
#endif
extern void entry(void);
extern int HwUsartInit();
@@ -46,15 +50,10 @@ void SystemClockConfig(void)
stc_clock_xtal_init_t stcXtalInit;
stc_clock_pll_init_t stcPLLHInit;
/* PCLK0, HCLK Max 240MHz */
/* PCLK1, PCLK4 Max 120MHz */
/* PCLK2, PCLK3 Max 60MHz */
/* EX BUS Max 120MHz */
CLK_SetClockDiv(CLK_BUS_CLK_ALL, \
(CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | \
CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | \
CLK_SetClockDiv(CLK_BUS_CLK_ALL,
(CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 |
CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 |
CLK_HCLK_DIV1));
(void)CLK_XtalStructInit(&stcXtalInit);
/* Config Xtal and enable Xtal */
stcXtalInit.u8Mode = CLK_XTAL_MD_OSC;
@@ -64,26 +63,23 @@ void SystemClockConfig(void)
(void)CLK_XtalInit(&stcXtalInit);
(void)CLK_PLLStructInit(&stcPLLHInit);
/* VCO = (8/1)*120 = 960MHz*/
stcPLLHInit.u8PLLState = CLK_PLL_ON;
stcPLLHInit.PLLCFGR = 0UL;
stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLN = 120UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL;
/* VCO = (8/1)*100 = 800MHz*/
stcPLLHInit.u8PLLState = CLK_PLL_ON;
stcPLLHInit.PLLCFGR = 0UL;
stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLN = 100UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL;
(void)CLK_PLLInit(&stcPLLHInit);
/* Highspeed SRAM set to 0 Read/Write wait cycle */
SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0);
/* SRAM1_2_3_4_backup set to 1 Read/Write wait cycle */
SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1);
/* Highspeed SRAM set to 1 Read/Write wait cycle */
SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1);
/* SRAM1_2_3_4_backup set to 2 Read/Write wait cycle */
SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE2, SRAM_WAIT_CYCLE2);
/* 0-wait @ 40MHz */
(void)EFM_SetWaitCycle(EFM_WAIT_CYCLE5);
EFM_SetWaitCycle(EFM_WAIT_CYCLE5);
/* 4 cycles for 200 ~ 250MHz */
GPIO_SetReadWaitCycle(GPIO_RD_WAIT4);
CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
@@ -98,7 +94,7 @@ void PeripheralClockConfig(void)
CLK_SetCANClockSrc(CLK_CAN2, CLK_CANCLK_SYSCLK_DIV6);
#endif
#if defined(RT_USING_ADC)
#if defined(BSP_USING_ADC)
CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK);
#endif
}
@@ -117,12 +113,20 @@ void SysTickConfiguration(void)
void SysTick_Handler(void)
{
x_base lock = 0;
lock = DISABLE_INTERRUPT();
TickAndTaskTimesliceUpdate();
ENABLE_INTERRUPT(lock);
}
struct InitSequenceDesc _board_init[] =
{
{ " NONE ",NONE },
{
#ifdef BSP_USING_SDIO
{ "sdio", HwSdioInit },
#endif
{ " NONE ", NONE },
};
void InitBoardHardware()