Modify uart
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1eedb9d24e
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8795b4138e
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@ -28,6 +28,10 @@ _boot_start:
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csrw CSR_IE, zero
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csrw CSR_IP, zero
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j primary_cpu_init
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/*
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switch_mode:
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csrr t0, sstatus
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srli t0, t0, 8
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andi t0, t0, 1
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@ -43,6 +47,7 @@ _boot_start:
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continue_execution:
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j primary_cpu_init
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*/
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primary_cpu_init:
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la t0, boot_start_addr
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@ -59,15 +59,10 @@ extern uint64_t kernel_data_begin[];
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#define IDX_MASK (0b111111111)
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#define L3_PDE_INDEX(idx) ((idx << LEVEL3_PDE_SHIFT) & L3_IDX_MASK)
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#define _PAGE_KERNEL (_PAGE_READ \
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| _PAGE_WRITE \
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| _PAGE_PRESENT \
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| _PAGE_ACCESSED \
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| _PAGE_DIRTY \
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| _PAGE_GLOBAL)
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#define PAGE_KERNEL (_PAGE_KERNEL)
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#define PAGE_KERNEL_READ (_PAGE_KERNEL & ~_PAGE_WRITE)
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#define PAGE_KERNEL_EXEC (_PAGE_KERNEL | _PAGE_EXEC)
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#define _PAGE_KERNEL (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | _PAGE_EXEC | _PAGE_ACCESSED | _PAGE_GLOBAL | _PAGE_DIRTY)
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#define PAGE_KERNEL (_PAGE_KERNEL)
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#define PAGE_KERNEL_READ (_PAGE_KERNEL & ~_PAGE_WRITE)
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#define PAGE_KERNEL_EXEC (_PAGE_KERNEL | _PAGE_EXEC)
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// clang-format on
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uint64_t boot_l2pgdir[NUM_LEVEL2_PDE] __attribute__((aligned(0x1000))) = { 0 };
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@ -125,15 +120,11 @@ static inline void local_flush_tlb_all(void)
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static void load_boot_pgdir()
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{
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unsigned long satp_val = (unsigned long)(((uintptr_t)boot_l2pgdir >> PAGE_SHIFT) | SATP_MODE);
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unsigned long status;
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unsigned long satp_val = 0;
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status = csr_read(CSR_STATUS);
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if( !(status & 0x100) ) {
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_debug_uart_printascii("current is not S mode\n");
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}
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#if 0 //to debug
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csr_write(CSR_SATP, ((uintptr_t)boot_l2pgdir >> PAGE_SHIFT) | SATP_MODE);
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satp_val = (unsigned long)(((uintptr_t)boot_l2pgdir >> PAGE_SHIFT) | SATP_MODE);
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#if 1 //to debug
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csr_write(CSR_SATP, satp_val);
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#endif
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}
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@ -141,12 +132,11 @@ extern void main(void);
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static bool _bss_inited = false;
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void bootmain()
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{
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_debug_uart_init();
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_debug_uart_phymem_init();
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_debug_uart_printascii("bootmain start.\n");
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build_boot_pgdir();
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load_boot_pgdir();
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// _debug_uart_base_map();
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_debug_uart_printascii("boot pgdir success\n");
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__asm__ __volatile__("addi sp, sp, %0" ::"i"(KERN_OFFSET));
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@ -214,6 +214,6 @@ void _debug_uart_init(void);
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void _debug_uart_putc(int ch);
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int _debug_uart_getc(void);
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void _debug_uart_printascii(const char *str);
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void _debug_uart_base_map(void);
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void _debug_uart_phymem_init(void);
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#endif /* __ns16550_h */
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@ -9,6 +9,7 @@
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struct ns16550 g_ns16550_com_port = {0};
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struct ns16550_plat g_ns16550_plat = {0};
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unsigned long g_ns16550_uart_base = {0};
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#define CONFIG_SYS_NS16550_UART_BASE 0x10000000
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#define CONFIG_BAUDRATE 115200
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@ -134,22 +135,12 @@ int ns16550_tstc(struct ns16550 *com_port)
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return (serial_in(&com_port->lsr) & UART_LSR_DR) != 0;
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}
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static int ns16550_serial_assign_base(struct ns16550_plat *plat, unsigned long base)
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{
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plat->base = base;
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return 0;
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}
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static void ns16550_plat_init(void)
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{
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struct ns16550_plat *plat = &g_ns16550_plat;
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unsigned long addr;
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addr = CONFIG_SYS_NS16550_UART_BASE;
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ns16550_serial_assign_base(plat, addr);
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/* refer jh7110 u-boot/arch/riscv/dts/jh7110.dtsi */
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plat->base = g_ns16550_uart_base;
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plat->reg_offset = 0;
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plat->reg_shift = 2;
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plat->reg_width = 4;
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@ -181,19 +172,20 @@ void _debug_uart_init(void)
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{
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int baudrate = CONFIG_BAUDRATE;
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g_ns16550_uart_base = CONFIG_SYS_NS16550_UART_BASE_MAP;
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ns16550_serial_init();
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ns16550_serial_setbrg(baudrate);
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_debug_uart_printascii("_debug_uart_init success.\n");
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}
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void _debug_uart_base_map(void)
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void _debug_uart_phymem_init(void)
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{
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struct ns16550_plat *plat = &g_ns16550_plat;
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unsigned long addr;
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int baudrate = CONFIG_BAUDRATE;
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addr = CONFIG_SYS_NS16550_UART_BASE_MAP;
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ns16550_serial_assign_base(plat, addr);
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_debug_uart_printascii("_debug_uart_init_mapped success.\n");
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g_ns16550_uart_base = CONFIG_SYS_NS16550_UART_BASE;
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ns16550_serial_init();
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ns16550_serial_setbrg(baudrate);
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_debug_uart_printascii("_debug_uart_phymem_init success.\n");
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}
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void _debug_uart_putc(int ch)
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