Kernel Support rk3568.(TODO: Fix user apps)
This commit is contained in:
TXuian
@@ -73,7 +73,7 @@ Modification:
|
||||
|
||||
#include "cortex_a72.h"
|
||||
|
||||
#define NR_CPU 4 // maximum number of CPUs
|
||||
#define NR_CPU 1 // maximum number of CPUs
|
||||
|
||||
__attribute__((always_inline)) static inline uint64_t EL0_mode() // Set ARM mode to EL0
|
||||
{
|
||||
|
||||
+100
-68
@@ -1,87 +1,119 @@
|
||||
// #include "memlayout.h"
|
||||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
#include "core.h"
|
||||
// #include "registers.h"
|
||||
// #include "cortex_a72.h"
|
||||
// qemu -kernel loads the kernel at 0x40000000
|
||||
// and causes each CPU to jump there.
|
||||
// kernel.ld causes the following code to
|
||||
// be placed at 0x40000000.
|
||||
.section ".text"
|
||||
//.global _entry
|
||||
|
||||
#define HCR_VALUE (1 << 31)
|
||||
#define SPSR_EL2_VALUE (7 << 6) | (5 << 0)
|
||||
#define SCTLR_EL1_VALUE (0x30D00800)
|
||||
|
||||
.section ".text", "ax"
|
||||
.global _boot_start
|
||||
.global primary_cpu_init
|
||||
.global el2_setup
|
||||
|
||||
_boot_start:
|
||||
// set up a stack for C.
|
||||
// stack0 is declared in start.c,
|
||||
// with a 4096-byte stack per CPU.
|
||||
// sp = stack0 + ((cpuid+1) * 4096)
|
||||
// cpuid = mpidr_el1 & 0xff
|
||||
// save r0 for cores 1-3, r0 arg field passed by ROM
|
||||
// r0 is a function pointer for secondary cpus
|
||||
bl el2_setup
|
||||
|
||||
// mov x4, x0
|
||||
/* set NSACR, both Secure and Non-secure access are allowed to NEON */
|
||||
mov x0, #(3 << 20)
|
||||
msr cpacr_el1, x0
|
||||
isb
|
||||
|
||||
mrs x0, spsr_el1 /* Enter EL1 (Exception Level 1) */
|
||||
bic x0, x0, #0x1f
|
||||
MOV x1, #0xC5
|
||||
ORR x0, x0, x1
|
||||
msr spsr_el1, x0
|
||||
// clear some registers
|
||||
msr elr_el1, XZR
|
||||
|
||||
ldr x0, =stacks_top
|
||||
mov x1, #MODE_STACK_SIZE
|
||||
|
||||
/* set NSACR, both Secure and Non-secure access are allowed to NEON */
|
||||
MRS X1, CPACR_EL1
|
||||
ORR X1, X1, #(0X3 << 20)
|
||||
MSR CPACR_EL1, X1
|
||||
ISB
|
||||
// get cpu id, and subtract the offset from the stacks base address
|
||||
mrs x2, mpidr_el1
|
||||
and x2, x2, #0x3
|
||||
mov x5, x2
|
||||
mul x3, x2, x1
|
||||
sub x0, x0, x3
|
||||
|
||||
mrs x0, sctlr_el1
|
||||
and x0, x0, #~(1 << 0)
|
||||
and x0, x0, #~(1 << 2)
|
||||
and x0, x0, #~(1 << 12)
|
||||
msr sctlr_el1, x0
|
||||
mov x2, #ARM_MODE_EL1_h | DIS_INT
|
||||
msr spsr_el1, x2
|
||||
mov sp, x0
|
||||
|
||||
// clear some registers
|
||||
msr elr_el1, XZR
|
||||
// bl el2_setup
|
||||
|
||||
ldr x0, =stacks_top
|
||||
mov x1, #MODE_STACK_SIZE
|
||||
// check cpu id - cpu0 is primary cpu
|
||||
mrs x2, mpidr_el1
|
||||
and x2, x2, #0x3
|
||||
mov x5, x2
|
||||
cmp x5, #0
|
||||
beq primary_cpu_init
|
||||
bl bootmain // for secondary cpus, jump to argument function pointer passed in by ROM
|
||||
|
||||
// get cpu id, and subtract the offset from the stacks base address
|
||||
mrs x2, mpidr_el1
|
||||
and x2, x2, #0x3
|
||||
mov x5, x2
|
||||
mul x3, x2, x1
|
||||
sub x0, x0, x3
|
||||
|
||||
MOV X2, #ARM_MODE_EL1_h | DIS_INT
|
||||
MSR SPSR_EL1, X2
|
||||
mov sp, x0
|
||||
SUB x0, x0,x1
|
||||
|
||||
// check cpu id - cpu0 is primary cpu
|
||||
cmp x5, #0
|
||||
beq primary_cpu_init
|
||||
bl bootmain // for secondary cpus, jump to argument function pointer passed in by ROM
|
||||
|
||||
bl .
|
||||
bl .
|
||||
|
||||
primary_cpu_init:
|
||||
/* init .bss */
|
||||
/* clear the .bss section (zero init) */
|
||||
ldr x1, =boot_start_addr
|
||||
ldr x2, =boot_end_addr
|
||||
mov x3, #0
|
||||
1:
|
||||
cmp x1, x2
|
||||
stp x3, x3, [x1], #16
|
||||
b.lt 1b
|
||||
|
||||
// branch to c library entry point
|
||||
mov x0, #0 // argc
|
||||
mov x1, #0 // argv
|
||||
mov x2, #0 // env
|
||||
/* clear the .bss section (zero init) */
|
||||
ldr x1, =boot_start_addr
|
||||
ldr x2, =boot_end_addr
|
||||
mov x3, #0
|
||||
1:
|
||||
cmp x1, x2
|
||||
stp x3, x3, [x1], #16
|
||||
b.lt 1b
|
||||
|
||||
bl bootmain
|
||||
|
||||
.end
|
||||
.func el2_setup
|
||||
el2_setup:
|
||||
mrs x0, CurrentEL
|
||||
lsr x0, x0, #2
|
||||
and x0, x0, #3
|
||||
cmp x0, #2
|
||||
beq 1f
|
||||
ret
|
||||
|
||||
/* Hyp configuration. */
|
||||
1:
|
||||
mov x0, #(1 << 31)
|
||||
msr hcr_el2, x0
|
||||
|
||||
/* Generic timers. */
|
||||
mrs x0, cnthctl_el2
|
||||
orr x0, x0, #3 // Enable EL1 physicaltimers
|
||||
msr cnthctl_el2, x0
|
||||
|
||||
/* Populate ID registers. */
|
||||
mrs x0, midr_el1
|
||||
mrs x1, mpidr_el1
|
||||
msr vpidr_el2, x0
|
||||
msr vmpidr_el2, x1
|
||||
|
||||
/* Disable Coprocessor traps. */
|
||||
mov x0, #0x33ff
|
||||
msr cptr_el2, x0 // Disable copro. traps to EL2
|
||||
|
||||
msr hstr_el2, xzr // Disable CP15 traps to EL2
|
||||
|
||||
mov x0, sp
|
||||
msr sp_el1, x0
|
||||
|
||||
mrs x0, sctlr_el1
|
||||
orr x0, x0, #(1 << 0)
|
||||
orr x0, x0, #(1 << 2)
|
||||
msr sctlr_el1, x0
|
||||
|
||||
/* spsr */
|
||||
mov x0, #SPSR_EL2_VALUE
|
||||
msr spsr_el2, x0
|
||||
msr elr_el2, lr
|
||||
eret
|
||||
.endfunc
|
||||
|
||||
.end
|
||||
|
||||
+1
-1
@@ -1,6 +1,6 @@
|
||||
export CROSS_COMPILE ?= aarch64-none-elf-
|
||||
export DEVICE = -mtune=cortex-a55 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie
|
||||
export CFLAGS := $(DEVICE) -Wall -Werror -O2 -g -fno-omit-frame-pointer -fPIC
|
||||
export CFLAGS := $(DEVICE) -Wall -Werror -O0 -g -fno-omit-frame-pointer -fPIC
|
||||
# export AFLAGS := -c $(DEVICE) -x assembler-with-cpp -D__ASSEMBLY__ -gdwarf-2
|
||||
export LFLAGS := $(DEVICE) -Wl,-T -Wl,$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/nxp_ls1028.lds -Wl,--start-group,-lgcc,-lc,--end-group
|
||||
export CXXFLAGS :=
|
||||
|
||||
+21
-17
@@ -46,33 +46,35 @@ ENTRY( _boot_start )
|
||||
|
||||
MEMORY {
|
||||
phy_ddr3 (rwx) : ORIGIN = 0x0000000010000000, LENGTH = 1024M
|
||||
vir_ddr3 (rwx) : ORIGIN = 0x000000604040D000, LENGTH = 1024M
|
||||
vir_ddr3 (rwx) : ORIGIN = 0x000000601040E000, LENGTH = 1024M
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.start_sec : {
|
||||
. = ALIGN(0x1000);
|
||||
. = ORIGIN(phy_ddr3);
|
||||
/* initialization start checkpoint. */
|
||||
|
||||
boot.o(.text)
|
||||
bootmmu.o(.text .text.*)
|
||||
ns16550.o(.text .text.*)
|
||||
_start_image_addr = .;
|
||||
|
||||
boot.o(.rodata .rodata.*)
|
||||
bootmmu.o(.rodata .rodata.*)
|
||||
ns16550.o(.rodata .rodata.*)
|
||||
boot.o(.text)
|
||||
bootmmu.o(.text .text.*)
|
||||
/* ns16550.o(.text .text.*) */
|
||||
|
||||
boot.o(.data .data.*)
|
||||
bootmmu.o(.data .data.*)
|
||||
ns16550.o(.data .data.*)
|
||||
boot.o(.rodata .rodata.*)
|
||||
bootmmu.o(.rodata .rodata.*)
|
||||
/* ns16550.o(.rodata .rodata.*) */
|
||||
|
||||
PROVIDE(boot_start_addr = .);
|
||||
boot.o(.data .data.*)
|
||||
bootmmu.o(.data .data.*)
|
||||
/* ns16550.o(.data .data.*) */
|
||||
|
||||
boot.o(.bss .bss.* COMMON)
|
||||
bootmmu.o(.bss .bss.* COMMON)
|
||||
ns16550.o(.bss .bss.* COMMON)
|
||||
PROVIDE(boot_start_addr = .);
|
||||
|
||||
boot.o(.bss .bss.* COMMON)
|
||||
bootmmu.o(.bss .bss.* COMMON)
|
||||
/* ns16550.o(.bss .bss.* COMMON) */
|
||||
|
||||
/* stack for booting code. */
|
||||
. = ALIGN(0x1000);
|
||||
@@ -85,7 +87,7 @@ SECTIONS
|
||||
PROVIDE(boot_end_addr = .);
|
||||
} > phy_ddr3
|
||||
|
||||
.text : AT(0x1040D000) {
|
||||
.text : AT(0x1040E000) {
|
||||
. = ALIGN(0x1000);
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
} > vir_ddr3
|
||||
@@ -107,12 +109,14 @@ SECTIONS
|
||||
PROVIDE(_binary_default_fs_start = .);
|
||||
*(.rawdata_memfs*)
|
||||
PROVIDE(_binary_default_fs_end = .);
|
||||
PROVIDE(__init_array_start = .);
|
||||
PROVIDE(__init_array_end = .);
|
||||
} > vir_ddr3
|
||||
|
||||
. = ALIGN(0x1000);
|
||||
PROVIDE(kernel_data_begin = .);
|
||||
|
||||
_image_size = . - 0x0000006040000000;
|
||||
_image_size = . - 0x0000006010000000;
|
||||
.bss : {
|
||||
PROVIDE(__bss_start__ = .);
|
||||
*(.bss .bss.* COMMON)
|
||||
|
||||
Reference in New Issue
Block a user