8-core SMP successfully started and 16G memory management

.gitignore

@@ -3,3 +3,7 @@
 *libmusl.a
 *liblwip.a
 .DS_Store
+Ubiquitous/XiZi_AIoT/services/app/bin/*
+Ubiquitous/XiZi_AIoT/build/*
+Ubiquitous/XiZi_AIoT/services/app/fs.img
+Ubiquitous/XiZi_AIoT/services/tools/mkfs/mkfs

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/core.h

@@ -33,7 +33,7 @@ Modification:
 #define NO_INT 0x80 // disable IRQ.
 #define DIS_INT 0xc0 // disable both IRQ and FIQ.
 
-#define MODE_STACK_SIZE 0x1000
+#define MODE_STACK_SIZE 0x4000
 
 //! @name SPSR fields
 //@{
@@ -73,7 +73,7 @@ Modification:
 
 #include "cortex_a55.h"
 
-#define NR_CPU 4 // maximum number of CPUs
+#define NR_CPU 8 // maximum number of CPUs
 
 __attribute__((always_inline)) static inline uint64_t EL0_mode() // Set ARM mode to EL0
 {

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3588/3588.lds

@@ -46,7 +46,7 @@ ENTRY( _boot_start )
 
 MEMORY {
   phy_ddr3 (rwx)      : ORIGIN = 0x0000000010000000, LENGTH = 1024M
-  vir_ddr3 (rwx)      : ORIGIN = 0x000000601040E000, LENGTH = 1024M
+  vir_ddr3 (rwx)      : ORIGIN = 0x0000006010a0c000, LENGTH = 1024M
 }
 
 
@@ -87,7 +87,7 @@ SECTIONS
 		PROVIDE(boot_end_addr = .);
 	} > phy_ddr3
 
-  .text : AT(0x1040E000) {
+  .text : AT(0x10a0c000) {
     . = ALIGN(0x1000);
     *(.text .text.* .gnu.linkonce.t.*)
   } > vir_ddr3

Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/3588/memlayout.h

@@ -35,9 +35,10 @@ Modification:
 
 /* A55 physical memory layout */
 #define PHY_MEM_BASE            (0x0000000010000000ULL)
-#define PHY_USER_FREEMEM_BASE   (0x0000000040000000ULL)
+#define PHY_KERN_STOP           (0x00000000e0000000ULL)
-#define PHY_USER_FREEMEM_TOP    (0x00000000e0000000ULL)
+#define PHY_USER_FREEMEM_BASE   (0x0000000100000000ULL)
-#define PHY_MEM_STOP            (0x00000000e0000000ULL)
+#define PHY_USER_FREEMEM_TOP    (0x0000000400000000ULL)
+#define PHY_MEM_STOP            (0x0000000400000000ULL)
 
 /* PTE-PAGE_SIZE */
 #define LEVEL4_PTE_SHIFT    12
@@ -58,7 +59,7 @@ Modification:
 #define NUM_TOPLEVEL_PDE    NUM_LEVEL2_PDE 
 
 #define PAGE_SIZE           LEVEL4_PTE_SIZE
-#define MAX_NR_FREE_PAGES   ((PHY_USER_FREEMEM_BASE - PHY_MEM_BASE) >> LEVEL4_PTE_SHIFT)
+#define MAX_NR_FREE_PAGES   ((PHY_KERN_STOP - PHY_MEM_BASE) >> LEVEL4_PTE_SHIFT)
 
 /* Deivce memory layout */
 #define DEV_PHYMEM_BASE     (0x00000000F0000000ULL)

Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/bootmmu.c

@@ -63,9 +63,15 @@ uint64_t boot_l2pgdir[NUM_LEVEL2_PDE] __attribute__((aligned(0x1000))) = { 0 };
 
 uint64_t boot_dev_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 };
 uint64_t boot_kern_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 };
+uint64_t boot_kern_l3pgdir2[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 };
+uint64_t boot_kern_l3pgdir3[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 };
+uint64_t boot_kern_l3pgdir4[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 };
 
 uint64_t boot_dev_l4pgdirs[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 };
 uint64_t boot_kern_l4pgdirs[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 };
+uint64_t boot_kern_l4pgdirs2[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 };
+uint64_t boot_kern_l4pgdirs3[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 };
+uint64_t boot_kern_l4pgdirs4[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 };
 
 static void build_boot_pgdir()
 {
@@ -96,7 +102,10 @@ static void build_boot_pgdir()
         // identical mem
         boot_l2pgdir[(PHY_MEM_BASE >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
         boot_l2pgdir[(P2V_WO(PHY_MEM_BASE) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
-
+        boot_l2pgdir[(P2V_WO(0x40000000) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir2 | L2_TYPE_TAB | L2_PTE_VALID;
+        boot_l2pgdir[(P2V_WO(0x80000000) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir3 | L2_TYPE_TAB | L2_PTE_VALID;
+        boot_l2pgdir[(P2V_WO(0xc0000000) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir4 | L2_TYPE_TAB | L2_PTE_VALID;
+        // Create a page table from 0x0 to 0x40000000
         cur_mem_paddr = ALIGNDOWN((uint64_t)0x00000000ULL, PAGE_SIZE);
         for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) {
             boot_kern_l3pgdir[i] = (uint64_t)boot_kern_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID;
@@ -107,6 +116,41 @@ static void build_boot_pgdir()
                 cur_mem_paddr += PAGE_SIZE;
             }
         }
+        // Create a page table from 0x40000000 to 0x80000000
+        cur_mem_paddr = ALIGNDOWN((uint64_t)0x40000000ULL, PAGE_SIZE);
+        for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) {
+            boot_kern_l3pgdir2[i] = (uint64_t)boot_kern_l4pgdirs2[i] | L3_TYPE_TAB | L3_PTE_VALID;
+
+            for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) {
+                boot_kern_l4pgdirs2[i][j] = cur_mem_paddr | 0x713;
+
+                cur_mem_paddr += PAGE_SIZE;
+            }
+        }
+        // Create a page table from 0x80000000 to 0xc0000000
+        cur_mem_paddr = ALIGNDOWN((uint64_t)0x80000000ULL, PAGE_SIZE);
+        for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) {
+            boot_kern_l3pgdir3[i] = (uint64_t)boot_kern_l4pgdirs3[i] | L3_TYPE_TAB | L3_PTE_VALID;
+
+            for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) {
+                boot_kern_l4pgdirs3[i][j] = cur_mem_paddr | 0x713;
+
+                cur_mem_paddr += PAGE_SIZE;
+            }
+        }
+        // Create a page table from 0xc0000000 to 0xe0000000
+        cur_mem_paddr = ALIGNDOWN((uint64_t)0xc0000000ULL, PAGE_SIZE);
+        for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) {
+            boot_kern_l3pgdir4[i] = (uint64_t)boot_kern_l4pgdirs4[i] | L3_TYPE_TAB | L3_PTE_VALID;
+            if(cur_mem_paddr >= 0xe0000000){
+                break;
+            }
+            for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) {
+                boot_kern_l4pgdirs4[i][j] = cur_mem_paddr | 0x713;
+
+                cur_mem_paddr += PAGE_SIZE;
+            }
+        }
 
         built = true;
     }

Ubiquitous/XiZi_AIoT/services/app/Makefile

@@ -127,6 +127,6 @@ test_net: test_net.o lwip_service.o libipc.o session.o libserial.o printf.o usys
 %.o: %.S
 	@${cc} ${cflags} ${c_useropts} -o $@ -c $< 
 
-eth_hal: test_gmac.o hal_gmac.o hal_gmac_3568.o hal_base.o hal_bsp.o hal_pinctrl_v2.o hal_cru.o hal_gpio.o hal_timer.o hal_cru_rk3568.o system_rk3568.o hal_debug.o libserial.o printf.o libmem.o usyscall.o arch_usyscall.o session.o libipc.o 
+eth_hal: test_gmac.o hal_gmac.o hal_gmac_3588.o hal_base.o hal_bsp.o hal_pinctrl_v2.o hal_cru.o hal_gpio.o hal_timer.o hal_cru_rk3588.o system_rk3588.o hal_debug.o libserial.o printf.o libmem.o usyscall.o arch_usyscall.o session.o libipc.o 
 	@${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
 	@${objdump} -S $@ > $@.asm

Ubiquitous/XiZi_AIoT/services/drivers/3588/hal/Makefile

@@ -42,7 +42,7 @@ INC_DIR = 	-I$(KERNEL_ROOT)/services/app \
 
 
 objs =  hal_gmac.o \
-		hal_gmac_3568.o \
+		hal_gmac_3588.o \
 		test_gmac.o \
 		hal_base.o \
 		hal_bsp.o \
@@ -50,9 +50,9 @@ objs =  hal_gmac.o \
 		hal_cru.o \
 		hal_gpio.o \
 		hal_timer.o \
-		hal_cru_rk3568.o \
+		hal_cru_rk3588.o \
 		hal_debug.o \
-		system_rk3568.o \
+		system_rk3588.o \
 
 all: ${objs}
 	@mv $^ $(KERNEL_ROOT)/services/app

Ubiquitous/XiZi_AIoT/softkernel/include/buddy.h

@@ -36,7 +36,7 @@ Modification:
 #include <stdbool.h>
 #include <stdint.h>
 
-#define MAX_BUDDY_ORDER (14)
+#define MAX_BUDDY_ORDER (18)
 
 #define FREE_LIST_INDEX(order) \
     (1 << order)

Ubiquitous/XiZi_AIoT/softkernel/main.c

@@ -78,7 +78,6 @@ int main(void)
         secondary_cpu_hardkernel_init(cpu_id, &hardkernel_tag);
         spinlock_unlock(&whole_kernel_lock);
     } 
- LOG_PRINTF("CPU %d coming \n", cpu_id);  
     spinlock_lock(&whole_kernel_lock);
     if (cpu_id == 0) {
         /* init softkernel */
@@ -104,7 +103,6 @@ int main(void)
     struct SchedulerRightGroup scheduler_rights;
     assert(AchieveResourceTag(&scheduler_rights.mmu_driver_tag, &hardkernel_tag, "mmu-ac-resource"));
     assert(AchieveResourceTag(&scheduler_rights.intr_driver_tag, &hardkernel_tag, "intr-ac-resource"));
-    LOG_PRINTF("CPU %d init done\n", cpu_id);
     spinlock_unlock(&whole_kernel_lock);
 
     // sync memory

Ubiquitous/XiZi_AIoT/softkernel/memory/kalloc.c

@@ -40,9 +40,9 @@ extern uintptr_t kernel_data_end[];
 bool module_phymem_init()
 {
     uintptr_t kern_freemem_start = V2P(kernel_data_end);
-    uintptr_t kern_freemem_end = PHY_USER_FREEMEM_BASE;
+    uintptr_t kern_freemem_end = PHY_KERN_STOP;
     uintptr_t user_freemem_start = PHY_USER_FREEMEM_BASE;
-    uintptr_t user_freemem_end = PHY_MEM_STOP;
+    uintptr_t user_freemem_end = PHY_USER_FREEMEM_TOP;
     user_phy_freemem_buddy.pages = NULL;
     KBuddySysInit(&kern_virtmem_buddy, kern_freemem_start, kern_freemem_end);
     KBuddyInit(&user_phy_freemem_buddy, user_freemem_start, user_freemem_end);

Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable.c

@@ -265,7 +265,7 @@ void load_kern_pgdir(struct TraceTag* mmu_driver_tag, struct TraceTag* intr_driv
     _p_pgtbl_mmu_access->MmuDevPteAttr(&dev_attr);
 
     // kern mem
-    _map_pages((uintptr_t*)kern_pgdir.pd_addr, KERN_MEM_BASE, PHY_MEM_BASE, (PHY_MEM_STOP - PHY_MEM_BASE), kern_attr);
+    _map_pages((uintptr_t*)kern_pgdir.pd_addr, KERN_MEM_BASE, PHY_MEM_BASE, (PHY_KERN_STOP - PHY_MEM_BASE), kern_attr);
     // dev mem
     _map_pages((uintptr_t*)kern_pgdir.pd_addr, DEV_VRTMEM_BASE, DEV_PHYMEM_BASE, DEV_MEM_SIZE, dev_attr);
 

Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_state.c

@@ -113,7 +113,7 @@ void show_mem(void)
 {
     SHOWINFO_BORDER_LINE();
 
-    uint64_t total = (PHY_MEM_STOP - V2P(kernel_data_end));
+    uint64_t total = (PHY_MEM_STOP - V2P(kernel_data_end) - 0x20000000);
     uint64_t user_dynamic_free = 0;
     uint64_t kernel_free = 0;
     for (int j = 0; j < MAX_BUDDY_ORDER; j++) {