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Support virt armv8.(Todo: fix clock intr)

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This commit is contained in:
TXuian
2024-05-27 14:57:58 +08:00
parent 80f80b64f0
commit 71cf0c667c
58 changed files with 590 additions and 454 deletions
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Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/context_switch.S
+24 -18
View File
@@ -26,25 +26,31 @@ History:
.global context_switch
context_switch:
# Save store original context to stack
stp x29, lr, [sp, #-16]!
stp x27, x28, [sp, #-16]!
stp x25, x26, [sp, #-16]!
stp x23, x24, [sp, #-16]!
stp x21, x22, [sp, #-16]!
stp x19, x20, [sp, #-16]!
# Switch stacks
mov x19, sp
str x19, [x0]
mov sp, x1
mov x9, sp
mov x10, sp
# restore context from stack
ldp x19, x20, [sp], #16
ldp x21, x22, [sp], #16
ldp x23, x24, [sp], #16
ldp x25, x26, [sp], #16
ldp x27, x28, [sp], #16
ldp x29, lr, [sp], #16
sub x9, x9, #16 * 7
stp x10/*sp*/, x18, [x9, #16 * 0]
stp x19, x20, [x9, #16 * 1]
stp x21, x22, [x9, #16 * 2]
stp x23, x24, [x9, #16 * 3]
stp x25, x26, [x9, #16 * 4]
stp x27, x28, [x9, #16 * 5]
stp x29, x30, [x9, #16 * 6]
str x9, [x0]
mov x9, x1
ldp x10/*sp*/, x18, [x9, #16 * 0]
ldp x19, x20, [x9, #16 * 1]
ldp x21, x22, [x9, #16 * 2]
ldp x23, x24, [x9, #16 * 3]
ldp x25, x26, [x9, #16 * 4]
ldp x27, x28, [x9, #16 * 5]
ldp x29, x30, [x9, #16 * 6]
add x9, x9, #16 * 7
mov sp, x9
ret
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/core.h
+2 -2
View File
@@ -77,7 +77,7 @@ Modification:
__attribute__((always_inline)) static inline uint64_t EL0_mode() // Set ARM mode to EL0
{
uint64_t val;
uint64_t val = 0;
__asm__ __volatile__(
"mrs %0, spsr_el1"
@@ -126,7 +126,7 @@ extern void task_prepare_enter(void);
__attribute__((__always_inline__)) static inline void arch_init_context(struct context* ctx)
{
memset(ctx, 0, sizeof(*ctx));
ctx->x30 = (uint64_t)(task_prepare_enter);
ctx->x30 = (uintptr_t)(task_prepare_enter + 4);
}
struct trapframe {
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/include/cortex_a72.h
+2 -2
View File
@@ -63,10 +63,10 @@ Modification:
#define ISB() __asm__ volatile("isb\n\t")
#define _ARM_MRS(coproc, opcode1, Rt, CRn, CRm, opcode2) \
asm volatile("mrc p" #coproc ", " #opcode1 ", %[output], c" #CRn ", c" #CRm ", " #opcode2 "\n" : [output] "=r"(Rt))
__asm__ volatile("mrc p" #coproc ", " #opcode1 ", %[output], c" #CRn ", c" #CRm ", " #opcode2 "\n" : [output] "=r"(Rt))
#define _ARM_MSR(coproc, opcode1, Rt, CRn, CRm, opcode2) \
asm volatile("mcr p" #coproc ", " #opcode1 ", %[input], c" #CRn ", c" #CRm ", " #opcode2 "\n" ::[input] "r"(Rt))
__asm__ volatile("mcr p" #coproc ", " #opcode1 ", %[input], c" #CRn ", c" #CRm ", " #opcode2 "\n" ::[input] "r"(Rt))
// #define WriteReg(value, address) (*(volatile unsigned int*)(address) = (value))
// #define ReadReg(address) (*(volatile unsigned int*)(address))
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/nxp_ls1028.lds
+4 -13
View File
@@ -45,24 +45,13 @@ ENTRY( _ENTRY )
ENTRY( _boot_start )
MEMORY {
/**
phy_ddr3 (rwx) : ORIGIN = 0x0000000040000000, LENGTH = 0x8000000
vir_ddr3 (rwx) : ORIGIN = 0xffffff8040010000, LENGTH = 0x8000000
*/
phy_ddr3 (rwx) : ORIGIN = 0x0000000040000000, LENGTH = 1024M
vir_ddr3 (rwx) : ORIGIN = 0x0000006040635000, LENGTH = 1024M
/* vir_ddr3 (rwx) : ORIGIN = 0xffffffE040635000, LENGTH = 1024M */
}
SECTIONS
{
/*
* ensure that entry.S / _entry is at 0x40000000(physical address),
* where qemu's -kernel jumps.
* 0x40000000(PA) is 0xffffff8040000000(VA);
*/
.start_sec : {
. = ALIGN(0x1000);
/* initialization start checkpoint. */
@@ -102,19 +91,21 @@ SECTIONS
.data : {
*(.data .data.*)
. = ALIGN(1000);
. = ALIGN(0x1000);
PROVIDE(_binary_fs_img_start = .);
*(.rawdata_fs_img*)
PROVIDE(_binary_fs_img_end = .);
. = ALIGN(0x1000);
PROVIDE(_binary_init_start = .);
*(.rawdata_init*)
PROVIDE(_binary_init_end = .);
. = ALIGN(0x1000);
PROVIDE(_binary_default_fs_start = .);
*(.rawdata_memfs*)
PROVIDE(_binary_default_fs_end = .);
} > vir_ddr3
. = ALIGN(1000);
. = ALIGN(0x1000);
PROVIDE(kernel_data_begin = .);
_image_size = . - 0x0000006040000000;