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TXuian
2024-03-05 16:18:01 +08:00
parent 5f9478251b
commit 6489d94dcd
5 changed files with 4 additions and 10 deletions
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Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_zynq7000-zc702/boot.S
+3 -3
View File
@@ -140,7 +140,7 @@ OKToRun:
mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
mcr p15, 0, r0, c7, c5, 6 /* Invalidate branch predictor array */
bl invalidate_dcache /* invalidate dcache */
bl boot_invalidate_dcache /* invalidate dcache */
/* Disable MMU, if enabled */
mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 */
@@ -193,14 +193,14 @@ OKToRun:
/*
*************************************************************************
*
* invalidate_dcache - invalidate the entire d-cache by set/way
* boot_invalidate_dcache - invalidate the entire d-cache by set/way
*
* Note: for Cortex-A9, there is no cp instruction for invalidating
* the whole D-cache. Need to invalidate each line.
*
*************************************************************************
*/
invalidate_dcache:
boot_invalidate_dcache:
mrc p15, 1, r0, c0, c0, 1 /* read CLIDR */
ands r3, r0, #0x7000000
mov r3, r3, lsr #23 /* cache level value (naturally aligned) */
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_zynq7000-zc702/zynq7000-zc702.lds
-2
View File
@@ -36,8 +36,6 @@ SECTIONS
.start_sec : {
. = ALIGN(0x1000);
*(.vectors)
/* read only area. */
boot.o(.text)
xil-crt0.o(.text .text.*)