Support armv8.(TODO: fix clock)
This commit is contained in:
TXuian
+3
-131
@@ -11,125 +11,6 @@
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.global _boot_start
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.global primary_cpu_init
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//_entry:
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// mrs x1, mpidr_el1
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// and x1, x1, #0x3
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// cbz x1, entry // primary
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# b entryothers // secondary
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//entry:
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// clear .bss
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// adrp x1, __bss_start__
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// ldr w2, =bss_size
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// 1:
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// // cbz w2, 2f
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// str xzr, [x1], #8
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// sub w2, w2, #1
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// b 1b
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// 2:
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// // set up entry pagetable
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// //
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// // Phase 1.
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// // map the kernel code identically.
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// // map [0x40000000,PA(end)) to [0x40000000,PA(end))
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// // memory type is normal
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// //
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// // Phase 2.
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// // map the kernel code.
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// // map [0xffffff8040000000,VA(end)) to [0x40000000,PA(end))
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// // memory type is normal.
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// // Phase 1
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// // map [0x40000000,PA(end)) to [0x40000000,PA(end))
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// adrp x0, l2entrypgt
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// mov x1, #0x00000000
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// ldr x2, =V2P_WO(end)-1
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// lsr x3, x1, #PXSHIFT(2)
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// and x3, x3, #PXMASK // PX(2, x1)
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// lsr x4, x2, #PXSHIFT(2)
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// and x4, x4, #PXMASK // PX(2, x2)
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// mov x5, #(PTE_AF | PTE_INDX(AI_NORMAL_NC_IDX) | PTE_VALID) // entry attr
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// orr x6, x1, x5 // block entry
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// l2epgt_loop:
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// str x6, [x0, x3, lsl #3] // l2entrypgt[l2idx] = block entry
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// add x3, x3, #1 // next index
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// add x6, x6, #0x200000 // next block, block size is 2MB
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// cmp x3, x4
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// b.ls l2epgt_loop // if start va idx <= end va idx
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// adrp x0, l1entrypgt
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// lsr x3, x1, #PXSHIFT(1)
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// and x3, x3, #PXMASK // start va level1 index
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// mov x4, #(PTE_TABLE | PTE_VALID) // entry attr
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// adrp x5, l2entrypgt
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// orr x6, x4, x5 // table entry
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// str x6, [x0, x3, lsl #3] // l1entrypgt[l1idx] = table entry
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// // Phase 2
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// // map [0xffffff8040000000,VA(end)) to [0x40000000,PA(end))
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// adrp x0, l2kpgt
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// mov x1, #0x00000000 // start pa
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// ldr x2, =V2P_WO(end)-1 // end pa
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// mov x3, #KERN_MEM_BASE
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// add x4, x1, x3 // start va
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// add x5, x2, x3 // end va
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// lsr x6, x4, #PXSHIFT(2)
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// and x6, x6, #PXMASK // x6 = PX(2,x4)
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// lsr x7, x5, #PXSHIFT(2)
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// and x7, x7, #PXMASK // x7 = PX(2,x5)
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// mov x8, #(PTE_AF | PTE_INDX(AI_NORMAL_NC_IDX) | PTE_VALID) // entry attr
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// orr x9, x1, x8 // block entry
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// l2kpgt_loop:
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// str x9, [x0, x6, lsl #3] // l2entrypgt[l2idx] = block entry
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// add x6, x6, #1 // next index
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// add x9, x9, #0x200000 // next block, block size is 2MB
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// cmp x6, x7
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// b.ls l2kpgt_loop // if start va idx <= end va idx
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// adrp x0, l1kpgt
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// lsr x5, x4, #PXSHIFT(1)
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// and x5, x5, #PXMASK // x5 = PX(1,x4)
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// mov x6, #(PTE_TABLE | PTE_VALID) // entry attr
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// adrp x7, l2kpgt
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// orr x8, x6, x7 // table entry
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// str x8, [x0, x5, lsl #3] // l1kpgt[l1idx] = table entry
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// entryothers: // secondary CPU starts here
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// // load pagetable
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// adrp x0, l1entrypgt
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// adrp x1, l1kpgt
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// msr ttbr0_el1, x0
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// msr ttbr1_el1, x1
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// // setup tcr
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// ldr x0, =(TCR_T0SZ(25)|TCR_T1SZ(25)|TCR_TG0(0)|TCR_TG1(2)|TCR_IPS(0))
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// msr tcr_el1, x0
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// // setup mair
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// ldr x1, =((MT_DEVICE_nGnRnE<<(8*AI_DEVICE_nGnRnE_IDX)) | (MT_NORMAL_NC<<(8*AI_NORMAL_NC_IDX)))
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// msr mair_el1, x1
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// ISB
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// ldr x1, =_start // x1 = VA(_start)
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// // enable paging
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// mrs x0, sctlr_el1
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// orr x0, x0, #1
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// msr sctlr_el1, x0
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// br x1 // jump to higher address (0xffffff8000000000~)
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_boot_start:
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// set up a stack for C.
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// stack0 is declared in start.c,
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@@ -138,7 +19,8 @@ _boot_start:
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// cpuid = mpidr_el1 & 0xff
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// save r0 for cores 1-3, r0 arg field passed by ROM
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// r0 is a function pointer for secondary cpus
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mov x4, x0
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// mov x4, x0
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mrs x0, spsr_el1 /* Enter EL1 (Exception Level 1) */
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bic x0, x0, #0x1f
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@@ -153,11 +35,6 @@ _boot_start:
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MSR CPACR_EL1, X1
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ISB
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/* Clear A bit of SCTLR */
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MRS x0, SCTLR_EL1
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BIC x0, x0, #0x2
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MSR SCTLR_EL1, x0
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// clear some registers
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msr elr_el1, XZR
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@@ -171,7 +48,7 @@ _boot_start:
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mul x3, x2, x1
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sub x0, x0, x3
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MOV X2, #ARM_MODE_EL1_h | DIS_INT
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MOV X2, #ARM_MODE_EL1_h | DIS_INT
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MSR SPSR_EL1, X2
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mov sp, x0
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SUB x0, x0,x1
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@@ -199,11 +76,6 @@ primary_cpu_init:
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mov x1, #0 // argv
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mov x2, #0 // env
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// jump to main()
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//b main
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//b . // spin
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bl bootmain
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.end
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+1
-5
@@ -1,11 +1,7 @@
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export CROSS_COMPILE ?= aarch64-none-elf-
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# export DEVICE = -march=armv8-a -mtune=cortex-a72 -ffreestanding -fno-common -nostdlib
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export DEVICE = -mtune=cortex-a72 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie
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# export CFLAGS := $(DEVICE) -Wall -Werror -O0 -g -fno-omit-frame-pointer -fPIC
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export CFLAGS := $(DEVICE) -O0 -g -fno-omit-frame-pointer -fPIC
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export CFLAGS := $(DEVICE) -Wall -Werror -O0 -g -fno-omit-frame-pointer -fPIC
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# export AFLAGS := -c $(DEVICE) -x assembler-with-cpp -D__ASSEMBLY__ -gdwarf-2
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# export LFLAGS := $(DEVICE) -Wl,-Map=XiZi-imx6q-sabrelite.map,-cref,-u,_boot_start -T $(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_imx6q-sabrelite/nxp_imx6q_sabrelite.lds
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# export LFLAGS := $(DEVICE) -mcmodel=large -Wl,-Map=XiZi-ok1028a-c.map,-cref,-u,_start -T $(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/nxp_ls1028.lds -Wl,--start-group,-lgcc,-lc,--end-group
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export LFLAGS := $(DEVICE) -Wl,-T -Wl,$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/nxp_ls1028.lds -Wl,--start-group,-lgcc,-lc,--end-group
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export CXXFLAGS :=
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+11
@@ -1,3 +1,14 @@
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/*
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* Copyright (c) 2020 AIIT XUOS Lab
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* XiUOS is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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* See the Mulan PSL v2 for more details.
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*/
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#ifndef INC_SYSREGS_H_
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#define INC_SYSREGS_H_
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