Fix conflict with the merge request to master

Ubiquitous/XiZi_AIoT/.config

@@ -0,0 +1,18 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# XiZi_AIoT Project Configuration
+#
+CONFIG_BOARD_IMX6Q_SABRELITE=y
+CONFIG_ARCH_ARM=y
+
+#
+# imx6q sabrelite feature
+#
+
+#
+# Lib
+#
+CONFIG_LIB=y
+CONFIG_LIB_POSIX=y
+CONFIG_LIB_NEWLIB=y
+# CONFIG_LIB_MUSLLIB is not set

Ubiquitous/XiZi_AIoT/.gitignore

@@ -0,0 +1 @@
+build

Ubiquitous/XiZi_AIoT/Makefile

@@ -145,3 +145,12 @@ distclean:
 	@rm -f .config*
 	@rm -f $(KERNEL_ROOT)/lib/musllib/libmusl.a
 	@rm -f $(KERNEL_ROOT)/board/*/.config
+
+
+# Run qemu with config discribed in README.md.
+.PHONY: qemu-default
+qemu-default:
+	qemu-system-arm -M sabrelite -m 1G -smp 4 -cpu cortex-a9 \
+    -display none -serial null -serial stdio \
+    -kernel ./build/XiZi-imx6q-sabrelite.elf
+

Ubiquitous/XiZi_AIoT/compiler.mk

@@ -34,7 +34,7 @@ $(eval LOCALC := $(addprefix $(BUILD_DIR)/,$(COBJ))) \
 $(eval OBJS += $(LOCALC)) \
 $(if $(strip $(LOCALC)),$(eval $(LOCALC): $(1)
 	@if [ ! -d $$(@D) ]; then mkdir -p $$(@D); fi
-	@echo cc $$< 
+	@echo cc $(subst $(KERNEL_ROOT)/,,$$<)
 	@/bin/echo -n $(dir $(LOCALC)) >>$(KERNEL_ROOT)/build/make.dep
 	@($(CROSS_COMPILE)gcc -MM $$(CFLAGS) -c $$<) >>$(KERNEL_ROOT)/build/make.dep
 	@$(CROSS_COMPILE)gcc $$(CFLAGS) -c $$< -o $$@))

Ubiquitous/XiZi_AIoT/hardkernel/arch/Makefile

@@ -1,6 +1,4 @@
-ifneq ($(findstring $(BOARD), 3568 imx6q-sabrelite zynq7000-zc702), )
 SRC_DIR := arm
-endif
 ifneq ($(findstring $(BOARD), jh7110), )
 SRC_DIR := riscv
 endif

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/core.h

@@ -76,6 +76,13 @@ Modification:
 
 #define NR_CPU 4
 
+static inline uint64_t arch_current_tick()
+{
+    uint32_t tick = 0;
+    __asm__ __volatile__("MRC p15, 0, %0, c9, c13, 0" : "=r"(tick)); // %0 应该是输出操作数
+    return (uint64_t)tick;
+}
+
 __attribute__((always_inline, optimize("O0"))) static inline uint32_t user_mode()
 {
     uint32_t val;

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_imx6q-sabrelite/boot.S

@@ -77,7 +77,7 @@ _boot_start:
     mul     r3, 	r2, r1
     sub     r0, 	r0, r3
            
-    msr     CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT
+    msr     CPSR_c, #ARM_MODE_SVC | I_BIT 
     mov     sp, 	r0
     sub     r0, 	r0, r1 
     

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_imx6q-sabrelite/include/regsepit.h

@@ -0,0 +1,710 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_EPIT_REGISTERS_H__
+#define __HW_EPIT_REGISTERS_H__
+
+#include "regs.h"
+#include "soc_memory_map.h"
+
+/*
+ * i.MX6SL EPIT
+ *
+ * EPIT
+ *
+ * Registers defined in this header file:
+ * - HW_EPIT_CR - Control register
+ * - HW_EPIT_SR - Status register
+ * - HW_EPIT_LR - Load register
+ * - HW_EPIT_CMPR - Compare register
+ * - HW_EPIT_CNR - Counter register
+ *
+ * - hw_epit_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_EPIT_BASE
+#define HW_EPIT_INSTANCE_COUNT (2) //!< Number of instances of the EPIT module.
+#define HW_EPIT1 (1) //!< Instance number for EPIT1.
+#define HW_EPIT2 (2) //!< Instance number for EPIT2.
+#define REGS_EPIT1_BASE USERLAND_MMIO_P2V(0x020d0000) //!< Base address for EPIT instance number 1.
+#define REGS_EPIT2_BASE USERLAND_MMIO_P2V(0x020d4000) //!< Base address for EPIT instance number 2.
+
+//! @brief Get the base address of EPIT by instance number.
+//! @param x EPIT instance number, from 1 through 2.
+#define REGS_EPIT_BASE(x) ((x) == HW_EPIT1 ? REGS_EPIT1_BASE : (x) == HW_EPIT2 ? REGS_EPIT2_BASE \
+                                                                               : 0x00d00000)
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of EPIT.
+#define REGS_EPIT_INSTANCE(b) ((b) == REGS_EPIT1_BASE ? HW_EPIT1 : (b) == REGS_EPIT2_BASE ? HW_EPIT2 \
+                                                                                          : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_EPIT_CR - Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_EPIT_CR - Control register (RW)
+ *
+ * Reset value: 0x00000000
+ *
+ * The EPIT control register (EPIT_CR) is used to configure the operating settings of the EPIT. It
+ * contains the clock division prescaler value and also the interrupt enable bit. Additionally, it
+ * contains other control bits which are described below. Peripheral Bus Write access to EPIT
+ * Control Register (EPIT_CR) results in one cycle of the wait state, while other valid peripheral
+ * bus accesses are with 0 wait state.
+ */
+typedef union _hw_epit_cr {
+    reg32_t U;
+    struct _hw_epit_cr_bitfields {
+        unsigned EN : 1; //!< [0] This bit enables the EPIT.
+        unsigned ENMOD : 1; //!< [1] EPIT enable mode.
+        unsigned OCIEN : 1; //!< [2] Output compare interrupt enable.
+        unsigned RLD : 1; //!< [3] Counter reload control.
+        unsigned PRESCALAR : 12; //!< [15:4] Counter clock prescaler value.
+        unsigned SWR : 1; //!< [16] Software reset.
+        unsigned IOVW : 1; //!< [17] EPIT counter overwrite enable.
+        unsigned DBGEN : 1; //!< [18] This bit is used to keep the EPIT functional in debug mode.
+        unsigned WAITEN : 1; //!< [19] This read/write control bit enables the operation of the EPIT during wait mode.
+        unsigned RESERVED0 : 1; //!< [20] Reserved.
+        unsigned STOPEN : 1; //!< [21] EPIT stop mode enable.
+        unsigned OM : 2; //!< [23:22] EPIT output mode.This bit field determines the mode of EPIT output on the output pin.
+        unsigned CLKSRC : 2; //!< [25:24] Select clock source
+        unsigned RESERVED1 : 6; //!< [31:26] Reserved.
+    } B;
+} hw_epit_cr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire EPIT_CR register
+ */
+//@{
+#define HW_EPIT_CR_ADDR(x) (REGS_EPIT_BASE(x) + 0x0)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_EPIT_CR(x) (*(volatile hw_epit_cr_t*)HW_EPIT_CR_ADDR(x))
+#define HW_EPIT_CR_RD(x) (HW_EPIT_CR(x).U)
+#define HW_EPIT_CR_WR(x, v) (HW_EPIT_CR(x).U = (v))
+#define HW_EPIT_CR_SET(x, v) (HW_EPIT_CR_WR(x, HW_EPIT_CR_RD(x) | (v)))
+#define HW_EPIT_CR_CLR(x, v) (HW_EPIT_CR_WR(x, HW_EPIT_CR_RD(x) & ~(v)))
+#define HW_EPIT_CR_TOG(x, v) (HW_EPIT_CR_WR(x, HW_EPIT_CR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * constants & macros for individual EPIT_CR bitfields
+ */
+
+/*! @name Register EPIT_CR, field EN[0] (RW)
+ *
+ * This bit enables the EPIT. EPIT counter and prescaler value when EPIT is enabled (EN = 1), is
+ * dependent upon ENMOD and RLD bit as described for ENMOD bit. It is recommended that all registers
+ * be properly programmed before setting this bit. This bit is reset by a hardware reset. A software
+ * reset does not affect this bit.
+ *
+ * Values:
+ * - 0 - EPIT is disabled
+ * - 1 - EPIT is enabled
+ */
+//@{
+#define BP_EPIT_CR_EN (0) //!< Bit position for EPIT_CR_EN.
+#define BM_EPIT_CR_EN (0x00000001) //!< Bit mask for EPIT_CR_EN.
+
+//! @brief Get value of EPIT_CR_EN from a register value.
+#define BG_EPIT_CR_EN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_EN) >> BP_EPIT_CR_EN)
+
+//! @brief Format value for bitfield EPIT_CR_EN.
+#define BF_EPIT_CR_EN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_EN) & BM_EPIT_CR_EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EN field to a new value.
+#define BW_EPIT_CR_EN(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_EN) | BF_EPIT_CR_EN(v)))
+#endif
+//@}
+
+/*! @name Register EPIT_CR, field ENMOD[1] (RW)
+ *
+ * EPIT enable mode. When EPIT is disabled (EN=0), both main counter and prescaler counter freeze
+ * their count at current count values. ENMOD bit is a r/w bit that determines the counter value
+ * when the EPIT is enabled again by setting EN bit. If ENMOD bit is set, then main counter is
+ * loaded with the load value (If RLD=1)/ 0xFFFF_FFFF (If RLD=0) and prescaler counter is reset,
+ * when EPIT is enabled (EN=1). If ENMOD is programmed to 0 then both main counter and prescaler
+ * counter restart counting from their frozen values when EPIT is enabled (EN=1). If EPIT is
+ * programmed to be disabled in a low-power mode (STOP/WAIT/DEBUG), then both the main counter and
+ * the prescaler counter freeze at their current count values when EPIT enters low-power mode. When
+ * EPIT exits the low-power mode, both main counter and prescaler counter start counting from their
+ * frozen values irrespective of the ENMOD bit. This bit is reset by a hardware reset. A software
+ * reset does not affect this bit.
+ *
+ * Values:
+ * - 0 - Counter starts counting from the value it had when it was disabled.
+ * - 1 - Counter starts count from load value (RLD=1) or 0xFFFF_FFFF (If RLD=0)
+ */
+//@{
+#define BP_EPIT_CR_ENMOD (1) //!< Bit position for EPIT_CR_ENMOD.
+#define BM_EPIT_CR_ENMOD (0x00000002) //!< Bit mask for EPIT_CR_ENMOD.
+
+//! @brief Get value of EPIT_CR_ENMOD from a register value.
+#define BG_EPIT_CR_ENMOD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_ENMOD) >> BP_EPIT_CR_ENMOD)
+
+//! @brief Format value for bitfield EPIT_CR_ENMOD.
+#define BF_EPIT_CR_ENMOD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_ENMOD) & BM_EPIT_CR_ENMOD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ENMOD field to a new value.
+#define BW_EPIT_CR_ENMOD(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_ENMOD) | BF_EPIT_CR_ENMOD(v)))
+#endif
+//@}
+
+/*! @name Register EPIT_CR, field OCIEN[2] (RW)
+ *
+ * Output compare interrupt enable. This bit enables the generation of interrupt on occurrence of
+ * compare event.
+ *
+ * Values:
+ * - 0 - Compare interrupt disabled
+ * - 1 - Compare interrupt enabled
+ */
+//@{
+#define BP_EPIT_CR_OCIEN (2) //!< Bit position for EPIT_CR_OCIEN.
+#define BM_EPIT_CR_OCIEN (0x00000004) //!< Bit mask for EPIT_CR_OCIEN.
+
+//! @brief Get value of EPIT_CR_OCIEN from a register value.
+#define BG_EPIT_CR_OCIEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_OCIEN) >> BP_EPIT_CR_OCIEN)
+
+//! @brief Format value for bitfield EPIT_CR_OCIEN.
+#define BF_EPIT_CR_OCIEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_OCIEN) & BM_EPIT_CR_OCIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OCIEN field to a new value.
+#define BW_EPIT_CR_OCIEN(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_OCIEN) | BF_EPIT_CR_OCIEN(v)))
+#endif
+//@}
+
+/*! @name Register EPIT_CR, field RLD[3] (RW)
+ *
+ * Counter reload control. This bit is cleared by hardware reset. It decides the counter
+ * functionality, whether to run in free-running mode or set-and-forget mode.
+ *
+ * Values:
+ * - 0 - When the counter reaches zero it rolls over to 0xFFFF_FFFF (free-running mode)
+ * - 1 - When the counter reaches zero it reloads from the modulus register (set-and-forget mode)
+ */
+//@{
+#define BP_EPIT_CR_RLD (3) //!< Bit position for EPIT_CR_RLD.
+#define BM_EPIT_CR_RLD (0x00000008) //!< Bit mask for EPIT_CR_RLD.
+
+//! @brief Get value of EPIT_CR_RLD from a register value.
+#define BG_EPIT_CR_RLD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_RLD) >> BP_EPIT_CR_RLD)
+
+//! @brief Format value for bitfield EPIT_CR_RLD.
+#define BF_EPIT_CR_RLD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_RLD) & BM_EPIT_CR_RLD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RLD field to a new value.
+#define BW_EPIT_CR_RLD(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_RLD) | BF_EPIT_CR_RLD(v)))
+#endif
+//@}
+
+/*! @name Register EPIT_CR, field PRESCALAR[15:4] (RW)
+ *
+ * Counter clock prescaler value. This bit field determines the prescaler value by which the clock
+ * is divided before it goes to the counter
+ *
+ * Values:
+ * - 0x000 - Divide by 1
+ * - 0x001 - Divide by 2...
+ * - 0xFFF - Divide by 4096
+ */
+//@{
+#define BP_EPIT_CR_PRESCALAR (4) //!< Bit position for EPIT_CR_PRESCALAR.
+#define BM_EPIT_CR_PRESCALAR (0x0000fff0) //!< Bit mask for EPIT_CR_PRESCALAR.
+
+//! @brief Get value of EPIT_CR_PRESCALAR from a register value.
+#define BG_EPIT_CR_PRESCALAR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_PRESCALAR) >> BP_EPIT_CR_PRESCALAR)
+
+//! @brief Format value for bitfield EPIT_CR_PRESCALAR.
+#define BF_EPIT_CR_PRESCALAR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_PRESCALAR) & BM_EPIT_CR_PRESCALAR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PRESCALAR field to a new value.
+#define BW_EPIT_CR_PRESCALAR(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_PRESCALAR) | BF_EPIT_CR_PRESCALAR(v)))
+#endif
+//@}
+
+/*! @name Register EPIT_CR, field SWR[16] (RW)
+ *
+ * Software reset. The EPIT is reset when this bit is set to 1. It is a self clearing bit. This bit
+ * is set when the block is in reset state and is cleared when the reset procedure is over. Setting
+ * this bit resets all the registers to their reset values, except for the EN, ENMOD, STOPEN, WAITEN
+ * and DBGEN bits in this control register
+ *
+ * Values:
+ * - 0 - EPIT is out of reset
+ * - 1 - EPIT is undergoing reset
+ */
+//@{
+#define BP_EPIT_CR_SWR (16) //!< Bit position for EPIT_CR_SWR.
+#define BM_EPIT_CR_SWR (0x00010000) //!< Bit mask for EPIT_CR_SWR.
+
+//! @brief Get value of EPIT_CR_SWR from a register value.
+#define BG_EPIT_CR_SWR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_SWR) >> BP_EPIT_CR_SWR)
+
+//! @brief Format value for bitfield EPIT_CR_SWR.
+#define BF_EPIT_CR_SWR(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_SWR) & BM_EPIT_CR_SWR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SWR field to a new value.
+#define BW_EPIT_CR_SWR(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_SWR) | BF_EPIT_CR_SWR(v)))
+#endif
+//@}
+
+/*! @name Register EPIT_CR, field IOVW[17] (RW)
+ *
+ * EPIT counter overwrite enable. This bit controls the counter data when the modulus register is
+ * written. When this bit is set, all writes to the load register overwrites the counter contents
+ * and the counter starts subsequently counting down from the programmed value.
+ *
+ * Values:
+ * - 0 - Write to load register does not result in counter value being overwritten.
+ * - 1 - Write to load register results in immediate overwriting of counter value.
+ */
+//@{
+#define BP_EPIT_CR_IOVW (17) //!< Bit position for EPIT_CR_IOVW.
+#define BM_EPIT_CR_IOVW (0x00020000) //!< Bit mask for EPIT_CR_IOVW.
+
+//! @brief Get value of EPIT_CR_IOVW from a register value.
+#define BG_EPIT_CR_IOVW(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_IOVW) >> BP_EPIT_CR_IOVW)
+
+//! @brief Format value for bitfield EPIT_CR_IOVW.
+#define BF_EPIT_CR_IOVW(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_IOVW) & BM_EPIT_CR_IOVW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IOVW field to a new value.
+#define BW_EPIT_CR_IOVW(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_IOVW) | BF_EPIT_CR_IOVW(v)))
+#endif
+//@}
+
+/*! @name Register EPIT_CR, field DBGEN[18] (RW)
+ *
+ * This bit is used to keep the EPIT functional in debug mode. When this bit is cleared, the input
+ * clock is gated off in debug mode.This bit is reset by hardware reset. A software reset does not
+ * affect this bit.
+ *
+ * Values:
+ * - 0 - Inactive in debug mode
+ * - 1 - Active in debug mode
+ */
+//@{
+#define BP_EPIT_CR_DBGEN (18) //!< Bit position for EPIT_CR_DBGEN.
+#define BM_EPIT_CR_DBGEN (0x00040000) //!< Bit mask for EPIT_CR_DBGEN.
+
+//! @brief Get value of EPIT_CR_DBGEN from a register value.
+#define BG_EPIT_CR_DBGEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_DBGEN) >> BP_EPIT_CR_DBGEN)
+
+//! @brief Format value for bitfield EPIT_CR_DBGEN.
+#define BF_EPIT_CR_DBGEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_DBGEN) & BM_EPIT_CR_DBGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DBGEN field to a new value.
+#define BW_EPIT_CR_DBGEN(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_DBGEN) | BF_EPIT_CR_DBGEN(v)))
+#endif
+//@}
+
+/*! @name Register EPIT_CR, field WAITEN[19] (RW)
+ *
+ * This read/write control bit enables the operation of the EPIT during wait mode. This bit is reset
+ * by a hardware reset. A software reset does not affect this bit.
+ *
+ * Values:
+ * - 0 - EPIT is disabled in wait mode
+ * - 1 - EPIT is enabled in wait mode
+ */
+//@{
+#define BP_EPIT_CR_WAITEN (19) //!< Bit position for EPIT_CR_WAITEN.
+#define BM_EPIT_CR_WAITEN (0x00080000) //!< Bit mask for EPIT_CR_WAITEN.
+
+//! @brief Get value of EPIT_CR_WAITEN from a register value.
+#define BG_EPIT_CR_WAITEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_WAITEN) >> BP_EPIT_CR_WAITEN)
+
+//! @brief Format value for bitfield EPIT_CR_WAITEN.
+#define BF_EPIT_CR_WAITEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_WAITEN) & BM_EPIT_CR_WAITEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WAITEN field to a new value.
+#define BW_EPIT_CR_WAITEN(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_WAITEN) | BF_EPIT_CR_WAITEN(v)))
+#endif
+//@}
+
+/*! @name Register EPIT_CR, field STOPEN[21] (RW)
+ *
+ * EPIT stop mode enable. This read/write control bit enables the operation of the EPIT during stop
+ * mode. This bit is reset by a hardware reset and unaffected by software reset.
+ *
+ * Values:
+ * - 0 - EPIT is disabled in stop mode
+ * - 1 - EPIT is enabled in stop mode
+ */
+//@{
+#define BP_EPIT_CR_STOPEN (21) //!< Bit position for EPIT_CR_STOPEN.
+#define BM_EPIT_CR_STOPEN (0x00200000) //!< Bit mask for EPIT_CR_STOPEN.
+
+//! @brief Get value of EPIT_CR_STOPEN from a register value.
+#define BG_EPIT_CR_STOPEN(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_STOPEN) >> BP_EPIT_CR_STOPEN)
+
+//! @brief Format value for bitfield EPIT_CR_STOPEN.
+#define BF_EPIT_CR_STOPEN(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_STOPEN) & BM_EPIT_CR_STOPEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the STOPEN field to a new value.
+#define BW_EPIT_CR_STOPEN(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_STOPEN) | BF_EPIT_CR_STOPEN(v)))
+#endif
+//@}
+
+/*! @name Register EPIT_CR, field OM[23:22] (RW)
+ *
+ * EPIT output mode.This bit field determines the mode of EPIT output on the output pin.
+ *
+ * Values:
+ * - 00 - EPIT output is disconnected from pad
+ * - 01 - Toggle output pin
+ * - 10 - Clear output pin
+ * - 11 - Set output pin
+ */
+//@{
+#define BP_EPIT_CR_OM (22) //!< Bit position for EPIT_CR_OM.
+#define BM_EPIT_CR_OM (0x00c00000) //!< Bit mask for EPIT_CR_OM.
+
+//! @brief Get value of EPIT_CR_OM from a register value.
+#define BG_EPIT_CR_OM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_OM) >> BP_EPIT_CR_OM)
+
+//! @brief Format value for bitfield EPIT_CR_OM.
+#define BF_EPIT_CR_OM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_OM) & BM_EPIT_CR_OM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OM field to a new value.
+#define BW_EPIT_CR_OM(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_OM) | BF_EPIT_CR_OM(v)))
+#endif
+//@}
+
+/*! @name Register EPIT_CR, field CLKSRC[25:24] (RW)
+ *
+ * Select clock source These bits determine which clock input is to be selected for running the
+ * counter. This field value should only be changed when the EPIT is disabled by clearing the EN bit
+ * in this register. For other programming requirements while changing clock source, refer to .
+ *
+ * Values:
+ * - 00 - Clock is off
+ * - 01 - Peripheral clock
+ * - 10 - High-frequency reference clock
+ * - 11 - Low-frequency reference clock
+ */
+//@{
+#define BP_EPIT_CR_CLKSRC (24) //!< Bit position for EPIT_CR_CLKSRC.
+#define BM_EPIT_CR_CLKSRC (0x03000000) //!< Bit mask for EPIT_CR_CLKSRC.
+
+//! @brief Get value of EPIT_CR_CLKSRC from a register value.
+#define BG_EPIT_CR_CLKSRC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_CLKSRC) >> BP_EPIT_CR_CLKSRC)
+
+//! @brief Format value for bitfield EPIT_CR_CLKSRC.
+#define BF_EPIT_CR_CLKSRC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_CLKSRC) & BM_EPIT_CR_CLKSRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLKSRC field to a new value.
+#define BW_EPIT_CR_CLKSRC(x, v) (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_CLKSRC) | BF_EPIT_CR_CLKSRC(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_EPIT_SR - Status register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_EPIT_SR - Status register (RW)
+ *
+ * Reset value: 0x00000000
+ *
+ * The EPIT status register (EPIT_SR) has a single status bit for the output compare event. The bit
+ * is a write 1 to clear bit.
+ */
+typedef union _hw_epit_sr {
+    reg32_t U;
+    struct _hw_epit_sr_bitfields {
+        unsigned OCIF : 1; //!< [0] Output compare interrupt flag.
+        unsigned RESERVED0 : 31; //!< [31:1] Reserved.
+    } B;
+} hw_epit_sr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire EPIT_SR register
+ */
+//@{
+#define HW_EPIT_SR_ADDR(x) (REGS_EPIT_BASE(x) + 0x4)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_EPIT_SR(x) (*(volatile hw_epit_sr_t*)HW_EPIT_SR_ADDR(x))
+#define HW_EPIT_SR_RD(x) (HW_EPIT_SR(x).U)
+#define HW_EPIT_SR_WR(x, v) (HW_EPIT_SR(x).U = (v))
+#define HW_EPIT_SR_SET(x, v) (HW_EPIT_SR_WR(x, HW_EPIT_SR_RD(x) | (v)))
+#define HW_EPIT_SR_CLR(x, v) (HW_EPIT_SR_WR(x, HW_EPIT_SR_RD(x) & ~(v)))
+#define HW_EPIT_SR_TOG(x, v) (HW_EPIT_SR_WR(x, HW_EPIT_SR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * constants & macros for individual EPIT_SR bitfields
+ */
+
+/*! @name Register EPIT_SR, field OCIF[0] (W1C)
+ *
+ * Output compare interrupt flag. This bit is the interrupt flag that is set when the content of
+ * counter equals the content of the compare register (EPIT_CMPR). The bit is a write 1 to clear
+ * bit.
+ *
+ * Values:
+ * - 0 - Compare event has not occurred
+ * - 1 - Compare event occurred
+ */
+//@{
+#define BP_EPIT_SR_OCIF (0) //!< Bit position for EPIT_SR_OCIF.
+#define BM_EPIT_SR_OCIF (0x00000001) //!< Bit mask for EPIT_SR_OCIF.
+
+//! @brief Get value of EPIT_SR_OCIF from a register value.
+#define BG_EPIT_SR_OCIF(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_SR_OCIF) >> BP_EPIT_SR_OCIF)
+
+//! @brief Format value for bitfield EPIT_SR_OCIF.
+#define BF_EPIT_SR_OCIF(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_SR_OCIF) & BM_EPIT_SR_OCIF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OCIF field to a new value.
+#define BW_EPIT_SR_OCIF(x, v) (HW_EPIT_SR_WR(x, (HW_EPIT_SR_RD(x) & ~BM_EPIT_SR_OCIF) | BF_EPIT_SR_OCIF(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_EPIT_LR - Load register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_EPIT_LR - Load register (RW)
+ *
+ * Reset value: 0xffffffff
+ *
+ * The EPIT load register (EPIT_LR) contains the value that is to be loaded into the counter when
+ * EPIT counter reaches zero if the RLD bit in EPIT_CR is set. If the IOVW bit in the EPIT_CR is set
+ * then a write to this register overwrites the value of the EPIT counter register in addition to
+ * updating this registers value. This overwrite feature is active even if the RLD bit is not set.
+ */
+typedef union _hw_epit_lr {
+    reg32_t U;
+    struct _hw_epit_lr_bitfields {
+        unsigned LOAD : 32; //!< [31:0] Load value.
+    } B;
+} hw_epit_lr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire EPIT_LR register
+ */
+//@{
+#define HW_EPIT_LR_ADDR(x) (REGS_EPIT_BASE(x) + 0x8)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_EPIT_LR(x) (*(volatile hw_epit_lr_t*)HW_EPIT_LR_ADDR(x))
+#define HW_EPIT_LR_RD(x) (HW_EPIT_LR(x).U)
+#define HW_EPIT_LR_WR(x, v) (HW_EPIT_LR(x).U = (v))
+#define HW_EPIT_LR_SET(x, v) (HW_EPIT_LR_WR(x, HW_EPIT_LR_RD(x) | (v)))
+#define HW_EPIT_LR_CLR(x, v) (HW_EPIT_LR_WR(x, HW_EPIT_LR_RD(x) & ~(v)))
+#define HW_EPIT_LR_TOG(x, v) (HW_EPIT_LR_WR(x, HW_EPIT_LR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * constants & macros for individual EPIT_LR bitfields
+ */
+
+/*! @name Register EPIT_LR, field LOAD[31:0] (RW)
+ *
+ * Load value. Value that is loaded into the counter at the start of each count cycle.
+ */
+//@{
+#define BP_EPIT_LR_LOAD (0) //!< Bit position for EPIT_LR_LOAD.
+#define BM_EPIT_LR_LOAD (0xffffffff) //!< Bit mask for EPIT_LR_LOAD.
+
+//! @brief Get value of EPIT_LR_LOAD from a register value.
+#define BG_EPIT_LR_LOAD(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_LR_LOAD) >> BP_EPIT_LR_LOAD)
+
+//! @brief Format value for bitfield EPIT_LR_LOAD.
+#define BF_EPIT_LR_LOAD(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_LR_LOAD) & BM_EPIT_LR_LOAD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LOAD field to a new value.
+#define BW_EPIT_LR_LOAD(x, v) (HW_EPIT_LR_WR(x, (HW_EPIT_LR_RD(x) & ~BM_EPIT_LR_LOAD) | BF_EPIT_LR_LOAD(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_EPIT_CMPR - Compare register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_EPIT_CMPR - Compare register (RW)
+ *
+ * Reset value: 0x00000000
+ *
+ * The EPIT compare register (EPIT_CMPR) holds the value that determines when a compare event is
+ * generated.
+ */
+typedef union _hw_epit_cmpr {
+    reg32_t U;
+    struct _hw_epit_cmpr_bitfields {
+        unsigned COMPARE : 32; //!< [31:0] Compare Value.
+    } B;
+} hw_epit_cmpr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire EPIT_CMPR register
+ */
+//@{
+#define HW_EPIT_CMPR_ADDR(x) (REGS_EPIT_BASE(x) + 0xc)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_EPIT_CMPR(x) (*(volatile hw_epit_cmpr_t*)HW_EPIT_CMPR_ADDR(x))
+#define HW_EPIT_CMPR_RD(x) (HW_EPIT_CMPR(x).U)
+#define HW_EPIT_CMPR_WR(x, v) (HW_EPIT_CMPR(x).U = (v))
+#define HW_EPIT_CMPR_SET(x, v) (HW_EPIT_CMPR_WR(x, HW_EPIT_CMPR_RD(x) | (v)))
+#define HW_EPIT_CMPR_CLR(x, v) (HW_EPIT_CMPR_WR(x, HW_EPIT_CMPR_RD(x) & ~(v)))
+#define HW_EPIT_CMPR_TOG(x, v) (HW_EPIT_CMPR_WR(x, HW_EPIT_CMPR_RD(x) ^ (v)))
+#endif
+//@}
+
+/*
+ * constants & macros for individual EPIT_CMPR bitfields
+ */
+
+/*! @name Register EPIT_CMPR, field COMPARE[31:0] (RW)
+ *
+ * Compare Value. When the counter value equals this bit field value a compare event is generated.
+ */
+//@{
+#define BP_EPIT_CMPR_COMPARE (0) //!< Bit position for EPIT_CMPR_COMPARE.
+#define BM_EPIT_CMPR_COMPARE (0xffffffff) //!< Bit mask for EPIT_CMPR_COMPARE.
+
+//! @brief Get value of EPIT_CMPR_COMPARE from a register value.
+#define BG_EPIT_CMPR_COMPARE(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CMPR_COMPARE) >> BP_EPIT_CMPR_COMPARE)
+
+//! @brief Format value for bitfield EPIT_CMPR_COMPARE.
+#define BF_EPIT_CMPR_COMPARE(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CMPR_COMPARE) & BM_EPIT_CMPR_COMPARE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COMPARE field to a new value.
+#define BW_EPIT_CMPR_COMPARE(x, v) (HW_EPIT_CMPR_WR(x, (HW_EPIT_CMPR_RD(x) & ~BM_EPIT_CMPR_COMPARE) | BF_EPIT_CMPR_COMPARE(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_EPIT_CNR - Counter register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_EPIT_CNR - Counter register (RO)
+ *
+ * Reset value: 0xffffffff
+ *
+ * The EPIT counter register (EPIT_CNR) contains the current count value and can be read at any time
+ * without disturbing the counter. This is a read-only register and any attempt to write into it
+ * generates a transfer error. But if the IOVW bit in EPIT_CR is set, the value of this register can
+ * be overwritten with a write to EPIT_LR. This change is reflected when this register is
+ * subsequently read.
+ */
+typedef union _hw_epit_cnr {
+    reg32_t U;
+    struct _hw_epit_cnr_bitfields {
+        unsigned COUNT : 32; //!< [31:0] Counter value.
+    } B;
+} hw_epit_cnr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire EPIT_CNR register
+ */
+//@{
+#define HW_EPIT_CNR_ADDR(x) (REGS_EPIT_BASE(x) + 0x10)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_EPIT_CNR(x) (*(volatile hw_epit_cnr_t*)HW_EPIT_CNR_ADDR(x))
+#define HW_EPIT_CNR_RD(x) (HW_EPIT_CNR(x).U)
+#endif
+//@}
+
+/*
+ * constants & macros for individual EPIT_CNR bitfields
+ */
+
+/*! @name Register EPIT_CNR, field COUNT[31:0] (RO)
+ *
+ * Counter value. This contains the current value of the counter.
+ */
+//@{
+#define BP_EPIT_CNR_COUNT (0) //!< Bit position for EPIT_CNR_COUNT.
+#define BM_EPIT_CNR_COUNT (0xffffffff) //!< Bit mask for EPIT_CNR_COUNT.
+
+//! @brief Get value of EPIT_CNR_COUNT from a register value.
+#define BG_EPIT_CNR_COUNT(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CNR_COUNT) >> BP_EPIT_CNR_COUNT)
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_epit_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All EPIT module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_epit {
+    volatile hw_epit_cr_t CR; //!< Control register
+    volatile hw_epit_sr_t SR; //!< Status register
+    volatile hw_epit_lr_t LR; //!< Load register
+    volatile hw_epit_cmpr_t CMPR; //!< Compare register
+    volatile hw_epit_cnr_t CNR; //!< Counter register
+} hw_epit_t;
+#pragma pack()
+
+//! @brief Macro to access all EPIT registers.
+//! @param x EPIT instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_EPIT(0)</code>.
+#define HW_EPIT(x) (*(hw_epit_t*)REGS_EPIT_BASE(x))
+#endif
+
+#endif // __HW_EPIT_REGISTERS_H__
+// v18/121106/1.2.2
+// EOF

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/core.h

@@ -33,7 +33,7 @@ Modification:
 #define NO_INT 0x80 // disable IRQ.
 #define DIS_INT 0xc0 // disable both IRQ and FIQ.
 
-#define MODE_STACK_SIZE 0x1000
+#define MODE_STACK_SIZE 0x2000
 
 //! @name SPSR fields
 //@{
@@ -75,6 +75,13 @@ Modification:
 
 #define NR_CPU 4 // maximum number of CPUs
 
+static inline uintptr_t arch_curr_tick()
+{
+    uint64_t x;
+    __asm__ volatile("mrs %0, cntpct_el0" : "=r"(x));
+    return x;
+}
+
 __attribute__((always_inline)) static inline uint64_t EL0_mode() // Set ARM mode to EL0
 {
     uint64_t val = 0;

Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/registers.h

@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2020 AIIT XUOS Lab
+ * XiUOS is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *        http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ */
+#ifndef INC_SYSREGS_H_
+#define INC_SYSREGS_H_
+
+/* SCTLR_EL1, System Control Register (EL1). */
+#define SCTLR_RESERVED \
+    ((3 << 28) | (3 << 22) | (1 << 20) | (1 << 11) | (1 << 8) | (1 << 7))
+#define SCTLR_EE_LITTLE_ENDIAN (0 << 25)
+#define SCTLR_E0E_LITTLE_ENDIAN (0 << 24)
+#define SCTLR_I_CACHE (1 << 12)
+#define SCTLR_D_CACHE (1 << 2)
+#define SCTLR_MMU_DISABLED (0 << 0)
+#define SCTLR_MMU_ENABLED (1 << 0)
+
+#define SCTLR_VALUE_MMU_DISABLED                                       \
+    (SCTLR_RESERVED | SCTLR_EE_LITTLE_ENDIAN | SCTLR_E0E_LITTLE_ENDIAN \
+        | SCTLR_I_CACHE | SCTLR_D_CACHE | SCTLR_MMU_DISABLED)
+
+/* HCR_EL2, Hypervisor Configuration Register (EL2). */
+#define HCR_RW (1 << 31)
+#define HCR_VALUE HCR_RW
+
+/* CPACR_EL1, Architectural Feature Access Control Register. */
+#define CPACR_FP_EN (3 << 20)
+#define CPACR_TRACE_EN (0 << 28)
+#define CPACR_VALUE (CPACR_FP_EN | CPACR_TRACE_EN)
+
+/* SCR_EL3, Secure Configuration Register (EL3). */
+#define SCR_RESERVED (3 << 4)
+#define SCR_RW (1 << 10)
+#define SCR_HCE (1 << 8)
+#define SCR_SMD (1 << 7)
+#define SCR_NS (1 << 0)
+#define SCR_VALUE (SCR_RESERVED | SCR_RW | SCR_HCE | SCR_SMD | SCR_NS)
+
+/* SPSR_EL1/2/3, Saved Program Status Register. */
+#define SPSR_MASK_ALL (7 << 6)
+#define SPSR_EL1h (5 << 0)
+#define SPSR_EL2h (9 << 0)
+#define SPSR_EL3_VALUE (SPSR_MASK_ALL | SPSR_EL2h)
+#define SPSR_EL2_VALUE (SPSR_MASK_ALL | SPSR_EL1h)
+
+/* Exception Class in ESR_EL1. */
+#define EC_SHIFT 26
+#define EC_UNKNOWN 0x00
+#define EC_SVC64 0x15
+#define EC_DABORT 0x24
+#define EC_IABORT 0x20
+
+#define PTE_VALID 1 // level 0,1,2 descriptor: valid
+#define PTE_TABLE 2 // level 0,1,2 descriptor: table
+#define PTE_V 3 // level 3 descriptor: valid
+// PTE_AF(Access Flag)
+//
+// 0 -- this block entry has not yet.
+// 1 -- this block entry has been used.
+#define PTE_AF (1 << 10)
+// PTE_AP(Access Permission) is 2bit field.
+//        EL0   EL1
+// 00 --   x    RW
+// 01 --  RW    RW
+// 10 --   x    RO
+// 11 --  RO    RO
+#define PTE_AP(ap) (((ap) & 3) << 6)
+#define PTE_U PTE_AP(1)
+#define PTE_RO PTE_AP(2)
+#define PTE_URO PTE_AP(3)
+#define PTE_PXN (1UL << 53) // Privileged eXecute Never
+#define PTE_UXN (1UL << 54) // Unprivileged(user) eXecute Never
+#define PTE_XN (PTE_PXN | PTE_UXN) // eXecute Never
+
+// attribute index
+// index is set by mair_el1
+#define AI_DEVICE_nGnRnE_IDX 0x0
+#define AI_NORMAL_NC_IDX 0x1
+
+// memory type
+#define MT_DEVICE_nGnRnE 0x0
+#define MT_NORMAL_NC 0x44
+
+#define PTE_INDX(i) (((i) & 7) << 2)
+#define PTE_DEVICE PTE_INDX(AI_DEVICE_nGnRnE_IDX)
+#define PTE_NORMAL PTE_INDX(AI_NORMAL_NC_IDX)
+
+// shift a physical address to the right place for a PTE.
+#define PA2PTE(pa) ((uint64_t)(pa) & 0xfffffffff000)
+#define PTE2PA(pte) ((uint64_t)(pte) & 0xfffffffff000)
+
+#define PTE_FLAGS(pte) ((pte) & (0x600000000003ff))
+
+// translation control register
+// #define TCR_T0SZ(n) ((n) & 0x3f)
+// #define TCR_TG0(n) (((n) & 0x3) << 14)
+// #define TCR_T1SZ(n) (((n) & 0x3f) << 16)
+// #define TCR_TG1(n) (((n) & 0x3) << 30)
+// #define TCR_IPS(n) (((n) & 0x7) << 32)
+
+#define ISS_MASK 0xFFFFFF
+
+#endif // INC_SYSREGS_H_

Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/Makefile

@@ -1,6 +1,4 @@
-ifneq ($(findstring $(BOARD), 3568 imx6q-sabrelite zynq7000-zc702), )
 SRC_DIR := arm
-endif
 ifneq ($(findstring $(BOARD), jh7110), )
 SRC_DIR := riscv
 endif

Ubiquitous/XiZi_AIoT/hardkernel/clock/Makefile

@@ -1,6 +1,4 @@
-ifneq ($(findstring $(BOARD), 3568 imx6q-sabrelite zynq7000-zc702), )
+SRC_DIR:= arm
-SRC_DIR := arm
-endif
 ifneq ($(findstring $(BOARD), jh7110), )
 SRC_DIR := riscv
 endif

Ubiquitous/XiZi_AIoT/hardkernel/hardkernel_init.c

@@ -129,7 +129,7 @@ static bool xizi_gpt_init()
         return false;
     }
     // register clock handler to intr
-    struct XiziTrapDriver* p_intr_driver = (struct XiziTrapDriver*)AchieveResource(&intr_driver_tag);
+    struct XiziTrapDriver* p_intr_driver = GetSysObject(struct XiziTrapDriver, &intr_driver_tag);
     p_intr_driver->bind_irq_handler(p_clock_driver->get_clock_int(), xizi_clock_handler);
     p_intr_driver->single_irq_enable(p_clock_driver->get_clock_int(), 0, 0);
     return true;

Ubiquitous/XiZi_AIoT/hardkernel/intr/Makefile

@@ -1,10 +1,7 @@
-ifneq ($(findstring $(BOARD), 3568 imx6q-sabrelite zynq7000-zc702), )
 SRC_DIR := arm
-endif
 ifneq ($(findstring $(BOARD), jh7110), )
 SRC_DIR := riscv
 endif
-
 SRC_FILES := spinlock.c
 
 include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/imx6q-sabrelite/trap_common.c

@@ -57,7 +57,7 @@ void panic(char* s)
 /* stack for different mode*/
 static char mode_stack_pages[NR_CPU][NR_MODE_STACKS][MODE_STACK_SIZE];
 extern uint32_t _vector_jumper;
-extern uint32_t _vector_start;
+extern uint32_t* _vector_start;
 extern uint32_t _vector_end;
 
 void init_cpu_mode_stacks(int cpu_id)
@@ -75,7 +75,7 @@ static void _sys_irq_init(int cpu_id)
     /* load exception vectors */
     init_cpu_mode_stacks(cpu_id);
     if (cpu_id == 0) {
-        volatile uint32_t* vector_base = &_vector_start;
+        volatile uint32_t* vector_base = (uint32_t*)&_vector_start;
 
         // Set Interrupt handler start address
         vector_base[1] = (uint32_t)trap_undefined_instruction; // Undefined Instruction

Ubiquitous/XiZi_AIoT/hardkernel/mmu/Makefile

@@ -1,6 +1,4 @@
-ifneq ($(findstring $(BOARD), 3568 imx6q-sabrelite zynq7000-zc702), )
 SRC_DIR := arm
-endif
 ifneq ($(findstring $(BOARD), jh7110), )
 SRC_DIR := riscv
 endif

Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/imx6q-sabrelite/memlayout.h

@@ -73,4 +73,11 @@ Modification:
 #define KERN_MEM_BASE       (0x90000000) // First kernel virtual address
 #define KERN_OFFSET         (KERN_MEM_BASE - PHY_MEM_BASE)
 
+/* virtual and physical addr translate */
+#define V2P(a) ((uint32_t)((uint32_t)(a)-KERN_OFFSET))
+#define P2V(a) ((void*)((void*)(a) + KERN_OFFSET))
+
+#define V2P_WO(x) ((x)-KERN_OFFSET) // same as V2P, but without casts
+#define P2V_WO(x) ((x) + KERN_OFFSET) // same as V2P, but without casts
+
 // clang-format on

Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/include/mmu.h

@@ -92,13 +92,6 @@ When the process switches, the flush TLB is no longer required anymore.
 #define CONTEXTIDR_R(val) __asm__ volatile("mrc p15, 0, %0, c13, c0, 1" : "=r"(val))
 #define CONTEXTIDR_W(val) __asm__ volatile("mcr p15, 0, %0, c13, c0, 1" ::"r"(val))
 
-/* virtual and physical addr translate */
-#define V2P(a) ((uint32_t)((uint32_t)(a)-KERN_OFFSET))
-#define P2V(a) ((void*)((void*)(a) + KERN_OFFSET))
-
-#define V2P_WO(x) ((x)-KERN_OFFSET) // same as V2P, but without casts
-#define P2V_WO(x) ((x) + KERN_OFFSET) // same as V2P, but without casts
-
 #ifndef __ASSEMBLER__
 #include <stdint.h>
 __attribute__((always_inline)) static inline uint32_t v2p(void* a) { return ((uint32_t)(a)) - KERN_MEM_BASE; }

Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/3568/memlayout.h

@@ -36,8 +36,8 @@ Modification:
 /* A55 physical memory layout */
 #define PHY_MEM_BASE            (0x0000000010000000ULL)
 #define PHY_USER_FREEMEM_BASE   (0x0000000040000000ULL)
-#define PHY_USER_FREEMEM_TOP    (0x00000000e0000000ULL)
+#define PHY_USER_FREEMEM_TOP    (0x00000000E0000000ULL)
-#define PHY_MEM_STOP            (0x00000000e0000000ULL)
+#define PHY_MEM_STOP            (0x00000000E0000000ULL)
 
 /* PTE-PAGE_SIZE */
 #define LEVEL4_PTE_SHIFT    12

Ubiquitous/XiZi_AIoT/hardkernel/uart/Makefile

@@ -1,10 +1,7 @@
-ifneq ($(findstring $(BOARD), 3568 imx6q-sabrelite zynq7000-zc702), )
 SRC_DIR := arm
-endif
 ifneq ($(findstring $(BOARD), jh7110), )
 SRC_DIR := riscv
 endif
-
 SRC_FILES := uart_common_ope.c
 
 include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_AIoT/hardkernel/uart/printf.h

@@ -101,5 +101,4 @@ int fctprintf(void (*out)(char character, void* arg), void* arg, const char* for
 }
 #endif
 
-#endif // _PRINTF_H_
+#endif // _PRINTF_H_
-

Ubiquitous/XiZi_AIoT/hardkernel/uart/uart_common_ope.c

@@ -897,7 +897,6 @@ int fctprintf(void (*out)(char character, void* arg), void* arg, const char* for
     return ret;
 }
 
-///////////////////////////////////////////////////////////////////////////////
 __attribute__((weak)) void _debug_uart_putc(int ch) {}
 
 static inline void _out_char_early(char character, void* buffer, size_t idx, size_t maxlen)

Ubiquitous/XiZi_AIoT/kernel_actracer/actracer.c

@@ -41,15 +41,16 @@ static void tracer_init_node(TracerNode* node, char* name, tracemeta_ac_type typ
     node->parent = NULL;
     if (name != NULL) {
         char* p_name = (char*)slab_alloc(&sys_tracer.node_name_allocator);
-        strcpy(p_name, name);
+        if (!p_name) {
-        p_name[TRACER_NODE_NAME_LEN - 1] = '\0';
+            p_name = "BAD_NAME(NOMEM)";
-        node->name = p_name;
+        } else {
-    }
+            strcpy(p_name, name);
-    if (node->type == TRACER_OWNER) {
+            p_name[TRACER_NODE_NAME_LEN - 1] = '\0';
-        doubleListNodeInit(&node->children_guard);
+            node->name = p_name;
-    } else {
+        }
-        node->p_resource = p_resource;
     }
+    doubleListNodeInit(&node->children_guard);
+    node->p_resource = p_resource;
     doubleListNodeInit(&node->list_node);
 }
 
@@ -61,8 +62,8 @@ void sys_tracer_init()
     sys_tracer.sys_tracer_tag.meta = &sys_tracer.root_node;
 
     // init memory allocator
-    slab_init(&sys_tracer.node_allocator, sizeof(TracerNode));
+    slab_init(&sys_tracer.node_allocator, sizeof(TracerNode), "TracerNodeAllocator");
-    slab_init(&sys_tracer.node_name_allocator, sizeof(char[TRACER_NODE_NAME_LEN]));
+    slab_init(&sys_tracer.node_name_allocator, sizeof(char[TRACER_NODE_NAME_LEN]), "TracerNodeNameAllocator");
 }
 
 static char* parse_path(char* path, char* const name)
@@ -84,7 +85,7 @@ static char* parse_path(char* path, char* const name)
     // handle current name
     int len = path - cur_start;
     if (len >= TRACER_NODE_NAME_LEN) {
-        strncpy(name, cur_start, TRACER_NODE_NAME_LEN);
+        strncpy(name, cur_start, TRACER_NODE_NAME_LEN - 1);
         name[TRACER_NODE_NAME_LEN - 1] = '\0';
     } else {
         strncpy(name, cur_start, len);
@@ -149,11 +150,12 @@ bool CreateResourceTag(TraceTag* new_tag, TraceTag* owner, char* name, tracemeta
 {
     assert(owner != NULL);
     if (owner->meta == NULL) {
-        ERROR("Tracer: Empty owner\n");
+        ERROR("Tracer: Empty owner, node name: %s\n", name);
         return false;
     }
-    assert(owner->meta->type == TRACER_OWNER);
+    // assert(owner->meta->type == TRACER_OWNER);
-    if (tracer_find_node_onestep(owner->meta, name) != NULL) {
+    if (type == TRACER_SERVER_IDENTITY_AC_RESOURCE && //
+        tracer_find_node_onestep(owner->meta, name) != NULL) {
         return false;
     }
 
@@ -179,7 +181,7 @@ bool DeleteResource(TraceTag* target, TraceTag* owner)
     assert(target != NULL && owner != NULL);
     assert(owner->meta != NULL && owner->meta->type == TRACER_OWNER);
     if (target->meta == NULL) {
-        ERROR("Tracer: Delete a empty resource\n");
+        ERROR("Tracer: Delete a empty resource, owner: %s\n", owner->meta->name);
         return false;
     }
 
@@ -204,27 +206,37 @@ bool DeleteResource(TraceTag* target, TraceTag* owner)
     return true;
 }
 
-void debug_list_tracetree_inner(TracerNode* cur_node)
+#define debug_print_blanks(n)           \
+    for (int __i = 0; __i < n; __i++) { \
+        DEBUG_PRINTF("  ");             \
+    }
+
+void debug_list_tracetree_inner(TracerNode* cur_node, int nr_blanks)
 {
-    DEBUG("[%s] ", cur_node->name);
+    debug_print_blanks(nr_blanks);
+    if (cur_node->name == NULL) {
+        DEBUG_PRINTF("[ANON %d] ", cur_node->type);
+    } else {
+        DEBUG_PRINTF("[%s %d] ", cur_node->name, cur_node->type);
+    }
     TracerNode* tmp = NULL;
     DOUBLE_LIST_FOR_EACH_ENTRY(tmp, &cur_node->children_guard, list_node)
     {
         if (tmp->name != NULL) {
-            DEBUG("%s ", tmp->name);
+            DEBUG_PRINTF("%s ", tmp->name);
         } else {
-            DEBUG("ANON ");
+            DEBUG_PRINTF("ANON ");
         }
     }
-    DEBUG("\n");
+    DEBUG_PRINTF("\n");
     DOUBLE_LIST_FOR_EACH_ENTRY(tmp, &cur_node->children_guard, list_node)
     {
-        debug_list_tracetree_inner(tmp);
+        debug_list_tracetree_inner(tmp, nr_blanks + 1);
     }
 }
 
 void debug_list_tracetree()
 {
     TracerNode* ref_root = RequireRootTag()->meta;
-    debug_list_tracetree_inner(ref_root);
+    debug_list_tracetree_inner(ref_root, 0);
 }

Ubiquitous/XiZi_AIoT/kernel_actracer/actracer.h

@@ -30,35 +30,12 @@ Modification:
 #include <stdbool.h>
 #include <stdint.h>
 
-#include "list.h"
+#include "actracer_tag.h"
 #include "object_allocator.h"
 
 #define TRACER_NODE_NAME_LEN 32
 
-typedef enum {
+#define GetSysObject(type, target_tag) (type*)AchieveResource(target_tag)
-    TRACER_INVALID = 0,
-    TRACER_OWNER,
-    TRACER_HARDKERNEL_AC_RESOURCE,
-    TRACER_TASK_DESCRIPTOR_AC_RESOURCE,
-    TRACER_SERVER_IDENTITY_AC_RESOURCE,
-    TRACER_MEM_FROM_BUDDY_AC_RESOURCE,
-} tracemeta_ac_type;
-
-typedef struct TracerNode {
-    tracemeta_ac_type type;
-    char* name;
-    union {
-        struct double_list_node children_guard;
-        void* p_resource;
-    };
-    struct TracerNode* parent;
-    struct double_list_node list_node;
-} TracerNode;
-
-/// @brief tag for other module to reference trace meta
-typedef struct TraceTag {
-    TracerNode* meta;
-} TraceTag;
 
 struct SysTracer {
     TracerNode root_node;
@@ -72,4 +49,6 @@ TraceTag* const RequireRootTag();
 bool AchieveResourceTag(struct TraceTag* target, struct TraceTag* owner, char* name);
 void* AchieveResource(struct TraceTag* tag);
 bool CreateResourceTag(struct TraceTag* new_tag, struct TraceTag* owner, char* name, tracemeta_ac_type type, void* p_resource);
-bool DeleteResource(struct TraceTag* target, struct TraceTag* owner);
+bool DeleteResource(struct TraceTag* target, struct TraceTag* owner);
+
+void debug_list_tracetree();

Ubiquitous/XiZi_AIoT/kernel_actracer/actracer_tag.h

@@ -0,0 +1,26 @@
+#pragma once
+#include "list.h"
+
+typedef enum {
+    TRACER_INVALID = 0,
+    TRACER_OWNER,
+    TRACER_HARDKERNEL_AC_RESOURCE,
+    TRACER_TASK_DESCRIPTOR_AC_RESOURCE,
+    TRACER_SERVER_IDENTITY_AC_RESOURCE,
+    TRACER_MEM_SIGNATURE,
+    TRACER_SYSOBJECT,
+} tracemeta_ac_type;
+
+typedef struct TracerNode {
+    tracemeta_ac_type type;
+    char* name;
+    void* p_resource;
+    struct TracerNode* parent;
+    struct double_list_node list_node;
+    struct double_list_node children_guard;
+} TracerNode;
+
+/// @brief tag for other module to reference trace meta
+typedef struct TraceTag {
+    TracerNode* meta;
+} TraceTag;

Ubiquitous/XiZi_AIoT/path_kernel.mk

@@ -63,7 +63,6 @@ KERNELPATHS += \
 	-I$(KERNEL_ROOT)/hardkernel/clock/riscv/rv64gc/$(BOARD)/include \
 	-I$(KERNEL_ROOT)/hardkernel/intr/riscv/rv64gc/ \
 	-I$(KERNEL_ROOT)/hardkernel/intr/riscv/rv64gc/$(BOARD) \
-	-I$(KERNEL_ROOT)/hardkernel/intr/riscv/rv64gc/gicv3 \
 	-I$(KERNEL_ROOT)/hardkernel/mmu/riscv/rv64gc/include  \
 	-I$(KERNEL_ROOT)/hardkernel/mmu/riscv/rv64gc/$(BOARD)  \
 	-I$(KERNEL_ROOT)/hardkernel/uart/riscv/rv64gc/uart_io_for_$(BOARD)/include \

Ubiquitous/XiZi_AIoT/services/Makefile

@@ -1,7 +1,7 @@
 ifeq ($(BOARD), jh7110)
 SRC_DIR := fs shell lib boards tools app
 else 
-SRC_DIR := fs shell lib boards drivers semaphore drivers tools net app 
+SRC_DIR := fs shell lib boards drivers semaphore tools app 
 endif
 
 include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_AIoT/services/app/.gitignore

@@ -0,0 +1,3 @@
+bin
+fs.img
+user.map

Ubiquitous/XiZi_AIoT/services/app/Makefile

@@ -50,12 +50,23 @@ INC_DIR = 	-I$(KERNEL_ROOT)/services/shell/letter-shell \
 			-I$(KERNEL_ROOT)/services/app 
 
 ifeq ($(BOARD), imx6q-sabrelite)
-all: test_fault simple_client simple_server shell fs_server semaphore_server test_semaphore test_ipc_null test_thread test_irq_hdlr test_irq_block test_irq_send eth_driver epit_server test_net lwip  readme.txt | bin
+all: pingpong_client pingpong_server \
+	test_fault simple_client simple_server \
+	shell fs_server semaphore_server \
+	test_sleep test_semaphore test_ipc_null test_thread test_irq_hdlr test_irq_block test_irq_send \
+	eth_driver epit_server  readme.txt | bin
 else 
 ifeq ($(BOARD), jh7110)
-all: shell fs_server | bin
+all: shell fs_server \
+	| bin
 else 
-all: test_fault simple_client simple_server shell fs_server semaphore_server test_ipc_null test_thread test_semaphore test_net lwip readme.txt eth_hal | bin
+all: pingpong_client pingpong_server \
+	test_fault simple_client simple_server \
+	shell fs_server semaphore_server \
+	test_irq_hdlr \
+	test_sleep test_ipc_null test_thread test_semaphore readme.txt \
+	test_context_user \
+	| bin
 endif
 endif
 	../tools/mkfs/mkfs ./fs.img $^
@@ -80,6 +91,22 @@ epit_server: timer.o epit.o ccm_pll.o usyscall.o arch_usyscall.o libserial.o pri
 	@${objdump} -S $@ > $@.asm
 endif
 
+pingpong_client: pingpong_service.o pingpong_client.o libserial.o printf.o libipc.o session.o libfs.o usyscall.o arch_usyscall.o  libmem.o
+	@${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
+	@${objdump} -S $@ > $@.asm
+
+pingpong_server: pingpong_service.o pingpong_server.o libserial.o printf.o libipc.o session.o libfs.o usyscall.o arch_usyscall.o  libmem.o
+	@${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
+	@${objdump} -S $@ > $@.asm
+
+test_sleep: test_sleep.o libserial.o printf.o usyscall.o arch_usyscall.o
+	@${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
+	@${objdump} -S $@ > $@.asm
+	
+test_context_user: test_context_user.o libserial.o printf.o usyscall.o arch_usyscall.o
+	@${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
+	@${objdump} -S $@ > $@.asm
+
 test_semaphore: test_semaphore.o libserial.o printf.o usyscall.o arch_usyscall.o
 	@${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
 	@${objdump} -S $@ > $@.asm
@@ -136,8 +163,4 @@ test_net: test_net.o lwip_service.o libipc.o session.o libserial.o printf.o usys
 	@${cc} ${cflags} ${c_useropts} ${INC_DIR} -o $@ -c $< 
 
 %.o: %.S
-	@${cc} ${cflags} ${c_useropts} -o $@ -c $< 
+	@${cc} ${cflags} ${c_useropts} -o $@ -c $< 
-
-eth_hal: test_gmac.o hal_gmac.o hal_gmac_3568.o hal_base.o hal_bsp.o hal_pinctrl_v2.o hal_cru.o hal_gpio.o hal_timer.o hal_cru_rk3568.o system_rk3568.o hal_debug.o libserial.o printf.o libmem.o usyscall.o arch_usyscall.o session.o libipc.o 
-	@${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
-	@${objdump} -S $@ > $@.asm

Ubiquitous/XiZi_AIoT/services/app/pingpong_client.c

@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2020 AIIT XUOS Lab
+ * XiUOS is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *        http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ */
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include "libfs.h"
+#include "libserial.h"
+#include "pingpong_service.h"
+#include "usyscall.h"
+
+int string_to_integer(const char* str)
+{
+    assert(str);
+    while (*str == ' ') {
+        str++;
+    }
+    int is_positive = 1; // 默认是正
+    if (*str - '+' == 0) {
+        is_positive = 1;
+        str++;
+    }
+    if (*str - '-' == 0) {
+        is_positive = 0;
+        str++;
+    }
+    long long result = 0; // int可能存不下 改为long long较为合适虽然返回值会丢失精度但感觉不要紧
+    while ('0' <= *str && *str <= '9') {
+        result *= 10;
+        result += *str - '0'; // 如'1' ascii的值为 49 '0'的ascii的值为48 相减得到1
+
+        if (result > INT32_MAX || result < INT32_MIN) // 可能出现的溢出问题
+        {
+            return result > INT32_MAX ? INT32_MAX : INT32_MIN;
+        }
+
+        str++;
+    }
+    return is_positive ? (result) : -result;
+}
+
+void itoa(int num, char* str, int radix)
+{
+    int i = 0;
+    int sum;
+    unsigned int num1 = num; // 如果是负数求补码，必须将他的绝对值放在无符号位中在进行求反码
+    char str1[33] = { 0 };
+    if (num < 0) { // 求出负数的补码
+        num = -num;
+        num1 = ~num;
+        num1 += 1;
+    }
+    if (num == 0) {
+        str1[i] = '0';
+
+        i++;
+    }
+    while (num1 != 0) { // 进行进制运算
+        sum = num1 % radix;
+        str1[i] = (sum > 9) ? (sum - 10) + 'a' : sum + '0';
+        num1 = num1 / radix;
+        i++;
+    }
+    i--;
+    int j = 0;
+    for (i; i >= 0; i--) { // 逆序输出
+        str[i] = str1[j];
+        j++;
+    }
+}
+
+uintptr_t pingpong_sample(struct Session* session, int times)
+{
+    char* msg = "hello";
+    uintptr_t tick1 = sys_test();
+    for (int i = 0; i < times; i++) {
+        uintptr_t tmp = sys_test();
+    }
+    uintptr_t tick2 = sys_test();
+    uintptr_t time = (tick2 - tick1) / 24;
+    // printf("Sync Tick Cost: %lu\n", time);
+    return time;
+}
+
+uintptr_t pingpong_test_sync(struct Session* session, int times)
+{
+    char* msg = "hello";
+    uintptr_t tick1 = sys_test();
+    for (int i = 0; i < times; i++) {
+        pingpong(session, msg);
+    }
+    uintptr_t tick2 = sys_test();
+    uintptr_t time = (tick2 - tick1) / 24;
+    // printf("Sync Tick Cost: %lu\n", time);
+    return time;
+}
+
+uintptr_t pingpong_test_async(struct Session* session, int times)
+{
+    char* msg = "hello";
+    uintptr_t tick1 = sys_test();
+    for (int i = 0; i < times; i++) {
+        pingpong_nowait(session, msg);
+    }
+
+    for (int i = 0; i < times; i++) {
+        ipc_session_wait(session);
+        ipc_session_forward(session);
+    }
+    uintptr_t tick2 = sys_test();
+    uintptr_t time = (tick2 - tick1) / 24;
+    // printf("ASync Tick Cost: %lu\n", (tick2 - tick1) / 24);
+    return time;
+}
+
+int main(int argc, char** argv)
+{
+    int times = 0;
+    if (argc >= 2) {
+        times = string_to_integer(argv[1]);
+    }
+
+    struct Session session;
+    if (connect_session(&session, "PingPongServer", 81920) < 0) {
+        printf("connect session failed\n");
+        exit(1);
+    }
+
+    printf("============ PingPong Test start ==============\n");
+    uintptr_t loop = 50;
+    uintptr_t t1 = 0, t2 = 0, t0 = 0;
+    for (uintptr_t i = 0; i < loop; i++) {
+        t0 += pingpong_sample(&session, times);
+        t1 += pingpong_test_sync(&session, times);
+        t2 += pingpong_test_async(&session, times);
+    }
+
+    printf("Compare Tick Cost: %lu\n", t0 / loop);
+    printf("Sync Tick Cost: %lu\n", t1 / loop);
+    printf("ASync Tick Cost: %lu\n", t2 / loop);
+    printf("============= PingPong Test End ===============\n");
+
+    exit(0);
+}

Ubiquitous/XiZi_AIoT/services/app/pingpong_server.c

@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2020 AIIT XUOS Lab
+ * XiUOS is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *        http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ */
+#include <stdbool.h>
+
+#include "libserial.h"
+#include "pingpong_service.h"
+#include "usyscall.h"
+
+/// @warning all the parameters should in the form of pointers
+///          for the true storing memory of parameters is session(shared memory between tasks)
+int IPC_DO_SERVE_FUNC(Ipc_pingpong)(char* str)
+{
+    return 0;
+}
+
+IPC_SERVER_INTERFACE(Ipc_pingpong, 1);
+IPC_SERVER_REGISTER_INTERFACES(IpcPingPongServer, 1, Ipc_pingpong);
+
+int main(int argc, char* argv[])
+{
+    if (register_server("PingPongServer") < 0) {
+        printf("register server name: %s failed.\n", "PingPong");
+        exit(1);
+    }
+    ipc_server_loop(&IpcPingPongServer);
+
+    // never reached
+    exit(0);
+    return 0;
+}

Ubiquitous/XiZi_AIoT/services/app/pingpong_service.c

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2020 AIIT XUOS Lab
+ * XiUOS is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *        http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ */
+#include "pingpong_service.h"
+
+IPC_INTERFACE(Ipc_pingpong, 1, str, strlen(str));
+int pingpong(struct Session* session, char* str)
+{
+    return IPC_CALL(Ipc_pingpong)(session, str);
+}
+
+void pingpong_nowait(struct Session* session, char* str)
+{
+    struct IpcMsg* msg = IPC_CREATE_MSG_FUNC(Ipc_pingpong)(session, str);
+    ipc_msg_set_nth_arg(msg, 0, str, strlen(str));
+    ipc_msg_set_opcode(msg, Ipc_pingpong);
+    ipc_msg_send_nowait(msg);
+}

Ubiquitous/XiZi_AIoT/services/app/pingpong_service.h

@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2020 AIIT XUOS Lab
+ * XiUOS is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *        http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ */
+#include <stdbool.h>
+#include <string.h>
+
+#include "libipc.h"
+
+IPC_SERVICES(IpcPingPongServer, Ipc_pingpong);
+
+int pingpong(struct Session* session, char* str);
+void pingpong_nowait(struct Session* session, char* str);

Ubiquitous/XiZi_AIoT/services/app/test_context_user.c

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2020 AIIT XUOS Lab
+ * XiUOS is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *        http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ */
+
+#include "libserial.h"
+#include "usyscall.h"
+
+static inline uintptr_t arch_curr_tick()
+{
+    uint64_t x;
+    __asm__ volatile("mrs %0, cntpct_el0" : "=r"(x));
+    return x;
+}
+
+int main(int argc, char* argv[])
+{
+    uintptr_t loop = 1000;
+    uintptr_t tick_total = 0;
+    for (uintptr_t i = 0; i < loop; i++) {
+        uintptr_t tick_1 = sys_test();
+        uintptr_t tick_2 = sys_test();
+        // printf("TICK before: %lu\n", tick_1);
+        // printf("TICK after: %lu\n", tick_2);
+        // printf("TICK diff: %lu\n", tick_2 - tick_1);
+        tick_total += tick_2 - tick_1;
+    }
+
+    printf("TICK DIFF: %lu\n", tick_total / loop);
+
+    printf("TEST TICK: %lu\n", arch_curr_tick());
+
+    exit(0);
+    return 0;
+}

Ubiquitous/XiZi_AIoT/services/app/test_sleep.c

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2020 AIIT XUOS Lab
+ * XiUOS is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *        http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ */
+
+#include "libserial.h"
+#include "usyscall.h"
+
+int main(int argc, char* argv[])
+{
+    while (true) {
+        printf("sleep for 2 seconds\n");
+        sleep(2000);
+    }
+
+    exit(0);
+}

Ubiquitous/XiZi_AIoT/services/app/test_thread.c

@@ -25,15 +25,9 @@ int sub_thread_entry(int argc, char** argv)
         global_value++;
     }
 
-    /// @warning session is single threaded, so that each thread cannot share a common session.
     // sub thread connect to semaphore server
-    struct Session sem_session;
-    while (connect_session(&sem_session, sem_server_name, 4096) < 0) {
-        yield(SYS_TASK_YIELD_NO_REASON);
-    }
-
     printf("Thread signal sem.\n");
-    sem_signal(&sem_session, &sem);
+    semaphore_signal(sem);
 
     exit(0);
     return 0;
@@ -45,39 +39,8 @@ int main(int argc, char** argv)
     global_value = 0;
 
     printf("Test Create Semaphore.\n");
-    struct Session sem_session;
-    bool spawn_sem_server = false;
-    while (connect_session(&sem_session, sem_server_name, 4096) < 0) {
-        if (!spawn_sem_server) {
-            struct Session fs_session;
-            printf("Connect FS.\n");
-            if (connect_session(&fs_session, "MemFS", 8192) < 0) {
-                printf("Connect FS failed.\n");
-                exit(1);
-            }
-
-            printf("Loading semaphore server.\n");
-            int fd = -1;
-            if ((fd = open(&fs_session, sem_file_name)) < 0) {
-                printf("Open %s failed.\n", sem_file_name);
-                free_session(&fs_session);
-                exit(1);
-            }
-
-            printf("Spawn semaphore server.\n");
-            char* sem_server_params[] = { sem_server_name, sem_server_name, NULL };
-            if (spawn(&fs_session, fd, read, fsize, sem_server_name, sem_server_params) < 0) {
-                printf("Spawn %s failed.\n", sem_file_name);
-                free_session(&fs_session);
-                exit(1);
-            }
-
-            spawn_sem_server = true;
-            free_session(&fs_session);
-        }
-    }
     printf("Create new sem.\n");
-    sem_create(&sem_session, &sem, 0);
+    sem = semaphore_new(0);
 
     printf("Create new thread.\n");
     char* task_param[2] = { "add_gval", NULL };
@@ -91,12 +54,11 @@ int main(int argc, char** argv)
 
     printf("Main thread waiting for sem for %d times.\n", nr_thread);
     for (int i = 0; i < nr_thread; i++) {
-        int sem_wait_ret = sem_wait(&sem_session, &sem, 0);
+        int sem_wait_ret = semaphore_wait(sem);
     }
     printf("Main thread sem %d wait return, global val: %d.\n", sem, global_value);
 
-    sem_delete(&sem_session, &sem);
+    semaphore_free(sem);
-    free_session(&sem_session);
     exit(0);
     return 0;
 }

Ubiquitous/XiZi_AIoT/services/boards/3568/arch_usyscall.c

@@ -15,6 +15,27 @@ int syscall(int sys_num, intptr_t a1, intptr_t a2, intptr_t a3, intptr_t a4)
 {
     int ret = -1;
 
+    __asm__ volatile(
+        "mov x0, %1;\
+        mov x1, %2;\
+        mov x2, %3;\
+        mov x3, %4;\
+        mov x4, %5;\
+        svc #0;\
+        dsb ish;\
+        isb;\
+        mov %0, x0"
+        : "=r"(ret)
+        : "r"(sys_num), "r"(a1), "r"(a2), "r"(a3), "r"(a4)
+        : "memory", "r0", "r1", "r2", "r3", "r4");
+
+    return ret;
+}
+
+uintptr_t syscall_ori(int sys_num, intptr_t a1, intptr_t a2, intptr_t a3, intptr_t a4)
+{
+    uintptr_t ret = -1;
+
     __asm__ volatile(
         "mov x0, %1;\
         mov x1, %2;\

Ubiquitous/XiZi_AIoT/services/drivers/3568/Makefile

@@ -1,4 +1,4 @@
 
-SRC_DIR := hal
+SRC_DIR :=
 
 include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_base.c

@@ -312,13 +312,12 @@ __attribute__((weak)) HAL_Status HAL_DelayMs(uint32_t ms)
  */
 HAL_Status HAL_DelayUs(uint32_t us)
 {
-// #if defined(SYS_TIMER) && defined(HAL_TIMER_MODULE_ENABLED)
+#if defined(SYS_TIMER) && defined(HAL_TIMER_MODULE_ENABLED)
-
-//     return TimerDelayUs(us);
-// #else
 
+    return TimerDelayUs(us);
+#else
     return HAL_CPUDelayUs(us);
-// #endif
+#endif
 }
 
 /**

Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_bsp.c

@@ -321,21 +321,43 @@ const struct HAL_CANFD_DEV g_can2Dev =
 #endif
 
 #ifdef HAL_GMAC_MODULE_ENABLED
+// const struct HAL_GMAC_DEV g_gmac0Dev =
+// {
+//     .pReg = GMAC0,
+//     .clkID = CLK_MAC0_2TOP,
+//     .clkGateID = CLK_MAC0_2TOP_GATE,
+//     .pclkID = PCLK_PHP,
+//     .pclkGateID = PCLK_GMAC0_GATE,
+//     .irqNum = GMAC0_IRQn,
+// };
 const struct HAL_GMAC_DEV g_gmac0Dev =
 {
     .pReg = GMAC0,
-    .clkID = CLK_MAC0_2TOP,
+    .clkID125M = CLK_MAC0_2TOP,
-    .clkGateID = CLK_MAC0_2TOP_GATE,
+    .clkID50M = CLK_MAC0_2TOP,
+    .clkGateID125M = CLK_MAC0_2TOP_GATE,
+    .clkGateID50M = CLK_MAC0_2TOP_GATE,
     .pclkID = PCLK_PHP,
     .pclkGateID = PCLK_GMAC0_GATE,
     .irqNum = GMAC0_IRQn,
 };
 
+// const struct HAL_GMAC_DEV g_gmac1Dev =
+// {
+//     .pReg = GMAC1,
+//     .clkID = CLK_MAC1_2TOP,
+//     .clkGateID = CLK_MAC1_2TOP_GATE,
+//     .pclkID = PCLK_USB,
+//     .pclkGateID = PCLK_GMAC1_GATE,
+//     .irqNum = GMAC1_IRQn,
+// };
 const struct HAL_GMAC_DEV g_gmac1Dev =
 {
     .pReg = GMAC1,
-    .clkID = CLK_MAC1_2TOP,
+    .clkID125M = CLK_MAC1_2TOP,
-    .clkGateID = CLK_MAC1_2TOP_GATE,
+    .clkID50M = CLK_MAC1_2TOP,
+    .clkGateID125M = CLK_MAC1_2TOP_GATE,
+    .clkGateID50M = CLK_MAC1_2TOP_GATE,
     .pclkID = PCLK_USB,
     .pclkGateID = PCLK_GMAC1_GATE,
     .irqNum = GMAC1_IRQn,

Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_cru.c

@@ -115,8 +115,8 @@
 
 #define CRU_PLL_ROUND_UP_TO_KHZ(x) (HAL_DIV_ROUND_UP((x), KHZ) * KHZ)
 
-#define CRU_READ(r)           (*(volatile uint32_t *)(r))
+#define CRU_READ(r)           (*(volatile uint32_t *)((uintptr_t)(r)))
-#define CRU_WRITE(r, b, w, v) (*(volatile uint32_t *)(r) = ((w) << (16) | (v) << (b)))
+#define CRU_WRITE(r, b, w, v) (*(volatile uint32_t *)((uintptr_t)(r)) = ((w) << (16) | (v) << (b)))
 
 /********************* Private Structure Definition **************************/
 static struct PLL_CONFIG g_rockchipAutoTable;
@@ -147,6 +147,22 @@ static int isBetterFreq(uint32_t now, uint32_t new, uint32_t best)
     return (new <= now && new > best);
 }
 
+int HAL_CRU_FreqGetMuxArray(uint32_t freq, uint32_t *table, int num)
+{
+    uint32_t best = 0, mux = 0;
+    int i;
+
+    for (i = 0; i < num; i++) {
+        if (isBetterFreq(freq, table[i], best)) {
+            best = table[i];
+            mux = i;
+            break;
+        }
+    }
+
+    return mux;
+}
+
 int HAL_CRU_FreqGetMux4(uint32_t freq, uint32_t freq0, uint32_t freq1,
                         uint32_t freq2, uint32_t freq3)
 {
@@ -191,6 +207,17 @@ int HAL_CRU_FreqGetMux2(uint32_t freq, uint32_t freq0, uint32_t freq1)
     return HAL_CRU_FreqGetMux4(freq, freq0, freq1, freq1, freq1);
 }
 
+uint32_t HAL_CRU_MuxGetFreqArray(uint32_t muxName, uint32_t *table, int num)
+{
+    uint32_t mux = HAL_CRU_ClkGetMux(muxName);
+
+    if (mux <= (uint32_t)num) {
+        return table[mux];
+    } else {
+        return HAL_INVAL;
+    }
+}
+
 uint32_t HAL_CRU_MuxGetFreq4(uint32_t muxName, uint32_t freq0, uint32_t freq1,
                              uint32_t freq2, uint32_t freq3)
 {
@@ -223,6 +250,30 @@ uint32_t HAL_CRU_MuxGetFreq2(uint32_t muxName, uint32_t freq0, uint32_t freq1)
     return HAL_CRU_MuxGetFreq4(muxName, freq0, freq1, freq1, freq1);
 }
 
+int HAL_CRU_RoundFreqGetMuxArray(uint32_t freq, uint32_t *table, int num, uint32_t *pFreqOut, bool is_div)
+{
+    uint32_t mux = 0;
+    int i = 0;
+
+    for (i = 0; i < num; i++) {
+        if (is_div) {
+            if (table[i] && (table[i] % freq == 0)) {
+                mux = i;
+                break;
+            }
+        } else {
+            if (table[i] && (table[i] == freq)) {
+                mux = i;
+                break;
+            }
+        }
+    }
+
+    *pFreqOut = table[mux];
+
+    return mux;
+}
+
 int HAL_CRU_RoundFreqGetMux4(uint32_t freq, uint32_t pFreq0,
                              uint32_t pFreq1, uint32_t pFreq2,
                              uint32_t pFreq3, uint32_t *pFreqOut)
@@ -811,7 +862,7 @@ HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup)
  */
 uint32_t HAL_CRU_GetPllFreq(struct PLL_SETUP *pSetup)
 {
-    uint32_t refDiv, fbDiv, postdDv1, postDiv2, frac, dsmpd;
+    uint64_t refDiv, fbDiv, postdDv1, postDiv2, frac, dsmpd;
     uint32_t mode = 0, rate = PLL_INPUT_OSC_RATE;
 
     mode = PLL_GET_PLLMODE(READ_REG(*(pSetup->modeOffset)), pSetup->modeShift,
@@ -956,6 +1007,271 @@ HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup)
 }
 #endif
 
+#ifdef CRU_CLK_USE_CON_BANK
+static const struct HAL_CRU_DEV *CRU_GetInfo(void)
+{
+    return &g_cruDev;
+}
+
+HAL_Check HAL_CRU_ClkIsEnabled(uint32_t clk)
+{
+    const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
+    uint32_t index = CLK_GATE_GET_REG_OFFSET(clk);
+    uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk);
+    uint32_t bank = CLK_GATE_GET_REG_BANK(clk);
+    uint32_t reg;
+    HAL_Check ret;
+
+    reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].gateOffset + index * 4;
+    ret = (HAL_Check)(!((CRU_READ(reg) & (1 << shift)) >> shift));
+
+    return ret;
+}
+
+HAL_SECTION_SRAM_CODE
+HAL_Status HAL_CRU_ClkEnable(uint32_t clk)
+{
+    const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
+    uint32_t index = CLK_GATE_GET_REG_OFFSET(clk);
+    uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk);
+    uint32_t bank = CLK_GATE_GET_REG_BANK(clk);
+    uint32_t reg;
+
+    reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].gateOffset + index * 4;
+    CRU_WRITE(reg, shift, 1U << shift, 0U);
+
+    return HAL_OK;
+}
+
+HAL_Status HAL_CRU_ClkDisable(uint32_t clk)
+{
+    const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
+    uint32_t index = CLK_GATE_GET_REG_OFFSET(clk);
+    uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk);
+    uint32_t bank = CLK_GATE_GET_REG_BANK(clk);
+    uint32_t reg;
+
+    reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].gateOffset + index * 4;
+    CRU_WRITE(reg, shift, 1U << shift, 1U);
+
+    return HAL_OK;
+}
+
+HAL_Status HAL_CRU_ClkDisableUnused(uint32_t bank, uint32_t index, uint32_t val)
+{
+    const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
+    uint32_t reg;
+
+    reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].gateOffset + index * 4;
+    CRU_WRITE(reg, 0, 0, val);
+
+    return HAL_OK;
+}
+
+HAL_Check HAL_CRU_ClkIsReset(uint32_t clk)
+{
+    const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
+    uint32_t index = CLK_GATE_GET_REG_OFFSET(clk);
+    uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk);
+    uint32_t bank = CLK_GATE_GET_REG_BANK(clk);
+    uint32_t reg;
+    HAL_Check ret;
+
+    reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4;
+    ret = (HAL_Check)((CRU_READ(reg) & (1 << shift)) >> shift);
+
+    return ret;
+}
+
+HAL_Status HAL_CRU_ClkResetAssert(uint32_t clk)
+{
+    const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
+    uint32_t index = CLK_RESET_GET_REG_OFFSET(clk);
+    uint32_t shift = CLK_RESET_GET_BITS_SHIFT(clk);
+    uint32_t bank = CLK_GATE_GET_REG_BANK(clk);
+    uint32_t reg;
+
+    HAL_ASSERT(shift < 16);
+    reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4;
+    CRU_WRITE(reg, shift, 1U << shift, 1U);
+
+    return HAL_OK;
+}
+
+HAL_Status HAL_CRU_ClkResetDeassert(uint32_t clk)
+{
+    const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
+    uint32_t index = CLK_RESET_GET_REG_OFFSET(clk);
+    uint32_t shift = CLK_RESET_GET_BITS_SHIFT(clk);
+    uint32_t bank = CLK_GATE_GET_REG_BANK(clk);
+    uint32_t reg;
+
+    HAL_ASSERT(shift < 16);
+    reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4;
+    CRU_WRITE(reg, shift, 1U << shift, 0U);
+
+    return HAL_OK;
+}
+
+HAL_Status HAL_CRU_ClkResetSyncAssert(int numClks, uint32_t *clks)
+{
+    const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
+    uint32_t index = CLK_RESET_GET_REG_OFFSET(clks[0]);
+    uint32_t bank = CLK_GATE_GET_REG_BANK(clks[0]);
+    uint32_t val = 0;
+    uint32_t reg;
+    int i;
+
+    for (i = 0; i < numClks; i++) {
+        val |= HAL_BIT(CLK_RESET_GET_BITS_SHIFT(clks[i]));
+        if (index != CLK_RESET_GET_REG_OFFSET(clks[i])) {
+            return HAL_ERROR;
+        }
+    }
+
+    reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4;
+    CRU_WRITE(reg, 0, val, val);
+    HAL_DBG("%s: index: 0x%lx, val: 0x%lx\n", __func__, index, val);
+
+    return HAL_OK;
+}
+
+HAL_Status HAL_CRU_ClkResetSyncDeassert(int numClks, uint32_t *clks)
+{
+    const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
+    uint32_t index = CLK_RESET_GET_REG_OFFSET(clks[0]);
+    uint32_t bank = CLK_GATE_GET_REG_BANK(clks[0]);
+    uint32_t val = 0;
+    uint32_t reg;
+    int i;
+
+    for (i = 0; i < numClks; i++) {
+        val |= HAL_BIT(CLK_RESET_GET_BITS_SHIFT(clks[i]));
+        if (index != CLK_RESET_GET_REG_OFFSET(clks[i])) {
+            return HAL_ERROR;
+        }
+    }
+
+    reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4;
+    CRU_WRITE(reg, 0, val, 0);
+    HAL_DBG("%s: index: 0x%lx, val: 0x%lx\n", __func__, index, val);
+
+    return HAL_OK;
+}
+
+HAL_SECTION_SRAM_CODE
+HAL_Status HAL_CRU_ClkSetDiv(uint32_t divName, uint32_t divValue)
+{
+    const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
+    uint32_t shift, mask, index;
+    uint32_t reg, bank, maxDiv;
+
+    index = CLK_DIV_GET_REG_OFFSET(divName);
+    shift = CLK_DIV_GET_BITS_SHIFT(divName);
+    HAL_ASSERT(shift < 16);
+    mask = CLK_DIV_GET_MASK(divName);
+    maxDiv = CLK_DIV_GET_MAXDIV(divName) + 1;
+    if (divValue > maxDiv) {
+        divValue = maxDiv;
+    }
+
+    bank = CLK_DIV_GET_BANK(divName);
+    reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4;
+    CRU_WRITE(reg, shift, mask, (divValue - 1U));
+
+    return HAL_OK;
+}
+
+uint32_t HAL_CRU_ClkGetDiv(uint32_t divName)
+{
+    const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
+    uint32_t shift, mask, index, divValue;
+    uint32_t reg, bank;
+
+    index = CLK_DIV_GET_REG_OFFSET(divName);
+    shift = CLK_DIV_GET_BITS_SHIFT(divName);
+    HAL_ASSERT(shift < 16);
+    mask = CLK_DIV_GET_MASK(divName);
+    bank = CLK_DIV_GET_BANK(divName);
+    reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4;
+    divValue = ((CRU_READ(reg) & mask) >> shift) + 1;
+
+    return divValue;
+}
+
+HAL_SECTION_SRAM_CODE
+HAL_Status HAL_CRU_ClkSetMux(uint32_t muxName, uint32_t muxValue)
+{
+    const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
+    uint32_t shift, mask, index;
+    uint32_t reg, bank;
+
+    index = CLK_MUX_GET_REG_OFFSET(muxName);
+    shift = CLK_MUX_GET_BITS_SHIFT(muxName);
+    HAL_ASSERT(shift < 16);
+    mask = CLK_MUX_GET_MASK(muxName);
+    bank = CLK_MUX_GET_BANK(muxName);
+    reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4;
+    CRU_WRITE(reg, shift, mask, muxValue);
+
+    return HAL_OK;
+}
+
+HAL_SECTION_SRAM_CODE
+uint32_t HAL_CRU_ClkGetMux(uint32_t muxName)
+{
+    const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
+    uint32_t shift, mask, index, muxValue;
+    uint32_t reg, bank;
+
+    index = CLK_MUX_GET_REG_OFFSET(muxName);
+    shift = CLK_MUX_GET_BITS_SHIFT(muxName);
+    HAL_ASSERT(shift < 16);
+    mask = CLK_MUX_GET_MASK(muxName);
+    bank = CLK_MUX_GET_BANK(muxName);
+    reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4;
+    muxValue = ((CRU_READ(reg) & mask) >> shift);
+
+    return muxValue;
+}
+
+HAL_Status HAL_CRU_ClkSetFracDiv(uint32_t fracDivName,
+                                 uint32_t numerator,
+                                 uint32_t denominator)
+{
+    const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
+    uint32_t reg, bank;
+    uint32_t index;
+
+    index = CLK_DIV_GET_REG_OFFSET(fracDivName);
+    bank = CLK_DIV_GET_BANK(fracDivName);
+    reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4;
+    CRU_WRITE(reg, 0, 0, ((numerator << 16) | denominator));
+
+    return HAL_OK;
+}
+
+HAL_Status HAL_CRU_ClkGetFracDiv(uint32_t fracDivName,
+                                 uint32_t *numerator,
+                                 uint32_t *denominator)
+{
+    const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
+    uint32_t reg, bank;
+    uint32_t index;
+    uint32_t val;
+
+    index = CLK_DIV_GET_REG_OFFSET(fracDivName);
+    bank = CLK_DIV_GET_BANK(fracDivName);
+    reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4;
+    val = CRU_READ(reg);
+
+    *numerator = (val & 0xffff0000) >> 16;
+    *denominator = (val & 0x0000ffff);
+
+    return HAL_OK;
+}
+#else /* CRU_CLK_USE_CON_BANK */
+
 HAL_Check HAL_CRU_ClkIsEnabled(uint32_t clk)
 {
     uint32_t index = CLK_GATE_GET_REG_OFFSET(clk);
@@ -1153,16 +1469,18 @@ HAL_Status HAL_CRU_ClkResetSyncDeassert(int numClks, uint32_t *clks)
     return HAL_OK;
 }
 
+HAL_SECTION_SRAM_CODE
 HAL_Status HAL_CRU_ClkSetDiv(uint32_t divName, uint32_t divValue)
 {
-    uint32_t shift, mask, index;
+    uint32_t shift, mask, index, maxDiv;
 
     index = CLK_DIV_GET_REG_OFFSET(divName);
     shift = CLK_DIV_GET_BITS_SHIFT(divName);
     HAL_ASSERT(shift < 16);
     mask = CLK_DIV_GET_MASK(divName);
-    if (divValue > mask) {
+    maxDiv = CLK_DIV_GET_MAXDIV(divName) + 1;
-        divValue = mask;
+    if (divValue > maxDiv) {
+        divValue = maxDiv;
     }
 
 #ifdef CRU_CLK_DIV_CON_CNT
@@ -1313,7 +1631,7 @@ HAL_Status HAL_CRU_ClkGetFracDiv(uint32_t fracDivName,
 
     return HAL_OK;
 }
-
+#endif /* CRU_CLK_USE_CON_BANK */
 
 HAL_Status HAL_CRU_FracdivGetConfig(uint32_t rateOut, uint32_t rate,
                                     uint32_t *numerator,
@@ -1340,6 +1658,31 @@ HAL_Status HAL_CRU_FracdivGetConfig(uint32_t rateOut, uint32_t rate,
     return HAL_OK;
 }
 
+HAL_Status HAL_CRU_FracdivGetConfigV2(uint32_t rateOut, uint32_t rate,
+                                      uint32_t *numerator,
+                                      uint32_t *denominator)
+{
+    uint32_t gcdVal;
+
+    gcdVal = CRU_Gcd(rate, rateOut);
+    if (!gcdVal) {
+        return HAL_ERROR;
+    }
+
+    *numerator = rateOut / gcdVal;
+    *denominator = rate / gcdVal;
+
+    if (*numerator < 4) {
+        *numerator *= 4;
+        *denominator *= 4;
+    }
+    if (*numerator > 0xffffff || *denominator > 0xffffff) {
+        return HAL_INVAL;
+    }
+
+    return HAL_OK;
+}
+
 HAL_Status HAL_CRU_ClkNp5BestDiv(eCLOCK_Name clockName, uint32_t rate, uint32_t pRate, uint32_t *bestdiv)
 {
     uint32_t div = CLK_GET_DIV(clockName);

Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_cru_rk3568.c

@@ -874,6 +874,23 @@ uint32_t HAL_CRU_ClkGetFreq(eCLOCK_Name clockName)
         }
 
         return freq;
+    case CLK_SDMMC0:
+        if (HAL_CRU_ClkGetMux(clkMux) == 1) {
+            freq = 400000000;
+        } else if (HAL_CRU_ClkGetMux(clkMux) == 2) {
+            freq = 300000000;
+        } else if (HAL_CRU_ClkGetMux(clkMux) == 3) {
+            freq = 100000000;
+        } else if (HAL_CRU_ClkGetMux(clkMux) == 4) {
+            freq = 50000000;
+        } else if (HAL_CRU_ClkGetMux(clkMux) == 5) {
+            freq = 750000;
+        } else {
+            freq = PLL_INPUT_OSC_RATE;
+        }
+
+        return freq;
+
     case ACLK_USB:
     case HCLK_USB:
     case PCLK_USB:
@@ -1002,6 +1019,22 @@ HAL_Status HAL_CRU_ClkSetFreq(eCLOCK_Name clockName, uint32_t rate)
             mux = 0;
         }
 
+        break;
+    case CLK_SDMMC0:
+        if (rate == 400000000) {
+            mux = 1;
+        } else if (rate == 750000) {
+            mux = 5;
+        } else if (rate == 50000000) {
+            mux = 4;
+        } else if (rate == 100000000) {
+            mux = 3;
+        } else if (rate == 300000000) {
+            mux = 2;
+        } else {
+            mux = 0;
+        }
+
         break;
     case ACLK_USB:
     case HCLK_USB:

Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_gmac.c

@@ -283,7 +283,9 @@
 #define GMAC_DESC3_FD    (0x1 << 29)
 #define GMAC_DESC3_LD    (0x1 << 28)
 #define GMAC_DESC3_BUF1V (0x1 << 24)
+#define GMAC_DESC3_CIC   (0x3 << 16)
 
+#define DES3_ERROR_SUMMARY (1 << 15)
 #define DES3_ERROR_SUMMARY (1 << 15)
 
 /* Generic MII registers. */
@@ -1123,7 +1125,7 @@ int32_t HAL_GMAC_MDIORead(struct GMAC_HANDLE *pGMAC, int32_t mdioAddr,
 
     HAL_ASSERT(pGMAC != NULL);
 
-    HAL_DBG("Mdio Read addr=%ld, reg=%ld\n", mdioAddr, mdioReg);
+    // HAL_DBG("Mdio Read addr=%ld, reg=%ld\n", mdioAddr, mdioReg);
     status = Mdio_WaitIdle(pGMAC);
     if (status) {
         HAL_DBG("MDIO not idle at entry");
@@ -1173,8 +1175,8 @@ HAL_Status HAL_GMAC_MDIOWrite(struct GMAC_HANDLE *pGMAC, int32_t mdioAddr,
 
     HAL_ASSERT(pGMAC != NULL);
 
-    HAL_DBG("%s(addr=%lx, reg=%ld, val=%x):\n", __func__,
+    // HAL_DBG("%s(addr=%lx, reg=%ld, val=%x):\n", __func__,
-            mdioAddr, mdioReg, mdioVal);
+    //         mdioAddr, mdioReg, mdioVal);
     status = Mdio_WaitIdle(pGMAC);
     if (status) {
         HAL_DBG("MDIO not idle at entry");
@@ -1347,7 +1349,6 @@ HAL_Status HAL_GMAC_PHYParseLink(struct GMAC_HANDLE *pGMAC)
     if (pGMAC->phyStatus.neg == PHY_AUTONEG_ENABLE) {
         uint32_t lpa = 0, estatus = 0;
         int32_t gblpa = 0;
-
         /* Check for gigabit capability */
         if (pGMAC->phyStatus.supported & (HAL_GMAC_PHY_SUPPORTED_1000baseT_Full |
                                           HAL_GMAC_PHY_SUPPORTED_1000baseT_Half)) {
@@ -1746,6 +1747,13 @@ HAL_Status HAL_GMAC_AdjustLink(struct GMAC_HANDLE *pGMAC, int32_t txDelay,
   *
   * @return HAL status
   */
+#define GENMASK(h, l)		(((1U << ((h) - (l) + 1)) - 1) << (l))
+#define DMA_AXI_WR_OSR_LMT		GENMASK(27, 24)
+#define DMA_AXI_WR_OSR_LMT_SHIFT	24
+#define DMA_AXI_RD_OSR_LMT		GENMASK(19, 16)
+#define DMA_AXI_RD_OSR_LMT_SHIFT	16
+#define DMA_AXI_OSR_MAX			0xf
+
 HAL_Status HAL_GMAC_Start(struct GMAC_HANDLE *pGMAC, uint8_t *addr)
 {
     uint32_t mmc_mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
@@ -1764,6 +1772,7 @@ HAL_Status HAL_GMAC_Start(struct GMAC_HANDLE *pGMAC, uint8_t *addr)
     value = READ_REG(pGMAC->pReg->DMA_MODE);
     WRITE_REG(pGMAC->pReg->DMA_MODE, value | DMA_MODE_SWR);
     /* Wait for software Reset */
+    HAL_DelayMs(100);
     while (limit--) {
         if (!(READ_REG(pGMAC->pReg->DMA_MODE) & DMA_MODE_SWR)) {
             break;
@@ -1777,10 +1786,16 @@ HAL_Status HAL_GMAC_Start(struct GMAC_HANDLE *pGMAC, uint8_t *addr)
     }
 
     HAL_DelayMs(100);
+    value = READ_REG(pGMAC->pReg->DMA_SYSBUS_MODE);
+    value &= ~DMA_AXI_WR_OSR_LMT;
+	value |= (0x0 & DMA_AXI_OSR_MAX) << DMA_AXI_WR_OSR_LMT_SHIFT;
+
+	value &= ~DMA_AXI_RD_OSR_LMT;
+	value |= (0x2 & DMA_AXI_OSR_MAX) << DMA_AXI_RD_OSR_LMT_SHIFT;
 
     /* DMA init */
-    WRITE_REG(pGMAC->pReg->DMA_SYSBUS_MODE, DMA_SYSBUS_MODE_BLEN16 |
+    WRITE_REG(pGMAC->pReg->DMA_SYSBUS_MODE, value | DMA_SYSBUS_MODE_BLEN16 |
-              DMA_SYSBUS_MODE_BLEN8 | DMA_SYSBUS_MODE_BLEN4 | 1 << 12 | 1 << 14);
+              DMA_SYSBUS_MODE_BLEN8 | DMA_SYSBUS_MODE_BLEN4);
 
     /* Mask interrupts by writing to CSR7 */
     WRITE_REG(pGMAC->pReg->DMA_CH0_INTERRUPT_ENABLE, DMA_CHAN_INTR_DEFAULT_MASK);
@@ -1789,6 +1804,7 @@ HAL_Status HAL_GMAC_Start(struct GMAC_HANDLE *pGMAC, uint8_t *addr)
     /* Set the HW DMA mode and the COE */
     txFifosz = 128 << ((hwCap & GMAC_HW_TXFIFOSIZE) >> GMAC_HW_TXFIFOSIZE_SHIFT);
     rxFifosz = 128 << ((hwCap & GMAC_HW_RXFIFOSIZE) >> GMAC_HW_RXFIFOSIZE_SHIFT);
+    
 
     /* init rx chan */
     value = READ_REG(pGMAC->pReg->DMA_CH0_RX_CONTROL);
@@ -1800,9 +1816,13 @@ HAL_Status HAL_GMAC_Start(struct GMAC_HANDLE *pGMAC, uint8_t *addr)
     WRITE_REG(pGMAC->pReg->DMA_CH0_RXDESC_TAIL_POINTER,
               (uint32_t)(uint64_t)(pGMAC->rxDescs_dma + pGMAC->rxSize));
 
+    value = READ_REG(pGMAC->pReg->DMA_CH0_CONTROL);
+    value = value | 1 << 16;
+    WRITE_REG(pGMAC->pReg->DMA_CH0_CONTROL, value);
+
     /* init tx chan */
     value = READ_REG(pGMAC->pReg->DMA_CH0_TX_CONTROL);
-    value = value | (8 << DMA_CH0_TX_CONTROL_TXPBL_SHIFT);
+    value = value | (32 << DMA_CH0_TX_CONTROL_TXPBL_SHIFT);
     value |= DMA_CH0_TX_CONTROL_OSF;
     WRITE_REG(pGMAC->pReg->DMA_CH0_TX_CONTROL, value);
 
@@ -2002,7 +2022,7 @@ HAL_Status HAL_GMAC_Send(struct GMAC_HANDLE *pGMAC, void *packet,
     
     desc->des0 = (uint32_t)(uint64_t)packet;
     desc->des1 = 0;
-    desc->des2 = length;
+    desc->des2 = length | 1<<31;
     /*
      * Make sure that if HW sees the _OWN write below, it will see all the
      * writes to the rest of the descriptor too.
@@ -2046,10 +2066,9 @@ uint8_t *HAL_GMAC_Recv(struct GMAC_HANDLE *pGMAC, int32_t *length)
 
     *length = 0;
     desc = pGMAC->rxDescs + pGMAC->rxDescIdx;
-    HAL_DBG("Rx at %p\n", desc->des0);
     des3 = desc->des3;
     if (des3 & GMAC_DESC3_OWN) {
-        HAL_DBG("%s: RX packet not available\n", __func__);
+        HAL_DBG("%p: RX packet not available\n", desc->des0);
 
         return NULL;
     }
@@ -2106,10 +2125,9 @@ void HAL_GMAC_CleanRX(struct GMAC_HANDLE *pGMAC)
     desc->des1 = 0;
     desc->des2 = 0;
     desc->des3 = GMAC_DESC3_OWN | GMAC_DESC3_BUF1V | GMAC_DESC3_IOC;
-    HAL_DBG("Clean buff  %p\n", desc->des0);
+
-    desc_dma = pGMAC->rxDescs_dma + pGMAC->rxDescIdx;
+    WRITE_REG(pGMAC->pReg->DMA_CH0_RXDESC_TAIL_POINTER, 
-    HAL_DBG("Clean desc %p\n", desc_dma);
+                (uint32_t)(uint64_t)(pGMAC->rxDescs_dma + pGMAC->rxDescIdx));
-    WRITE_REG(pGMAC->pReg->DMA_CH0_RXDESC_TAIL_POINTER, (uint32_t)(uint64_t)desc_dma);
 
     pGMAC->rxDescIdx++;
     pGMAC->rxDescIdx %= pGMAC->rxSize;
@@ -2172,7 +2190,6 @@ HAL_Status HAL_GMAC_Init(struct GMAC_HANDLE *pGMAC, struct GMAC_REG *pReg,
 
     pGMAC->txDescIdx = 0;
     pGMAC->rxDescIdx = 0;
-
     /* Get CR bits depending on hclk value */
     if ((freq >= 20000000) && (freq < 35000000)) {
         /* CSR Clock Range between 20-35 MHz */

Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/hal_gpio.c

@@ -58,7 +58,7 @@
  */
 static void GPIO_SetEOI(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
 {
-#if (GPIO_VER_ID == 0x01000C2BU)
+#if (GPIO_VER_ID >= 0x01000C2BU)
     if (IS_GPIO_HIGH_PIN(pin)) {
         pin &= 0xFFFF0000;
         pGPIO->PORT_EOI_H = pin | (pin >> 16);
@@ -82,7 +82,7 @@ static uint32_t GPIO_GetIntType(struct GPIO_REG *pGPIO)
 {
     uint32_t type;
 
-#if (GPIO_VER_ID == 0x01000C2BU)
+#if (GPIO_VER_ID >= 0x01000C2BU)
     type = (pGPIO->INT_TYPE_L & 0xffff);
     type |= ((pGPIO->INT_TYPE_H & 0xffff) << 16);
     type |= (pGPIO->INT_BOTHEDGE_L & 0xffff);
@@ -161,7 +161,7 @@ HAL_Status HAL_GPIO_SetIntType(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, e
         return HAL_INVAL;
     }
 
-#if (GPIO_VER_ID == 0x01000C2BU)
+#if (GPIO_VER_ID >= 0x01000C2BU)
     if (IS_GPIO_HIGH_PIN(pin)) {
         pin &= 0xFFFF0000;
         pGPIO->INT_TYPE_H = (type) ? (pin | (pin >> 16)) : (pin);
@@ -195,7 +195,7 @@ HAL_Status HAL_GPIO_SetIntType(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, e
  */
 HAL_Status HAL_GPIO_SetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinDirection direction)
 {
-#if (GPIO_VER_ID == 0x01000C2BU)
+#if (GPIO_VER_ID >= 0x01000C2BU)
     if (IS_GPIO_HIGH_PIN(pin)) {
         pin &= 0xFFFF0000;
         pGPIO->SWPORT_DDR_H = (direction == GPIO_OUT) ? (pin | (pin >> 16)) : (pin);
@@ -251,7 +251,7 @@ eGPIO_pinDirection HAL_GPIO_GetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPI
     eGPIO_pinDirection direction;
     uint32_t value;
 
-#if (GPIO_VER_ID == 0x01000C2BU)
+#if (GPIO_VER_ID >= 0x01000C2BU)
     value = IS_GPIO_HIGH_PIN(pin) ? (pGPIO->SWPORT_DDR_H & (pin >> 16)) : (pGPIO->SWPORT_DDR_L & pin);
 #else
     value = pGPIO->SWPORTA_DDR & pin;
@@ -275,7 +275,7 @@ eGPIO_pinDirection HAL_GPIO_GetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPI
  */
 HAL_Status HAL_GPIO_SetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinLevel level)
 {
-#if (GPIO_VER_ID == 0x01000C2BU)
+#if (GPIO_VER_ID >= 0x01000C2BU)
     if (IS_GPIO_HIGH_PIN(pin)) {
         pin &= 0xFFFF0000;
         pGPIO->SWPORT_DR_H = (level == GPIO_HIGH) ? (pin | (pin >> 16)) : (pin);
@@ -340,7 +340,7 @@ eGPIO_pinLevel HAL_GPIO_GetPinData(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pi
     eGPIO_pinLevel level;
     uint32_t value;
 
-#if (GPIO_VER_ID == 0x01000C2BU)
+#if (GPIO_VER_ID >= 0x01000C2BU)
     value = IS_GPIO_HIGH_PIN(pin) ? (pGPIO->SWPORT_DR_H & (pin >> 16)) : (pGPIO->SWPORT_DR_L & pin);
 #else
     value = pGPIO->SWPORTA_DR & pin;
@@ -365,7 +365,7 @@ eGPIO_pinLevel HAL_GPIO_GetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS p
 {
     uint32_t value;
 
-#if (GPIO_VER_ID == 0x01000C2BU)
+#if (GPIO_VER_ID >= 0x01000C2BU)
     value = (pGPIO->EXT_PORT & pin);
 #else
     value = (pGPIO->EXT_PORTA & pin);
@@ -383,7 +383,7 @@ uint32_t HAL_GPIO_GetBankLevel(struct GPIO_REG *pGPIO)
 {
     uint32_t value;
 
-#if (GPIO_VER_ID == 0x01000C2BU)
+#if (GPIO_VER_ID >= 0x01000C2BU)
     value = (pGPIO->EXT_PORT);
 #else
     value = (pGPIO->EXT_PORTA);
@@ -404,7 +404,7 @@ uint32_t HAL_GPIO_GetBankLevel(struct GPIO_REG *pGPIO)
  */
 void HAL_GPIO_EnableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
 {
-#if (GPIO_VER_ID == 0x01000C2BU)
+#if (GPIO_VER_ID >= 0x01000C2BU)
     if (IS_GPIO_HIGH_PIN(pin)) {
         pin &= 0xFFFF0000;
 #ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED
@@ -433,7 +433,7 @@ void HAL_GPIO_EnableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
  */
 void HAL_GPIO_DisableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
 {
-#if (GPIO_VER_ID == 0x01000C2BU)
+#if (GPIO_VER_ID >= 0x01000C2BU)
     if (IS_GPIO_HIGH_PIN(pin)) {
         pin &= 0xFFFF0000;
         pGPIO->INT_EN_H = pin;
@@ -511,7 +511,7 @@ void HAL_GPIO_IRQHandler(struct GPIO_REG *pGPIO, eGPIO_bankId bank)
  */
 HAL_Status HAL_GPIO_EnableVirtualModel(struct GPIO_REG *pGPIO)
 {
-#if (GPIO_VER_ID == 0x01000C2BU)
+#if (GPIO_VER_ID >= 0x01000C2BU)
     pGPIO->GPIO_VIRTUAL_EN = 0x10001;
 
     return HAL_OK;
@@ -527,7 +527,7 @@ HAL_Status HAL_GPIO_EnableVirtualModel(struct GPIO_REG *pGPIO)
  */
 HAL_Status HAL_GPIO_DisableVirtualModel(struct GPIO_REG *pGPIO)
 {
-#if (GPIO_VER_ID == 0x01000C2BU)
+#if (GPIO_VER_ID >= 0x01000C2BU)
     pGPIO->GPIO_VIRTUAL_EN = 0x10000;
 
     return HAL_OK;
@@ -545,22 +545,51 @@ HAL_Status HAL_GPIO_DisableVirtualModel(struct GPIO_REG *pGPIO)
  */
 HAL_Status HAL_GPIO_SetVirtualModel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_VirtualModel vmodel)
 {
-#if (GPIO_VER_ID == 0x01000C2BU)
+#if (GPIO_VER_ID >= 0x01000C2BU)
-    uint32_t low_pins, high_pins;
+    uint32_t lowPins, highPins;
 
-    low_pins = pin & 0x0000ffff;
+    lowPins = pin & 0x0000ffff;
-    high_pins = (pin & 0xffff0000) >> 16;
+    highPins = (pin & 0xffff0000) >> 16;
 
+#if defined(GPIO0_EXP)
     /* Support OS_A and OS_B */
     if (vmodel == GPIO_VIRTUAL_MODEL_OS_B) {
-        pGPIO->GPIO_REG_GROUP_L = low_pins << 16;
+        pGPIO->GPIO_REG_GROUP_L = lowPins << 16;
-        pGPIO->GPIO_REG_GROUP_H = high_pins << 16;
+        pGPIO->GPIO_REG_GROUP_H = highPins << 16;
     } else {
-        pGPIO->GPIO_REG_GROUP_L = low_pins | (low_pins << 16);
+        pGPIO->GPIO_REG_GROUP_L = lowPins | (lowPins << 16);
-        pGPIO->GPIO_REG_GROUP_H = high_pins | (high_pins << 16);
+        pGPIO->GPIO_REG_GROUP_H = highPins | (highPins << 16);
     }
 
     return HAL_OK;
+#elif defined(GPIO0_EXP3)
+    /* Support 4 OS */
+    switch (vmodel) {
+    case GPIO_VIRTUAL_MODEL_OS_A:
+        pGPIO->GPIO_REG_GROUP_L = lowPins | (lowPins << 16);
+        pGPIO->GPIO_REG_GROUP_H = highPins | (highPins << 16);
+        break;
+    case GPIO_VIRTUAL_MODEL_OS_B:
+        pGPIO->GPIO_REG_GROUP1_L = lowPins | (lowPins << 16);
+        pGPIO->GPIO_REG_GROUP1_H = highPins | (highPins << 16);
+        break;
+    case GPIO_VIRTUAL_MODEL_OS_C:
+        pGPIO->GPIO_REG_GROUP2_L = lowPins | (lowPins << 16);
+        pGPIO->GPIO_REG_GROUP2_H = highPins | (highPins << 16);
+        break;
+    case GPIO_VIRTUAL_MODEL_OS_D:
+        pGPIO->GPIO_REG_GROUP3_L = lowPins | (lowPins << 16);
+        pGPIO->GPIO_REG_GROUP3_H = highPins | (highPins << 16);
+        break;
+    default:
+        HAL_DBG("unknown gpio virtual model-%d\n", vmodel);
+        break;
+    }
+
+    return HAL_OK;
+#else
+#error missing GPIO EXP register definition!
+#endif
 #endif
 
     return HAL_ERROR;

Ubiquitous/XiZi_AIoT/services/drivers/3568/hal/test_gmac.c

@@ -85,7 +85,7 @@ struct GMAC_ETH_CONFIG {
 /********************* Private Variable Definition ***************************/
 
 
-static uint8_t dstAddr[6] = { 0x00, 0x0C, 0x29, 0xf8, 0x7a, 0x6b };
+static uint8_t dstAddr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff  };
 
 #if defined(HAL_GMAC_MODULE_ENABLED) && defined(SOC_RK3568)
 static struct GMAC_ETH_CONFIG ethConfigTable[] =
@@ -349,7 +349,6 @@ static void *malloc_align(size_t size, size_t align, uintptr_t va, uintptr_t *pa
     /* get total aligned size */
     align_size = ((size + 0x03) & ~0x03);
     /* allocate memory block from heap */
-    HAL_DBG("size: %d, align:%d\n",align_size, align);
     // ptr = malloc(align_size);
 
     if (naive_mmap(&va, pa, align_size, true) < 0){
@@ -417,7 +416,7 @@ static HAL_Status GMAC_Send_Test(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE
     }
 
     /* dump packages */
-    // Dump_Hex("Tx", ptr, len);
+    Dump_Hex("Tx", ptr, len);
 
     // HAL_DCACHE_CleanByRange((uint64_t)ptr, len);
     uint8_t * ptr_dma = (uint8_t *)HAL_GMAC_GetTXBufferDMA(pGMAC);
@@ -426,7 +425,6 @@ static HAL_Status GMAC_Send_Test(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE
         printf("GMAC send failed: %d\n", status);
     }
     
-    print_desc(pGMAC);
     return status;
 }
 
@@ -444,7 +442,6 @@ static uint16_t GMAC_Recv_Test(struct GMAC_HANDLE *pGMAC)
     status = GMAC_ETH_IRQ(pGMAC);
     ptr = HAL_GMAC_Recv(pGMAC, &size);
     while (status && ptr) {
-        print_desc(pGMAC);
         if (size > 0 && ptr) {
             /* dump packages */
             Dump_Hex("Rx", ptr, size);
@@ -462,20 +459,21 @@ static uint16_t GMAC_Recv_Test(struct GMAC_HANDLE *pGMAC)
 
 static HAL_Status GMAC_Memory_Init(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE *pGMAC)
 {   
-    uintptr_t rx_va = 0x1000000000, rx_pa = 0;
-    if (naive_mmap(&rx_va, &rx_pa, GMAC_DESC_RX_SIZE, true) < 0){
-        HAL_DBG("RX Desc alloc failed\n");
-    }
-    eth->rxDescs = (struct GMAC_Desc *)0x1000000000;
-    eth->rxDescs_dma = (struct GMAC_Desc *)rx_pa;
 
-    uintptr_t tx_va = 0x1000400000, tx_pa = 0;
+    uintptr_t tx_va = 0x1000000000, tx_pa = 0;
     if (naive_mmap(&tx_va, &tx_pa, GMAC_DESC_TX_SIZE, true) < 0){
         HAL_DBG("TX Desc alloc failed\n");
     }
-    eth->txDescs = (struct GMAC_Desc *)0x1000400000;
+    eth->txDescs = (struct GMAC_Desc *)0x1000000000;
     eth->txDescs_dma = (struct GMAC_Desc *)tx_pa;
 
+    uintptr_t rx_va = 0x1000400000, rx_pa = 0;
+    if (naive_mmap(&rx_va, &rx_pa, GMAC_DESC_RX_SIZE, true) < 0){
+        HAL_DBG("RX Desc alloc failed\n");
+    }
+    eth->rxDescs = (struct GMAC_Desc *)0x1000400000;
+    eth->rxDescs_dma = (struct GMAC_Desc *)rx_pa;
+
     if (!eth->rxDescs || !eth->txDescs_dma ||
         !eth->txDescs || !eth->txDescs_dma){
         return -1;
@@ -484,14 +482,16 @@ static HAL_Status GMAC_Memory_Init(struct GMAC_ETH_CONFIG *eth, struct GMAC_HAND
     HAL_DBG("rx:%p, %p\n",eth->rxDescs, eth->rxDescs_dma);
     HAL_DBG("tx:%p, %p\n",eth->txDescs, eth->txDescs_dma);
 
-    uintptr_t rxbuf_va = 0x1000800000, rxbuf_pa = 0;
+    
-    uintptr_t txbuf_va = 0x1000C00000, txbuf_pa = 0;
+    uintptr_t txbuf_va = 0x1000800000, txbuf_pa = 0;
-    eth->rxBuff = malloc_align(GMAC_RX_BUFFER_SIZE, ARCH_DMA_MINALIGN, rxbuf_va, &rxbuf_pa);
-    eth->rxBuff = (void *)0x1000800000;
-    eth->rxBuff_dma = (void *)rxbuf_pa;
     eth->txBuff = malloc_align(GMAC_TX_BUFFER_SIZE, ARCH_DMA_MINALIGN, txbuf_va, &txbuf_pa);
-    eth->txBuff = (void *)0x1000C00000;
+    eth->txBuff = (void *)0x1000800000;
     eth->txBuff_dma = (void *)txbuf_pa;
+
+    uintptr_t rxbuf_va = 0x1000c00000, rxbuf_pa = 0;
+    eth->rxBuff = malloc_align(GMAC_RX_BUFFER_SIZE, ARCH_DMA_MINALIGN, rxbuf_va, &rxbuf_pa);
+    eth->rxBuff = (void *)0x1000c00000;
+    eth->rxBuff_dma = (void *)rxbuf_pa;
     
     if (!eth->rxBuff || !eth->txBuff ||
         !eth->rxBuff_dma || !eth->txBuff_dma){   
@@ -499,8 +499,6 @@ static HAL_Status GMAC_Memory_Init(struct GMAC_ETH_CONFIG *eth, struct GMAC_HAND
     }
     HAL_DBG("rx_buff:%p,%p\n",eth->rxBuff, eth->rxBuff_dma);
     HAL_DBG("tx_buff:%p,%p,\n",eth->txBuff, eth->txBuff_dma);
-    HAL_DBG("GMAC_DESC_RX_SIZE:%d\n", GMAC_DESC_RX_SIZE);
-    HAL_DBG("GMAC_RX_BUFFER_SIZE:%d\n", GMAC_RX_BUFFER_SIZE);
     memset(eth->rxDescs, 0, GMAC_DESC_RX_SIZE);
     memset(eth->txDescs, 0, GMAC_DESC_TX_SIZE);
     memset(eth->rxBuff, 0, GMAC_RX_BUFFER_SIZE);
@@ -540,9 +538,9 @@ static HAL_Status GMAC_Init(uint8_t id)
     interface = eth->mode;
 
     if (interface == PHY_INTERFACE_MODE_RGMII) {
-        HAL_CRU_ClkSetFreq(gmacDev->clkID, 125000000);
+        HAL_CRU_ClkSetFreq(gmacDev->clkID125M, 125000000);
     } else {
-        HAL_CRU_ClkSetFreq(gmacDev->clkID, 50000000);
+        HAL_CRU_ClkSetFreq(gmacDev->clkID50M, 50000000);
     }
 
     freq = HAL_CRU_ClkGetFreq(gmacDev->pclkID);
@@ -583,7 +581,6 @@ static void GMAC0_Iomux_Config(void)
                          GPIO_PIN_B6, /* gmac0_rxd0 */
                          PIN_CONFIG_MUX_FUNC1);
     HAL_PINCTRL_SetIOMUX(GPIO_BANK2,
-                         GPIO_PIN_C0 | ///* eth0_refclko25m */
                          GPIO_PIN_C3 | /* gmac0_mdc */
                          GPIO_PIN_C4 | /* gmac0_mdio */
                          GPIO_PIN_C0 | /* gmac0_rxdvcrs */
@@ -646,19 +643,19 @@ int main() {
         } else {
             return -1;
         }
-        HAL_DBG("map GMAC0\n");
+
         if (!mmap(0x2000000000ULL+ GMAC0_BASE, GMAC0_BASE, 0x10000, true)) {
             printf("eth_hal: mmap GMAC0(%8x) failed\n", GMAC0);
             exit(1);
         }
-        HAL_DBG("map GPIO2\n");
+        
         if (!mmap(0x2000000000ULL + GPIO2_BASE, GPIO2_BASE, 0x10000, true)) {
             printf("eth_hal: mmap GPIO2(%8x) failed\n", GPIO2);
             exit(1);
         }
-        HAL_DBG("map GPIO3\n");
+        
         if (!mmap(0x2000000000ULL + GPIO3_BASE, GPIO3_BASE, 0x10000, true)) {
-            printf("eth_hal: mmap GPIO2(%8x) failed\n", GPIO2);
+            printf("eth_hal: mmap GPIO3(%8x) failed\n", GPIO3);
             exit(1);
         }
 
@@ -668,65 +665,69 @@ int main() {
         }
         
         if (!mmap(0x2000000000ULL + CRU_BASE, CRU_BASE, 0x10000, true)) {
-            printf("eth_hal: mmap GRF(%8x) failed\n", GRF);
+            printf("eth_hal: mmap CRU(%8x) failed\n", CRU);
             exit(1);
         }
-        if (!mmap(0x2000000000ULL + TIMER5_BASE, CRU_BASE, 32, true)) {
+        if (!mmap(0x2000000000ULL + TIMER5_BASE, TIMER5_BASE, 32, true)) {
-            printf("eth_hal: mmap GRF(%8x) failed\n", GRF);
+            printf("eth_hal: mmap TIMER5(%8x) failed\n", TIMER5);
             exit(1);
         }
         if (!mmap(0x2000000000ULL + PMUCRU_BASE, PMUCRU_BASE, 0x10000, true)) {
-            printf("eth_hal: mmap GRF(%8x) failed\n", GRF);
+            printf("eth_hal: mmap PMUCRU(%8x) failed\n", PMUCRU);
             exit(1);
         }
 
-        HAL_DBG("config iomux\n");
+        HAL_TIMER_SysTimerInit(TIMER5);
+
         /* ionmux */
         GMAC_Iomux_Config(bus);
-        HAL_DBG("config cru\n");
         HAL_CRU_ClkEnable(eth->halDev->pclkGateID);
-        HAL_CRU_ClkEnable(eth->halDev->clkGateID);
+        HAL_CRU_ClkEnable(eth->halDev->clkGateID125M);
+        HAL_CRU_ClkEnable(eth->halDev->clkGateID50M);
         
         /* Register irq */
         // register_irq(eth->halDev->irqNum, );
         /* PHY reset */
-        HAL_DBG("reset phy\n");
         GMAC_PHY_Reset(eth);
         
         /* GMAC Init */
-        HAL_DBG("init gmac\n");
         GMAC_Init(bus);
 
-        HAL_DBG("init memory\n");
         GMAC_Memory_Init(eth, pGMAC);
         
         /* Enable GMAC and DMA transmission and reception */
-        HAL_DBG("start gmac\n");
         HAL_GMAC_Start(pGMAC, eth->macAddr);
-        // print_desc(pGMAC);
+
         /* Update links information */
-        HAL_DBG("phy update link\n");
         PHY_Update_Links(eth, pGMAC, bus);
-        // print_desc(pGMAC);
+    
         /* Dump MAC Regs */
         Dump_Regs(pGMAC);
+
         /* Dump PHY Regs */
         // PHY_Dump(eth, pGMAC);
-        HAL_DBG("Init Down\n");
         for (i = 0; i < GMAC_TEST_TIMES; i++) {
-            HAL_DBG("TEST Send %d\n", i);
+            HAL_DBG("TEST %d\n", i);
+
             /* GMAC Send 64 bytes */
-            // GMAC_Send_Test(eth, pGMAC, 64);
+            HAL_DBG("--------------GMAC_Send_Test  START!--------------\n");	
-            /* GMAC Send 1500 bytes */
+            GMAC_Send_Test(eth, pGMAC, 64);
-            GMAC_Send_Test(eth, pGMAC, 1500);
+	        HAL_DBG("--------------GMAC_Send_Test  END!--------------\n");	
+           
             HAL_DelayMs(1000);
-            HAL_DBG("TEST Recv %d\n", i);
+            print_desc(pGMAC);
+            
             /* GMAC Recv */
+            HAL_DBG("--------------GMAC_Recv_Test  START! -------------- \n");
             GMAC_Recv_Test(pGMAC);
+            HAL_DBG("--------------GMAC_Recv_Test  END!!-------------- \n");
+
+            HAL_DelayMs(1000);
+            Dump_Regs(pGMAC);
         }
-        Dump_Regs(pGMAC);
         HAL_CRU_ClkDisable(eth->halDev->pclkGateID);
-        HAL_CRU_ClkDisable(eth->halDev->clkGateID);
+        HAL_CRU_ClkDisable(eth->halDev->clkGateID125M);
+        HAL_CRU_ClkDisable(eth->halDev->clkGateID50M);
 
         // free_align(eth->txBuff);
         // free_align(eth->rxBuff);

Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_cru.h

@@ -159,6 +159,11 @@ typedef enum {
     GLB_RST_SND_WDT1,
     GLB_RST_FST_WDT2,
     GLB_RST_SND_WDT2,
+    GLB_RST_FST_WDT3,
+    GLB_RST_SND_WDT3,
+    GLB_RST_FST_WDT4,
+    GLB_RST_SND_WDT4,
+
 } eCRU_WdtRstType;
 
 struct CRU_BANK_INFO {
@@ -192,12 +197,14 @@ int HAL_CRU_FreqGetMux4(uint32_t freq, uint32_t freq0, uint32_t freq1,
 int HAL_CRU_FreqGetMux3(uint32_t freq, uint32_t freq0, uint32_t freq1,
                         uint32_t freq2);
 int HAL_CRU_FreqGetMux2(uint32_t freq, uint32_t freq0, uint32_t freq1);
+int HAL_CRU_FreqGetMuxArray(uint32_t freq, uint32_t *table, int num);
 
 uint32_t HAL_CRU_MuxGetFreq4(uint32_t muxName, uint32_t freq0, uint32_t freq1,
                              uint32_t freq2, uint32_t freq3);
 uint32_t HAL_CRU_MuxGetFreq3(uint32_t muxName, uint32_t freq0, uint32_t freq1,
                              uint32_t freq2);
 uint32_t HAL_CRU_MuxGetFreq2(uint32_t muxName, uint32_t freq0, uint32_t freq1);
+uint32_t HAL_CRU_MuxGetFreqArray(uint32_t muxName, uint32_t *table, int num);
 
 int HAL_CRU_RoundFreqGetMux4(uint32_t freq, uint32_t pFreq0, uint32_t pFreq1,
                              uint32_t pFreq2, uint32_t pFreq3, uint32_t *pFreqOut);
@@ -205,6 +212,7 @@ int HAL_CRU_RoundFreqGetMux3(uint32_t freq, uint32_t pFreq0, uint32_t pFreq1,
                              uint32_t pFreq2, uint32_t *pFreqOut);
 int HAL_CRU_RoundFreqGetMux2(uint32_t freq, uint32_t pFreq0, uint32_t pFreq1,
                              uint32_t *pFreqOut);
+int HAL_CRU_RoundFreqGetMuxArray(uint32_t freq, uint32_t *table, int num, uint32_t *pFreqOut, bool is_div);
 
 /** @} */
 
@@ -371,6 +379,21 @@ uint32_t HAL_CRU_ClkGetMux(uint32_t muxName);
 HAL_Status HAL_CRU_FracdivGetConfig(uint32_t rateOut, uint32_t rate,
                                     uint32_t *numerator,
                                     uint32_t *denominator);
+
+
+/**
+ * @brief  Get frac div config V2(24bit).
+ * @param  rateOut: clk out rate.
+ * @param  rate: clk src rate.
+ * @param  numerator: the returned numerator.
+ * @param  denominator: the returned denominator.
+ * @return HAL_Status.
+ */
+HAL_Status HAL_CRU_FracdivGetConfigV2(uint32_t rateOut, uint32_t rate,
+                                      uint32_t *numerator,
+                                      uint32_t *denominator);
+                                      
+
 /**
  * @brief Get clk freq.
  * @param  clockName: CLOCK_Name id.

Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_gmac.h

@@ -207,10 +207,10 @@ struct GMAC_Link {
   * @brief  GMAC DMA Descriptors Data Structure Definition
   */
 struct GMAC_Desc {
-    uint32_t des0; /**< DMA Descriptors first word */
+    volatile uint32_t des0; /**< DMA Descriptors first word */
-    uint32_t des1; /**< DMA Descriptors second word */
+    volatile uint32_t des1; /**< DMA Descriptors second word */
-    uint32_t des2; /**< DMA Descriptors third word */
+    volatile uint32_t des2; /**< DMA Descriptors third word */
-    uint32_t des3; /**< DMA Descriptors four word */
+    volatile uint32_t des3; /**< DMA Descriptors four word */
 };
 
 /**
@@ -287,8 +287,10 @@ struct GMAC_HANDLE {
   */
 struct HAL_GMAC_DEV {
     struct GMAC_REG *pReg;
-    eCLOCK_Name clkID;
+    eCLOCK_Name clkID125M;
-    uint32_t clkGateID;
+    eCLOCK_Name clkID50M;
+    uint32_t clkGateID125M;
+    uint32_t clkGateID50M;
     eCLOCK_Name pclkID;
     uint32_t pclkGateID;
     IRQn_Type irqNum;

Ubiquitous/XiZi_AIoT/services/drivers/3568/include/hal_pinctrl.h

@@ -370,6 +370,516 @@ typedef enum {
     GPIO4_EXP_D5,
     GPIO4_EXP_D6,
     GPIO4_EXP_D7,
+#endif
+#if defined(GPIO0_EXP1)
+    GPIO0_EXP1_A0 = 160,
+    GPIO0_EXP1_A1,
+    GPIO0_EXP1_A2,
+    GPIO0_EXP1_A3,
+    GPIO0_EXP1_A4,
+    GPIO0_EXP1_A5,
+    GPIO0_EXP1_A6,
+    GPIO0_EXP1_A7,
+    GPIO0_EXP1_B0 = 168,
+    GPIO0_EXP1_B1,
+    GPIO0_EXP1_B2,
+    GPIO0_EXP1_B3,
+    GPIO0_EXP1_B4,
+    GPIO0_EXP1_B5,
+    GPIO0_EXP1_B6,
+    GPIO0_EXP1_B7,
+    GPIO0_EXP1_C0 = 176,
+    GPIO0_EXP1_C1,
+    GPIO0_EXP1_C2,
+    GPIO0_EXP1_C3,
+    GPIO0_EXP1_C4,
+    GPIO0_EXP1_C5,
+    GPIO0_EXP1_C6,
+    GPIO0_EXP1_C7,
+    GPIO0_EXP1_D0 = 184,
+    GPIO0_EXP1_D1,
+    GPIO0_EXP1_D2,
+    GPIO0_EXP1_D3,
+    GPIO0_EXP1_D4,
+    GPIO0_EXP1_D5,
+    GPIO0_EXP1_D6,
+    GPIO0_EXP1_D7,
+#endif
+#if defined(GPIO1_EXP1)
+    GPIO1_EXP1_A0 = 192,
+    GPIO1_EXP1_A1,
+    GPIO1_EXP1_A2,
+    GPIO1_EXP1_A3,
+    GPIO1_EXP1_A4,
+    GPIO1_EXP1_A5,
+    GPIO1_EXP1_A6,
+    GPIO1_EXP1_A7,
+    GPIO1_EXP1_B0 = 200,
+    GPIO1_EXP1_B1,
+    GPIO1_EXP1_B2,
+    GPIO1_EXP1_B3,
+    GPIO1_EXP1_B4,
+    GPIO1_EXP1_B5,
+    GPIO1_EXP1_B6,
+    GPIO1_EXP1_B7,
+    GPIO1_EXP1_C0 = 208,
+    GPIO1_EXP1_C1,
+    GPIO1_EXP1_C2,
+    GPIO1_EXP1_C3,
+    GPIO1_EXP1_C4,
+    GPIO1_EXP1_C5,
+    GPIO1_EXP1_C6,
+    GPIO1_EXP1_C7,
+    GPIO1_EXP1_D0 = 216,
+    GPIO1_EXP1_D1,
+    GPIO1_EXP1_D2,
+    GPIO1_EXP1_D3,
+    GPIO1_EXP1_D4,
+    GPIO1_EXP1_D5,
+    GPIO1_EXP1_D6,
+    GPIO1_EXP1_D7,
+#endif
+#if defined(GPIO2_EXP1)
+    GPIO2_EXP1_A0 = 224,
+    GPIO2_EXP1_A1,
+    GPIO2_EXP1_A2,
+    GPIO2_EXP1_A3,
+    GPIO2_EXP1_A4,
+    GPIO2_EXP1_A5,
+    GPIO2_EXP1_A6,
+    GPIO2_EXP1_A7,
+    GPIO2_EXP1_B0 = 232,
+    GPIO2_EXP1_B1,
+    GPIO2_EXP1_B2,
+    GPIO2_EXP1_B3,
+    GPIO2_EXP1_B4,
+    GPIO2_EXP1_B5,
+    GPIO2_EXP1_B6,
+    GPIO2_EXP1_B7,
+    GPIO2_EXP1_C0 = 240,
+    GPIO2_EXP1_C1,
+    GPIO2_EXP1_C2,
+    GPIO2_EXP1_C3,
+    GPIO2_EXP1_C4,
+    GPIO2_EXP1_C5,
+    GPIO2_EXP1_C6,
+    GPIO2_EXP1_C7,
+    GPIO2_EXP1_D0 = 248,
+    GPIO2_EXP1_D1,
+    GPIO2_EXP1_D2,
+    GPIO2_EXP1_D3,
+    GPIO2_EXP1_D4,
+    GPIO2_EXP1_D5,
+    GPIO2_EXP1_D6,
+    GPIO2_EXP1_D7,
+#endif
+#if defined(GPIO3_EXP1)
+    GPIO3_EXP1_A0 = 256,
+    GPIO3_EXP1_A1,
+    GPIO3_EXP1_A2,
+    GPIO3_EXP1_A3,
+    GPIO3_EXP1_A4,
+    GPIO3_EXP1_A5,
+    GPIO3_EXP1_A6,
+    GPIO3_EXP1_A7,
+    GPIO3_EXP1_B0 = 264,
+    GPIO3_EXP1_B1,
+    GPIO3_EXP1_B2,
+    GPIO3_EXP1_B3,
+    GPIO3_EXP1_B4,
+    GPIO3_EXP1_B5,
+    GPIO3_EXP1_B6,
+    GPIO3_EXP1_B7,
+    GPIO3_EXP1_C0 = 272,
+    GPIO3_EXP1_C1,
+    GPIO3_EXP1_C2,
+    GPIO3_EXP1_C3,
+    GPIO3_EXP1_C4,
+    GPIO3_EXP1_C5,
+    GPIO3_EXP1_C6,
+    GPIO3_EXP1_C7,
+    GPIO3_EXP1_D0 = 280,
+    GPIO3_EXP1_D1,
+    GPIO3_EXP1_D2,
+    GPIO3_EXP1_D3,
+    GPIO3_EXP1_D4,
+    GPIO3_EXP1_D5,
+    GPIO3_EXP1_D6,
+    GPIO3_EXP1_D7,
+#endif
+#if defined(GPIO4_EXP1)
+    GPIO4_EXP1_A0 = 288,
+    GPIO4_EXP1_A1,
+    GPIO4_EXP1_A2,
+    GPIO4_EXP1_A3,
+    GPIO4_EXP1_A4,
+    GPIO4_EXP1_A5,
+    GPIO4_EXP1_A6,
+    GPIO4_EXP1_A7,
+    GPIO4_EXP1_B0 = 296,
+    GPIO4_EXP1_B1,
+    GPIO4_EXP1_B2,
+    GPIO4_EXP1_B3,
+    GPIO4_EXP1_B4,
+    GPIO4_EXP1_B5,
+    GPIO4_EXP1_B6,
+    GPIO4_EXP1_B7,
+    GPIO4_EXP1_C0 = 304,
+    GPIO4_EXP1_C1,
+    GPIO4_EXP1_C2,
+    GPIO4_EXP1_C3,
+    GPIO4_EXP1_C4,
+    GPIO4_EXP1_C5,
+    GPIO4_EXP1_C6,
+    GPIO4_EXP1_C7,
+    GPIO4_EXP1_D0 = 312,
+    GPIO4_EXP1_D1,
+    GPIO4_EXP1_D2,
+    GPIO4_EXP1_D3,
+    GPIO4_EXP1_D4,
+    GPIO4_EXP1_D5,
+    GPIO4_EXP1_D6,
+    GPIO4_EXP1_D7,
+#endif
+#if defined(GPIO0_EXP2)
+    GPIO0_EXP2_A0 = 320,
+    GPIO0_EXP2_A1,
+    GPIO0_EXP2_A2,
+    GPIO0_EXP2_A3,
+    GPIO0_EXP2_A4,
+    GPIO0_EXP2_A5,
+    GPIO0_EXP2_A6,
+    GPIO0_EXP2_A7,
+    GPIO0_EXP2_B0 = 328,
+    GPIO0_EXP2_B1,
+    GPIO0_EXP2_B2,
+    GPIO0_EXP2_B3,
+    GPIO0_EXP2_B4,
+    GPIO0_EXP2_B5,
+    GPIO0_EXP2_B6,
+    GPIO0_EXP2_B7,
+    GPIO0_EXP2_C0 = 336,
+    GPIO0_EXP2_C1,
+    GPIO0_EXP2_C2,
+    GPIO0_EXP2_C3,
+    GPIO0_EXP2_C4,
+    GPIO0_EXP2_C5,
+    GPIO0_EXP2_C6,
+    GPIO0_EXP2_C7,
+    GPIO0_EXP2_D0 = 344,
+    GPIO0_EXP2_D1,
+    GPIO0_EXP2_D2,
+    GPIO0_EXP2_D3,
+    GPIO0_EXP2_D4,
+    GPIO0_EXP2_D5,
+    GPIO0_EXP2_D6,
+    GPIO0_EXP2_D7,
+#endif
+#if defined(GPIO1_EXP2)
+    GPIO1_EXP2_A0 = 352,
+    GPIO1_EXP2_A1,
+    GPIO1_EXP2_A2,
+    GPIO1_EXP2_A3,
+    GPIO1_EXP2_A4,
+    GPIO1_EXP2_A5,
+    GPIO1_EXP2_A6,
+    GPIO1_EXP2_A7,
+    GPIO1_EXP2_B0 = 360,
+    GPIO1_EXP2_B1,
+    GPIO1_EXP2_B2,
+    GPIO1_EXP2_B3,
+    GPIO1_EXP2_B4,
+    GPIO1_EXP2_B5,
+    GPIO1_EXP2_B6,
+    GPIO1_EXP2_B7,
+    GPIO1_EXP2_C0 = 368,
+    GPIO1_EXP2_C1,
+    GPIO1_EXP2_C2,
+    GPIO1_EXP2_C3,
+    GPIO1_EXP2_C4,
+    GPIO1_EXP2_C5,
+    GPIO1_EXP2_C6,
+    GPIO1_EXP2_C7,
+    GPIO1_EXP2_D0 = 376,
+    GPIO1_EXP2_D1,
+    GPIO1_EXP2_D2,
+    GPIO1_EXP2_D3,
+    GPIO1_EXP2_D4,
+    GPIO1_EXP2_D5,
+    GPIO1_EXP2_D6,
+    GPIO1_EXP2_D7,
+#endif
+#if defined(GPIO2_EXP2)
+    GPIO2_EXP2_A0 = 384,
+    GPIO2_EXP2_A1,
+    GPIO2_EXP2_A2,
+    GPIO2_EXP2_A3,
+    GPIO2_EXP2_A4,
+    GPIO2_EXP2_A5,
+    GPIO2_EXP2_A6,
+    GPIO2_EXP2_A7,
+    GPIO2_EXP2_B0 = 392,
+    GPIO2_EXP2_B1,
+    GPIO2_EXP2_B2,
+    GPIO2_EXP2_B3,
+    GPIO2_EXP2_B4,
+    GPIO2_EXP2_B5,
+    GPIO2_EXP2_B6,
+    GPIO2_EXP2_B7,
+    GPIO2_EXP2_C0 = 400,
+    GPIO2_EXP2_C1,
+    GPIO2_EXP2_C2,
+    GPIO2_EXP2_C3,
+    GPIO2_EXP2_C4,
+    GPIO2_EXP2_C5,
+    GPIO2_EXP2_C6,
+    GPIO2_EXP2_C7,
+    GPIO2_EXP2_D0 = 408,
+    GPIO2_EXP2_D1,
+    GPIO2_EXP2_D2,
+    GPIO2_EXP2_D3,
+    GPIO2_EXP2_D4,
+    GPIO2_EXP2_D5,
+    GPIO2_EXP2_D6,
+    GPIO2_EXP2_D7,
+#endif
+#if defined(GPIO3_EXP2)
+    GPIO3_EXP2_A0 = 416,
+    GPIO3_EXP2_A1,
+    GPIO3_EXP2_A2,
+    GPIO3_EXP2_A3,
+    GPIO3_EXP2_A4,
+    GPIO3_EXP2_A5,
+    GPIO3_EXP2_A6,
+    GPIO3_EXP2_A7,
+    GPIO3_EXP2_B0 = 424,
+    GPIO3_EXP2_B1,
+    GPIO3_EXP2_B2,
+    GPIO3_EXP2_B3,
+    GPIO3_EXP2_B4,
+    GPIO3_EXP2_B5,
+    GPIO3_EXP2_B6,
+    GPIO3_EXP2_B7,
+    GPIO3_EXP2_C0 = 432,
+    GPIO3_EXP2_C1,
+    GPIO3_EXP2_C2,
+    GPIO3_EXP2_C3,
+    GPIO3_EXP2_C4,
+    GPIO3_EXP2_C5,
+    GPIO3_EXP2_C6,
+    GPIO3_EXP2_C7,
+    GPIO3_EXP2_D0 = 440,
+    GPIO3_EXP2_D1,
+    GPIO3_EXP2_D2,
+    GPIO3_EXP2_D3,
+    GPIO3_EXP2_D4,
+    GPIO3_EXP2_D5,
+    GPIO3_EXP2_D6,
+    GPIO3_EXP2_D7,
+#endif
+#if defined(GPIO4_EXP2)
+    GPIO4_EXP2_A0 = 448,
+    GPIO4_EXP2_A1,
+    GPIO4_EXP2_A2,
+    GPIO4_EXP2_A3,
+    GPIO4_EXP2_A4,
+    GPIO4_EXP2_A5,
+    GPIO4_EXP2_A6,
+    GPIO4_EXP2_A7,
+    GPIO4_EXP2_B0 = 456,
+    GPIO4_EXP2_B1,
+    GPIO4_EXP2_B2,
+    GPIO4_EXP2_B3,
+    GPIO4_EXP2_B4,
+    GPIO4_EXP2_B5,
+    GPIO4_EXP2_B6,
+    GPIO4_EXP2_B7,
+    GPIO4_EXP2_C0 = 464,
+    GPIO4_EXP2_C1,
+    GPIO4_EXP2_C2,
+    GPIO4_EXP2_C3,
+    GPIO4_EXP2_C4,
+    GPIO4_EXP2_C5,
+    GPIO4_EXP2_C6,
+    GPIO4_EXP2_C7,
+    GPIO4_EXP2_D0 = 472,
+    GPIO4_EXP2_D1,
+    GPIO4_EXP2_D2,
+    GPIO4_EXP2_D3,
+    GPIO4_EXP2_D4,
+    GPIO4_EXP2_D5,
+    GPIO4_EXP2_D6,
+    GPIO4_EXP2_D7,
+#endif
+#if defined(GPIO0_EXP3)
+    GPIO0_EXP3_A0 = 480,
+    GPIO0_EXP3_A1,
+    GPIO0_EXP3_A2,
+    GPIO0_EXP3_A3,
+    GPIO0_EXP3_A4,
+    GPIO0_EXP3_A5,
+    GPIO0_EXP3_A6,
+    GPIO0_EXP3_A7,
+    GPIO0_EXP3_B0 = 488,
+    GPIO0_EXP3_B1,
+    GPIO0_EXP3_B2,
+    GPIO0_EXP3_B3,
+    GPIO0_EXP3_B4,
+    GPIO0_EXP3_B5,
+    GPIO0_EXP3_B6,
+    GPIO0_EXP3_B7,
+    GPIO0_EXP3_C0 = 496,
+    GPIO0_EXP3_C1,
+    GPIO0_EXP3_C2,
+    GPIO0_EXP3_C3,
+    GPIO0_EXP3_C4,
+    GPIO0_EXP3_C5,
+    GPIO0_EXP3_C6,
+    GPIO0_EXP3_C7,
+    GPIO0_EXP3_D0 = 504,
+    GPIO0_EXP3_D1,
+    GPIO0_EXP3_D2,
+    GPIO0_EXP3_D3,
+    GPIO0_EXP3_D4,
+    GPIO0_EXP3_D5,
+    GPIO0_EXP3_D6,
+    GPIO0_EXP3_D7,
+#endif
+#if defined(GPIO1_EXP3)
+    GPIO1_EXP3_A0 = 512,
+    GPIO1_EXP3_A1,
+    GPIO1_EXP3_A2,
+    GPIO1_EXP3_A3,
+    GPIO1_EXP3_A4,
+    GPIO1_EXP3_A5,
+    GPIO1_EXP3_A6,
+    GPIO1_EXP3_A7,
+    GPIO1_EXP3_B0 = 520,
+    GPIO1_EXP3_B1,
+    GPIO1_EXP3_B2,
+    GPIO1_EXP3_B3,
+    GPIO1_EXP3_B4,
+    GPIO1_EXP3_B5,
+    GPIO1_EXP3_B6,
+    GPIO1_EXP3_B7,
+    GPIO1_EXP3_C0 = 528,
+    GPIO1_EXP3_C1,
+    GPIO1_EXP3_C2,
+    GPIO1_EXP3_C3,
+    GPIO1_EXP3_C4,
+    GPIO1_EXP3_C5,
+    GPIO1_EXP3_C6,
+    GPIO1_EXP3_C7,
+    GPIO1_EXP3_D0 = 536,
+    GPIO1_EXP3_D1,
+    GPIO1_EXP3_D2,
+    GPIO1_EXP3_D3,
+    GPIO1_EXP3_D4,
+    GPIO1_EXP3_D5,
+    GPIO1_EXP3_D6,
+    GPIO1_EXP3_D7,
+#endif
+#if defined(GPIO2_EXP3)
+    GPIO2_EXP3_A0 = 544,
+    GPIO2_EXP3_A1,
+    GPIO2_EXP3_A2,
+    GPIO2_EXP3_A3,
+    GPIO2_EXP3_A4,
+    GPIO2_EXP3_A5,
+    GPIO2_EXP3_A6,
+    GPIO2_EXP3_A7,
+    GPIO2_EXP3_B0 = 552,
+    GPIO2_EXP3_B1,
+    GPIO2_EXP3_B2,
+    GPIO2_EXP3_B3,
+    GPIO2_EXP3_B4,
+    GPIO2_EXP3_B5,
+    GPIO2_EXP3_B6,
+    GPIO2_EXP3_B7,
+    GPIO2_EXP3_C0 = 560,
+    GPIO2_EXP3_C1,
+    GPIO2_EXP3_C2,
+    GPIO2_EXP3_C3,
+    GPIO2_EXP3_C4,
+    GPIO2_EXP3_C5,
+    GPIO2_EXP3_C6,
+    GPIO2_EXP3_C7,
+    GPIO2_EXP3_D0 = 568,
+    GPIO2_EXP3_D1,
+    GPIO2_EXP3_D2,
+    GPIO2_EXP3_D3,
+    GPIO2_EXP3_D4,
+    GPIO2_EXP3_D5,
+    GPIO2_EXP3_D6,
+    GPIO2_EXP3_D7,
+#endif
+#if defined(GPIO3_EXP3)
+    GPIO3_EXP3_A0 = 576,
+    GPIO3_EXP3_A1,
+    GPIO3_EXP3_A2,
+    GPIO3_EXP3_A3,
+    GPIO3_EXP3_A4,
+    GPIO3_EXP3_A5,
+    GPIO3_EXP3_A6,
+    GPIO3_EXP3_A7,
+    GPIO3_EXP3_B0 = 584,
+    GPIO3_EXP3_B1,
+    GPIO3_EXP3_B2,
+    GPIO3_EXP3_B3,
+    GPIO3_EXP3_B4,
+    GPIO3_EXP3_B5,
+    GPIO3_EXP3_B6,
+    GPIO3_EXP3_B7,
+    GPIO3_EXP3_C0 = 592,
+    GPIO3_EXP3_C1,
+    GPIO3_EXP3_C2,
+    GPIO3_EXP3_C3,
+    GPIO3_EXP3_C4,
+    GPIO3_EXP3_C5,
+    GPIO3_EXP3_C6,
+    GPIO3_EXP3_C7,
+    GPIO3_EXP3_D0 = 600,
+    GPIO3_EXP3_D1,
+    GPIO3_EXP3_D2,
+    GPIO3_EXP3_D3,
+    GPIO3_EXP3_D4,
+    GPIO3_EXP3_D5,
+    GPIO3_EXP3_D6,
+    GPIO3_EXP3_D7,
+#endif
+#if defined(GPIO4_EXP3)
+    GPIO4_EXP3_A0 = 608,
+    GPIO4_EXP3_A1,
+    GPIO4_EXP3_A2,
+    GPIO4_EXP3_A3,
+    GPIO4_EXP3_A4,
+    GPIO4_EXP3_A5,
+    GPIO4_EXP3_A6,
+    GPIO4_EXP3_A7,
+    GPIO4_EXP3_B0 = 616,
+    GPIO4_EXP3_B1,
+    GPIO4_EXP3_B2,
+    GPIO4_EXP3_B3,
+    GPIO4_EXP3_B4,
+    GPIO4_EXP3_B5,
+    GPIO4_EXP3_B6,
+    GPIO4_EXP3_B7,
+    GPIO4_EXP3_C0 = 624,
+    GPIO4_EXP3_C1,
+    GPIO4_EXP3_C2,
+    GPIO4_EXP3_C3,
+    GPIO4_EXP3_C4,
+    GPIO4_EXP3_C5,
+    GPIO4_EXP3_C6,
+    GPIO4_EXP3_C7,
+    GPIO4_EXP3_D0 = 632,
+    GPIO4_EXP3_D1,
+    GPIO4_EXP3_D2,
+    GPIO4_EXP3_D3,
+    GPIO4_EXP3_D4,
+    GPIO4_EXP3_D5,
+    GPIO4_EXP3_D6,
+    GPIO4_EXP3_D7,
 #endif
     GPIO_NUM_MAX
 } ePINCTRL_PIN;
@@ -476,7 +986,7 @@ typedef enum {
     PIN_CONFIG_PUL_UP      = PIN_CONFIG_PUL_DEFAULT,
     PIN_CONFIG_PUL_DOWN    = PIN_CONFIG_PUL_DEFAULT,
     PIN_CONFIG_PUL_KEEP    = PIN_CONFIG_PUL_DEFAULT,
-#elif defined(SOC_RK3588)
+#elif defined(SOC_RK3588) || defined(SOC_RK3576)
     PIN_CONFIG_PUL_NORMAL  = (0x0 << SHIFT_PUL | FLAG_PUL),
     PIN_CONFIG_PUL_DOWN    = (0x1 << SHIFT_PUL | FLAG_PUL),
     PIN_CONFIG_PUL_KEEP    = (0x2 << SHIFT_PUL | FLAG_PUL),
@@ -490,7 +1000,7 @@ typedef enum {
     PIN_CONFIG_PUL_DEFAULT = PIN_CONFIG_PUL_NORMAL,
 #endif
 
-#if defined(SOC_RK3568) || defined(SOC_RV1106) || defined(SOC_RK3562)
+#if defined(SOC_RK3568) || defined(SOC_RV1106) || defined(SOC_RK3562) || defined(RKMCU_RK2118)
     PIN_CONFIG_DRV_LEVEL0        = (0x1 << SHIFT_DRV | FLAG_DRV),
     PIN_CONFIG_DRV_LEVEL1        = (0x3 << SHIFT_DRV | FLAG_DRV),
     PIN_CONFIG_DRV_LEVEL2        = (0x7 << SHIFT_DRV | FLAG_DRV),
@@ -504,6 +1014,14 @@ typedef enum {
     PIN_CONFIG_DRV_LEVEL2        = (0x1 << SHIFT_DRV | FLAG_DRV),
     PIN_CONFIG_DRV_LEVEL3        = (0x3 << SHIFT_DRV | FLAG_DRV),
     PIN_CONFIG_DRV_LEVEL_DEFAULT = PIN_CONFIG_DRV_LEVEL2,
+#elif defined(SOC_RK3576)
+    PIN_CONFIG_DRV_LEVEL0        = (0x0 << SHIFT_DRV | FLAG_DRV),
+    PIN_CONFIG_DRV_LEVEL1        = (0x4 << SHIFT_DRV | FLAG_DRV),
+    PIN_CONFIG_DRV_LEVEL2        = (0x2 << SHIFT_DRV | FLAG_DRV),
+    PIN_CONFIG_DRV_LEVEL3        = (0x6 << SHIFT_DRV | FLAG_DRV),
+    PIN_CONFIG_DRV_LEVEL4        = (0x1 << SHIFT_DRV | FLAG_DRV),
+    PIN_CONFIG_DRV_LEVEL5        = (0x5 << SHIFT_DRV | FLAG_DRV),
+    PIN_CONFIG_DRV_LEVEL_DEFAULT = PIN_CONFIG_DRV_LEVEL2,
 #else
     PIN_CONFIG_DRV_LEVEL0        = (0x0 << SHIFT_DRV | FLAG_DRV),
     PIN_CONFIG_DRV_LEVEL1        = (0x1 << SHIFT_DRV | FLAG_DRV),
@@ -678,6 +1196,9 @@ HAL_Status HAL_PINCTRL_DeInit(void);
 
 HAL_Status HAL_PINCTRL_SetParam(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param);
 HAL_Status HAL_PINCTRL_SetIOMUX(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param);
+#ifdef RM0_IO
+HAL_Status HAL_PINCTRL_SetRMIO(eGPIO_bankId bank, uint32_t rmioPin, eRMIO_Name rmioFunc);
+#endif
 
 HAL_Status HAL_PINCTRL_IOFuncSelForCIF(eIOFUNC_SEL mode);
 HAL_Status HAL_PINCTRL_IOFuncSelForEMMC(eIOFUNC_SEL mode);

Ubiquitous/XiZi_AIoT/services/drivers/3568/include/soc.h

@@ -415,6 +415,7 @@ typedef enum CLOCK_Name {
     ACLK_USB               = CLK(ACLK_USB_SEL, 0U),
     HCLK_USB               = CLK(HCLK_USB_SEL, 0U),
     PCLK_USB               = CLK(0U, PCLK_USB_DIV),
+    CLK_SDMMC0             = CLK(CLK_SDMMC0_SEL, 0U),
 } eCLOCK_Name;
 #endif
 /****************************************MBOX********************************************/
@@ -425,10 +426,10 @@ typedef enum CLOCK_Name {
 #define GRF_DS_BIT_PER_PIN	(8)
 #define GRF_PULL_BIT_PER_PIN	(2)
 /****************************************GPIO********************************************/
-#ifdef GPIO_VER_ID
+// #ifdef GPIO_VER_ID
-#undef GPIO_VER_ID
+// #undef GPIO_VER_ID
-#define GPIO_VER_ID             (0x01000C2BU)
+// #define GPIO_VER_ID             (0x01000C2BU)
-#endif
+// #endif
 /****************************************PMU*********************************************/
 #ifndef __ASSEMBLY__
 typedef enum PD_Id {
@@ -438,6 +439,10 @@ typedef enum PD_Id {
 /****************************************FSPI********************************************/
 #define FSPI_CHIP_CNT                            (2)
 
+/****************************************WDT*********************************************/
+#define GLB_RST_SND_WDT GLB_RST_SND_WDT0
+#define GLB_RST_FST_WDT GLB_RST_FST_WDT0
+
 #ifdef __cplusplus
 }
 #endif /* __cplusplus */

Ubiquitous/XiZi_AIoT/services/fs/fs_server/fs.c

@@ -63,7 +63,7 @@ static struct FileDescriptor fd_table[MAX_SUPPORT_FD];
 struct MemFsRange MemFsRange;
 
 /// @brief Using syscall to get fs.img real location in the memory
-void MemFsInit(uintptr_t _binary_fs_img_start, uint32_t fs_img_len)
+void MemFsInit(uintptr_t _binary_fs_img_start, uintptr_t fs_img_len)
 {
     MemFsRange.memfs_start = _binary_fs_img_start;
     MemFsRange.memfs_nr_blocks = fs_img_len / BLOCK_SIZE;
@@ -251,12 +251,12 @@ struct Inode* InodeParentSeek(struct Inode* source, char* path, char* name)
 /// @brief Alloc a new Inode using type
 static struct Inode* InodeAlloc(int type)
 {
-    int inum;
+    int inum = 0;
     struct Inode* inode;
     struct SuperBlock sb;
 
     ReadSuperBlock(&sb);
-    for (inum = 1; inum < sb.ninodes; inum++) {
+    for (inum = 1; inum < (int)sb.ninodes; inum++) {
         uint8_t* block = BlockRead(BLOCK_INDEX(inum));
         inode = (struct Inode*)block + INODE_INDEX(inum);
         if (inode->type == 0) {

Ubiquitous/XiZi_AIoT/services/fs/fs_server/fs_server.c

@@ -352,10 +352,10 @@ int main(int argc, char* argv[])
     sys_state_info info;
     get_memblock_info(&info);
 
-    int len = info.memblock_info.memblock_end - info.memblock_info.memblock_start;
+    uintptr_t len = info.memblock_info.memblock_end - info.memblock_info.memblock_start;
     mmap(FS_IMG_ADDR, info.memblock_info.memblock_start, len, false);
 
-    MemFsInit((uintptr_t)FS_IMG_ADDR, (uint32_t)len);
+    MemFsInit((uintptr_t)FS_IMG_ADDR, (uintptr_t)len);
 
     if (register_server("MemFS") < 0) {
         printf("register server name: %s failed.\n", "MemFs");

Ubiquitous/XiZi_AIoT/services/fs/fs_server/include/fs.h

@@ -61,7 +61,7 @@ Modification:
 // memory fs range
 struct MemFsRange {
     uintptr_t memfs_start;
-    uint32_t memfs_nr_blocks;
+    uintptr_t memfs_nr_blocks;
 };
 
 // memfs file type
@@ -89,9 +89,9 @@ struct Inode {
 };
 
 // directory entry
-#define DIR_NAME_SIZE 30
+#define DIR_NAME_SIZE 28
 struct DirectEntry {
-    uint16_t inum;
+    uint32_t inum;
     char name[DIR_NAME_SIZE];
 };
 
@@ -105,7 +105,7 @@ struct FileDescriptor {
 // range of memory fs
 extern struct MemFsRange MemFsRange;
 
-void MemFsInit(uintptr_t _binary_fs_img_start, uint32_t fs_img_len);
+void MemFsInit(uintptr_t _binary_fs_img_start, uintptr_t fs_img_len);
 void ReadSuperBlock(struct SuperBlock*);
 
 // fs Inode ops

Ubiquitous/XiZi_AIoT/services/lib/ipc/libipc.c

@@ -131,14 +131,14 @@ bool ipc_msg_get_nth_arg(struct IpcMsg* msg, const int arg_num, void* data, cons
     return true;
 }
 
-void ipc_msg_send_wait(struct IpcMsg* msg)
+void ipc_msg_send_wait(struct Session* session, struct IpcMsg* msg)
 {
     msg->header.magic = IPC_MSG_MAGIC;
     msg->header.valid = 1;
     msg->header.done = 0;
     while (msg->header.done == 0) {
         /// @todo syscall yield with prio decrease
-        yield(SYS_TASK_YIELD_BLOCK_IPC);
+        wait_session_call(session);
     }
     assert(msg->header.done == 1);
 }
@@ -155,7 +155,7 @@ int ipc_session_wait(struct Session* session)
     struct IpcMsg* msg = IPCSESSION_MSG(session);
     while (msg->header.done == 0) {
         /// @todo syscall yield with prio decrease
-        yield(SYS_TASK_YIELD_BLOCK_IPC);
+        wait_session_call(session);
     }
     assert(msg->header.done == 1);
     return msg->header.ret_val;

Ubiquitous/XiZi_AIoT/services/lib/ipc/libipc.h

@@ -180,7 +180,7 @@ __attribute__((__always_inline__)) static inline bool ipc_session_forward(struct
 struct IpcMsg* new_ipc_msg(struct Session* session, const int argc, const int* arg_size);
 bool ipc_msg_set_nth_arg(struct IpcMsg* msg, const int arg_num, const void* const data, const int len);
 bool ipc_msg_get_nth_arg(struct IpcMsg* msg, const int arg_num, void* data, const int len);
-void ipc_msg_send_wait(struct IpcMsg* msg);
+void ipc_msg_send_wait(struct Session* session, struct IpcMsg* msg);
 void ipc_msg_send_nowait(struct IpcMsg* msg);
 int ipc_session_wait(struct Session* session);
 
@@ -230,7 +230,7 @@ void ipc_server_loop(struct IpcNode* ipc_node);
         struct IpcMsg* msg = IPC_CREATE_MSG_FUNC(ipc_name)(session, _VA_FRONT_ARG##argc(__VA_ARGS__));                                         \
         int ret = IPC_MSG_ARGS_COPY_SET_FUNC(ipc_name)(msg, _VA_FRONT_ARG##argc(__VA_ARGS__));                                                 \
         ret = ipc_msg_set_opcode(msg, ipc_name);                                                                                               \
-        ipc_msg_send_wait(msg);                                                                                                                \
+        ipc_msg_send_wait(session, msg);                                                                                                       \
         ret = IPC_MSG_ARGS_COPY_GET_FUNC(ipc_name)(msg, _VA_FRONT_ARG##argc(__VA_ARGS__));                                                     \
         int32_t res = 0;                                                                                                                       \
         ipc_msg_get_return(msg, &res);                                                                                                         \
@@ -278,9 +278,10 @@ uintptr_t _ipc_buf_to_addr(char* buf);
         char addr_buf[17];                                                  \
         _ipc_addr_to_buf((uintptr_t)msg, addr_buf);                         \
         char* param[] = { #ipc_name, addr_buf, NULL };                      \
+        msg->header.handling = 1;                                           \
         int tid = thread(IPC_THREAD_SERVE(ipc_name), #ipc_name, param);     \
-        if (tid > 0) {                                                      \
+        if (tid <= 0) {                                                     \
-            msg->header.handling = 1;                                       \
+            msg->header.handling = 0;                                       \
         }                                                                   \
         return 0;                                                           \
     }

Ubiquitous/XiZi_AIoT/services/lib/ipc/session.h

@@ -36,7 +36,7 @@ Modification:
 #include "libserial.h"
 
 struct Session {
-    int id;
+    uintptr_t id;
     int capacity;
     int head;
     int tail;

Ubiquitous/XiZi_AIoT/services/lib/usyscall/usyscall.c

@@ -12,6 +12,11 @@
 #include "usyscall.h"
 #include "libmem.h"
 
+uintptr_t sys_test()
+{
+    return syscall(SYSCALL_TEST, 0, 0, 0, 0);
+}
+
 int spawn(struct Session* session, int fd, ipc_read_fn ipc_read, ipc_fsize_fn ipc_fsize, char* name, char** argv)
 {
     /* read elf image */
@@ -72,6 +77,11 @@ int close_session(struct Session* session)
     return syscall(SYSCALL_CLOSE_SESSION, (intptr_t)session, 0, 0, 0);
 }
 
+int wait_session_call(struct Session* userland_session)
+{
+    return syscall(SYSCALL_WAIT_SESSION, (intptr_t)userland_session, 0, 0, 0);
+}
+
 int get_memblock_info(sys_state_info* info)
 {
     return syscall(SYSCALL_SYS_STATE, SYS_STATE_MEMBLOCK_INFO, (intptr_t)info, 0, 0);
@@ -102,6 +112,11 @@ int show_cpu()
     return syscall(SYSCALL_SYS_STATE, SYS_STATE_SHOW_CPU_INFO, 0, 0, 0);
 }
 
+int show_actree()
+{
+    return syscall(SYSCALL_SYS_STATE, SYS_STATE_SHOW_ACTREE, 0, 0, 0);
+}
+
 uintptr_t get_second()
 {
     sys_state_info info;
@@ -118,8 +133,12 @@ uintptr_t get_tick()
 
 uintptr_t mmap(uintptr_t vaddr, uintptr_t paddr, int len, bool is_dev)
 {
+    sys_mmap_info info = {
+        .type = SYS_MMAP_NORMAL,
+        .is_dev = is_dev,
+    };
     uintptr_t vaddr_inner = vaddr, paddr_inner = paddr;
-    if (syscall(SYSCALL_MMAP, (intptr_t)&vaddr_inner, (intptr_t)&paddr_inner, (intptr_t)len, (intptr_t)is_dev) < 0) {
+    if (syscall(SYSCALL_MMAP, (intptr_t)&vaddr_inner, (intptr_t)&paddr_inner, (intptr_t)len, (intptr_t)&info) < 0) {
         return (uintptr_t)NULL;
     }
     return vaddr_inner;
@@ -127,7 +146,20 @@ uintptr_t mmap(uintptr_t vaddr, uintptr_t paddr, int len, bool is_dev)
 
 int naive_mmap(uintptr_t* vaddr, uintptr_t* paddr, int len, bool is_dev)
 {
-    return syscall(SYSCALL_MMAP, (uintptr_t)vaddr, (intptr_t)paddr, (intptr_t)len, (intptr_t)is_dev);
+    sys_mmap_info info = {
+        .type = SYS_MMAP_NORMAL,
+        .is_dev = is_dev,
+    };
+    return syscall(SYSCALL_MMAP, (uintptr_t)vaddr, (intptr_t)paddr, (intptr_t)len, (intptr_t)&info);
+}
+
+int mmap_with_attr(uintptr_t vaddr, uintptr_t paddr, int len, uintptr_t attr)
+{
+    sys_mmap_info info = {
+        .type = SYS_MMAP_CUSTOMIZE,
+        .attr = attr,
+    };
+    return syscall(SYSCALL_MMAP, (intptr_t)vaddr, (intptr_t)paddr, (intptr_t)len, (intptr_t)&info);
 }
 
 int register_irq(int irq, int opcode)
@@ -153,4 +185,9 @@ bool semaphore_wait(int sem_id)
 bool semaphore_signal(int sem_id)
 {
     return syscall(SYSCALL_SEMAPHORE, (intptr_t)SYS_SEM_SIGNAL, (intptr_t)sem_id, 0, 0);
+}
+
+int sleep(intptr_t ms)
+{
+    return syscall(SYSCALL_SLEEP, (intptr_t)ms, 0, 0, 0);
 }

Ubiquitous/XiZi_AIoT/services/lib/usyscall/usyscall.h

@@ -34,6 +34,9 @@
 #define SYSCALL_KILL            12  // kill the task by id
 
 #define SYSCALL_SEMAPHORE       13  // semaphore related operations
+#define SYSCALL_SLEEP           14  // sleep
+
+#define SYSCALL_WAIT_SESSION    15
 // clang-format on
 
 typedef enum {
@@ -46,6 +49,7 @@ typedef enum {
     SYS_STATE_SHOW_CPU_INFO,
     SYS_STATE_GET_CURRENT_TICK,
     SYS_STATE_GET_CURRENT_SECOND,
+    SYS_STATE_SHOW_ACTREE,
 } sys_state_option;
 
 typedef enum {
@@ -54,6 +58,17 @@ typedef enum {
     SYS_TASK_YIELD_BLOCK_IPC = 0x2,
 } task_yield_reason;
 
+typedef enum {
+    SYS_MMAP_NORMAL = 0x0,
+    SYS_MMAP_CUSTOMIZE,
+} sys_mmap_type;
+
+typedef struct sys_mmap_info {
+    sys_mmap_type type;
+    uintptr_t attr;
+    bool is_dev;
+} sys_mmap_info;
+
 typedef union {
     struct {
         uintptr_t memblock_start;
@@ -76,6 +91,9 @@ typedef int (*ipc_fsize_fn)(struct Session* session, int fd);
 typedef int (*ipc_write_fn)(struct Session* session, int fd, char* src, int offset, int len);
 
 int syscall(int sys_num, intptr_t a1, intptr_t a2, intptr_t a3, intptr_t a4);
+uintptr_t syscall_ori(int sys_num, intptr_t a1, intptr_t a2, intptr_t a3, intptr_t a4);
+
+uintptr_t sys_test();
 
 int spawn(struct Session* session, int fd, ipc_read_fn ipc_read, ipc_fsize_fn ipc_fsize, char* name, char** argv);
 int thread(void* entry, const char* name, char** argv);
@@ -85,12 +103,14 @@ int kill(int pid);
 
 int register_server(char* name);
 int session(char* path, int capacity, struct Session* user_session);
-int poll_session(struct Session* userland_session_arr, int arr_capacity);
+int poll_session(struct Session* userland_session, int arr_capacity);
+int wait_session_call(struct Session* userland_session);
 int close_session(struct Session* session);
 int register_irq(int irq, int opcode);
 
 uintptr_t mmap(uintptr_t vaddr, uintptr_t paddr, int len, bool is_dev);
 int naive_mmap(uintptr_t* vaddr, uintptr_t* paddr, int len, bool is_dev);
+int customized_mmap(uintptr_t vaddr, uintptr_t paddr, int len, uintptr_t attr);
 
 int task_heap_base();
 int get_memblock_info(sys_state_info* info);
@@ -98,6 +118,7 @@ int set_priority(sys_state_info* info);
 int show_task();
 int show_mem();
 int show_cpu();
+int show_actree();
 
 uintptr_t get_second();
 uintptr_t get_tick();
@@ -105,4 +126,6 @@ uintptr_t get_tick();
 int semaphore_new(int val);
 bool semaphore_free(int sem_id);
 bool semaphore_wait(int sem_id);
-bool semaphore_signal(int sem_id);
+bool semaphore_signal(int sem_id);
+
+int sleep(intptr_t ms);

Ubiquitous/XiZi_AIoT/services/semaphore/semaphore_server.c

@@ -41,15 +41,28 @@ int IPC_DO_SERVE_FUNC(Ipc_sem_create)(sem_t* sem, int* count)
     return SEMAPHORE_SUC;
 }
 
+
+#define CHECK_SEM_RANGE(sem) \
+    do { \
+        if (*sem < 0 || *sem >= MAX_SUPPORT_SEMAPHORES) { \
+            return SEMAPHORE_ERR; \
+        } \
+    } while (0)
+
+
+#define CHECK_SEM_RANGE_AND_VALID(sem) \
+    do { \
+        CHECK_SEM_RANGE(sem); \
+        \
+        if (!sem_pool[*sem].valid) { \
+            return SEMAPHORE_ERR; \
+        } \
+    } while (0)
+
+
 int IPC_DO_SERVE_FUNC(Ipc_sem_delete)(sem_t* sem)
 {
-    if (*sem < 0 || *sem > MAX_SUPPORT_SEMAPHORES) {
+    CHECK_SEM_RANGE_AND_VALID(sem);
-        return SEMAPHORE_ERR;
-    }
-
-    if (!sem_pool[*sem].valid) {
-        return SEMAPHORE_ERR;
-    }
 
     sem_pool[*sem].valid = false;
     return SEMAPHORE_SUC;
@@ -57,9 +70,7 @@ int IPC_DO_SERVE_FUNC(Ipc_sem_delete)(sem_t* sem)
 
 int IPC_DO_SERVE_FUNC(Ipc_sem_wait)(sem_t* sem, int* timeout)
 {
-    if (*sem < 0 || *sem > MAX_SUPPORT_SEMAPHORES) {
+    CHECK_SEM_RANGE(sem);
-        return SEMAPHORE_ERR;
-    }
 
     /// @todo support timeout
     // return if sem is freed(no valid) or sem count is sufficient
@@ -72,13 +83,7 @@ int IPC_DO_SERVE_FUNC(Ipc_sem_wait)(sem_t* sem, int* timeout)
 
 int IPC_DO_SERVE_FUNC(Ipc_sem_signal)(sem_t* sem)
 {
-    if (*sem < 0 || *sem >= MAX_SUPPORT_SEMAPHORES) {
+    CHECK_SEM_RANGE_AND_VALID(sem);
-        return SEMAPHORE_ERR;
-    }
-
-    if (!sem_pool[*sem].valid) {
-        return SEMAPHORE_ERR;
-    }
 
     sem_pool[*sem].count++;
     return SEMAPHORE_SUC;

Ubiquitous/XiZi_AIoT/services/shell/letter-shell/shell.c

@@ -1797,6 +1797,11 @@ void shellShowCpusInfo()
     show_cpu();
 }
 
+void shellShowActree()
+{
+    show_actree();
+}
+
 #if SHELL_EXEC_UNDEF_FUNC == 1
 /**
  * @brief shell执行未定义函数

Ubiquitous/XiZi_AIoT/services/shell/letter-shell/shell_cmd_list.c

@@ -40,6 +40,7 @@ extern void shellKill(int pid);
 extern void shellShowTasks();
 extern void shellShowMemInfo();
 extern void shellShowCpusInfo();
+extern void shellShowActree();
 
 #if SHELL_EXEC_UNDEF_FUNC == 1
 extern int shellExecute(int argc, char* argv[]);
@@ -118,6 +119,8 @@ const ShellCommand shellCommandList[] = {
         showMemInfo, shellShowMemInfo, display memory info),
     SHELL_CMD_ITEM(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC) | SHELL_CMD_DISABLE_RETURN,
         showCpusInfo, shellShowCpusInfo, display cpus info),
+    SHELL_CMD_ITEM(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC) | SHELL_CMD_DISABLE_RETURN,
+        showActree, shellShowActree, display actracer tree),
 
 #if SHELL_EXEC_UNDEF_FUNC == 1
     SHELL_CMD_ITEM(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_DISABLE_RETURN,