transplant development board of gd32vf103_rvstar
This commit is contained in:
Wang_Weigen
@@ -20,4 +20,8 @@ ifeq ($(CONFIG_BOARD_GAPUINO),y)
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SRC_DIR +=gap8
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endif
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ifeq ($(CONFIG_BOARD_GD32VF103RVSTAR),y)
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SRC_DIR +=gd32vf103_rvstar
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endif
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include $(KERNEL_ROOT)/compiler.mk
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@@ -0,0 +1,3 @@
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SRC_FILES := boot.S intexc_gd32vf103.S interrupt.c tick.c
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include $(KERNEL_ROOT)/compiler.mk
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@@ -0,0 +1,12 @@
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#ifndef ARCH_INTERRUPT_H__
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#define ARCH_INTERRUPT_H__
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#include <nuclei_sdk_soc.h>
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#define ARCH_MAX_IRQ_NUM 128
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#define ARCH_IRQ_NUM_OFFSET 0
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int ArchEnableHwIrq(uint32_t irq_num);
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int ArchDisableHwIrq(uint32_t irq_num);
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#endif
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+486
@@ -0,0 +1,486 @@
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/*
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* Copyright (c) 2019 Nuclei Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/******************************************************************************
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* \file startup_gd32vf103.S
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* \brief NMSIS Nuclei N/NX Class Core based Core Device Startup File for
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* Device gd32vf103
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* \version V1.00
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* \date 21 Nov 2019
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*
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*
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******************************************************************************/
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#include "boot.h"
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#include "riscv_encoding.h"
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#ifndef __riscv_32e
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#define portRegNum 30
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#else
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#define portRegNum 14
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#endif
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#define portCONTEXT_SIZE ( portRegNum * REGBYTES )
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# .align 2
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# .global eclic_msip_handler
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# eclic_msip_handler:
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# addi sp, sp, -portCONTEXT_SIZE
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# STORE x1, 1 * REGBYTES(sp) /* RA */
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# STORE x5, 2 * REGBYTES(sp)
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# STORE x6, 3 * REGBYTES(sp)
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# STORE x7, 4 * REGBYTES(sp)
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# STORE x8, 5 * REGBYTES(sp)
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# STORE x9, 6 * REGBYTES(sp)
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# STORE x10, 7 * REGBYTES(sp)
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# STORE x11, 8 * REGBYTES(sp)
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# STORE x12, 9 * REGBYTES(sp)
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# STORE x13, 10 * REGBYTES(sp)
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# STORE x14, 11 * REGBYTES(sp)
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# STORE x15, 12 * REGBYTES(sp)
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# #ifndef __riscv_32e
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# STORE x16, 13 * REGBYTES(sp)
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# STORE x17, 14 * REGBYTES(sp)
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# STORE x18, 15 * REGBYTES(sp)
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# STORE x19, 16 * REGBYTES(sp)
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# STORE x20, 17 * REGBYTES(sp)
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# STORE x21, 18 * REGBYTES(sp)
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# STORE x22, 19 * REGBYTES(sp)
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# STORE x23, 20 * REGBYTES(sp)
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# STORE x24, 21 * REGBYTES(sp)
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# STORE x25, 22 * REGBYTES(sp)
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# STORE x26, 23 * REGBYTES(sp)
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# STORE x27, 24 * REGBYTES(sp)
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# STORE x28, 25 * REGBYTES(sp)
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# STORE x29, 26 * REGBYTES(sp)
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# STORE x30, 27 * REGBYTES(sp)
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# STORE x31, 28 * REGBYTES(sp)
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# #endif
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# /* Push mstatus to stack */
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# csrr t0, CSR_MSTATUS
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# STORE t0, (portRegNum - 1) * REGBYTES(sp)
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# /* Push additional registers */
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# /* Store sp to task stack */
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# LOAD t0, rt_interrupt_from_thread
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# STORE sp, 0(t0)
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# csrr t0, CSR_MEPC
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# STORE t0, 0(sp)
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# jal xPortTaskSwitch
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# /* Switch task context */
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# LOAD t0, rt_interrupt_to_thread
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# LOAD sp, 0x0(t0)
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# /* Pop PC from stack and set MEPC */
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# LOAD t0, 0 * REGBYTES(sp)
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# csrw CSR_MEPC, t0
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# /* Pop additional registers */
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# /* Pop mstatus from stack and set it */
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# LOAD t0, (portRegNum - 1) * REGBYTES(sp)
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# csrw CSR_MSTATUS, t0
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# /* Interrupt still disable here */
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# /* Restore Registers from Stack */
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# LOAD x1, 1 * REGBYTES(sp) /* RA */
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# LOAD x5, 2 * REGBYTES(sp)
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# LOAD x6, 3 * REGBYTES(sp)
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# LOAD x7, 4 * REGBYTES(sp)
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# LOAD x8, 5 * REGBYTES(sp)
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# LOAD x9, 6 * REGBYTES(sp)
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# LOAD x10, 7 * REGBYTES(sp)
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# LOAD x11, 8 * REGBYTES(sp)
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# LOAD x12, 9 * REGBYTES(sp)
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# LOAD x13, 10 * REGBYTES(sp)
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# LOAD x14, 11 * REGBYTES(sp)
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# LOAD x15, 12 * REGBYTES(sp)
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# #ifndef __riscv_32e
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# LOAD x16, 13 * REGBYTES(sp)
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# LOAD x17, 14 * REGBYTES(sp)
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# LOAD x18, 15 * REGBYTES(sp)
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# LOAD x19, 16 * REGBYTES(sp)
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# LOAD x20, 17 * REGBYTES(sp)
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# LOAD x21, 18 * REGBYTES(sp)
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# LOAD x22, 19 * REGBYTES(sp)
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# LOAD x23, 20 * REGBYTES(sp)
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# LOAD x24, 21 * REGBYTES(sp)
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# LOAD x25, 22 * REGBYTES(sp)
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# LOAD x26, 23 * REGBYTES(sp)
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# LOAD x27, 24 * REGBYTES(sp)
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# LOAD x28, 25 * REGBYTES(sp)
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# LOAD x29, 26 * REGBYTES(sp)
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# LOAD x30, 27 * REGBYTES(sp)
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# LOAD x31, 28 * REGBYTES(sp)
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# #endif
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# addi sp, sp, portCONTEXT_SIZE
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# mret
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.extern xPortTaskSwitch
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.align 2
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.global eclic_msip_handler
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eclic_msip_handler:
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SAVE_X_REGISTERS
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jal xPortTaskSwitch
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call KTaskOsAssignAfterIrq
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j SwitchKTaskContextExit
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.macro DECLARE_INT_HANDLER INT_HDL_NAME
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#if defined(__riscv_xlen) && (__riscv_xlen == 32)
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.word \INT_HDL_NAME
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#else
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.dword \INT_HDL_NAME
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#endif
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.endm
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/*
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* Put the interrupt vectors in this section according to vector remapped or not:
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* .vtable: vector table's LMA and VMA are the same, it is not remapped
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* .vtable_ilm: vector table's LMA and VMA are different, it is remapped, and
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* VECTOR_TABLE_REMAPPED need to be defined
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*/
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#if defined(VECTOR_TABLE_REMAPPED)
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.section .vtable_ilm
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#else
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.section .vtable
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#endif
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.weak eclic_msip_handler
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.weak eclic_mtip_handler
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.weak eclic_bwei_handler
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.weak eclic_pmovi_handler
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.weak WWDGT_IRQHandler
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.weak LVD_IRQHandler
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.weak TAMPER_IRQHandler
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.weak RTC_IRQHandler
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.weak FMC_IRQHandler
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.weak RCU_IRQHandler
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.weak EXTI0_IRQHandler
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.weak EXTI1_IRQHandler
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.weak EXTI2_IRQHandler
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.weak EXTI3_IRQHandler
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.weak EXTI4_IRQHandler
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.weak DMA0_Channel0_IRQHandler
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.weak DMA0_Channel1_IRQHandler
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.weak DMA0_Channel2_IRQHandler
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.weak DMA0_Channel3_IRQHandler
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.weak DMA0_Channel4_IRQHandler
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.weak DMA0_Channel5_IRQHandler
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.weak DMA0_Channel6_IRQHandler
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.weak ADC0_1_IRQHandler
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.weak CAN0_TX_IRQHandler
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.weak CAN0_RX0_IRQHandler
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.weak CAN0_RX1_IRQHandler
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.weak CAN0_EWMC_IRQHandler
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.weak EXTI5_9_IRQHandler
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.weak TIMER0_BRK_IRQHandler
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.weak TIMER0_UP_IRQHandler
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.weak TIMER0_TRG_CMT_IRQHandler
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.weak TIMER0_Channel_IRQHandler
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.weak TIMER1_IRQHandler
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.weak TIMER2_IRQHandler
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.weak TIMER3_IRQHandler
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.weak I2C0_EV_IRQHandler
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.weak I2C0_ER_IRQHandler
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.weak I2C1_EV_IRQHandler
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.weak I2C1_ER_IRQHandler
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.weak SPI0_IRQHandler
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.weak SPI1_IRQHandler
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.weak USART0_IRQHandler
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.weak USART1_IRQHandler
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.weak USART2_IRQHandler
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.weak EXTI10_15_IRQHandler
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.weak RTC_Alarm_IRQHandler
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.weak USBFS_WKUP_IRQHandler
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.weak EXMC_IRQHandler
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.weak TIMER4_IRQHandler
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.weak SPI2_IRQHandler
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.weak UART3_IRQHandler
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.weak UART4_IRQHandler
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.weak TIMER5_IRQHandler
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.weak TIMER6_IRQHandler
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.weak DMA1_Channel0_IRQHandler
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.weak DMA1_Channel1_IRQHandler
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.weak DMA1_Channel2_IRQHandler
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.weak DMA1_Channel3_IRQHandler
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.weak DMA1_Channel4_IRQHandler
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.weak CAN1_TX_IRQHandler
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.weak CAN1_RX0_IRQHandler
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.weak CAN1_RX1_IRQHandler
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.weak CAN1_EWMC_IRQHandler
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.weak USBFS_IRQHandler
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.globl vector_base
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.type vector_base, @object
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vector_base:
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#ifndef VECTOR_TABLE_REMAPPED
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j _start /* 0: Reserved, Jump to _start when reset for vector table not remapped cases.*/
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.align LOG_REGBYTES /* Need to align 4 byte for RV32, 8 Byte for RV64 */
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#else
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DECLARE_INT_HANDLER default_intexc_handler /* 0: Reserved, default handler for vector table remapped cases */
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#endif
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DECLARE_INT_HANDLER default_intexc_handler /* 1: Reserved */
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DECLARE_INT_HANDLER default_intexc_handler /* 2: Reserved */
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DECLARE_INT_HANDLER eclic_msip_handler /* 3: Machine software interrupt */
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DECLARE_INT_HANDLER default_intexc_handler /* 4: Reserved */
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DECLARE_INT_HANDLER default_intexc_handler /* 5: Reserved */
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DECLARE_INT_HANDLER default_intexc_handler /* 6: Reserved */
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DECLARE_INT_HANDLER eclic_mtip_handler /* 7: Machine timer interrupt */
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DECLARE_INT_HANDLER default_intexc_handler /* 8: Reserved */
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DECLARE_INT_HANDLER default_intexc_handler /* 9: Reserved */
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DECLARE_INT_HANDLER default_intexc_handler /* 10: Reserved */
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DECLARE_INT_HANDLER default_intexc_handler /* 11: Reserved */
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DECLARE_INT_HANDLER default_intexc_handler /* 12: Reserved */
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DECLARE_INT_HANDLER default_intexc_handler /* 13: Reserved */
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DECLARE_INT_HANDLER default_intexc_handler /* 14: Reserved */
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DECLARE_INT_HANDLER default_intexc_handler /* 15: Reserved */
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DECLARE_INT_HANDLER default_intexc_handler /* 16: Reserved */
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DECLARE_INT_HANDLER eclic_bwei_handler /* 17: Bus Error interrupt */
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DECLARE_INT_HANDLER eclic_pmovi_handler /* 18: Performance Monitor */
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DECLARE_INT_HANDLER WWDGT_IRQHandler
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DECLARE_INT_HANDLER LVD_IRQHandler
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DECLARE_INT_HANDLER TAMPER_IRQHandler
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DECLARE_INT_HANDLER RTC_IRQHandler
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DECLARE_INT_HANDLER FMC_IRQHandler
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DECLARE_INT_HANDLER RCU_IRQHandler
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DECLARE_INT_HANDLER EXTI0_IRQHandler
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DECLARE_INT_HANDLER EXTI1_IRQHandler
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DECLARE_INT_HANDLER EXTI2_IRQHandler
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DECLARE_INT_HANDLER EXTI3_IRQHandler
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DECLARE_INT_HANDLER EXTI4_IRQHandler
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DECLARE_INT_HANDLER DMA0_Channel0_IRQHandler
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DECLARE_INT_HANDLER DMA0_Channel1_IRQHandler
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DECLARE_INT_HANDLER DMA0_Channel2_IRQHandler
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DECLARE_INT_HANDLER DMA0_Channel3_IRQHandler
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DECLARE_INT_HANDLER DMA0_Channel4_IRQHandler
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DECLARE_INT_HANDLER DMA0_Channel5_IRQHandler
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DECLARE_INT_HANDLER DMA0_Channel6_IRQHandler
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DECLARE_INT_HANDLER ADC0_1_IRQHandler
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DECLARE_INT_HANDLER CAN0_TX_IRQHandler
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DECLARE_INT_HANDLER CAN0_RX0_IRQHandler
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DECLARE_INT_HANDLER CAN0_RX1_IRQHandler
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DECLARE_INT_HANDLER CAN0_EWMC_IRQHandler
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DECLARE_INT_HANDLER EXTI5_9_IRQHandler
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DECLARE_INT_HANDLER TIMER0_BRK_IRQHandler
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DECLARE_INT_HANDLER TIMER0_UP_IRQHandler
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DECLARE_INT_HANDLER TIMER0_TRG_CMT_IRQHandler
|
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DECLARE_INT_HANDLER TIMER0_Channel_IRQHandler
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||||
DECLARE_INT_HANDLER TIMER1_IRQHandler
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DECLARE_INT_HANDLER TIMER2_IRQHandler
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DECLARE_INT_HANDLER TIMER3_IRQHandler
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DECLARE_INT_HANDLER I2C0_EV_IRQHandler
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||||
DECLARE_INT_HANDLER I2C0_ER_IRQHandler
|
||||
DECLARE_INT_HANDLER I2C1_EV_IRQHandler
|
||||
DECLARE_INT_HANDLER I2C1_ER_IRQHandler
|
||||
DECLARE_INT_HANDLER SPI0_IRQHandler
|
||||
DECLARE_INT_HANDLER SPI1_IRQHandler
|
||||
DECLARE_INT_HANDLER USART0_IRQHandler
|
||||
DECLARE_INT_HANDLER USART1_IRQHandler
|
||||
DECLARE_INT_HANDLER USART2_IRQHandler
|
||||
DECLARE_INT_HANDLER EXTI10_15_IRQHandler
|
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DECLARE_INT_HANDLER RTC_Alarm_IRQHandler
|
||||
DECLARE_INT_HANDLER USBFS_WKUP_IRQHandler
|
||||
DECLARE_INT_HANDLER default_intexc_handler
|
||||
DECLARE_INT_HANDLER default_intexc_handler
|
||||
DECLARE_INT_HANDLER default_intexc_handler
|
||||
DECLARE_INT_HANDLER default_intexc_handler
|
||||
DECLARE_INT_HANDLER default_intexc_handler
|
||||
DECLARE_INT_HANDLER EXMC_IRQHandler
|
||||
DECLARE_INT_HANDLER default_intexc_handler
|
||||
DECLARE_INT_HANDLER TIMER4_IRQHandler
|
||||
DECLARE_INT_HANDLER SPI2_IRQHandler
|
||||
DECLARE_INT_HANDLER UART3_IRQHandler
|
||||
DECLARE_INT_HANDLER UART4_IRQHandler
|
||||
DECLARE_INT_HANDLER TIMER5_IRQHandler
|
||||
DECLARE_INT_HANDLER TIMER6_IRQHandler
|
||||
DECLARE_INT_HANDLER DMA1_Channel0_IRQHandler
|
||||
DECLARE_INT_HANDLER DMA1_Channel1_IRQHandler
|
||||
DECLARE_INT_HANDLER DMA1_Channel2_IRQHandler
|
||||
DECLARE_INT_HANDLER DMA1_Channel3_IRQHandler
|
||||
DECLARE_INT_HANDLER DMA1_Channel4_IRQHandler
|
||||
DECLARE_INT_HANDLER default_intexc_handler
|
||||
DECLARE_INT_HANDLER default_intexc_handler
|
||||
DECLARE_INT_HANDLER CAN1_TX_IRQHandler
|
||||
DECLARE_INT_HANDLER CAN1_RX0_IRQHandler
|
||||
DECLARE_INT_HANDLER CAN1_RX1_IRQHandler
|
||||
DECLARE_INT_HANDLER CAN1_EWMC_IRQHandler
|
||||
DECLARE_INT_HANDLER USBFS_IRQHandler
|
||||
|
||||
.extern Gd32vf103Start
|
||||
.extern SystemInit
|
||||
.extern _premain_init
|
||||
|
||||
|
||||
.section .init
|
||||
|
||||
.globl _start
|
||||
.type _start, @function
|
||||
|
||||
/**
|
||||
* Reset Handler called on controller reset
|
||||
*/
|
||||
_start:
|
||||
/* ===== Startup Stage 1 ===== */
|
||||
/* Disable Global Interrupt */
|
||||
csrc CSR_MSTATUS, MSTATUS_MIE
|
||||
/* Jump to logical address first to ensure correct operation of RAM region */
|
||||
la a0, _start
|
||||
li a1, 1
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||||
slli a1, a1, 29
|
||||
bleu a1, a0, _start0800
|
||||
srli a1, a1, 2
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||||
bleu a1, a0, _start0800
|
||||
la a0, _start0800
|
||||
add a0, a0, a1
|
||||
jr a0
|
||||
|
||||
_start0800:
|
||||
/* Initialize GP and Stack Pointer SP */
|
||||
.option push
|
||||
.option norelax
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||||
la gp, __global_pointer$
|
||||
|
||||
.option pop
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||||
la sp, _sp
|
||||
|
||||
/*
|
||||
* Set the the NMI base mnvec to share
|
||||
* with mtvec by setting CSR_MMISC_CTL
|
||||
* bit 9 NMI_CAUSE_FFF to 1
|
||||
*/
|
||||
li t0, MMISC_CTL_NMI_CAUSE_FFF
|
||||
csrs CSR_MMISC_CTL, t0
|
||||
|
||||
/*
|
||||
* Intialize ECLIC vector interrupt
|
||||
* base address mtvt to vector_base
|
||||
*/
|
||||
la t0, vector_base
|
||||
csrw CSR_MTVT, t0
|
||||
|
||||
/*
|
||||
* Set ECLIC non-vector entry to be controlled
|
||||
* by mtvt2 CSR register.
|
||||
* Intialize ECLIC non-vector interrupt
|
||||
* base address mtvt2 to irq_entry.
|
||||
*/
|
||||
la t0, irq_entry
|
||||
csrw CSR_MTVT2, t0
|
||||
csrs CSR_MTVT2, 0x1
|
||||
|
||||
/*
|
||||
* Set Exception Entry MTVEC to exc_entry
|
||||
* Due to settings above, Exception and NMI
|
||||
* will share common entry.
|
||||
*/
|
||||
la t0, exc_entry
|
||||
csrw CSR_MTVEC, t0
|
||||
|
||||
/* Set the interrupt processing mode to ECLIC mode */
|
||||
li t0, 0x3f
|
||||
csrc CSR_MTVEC, t0
|
||||
csrs CSR_MTVEC, 0x3
|
||||
|
||||
/* ===== Startup Stage 2 ===== */
|
||||
|
||||
#if defined(__riscv_flen) && __riscv_flen > 0
|
||||
/* Enable FPU */
|
||||
li t0, MSTATUS_FS
|
||||
csrs mstatus, t0
|
||||
csrw fcsr, x0
|
||||
#endif
|
||||
|
||||
/* Enable mcycle and minstret counter */
|
||||
csrci CSR_MCOUNTINHIBIT, 0x5
|
||||
|
||||
/* ===== Startup Stage 3 ===== */
|
||||
/*
|
||||
* Load code section from FLASH to ILM
|
||||
* when code LMA is different with VMA
|
||||
*/
|
||||
la a0, _ilm_lma
|
||||
la a1, _ilm
|
||||
/* If the ILM phy-address same as the logic-address, then quit */
|
||||
beq a0, a1, 2f
|
||||
la a2, _eilm
|
||||
bgeu a1, a2, 2f
|
||||
|
||||
1:
|
||||
/* Load code section if necessary */
|
||||
lw t0, (a0)
|
||||
sw t0, (a1)
|
||||
addi a0, a0, 4
|
||||
addi a1, a1, 4
|
||||
bltu a1, a2, 1b
|
||||
2:
|
||||
/* Load data section */
|
||||
la a0, _data_lma
|
||||
la a1, _data
|
||||
la a2, _edata
|
||||
bgeu a1, a2, 2f
|
||||
1:
|
||||
lw t0, (a0)
|
||||
sw t0, (a1)
|
||||
addi a0, a0, 4
|
||||
addi a1, a1, 4
|
||||
bltu a1, a2, 1b
|
||||
2:
|
||||
/* Clear bss section */
|
||||
la a0, __bss_start
|
||||
la a1, _end
|
||||
bgeu a0, a1, 2f
|
||||
1:
|
||||
sw zero, (a0)
|
||||
addi a0, a0, 4
|
||||
bltu a0, a1, 1b
|
||||
2:
|
||||
/*
|
||||
* Call vendor defined SystemInit to
|
||||
* initialize the micro-controller system
|
||||
*/
|
||||
call SystemInit
|
||||
|
||||
/* Call global constructors */
|
||||
la a0, __libc_fini_array
|
||||
call atexit
|
||||
/* Call C/C++ constructor start up code */
|
||||
call __libc_init_array
|
||||
|
||||
/* do pre-init steps before main */
|
||||
call _premain_init
|
||||
|
||||
/* ===== Call entry Function ===== */
|
||||
/* argc = argv = 0 */
|
||||
li a0, 0
|
||||
li a1, 0
|
||||
|
||||
j Gd32vf103Start
|
||||
|
||||
1:
|
||||
j 1b
|
||||
@@ -0,0 +1,61 @@
|
||||
/**
|
||||
* @file interrupt.c
|
||||
* @brief support gap8 interrupt enable and disable
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-09-02
|
||||
*/
|
||||
|
||||
|
||||
#include <arch_interrupt.h>
|
||||
#include <xs_base.h>
|
||||
#include <xs_isr.h>
|
||||
#include <core_feature_base.h>
|
||||
|
||||
int ArchDisableHwIrq(uint32_t irq_num)
|
||||
{
|
||||
ECLIC_DisableIRQ(irq_num);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ArchEnableHwIrq(uint32_t irq_num)
|
||||
{
|
||||
ECLIC_EnableIRQ(irq_num);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
x_base DisableLocalInterrupt(void)
|
||||
{
|
||||
return __RV_CSR_READ_CLEAR(CSR_MSTATUS, MSTATUS_MIE);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: EnableLocalInterrupt
|
||||
*
|
||||
* Description:
|
||||
* Return the current interrupt state and enable interrupts
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void EnableLocalInterrupt(x_base oldstat)
|
||||
{
|
||||
__RV_CSR_WRITE(CSR_MSTATUS, oldstat);
|
||||
}
|
||||
|
||||
|
||||
// extern void KTaskOsAssignAfterIrq(void *context);
|
||||
|
||||
// void IsrEntry()
|
||||
// {
|
||||
// uint32 ipsr;
|
||||
|
||||
// isrManager.done->incCounter();
|
||||
// isrManager.done->handleIrq(ipsr);
|
||||
// KTaskOsAssignAfterIrq(NONE);
|
||||
// isrManager.done->decCounter();
|
||||
|
||||
// }
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,232 @@
|
||||
/*
|
||||
* Copyright (c) 2019 Nuclei Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/******************************************************************************
|
||||
* \file intexc_gd32vf103.S
|
||||
* \brief NMSIS Interrupt and Exception Handling Template File
|
||||
* for Device gd32vf103
|
||||
* \version V1.00
|
||||
* \date 7 Jan 2020
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "riscv_encoding.h"
|
||||
|
||||
/**
|
||||
* \brief Global interrupt disabled
|
||||
* \details
|
||||
* This function disable global interrupt.
|
||||
* \remarks
|
||||
* - All the interrupt requests will be ignored by CPU.
|
||||
*/
|
||||
.macro DISABLE_MIE
|
||||
csrc CSR_MSTATUS, MSTATUS_MIE
|
||||
.endm
|
||||
|
||||
/**
|
||||
* \brief Macro for context save
|
||||
* \details
|
||||
* This macro save ABI defined caller saved registers in the stack.
|
||||
* \remarks
|
||||
* - This Macro could use to save context when you enter to interrupt
|
||||
* or exception
|
||||
*/
|
||||
/* Save caller registers */
|
||||
.macro SAVE_CONTEXT
|
||||
/* Allocate stack space for context saving */
|
||||
#ifndef __riscv_32e
|
||||
addi sp, sp, -20*REGBYTES
|
||||
#else
|
||||
addi sp, sp, -14*REGBYTES
|
||||
#endif /* __riscv_32e */
|
||||
|
||||
STORE x1, 0*REGBYTES(sp)
|
||||
STORE x4, 1*REGBYTES(sp)
|
||||
STORE x5, 2*REGBYTES(sp)
|
||||
STORE x6, 3*REGBYTES(sp)
|
||||
STORE x7, 4*REGBYTES(sp)
|
||||
STORE x10, 5*REGBYTES(sp)
|
||||
STORE x11, 6*REGBYTES(sp)
|
||||
STORE x12, 7*REGBYTES(sp)
|
||||
STORE x13, 8*REGBYTES(sp)
|
||||
STORE x14, 9*REGBYTES(sp)
|
||||
STORE x15, 10*REGBYTES(sp)
|
||||
#ifndef __riscv_32e
|
||||
STORE x16, 14*REGBYTES(sp)
|
||||
STORE x17, 15*REGBYTES(sp)
|
||||
STORE x28, 16*REGBYTES(sp)
|
||||
STORE x29, 17*REGBYTES(sp)
|
||||
STORE x30, 18*REGBYTES(sp)
|
||||
STORE x31, 19*REGBYTES(sp)
|
||||
#endif /* __riscv_32e */
|
||||
.endm
|
||||
|
||||
/**
|
||||
* \brief Macro for restore caller registers
|
||||
* \details
|
||||
* This macro restore ABI defined caller saved registers from stack.
|
||||
* \remarks
|
||||
* - You could use this macro to restore context before you want return
|
||||
* from interrupt or exeception
|
||||
*/
|
||||
/* Restore caller registers */
|
||||
.macro RESTORE_CONTEXT
|
||||
LOAD x1, 0*REGBYTES(sp)
|
||||
LOAD x4, 1*REGBYTES(sp)
|
||||
LOAD x5, 2*REGBYTES(sp)
|
||||
LOAD x6, 3*REGBYTES(sp)
|
||||
LOAD x7, 4*REGBYTES(sp)
|
||||
LOAD x10, 5*REGBYTES(sp)
|
||||
LOAD x11, 6*REGBYTES(sp)
|
||||
LOAD x12, 7*REGBYTES(sp)
|
||||
LOAD x13, 8*REGBYTES(sp)
|
||||
LOAD x14, 9*REGBYTES(sp)
|
||||
LOAD x15, 10*REGBYTES(sp)
|
||||
#ifndef __riscv_32e
|
||||
LOAD x16, 14*REGBYTES(sp)
|
||||
LOAD x17, 15*REGBYTES(sp)
|
||||
LOAD x28, 16*REGBYTES(sp)
|
||||
LOAD x29, 17*REGBYTES(sp)
|
||||
LOAD x30, 18*REGBYTES(sp)
|
||||
LOAD x31, 19*REGBYTES(sp)
|
||||
|
||||
/* De-allocate the stack space */
|
||||
addi sp, sp, 20*REGBYTES
|
||||
#else
|
||||
/* De-allocate the stack space */
|
||||
addi sp, sp, 14*REGBYTES
|
||||
#endif /* __riscv_32e */
|
||||
|
||||
.endm
|
||||
|
||||
/**
|
||||
* \brief Macro for save necessary CSRs to stack
|
||||
* \details
|
||||
* This macro store MCAUSE, MEPC, MSUBM to stack.
|
||||
*/
|
||||
.macro SAVE_CSR_CONTEXT
|
||||
/* Store CSR mcause to stack using pushmcause */
|
||||
csrrwi x0, CSR_PUSHMCAUSE, 11
|
||||
/* Store CSR mepc to stack using pushmepc */
|
||||
csrrwi x0, CSR_PUSHMEPC, 12
|
||||
/* Store CSR msub to stack using pushmsub */
|
||||
csrrwi x0, CSR_PUSHMSUBM, 13
|
||||
.endm
|
||||
|
||||
/**
|
||||
* \brief Macro for restore necessary CSRs from stack
|
||||
* \details
|
||||
* This macro restore MSUBM, MEPC, MCAUSE from stack.
|
||||
*/
|
||||
.macro RESTORE_CSR_CONTEXT
|
||||
LOAD x5, 13*REGBYTES(sp)
|
||||
csrw CSR_MSUBM, x5
|
||||
LOAD x5, 12*REGBYTES(sp)
|
||||
csrw CSR_MEPC, x5
|
||||
LOAD x5, 11*REGBYTES(sp)
|
||||
csrw CSR_MCAUSE, x5
|
||||
.endm
|
||||
|
||||
/**
|
||||
* \brief Exception/NMI Entry
|
||||
* \details
|
||||
* This function provide common entry functions for exception/nmi.
|
||||
* \remarks
|
||||
* This function provide a default exception/nmi entry.
|
||||
* ABI defined caller save register and some CSR registers
|
||||
* to be saved before enter interrupt handler and be restored before return.
|
||||
*/
|
||||
.section .text.trap
|
||||
/* In CLIC mode, the exeception entry must be 64bytes aligned */
|
||||
.align 6
|
||||
.global exc_entry
|
||||
.weak exc_entry
|
||||
exc_entry:
|
||||
/* Save the caller saving registers (context) */
|
||||
SAVE_CONTEXT
|
||||
/* Save the necessary CSR registers */
|
||||
SAVE_CSR_CONTEXT
|
||||
|
||||
/*
|
||||
* Set the exception handler function arguments
|
||||
* argument 1: mcause value
|
||||
* argument 2: current stack point(SP) value
|
||||
*/
|
||||
csrr a0, mcause
|
||||
mv a1, sp
|
||||
/*
|
||||
* TODO: Call the exception handler function
|
||||
* By default, the function template is provided in
|
||||
* system_Device.c, you can adjust it as you want
|
||||
*/
|
||||
call core_exception_handler
|
||||
|
||||
/* Restore the necessary CSR registers */
|
||||
RESTORE_CSR_CONTEXT
|
||||
/* Restore the caller saving registers (context) */
|
||||
RESTORE_CONTEXT
|
||||
|
||||
/* Return to regular code */
|
||||
mret
|
||||
|
||||
/**
|
||||
* \brief Non-Vector Interrupt Entry
|
||||
* \details
|
||||
* This function provide common entry functions for handling
|
||||
* non-vector interrupts
|
||||
* \remarks
|
||||
* This function provide a default non-vector interrupt entry.
|
||||
* ABI defined caller save register and some CSR registers need
|
||||
* to be saved before enter interrupt handler and be restored before return.
|
||||
*/
|
||||
.section .text.irq
|
||||
/* In CLIC mode, the interrupt entry must be 4bytes aligned */
|
||||
.align 2
|
||||
.global irq_entry
|
||||
.weak irq_entry
|
||||
/* This label will be set to MTVT2 register */
|
||||
irq_entry:
|
||||
/* Save the caller saving registers (context) */
|
||||
SAVE_CONTEXT
|
||||
/* Save the necessary CSR registers */
|
||||
SAVE_CSR_CONTEXT
|
||||
|
||||
/* This special CSR read/write operation, which is actually
|
||||
* claim the CLIC to find its pending highest ID, if the ID
|
||||
* is not 0, then automatically enable the mstatus.MIE, and
|
||||
* jump to its vector-entry-label, and update the link register
|
||||
*/
|
||||
csrrw ra, CSR_JALMNXTI, ra
|
||||
|
||||
/* Critical section with interrupts disabled */
|
||||
DISABLE_MIE
|
||||
|
||||
/* Restore the necessary CSR registers */
|
||||
RESTORE_CSR_CONTEXT
|
||||
/* Restore the caller saving registers (context) */
|
||||
RESTORE_CONTEXT
|
||||
|
||||
/* Return to regular code */
|
||||
mret
|
||||
|
||||
/* Default Handler for Exceptions / Interrupts */
|
||||
.global default_intexc_handler
|
||||
.weak default_intexc_handler
|
||||
Undef_Handler:
|
||||
default_intexc_handler:
|
||||
1:
|
||||
j 1b
|
||||
+28
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
#include <xs_ktick.h>
|
||||
#include <gd32vf103.h>
|
||||
#include <core_feature_timer.h>
|
||||
|
||||
#define SysTick_Handler eclic_mtip_handler
|
||||
|
||||
/* This is the timer interrupt service routine. */
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
SysTick_Reload(SYSTICK_TICK_CONST);
|
||||
|
||||
// isrManager.done->incCounter();
|
||||
|
||||
TickAndTaskTimesliceUpdate();
|
||||
|
||||
// isrManager.done->decCounter();
|
||||
}
|
||||
Reference in New Issue
Block a user