support zynq7000-zc702
This commit is contained in:
TXuian
@@ -1,4 +1,4 @@
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SRC_DIR := preboot_for_nxp_imx6q_sabrelite
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SRC_FILES := boot.S context_switch.S core.c
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SRC_DIR := preboot_for_$(BOARD)
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SRC_FILES := context_switch.S core.c
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include $(KERNEL_ROOT)/compiler.mk
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+3
@@ -0,0 +1,3 @@
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SRC_FILES := ivt.c dcd.c imx6q_lowlevel_init.S cortexA9.S boot.S
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include $(KERNEL_ROOT)/compiler.mk
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+2
-4
@@ -2,8 +2,8 @@ export CROSS_COMPILE ?= arm-none-eabi-
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export DEVICE = -march=armv7-a -mtune=cortex-a9 -mfpu=vfpv3-d16 -ftree-vectorize -ffast-math -mfloat-abi=softfp
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export CFLAGS := $(DEVICE) -Wall -O0 -g -gdwarf-2
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export AFLAGS := -c $(DEVICE) -x assembler-with-cpp -D__ASSEMBLY__ -gdwarf-2
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# export LFLAGS := $(DEVICE) -Wl,-Map=XiZi-imx6q-sabrelite.map,-cref,-u,_boot_start -T $(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/nxp_imx6q_sabrelite.lds
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export LFLAGS := $(DEVICE) --specs=nosys.specs -Wl,-Map=XiZi-imx6q-sabrelite.map,-cref,-u,_boot_start -T $(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/nxp_imx6q_sabrelite.lds
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# export LFLAGS := $(DEVICE) -Wl,-Map=XiZi-imx6q-sabrelite.map,-cref,-u,_boot_start -T $(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_imx6q-sabrelite/nxp_imx6q_sabrelite.lds
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export LFLAGS := $(DEVICE) --specs=nosys.specs -Wl,-Map=XiZi-imx6q-sabrelite.map,-cref,-u,_boot_start -T $(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_imx6q-sabrelite/nxp_imx6q_sabrelite.lds
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export CXXFLAGS :=
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ifeq ($(CONFIG_LIB_MUSLLIB), y)
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@@ -14,7 +14,5 @@ endif
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export DEFINES := -DHAVE_CCONFIG_H -DCHIP_MX6DQ
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export USING_NEWLIB =1
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export USING_VFS = 1
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export ARCH = arm
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export ARCH_ARMV = armv7-a
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-3
@@ -1,3 +0,0 @@
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SRC_FILES := ivt.c dcd.c imx6q_lowlevel_init.S cortexA9.S
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include $(KERNEL_ROOT)/compiler.mk
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+3
@@ -0,0 +1,3 @@
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SRC_FILES := boot.S cpu_init.S xil-crt0.S cortexA9.S
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include $(KERNEL_ROOT)/compiler.mk
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+248
@@ -0,0 +1,248 @@
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/******************************************************************************
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*
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* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
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||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
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*
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||||
* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
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||||
*
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||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
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||||
*
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******************************************************************************/
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/*****************************************************************************/
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/**
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* @file boot.S
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*
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* This file contains the initial startup code for the Cortex A9 processor
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ------- -------- ---------------------------------------------------
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* 1.00a ecm/sdm 10/20/09 Initial version
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* 3.06a sgd 05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control
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* register settings.
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* 3.06a asa 06/17/12 Modified the TTBR settings and L2 Cache auxiliary
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* register settings.
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* 3.07a asa 07/16/12 Modified the L2 Cache controller settings to improve
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* performance. Changed the property of the ".boot"
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* section.
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* 3.07a sgd 08/21/12 Modified the L2 Cache controller and cp15 Aux Control
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* Register settings
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* 3.09a sgd 02/06/13 Updated SLCR l2c Ram Control register to a
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* value of 0x00020202. Fix for CR 697094 (SI#687034).
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* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
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* 'xil_errata.h' for errata description
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* 4.2 pkp 06/19/14 Enabled asynchronous abort exception
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* 5.0 pkp 16/15/14 Modified initialization code to enable scu after
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* MMU is enabled
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* 5.1 pkp 05/13/15 Changed the initialization order so to first invalidate
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* caches and TLB, enable MMU and caches, then enable SMP
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* bit in ACTLR. L2Cache invalidation and enabling of L2Cache
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* is done later.
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* </pre>
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*
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* @note
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*
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* None.
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*
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******************************************************************************/
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#include "xparameters.h"
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#include "xil_errata.h"
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.globl MMUTable
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.global _boot_start
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.global stacks_start
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.global _vector_jumper
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.set SYS_stack, stacks_start
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.set vector_base, _vector_jumper
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.set FPEXC_EN, 0x40000000 /* FPU enable bit, (1 << 30) */
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/* this initializes the various processor modes */
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_boot_start:
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#if XPAR_CPU_ID==0
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/* only allow cpu0 through */
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mrc p15,0,r1,c0,c0,5
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and r1, r1, #0xf
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cmp r1, #0
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beq OKToRun
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EndlessLoop0:
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wfe
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b EndlessLoop0
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#elif XPAR_CPU_ID==1
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/* only allow cpu1 through */
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mrc p15,0,r1,c0,c0,5
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and r1, r1, #0xf
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cmp r1, #1
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beq OKToRun
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EndlessLoop1:
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wfe
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b EndlessLoop1
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#endif
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OKToRun:
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mrc p15, 0, r0, c0, c0, 0 /* Get the revision */
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and r5, r0, #0x00f00000
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and r6, r0, #0x0000000f
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orr r6, r6, r5, lsr #20-4
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#ifdef CONFIG_ARM_ERRATA_742230
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cmp r6, #0x22 /* only present up to r2p2 */
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mrcle p15, 0, r10, c15, c0, 1 /* read diagnostic register */
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orrle r10, r10, #1 << 4 /* set bit #4 */
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mcrle p15, 0, r10, c15, c0, 1 /* write diagnostic register */
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#endif
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#ifdef CONFIG_ARM_ERRATA_743622
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teq r5, #0x00200000 /* only present in r2p* */
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mrceq p15, 0, r10, c15, c0, 1 /* read diagnostic register */
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orreq r10, r10, #1 << 6 /* set bit #6 */
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mcreq p15, 0, r10, c15, c0, 1 /* write diagnostic register */
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#endif
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/* set VBAR to the _vector_table address in linker script */
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ldr r0, =vector_base
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mcr p15, 0, r0, c12, c0, 0
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/*invalidate scu*/
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ldr r7, =0xf8f0000c
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ldr r6, =0xffff
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str r6, [r7]
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/* Invalidate caches and TLBs */
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mov r0,#0 /* r0 = 0 */
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mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
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mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
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mcr p15, 0, r0, c7, c5, 6 /* Invalidate branch predictor array */
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bl invalidate_dcache /* invalidate dcache */
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/* Disable MMU, if enabled */
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mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 */
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bic r0, r0, #0x1 /* clear bit 0 */
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mcr p15, 0, r0, c1, c0, 0 /* write value back */
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mrs r0, cpsr /* get the current PSR */
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mvn r1, #0x1f /* set up the system stack pointer */
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and r2, r1, r0
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orr r2, r2, #0x13 /* SVC mode */
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msr cpsr, r2
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ldr r13,=SYS_stack /* SYS stack pointer */
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/*set scu enable bit in scu*/
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ldr r7, =0xf8f00000
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ldr r0, [r7]
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orr r0, r0, #0x1
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str r0, [r7]
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mov r0, r0
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mrc p15, 0, r1, c1, c0, 2 /* read cp access control register (CACR) into r1 */
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orr r1, r1, #(0xf << 20) /* enable full access for p10 & p11 */
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mcr p15, 0, r1, c1, c0, 2 /* write back into CACR */
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/* enable vfp */
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fmrx r1, FPEXC /* read the exception register */
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orr r1,r1, #FPEXC_EN /* set VFP enable bit, leave the others in orig state */
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fmxr FPEXC, r1 /* write back the exception register */
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mrc p15,0,r0,c1,c0,0 /* flow prediction enable */
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orr r0, r0, #(0x01 << 11) /* #0x8000 */
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mcr p15,0,r0,c1,c0,0
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mrc p15,0,r0,c1,c0,1 /* read Auxiliary Control Register */
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orr r0, r0, #(0x1 << 2) /* enable Dside prefetch */
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orr r0, r0, #(0x1 << 1) /* enable L2 Prefetch hint */
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mcr p15,0,r0,c1,c0,1 /* write Auxiliary Control Register */
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mrs r0, cpsr /* get the current PSR */
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bic r0, r0, #0x100 /* enable asynchronous abort exception */
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msr cpsr_xsf, r0
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b _start /* jump to C startup code */
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and r0, r0, r0 /* no op */
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||||
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.Ldone: b .Ldone /* Paranoia: we should never get here */
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||||
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/*
|
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*************************************************************************
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||||
*
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* invalidate_dcache - invalidate the entire d-cache by set/way
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||||
*
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* Note: for Cortex-A9, there is no cp instruction for invalidating
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* the whole D-cache. Need to invalidate each line.
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*
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||||
*************************************************************************
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||||
*/
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invalidate_dcache:
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mrc p15, 1, r0, c0, c0, 1 /* read CLIDR */
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ands r3, r0, #0x7000000
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mov r3, r3, lsr #23 /* cache level value (naturally aligned) */
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||||
beq finished
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mov r10, #0 /* start with level 0 */
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loop1:
|
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add r2, r10, r10, lsr #1 /* work out 3xcachelevel */
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mov r1, r0, lsr r2 /* bottom 3 bits are the Cache type for this level */
|
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and r1, r1, #7 /* get those 3 bits alone */
|
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cmp r1, #2
|
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blt skip /* no cache or only instruction cache at this level */
|
||||
mcr p15, 2, r10, c0, c0, 0 /* write the Cache Size selection register */
|
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isb /* isb to sync the change to the CacheSizeID reg */
|
||||
mrc p15, 1, r1, c0, c0, 0 /* reads current Cache Size ID register */
|
||||
and r2, r1, #7 /* extract the line length field */
|
||||
add r2, r2, #4 /* add 4 for the line length offset (log2 16 bytes) */
|
||||
ldr r4, =0x3ff
|
||||
ands r4, r4, r1, lsr #3 /* r4 is the max number on the way size (right aligned) */
|
||||
clz r5, r4 /* r5 is the bit position of the way size increment */
|
||||
ldr r7, =0x7fff
|
||||
ands r7, r7, r1, lsr #13 /* r7 is the max number of the index size (right aligned) */
|
||||
loop2:
|
||||
mov r9, r4 /* r9 working copy of the max way size (right aligned) */
|
||||
loop3:
|
||||
orr r11, r10, r9, lsl r5 /* factor in the way number and cache number into r11 */
|
||||
orr r11, r11, r7, lsl r2 /* factor in the index number */
|
||||
mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */
|
||||
subs r9, r9, #1 /* decrement the way number */
|
||||
bge loop3
|
||||
subs r7, r7, #1 /* decrement the index */
|
||||
bge loop2
|
||||
skip:
|
||||
add r10, r10, #2 /* increment the cache number */
|
||||
cmp r3, r10
|
||||
bgt loop1
|
||||
|
||||
finished:
|
||||
mov r10, #0 /* swith back to cache level 0 */
|
||||
mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */
|
||||
dsb
|
||||
isb
|
||||
|
||||
bx lr
|
||||
|
||||
.end
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
export CROSS_COMPILE ?= arm-xilinx-eabi-
|
||||
export DEVICE =
|
||||
export CFLAGS := $(DEVICE) -Wall -O0 -g -std=c11
|
||||
export AFLAGS := -r
|
||||
export LFLAGS := $(DEVICE) -Wl,-T -Wl,$(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_$(BOARD)/$(BOARD).lds -Wl,--start-group,-lgcc,-lc,--end-group
|
||||
export CXXFLAGS :=
|
||||
|
||||
export ARCH = arm
|
||||
export ARCH_ARMV = armv7-a
|
||||
Executable
+340
@@ -0,0 +1,340 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2012, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file cortexA9.s
|
||||
* @brief This file contains cortexA9 functions
|
||||
*
|
||||
*/
|
||||
/*************************************************
|
||||
File name: cortexA9.S
|
||||
Description: This file contains cortexA9 functions
|
||||
Others:
|
||||
History:
|
||||
1. Date: 2023-08-28
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. No modifications
|
||||
*************************************************/
|
||||
|
||||
.code 32
|
||||
.section ".text","ax"
|
||||
|
||||
/*
|
||||
* bool arm_set_interrupt_state(bool enable)
|
||||
*/
|
||||
.global arm_set_interrupt_state
|
||||
.func arm_set_interrupt_state
|
||||
arm_set_interrupt_state:
|
||||
mrs r2,CPSR @ read CPSR (Current Program Status Register)
|
||||
teq r0,#0
|
||||
bicne r1,r2,#0xc0 @ disable IRQ and FIQ
|
||||
orreq r1,r2,#0xc0 @ enable IRQ and FIQ
|
||||
msr CPSR_c,r1
|
||||
tst r2,#0x80
|
||||
movne r0,#0
|
||||
moveq r0,#1
|
||||
bx lr
|
||||
.endfunc
|
||||
|
||||
.global cpu_get_current
|
||||
@ int cpu_get_current(void)@
|
||||
@ get current CPU ID
|
||||
.func cpu_get_current
|
||||
cpu_get_current:
|
||||
mrc p15, 0, r0, c0, c0, 5
|
||||
and r0, r0, #3
|
||||
BX lr
|
||||
.endfunc @cpu_get_current()@
|
||||
|
||||
.global enable_neon_fpu
|
||||
.func enable_neon_fpu
|
||||
enable_neon_fpu:
|
||||
/* set NSACR, both Secure and Non-secure access are allowed to NEON */
|
||||
MRC p15, 0, r0, c1, c1, 2
|
||||
ORR r0, r0, #(0x3<<10) @ enable fpu/neon
|
||||
MCR p15, 0, r0, c1, c1, 2
|
||||
/* Set the CPACR for access to CP10 and CP11*/
|
||||
LDR r0, =0xF00000
|
||||
MCR p15, 0, r0, c1, c0, 2
|
||||
/* Set the FPEXC EN bit to enable the FPU */
|
||||
MOV r3, #0x40000000
|
||||
@VMSR FPEXC, r3
|
||||
MCR p10, 7, r3, c8, c0, 0
|
||||
.endfunc
|
||||
|
||||
.global disable_strict_align_check
|
||||
.func disable_strict_align_check
|
||||
disable_strict_align_check:
|
||||
/*Ray's note: disable strict alignment fault checking.
|
||||
without disabling this, data abort will happen when accessing
|
||||
the BPB structure of file system since it is packed.*/
|
||||
|
||||
push {r0, lr}
|
||||
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
bic r0, r0, #(0x1<<1) @clear A bit of SCTLR
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
|
||||
pop {r0, pc}
|
||||
.endfunc
|
||||
|
||||
.global disable_L1_cache
|
||||
.func disable_L1_cache
|
||||
disable_L1_cache:
|
||||
push {r0-r6, lr}
|
||||
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
bic r0, r0, #(0x1<<12)
|
||||
bic r0, r0, #(0x1<<11)
|
||||
bic r0, r0, #(0x1<<2)
|
||||
bic r0, r0, #(0x1<<0)
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
|
||||
pop {r0-r6, pc}
|
||||
|
||||
.endfunc
|
||||
|
||||
.global get_arm_private_peripheral_base
|
||||
@ uint32_t get_arm_private_peripheral_base(void)@
|
||||
.func get_arm_private_peripheral_base
|
||||
get_arm_private_peripheral_base:
|
||||
|
||||
@ Get base address of private perpherial space
|
||||
mrc p15, 4, r0, c15, c0, 0 @ Read periph base address
|
||||
@ mov r0, #0x00A00000
|
||||
bx lr
|
||||
|
||||
.endfunc @get_arm_private_peripheral_base()@
|
||||
|
||||
@ ------------------------------------------------------------
|
||||
@ TLB
|
||||
@ ------------------------------------------------------------
|
||||
|
||||
.global arm_unified_tlb_invalidate
|
||||
@ void arm_unified_tlb_invalidate(void)@
|
||||
.func arm_unified_tlb_invalidate
|
||||
arm_unified_tlb_invalidate:
|
||||
mov r0, #1
|
||||
mcr p15, 0, r0, c8, c7, 0 @ TLBIALL - Invalidate entire unified TLB
|
||||
dsb
|
||||
bx lr
|
||||
.endfunc
|
||||
|
||||
.global arm_unified_tlb_invalidate_is
|
||||
@ void arm_unified_tlb_invalidate_is(void)@
|
||||
.func arm_unified_tlb_invalidate_is
|
||||
arm_unified_tlb_invalidate_is:
|
||||
mov r0, #1
|
||||
mcr p15, 0, r0, c8, c3, 0 @ TLBIALLIS - Invalidate entire unified TLB Inner Shareable
|
||||
dsb
|
||||
bx lr
|
||||
.endfunc
|
||||
|
||||
@ ------------------------------------------------------------
|
||||
@ Branch Prediction
|
||||
@ ------------------------------------------------------------
|
||||
|
||||
.global arm_branch_prediction_enable
|
||||
@ void arm_branch_prediction_enable(void)
|
||||
.func arm_branch_prediction_enable
|
||||
arm_branch_prediction_enable:
|
||||
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR
|
||||
orr r0, r0, #(1 << 11) @ Set the Z bit (bit 11)
|
||||
mcr p15, 0,r0, c1, c0, 0 @ Write SCTLR
|
||||
bx lr
|
||||
.endfunc
|
||||
|
||||
.global arm_branch_prediction_disable
|
||||
@ void arm_branch_prediction_disable(void)
|
||||
.func arm_branch_prediction_disable
|
||||
arm_branch_prediction_disable:
|
||||
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR
|
||||
bic r0, r0, #(1 << 11) @ Clear the Z bit (bit 11)
|
||||
mcr p15, 0,r0, c1, c0, 0 @ Write SCTLR
|
||||
bx lr
|
||||
.endfunc
|
||||
|
||||
.global arm_branch_target_cache_invalidate
|
||||
@ void arm_branch_target_cache_invalidate(void)
|
||||
.func arm_branch_target_cache_invalidate
|
||||
arm_branch_target_cache_invalidate:
|
||||
mov r0, #0
|
||||
mcr p15, 0, r0, c7, c5, 6 @ BPIALL - Invalidate entire branch predictor array
|
||||
bx lr
|
||||
.endfunc
|
||||
|
||||
.global arm_branch_target_cache_invalidate_is
|
||||
@ void arm_branch_target_cache_invalidate_is(void)
|
||||
.func arm_branch_target_cache_invalidate_is
|
||||
arm_branch_target_cache_invalidate_is:
|
||||
mov r0, #0
|
||||
mcr p15, 0, r0, c7, c1, 6 @ BPIALLIS - Invalidate entire branch predictor array Inner Shareable
|
||||
bx lr
|
||||
.endfunc
|
||||
|
||||
@ ------------------------------------------------------------
|
||||
@ SCU
|
||||
@ ------------------------------------------------------------
|
||||
|
||||
@ SCU offset from base of private peripheral space --> 0x000
|
||||
|
||||
.global scu_enable
|
||||
@ void scu_enable(void)
|
||||
@ Enables the SCU
|
||||
.func scu_enable
|
||||
scu_enable:
|
||||
|
||||
@ mrc p15, 4, r0, c15, c0, 0 @ Read periph base address
|
||||
mov r0, #0x00A00000
|
||||
|
||||
ldr r1, [r0, #0x0] @ Read the SCU Control Register
|
||||
orr r1, r1, #0x1 @ Set bit 0 (The Enable bit)
|
||||
str r1, [r0, #0x0] @ Write back modifed value
|
||||
|
||||
bx lr
|
||||
.endfunc
|
||||
|
||||
@ ------------------------------------------------------------
|
||||
|
||||
.global scu_join_smp
|
||||
@ void scu_join_smp(void)
|
||||
@ Set this CPU as participating in SMP
|
||||
.func scu_join_smp
|
||||
scu_join_smp:
|
||||
|
||||
@ SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg
|
||||
|
||||
mrc p15, 0, r0, c1, c0, 1 @ Read ACTLR
|
||||
orr r0, r0, #0x040 @ Set bit 6
|
||||
mcr p15, 0, r0, c1, c0, 1 @ Write ACTLR
|
||||
|
||||
bx lr
|
||||
.endfunc
|
||||
|
||||
@ ------------------------------------------------------------
|
||||
|
||||
.global scu_leave_smp
|
||||
@ void scu_leave_smp(void)
|
||||
@ Set this CPU as NOT participating in SMP
|
||||
.func scu_leave_smp
|
||||
scu_leave_smp:
|
||||
|
||||
@ SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg
|
||||
|
||||
mrc p15, 0, r0, c1, c0, 1 @ Read ACTLR
|
||||
bic r0, r0, #0x040 @ Clear bit 6
|
||||
mcr p15, 0, r0, c1, c0, 1 @ Write ACTLR
|
||||
|
||||
bx lr
|
||||
.endfunc
|
||||
|
||||
@ ------------------------------------------------------------
|
||||
|
||||
.global scu_get_cpus_in_smp
|
||||
@ unsigned int scu_get_cpus_in_smp(void)
|
||||
@ The return value is 1 bit per core:
|
||||
@ bit 0 - CPU 0
|
||||
@ bit 1 - CPU 1
|
||||
@ etc...
|
||||
.func scu_get_cpus_in_smp
|
||||
scu_get_cpus_in_smp:
|
||||
|
||||
@ mrc p15, 4, r0, c15, c0, 0 @ Read periph base address
|
||||
mov r0, #0x00A00000
|
||||
|
||||
ldr r0, [r0, #0x004] @ Read SCU Configuration register
|
||||
mov r0, r0, lsr #4 @ Bits 7:4 gives the cores in SMP mode, shift then mask
|
||||
and r0, r0, #0x0F
|
||||
|
||||
bx lr
|
||||
.endfunc
|
||||
|
||||
@ ------------------------------------------------------------
|
||||
|
||||
.global scu_enable_maintenance_broadcast
|
||||
@ void scu_enable_maintenance_broadcast(void)
|
||||
@ Enable the broadcasting of cache & TLB maintenance operations
|
||||
@ When enabled AND in SMP, broadcast all "inner sharable"
|
||||
@ cache and TLM maintenance operations to other SMP cores
|
||||
.func scu_enable_maintenance_broadcast
|
||||
scu_enable_maintenance_broadcast:
|
||||
mrc p15, 0, r0, c1, c0, 1 @ Read Aux Ctrl register
|
||||
orr r0, r0, #0x01 @ Set the FW bit (bit 0)
|
||||
mcr p15, 0, r0, c1, c0, 1 @ Write Aux Ctrl register
|
||||
|
||||
bx lr
|
||||
.endfunc
|
||||
|
||||
@ ------------------------------------------------------------
|
||||
|
||||
.global scu_disable_maintenance_broadcast
|
||||
@ void scu_disable_maintenance_broadcast(void)
|
||||
@ Disable the broadcasting of cache & TLB maintenance operations
|
||||
.func scu_disable_maintenance_broadcast
|
||||
scu_disable_maintenance_broadcast:
|
||||
mrc p15, 0, r0, c1, c0, 1 @ Read Aux Ctrl register
|
||||
bic r0, r0, #0x01 @ Clear the FW bit (bit 0)
|
||||
mcr p15, 0, r0, c1, c0, 1 @ Write Aux Ctrl register
|
||||
|
||||
bx lr
|
||||
.endfunc
|
||||
|
||||
@ ------------------------------------------------------------
|
||||
|
||||
.global scu_secure_invalidate
|
||||
@ void scu_secure_invalidate(unsigned int cpu, unsigned int ways)
|
||||
@ cpu: 0x0=CPU 0 0x1=CPU 1 etc...
|
||||
@ This function invalidates the SCU copy of the tag rams
|
||||
@ for the specified core. typically only done at start-up.
|
||||
@ Possible flow:
|
||||
@ - Invalidate L1 caches
|
||||
@ - Invalidate SCU copy of TAG RAMs
|
||||
@ - Join SMP
|
||||
.func scu_secure_invalidate
|
||||
scu_secure_invalidate:
|
||||
and r0, r0, #0x03 @ Mask off unused bits of CPU ID
|
||||
mov r0, r0, lsl #2 @ Convert into bit offset (four bits per core)
|
||||
|
||||
and r1, r1, #0x0F @ Mask off unused bits of ways
|
||||
mov r1, r1, lsl r0 @ Shift ways into the correct CPU field
|
||||
|
||||
mrc p15, 4, r2, c15, c0, 0 @ Read periph base address
|
||||
|
||||
str r1, [r2, #0x0C] @ Write to SCU Invalidate All in Secure State
|
||||
|
||||
bx lr
|
||||
|
||||
.endfunc
|
||||
|
||||
@ ------------------------------------------------------------
|
||||
@ End of cortexA9.s
|
||||
@ ------------------------------------------------------------
|
||||
.end
|
||||
+80
@@ -0,0 +1,80 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file cpu_init.s
|
||||
*
|
||||
* This file contains CPU specific initialization. Invoked from main CRT
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ------- -------- ---------------------------------------------------
|
||||
* 1.00a ecm/sdm 10/20/09 Initial version
|
||||
* 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
|
||||
* 5.0 pkp 12/16/14 removed incorrect initialization of TLB lockdown
|
||||
* register to fix CR#830580
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* None.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
.text
|
||||
.global __cpu_init
|
||||
.align 2
|
||||
__cpu_init:
|
||||
|
||||
/* Clear cp15 regs with unknown reset values */
|
||||
mov r0, #0x0
|
||||
mcr p15, 0, r0, c5, c0, 0 /* DFSR */
|
||||
mcr p15, 0, r0, c5, c0, 1 /* IFSR */
|
||||
mcr p15, 0, r0, c6, c0, 0 /* DFAR */
|
||||
mcr p15, 0, r0, c6, c0, 2 /* IFAR */
|
||||
mcr p15, 0, r0, c9, c13, 2 /* PMXEVCNTR */
|
||||
mcr p15, 0, r0, c13, c0, 2 /* TPIDRURW */
|
||||
mcr p15, 0, r0, c13, c0, 3 /* TPIDRURO */
|
||||
|
||||
/* Reset and start Cycle Counter */
|
||||
mov r2, #0x80000000 /* clear overflow */
|
||||
mcr p15, 0, r2, c9, c12, 3
|
||||
mov r2, #0xd /* D, C, E */
|
||||
mcr p15, 0, r2, c9, c12, 0
|
||||
mov r2, #0x80000000 /* enable cycle counter */
|
||||
mcr p15, 0, r2, c9, c12, 1
|
||||
|
||||
bx lr
|
||||
|
||||
.end
|
||||
+251
@@ -0,0 +1,251 @@
|
||||
/*
|
||||
* Copyright (c) 2012, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
/**
|
||||
* @file cortex_a9.h
|
||||
* @brief some cortex A9 core functions
|
||||
* @version 3.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2023.08.25
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: cortex_a9.h
|
||||
Description: some cortex A9 core functions
|
||||
Others:
|
||||
History:
|
||||
1. Date: 2023-08-28
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. No modifications
|
||||
*************************************************/
|
||||
#if !defined(__CORTEX_A9_H__)
|
||||
#define __CORTEX_A9_H__
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
//! @addtogroup cortexa9
|
||||
//! @{
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Definitions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//! @name Instruction macros
|
||||
//@{
|
||||
#define NOP() __asm__ volatile("nop\n\t")
|
||||
#define WFI() __asm__ volatile("wfi\n\t")
|
||||
#define WFE() __asm__ volatile("wfe\n\t")
|
||||
#define SEV() __asm__ volatile("sev\n\t")
|
||||
#define DMB() __asm__ volatile("dmb\n\t")
|
||||
#define DSB() __asm__ volatile("dsb\n\t")
|
||||
#define ISB() __asm__ volatile("isb\n\t")
|
||||
|
||||
#define _ARM_MRC(coproc, opcode1, Rt, CRn, CRm, opcode2) \
|
||||
__asm__ __volatile__("mrc p" #coproc ", " #opcode1 ", %[output], c" #CRn ", c" #CRm ", " #opcode2 "\n" : [output] "=r"(Rt))
|
||||
|
||||
#define _ARM_MCR(coproc, opcode1, Rt, CRn, CRm, opcode2) \
|
||||
__asm__ __volatile__("mcr p" #coproc ", " #opcode1 ", %[input], c" #CRn ", c" #CRm ", " #opcode2 "\n" ::[input] "r"(Rt))
|
||||
|
||||
#define WriteReg(value, address) (*(volatile unsigned int*)(address) = (value))
|
||||
#define ReadReg(address) (*(volatile unsigned int*)(address))
|
||||
//@}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Code
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//! @name Misc
|
||||
//@{
|
||||
//! @brief Enable or disable the IRQ and FIQ state.
|
||||
bool arm_set_interrupt_state(bool enable);
|
||||
|
||||
//! @brief Get current CPU ID.
|
||||
int cpu_get_current(void);
|
||||
|
||||
//! @brief Enable the NEON MPE.
|
||||
void enable_neon_fpu(void);
|
||||
|
||||
//! @brief Disable aborts on unaligned accesses.
|
||||
void disable_strict_align_check(void);
|
||||
|
||||
//! @brief Get base address of private perpherial space.
|
||||
//!
|
||||
//! @return The address of the ARM CPU's private peripherals.
|
||||
// uint32_t get_arm_private_peripheral_base(void);
|
||||
//@}
|
||||
|
||||
//! @name Data cache operations
|
||||
//@{
|
||||
|
||||
//! @brief Check if dcache is enabled or disabled.
|
||||
int arm_dcache_state_query();
|
||||
|
||||
//! @brief Enables data cache at any available cache level.
|
||||
//!
|
||||
//! Works only if MMU is enabled!
|
||||
void arm_dcache_enable();
|
||||
|
||||
//! @brief Disables the data cache at any available cache level.
|
||||
void arm_dcache_disable();
|
||||
|
||||
//! @brief Invalidates the entire data cache.
|
||||
void arm_dcache_invalidate();
|
||||
|
||||
//! @brief Invalidate a line of data cache.
|
||||
void arm_dcache_invalidate_line(const void* addr);
|
||||
|
||||
//! @brief Invalidate a number of lines of data cache.
|
||||
//!
|
||||
//! Number of lines depends on length parameter and size of line.
|
||||
//! Size of line for A9 L1 cache is 32B.
|
||||
void arm_dcache_invalidate_mlines(const void* addr, size_t length);
|
||||
|
||||
//! @brief Flush (clean) all lines of cache (all sets in all ways).
|
||||
void arm_dcache_flush();
|
||||
|
||||
//! @brief Flush (clean) one line of cache.
|
||||
void arm_dcache_flush_line(const void* addr);
|
||||
|
||||
// @brief Flush (clean) multiple lines of cache.
|
||||
//!
|
||||
//! Number of lines depends on length parameter and size of line.
|
||||
void arm_dcache_flush_mlines(const void* addr, size_t length);
|
||||
//@}
|
||||
|
||||
//! @name Instrution cache operations
|
||||
//@{
|
||||
|
||||
//! @brief Check if icache is enabled or disabled.
|
||||
int arm_icache_state_query();
|
||||
|
||||
//! @brief Enables instruction cache at any available cache level.
|
||||
//!
|
||||
//! Works without enabled MMU too!
|
||||
void arm_icache_enable();
|
||||
|
||||
//! @brief Disables the instruction cache at any available cache level.
|
||||
void arm_icache_disable();
|
||||
|
||||
//! @brief Invalidates the entire instruction cache.
|
||||
void arm_icache_invalidate();
|
||||
|
||||
//! @brief Invalidates the entire instruction cache inner shareable.
|
||||
void arm_icache_invalidate_is();
|
||||
|
||||
//! @brief Invalidate a line of the instruction cache.
|
||||
void arm_icache_invalidate_line(const void* addr);
|
||||
|
||||
//! @brief Invalidate a number of lines of instruction cache.
|
||||
//!
|
||||
//! Number of lines depends on length parameter and size of line.
|
||||
void arm_icache_invalidate_mlines(const void* addr, size_t length);
|
||||
//@}
|
||||
|
||||
//! @name TLB operations
|
||||
//@{
|
||||
//! @brief Invalidate entire unified TLB.
|
||||
void arm_unified_tlb_invalidate(void);
|
||||
|
||||
//! @brief Invalidate entire unified TLB Inner Shareable.
|
||||
void arm_unified_tlb_invalidate_is(void);
|
||||
//@}
|
||||
|
||||
//! @name Branch predictor operations
|
||||
//@{
|
||||
//! @brief Enable branch prediction.
|
||||
void arm_branch_prediction_enable(void);
|
||||
|
||||
//! @brief Disable branch prediction.
|
||||
void arm_branch_prediction_disable(void);
|
||||
|
||||
//! @brief Invalidate entire branch predictor array.
|
||||
void arm_branch_target_cache_invalidate(void);
|
||||
|
||||
//! @brief Invalidate entire branch predictor array Inner Shareable
|
||||
void arm_branch_target_cache_invalidate_is(void);
|
||||
//@}
|
||||
|
||||
//! @name SCU
|
||||
//@{
|
||||
//! @brief Enables the SCU.
|
||||
void scu_enable(void);
|
||||
|
||||
//! @brief Set this CPU as participating in SMP.
|
||||
void scu_join_smp(void);
|
||||
|
||||
//! @brief Set this CPU as not participating in SMP.
|
||||
void scu_leave_smp(void);
|
||||
|
||||
//! @brief Determine which CPUs are participating in SMP.
|
||||
//!
|
||||
//! The return value is 1 bit per core:
|
||||
//! - bit 0 - CPU 0
|
||||
//! - bit 1 - CPU 1
|
||||
//! - etc...
|
||||
unsigned int scu_get_cpus_in_smp(void);
|
||||
|
||||
//! @brief Enable the broadcasting of cache & TLB maintenance operations.
|
||||
//!
|
||||
//! When enabled AND in SMP, broadcast all "inner sharable"
|
||||
//! cache and TLM maintenance operations to other SMP cores
|
||||
void scu_enable_maintenance_broadcast(void);
|
||||
|
||||
//! @brief Disable the broadcasting of cache & TLB maintenance operations.
|
||||
void scu_disable_maintenance_broadcast(void);
|
||||
|
||||
//! @brief Invalidates the SCU copy of the tag rams for the specified core.
|
||||
//!
|
||||
//! Typically only done at start-up.
|
||||
//! Possible flow:
|
||||
//! - Invalidate L1 caches
|
||||
//! - Invalidate SCU copy of TAG RAMs
|
||||
//! - Join SMP
|
||||
//!
|
||||
//! @param cpu 0x0=CPU 0, 0x1=CPU 1, etc...
|
||||
//! @param ways The ways to invalidate. Pass 0xf to invalidate all ways.
|
||||
void scu_secure_invalidate(unsigned int cpu, unsigned int ways);
|
||||
//@}
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
//! @}
|
||||
|
||||
#endif // __CORTEX_A9_H__
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// EOF
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
+189
@@ -0,0 +1,189 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xil_assert.h
|
||||
*
|
||||
* This file contains assert related functions.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.00a hbm 07/14/09 First release
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef XIL_ASSERT_H /* prevent circular inclusions */
|
||||
#define XIL_ASSERT_H /* by using protection macros */
|
||||
|
||||
#include "xil_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
#define XIL_ASSERT_NONE 0U
|
||||
#define XIL_ASSERT_OCCURRED 1U
|
||||
#define XNULL NULL
|
||||
|
||||
extern u32 Xil_AssertStatus;
|
||||
extern void Xil_Assert(const char8 *File, s32 Line);
|
||||
void XNullHandler(void *NullParameter);
|
||||
|
||||
/**
|
||||
* This data type defines a callback to be invoked when an
|
||||
* assert occurs. The callback is invoked only when asserts are enabled
|
||||
*/
|
||||
typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
#ifndef NDEBUG
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* This assert macro is to be used for functions that do not return anything
|
||||
* (void). This in conjunction with the Xil_AssertWait boolean can be used to
|
||||
* accomodate tests so that asserts which fail allow execution to continue.
|
||||
*
|
||||
* @param Expression is the expression to evaluate. If it evaluates to
|
||||
* false, the assert occurs.
|
||||
*
|
||||
* @return Returns void unless the Xil_AssertWait variable is true, in which
|
||||
* case no return is made and an infinite loop is entered.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_AssertVoid(Expression) \
|
||||
{ \
|
||||
if (Expression) { \
|
||||
Xil_AssertStatus = XIL_ASSERT_NONE; \
|
||||
} else { \
|
||||
Xil_Assert(__FILE__, __LINE__); \
|
||||
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
|
||||
return; \
|
||||
} \
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* This assert macro is to be used for functions that do return a value. This in
|
||||
* conjunction with the Xil_AssertWait boolean can be used to accomodate tests
|
||||
* so that asserts which fail allow execution to continue.
|
||||
*
|
||||
* @param Expression is the expression to evaluate. If it evaluates to false,
|
||||
* the assert occurs.
|
||||
*
|
||||
* @return Returns 0 unless the Xil_AssertWait variable is true, in which
|
||||
* case no return is made and an infinite loop is entered.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_AssertNonvoid(Expression) \
|
||||
{ \
|
||||
if (Expression) { \
|
||||
Xil_AssertStatus = XIL_ASSERT_NONE; \
|
||||
} else { \
|
||||
Xil_Assert(__FILE__, __LINE__); \
|
||||
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
|
||||
return 0; \
|
||||
} \
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* Always assert. This assert macro is to be used for functions that do not
|
||||
* return anything (void). Use for instances where an assert should always
|
||||
* occur.
|
||||
*
|
||||
* @return Returns void unless the Xil_AssertWait variable is true, in which
|
||||
* case no return is made and an infinite loop is entered.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_AssertVoidAlways() \
|
||||
{ \
|
||||
Xil_Assert(__FILE__, __LINE__); \
|
||||
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
|
||||
return; \
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* Always assert. This assert macro is to be used for functions that do return
|
||||
* a value. Use for instances where an assert should always occur.
|
||||
*
|
||||
* @return Returns void unless the Xil_AssertWait variable is true, in which
|
||||
* case no return is made and an infinite loop is entered.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define Xil_AssertNonvoidAlways() \
|
||||
{ \
|
||||
Xil_Assert(__FILE__, __LINE__); \
|
||||
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
|
||||
return 0; \
|
||||
}
|
||||
|
||||
|
||||
#else
|
||||
|
||||
#define Xil_AssertVoid(Expression)
|
||||
#define Xil_AssertVoidAlways()
|
||||
#define Xil_AssertNonvoid(Expression)
|
||||
#define Xil_AssertNonvoidAlways()
|
||||
|
||||
#endif
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
void Xil_AssertSetCallback(Xil_AssertCallback Routine);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
+109
@@ -0,0 +1,109 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xil_errata.h
|
||||
*
|
||||
* This header file contains Cortex A9 and PL310 Errata definitions.
|
||||
*
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -----------------------------------------------
|
||||
* 1.00a srt 04/18/13 First release
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef XIL_ERRATA_H
|
||||
#define XIL_ERRATA_H
|
||||
|
||||
#define ENABLE_ARM_ERRATA 1
|
||||
|
||||
#ifdef ENABLE_ARM_ERRATA
|
||||
/* Cortex A9 ARM Errata */
|
||||
|
||||
/*
|
||||
* Errata No: 742230
|
||||
* Description: DMB operation may be faulty
|
||||
*/
|
||||
#define CONFIG_ARM_ERRATA_742230 1
|
||||
|
||||
/*
|
||||
* Errata No: 743622
|
||||
* Description: Faulty hazard checking in the Store Buffer may lead
|
||||
* to data corruption.
|
||||
*/
|
||||
#define CONFIG_ARM_ERRATA_743622 1
|
||||
|
||||
/*
|
||||
* Errata No: 775420
|
||||
* Description: A data cache maintenance operation which aborts,
|
||||
* might lead to deadlock
|
||||
*/
|
||||
#define CONFIG_ARM_ERRATA_775420 1
|
||||
|
||||
/*
|
||||
* Errata No: 794073
|
||||
* Description: Speculative instruction fetches with MMU disabled
|
||||
* might not comply with architectural requirements
|
||||
*/
|
||||
#define CONFIG_ARM_ERRATA_794073 1
|
||||
|
||||
|
||||
/* PL310 L2 Cache Errata */
|
||||
|
||||
/*
|
||||
* Errata No: 588369
|
||||
* Description: Clean & Invalidate maintenance operations do not
|
||||
* invalidate clean lines
|
||||
*/
|
||||
#define CONFIG_PL310_ERRATA_588369 1
|
||||
|
||||
/*
|
||||
* Errata No: 727915
|
||||
* Description: Background Clean and Invalidate by Way operation
|
||||
* can cause data corruption
|
||||
*/
|
||||
#define CONFIG_PL310_ERRATA_727915 1
|
||||
|
||||
/*
|
||||
* Errata No: 753970
|
||||
* Description: Cache sync operation may be faulty
|
||||
*/
|
||||
#define CONFIG_PL310_ERRATA_753970 1
|
||||
|
||||
#endif /* ENABLE_ARM_ERRATA */
|
||||
|
||||
#endif /* XIL_ERRATA_H */
|
||||
+200
@@ -0,0 +1,200 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xil_types.h
|
||||
*
|
||||
* This file contains basic types for Xilinx software IP.
|
||||
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.00a hbm 07/14/09 First release
|
||||
* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
|
||||
* 5.00 pkp 05/29/14 Made changes for 64 bit architecture
|
||||
* srt 07/14/14 Use standard definitions from stdint.h and stddef.h
|
||||
* Define LONG and ULONG datatypes and mask values
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef XIL_TYPES_H /* prevent circular inclusions */
|
||||
#define XIL_TYPES_H /* by using protection macros */
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
#ifndef TRUE
|
||||
# define TRUE 1U
|
||||
#endif
|
||||
|
||||
#ifndef FALSE
|
||||
# define FALSE 0U
|
||||
#endif
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL 0U
|
||||
#endif
|
||||
|
||||
#define XIL_COMPONENT_IS_READY 0x11111111U /**< component has been initialized */
|
||||
#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< component has been started */
|
||||
|
||||
/** @name New types
|
||||
* New simple types.
|
||||
* @{
|
||||
*/
|
||||
#ifndef __KERNEL__
|
||||
#ifndef XBASIC_TYPES_H
|
||||
/**
|
||||
* guarded against xbasic_types.h.
|
||||
*/
|
||||
typedef uint8_t u8;
|
||||
typedef uint16_t u16;
|
||||
typedef uint32_t u32;
|
||||
|
||||
#define __XUINT64__
|
||||
typedef struct
|
||||
{
|
||||
u32 Upper;
|
||||
u32 Lower;
|
||||
} Xuint64;
|
||||
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* Return the most significant half of the 64 bit data type.
|
||||
*
|
||||
* @param x is the 64 bit word.
|
||||
*
|
||||
* @return The upper 32 bits of the 64 bit word.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XUINT64_MSW(x) ((x).Upper)
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* Return the least significant half of the 64 bit data type.
|
||||
*
|
||||
* @param x is the 64 bit word.
|
||||
*
|
||||
* @return The lower 32 bits of the 64 bit word.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XUINT64_LSW(x) ((x).Lower)
|
||||
|
||||
#endif /* XBASIC_TYPES_H */
|
||||
|
||||
/**
|
||||
* xbasic_types.h does not typedef s* or u64
|
||||
*/
|
||||
|
||||
typedef char char8;
|
||||
typedef int8_t s8;
|
||||
typedef int16_t s16;
|
||||
typedef int32_t s32;
|
||||
typedef int64_t s64;
|
||||
typedef uint64_t u64;
|
||||
typedef int sint32;
|
||||
|
||||
typedef intptr_t INTPTR;
|
||||
typedef uintptr_t UINTPTR;
|
||||
typedef ptrdiff_t PTRDIFF;
|
||||
|
||||
#if !defined(LONG) || !defined(ULONG)
|
||||
typedef long LONG;
|
||||
typedef unsigned long ULONG;
|
||||
#endif
|
||||
|
||||
#define ULONG64_HI_MASK 0xFFFFFFFF00000000U
|
||||
#define ULONG64_LO_MASK ~ULONG64_HI_MASK
|
||||
|
||||
#else
|
||||
#include <linux/types.h>
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* This data type defines an interrupt handler for a device.
|
||||
* The argument points to the instance of the component
|
||||
*/
|
||||
typedef void (*XInterruptHandler) (void *InstancePtr);
|
||||
|
||||
/**
|
||||
* This data type defines an exception handler for a processor.
|
||||
* The argument points to the instance of the component
|
||||
*/
|
||||
typedef void (*XExceptionHandler) (void *InstancePtr);
|
||||
|
||||
/**
|
||||
* UPPER_32_BITS - return bits 32-63 of a number
|
||||
* @n: the number we're accessing
|
||||
*
|
||||
* A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
|
||||
* the "right shift count >= width of type" warning when that quantity is
|
||||
* 32-bits.
|
||||
*/
|
||||
#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
|
||||
|
||||
/**
|
||||
* LOWER_32_BITS - return bits 0-31 of a number
|
||||
* @n: the number we're accessing
|
||||
*/
|
||||
#define LOWER_32_BITS(n) ((u32)(n))
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
#ifndef TRUE
|
||||
#define TRUE 1U
|
||||
#endif
|
||||
|
||||
#ifndef FALSE
|
||||
#define FALSE 0U
|
||||
#endif
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL 0U
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
+475
@@ -0,0 +1,475 @@
|
||||
/* Definition for CPU ID */
|
||||
#define XPAR_CPU_ID 0
|
||||
|
||||
/* Definitions for peripheral PS7_CORTEXA9_0 */
|
||||
#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_CORTEXA9_0 */
|
||||
#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
#include "xparameters_ps.h"
|
||||
|
||||
#define STDIN_BASEADDRESS 0xE0001000
|
||||
#define STDOUT_BASEADDRESS 0xE0001000
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver CANPS */
|
||||
#define XPAR_XCANPS_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral PS7_CAN_0 */
|
||||
#define XPAR_PS7_CAN_0_DEVICE_ID 0
|
||||
#define XPAR_PS7_CAN_0_BASEADDR 0xE0008000
|
||||
#define XPAR_PS7_CAN_0_HIGHADDR 0xE0008FFF
|
||||
#define XPAR_PS7_CAN_0_CAN_CLK_FREQ_HZ 23809523
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_CAN_0 */
|
||||
#define XPAR_XCANPS_0_DEVICE_ID XPAR_PS7_CAN_0_DEVICE_ID
|
||||
#define XPAR_XCANPS_0_BASEADDR 0xE0008000
|
||||
#define XPAR_XCANPS_0_HIGHADDR 0xE0008FFF
|
||||
#define XPAR_XCANPS_0_CAN_CLK_FREQ_HZ 23809523
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_DDR_0 */
|
||||
#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
|
||||
#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver DEVCFG */
|
||||
#define XPAR_XDCFG_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral PS7_DEV_CFG_0 */
|
||||
#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0
|
||||
#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000
|
||||
#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_DEV_CFG_0 */
|
||||
#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
|
||||
#define XPAR_XDCFG_0_BASEADDR 0xF8007000
|
||||
#define XPAR_XDCFG_0_HIGHADDR 0xF80070FF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver DMAPS */
|
||||
#define XPAR_XDMAPS_NUM_INSTANCES 2
|
||||
|
||||
/* Definitions for peripheral PS7_DMA_NS */
|
||||
#define XPAR_PS7_DMA_NS_DEVICE_ID 0
|
||||
#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000
|
||||
#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_DMA_S */
|
||||
#define XPAR_PS7_DMA_S_DEVICE_ID 1
|
||||
#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000
|
||||
#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_DMA_NS */
|
||||
#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID
|
||||
#define XPAR_XDMAPS_0_BASEADDR 0xF8004000
|
||||
#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF
|
||||
|
||||
/* Canonical definitions for peripheral PS7_DMA_S */
|
||||
#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID
|
||||
#define XPAR_XDMAPS_1_BASEADDR 0xF8003000
|
||||
#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver EMACPS */
|
||||
#define XPAR_XEMACPS_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral PS7_ETHERNET_0 */
|
||||
#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0
|
||||
#define XPAR_PS7_ETHERNET_0_BASEADDR 0xE000B000
|
||||
#define XPAR_PS7_ETHERNET_0_HIGHADDR 0xE000BFFF
|
||||
#define XPAR_PS7_ETHERNET_0_ENET_CLK_FREQ_HZ 25000000
|
||||
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 8
|
||||
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1
|
||||
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 8
|
||||
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5
|
||||
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8
|
||||
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_ETHERNET_0 */
|
||||
#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID
|
||||
#define XPAR_XEMACPS_0_BASEADDR 0xE000B000
|
||||
#define XPAR_XEMACPS_0_HIGHADDR 0xE000BFFF
|
||||
#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 25000000
|
||||
#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 8
|
||||
#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
|
||||
#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 8
|
||||
#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5
|
||||
#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8
|
||||
#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_AFI_0 */
|
||||
#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000
|
||||
#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_AFI_1 */
|
||||
#define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000
|
||||
#define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_AFI_2 */
|
||||
#define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000
|
||||
#define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_AFI_3 */
|
||||
#define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000
|
||||
#define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_DDRC_0 */
|
||||
#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
|
||||
#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_GLOBALTIMER_0 */
|
||||
#define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200
|
||||
#define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_GPV_0 */
|
||||
#define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000
|
||||
#define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_INTC_DIST_0 */
|
||||
#define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000
|
||||
#define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */
|
||||
#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
|
||||
#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_L2CACHEC_0 */
|
||||
#define XPAR_PS7_L2CACHEC_0_S_AXI_BASEADDR 0xF8F02000
|
||||
#define XPAR_PS7_L2CACHEC_0_S_AXI_HIGHADDR 0xF8F02FFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_OCMC_0 */
|
||||
#define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000
|
||||
#define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_PL310_0 */
|
||||
#define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000
|
||||
#define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_PMU_0 */
|
||||
#define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000
|
||||
#define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF
|
||||
#define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000
|
||||
#define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_QSPI_LINEAR_0 */
|
||||
#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
|
||||
#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFCFFFFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_RAM_0 */
|
||||
#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000
|
||||
#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_RAM_1 */
|
||||
#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000
|
||||
#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_SCUC_0 */
|
||||
#define XPAR_PS7_SCUC_0_S_AXI_BASEADDR 0xF8F00000
|
||||
#define XPAR_PS7_SCUC_0_S_AXI_HIGHADDR 0xF8F000FC
|
||||
|
||||
|
||||
/* Definitions for peripheral PS7_SLCR_0 */
|
||||
#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
|
||||
#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver GPIOPS */
|
||||
#define XPAR_XGPIOPS_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral PS7_GPIO_0 */
|
||||
#define XPAR_PS7_GPIO_0_DEVICE_ID 0
|
||||
#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
|
||||
#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_GPIO_0 */
|
||||
#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
|
||||
#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
|
||||
#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver IICPS */
|
||||
#define XPAR_XIICPS_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral PS7_I2C_0 */
|
||||
#define XPAR_PS7_I2C_0_DEVICE_ID 0
|
||||
#define XPAR_PS7_I2C_0_BASEADDR 0xE0004000
|
||||
#define XPAR_PS7_I2C_0_HIGHADDR 0xE0004FFF
|
||||
#define XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ 111111115
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_I2C_0 */
|
||||
#define XPAR_XIICPS_0_DEVICE_ID XPAR_PS7_I2C_0_DEVICE_ID
|
||||
#define XPAR_XIICPS_0_BASEADDR 0xE0004000
|
||||
#define XPAR_XIICPS_0_HIGHADDR 0xE0004FFF
|
||||
#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 111111115
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver QSPIPS */
|
||||
#define XPAR_XQSPIPS_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral PS7_QSPI_0 */
|
||||
#define XPAR_PS7_QSPI_0_DEVICE_ID 0
|
||||
#define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000
|
||||
#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF
|
||||
#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000
|
||||
#define XPAR_PS7_QSPI_0_QSPI_MODE 0
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_QSPI_0 */
|
||||
#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID
|
||||
#define XPAR_XQSPIPS_0_BASEADDR 0xE000D000
|
||||
#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF
|
||||
#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000
|
||||
#define XPAR_XQSPIPS_0_QSPI_MODE 0
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver SCUGIC */
|
||||
#define XPAR_XSCUGIC_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral PS7_SCUGIC_0 */
|
||||
#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0
|
||||
#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100
|
||||
#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FF
|
||||
#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_SCUGIC_0 */
|
||||
#define XPAR_SCUGIC_0_DEVICE_ID 0
|
||||
#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100
|
||||
#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FF
|
||||
#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver SCUTIMER */
|
||||
#define XPAR_XSCUTIMER_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral PS7_SCUTIMER_0 */
|
||||
#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0
|
||||
#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600
|
||||
#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_SCUTIMER_0 */
|
||||
#define XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID
|
||||
#define XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600
|
||||
#define XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver SCUWDT */
|
||||
#define XPAR_XSCUWDT_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral PS7_SCUWDT_0 */
|
||||
#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0
|
||||
#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620
|
||||
#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_SCUWDT_0 */
|
||||
#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID
|
||||
#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620
|
||||
#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver SDPS */
|
||||
#define XPAR_XSDPS_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral PS7_SD_0 */
|
||||
#define XPAR_PS7_SD_0_DEVICE_ID 0
|
||||
#define XPAR_PS7_SD_0_BASEADDR 0xE0100000
|
||||
#define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF
|
||||
#define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000
|
||||
#define XPAR_PS7_SD_0_HAS_CD 1
|
||||
#define XPAR_PS7_SD_0_HAS_WP 1
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_SD_0 */
|
||||
#define XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID
|
||||
#define XPAR_XSDPS_0_BASEADDR 0xE0100000
|
||||
#define XPAR_XSDPS_0_HIGHADDR 0xE0100FFF
|
||||
#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000
|
||||
#define XPAR_XSDPS_0_HAS_CD 1
|
||||
#define XPAR_XSDPS_0_HAS_WP 1
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver TTCPS */
|
||||
#define XPAR_XTTCPS_NUM_INSTANCES 3
|
||||
|
||||
/* Definitions for peripheral PS7_TTC_0 */
|
||||
#define XPAR_PS7_TTC_0_DEVICE_ID 0
|
||||
#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000
|
||||
#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115
|
||||
#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0
|
||||
#define XPAR_PS7_TTC_1_DEVICE_ID 1
|
||||
#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004
|
||||
#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115
|
||||
#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0
|
||||
#define XPAR_PS7_TTC_2_DEVICE_ID 2
|
||||
#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008
|
||||
#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115
|
||||
#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_TTC_0 */
|
||||
#define XPAR_XTTCPS_0_DEVICE_ID XPAR_PS7_TTC_0_DEVICE_ID
|
||||
#define XPAR_XTTCPS_0_BASEADDR 0xF8001000
|
||||
#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 111111115
|
||||
#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0
|
||||
|
||||
#define XPAR_XTTCPS_1_DEVICE_ID XPAR_PS7_TTC_1_DEVICE_ID
|
||||
#define XPAR_XTTCPS_1_BASEADDR 0xF8001004
|
||||
#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 111111115
|
||||
#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0
|
||||
|
||||
#define XPAR_XTTCPS_2_DEVICE_ID XPAR_PS7_TTC_2_DEVICE_ID
|
||||
#define XPAR_XTTCPS_2_BASEADDR 0xF8001008
|
||||
#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 111111115
|
||||
#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver UARTPS */
|
||||
#define XPAR_XUARTPS_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral PS7_UART_1 */
|
||||
#define XPAR_PS7_UART_1_DEVICE_ID 0
|
||||
#define XPAR_PS7_UART_1_BASEADDR 0xE0001000
|
||||
#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
|
||||
#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 50000000
|
||||
#define XPAR_PS7_UART_1_HAS_MODEM 0
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_UART_1 */
|
||||
#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID
|
||||
#define XPAR_XUARTPS_0_BASEADDR 0xE0001000
|
||||
#define XPAR_XUARTPS_0_HIGHADDR 0xE0001FFF
|
||||
#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 50000000
|
||||
#define XPAR_XUARTPS_0_HAS_MODEM 0
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver USBPS */
|
||||
#define XPAR_XUSBPS_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral PS7_USB_0 */
|
||||
#define XPAR_PS7_USB_0_DEVICE_ID 0
|
||||
#define XPAR_PS7_USB_0_BASEADDR 0xE0002000
|
||||
#define XPAR_PS7_USB_0_HIGHADDR 0xE0002FFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_USB_0 */
|
||||
#define XPAR_XUSBPS_0_DEVICE_ID XPAR_PS7_USB_0_DEVICE_ID
|
||||
#define XPAR_XUSBPS_0_BASEADDR 0xE0002000
|
||||
#define XPAR_XUSBPS_0_HIGHADDR 0xE0002FFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver XADCPS */
|
||||
#define XPAR_XADCPS_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral PS7_XADC_0 */
|
||||
#define XPAR_PS7_XADC_0_DEVICE_ID 0
|
||||
#define XPAR_PS7_XADC_0_BASEADDR 0xF8007100
|
||||
#define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_XADC_0 */
|
||||
#define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID
|
||||
#define XPAR_XADCPS_0_BASEADDR 0xF8007100
|
||||
#define XPAR_XADCPS_0_HIGHADDR 0xF8007120
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
+333
@@ -0,0 +1,333 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file xparameters_ps.h
|
||||
*
|
||||
* This file contains the address definitions for the hard peripherals
|
||||
* attached to the ARM Cortex A9 core.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ------- -------- ---------------------------------------------------
|
||||
* 1.00a ecm/sdm 02/01/10 Initial version
|
||||
* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through
|
||||
* driver tcl
|
||||
* 5.0 pkp 01/16/15 Added interrupt ID definition of ttc for TEST APP
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* None.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _XPARAMETERS_PS_H_
|
||||
#define _XPARAMETERS_PS_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/*
|
||||
* This block contains constant declarations for the peripherals
|
||||
* within the hardblock
|
||||
*/
|
||||
|
||||
/* Canonical definitions for DDR MEMORY */
|
||||
#define XPAR_DDR_MEM_BASEADDR 0x00000000U
|
||||
#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
|
||||
|
||||
/* Canonical definitions for Interrupts */
|
||||
#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
|
||||
#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
|
||||
#define XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID
|
||||
#define XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID
|
||||
#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
|
||||
#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
|
||||
#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
|
||||
#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
|
||||
#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
|
||||
#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
|
||||
#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
|
||||
#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
|
||||
#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
|
||||
#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
|
||||
#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
|
||||
#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
|
||||
#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
|
||||
#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
|
||||
#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID
|
||||
#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
|
||||
#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID
|
||||
#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID
|
||||
#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
|
||||
#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
|
||||
#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
|
||||
#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
|
||||
#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
|
||||
#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
|
||||
#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID
|
||||
#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID
|
||||
#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID
|
||||
#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID
|
||||
#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID
|
||||
#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID
|
||||
#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID
|
||||
#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID
|
||||
#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID
|
||||
|
||||
|
||||
#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR
|
||||
#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR
|
||||
|
||||
|
||||
|
||||
/* Canonical definitions for DMAC */
|
||||
|
||||
|
||||
/* Canonical definitions for WDT */
|
||||
|
||||
/* Canonical definitions for SLCR */
|
||||
#define XPAR_XSLCR_NUM_INSTANCES 1U
|
||||
#define XPAR_XSLCR_0_DEVICE_ID 0U
|
||||
#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR
|
||||
|
||||
/* Canonical definitions for SCU GIC */
|
||||
#define XPAR_SCUGIC_NUM_INSTANCES 1U
|
||||
#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
|
||||
#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000100U)
|
||||
#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
|
||||
#define XPAR_SCUGIC_ACK_BEFORE 0U
|
||||
|
||||
/* Canonical definitions for Global Timer */
|
||||
#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1U
|
||||
#define XPAR_GLOBAL_TMR_DEVICE_ID 0U
|
||||
#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000200U)
|
||||
#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID
|
||||
|
||||
|
||||
/* Xilinx Parallel Flash Library (XilFlash) User Settings */
|
||||
#define XPAR_AXI_EMC
|
||||
|
||||
|
||||
#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
|
||||
|
||||
|
||||
/*
|
||||
* This block contains constant declarations for the peripherals
|
||||
* within the hardblock. These have been put for bacwards compatibilty
|
||||
*/
|
||||
|
||||
#define XPS_PERIPHERAL_BASEADDR 0xE0000000U
|
||||
#define XPS_UART0_BASEADDR 0xE0000000U
|
||||
#define XPS_UART1_BASEADDR 0xE0001000U
|
||||
#define XPS_USB0_BASEADDR 0xE0002000U
|
||||
#define XPS_USB1_BASEADDR 0xE0003000U
|
||||
#define XPS_I2C0_BASEADDR 0xE0004000U
|
||||
#define XPS_I2C1_BASEADDR 0xE0005000U
|
||||
#define XPS_SPI0_BASEADDR 0xE0006000U
|
||||
#define XPS_SPI1_BASEADDR 0xE0007000U
|
||||
#define XPS_CAN0_BASEADDR 0xE0008000U
|
||||
#define XPS_CAN1_BASEADDR 0xE0009000U
|
||||
#define XPS_GPIO_BASEADDR 0xE000A000U
|
||||
#define XPS_GEM0_BASEADDR 0xE000B000U
|
||||
#define XPS_GEM1_BASEADDR 0xE000C000U
|
||||
#define XPS_QSPI_BASEADDR 0xE000D000U
|
||||
#define XPS_PARPORT_CRTL_BASEADDR 0xE000E000U
|
||||
#define XPS_SDIO0_BASEADDR 0xE0100000U
|
||||
#define XPS_SDIO1_BASEADDR 0xE0101000U
|
||||
#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000U
|
||||
#define XPS_NAND_BASEADDR 0xE1000000U
|
||||
#define XPS_PARPORT0_BASEADDR 0xE2000000U
|
||||
#define XPS_PARPORT1_BASEADDR 0xE4000000U
|
||||
#define XPS_QSPI_LINEAR_BASEADDR 0xFC000000U
|
||||
#define XPS_SYS_CTRL_BASEADDR 0xF8000000U /* AKA SLCR */
|
||||
#define XPS_TTC0_BASEADDR 0xF8001000U
|
||||
#define XPS_TTC1_BASEADDR 0xF8002000U
|
||||
#define XPS_DMAC0_SEC_BASEADDR 0xF8003000U
|
||||
#define XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000U
|
||||
#define XPS_WDT_BASEADDR 0xF8005000U
|
||||
#define XPS_DDR_CTRL_BASEADDR 0xF8006000U
|
||||
#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000U
|
||||
#define XPS_AFI0_BASEADDR 0xF8008000U
|
||||
#define XPS_AFI1_BASEADDR 0xF8009000U
|
||||
#define XPS_AFI2_BASEADDR 0xF800A000U
|
||||
#define XPS_AFI3_BASEADDR 0xF800B000U
|
||||
#define XPS_OCM_BASEADDR 0xF800C000U
|
||||
#define XPS_EFUSE_BASEADDR 0xF800D000U
|
||||
#define XPS_CORESIGHT_BASEADDR 0xF8800000U
|
||||
#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000U
|
||||
#define XPS_SCU_PERIPH_BASE 0xF8F00000U
|
||||
#define XPS_L2CC_BASEADDR 0xF8F02000U
|
||||
#define XPS_SAM_RAM_BASEADDR 0xFFFC0000U
|
||||
#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000U
|
||||
#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000U
|
||||
#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000U
|
||||
#define XPS_PERIPH_APB_BASEADDR 0xF8000000U
|
||||
|
||||
/* Shared Peripheral Interrupts (SPI) */
|
||||
#define XPS_CORE_PARITY0_INT_ID 32U
|
||||
#define XPS_CORE_PARITY1_INT_ID 33U
|
||||
#define XPS_L2CC_INT_ID 34U
|
||||
#define XPS_OCMINTR_INT_ID 35U
|
||||
#define XPS_ECC_INT_ID 36U
|
||||
#define XPS_PMU0_INT_ID 37U
|
||||
#define XPS_PMU1_INT_ID 38U
|
||||
#define XPS_SYSMON_INT_ID 39U
|
||||
#define XPS_DVC_INT_ID 40U
|
||||
#define XPS_WDT_INT_ID 41U
|
||||
#define XPS_TTC0_0_INT_ID 42U
|
||||
#define XPS_TTC0_1_INT_ID 43U
|
||||
#define XPS_TTC0_2_INT_ID 44U
|
||||
#define XPS_DMA0_ABORT_INT_ID 45U
|
||||
#define XPS_DMA0_INT_ID 46U
|
||||
#define XPS_DMA1_INT_ID 47U
|
||||
#define XPS_DMA2_INT_ID 48U
|
||||
#define XPS_DMA3_INT_ID 49U
|
||||
#define XPS_SMC_INT_ID 50U
|
||||
#define XPS_QSPI_INT_ID 51U
|
||||
#define XPS_GPIO_INT_ID 52U
|
||||
#define XPS_USB0_INT_ID 53U
|
||||
#define XPS_GEM0_INT_ID 54U
|
||||
#define XPS_GEM0_WAKE_INT_ID 55U
|
||||
#define XPS_SDIO0_INT_ID 56U
|
||||
#define XPS_I2C0_INT_ID 57U
|
||||
#define XPS_SPI0_INT_ID 58U
|
||||
#define XPS_UART0_INT_ID 59U
|
||||
#define XPS_CAN0_INT_ID 60U
|
||||
#define XPS_FPGA0_INT_ID 61U
|
||||
#define XPS_FPGA1_INT_ID 62U
|
||||
#define XPS_FPGA2_INT_ID 63U
|
||||
#define XPS_FPGA3_INT_ID 64U
|
||||
#define XPS_FPGA4_INT_ID 65U
|
||||
#define XPS_FPGA5_INT_ID 66U
|
||||
#define XPS_FPGA6_INT_ID 67U
|
||||
#define XPS_FPGA7_INT_ID 68U
|
||||
#define XPS_TTC1_0_INT_ID 69U
|
||||
#define XPS_TTC1_1_INT_ID 70U
|
||||
#define XPS_TTC1_2_INT_ID 71U
|
||||
#define XPS_DMA4_INT_ID 72U
|
||||
#define XPS_DMA5_INT_ID 73U
|
||||
#define XPS_DMA6_INT_ID 74U
|
||||
#define XPS_DMA7_INT_ID 75U
|
||||
#define XPS_USB1_INT_ID 76U
|
||||
#define XPS_GEM1_INT_ID 77U
|
||||
#define XPS_GEM1_WAKE_INT_ID 78U
|
||||
#define XPS_SDIO1_INT_ID 79U
|
||||
#define XPS_I2C1_INT_ID 80U
|
||||
#define XPS_SPI1_INT_ID 81U
|
||||
#define XPS_UART1_INT_ID 82U
|
||||
#define XPS_CAN1_INT_ID 83U
|
||||
#define XPS_FPGA8_INT_ID 84U
|
||||
#define XPS_FPGA9_INT_ID 85U
|
||||
#define XPS_FPGA10_INT_ID 86U
|
||||
#define XPS_FPGA11_INT_ID 87U
|
||||
#define XPS_FPGA12_INT_ID 88U
|
||||
#define XPS_FPGA13_INT_ID 89U
|
||||
#define XPS_FPGA14_INT_ID 90U
|
||||
#define XPS_FPGA15_INT_ID 91U
|
||||
|
||||
/* Private Peripheral Interrupts (PPI) */
|
||||
#define XPS_GLOBAL_TMR_INT_ID 27U /* SCU Global Timer interrupt */
|
||||
#define XPS_FIQ_INT_ID 28U /* FIQ from FPGA fabric */
|
||||
#define XPS_SCU_TMR_INT_ID 29U /* SCU Private Timer interrupt */
|
||||
#define XPS_SCU_WDT_INT_ID 30U /* SCU Private WDT interrupt */
|
||||
#define XPS_IRQ_INT_ID 31U /* IRQ from FPGA fabric */
|
||||
|
||||
|
||||
/* REDEFINES for TEST APP */
|
||||
/* Definitions for UART */
|
||||
#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID
|
||||
#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID
|
||||
#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID
|
||||
#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID
|
||||
#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID
|
||||
#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID
|
||||
#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID
|
||||
#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID
|
||||
#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID
|
||||
#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID
|
||||
#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID
|
||||
#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID
|
||||
#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
|
||||
#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID
|
||||
#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
|
||||
#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID
|
||||
#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID
|
||||
#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
|
||||
#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
|
||||
#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID
|
||||
#define XPAR_PS7_TTC_0_INTR XPS_TTC0_0_INT_ID
|
||||
#define XPAR_PS7_TTC_1_INTR XPS_TTC0_1_INT_ID
|
||||
#define XPAR_PS7_TTC_2_INTR XPS_TTC0_2_INT_ID
|
||||
#define XPAR_PS7_TTC_3_INTR XPS_TTC1_0_INT_ID
|
||||
#define XPAR_PS7_TTC_4_INTR XPS_TTC1_1_INT_ID
|
||||
#define XPAR_PS7_TTC_5_INTR XPS_TTC1_2_INT_ID
|
||||
|
||||
#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
|
||||
|
||||
/* For backwards compatibilty */
|
||||
#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
|
||||
#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
|
||||
#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
|
||||
#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
|
||||
#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
|
||||
#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
|
||||
#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
|
||||
#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
|
||||
#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
|
||||
#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
|
||||
|
||||
#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
|
||||
|
||||
#ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
|
||||
#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
|
||||
#endif
|
||||
|
||||
#ifdef XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
|
||||
#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
|
||||
#endif
|
||||
|
||||
#define XPAR_SCUTIMER_DEVICE_ID 0U
|
||||
#define XPAR_SCUWDT_DEVICE_ID 0U
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* protection macro */
|
||||
+95
@@ -0,0 +1,95 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file xil-crt0.S
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- ---------------------------------------------------
|
||||
* 1.00a ecm 10/20/09 Initial version
|
||||
* 3.05a sdm 02/02/12 Added code for profiling
|
||||
* 3.06a sgd 05/16/12 Added global constructors and cleanup code
|
||||
* Uart initialization based on compiler flag
|
||||
* 3.07a sgd 07/05/12 Updated with reset and start Global Timer
|
||||
* 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with build option
|
||||
* 4.2 pkp 08/04/14 Removed PEEP board related code which contained
|
||||
* initialization of uart smc nor and sram
|
||||
* 5.3 pkp 10/07/15 Added support for OpenAMP by not initializing global
|
||||
* timer when USE_AMP flag is defined
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* None.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
.file "xil-crt0.S"
|
||||
.section ".got2","aw"
|
||||
.align 2
|
||||
|
||||
.text
|
||||
.Lstack:
|
||||
.long stacks_top
|
||||
|
||||
|
||||
.globl _start
|
||||
_start:
|
||||
bl __cpu_init /* Initialize the CPU first (BSP provides this) */
|
||||
|
||||
mov r0, #0
|
||||
|
||||
ldr r13, .Lstack /* stack address */
|
||||
|
||||
/* Reset and start Global Timer */
|
||||
mov r0, #0x0
|
||||
mov r1, #0x0
|
||||
|
||||
@ #if USE_AMP != 1
|
||||
@ bl XTime_SetTime
|
||||
@ #endif
|
||||
|
||||
/* make sure argc and argv are valid */
|
||||
mov r0, #0
|
||||
mov r1, #0
|
||||
|
||||
/* Let her rip */
|
||||
bl bootmain
|
||||
|
||||
/* All done */
|
||||
b .
|
||||
|
||||
.Lstart:
|
||||
.size _start,.Lstart-_start
|
||||
+114
@@ -0,0 +1,114 @@
|
||||
/*******************************************************************/
|
||||
/* */
|
||||
/* This file is automatically generated by linker script generator.*/
|
||||
/* */
|
||||
/* Version: */
|
||||
/* */
|
||||
/* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */
|
||||
/* */
|
||||
/* Description : Cortex-A9 Linker Script */
|
||||
/* */
|
||||
/*******************************************************************/
|
||||
|
||||
/* Define Memories in the system */
|
||||
BOOT_STACK_SIZE = 0x4000;
|
||||
RAM_VECTORS_SIZE = 72;
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
ddr3 (rwx) : ORIGIN = 0x00100000, LENGTH = 0x3FF00000
|
||||
virt_ddr3 (WRX) : ORIGIN = 0xA0010000, LENGTH = 0x3FF00000
|
||||
}
|
||||
|
||||
/* Specify the default entry point to the program */
|
||||
|
||||
ENTRY(_boot_start)
|
||||
|
||||
/* Define the sections, and where they are mapped in memory */
|
||||
SECTIONS
|
||||
{
|
||||
. = ORIGIN(ddr3);
|
||||
. = ALIGN(4);
|
||||
|
||||
_start_image_addr = .;
|
||||
|
||||
.start_sec : {
|
||||
. = ALIGN(0x1000);
|
||||
|
||||
*(.vectors)
|
||||
|
||||
/* read only area. */
|
||||
boot.o(.text)
|
||||
xil-crt0.o(.text .text.*)
|
||||
cpu_init.o(.text .text.*)
|
||||
bootmmu.o(.text .text.*)
|
||||
|
||||
boot.o(.rodata .rodata.*)
|
||||
xil-crt0.o(.rodata .rodata.*)
|
||||
cpu_init.o(.rodata .rodata.*)
|
||||
bootmmu.o(.rodata .rodata.*)
|
||||
|
||||
/* already initialized to zero. */
|
||||
boot.o(.data .data.*)
|
||||
xil-crt0.o(.data .data.*)
|
||||
cpu_init.o(.data .data.*)
|
||||
bootmmu.o(.data .data.*)
|
||||
|
||||
/* initialization start checkpoint. */
|
||||
PROVIDE(boot_start_addr = .);
|
||||
|
||||
boot.o(.bss .bss.* COMMON)
|
||||
xil-crt0.o(.bss .bss.* COMMON)
|
||||
cpu_init.o(.bss .bss.* COMMON)
|
||||
bootmmu.o(.bss .bss.* COMMON)
|
||||
|
||||
/* stack for booting code. */
|
||||
. = ALIGN(0x1000);
|
||||
PROVIDE(stacks_start = .);
|
||||
. += BOOT_STACK_SIZE;
|
||||
PROVIDE(stacks_end = .);
|
||||
PROVIDE(stacks_top = .);
|
||||
|
||||
/* initialization end checkpoint. */
|
||||
PROVIDE(boot_end_addr = .);
|
||||
} > ddr3
|
||||
|
||||
/* Other Kernel code is placed over 0x80000000 + 128KB. */
|
||||
.text : AT(0x00110000) {
|
||||
*(.vectors)
|
||||
. = ALIGN(0x1000);
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
} > virt_ddr3
|
||||
|
||||
. = ALIGN(0x1000);
|
||||
/* Other Kernel code text checkpoint. */
|
||||
PROVIDE(kern_text = .);
|
||||
|
||||
.data : {
|
||||
*(.data .data.*)
|
||||
/* user app */
|
||||
. = ALIGN(0x1000);
|
||||
PROVIDE(_binary_fs_img_start = .);
|
||||
*(.rawdata_fs_img*)
|
||||
PROVIDE(_binary_fs_img_end = .);
|
||||
PROVIDE(_binary_init_start = .);
|
||||
*(.rawdata_init*)
|
||||
PROVIDE(_binary_init_end = .);
|
||||
PROVIDE(_binary_default_fs_start = .);
|
||||
*(.rawdata_memfs*)
|
||||
PROVIDE(_binary_default_fs_end = .);
|
||||
} > virt_ddr3
|
||||
|
||||
PROVIDE(kernel_data_begin = .);
|
||||
|
||||
_image_size = . - 0xA0000000;
|
||||
|
||||
.bss : {
|
||||
PROVIDE(__bss_start__ = .);
|
||||
*(.bss .bss.* COMMON)
|
||||
PROVIDE(__bss_end__ = .);
|
||||
} > virt_ddr3
|
||||
. = ALIGN(0x1000);
|
||||
PROVIDE(kernel_data_end = .);
|
||||
}
|
||||
Reference in New Issue
Block a user