Add ch569w arch and board codes, support for uart

2025-04-07 18:18:51 +08:00
parent 0fa8ff5368
commit 5e331e4c7c
36 changed files with 2281 additions and 3 deletions
@@ -0,0 +1,31 @@
+mainmenu "XiZi_IIoT Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config KERNEL_DIR
+    string
+    option env="KERNEL_ROOT"
+    default "../.."
+
+config BOARD_CH569W
+    bool
+    select ARCH_RISCV
+    default y  
+
+source "$KERNEL_DIR/arch/Kconfig"
+
+menu "ch569w feature"
+    source "$BSP_DIR/third_party_driver/Kconfig"
+endmenu
+
+
+menu "Hardware feature"
+    source "$KERNEL_DIR/resources/Kconfig"
+endmenu
+
+source "$KERNEL_DIR/Kconfig"
+
+
@@ -0,0 +1,6 @@
+SRC_FILES := board.c
+
+SRC_DIR := third_party_driver 
+
+
+include $(KERNEL_ROOT)/compiler.mk
@@ -0,0 +1,78 @@
+# 1. 简介
+
+| 硬件      | 描述                                      |
+| --------- | ----------------------------------------- |
+| 芯片型号  | CH569W                                    |
+| CPU       | 单核RISC-V3A                              |
+| 主频      | 120MHz                                    |
+| 片内SRAM  | 32/64/96KB 可配置的 128 位宽 SRAM（RAMX） |
+| 片内FLASH | 448KB 用户应用程序存储区 CodeFlash        |
+| 外设      | UART等                                    |
+
+# 2. 克隆代码
+
+将XiUOS的源代码克隆下来：
+
+```bash
+git clone https://gitlink.org.cn/xuos/xiuos.git
+```
+
+# 3. 下载编译工具链
+
+编译环境：Ubuntu 20.04.6 LTS
+
+编译工具链：riscv-none-embed-gcc（xpack-riscv-none-embed-gcc-8.2.0-3.1）
+
+编译工具链可到Github进行下载：https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack/releases/download/v8.2.0-3.1/xpack-riscv-none-embed-gcc-8.2.0-3.1-linux-x64.tgz
+
+下载完成后将其移动到`/opt`目录下，并进行解压：
+
+```bash
+sudo tar -xvzf xpack-riscv-none-embed-gcc-8.2.0-3.1-linux-x64.tgz
+```
+
+# 4. 编译
+
+## 方式1（推荐）
+
+可以在`Ubiquitous/XiZi_IIoT`目录下创建文件`script.sh`，内容如下：
+
+```sh
+#! /bin/env sh
+export CROSS_COMPILE=/opt/xPacks/riscv-none-embed-gcc/8.2.0-3.1/bin/riscv-none-embed-
+make BOARD=ch569w distclean # 将之前的编译生成文件清空
+make BOARD=ch569w menuconfig
+make BOARD=ch569w
+```
+
+创建之后，在命令行移动到`XiZi-IIOT`目录下，键入`./script`运行该脚本。
+
+经过Kconfig配置、编译后，即可在`Ubiquitous/XiZi_IIoT/build`目录中生成`XiZi-ch569w.bin`文件，将该文件拷贝至Windows侧待下一步进行烧录。
+
+> [!CAUTION]
+>
+> 如果`make BOARD=ch569w menuconfig`显示【无法找到`kconfig-mconf`】，需要先安装`ncurses-devel`和`kconfig-mconf`，如下：
+>
+> ```bash
+> sudo apt install libncurses5-dev kconfig-frontends
+
+
+
+# 5. 烧录
+
+1. 沁恒微电子官网下载 WCHISPTool.exe 工具进行 bin 文件下载到芯片 flash 的操作。CH569W 芯片需要进入下载模式才能使用 ISP 工具下载代码，一般使用 USB 方式下载代码最为方便。
+2. 将 CH569W 评估板使用 USB 插头对插头线和计算机连接起来。如图，打开 ISP 下载工具，芯片信号选择 CH569，下载方式选择 USB，将 CH569W 评估板断电，然后将下载配置脚（出厂默认为 PA5，原理图上的HD0）接地后对评估板上电，此时 ISP 工具的 USB 设备列表中将显示新连上来的 CH569W 芯片。最后点击“下载”，即可使程序下载到评估版上的主芯片。
+
+<img src="imgs/image_shaolukaifabanpaizhao.jpg" alt="image_shaolukaifabanpaizhao" style="zoom:30%;" />
+
+<img src="imgs/image_shaoluruanjianjietu.png" alt="image_shaoluruanjianjietu" style="zoom:50%;" />
+
+
+
+# 6. 启动
+
+烧录完成后，并且将串口连接至电脑。
+
+将评估板上电重新，即可看到操作系统启动的信息，如下：
+
+![image_xitongqidongrizhi](imgs/image_xitongqidongrizhi.png)
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2020 AIIT XUOS Lab
+ * XiUOS is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *        http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ */
+
+/**
+ * @file board.c
+ * @brief support ch569 init configure and start-up
+ * @version 1.0
+ * @author AIIT XUOS Lab
+ * @date 2025-04-07
+ */
+
+#include <device.h>
+#include <stdint.h>
+#include <xizi.h>
+
+#include "CH56x_common.h"
+#include "connect_uart.h"
+#include "board.h"
+
+
+void InitBoardHardware()
+{
+
+	SystemInit(FREQ_SYS);
+	Delay_Init(FREQ_SYS);
+
+    SysTick_Config(FREQ_SYS / 8 / TICK_PER_SECOND);
+    PFIC_EnableIRQ(SWI_IRQn);
+
+    /* initialize memory system */
+    InitBoardMemory(MEMORY_START_ADDRESS, (void *)MEMORY_END_ADDRESS);
+
+#ifdef BSP_USING_UART
+    InitHwUart();
+    InstallConsole("uart1", SERIAL_DRV_NAME_1, SERIAL_1_DEVICE_NAME_0);
+    KPrintf("\nconsole init completed.\n");
+#endif
+
+    KPrintf("memory address range: [0x%08x - 0x%08x] ssize: %x\n", (x_ubase)MEMORY_START_ADDRESS,
+            (x_ubase)MEMORY_END_ADDRESS, MEMORY_STACK_SIZE);
+
+    KPrintf("board init done.\n");
+    KPrintf("start kernel...\n");
+}
@@ -0,0 +1,38 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file board.h
+* @brief define ch569 init configure and start-up function
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2025-04-07
+*/
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <stdint.h>
+#include "CH56xSFR.h"
+
+
+extern uint32_t _ebss;
+extern uint32_t __stack_size;
+
+#define MEMORY_START_ADDRESS    ((void *)&_ebss)
+//#define MEMORY_END_ADDRESS      ((void *)(BA_RAM) + (SZ_RAM))
+#define MEMORY_END_ADDRESS      ((void *)(BA_RAMX) + (SZ_RAMX))
+#define MEMORY_STACK_SIZE    (&__stack_size)
+
+void InitBoardHardware(void);
+
+#endif /* __BOARD_H__ */
@@ -0,0 +1,18 @@
+export MARCH := rv32imac
+
+# export CFLAGS :=  -march=$(MARCH) -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -g
+
+export CFLAGS := -march=rv32imac -mabi=ilp32 -msmall-data-limit=8 -mno-save-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -g -std=gnu99
+export AFLAGS :=  -march=$(MARCH) -mabi=ilp32 -x assembler-with-cpp -ggdb
+export LFLAGS :=  -march=$(MARCH) -mabi=ilp32 -nostartfiles -Wl,--gc-sections,-Map=XiZi-ch569w.map,-cref,-u,_start -T $(BSP_ROOT)/link.ld
+
+export APPLFLAGS :=  -nostartfiles -Wl,--gc-sections,-Map=XiZi-app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
+export CXXFLAGS :=  -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common # -std=gnu99
+
+export DEFINES := -DDEBUG=1
+
+export ARCH = risc-v
+export MCU =  CH569W
+
+
+
@@ -0,0 +1,209 @@
+ENTRY( _start )
+
+__stack_size = 2048;
+
+PROVIDE( _stack_size = __stack_size );
+
+
+MEMORY
+{
+	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 448K
+	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 16K
+	RAMX (xrw) : ORIGIN = 0x20020000, LENGTH = 96K
+}
+
+
+SECTIONS
+{
+	.init :
+	{
+		_sinit = .;
+		. = ALIGN(4);
+		KEEP(*(SORT_NONE(.init)))
+		. = ALIGN(4);
+		_einit = .;
+	} >FLASH AT>FLASH
+	
+    .vector :
+    {
+        *(.vector);
+        . = ALIGN(64);
+    } >FLASH AT>FLASH 
+	
+	.hclib :
+	{
+		. = ALIGN(4);
+		*ISPEM569.o(*)
+		. = ALIGN(4);	
+	}		
+	
+	.text :
+	{
+		. = ALIGN(4);
+		*(.text)
+		*(.text.*)
+		*(.rodata)
+		*(.rodata*)
+		*(.glue_7)
+		*(.glue_7t)
+		*(.gnu.linkonce.t.*)
+		. = ALIGN(4);
+
+		/* section information for  shell */
+		. = ALIGN(4);
+		_shell_command_start = .;
+		KEEP (*(shellCommand))
+		_shell_command_end = .;
+		. = ALIGN(4);
+
+		PROVIDE(__ctors_start__ = .);
+		KEEP (*(SORT(.init_array.*)))
+		KEEP (*(.init_array))
+		PROVIDE(__ctors_end__ = .);
+
+		. = ALIGN(4);
+		__isrtbl_idx_start = .;
+		KEEP(*(.isrtbl.idx))
+		__isrtbl_start = .;
+		KEEP(*(.isrtbl))
+		__isrtbl_end = .;
+		. = ALIGN(4);
+
+		PROVIDE(g_service_table_start = ABSOLUTE(.));
+		KEEP(*(.g_service_table))
+		PROVIDE(g_service_table_end = ABSOLUTE(.));
+
+		*(.gnu.linkonce.t.*)
+	} >FLASH AT>FLASH 
+
+	.fini :
+	{
+		KEEP(*(SORT_NONE(.fini)))
+		. = ALIGN(4);
+	} >FLASH AT>FLASH
+
+	PROVIDE( _etext = . );
+	PROVIDE( _eitcm = . );	
+
+	.preinit_array  :
+	{
+	  PROVIDE_HIDDEN (__preinit_array_start = .);
+	  KEEP (*(.preinit_array))
+	  PROVIDE_HIDDEN (__preinit_array_end = .);
+	} >FLASH AT>FLASH 
+	
+	.init_array     :
+	{
+	  PROVIDE_HIDDEN (__init_array_start = .);
+	  KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+	  KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+	  PROVIDE_HIDDEN (__init_array_end = .);
+	} >FLASH AT>FLASH 
+	
+	.fini_array     :
+	{
+	  PROVIDE_HIDDEN (__fini_array_start = .);
+	  KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+	  KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+	  PROVIDE_HIDDEN (__fini_array_end = .);
+	} >FLASH AT>FLASH 
+	
+	.ctors          :
+	{
+	  /* gcc uses crtbegin.o to find the start of
+	     the constructors, so we make sure it is
+	     first.  Because this is a wildcard, it
+	     doesn't matter if the user does not
+	     actually link against crtbegin.o; the
+	     linker won't look for a file to match a
+	     wildcard.  The wildcard also means that it
+	     doesn't matter which directory crtbegin.o
+	     is in.  */
+	  KEEP (*crtbegin.o(.ctors))
+	  KEEP (*crtbegin?.o(.ctors))
+	  /* We don't want to include the .ctor section from
+	     the crtend.o file until after the sorted ctors.
+	     The .ctor section from the crtend file contains the
+	     end of ctors marker and it must be last */
+	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+	  KEEP (*(SORT(.ctors.*)))
+	  KEEP (*(.ctors))
+	} >FLASH AT>FLASH 
+	
+	.dtors          :
+	{
+	  KEEP (*crtbegin.o(.dtors))
+	  KEEP (*crtbegin?.o(.dtors))
+	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+	  KEEP (*(SORT(.dtors.*)))
+	  KEEP (*(.dtors))
+	} >FLASH AT>FLASH 
+
+	.dalign :
+	{
+		. = ALIGN(4);
+		PROVIDE(_data_vma = .);
+	} >RAMX AT>FLASH	
+
+	.dlalign :
+	{
+		. = ALIGN(4); 
+		PROVIDE(_data_lma = .);
+	} >FLASH AT>FLASH
+
+	.data :
+	{
+    	*(.gnu.linkonce.r.*)
+    	*(.data .data.*)
+    	*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+    	PROVIDE( __global_pointer$ = . + 0x800 );
+    	*(.sdata .sdata.*)
+    	*(.sdata2.*)
+    	*(.gnu.linkonce.s.*)
+    	. = ALIGN(8);
+    	*(.srodata.cst16)
+    	*(.srodata.cst8)
+    	*(.srodata.cst4)
+    	*(.srodata.cst2)
+    	*(.srodata .srodata.*)
+    	. = ALIGN(4);
+		PROVIDE( _edata = .);
+	} >RAMX AT>FLASH
+
+	.bss :
+	{
+		. = ALIGN(4);
+		PROVIDE( _sbss = .);
+  	    *(.sbss*)
+        *(.gnu.linkonce.sb.*)
+		*(.bss*)
+     	*(.gnu.linkonce.b.*)		
+		*(COMMON*)
+		. = ALIGN(4);
+		PROVIDE( _ebss = .);
+	} >RAMX AT>FLASH
+	
+	PROVIDE( _end = _ebss);
+	PROVIDE( end = . );	
+	
+	/*
+	.DMADATA :
+    {
+        . = ALIGN(16);
+        PROVIDE( _dmadata_start = .);
+        *(.dmadata*)
+        *(.dmadata.*)
+        . = ALIGN(16);
+       PROVIDE( _dmadata_end = .);
+    } >RAMX AT>FLASH
+	*/
+
+    .stack ORIGIN(RAMX) + LENGTH(RAMX) - __stack_size :
+    {
+        . = ALIGN(4);
+        PROVIDE(_susrstack = . );
+        . = . + __stack_size;
+        PROVIDE( _eusrstack = .);
+    } >RAMX 
+}
@@ -0,0 +1,7 @@
+menuconfig BSP_USING_UART
+    bool "Using UART device"
+    default y
+    select RESOURCES_SERIAL
+    if BSP_USING_UART
+        source "$BSP_DIR/third_party_driver/uart/Kconfig"
+    endif
@@ -0,0 +1,7 @@
+SRC_DIR := Peripheral
+
+ifeq ($(CONFIG_BSP_USING_UART),y)
+  SRC_DIR += uart
+endif
+
+include $(KERNEL_ROOT)/compiler.mk
@@ -0,0 +1,3 @@
+SRC_DIR := src
+
+include $(KERNEL_ROOT)/compiler.mk
@@ -254,7 +254,7 @@ extern "C" {
 #define RB_SOFTWARE_RESET       0x01                     // WA/WZ, global software reset, high action, auto clear
 #define RB_WDOG_RST_EN          0x02                     // RWA, enable watch-dog reset if watch-dog timer overflow: 0=as timer only, 1=enable reset if timer overflow
 #define RB_WDOG_INT_EN          0x04                     // RWA, watch-dog interrupt enable or INT_ID_WDOG interrupt source selection: 0=software interrupt, 1=from watch-dog timer overflow
-#define RB_WDOG_INT_FLAG        0x10                     // RW1, watch-dog timer overflow interrupt flag, cleared by RW1 or reload watch-dog count
+#define RB_WDOG_INT_FLAG        0x08                     // RW1, watch-dog timer overflow interrupt flag, cleared by RW1 or reload watch-dog count
 #define R8_GLOB_RESET_KEEP      (*((PUINT8V)0x40001007)) // RW, value keeper during global reset

 /* System: clock configuration register */
@@ -0,0 +1,17 @@
+SRC_FILES := \
+	CH56x_bus8.c \
+	CH56x_clk.c \
+	CH56x_dvp.c \
+	CH56x_ecdc.c \
+	CH56x_emmc.c \
+	CH56x_eth.c \
+	CH56x_gpio.c \
+	CH56x_hspi.c \
+	CH56x_pwm.c \
+	CH56x_pwr.c \
+	CH56x_spi.c \
+	CH56x_sys.c \
+	CH56x_timer.c \
+	CH56x_uart.c
+
+include $(KERNEL_ROOT)/compiler.mk
@@ -0,0 +1,178 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_uart.h
+* @brief define rvstar uart function 
+* @version 1.0
+* @author AIIT XUOS Lab
+* @date 2022-08-01
+*/
+
+#ifndef CONNECT_UART_H
+#define CONNECT_UART_H
+
+#include <device.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+union _uart_mcr
+{
+    uint8_t reg;
+    struct
+    {
+        uint8_t dtr         : 1;  // B.0 : RW, DTR output (UART0 only)
+        uint8_t rts         : 1;  // B.1 : RW, RTS output (UART0 only)
+        uint8_t out1        : 1;  // B.2 : RW, user defined modem control (UART0 only)
+        uint8_t int_oe      : 1;  // B.3 : RW, interrupt output enable / OUT2
+        uint8_t loop        : 1;  // B.4 : RW, enable internal loop test (UART0 only)
+        uint8_t au_flow_en  : 1;  // B.5 : RW, enable CTS/RTS autoflow control
+        uint8_t tnow        : 1;  // B.6 : RW, enable DTR TNOW output (UART0 only)
+        uint8_t half        : 1;  // B.7 : RW, enable half-duplex mode (UART0 only)
+    };
+};
+
+union _uart_ier
+{
+    uint8_t reg;
+    struct
+    {
+        uint8_t recv_rdy    : 1;  // B.0 : RW, enable rx data ready intr
+        uint8_t thr_empty   : 1;  // B.1 : RW, enable THR empty intr
+        uint8_t line_stat   : 1;  // B.2 : RW, enable rx line status intr
+        uint8_t modem_chg   : 1;  // B.3 : RW, enable modem status change intr (UART0 only)
+        uint8_t dtr_en      : 1;  // B.4 : RW, DTR/TNOW output pin enable (UART0 only)
+        uint8_t rts_en      : 1;  // B.5 : RW, RTS output pin enable (UART0 only)
+        uint8_t txd_en      : 1;  // B.6 : RW, TXD pin enable
+        uint8_t reset       : 1;  // B.7 : WZ, software reset control, active high, auto clear
+    };
+};
+
+union _uart_fcr
+{
+    uint8_t reg;
+    struct
+    {
+        uint8_t fifo_en     : 1;  // B.0   : RW, FIFO enable
+        uint8_t rx_fifo_clr : 1;  // B.1   : WZ, write 1 to clear rx FIFO, auto clear
+        uint8_t tx_fifo_clr : 1;  // B.2   : WZ, write 1 to clear tx FIFO, auto clear
+        uint8_t resv_3      : 3;
+        uint8_t fifo_trig   : 2;  // B.7-6 : RW, rx FIFO trigger level, 1/2/4/7 bytes
+    };
+};
+
+union _uart_lcr
+{
+    uint8_t reg;
+    struct
+    {
+        uint8_t word_sz     : 2;  // B.1-0 : RW, word bit length, 5/6/7/8 bits
+        uint8_t stop_bit    : 1;  // B.2   : RW, stop bit length, 1/2 bits
+        uint8_t par_en      : 1;  // B.3   : RW, parity enable
+        uint8_t par_mod     : 2;  // B.5-4 : RW, parity mode, odd/even/mark/space
+        uint8_t break_en    : 1;  // B.6   : RW, force BREAK line condition
+        uint8_t dlab        : 1;  // B.7   : RW, user defined general purpose bit
+    };
+};
+
+
+#define LCR_DATA_BITS_5     0
+#define LCR_DATA_BITS_6     1
+#define LCR_DATA_BITS_7     2
+#define LCR_DATA_BITS_8     3
+
+#define LCR_STOP_BITS_1     0
+#define LCR_STOP_BITS_2     1
+
+#define LCR_PARITY_ODD      0
+#define LCR_PARITY_EVEN     1
+#define LCR_PARITY_MARK     2
+#define LCR_PARITY_SPACE    3
+
+union _uart_iir
+{
+    uint8_t reg;
+    struct
+    {
+        uint8_t int_mask    : 4;  // B.3-0 : RO, interrupt mask (intr if B.0 is 0)
+        uint8_t resv_4      : 2;
+        uint8_t fifo_id     : 2;  // B.7-6 : RO, FIFO enabled flag
+    };
+};
+
+
+union _uart_lsr
+{
+    uint8_t reg;
+    struct
+    {
+        uint8_t data_rdy    : 1;  // B.0 : RO, rx FIFO data ready
+        uint8_t over_err    : 1;  // B.1 : RZ, rx FIFO data overrun
+        uint8_t par_err     : 1;  // B.2 : RZ, rx parity error
+        uint8_t frame_err   : 1;  // B.3 : RZ, rx frame error
+        uint8_t break_err   : 1;  // B.4 : RZ, rx BREAK detected
+        uint8_t tx_fifo_emp : 1;  // B.5 : RO, tx FIFO empty
+        uint8_t tx_all_emp  : 1;  // B.6 : RO, THR/TSR all empty
+        uint8_t err_rx_fifo : 1;  // B.7 : RO, PAR/FRAME/BREAK ERR in rx FIFO
+    };
+};
+
+union _uart_msr
+{
+    uint8_t reg;
+    struct
+    {
+        uint8_t cts_chg     : 1;  // B.0 : RZ, CTS input changed
+        uint8_t dsr_chg     : 1;  // B.1 : RZ, DSR input changed
+        uint8_t ri_chg      : 1;  // B.2 : RZ, RI  input changed
+        uint8_t dcd_chg     : 1;  // B.3 : RZ, DCD input changed
+        uint8_t cts         : 1;  // B.4 : RO, CTS action status
+        uint8_t dsr         : 1;  // B.5 : RO, DSR action status
+        uint8_t ri          : 1;  // B.6 : RO, RI  action status
+        uint8_t dcd         : 1;  // B.7 : RO, DCD action status
+    };
+};
+
+struct uart_registers
+{
+    union _uart_mcr MCR;
+    union _uart_ier IER;
+    union _uart_fcr FCR;
+    union _uart_lcr LCR;
+    union _uart_iir IIR;
+    union _uart_lsr LSR;
+    union _uart_lsr MSR;
+    uint8_t         resv_7;
+    union
+    {
+        uint8_t     RBR;
+        uint8_t     THR;
+    };
+    uint8_t         resv_9;
+    uint8_t         RFC;
+    uint8_t         TFC;
+    uint16_t        DL;
+    uint8_t         DIV;
+    uint8_t         ADR;
+} __packed;
+
+
+int InitHwUart(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
@@ -0,0 +1,14 @@
+menuconfig BSP_USING_UART1
+    bool "Enable UART1"
+    default y
+    if BSP_USING_UART1
+        config SERIAL_BUS_NAME_1
+            string "serial bus  name"
+            default "uart1"
+        config SERIAL_DRV_NAME_1
+            string "serial bus  driver name"
+            default "uart1_drv"
+        config SERIAL_1_DEVICE_NAME_0
+                string "serial bus  device name"
+                default "uart1_dev1"   
+    endif
@@ -0,0 +1,4 @@
+SRC_FILES := connect_uart.c
+
+
+include $(KERNEL_ROOT)/compiler.mk
@@ -0,0 +1,404 @@
+/*
+ * Copyright (c) 2020 AIIT XUOS Lab
+ * XiUOS is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan
+ * PSL v2. You may obtain a copy of Mulan PSL v2 at:
+ *        http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY
+ * KIND, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO
+ * NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. See the
+ * Mulan PSL v2 for more details.
+ */
+
+/**
+ * @file connect_usart.c
+ * @brief support ch569 uart function and register to bus framework
+ * @version 1.0
+ * @author AIIT XUOS Lab
+ * @date 2025-04-07
+ */
+
+#include <xizi.h>
+#include "xsconfig.h"
+#include "CH56x_common.h"
+#include "ch56x_it.h"
+#include "board.h"
+#include "connect_uart.h"
+
+
+/*  uart driver */
+
+
+static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new) {
+    struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg;
+    struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg;
+
+    if ((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) {
+        data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate;
+    }
+
+    if ((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) {
+        data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order;
+    }
+
+    if ((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) &&
+        (data_cfg_new->serial_buffer_size)) {
+        data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size;
+    }
+
+    if ((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) {
+        data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits;
+    }
+
+    if ((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) &&
+        (data_cfg_new->serial_invert_mode)) {
+        data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode;
+    }
+
+    if ((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) &&
+        (data_cfg_new->serial_parity_mode)) {
+        data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode;
+    }
+
+    if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
+        data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
+    }
+
+    if ((data_cfg_default->serial_timeout != data_cfg_new->serial_timeout) && (data_cfg_new->serial_timeout)) {
+        data_cfg_default->serial_timeout = data_cfg_new->serial_timeout;
+    }
+}
+
+static void UartIsr(struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev) {
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
+    struct uart_registers *uxreg = (struct uart_registers *)serial_cfg->hw_cfg.serial_register_base;
+
+    if (UART_II_RECV_RDY == uxreg->IIR.int_mask) {
+        SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND);
+        PFIC_ClearPendingIRQ(serial_cfg->hw_cfg.serial_irq_interrupt);
+    }
+}
+
+static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info) {
+    NULL_PARAM_CHECK(serial_drv);
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
+
+    struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
+    struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
+
+    if (configure_info->private_data) {
+        struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data;
+        SerialCfgParamCheck(serial_cfg, serial_cfg_new);
+
+        if (serial_cfg_new->data_cfg.dev_recv_callback) {
+            BusDevRecvCallback(&(serial_dev->haldev), serial_cfg_new->data_cfg.dev_recv_callback);
+        }
+    }
+
+    // config serial receive sem timeout
+    dev_param->serial_timeout = serial_cfg->data_cfg.serial_timeout;
+
+
+#if 1
+    struct uart_registers *uxreg = (struct uart_registers *)serial_cfg->hw_cfg.serial_register_base;
+
+    union _uart_fcr fcr;
+    union _uart_lcr lcr;
+    uint32_t x;
+    uint32_t t = FREQ_SYS;
+
+//    x = 10 * sys_hclk_get() / 8 / serial_cfg->data_cfg.serial_baud_rate;
+    x = 10 * t / 8 / serial_cfg->data_cfg.serial_baud_rate;
+    x = (x + 5) / 10;
+    uxreg->DL = x;
+    uxreg->DIV = 1;
+
+    lcr.reg = 0;
+    switch (serial_cfg->data_cfg.serial_data_bits)
+    {
+    case DATA_BITS_5:
+        lcr.word_sz = LCR_DATA_BITS_5;
+        break;
+    case DATA_BITS_6:
+        lcr.word_sz = LCR_DATA_BITS_6;
+        break;
+    case DATA_BITS_7:
+        lcr.word_sz = LCR_DATA_BITS_7;
+        break;
+    case DATA_BITS_8:
+    default:
+        lcr.word_sz = LCR_DATA_BITS_8;
+        break;
+    }
+
+    switch (serial_cfg->data_cfg.serial_stop_bits)
+    {
+    case STOP_BITS_2:
+        lcr.stop_bit = LCR_STOP_BITS_2;
+        break;
+    case STOP_BITS_1:
+    default:
+        lcr.stop_bit = LCR_STOP_BITS_1;
+        break;
+    }
+
+    switch (serial_cfg->data_cfg.serial_parity_mode)
+    {
+    case PARITY_ODD:
+        lcr.par_mod = LCR_PARITY_ODD;
+        lcr.par_en = 1;
+        break;
+    case PARITY_EVEN:
+        lcr.par_mod = LCR_PARITY_EVEN;
+        lcr.par_en = 1;
+        break;
+    case PARITY_NONE:
+    default:
+        lcr.par_en = 0;
+        break;
+    }
+    uxreg->LCR.reg = lcr.reg;
+
+    fcr.reg = RB_FCR_FIFO_EN | RB_FCR_RX_FIFO_CLR | RB_FCR_TX_FIFO_CLR;
+    fcr.fifo_trig = UART_1BYTE_TRIG;
+    uxreg->FCR.reg = fcr.reg;
+
+    /* TXD pin output enable */
+    uxreg->IER.txd_en = 1;
+
+#endif
+
+    return EOK;
+}
+
+static uint32 SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd) {
+    NULL_PARAM_CHECK(serial_drv);
+
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
+    struct uart_registers *uxreg = (struct uart_registers *)serial_cfg->hw_cfg.serial_register_base;
+
+    switch (serial_operation_cmd) {
+        case OPER_CLR_INT:
+            uxreg->IER.recv_rdy = 0;
+            uxreg->IER.line_stat = 0;
+            uxreg->IER.thr_empty = 0;
+            PFIC_DisableIRQ(serial_cfg->hw_cfg.serial_irq_interrupt);
+            break;
+        case OPER_SET_INT:
+            uxreg->FCR.fifo_trig = UART_1BYTE_TRIG;
+            uxreg->MCR.int_oe = 1;
+            uxreg->IER.recv_rdy = 1;
+            uxreg->IER.line_stat = 1;
+            uxreg->IER.thr_empty = 1;
+            PFIC_EnableIRQ(serial_cfg->hw_cfg.serial_irq_interrupt);
+            break;
+    }
+
+    return EOK;
+}
+
+static uint32 SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info) {
+    NULL_PARAM_CHECK(drv);
+    NULL_PARAM_CHECK(configure_info);
+
+    x_err_t ret = EOK;
+    int serial_operation_cmd;
+    struct SerialDriver *serial_drv = (struct SerialDriver *)drv;
+
+    switch (configure_info->configure_cmd) {
+        case OPE_INT:
+            ret = SerialInit(serial_drv, configure_info);
+            break;
+        case OPE_CFG:
+            serial_operation_cmd = *(int *)configure_info->private_data;
+            ret = SerialConfigure(serial_drv, serial_operation_cmd);
+            break;
+        default:
+            break;
+    }
+
+    return ret;
+}
+
+static int SerialPutChar(struct SerialHardwareDevice *serial_dev, char ch) {
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
+    volatile struct uart_registers *uxreg = (struct uart_registers *)serial_cfg->hw_cfg.serial_register_base;
+
+    if (uxreg->TFC >= UART_FIFO_SIZE) {
+        return -1;
+    }
+    while (1 != uxreg->LSR.tx_fifo_emp);
+    uxreg->THR = ch;
+
+    return 1;
+}
+
+static int SerialGetChar(struct SerialHardwareDevice *serial_dev) {
+    int ch = -1;
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
+
+    if ( (UART1_GetLinSTA() & RB_LSR_DATA_RDY) == RB_LSR_DATA_RDY) {
+        ch = UART1_RecvByte();
+    }
+#if 0
+    if (RESET != USART_GetFlagStatus((USART_TypeDef *)serial_cfg->hw_cfg.serial_register_base, USART_FLAG_RXNE)) {
+        ch = USART_ReceiveData((USART_TypeDef *)serial_cfg->hw_cfg.serial_register_base) & 0xff;
+    }
+#endif
+
+    return ch;
+}
+
+static const struct SerialDataCfg data_cfg_init = {
+    .serial_baud_rate = BAUD_RATE_115200,
+    .serial_data_bits = DATA_BITS_8,
+    .serial_stop_bits = STOP_BITS_1,
+    .serial_parity_mode = PARITY_NONE,
+    .serial_bit_order = BIT_ORDER_LSB,
+    .serial_invert_mode = NRZ_NORMAL,
+    .serial_buffer_size = SERIAL_RB_BUFSZ,
+    .serial_timeout = WAITING_FOREVER,
+};
+
+/*manage the serial device operations*/
+static const struct SerialDrvDone drv_done = {
+    .init = SerialInit,
+    .configure = SerialConfigure,
+};
+
+/*manage the serial device hal operations*/
+static struct SerialHwDevDone hwdev_done = {
+    .put_char = SerialPutChar,
+    .get_char = SerialGetChar,
+};
+
+static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name,
+                              const char *drv_name) {
+    x_err_t ret = EOK;
+
+    /*Init the serial bus */
+    ret = SerialBusInit(serial_bus, bus_name);
+    if (EOK != ret) {
+        KPrintf("InitHwUart SerialBusInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Init the serial driver*/
+    ret = SerialDriverInit(serial_driver, drv_name);
+    if (EOK != ret) {
+        KPrintf("InitHwUart SerialDriverInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Attach the serial driver to the serial bus*/
+    ret = SerialDriverAttachToBus(drv_name, bus_name);
+    if (EOK != ret) {
+        KPrintf("InitHwUart SerialDriverAttachToBus error %d\n", ret);
+        return ERROR;
+    }
+
+    return ret;
+}
+
+/*Attach the serial device to the serial bus*/
+static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name,
+                              const char *dev_name) {
+    x_err_t ret = EOK;
+
+    ret = SerialDeviceRegister(serial_device, serial_param, dev_name);
+    if (EOK != ret) {
+        KPrintf("InitHwUart SerialDeviceInit device %s error %d\n", dev_name, ret);
+        return ERROR;
+    }
+
+    ret = SerialDeviceAttachToBus(dev_name, bus_name);
+    if (EOK != ret) {
+        KPrintf("InitHwUart SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
+        return ERROR;
+    }
+
+    return ret;
+}
+
+#ifdef BSP_USING_UART1
+struct SerialDriver serial_driver_1;
+struct SerialHardwareDevice serial_device_1;
+
+void UART1_IRQHandler(void) __attribute__((interrupt()));
+void UART1_IRQHandler(void) {
+#if 1
+    GET_INT_SP();
+    //isr_sp_enter();
+    x_base level;
+    level = DisableLocalInterrupt();
+    isrManager.done->incCounter();
+    EnableLocalInterrupt(level);
+    UartIsr(&serial_driver_1, &serial_device_1);
+    level = DisableLocalInterrupt();
+    isrManager.done->decCounter();
+    EnableLocalInterrupt(level);
+    FREE_INT_SP();
+    //isr_sp_leave();
+#endif
+}
+#endif
+
+int InitHwUart(void) {
+    x_err_t ret = EOK;
+
+#ifdef BSP_USING_UART1
+    static struct SerialBus serial_bus;
+    memset(&serial_bus, 0, sizeof(struct SerialBus));
+
+    memset(&serial_driver_1, 0, sizeof(struct SerialDriver));
+
+    memset(&serial_device_1, 0, sizeof(struct SerialHardwareDevice));
+
+    static struct SerialCfgParam serial_cfg;
+    memset(&serial_cfg, 0, sizeof(struct SerialCfgParam));
+
+    static struct SerialDevParam serial_dev_param;
+    memset(&serial_dev_param, 0, sizeof(struct SerialDevParam));
+
+    serial_driver_1.drv_done = &drv_done;
+    serial_driver_1.configure = &SerialDrvConfigure;
+    serial_device_1.hwdev_done = &hwdev_done;
+
+    serial_cfg.data_cfg = data_cfg_init;
+
+    serial_cfg.hw_cfg.serial_register_base = (uint32)BA_UART1;
+    serial_cfg.hw_cfg.serial_irq_interrupt = UART1_IRQn;
+
+    serial_driver_1.private_data = (void *)&serial_cfg;
+
+    serial_dev_param.serial_work_mode = SIGN_OPER_INT_RX;
+    serial_device_1.haldev.private_data = (void *)&serial_dev_param;
+
+    ret = BoardSerialBusInit(&serial_bus, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1);
+    if (EOK != ret) {
+        KPrintf("InitHwUart uarths error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg, SERIAL_BUS_NAME_1, SERIAL_1_DEVICE_NAME_0);
+    if (EOK != ret) {
+        KPrintf("InitHwUart uarths error ret %u\n", ret);
+        return ERROR;
+    }
+
+
+    /* Configure the serial port */
+	GPIOA_SetBits(GPIO_Pin_8);
+	GPIOA_ModeCfg(GPIO_Pin_7, GPIO_ModeIN_PU_NSMT);			// RXD-pull-up input
+	GPIOA_ModeCfg(GPIO_Pin_8, GPIO_Slowascent_PP_8mA);		// TXD-push-pull output
+//	UART1_DefInit();
+/*
+    //Interrupt method
+	UART1_ByteTrigCfg( UART_1BYTE_TRIG );
+	UART1_INTCfg( ENABLE, RB_IER_RECV_RDY|RB_IER_LINE_STAT );
+	PFIC_EnableIRQ( UART1_IRQn );
+*/
+#endif
+
+    return ret;
+}