rename board name 'gd32vf103_rvstar' as 'gd32vf103-rvstar'
This commit is contained in:
Wang_Weigen
+445
@@ -0,0 +1,445 @@
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/******************************************************************************
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* @file gd32vf103.h
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* @brief NMSIS Core Peripheral Access Layer Header File for GD32VF103 series
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*
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* @version V1.00
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* @date 4. Jan 2020
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******************************************************************************/
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/*
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* Copyright (c) 2019 Nuclei Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __GD32VF103_H__
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#define __GD32VF103_H__
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#include <stddef.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @addtogroup gd32
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* @{
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*/
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/** @addtogroup gd32vf103
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* @{
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*/
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/** @addtogroup Configuration_of_NMSIS
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* @{
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*/
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/** \brief SoC Download mode definition */
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typedef enum {
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DOWNLOAD_MODE_FLASHXIP = 0, /*!< Flashxip download mode */
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DOWNLOAD_MODE_FLASH = 1, /*!< Flash download mode */
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DOWNLOAD_MODE_ILM = 2, /*!< ilm download mode */
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DOWNLOAD_MODE_DDR = 3, /*!< ddr download mode */
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DOWNLOAD_MODE_MAX,
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} DownloadMode_Type;
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/* =========================================================================================================================== */
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/* ================ Interrupt Number Definition ================ */
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/* =========================================================================================================================== */
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typedef enum IRQn {
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/* ======================================= Nuclei Core Specific Interrupt Numbers ======================================== */
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Reserved0_IRQn = 0, /*!< Internal reserved */
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Reserved1_IRQn = 1, /*!< Internal reserved */
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Reserved2_IRQn = 2, /*!< Internal reserved */
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SysTimerSW_IRQn = 3, /*!< System Timer SW interrupt */
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Reserved3_IRQn = 4, /*!< Internal reserved */
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Reserved4_IRQn = 5, /*!< Internal reserved */
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Reserved5_IRQn = 6, /*!< Internal reserved */
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SysTimer_IRQn = 7, /*!< System Timer Interrupt */
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Reserved6_IRQn = 8, /*!< Internal reserved */
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Reserved7_IRQn = 9, /*!< Internal reserved */
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Reserved8_IRQn = 10, /*!< Internal reserved */
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Reserved9_IRQn = 11, /*!< Internal reserved */
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Reserved10_IRQn = 12, /*!< Internal reserved */
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Reserved11_IRQn = 13, /*!< Internal reserved */
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Reserved12_IRQn = 14, /*!< Internal reserved */
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Reserved13_IRQn = 15, /*!< Internal reserved */
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Reserved14_IRQn = 16, /*!< Internal reserved */
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BusError_IRQn = 17, /*!< Bus Error interrupt */
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PerfMon_IRQn = 18, /*!< Performance Monitor */
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/* =========================================== GD32VF103 Specific Interrupt Numbers ========================================= */
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/* ToDo: add here your device specific external interrupt numbers. 19~1023 is reserved number for user. Maxmum interrupt supported
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could get from clicinfo.NUM_INTERRUPT. According the interrupt handlers defined in startup_Device.s
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eg.: Interrupt for Timer#1 TIM1_IRQHandler -> TIM1_IRQn */
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/* interruput numbers */
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WWDGT_IRQn = 19, /*!< window watchDog timer interrupt */
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LVD_IRQn = 20, /*!< LVD through EXTI line detect interrupt */
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TAMPER_IRQn = 21, /*!< tamper through EXTI line detect */
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RTC_IRQn = 22, /*!< RTC alarm interrupt */
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FMC_IRQn = 23, /*!< FMC interrupt */
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RCU_CTC_IRQn = 24, /*!< RCU and CTC interrupt */
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EXTI0_IRQn = 25, /*!< EXTI line 0 interrupts */
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EXTI1_IRQn = 26, /*!< EXTI line 1 interrupts */
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EXTI2_IRQn = 27, /*!< EXTI line 2 interrupts */
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EXTI3_IRQn = 28, /*!< EXTI line 3 interrupts */
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EXTI4_IRQn = 29, /*!< EXTI line 4 interrupts */
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DMA0_Channel0_IRQn = 30, /*!< DMA0 channel0 interrupt */
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DMA0_Channel1_IRQn = 31, /*!< DMA0 channel1 interrupt */
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DMA0_Channel2_IRQn = 32, /*!< DMA0 channel2 interrupt */
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DMA0_Channel3_IRQn = 33, /*!< DMA0 channel3 interrupt */
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DMA0_Channel4_IRQn = 34, /*!< DMA0 channel4 interrupt */
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DMA0_Channel5_IRQn = 35, /*!< DMA0 channel5 interrupt */
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DMA0_Channel6_IRQn = 36, /*!< DMA0 channel6 interrupt */
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ADC0_1_IRQn = 37, /*!< ADC0 and ADC1 interrupt */
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CAN0_TX_IRQn = 38, /*!< CAN0 TX interrupts */
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CAN0_RX0_IRQn = 39, /*!< CAN0 RX0 interrupts */
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CAN0_RX1_IRQn = 40, /*!< CAN0 RX1 interrupts */
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CAN0_EWMC_IRQn = 41, /*!< CAN0 EWMC interrupts */
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EXTI5_9_IRQn = 42, /*!< EXTI[9:5] interrupts */
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TIMER0_BRK_IRQn = 43, /*!< TIMER0 break interrupts */
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TIMER0_UP_IRQn = 44, /*!< TIMER0 update interrupts */
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TIMER0_TRG_CMT_IRQn = 45, /*!< TIMER0 trigger and commutation interrupts */
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TIMER0_Channel_IRQn = 46, /*!< TIMER0 channel capture compare interrupts */
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TIMER1_IRQn = 47, /*!< TIMER1 interrupt */
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TIMER2_IRQn = 48, /*!< TIMER2 interrupt */
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TIMER3_IRQn = 49, /*!< TIMER3 interrupts */
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I2C0_EV_IRQn = 50, /*!< I2C0 event interrupt */
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I2C0_ER_IRQn = 51, /*!< I2C0 error interrupt */
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I2C1_EV_IRQn = 52, /*!< I2C1 event interrupt */
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I2C1_ER_IRQn = 53, /*!< I2C1 error interrupt */
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SPI0_IRQn = 54, /*!< SPI0 interrupt */
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SPI1_IRQn = 55, /*!< SPI1 interrupt */
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USART0_IRQn = 56, /*!< USART0 interrupt */
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USART1_IRQn = 57, /*!< USART1 interrupt */
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USART2_IRQn = 58, /*!< USART2 interrupt */
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EXTI10_15_IRQn = 59, /*!< EXTI[15:10] interrupts */
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RTC_ALARM_IRQn = 60, /*!< RTC alarm interrupt EXTI */
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USBFS_WKUP_IRQn = 61, /*!< USBFS wakeup interrupt */
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EXMC_IRQn = 67, /*!< EXMC global interrupt */
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TIMER4_IRQn = 69, /*!< TIMER4 global interrupt */
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SPI2_IRQn = 70, /*!< SPI2 global interrupt */
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UART3_IRQn = 71, /*!< UART3 global interrupt */
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UART4_IRQn = 72, /*!< UART4 global interrupt */
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TIMER5_IRQn = 73, /*!< TIMER5 global interrupt */
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TIMER6_IRQn = 74, /*!< TIMER6 global interrupt */
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DMA1_Channel0_IRQn = 75, /*!< DMA1 channel0 global interrupt */
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DMA1_Channel1_IRQn = 76, /*!< DMA1 channel1 global interrupt */
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DMA1_Channel2_IRQn = 77, /*!< DMA1 channel2 global interrupt */
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DMA1_Channel3_IRQn = 78, /*!< DMA1 channel3 global interrupt */
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DMA1_Channel4_IRQn = 79, /*!< DMA1 channel3 global interrupt */
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CAN1_TX_IRQn = 82, /*!< CAN1 TX interrupt */
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CAN1_RX0_IRQn = 83, /*!< CAN1 RX0 interrupt */
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CAN1_RX1_IRQn = 84, /*!< CAN1 RX1 interrupt */
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CAN1_EWMC_IRQn = 85, /*!< CAN1 EWMC interrupt */
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USBFS_IRQn = 86, /*!< USBFS global interrupt */
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SOC_INT_MAX,
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} IRQn_Type;
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/* =========================================================================================================================== */
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/* ================ Exception Code Definition ================ */
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/* =========================================================================================================================== */
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typedef enum EXCn {
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/* ======================================= Nuclei N/NX Specific Exception Code ======================================== */
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InsUnalign_EXCn = 0, /*!< Instruction address misaligned */
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InsAccFault_EXCn = 1, /*!< Instruction access fault */
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IlleIns_EXCn = 2, /*!< Illegal instruction */
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Break_EXCn = 3, /*!< Beakpoint */
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LdAddrUnalign_EXCn = 4, /*!< Load address misaligned */
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LdFault_EXCn = 5, /*!< Load access fault */
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StAddrUnalign_EXCn = 6, /*!< Store or AMO address misaligned */
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StAccessFault_EXCn = 7, /*!< Store or AMO access fault */
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UmodeEcall_EXCn = 8, /*!< Environment call from User mode */
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MmodeEcall_EXCn = 11, /*!< Environment call from Machine mode */
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NMI_EXCn = 0xfff, /*!< NMI interrupt*/
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} EXCn_Type;
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/* =========================================================================================================================== */
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/* ================ Processor and Core Peripheral Section ================ */
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/* =========================================================================================================================== */
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/* ToDo: set the defines according your Device */
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/* ToDo: define the correct core revision */
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#define __NUCLEI_N_REV 0x0100 /*!< Core Revision r1p0 */
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/* ToDo: define the correct core features for the nuclei_soc */
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#define __ECLIC_PRESENT 1 /*!< Set to 1 if ECLIC is present */
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#define __ECLIC_BASEADDR 0xD2000000UL /*!< Set to ECLIC baseaddr of your device */
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#define __ECLIC_INTCTLBITS 4 /*!< Set to 1 - 8, the number of hardware bits are actually implemented in the clicintctl registers. */
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#define __ECLIC_INTNUM 86 /*!< Set to 1 - 1005, the external interrupt number of ECLIC Unit */
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#define __SYSTIMER_PRESENT 1 /*!< Set to 1 if System Timer is present */
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#define __SYSTIMER_BASEADDR 0xD1000000UL /*!< Set to SysTimer baseaddr of your device */
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/*!< Set to 0, 1, or 2, 0 not present, 1 single floating point unit present, 2 double floating point unit present */
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#define __FPU_PRESENT 0
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#define __DSP_PRESENT 0 /*!< Set to 1 if DSP is present */
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#define __PMP_PRESENT 1 /*!< Set to 1 if PMP is present */
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#define __PMP_ENTRY_NUM 8 /*!< Set to 8 or 16, the number of PMP entries */
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#define __ICACHE_PRESENT 0 /*!< Set to 1 if I-Cache is present */
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#define __DCACHE_PRESENT 0 /*!< Set to 1 if D-Cache is present */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#define __Vendor_EXCEPTION 0 /*!< Set to 1 if vendor exception hander is present */
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/** @} */ /* End of group Configuration_of_CMSIS */
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// #include <nmsis_core.h> /*!< Nuclei N/NX class processor and core peripherals */
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/* ToDo: include your system_nuclei_soc.h file
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replace 'Device' with your device name */
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#include "system_gd32vf103.h" /*!< gd32vf103 System */
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/* ======================================== Start of section using anonymous unions ======================================== */
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#if defined (__GNUC__)
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/* anonymous unions are enabled by default */
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#else
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#warning Not supported compiler type
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#endif
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/* system frequency define */
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#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */
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#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */
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#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */
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#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000)
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#define RTC_FREQ LXTAL_VALUE
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// The TIMER frequency is just the RTC frequency
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#define SOC_TIMER_FREQ ((uint32_t)SystemCoreClock/4) //LXTAL_VALUE units HZ
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#define SYSTICK_TICK_CONST (SOC_TIMER_FREQ / TICK_PER_SECOND)
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/* enum definitions */
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typedef enum {
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DISABLE = 0,
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ENABLE = !DISABLE
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} EventStatus, ControlStatus;
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typedef enum {
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FALSE = 0,
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TRUE = !FALSE
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} BOOL;
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typedef enum {
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RESET = 0,
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SET = 1,
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MAX = 0X7FFFFFFF
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} FlagStatus;
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typedef enum {
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ERR = 0,
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SUCCESS = !ERR
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} ErrStatus;
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/* =========================================================================================================================== */
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/* ================ Device Specific Peripheral Section ================ */
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/* =========================================================================================================================== */
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/** @addtogroup Device_Peripheral_peripherals
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* @{
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*/
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/****************************************************************************
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* Platform definitions
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*****************************************************************************/
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/* ToDo: add here your device specific peripheral access structure typedefs
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following is an example for Systick Timer*/
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/* =========================================================================================================================== */
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/* ================ SysTick Timer ================ */
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/* =========================================================================================================================== */
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/*@}*/ /* end of group nuclei_soc_Peripherals */
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/* ========================================= End of section using anonymous unions ========================================= */
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#if defined (__GNUC__)
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/* anonymous unions are enabled by default */
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#else
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#warning Not supported compiler type
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#endif
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/* =========================================================================================================================== */
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/* ================ Device Specific Peripheral Address Map ================ */
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/* =========================================================================================================================== */
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/* ToDo: add here your device peripherals base addresses
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following is an example for timer */
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/** @addtogroup Device_Peripheral_peripheralAddr
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* @{
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*/
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/* main flash and SRAM memory map */
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#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
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#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */
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#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */
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#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */
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#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */
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/* peripheral memory map */
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#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
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#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
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#define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */
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#define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */
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/* advanced peripheral bus 1 memory map */
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#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
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#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
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#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
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#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
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#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
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#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
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#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
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#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */
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||||
#define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */
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||||
#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
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#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */
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||||
|
||||
/* advanced peripheral bus 2 memory map */
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#define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */
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#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */
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||||
#define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */
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||||
#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */
|
||||
|
||||
/* advanced high performance bus 1 memory map */
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#define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */
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||||
#define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */
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||||
#define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */
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||||
#define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */
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||||
#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */
|
||||
|
||||
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||||
/** @} */ /* End of group Device_Peripheral_peripheralAddr */
|
||||
|
||||
|
||||
/* =========================================================================================================================== */
|
||||
/* ================ Peripheral declaration ================ */
|
||||
/* =========================================================================================================================== */
|
||||
|
||||
/* Macros for memory access operations */
|
||||
#define _REG8P(p, i) ((volatile uint8_t *) ((uintptr_t)((p) + (i))))
|
||||
#define _REG16P(p, i) ((volatile uint16_t *) ((uintptr_t)((p) + (i))))
|
||||
#define _REG32P(p, i) ((volatile uint32_t *) ((uintptr_t)((p) + (i))))
|
||||
#define _REG64P(p, i) ((volatile uint64_t *) ((uintptr_t)((p) + (i))))
|
||||
#define _REG8(p, i) (*(_REG8P(p, i)))
|
||||
#define _REG16(p, i) (*(_REG16P(p, i)))
|
||||
#define _REG32(p, i) (*(_REG32P(p, i)))
|
||||
#define _REG64(p, i) (*(_REG64P(p, i)))
|
||||
#define REG8(addr) _REG8((addr), 0)
|
||||
#define REG16(addr) _REG16((addr), 0)
|
||||
#define REG32(addr) _REG32((addr), 0)
|
||||
#define REG64(addr) _REG64((addr), 0)
|
||||
|
||||
/* Macros for address type convert and access operations */
|
||||
#define ADDR16(addr) ((uint16_t)(uintptr_t)(addr))
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||||
#define ADDR32(addr) ((uint32_t)(uintptr_t)(addr))
|
||||
#define ADDR64(addr) ((uint64_t)(uintptr_t)(addr))
|
||||
#define ADDR8P(addr) ((uint8_t *)(uintptr_t)(addr))
|
||||
#define ADDR16P(addr) ((uint16_t *)(uintptr_t)(addr))
|
||||
#define ADDR32P(addr) ((uint32_t *)(uintptr_t)(addr))
|
||||
#define ADDR64P(addr) ((uint64_t *)(uintptr_t)(addr))
|
||||
|
||||
/* Macros for Bit Operations */
|
||||
#if __riscv_xlen == 32
|
||||
#define BITMASK_MAX 0xFFFFFFFFUL
|
||||
#define BITOFS_MAX 31
|
||||
#else
|
||||
#define BITMASK_MAX 0xFFFFFFFFFFFFFFFFULL
|
||||
#define BITOFS_MAX 63
|
||||
#endif
|
||||
|
||||
// BIT/BITS only support bit mask for __riscv_xlen
|
||||
// For RISC-V 32 bit, it support mask 32 bit wide
|
||||
// For RISC-V 64 bit, it support mask 64 bit wide
|
||||
#define BIT(ofs) (0x1UL << (ofs))
|
||||
#define BITS(start, end) ((BITMASK_MAX) << (start) & (BITMASK_MAX) >> (BITOFS_MAX - (end)))
|
||||
#define GET_BIT(regval, bitofs) (((regval) >> (bitofs)) & 0x1)
|
||||
#define SET_BIT(regval, bitofs) ((regval) |= BIT(bitofs))
|
||||
#define CLR_BIT(regval, bitofs) ((regval) &= (~BIT(bitofs)))
|
||||
#define FLIP_BIT(regval, bitofs) ((regval) ^= BIT(bitofs))
|
||||
#define WRITE_BIT(regval, bitofs, val) CLR_BIT(regval, bitofs); ((regval) |= ((val) << bitofs) & BIT(bitofs))
|
||||
#define CHECK_BIT(regval, bitofs) (!!((regval) & (0x1UL<<(bitofs))))
|
||||
#define GET_BITS(regval, start, end) (((regval) & BITS((start), (end))) >> (start))
|
||||
#define SET_BITS(regval, start, end) ((regval) |= BITS((start), (end)))
|
||||
#define CLR_BITS(regval, start, end) ((regval) &= (~BITS((start), (end))))
|
||||
#define FLIP_BITS(regval, start, end) ((regval) ^= BITS((start), (end)))
|
||||
#define WRITE_BITS(regval, start, end, val) CLR_BITS(regval, start, end); ((regval) |= ((val) << start) & BITS((start), (end)))
|
||||
#define CHECK_BITS_ALL(regval, start, end) (!((~(regval)) & BITS((start), (end))))
|
||||
#define CHECK_BITS_ANY(regval, start, end) ((regval) & BITS((start), (end)))
|
||||
|
||||
#define BITMASK_SET(regval, mask) ((regval) |= (mask))
|
||||
#define BITMASK_CLR(regval, mask) ((regval) &= (~(mask)))
|
||||
#define BITMASK_FLIP(regval, mask) ((regval) ^= (mask))
|
||||
#define BITMASK_CHECK_ALL(regval, mask) (!((~(regval)) & (mask)))
|
||||
#define BITMASK_CHECK_ANY(regval, mask) ((regval) & (mask))
|
||||
|
||||
/* ToDo: add here your device peripherals pointer definitions
|
||||
following is an example for timer */
|
||||
/** @addtogroup Device_Peripheral_declaration
|
||||
* @{
|
||||
*/
|
||||
|
||||
// Interrupt Numbers
|
||||
#define SOC_ECLIC_NUM_INTERRUPTS 86
|
||||
#define SOC_ECLIC_INT_GPIO_BASE 19
|
||||
|
||||
|
||||
// Interrupt Handler Definitions
|
||||
#define SOC_MTIMER_HANDLER eclic_mtip_handler
|
||||
#define SOC_SOFTINT_HANDLER eclic_msip_handler
|
||||
|
||||
#define NUM_GPIO 32
|
||||
|
||||
extern uint32_t get_cpu_freq(void);
|
||||
|
||||
/**
|
||||
* \brief delay a time in milliseconds
|
||||
* \param[in] count: count in milliseconds
|
||||
* \param[out] none
|
||||
* \retval none
|
||||
*/
|
||||
extern void delay_1ms(uint32_t count);
|
||||
|
||||
|
||||
/** @} */ /* End of group gd32vf103_soc */
|
||||
|
||||
/** @} */ /* End of group gd32vf103 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __GD32VF103_SOC_H__ */
|
||||
Reference in New Issue
Block a user