Delete unused code
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songyanguang
parent
c5bd15ab91
commit
3e70ccddce
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@ -78,24 +78,6 @@ Modification:
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#define NR_CPU 1 // maximum number of CPUs
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__attribute__((always_inline)) static inline uint64_t EL0_mode() // Set ARM mode to EL0
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{
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uint64_t val = 0;
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return val;
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}
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__attribute__((always_inline, optimize("O0"))) static inline void cpu_into_low_power()
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{
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WFE();
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}
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__attribute__((always_inline, optimize("O0"))) static inline void cpu_leave_low_power()
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{
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SEV();
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}
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struct __riscv_d_ext_state {
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uint64_t f[32];
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uint32_t fcsr;
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@ -1,10 +1,10 @@
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/*!
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* @file cortexA55.s
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* @file cortex.s
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* @brief This file contains cortexA55 functions
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*
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*/
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/*************************************************
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File name: cortexA55.S
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File name: cortex.S
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Description: This file contains cortexA9 functions
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Others:
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History:
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@ -28,7 +28,7 @@
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file cortex_a55.h
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* @file cortex.h
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* @brief some cortex A55 core functions
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* @version 1.0
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* @author AIIT XUOS Lab
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@ -36,7 +36,7 @@
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*/
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/*************************************************
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File name: cortex_a55.h
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File name: cortex.h
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Description: some cortex A55 core functions
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Others:
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History:
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@ -1,110 +0,0 @@
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/*
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* Copyright (c) 2020 AIIT XUOS Lab
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* XiUOS is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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* See the Mulan PSL v2 for more details.
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*/
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#ifndef INC_SYSREGS_H_
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#define INC_SYSREGS_H_
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/* SCTLR_EL1, System Control Register (EL1). */
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#define SCTLR_RESERVED \
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((3 << 28) | (3 << 22) | (1 << 20) | (1 << 11) | (1 << 8) | (1 << 7))
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#define SCTLR_EE_LITTLE_ENDIAN (0 << 25)
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#define SCTLR_E0E_LITTLE_ENDIAN (0 << 24)
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#define SCTLR_I_CACHE (1 << 12)
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#define SCTLR_D_CACHE (1 << 2)
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#define SCTLR_MMU_DISABLED (0 << 0)
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#define SCTLR_MMU_ENABLED (1 << 0)
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#define SCTLR_VALUE_MMU_DISABLED \
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(SCTLR_RESERVED | SCTLR_EE_LITTLE_ENDIAN | SCTLR_E0E_LITTLE_ENDIAN \
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| SCTLR_I_CACHE | SCTLR_D_CACHE | SCTLR_MMU_DISABLED)
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/* HCR_EL2, Hypervisor Configuration Register (EL2). */
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#define HCR_RW (1 << 31)
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#define HCR_VALUE HCR_RW
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/* CPACR_EL1, Architectural Feature Access Control Register. */
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#define CPACR_FP_EN (3 << 20)
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#define CPACR_TRACE_EN (0 << 28)
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#define CPACR_VALUE (CPACR_FP_EN | CPACR_TRACE_EN)
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/* SCR_EL3, Secure Configuration Register (EL3). */
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#define SCR_RESERVED (3 << 4)
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#define SCR_RW (1 << 10)
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#define SCR_HCE (1 << 8)
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#define SCR_SMD (1 << 7)
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#define SCR_NS (1 << 0)
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#define SCR_VALUE (SCR_RESERVED | SCR_RW | SCR_HCE | SCR_SMD | SCR_NS)
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/* SPSR_EL1/2/3, Saved Program Status Register. */
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#define SPSR_MASK_ALL (7 << 6)
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#define SPSR_EL1h (5 << 0)
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#define SPSR_EL2h (9 << 0)
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#define SPSR_EL3_VALUE (SPSR_MASK_ALL | SPSR_EL2h)
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#define SPSR_EL2_VALUE (SPSR_MASK_ALL | SPSR_EL1h)
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/* Exception Class in ESR_EL1. */
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#define EC_SHIFT 26
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#define EC_UNKNOWN 0x00
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#define EC_SVC64 0x15
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#define EC_DABORT 0x24
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#define EC_IABORT 0x20
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#define PTE_VALID 1 // level 0,1,2 descriptor: valid
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#define PTE_TABLE 2 // level 0,1,2 descriptor: table
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#define PTE_V 3 // level 3 descriptor: valid
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// PTE_AF(Access Flag)
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//
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// 0 -- this block entry has not yet.
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// 1 -- this block entry has been used.
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#define PTE_AF (1 << 10)
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// PTE_AP(Access Permission) is 2bit field.
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// EL0 EL1
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// 00 -- x RW
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// 01 -- RW RW
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// 10 -- x RO
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// 11 -- RO RO
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#define PTE_AP(ap) (((ap) & 3) << 6)
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#define PTE_U PTE_AP(1)
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#define PTE_RO PTE_AP(2)
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#define PTE_URO PTE_AP(3)
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#define PTE_PXN (1UL << 53) // Privileged eXecute Never
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#define PTE_UXN (1UL << 54) // Unprivileged(user) eXecute Never
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#define PTE_XN (PTE_PXN | PTE_UXN) // eXecute Never
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// attribute index
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// index is set by mair_el1
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#define AI_DEVICE_nGnRnE_IDX 0x0
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#define AI_NORMAL_NC_IDX 0x1
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// memory type
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#define MT_DEVICE_nGnRnE 0x0
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#define MT_NORMAL_NC 0x44
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#define PTE_INDX(i) (((i) & 7) << 2)
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#define PTE_DEVICE PTE_INDX(AI_DEVICE_nGnRnE_IDX)
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#define PTE_NORMAL PTE_INDX(AI_NORMAL_NC_IDX)
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// shift a physical address to the right place for a PTE.
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#define PA2PTE(pa) ((uint64_t)(pa) & 0xfffffffff000)
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#define PTE2PA(pte) ((uint64_t)(pte) & 0xfffffffff000)
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#define PTE_FLAGS(pte) ((pte) & (0x600000000003ff))
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// translation control register
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// #define TCR_T0SZ(n) ((n) & 0x3f)
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// #define TCR_TG0(n) (((n) & 0x3) << 14)
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// #define TCR_T1SZ(n) (((n) & 0x3f) << 16)
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// #define TCR_TG1(n) (((n) & 0x3) << 30)
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// #define TCR_IPS(n) (((n) & 0x7) << 32)
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#define ISS_MASK 0xFFFFFF
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#endif // INC_SYSREGS_H_
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