diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile index 8aaf42053..ee8377f49 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile @@ -1,10 +1,4 @@ SRC_FILES := trampoline.S $(BOARD)/trap_common.c $(BOARD)/trap.c $(BOARD)/plic.c error_debug.c hard_spinlock.S - -ifeq ($(BOARD), jh7110) -SRC_DIR := gicv3 SRC_FILES += $(BOARD)/ -endif - include $(KERNEL_ROOT)/compiler.mk - diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/Makefile deleted file mode 100644 index c5085627e..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -SRC_FILES := gicv3.c - -include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3.c deleted file mode 100644 index f299f4966..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3.c +++ /dev/null @@ -1,260 +0,0 @@ -/* - * Copyright (c) 2020 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ -/** - * @file gicv3.c - * @brief gicv3 operation - * @version 1.0 - * @author AIIT XUOS Lab - * @date 2024.05.10 - */ - -/************************************************* -File name: gicv3.c -Description: gicv3 operation -Others: -History: -Author: AIIT XUOS Lab -Modification: -*************************************************/ -#include - -#include "core.h" -#include "gicv3_common_opa.h" -#include "gicv3_registers.h" - -static struct { - char* gicd; - char* rdist_addrs[NR_CPU]; -} gicv3; - -static inline uint32_t icc_igrpen1_el1() -{ - uint32_t x; -// __asm__ volatile("mrs %0, S3_0_C12_C12_7" : "=r"(x)); - return x; -} - -static inline void w_icc_igrpen1_el1(uint32_t x) -{ -// __asm__ volatile("msr S3_0_C12_C12_7, %0" : : "r"(x)); -} - -static inline uint32_t icc_pmr_el1() -{ - uint32_t x; -// __asm__ volatile("mrs %0, S3_0_C4_C6_0" : "=r"(x)); - return x; -} - -static inline void w_icc_pmr_el1(uint32_t x) -{ -// __asm__ volatile("msr S3_0_C4_C6_0, %0" : : "r"(x)); -} - -inline uint32_t gic_read_irq_ack() -{ - uint32_t x; -// __asm__ volatile("mrs %0, S3_0_C12_C12_0" : "=r"(x)); - return x; -} - -inline void -gic_write_end_of_irq(uint32_t x) -{ -// __asm__ volatile("msr S3_0_C12_C12_1, %0" : : "r"(x)); -} - -static inline uint32_t icc_sre_el1() -{ - uint32_t x; -// __asm__ volatile("mrs %0, S3_0_C12_C12_5" : "=r"(x)); - return x; -} - -static inline void w_icc_sre_el1(uint32_t x) -{ -// __asm__ volatile("msr S3_0_C12_C12_5, %0" : : "r"(x)); -} - -static void gicd_write(uint32_t off, uint32_t val) -{ -// *(volatile uint32_t*)(gicv3.gicd + off) = val; -} - -static uint32_t gicd_read(uint32_t off) -{ -// return *(volatile uint32_t*)(gicv3.gicd + off); - return 0; -} - -static void gicr_write(uint32_t cpuid, uint32_t off, uint32_t val) -{ -// *(volatile uint32_t*)(gicv3.rdist_addrs[cpuid] + off) = val; -} - -static uint32_t gicr_read(uint32_t cpuid, uint32_t off) -{ -// return *(volatile uint32_t*)(gicv3.rdist_addrs[cpuid] + off); - return 0; -} - -static void giccinit() -{ - w_icc_igrpen1_el1(0); - w_icc_pmr_el1(0xff); -} - -static void gicdinit() -{ - gicd_write(D_CTLR, 0); - - uint32_t typer = gicd_read(D_TYPER); - uint32_t lines = typer & 0x1f; - - for (int i = 0; i < lines; i++) - gicd_write(D_IGROUPR(i), ~0); -} - -static void gicrinit(uint32_t cpuid) -{ - gicr_write(cpuid, R_CTLR, 0); - - w_icc_sre_el1(icc_sre_el1() | 1); - - gicr_write(cpuid, R_IGROUPR0, ~0); - gicr_write(cpuid, R_IGRPMODR0, 0); - - uint32_t waker = gicr_read(cpuid, R_WAKER); - gicr_write(cpuid, R_WAKER, waker & ~(1 << 1)); - while (gicr_read(cpuid, R_WAKER) & (1 << 2)) - ; -} - -void gic_enable() -{ - gicd_write(D_CTLR, (1 << 1)); - w_icc_igrpen1_el1(1); -} - -void gic_init() -{ - gicv3.gicd = (char*)GICV3; - for (int i = 0; i < NR_CPU; i++) { - gicv3.rdist_addrs[i] = (char*)(GICV3_REDIST + (i) * 0x20000); - } - - gicdinit(); -} - -void gicv3inithart(uint32_t cpu_id) -{ - giccinit(); - gicrinit(cpu_id); - - gic_enable(); -} - -static void -gic_enable_int(uint32_t intid) -{ - uint32_t is = gicd_read(D_ISENABLER(intid / 32)); - is |= 1 << (intid % 32); - gicd_write(D_ISENABLER(intid / 32), is); -} - -int gic_int_enabled(uint32_t intid) -{ - uint32_t is = gicd_read(D_ISENABLER(intid / 32)); - return is & (1 << (intid % 32)); -} - -static void -gic_clear_pending(uint32_t intid) -{ - uint32_t ic = gicd_read(D_ICPENDR(intid / 32)); - ic |= 1 << (intid % 32); - gicd_write(D_ICPENDR(intid / 32), ic); -} - -static void -gic_set_prio0(uint32_t intid) -{ - // set priority to 0 - uint32_t p = gicd_read(D_IPRIORITYR(intid / 4)); - p &= ~((uint32_t)0xff << (intid % 4 * 8)); // set prio 0 - gicd_write(D_IPRIORITYR(intid / 4), p); -} - -static void gic_set_target(uint32_t intid, uint32_t cpuid) -{ - uint32_t itargetsr = gicd_read(D_ITARGETSR(intid / 4)); - itargetsr &= ~((uint32_t)0xff << (intid % 4 * 8)); - gicd_write(D_ITARGETSR(intid / 4), itargetsr | ((uint32_t)(1 << cpuid) << (intid % 4 * 8))); -} - -static void -gicr_enable_int(uint32_t cpuid, uint32_t intid) -{ - uint32_t is = gicr_read(cpuid, R_ISENABLER0); - is |= 1 << (intid % 32); - gicr_write(cpuid, R_ISENABLER0, is); -} - -static void -gicr_clear_pending(uint32_t cpuid, uint32_t intid) -{ - uint32_t ic = gicr_read(cpuid, R_ICPENDR0); - ic |= 1 << (intid % 32); - gicr_write(cpuid, R_ICPENDR0, ic); -} - -static void -gicr_set_prio0(uint32_t cpuid, uint32_t intid) -{ - uint32_t p = gicr_read(cpuid, R_IPRIORITYR(intid / 4)); - p &= ~((uint32_t)0xff << (intid % 4 * 8)); // set prio 0 - gicr_write(cpuid, R_IPRIORITYR(intid / 4), p); -} - -void gic_setup_ppi(uint32_t cpuid, uint32_t intid) -{ - gicr_set_prio0(cpuid, intid); - gicr_clear_pending(cpuid, intid); - gicr_enable_int(cpuid, intid); -} - -void gic_setup_spi(uint32_t cpuid, uint32_t intid) -{ - gic_set_prio0(intid); - gic_set_target(intid, cpuid); - gic_clear_pending(intid); - gic_enable_int(intid); -} - -// irq from iar -int gic_iar_irq(uint32_t iar) -{ - return iar & 0x3ff; -} - -// interrupt acknowledge register: -// ask GIC what interrupt we should serve. -uint32_t gic_iar() -{ - return gic_read_irq_ack(); -} - -// tell GIC we've served this IRQ. -void gic_eoi(uint32_t iar) -{ - gic_write_end_of_irq(iar); -} diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_common_opa.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_common_opa.h deleted file mode 100644 index 17e3632eb..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_common_opa.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (c) 2020 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ -/** - * @file gicv3_common_opa.h - * @brief gicv3 operation - * @version 1.0 - * @author AIIT XUOS Lab - * @date 2024.05.07 - */ -/************************************************* -File name: gicv3_common_opa.h -Description: gicv3 operation -Others: -History: -Author: AIIT XUOS Lab -Modification: -1. Rename file -*************************************************/ -#pragma once - -#include -#include - -#include - -//! @name Initialization -//@{ -//! @brief Init interrupt handling. -//! -//! This function is intended to be called only by the primary CPU init code, so it will -//! only be called once during system bootup. -//! -//! Also inits the current CPU. You don't need to call gic_init_cpu() separately. -//! -//! @post The interrupt distributor and the current CPU interface are enabled. All interrupts -//! that were pending are cleared, and all interrupts are made secure (group 0). -void gic_init(void); - -//! @name GIC Interrupt Distributor Functions -//@{ -//! @brief Enable or disable the GIC Distributor. -//! -//! Enables or disables the GIC distributor passing both secure (group 0) and non-secure -//! (group 1) interrupts to the CPU interfaces. -//! -//! @param enableIt Pass true to enable or false to disable. -void gic_enable(); - -//! @brief Set the security mode for an interrupt. -//! -//! @param irqID The interrupt number. -//! @param isSecure Whether the interrupt is taken to secure mode. -void gic_set_irq_security(uint32_t irqID, bool isSecure); - -//! @brief Enable or disable an interrupt. -//! -//! @param irqID The number of the interrupt to control. -//! @param isEnabled Pass true to enable or false to disable. -void gic_enable_irq(uint32_t irqID, bool isEnabled); - -//! @brief Set whether a CPU will receive a particular interrupt. -//! -//! @param irqID The interrupt number. -//! @param cpuNumber The CPU number. The first CPU core is 0. -//! @param enableIt Whether to send the interrupt to the specified CPU. Pass true to enable -//! or false to disable. -void gic_set_cpu_target(uint32_t irqID, unsigned cpuNumber, bool enableIt); - -//! @brief Set an interrupt's priority. -//! -//! @param irq_id The interrupt number. -//! @param priority The priority for the interrupt. In the range of 0 through 0xff, with -//! 0 being the highest priority. -void gic_set_irq_priority(uint32_t irq_id, uint32_t priority); - -void gic_setup_spi(uint32_t cpuid, uint32_t intid); -void gic_setup_ppi(uint32_t cpuid, uint32_t intid); - -void gicv3inithart(uint32_t cpu_id); -//! @brief Send a software generated interrupt to a specific CPU. -//! -//! @param irq_id The interrupt number to send. -//! @param target_list Each bit indicates a CPU to which the interrupt will be forwarded. -//! Bit 0 is CPU 0, bit 1 is CPU 1, and so on. If the value is 0, then the interrupt -//! will not be forwarded to any CPUs. This parameter is only used if @a filter_list -//! is set to #kGicSgiFilter_UseTargetList. -//! @param filter_list One of the enums of the #_gicd_sgi_filter enumeration. The selected -//! option determines which CPUs the interrupt will be sent to. If the value -//! is #kGicSgiFilter_UseTargetList, then the @a target_list parameter is used. -void gic_send_sgi(uint32_t irq_id, uint32_t target_list, uint32_t filter_list); -//@} - -//! @name GIC CPU Interface Functions -//@{ -//! @brief Enable or disable the interface to the GIC for the current CPU. -//! -//! @param enableIt Pass true to enable or false to disable. -void gic_cpu_enable(bool enableIt); - -//! @brief Set the mask of which interrupt priorities the CPU will receive. -//! -//! @param priority The lowest priority that will be passed to the current CPU. Pass 0xff to -//! allow all priority interrupts to signal the CPU. -void gic_set_cpu_priority_mask(uint32_t priority); - -//! @brief Acknowledge starting of interrupt handling and get the interrupt number. -//! -//! Normally, this function is called at the beginning of the IRQ handler. It tells the GIC -//! that you are starting to handle an interupt, and returns the number of the interrupt you -//! need to handle. After the interrupt is handled, you should call gic_write_end_of_irq() -//! to signal that the interrupt is completely handled. -//! -//! In some cases, a spurious interrupt might happen. One possibility is if another CPU handles -//! the interrupt. When a spurious interrupt occurs, the end of the interrupt should be indicated -//! but nothing else. -//! -//! @return The number for the highest priority interrupt available for the calling CPU. If -//! the return value is 1022 or 1023, a spurious interrupt has occurred. -uint32_t gic_read_irq_ack(void); - -//! @brief Signal the end of handling an interrupt. -//! -//! @param irq_id The number of the interrupt for which handling has finished. -void gic_write_end_of_irq(uint32_t irq_id); -//@} - -//! @} - -//////////////////////////////////////////////////////////////////////////////// -// EOF -//////////////////////////////////////////////////////////////////////////////// \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_registers.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_registers.h deleted file mode 100644 index 389d6a5b1..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_registers.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * - * Copyright (C) 2002 ARM Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/** - * @file gicv3_registers.h - * @brief gicv3 registers - * @version 1.0 - * @author AIIT XUOS Lab - * @date 2024.05.09 - */ - -/************************************************* -File name: gicv3_registers.c -Description: gicv3 registers -Others: -History: -Author: AIIT XUOS Lab -Modification: -1. Rename the file -*************************************************/ - -#pragma once - -#include "memlayout.h" - -// clang-format off -// interrupt controller GICv3 -#define GICV3 MMIO_P2V_WO(0xFD400000ULL) -#define GICV3_REDIST MMIO_P2V_WO(0xFD460000ULL) - -#define D_CTLR 0x0 -#define D_TYPER 0x4 -#define D_IGROUPR(n) (0x80 + (uint64_t)(n) * 4) -#define D_ISENABLER(n) (0x100 + (uint64_t)(n) * 4) -#define D_ICENABLER(n) (0x180 + (uint64_t)(n) * 4) -#define D_ISPENDR(n) (0x200 + (uint64_t)(n) * 4) -#define D_ICPENDR(n) (0x280 + (uint64_t)(n) * 4) -#define D_IPRIORITYR(n) (0x400 + (uint64_t)(n) * 4) -#define D_ITARGETSR(n) (0x800 + (uint64_t)(n) * 4) -#define D_ICFGR(n) (0xc00 + (uint64_t)(n) * 4) - -#define R_CTLR 0x0 -#define R_WAKER 0x14 - -#define SGI_BASE 0x10000 -#define R_IGROUPR0 (SGI_BASE + 0x80) -#define R_ISENABLER0 (SGI_BASE + 0x100) -#define R_ICENABLER0 (SGI_BASE + 0x180) -#define R_ICPENDR0 (SGI_BASE + 0x280) -#define R_IPRIORITYR(n) (SGI_BASE + 0x400 + (n) * 4) -#define R_ICFGR0 (SGI_BASE + 0xc00) -#define R_ICFGR1 (SGI_BASE + 0xc04) -#define R_IGRPMODR0 (SGI_BASE + 0xd00) -// clang-format on diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c index aa3546ee5..6a4ae7674 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c @@ -65,7 +65,6 @@ int plic_init(void) return 0; } - void plic_handle_irq(struct pt_regs *regs) { int hwirq; @@ -75,3 +74,18 @@ void plic_handle_irq(struct pt_regs *regs) //TODO csr_set(CSR_IE, IE_EIE); } + +void plic_init_hart(uint32_t cpu_id) +{ + ; +} + +uint32_t plic_read_irq_ack(void) +{ + return 0; +} + +void plic_write_end_of_irq(uint32_t x) +{ + ; +} diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h index 4ac98fc32..db627a4de 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h @@ -3,6 +3,7 @@ #include "memlayout.h" #include "ptrace.h" +#include #define PLIC_BASE PLIC_VIRTMEM_BASE @@ -16,5 +17,8 @@ int plic_init(void); void plic_enable_irq(int cpu, int hwirq, int enable); void plic_handle_irq(struct pt_regs *regs); +void plic_init_hart(uint32_t cpu_id); +uint32_t plic_read_irq_ack(void); +void plic_write_end_of_irq(uint32_t x); #endif /* _RISCV_PLIC_H */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c index 32c66ca5c..dda066780 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c @@ -97,7 +97,7 @@ void syscall_arch_handler(struct trapframe* tf) assert(cur_cpu()->task != NULL); ERROR("Error Task: %s\n", cur_cpu()->task->name); sys_exit(cur_cpu()->task); - context_switch(&cur_cpu()->task->thread_context.context, &cur_cpu()->scheduler); + context_switch(cur_cpu()->task->thread_context.context, &cur_cpu()->scheduler); panic("dabort end should never be reashed.\n"); } } @@ -157,7 +157,7 @@ struct fault_info { const char *name; }; -static const struct fault_info fault_inf[] = { +static struct fault_info fault_inf[] = { {do_trap_insn_misaligned, "Instruction address misaligned"}, {do_trap_insn_fault, "Instruction access fault"}, {do_trap_insn_illegal, "Illegal instruction"}, diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c index 1c9430251..35442bb23 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c @@ -31,7 +31,6 @@ Modification: #include "core.h" #include "cortex.h" #include "exception_registers.h" -#include "gicv3_common_opa.h" #include "trap_common.h" #include "log.h" @@ -57,7 +56,7 @@ static void _sys_irq_init(int cpu_id) if (cpu_id == 0) { plic_init(); } - gicv3inithart(cpu_id); + plic_init_hart(cpu_id); } static void _sys_trap_init(int cpu_id) @@ -90,7 +89,7 @@ static void _single_irq_disable(int irq, int cpu) static inline uintptr_t* _switch_hw_irqtbl(uintptr_t* new_tbl_base) { - trap_set_exception_vector(new_tbl_base); + trap_set_exception_vector((uintptr_t)new_tbl_base); return NULL; } @@ -102,7 +101,7 @@ static void _bind_irq_handler(int irq, irq_handler_t handler) static uint32_t _hw_before_irq() { - uint32_t iar = gic_read_irq_ack(); + uint32_t iar = plic_read_irq_ack(); return iar; } @@ -113,7 +112,7 @@ static uint32_t _hw_cur_int_num(uint32_t int_info) static void _hw_after_irq(uint32_t int_info) { - gic_write_end_of_irq(int_info); + plic_write_end_of_irq(int_info); } int _cur_cpu_id()