Debug MMU TLB

Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/asm.h

@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2015 Regents of the University of California
+ */
+
+#ifndef _ASM_RISCV_ASM_H
+#define _ASM_RISCV_ASM_H
+
+//#define __ASSEMBLY__
+
+#ifdef __ASSEMBLY__
+#define __ASM_STR(x)	x
+#else
+#define __ASM_STR(x)	#x
+#endif
+
+#if __riscv_xlen == 64
+#define __REG_SEL(a, b)	__ASM_STR(a)
+#elif __riscv_xlen == 32
+#define __REG_SEL(a, b)	__ASM_STR(b)
+#else
+#error "Unexpected __riscv_xlen"
+#endif
+
+#define REG_L		__REG_SEL(ld, lw)
+#define REG_S		__REG_SEL(sd, sw)
+#define REG_SC		__REG_SEL(sc.d, sc.w)
+#define REG_ASM		__REG_SEL(.dword, .word)
+#define SZREG		__REG_SEL(8, 4)
+#define LGREG		__REG_SEL(3, 2)
+
+
+#define RISCV_PTR		.dword
+#define RISCV_SZPTR		8
+#define RISCV_LGPTR		3
+
+
+#define RISCV_INT		__ASM_STR(.word)
+#define RISCV_SZINT		__ASM_STR(4)
+#define RISCV_LGINT		__ASM_STR(2)
+
+
+#define RISCV_SHORT		__ASM_STR(.half)
+#define RISCV_SZSHORT		__ASM_STR(2)
+#define RISCV_LGSHORT		__ASM_STR(1)
+
+
+#endif /* _ASM_RISCV_ASM_H */

Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/const.h

@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/* const.h: Macros for dealing with constants.  */
+
+#ifndef _UAPI_LINUX_CONST_H
+#define _UAPI_LINUX_CONST_H
+
+/* Some constant macros are used in both assembler and
+ * C code.  Therefore we cannot annotate them always with
+ * 'UL' and other type specifiers unilaterally.  We
+ * use the following macros to deal with this.
+ *
+ * Similarly, _AT() will cast an expression with a type in C, but
+ * leave it unchanged in asm.
+ */
+
+//#ifdef __ASSEMBLY__
+#if 0
+#define _AC(X,Y)	X
+#define _AT(T,X)	X
+#else
+#define __AC(X,Y)	(X##Y)
+#define _AC(X,Y)	__AC(X,Y)
+#define _AT(T,X)	((T)(X))
+#endif
+
+#define _UL(x)		(_AC(x, UL))
+#define _ULL(x)		(_AC(x, ULL))
+
+#define _BITUL(x)	(_UL(1) << (x))
+#define _BITULL(x)	(_ULL(1) << (x))
+
+#define __ALIGN_KERNEL(x, a)		__ALIGN_KERNEL_MASK(x, (typeof(x))(a) - 1)
+#define __ALIGN_KERNEL_MASK(x, mask)	(((x) + (mask)) & ~(mask))
+
+#define __KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
+
+#endif /* _UAPI_LINUX_CONST_H */

Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/csr.h

@@ -0,0 +1,294 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2015 Regents of the University of California
+ */
+
+#ifndef _ASM_RISCV_CSR_H
+#define _ASM_RISCV_CSR_H
+
+#include <asm/asm.h>
+#include <asm/const.h>
+
+#define CONFIG_64BIT
+
+/* Status register flags */
+#define SR_SIE		_AC(0x00000002, UL) /* Supervisor Interrupt Enable */
+#define SR_MIE		_AC(0x00000008, UL) /* Machine Interrupt Enable */
+#define SR_SPIE		_AC(0x00000020, UL) /* Previous Supervisor IE */
+#define SR_MPIE		_AC(0x00000080, UL) /* Previous Machine IE */
+#define SR_SPP		_AC(0x00000100, UL) /* Previously Supervisor */
+#define SR_MPP		_AC(0x00001800, UL) /* Previously Machine */
+#define SR_SUM		_AC(0x00040000, UL) /* Supervisor User Memory Access */
+
+#define SR_FS		_AC(0x00006000, UL) /* Floating-point Status */
+#define SR_FS_OFF	_AC(0x00000000, UL)
+#define SR_FS_INITIAL	_AC(0x00002000, UL)
+#define SR_FS_CLEAN	_AC(0x00004000, UL)
+#define SR_FS_DIRTY	_AC(0x00006000, UL)
+
+#define SR_XS		_AC(0x00018000, UL) /* Extension Status */
+#define SR_XS_OFF	_AC(0x00000000, UL)
+#define SR_XS_INITIAL	_AC(0x00008000, UL)
+#define SR_XS_CLEAN	_AC(0x00010000, UL)
+#define SR_XS_DIRTY	_AC(0x00018000, UL)
+
+#ifndef CONFIG_64BIT
+#define SR_SD		_AC(0x80000000, UL) /* FS/XS dirty */
+#else
+#define SR_SD		_AC(0x8000000000000000, UL) /* FS/XS dirty */
+#endif
+
+/* SATP flags */
+#ifndef CONFIG_64BIT
+#define SATP_PPN	_AC(0x003FFFFF, UL)
+#define SATP_MODE_32	_AC(0x80000000, UL)
+#define SATP_MODE	SATP_MODE_32
+#define SATP_ASID_BITS	9
+#define SATP_ASID_SHIFT	22
+#define SATP_ASID_MASK	_AC(0x1FF, UL)
+#else
+#define SATP_PPN	_AC(0x00000FFFFFFFFFFF, UL)
+#define SATP_MODE_39	_AC(0x8000000000000000, UL)
+#define SATP_MODE	SATP_MODE_39
+#define SATP_ASID_BITS	16
+#define SATP_ASID_SHIFT	44
+#define SATP_ASID_MASK	_AC(0xFFFF, UL)
+#endif
+
+/* Exception cause high bit - is an interrupt if set */
+#define CAUSE_IRQ_FLAG		(_AC(1, UL) << (__riscv_xlen - 1))
+
+/* Interrupt causes (minus the high bit) */
+#define IRQ_S_SOFT		1
+#define IRQ_M_SOFT		3
+#define IRQ_S_TIMER		5
+#define IRQ_M_TIMER		7
+#define IRQ_S_EXT		9
+#define IRQ_M_EXT		11
+#define IRQ_PMU_OVF		13
+
+/* Exception causes */
+#define EXC_INST_MISALIGNED	0
+#define EXC_INST_ACCESS		1
+#define EXC_BREAKPOINT		3
+#define EXC_LOAD_ACCESS		5
+#define EXC_STORE_ACCESS	7
+#define EXC_SYSCALL		8
+#define EXC_INST_PAGE_FAULT	12
+#define EXC_LOAD_PAGE_FAULT	13
+#define EXC_STORE_PAGE_FAULT	15
+
+/* PMP configuration */
+#define PMP_R			0x01
+#define PMP_W			0x02
+#define PMP_X			0x04
+#define PMP_A			0x18
+#define PMP_A_TOR		0x08
+#define PMP_A_NA4		0x10
+#define PMP_A_NAPOT		0x18
+#define PMP_L			0x80
+
+/* symbolic CSR names: */
+#define CSR_CYCLE		0xc00
+#define CSR_TIME		0xc01
+#define CSR_INSTRET		0xc02
+#define CSR_HPMCOUNTER3		0xc03
+#define CSR_HPMCOUNTER4		0xc04
+#define CSR_HPMCOUNTER5		0xc05
+#define CSR_HPMCOUNTER6		0xc06
+#define CSR_HPMCOUNTER7		0xc07
+#define CSR_HPMCOUNTER8		0xc08
+#define CSR_HPMCOUNTER9		0xc09
+#define CSR_HPMCOUNTER10	0xc0a
+#define CSR_HPMCOUNTER11	0xc0b
+#define CSR_HPMCOUNTER12	0xc0c
+#define CSR_HPMCOUNTER13	0xc0d
+#define CSR_HPMCOUNTER14	0xc0e
+#define CSR_HPMCOUNTER15	0xc0f
+#define CSR_HPMCOUNTER16	0xc10
+#define CSR_HPMCOUNTER17	0xc11
+#define CSR_HPMCOUNTER18	0xc12
+#define CSR_HPMCOUNTER19	0xc13
+#define CSR_HPMCOUNTER20	0xc14
+#define CSR_HPMCOUNTER21	0xc15
+#define CSR_HPMCOUNTER22	0xc16
+#define CSR_HPMCOUNTER23	0xc17
+#define CSR_HPMCOUNTER24	0xc18
+#define CSR_HPMCOUNTER25	0xc19
+#define CSR_HPMCOUNTER26	0xc1a
+#define CSR_HPMCOUNTER27	0xc1b
+#define CSR_HPMCOUNTER28	0xc1c
+#define CSR_HPMCOUNTER29	0xc1d
+#define CSR_HPMCOUNTER30	0xc1e
+#define CSR_HPMCOUNTER31	0xc1f
+#define CSR_CYCLEH		0xc80
+#define CSR_TIMEH		0xc81
+#define CSR_INSTRETH		0xc82
+#define CSR_HPMCOUNTER3H	0xc83
+#define CSR_HPMCOUNTER4H	0xc84
+#define CSR_HPMCOUNTER5H	0xc85
+#define CSR_HPMCOUNTER6H	0xc86
+#define CSR_HPMCOUNTER7H	0xc87
+#define CSR_HPMCOUNTER8H	0xc88
+#define CSR_HPMCOUNTER9H	0xc89
+#define CSR_HPMCOUNTER10H	0xc8a
+#define CSR_HPMCOUNTER11H	0xc8b
+#define CSR_HPMCOUNTER12H	0xc8c
+#define CSR_HPMCOUNTER13H	0xc8d
+#define CSR_HPMCOUNTER14H	0xc8e
+#define CSR_HPMCOUNTER15H	0xc8f
+#define CSR_HPMCOUNTER16H	0xc90
+#define CSR_HPMCOUNTER17H	0xc91
+#define CSR_HPMCOUNTER18H	0xc92
+#define CSR_HPMCOUNTER19H	0xc93
+#define CSR_HPMCOUNTER20H	0xc94
+#define CSR_HPMCOUNTER21H	0xc95
+#define CSR_HPMCOUNTER22H	0xc96
+#define CSR_HPMCOUNTER23H	0xc97
+#define CSR_HPMCOUNTER24H	0xc98
+#define CSR_HPMCOUNTER25H	0xc99
+#define CSR_HPMCOUNTER26H	0xc9a
+#define CSR_HPMCOUNTER27H	0xc9b
+#define CSR_HPMCOUNTER28H	0xc9c
+#define CSR_HPMCOUNTER29H	0xc9d
+#define CSR_HPMCOUNTER30H	0xc9e
+#define CSR_HPMCOUNTER31H	0xc9f
+
+#define CSR_SSCOUNTOVF		0xda0
+
+#define CSR_SSTATUS		0x100
+#define CSR_SIE			0x104
+#define CSR_STVEC		0x105
+#define CSR_SCOUNTEREN		0x106
+#define CSR_SSCRATCH		0x140
+#define CSR_SEPC		0x141
+#define CSR_SCAUSE		0x142
+#define CSR_STVAL		0x143
+#define CSR_SIP			0x144
+#define CSR_SATP		0x180
+
+#define CSR_MSTATUS		0x300
+#define CSR_MISA		0x301
+#define CSR_MIE			0x304
+#define CSR_MTVEC		0x305
+#define CSR_MSCRATCH		0x340
+#define CSR_MEPC		0x341
+#define CSR_MCAUSE		0x342
+#define CSR_MTVAL		0x343
+#define CSR_MIP			0x344
+#define CSR_PMPCFG0		0x3a0
+#define CSR_PMPADDR0		0x3b0
+#define CSR_MVENDORID		0xf11
+#define CSR_MARCHID		0xf12
+#define CSR_MIMPID		0xf13
+#define CSR_MHARTID		0xf14
+
+#ifdef CONFIG_RISCV_M_MODE
+# define CSR_STATUS	CSR_MSTATUS
+# define CSR_IE		CSR_MIE
+# define CSR_TVEC	CSR_MTVEC
+# define CSR_SCRATCH	CSR_MSCRATCH
+# define CSR_EPC	CSR_MEPC
+# define CSR_CAUSE	CSR_MCAUSE
+# define CSR_TVAL	CSR_MTVAL
+# define CSR_IP		CSR_MIP
+
+# define SR_IE		SR_MIE
+# define SR_PIE		SR_MPIE
+# define SR_PP		SR_MPP
+
+# define RV_IRQ_SOFT		IRQ_M_SOFT
+# define RV_IRQ_TIMER	IRQ_M_TIMER
+# define RV_IRQ_EXT		IRQ_M_EXT
+#else /* CONFIG_RISCV_M_MODE */
+# define CSR_STATUS	CSR_SSTATUS
+# define CSR_IE		CSR_SIE
+# define CSR_TVEC	CSR_STVEC
+# define CSR_SCRATCH	CSR_SSCRATCH
+# define CSR_EPC	CSR_SEPC
+# define CSR_CAUSE	CSR_SCAUSE
+# define CSR_TVAL	CSR_STVAL
+# define CSR_IP		CSR_SIP
+
+# define SR_IE		SR_SIE
+# define SR_PIE		SR_SPIE
+# define SR_PP		SR_SPP
+
+# define RV_IRQ_SOFT		IRQ_S_SOFT
+# define RV_IRQ_TIMER	IRQ_S_TIMER
+# define RV_IRQ_EXT		IRQ_S_EXT
+# define RV_IRQ_PMU	IRQ_PMU_OVF
+# define SIP_LCOFIP     (_AC(0x1, UL) << IRQ_PMU_OVF)
+
+#endif /* !CONFIG_RISCV_M_MODE */
+
+/* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */
+#define IE_SIE		(_AC(0x1, UL) << RV_IRQ_SOFT)
+#define IE_TIE		(_AC(0x1, UL) << RV_IRQ_TIMER)
+#define IE_EIE		(_AC(0x1, UL) << RV_IRQ_EXT)
+
+#ifndef __ASSEMBLY__
+
+#define csr_swap(csr, val)					\
+({								\
+	unsigned long __v = (unsigned long)(val);		\
+	__asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
+			      : "=r" (__v) : "rK" (__v)		\
+			      : "memory");			\
+	__v;							\
+})
+
+#define csr_read(csr)						\
+({								\
+	register unsigned long __v;				\
+	__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr)	\
+			      : "=r" (__v) :			\
+			      : "memory");			\
+	__v;							\
+})
+
+#define csr_write(csr, val)					\
+({								\
+	unsigned long __v = (unsigned long)(val);		\
+	__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0"	\
+			      : : "rK" (__v)			\
+			      : "memory");			\
+})
+
+#define csr_read_set(csr, val)					\
+({								\
+	unsigned long __v = (unsigned long)(val);		\
+	__asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
+			      : "=r" (__v) : "rK" (__v)		\
+			      : "memory");			\
+	__v;							\
+})
+
+#define csr_set(csr, val)					\
+({								\
+	unsigned long __v = (unsigned long)(val);		\
+	__asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0"	\
+			      : : "rK" (__v)			\
+			      : "memory");			\
+})
+
+#define csr_read_clear(csr, val)				\
+({								\
+	unsigned long __v = (unsigned long)(val);		\
+	__asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
+			      : "=r" (__v) : "rK" (__v)		\
+			      : "memory");			\
+	__v;							\
+})
+
+#define csr_clear(csr, val)					\
+({								\
+	unsigned long __v = (unsigned long)(val);		\
+	__asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0"	\
+			      : : "rK" (__v)			\
+			      : "memory");			\
+})
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_RISCV_CSR_H */

Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pgtable-bits.h

@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2012 Regents of the University of California
+ */
+
+#ifndef _ASM_RISCV_PGTABLE_BITS_H
+#define _ASM_RISCV_PGTABLE_BITS_H
+
+/*
+ * PTE format:
+ * | XLEN-1  10 | 9             8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
+ *       PFN      reserved for SW   D   A   G   U   X   W   R   V
+ */
+
+#define _PAGE_ACCESSED_OFFSET 6
+
+#define _PAGE_PRESENT   (1 << 0)
+#define _PAGE_READ      (1 << 1)    /* Readable */
+#define _PAGE_WRITE     (1 << 2)    /* Writable */
+#define _PAGE_EXEC      (1 << 3)    /* Executable */
+#define _PAGE_USER      (1 << 4)    /* User */
+#define _PAGE_GLOBAL    (1 << 5)    /* Global */
+#define _PAGE_ACCESSED  (1 << 6)    /* Set by hardware on any access */
+#define _PAGE_DIRTY     (1 << 7)    /* Set by hardware on any write */
+#define _PAGE_SOFT      (1 << 8)    /* Reserved for software */
+
+#define _PAGE_SPECIAL   _PAGE_SOFT
+#define _PAGE_TABLE     _PAGE_PRESENT
+
+/*
+ * _PAGE_PROT_NONE is set on not-present pages (and ignored by the hardware) to
+ * distinguish them from swapped out pages
+ */
+#define _PAGE_PROT_NONE _PAGE_READ
+
+#define _PAGE_PFN_SHIFT 10
+
+/* Set of bits to preserve across pte_modify() */
+#define _PAGE_CHG_MASK  (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ |	\
+					  _PAGE_WRITE | _PAGE_EXEC |	\
+					  _PAGE_USER | _PAGE_GLOBAL))
+/*
+ * when all of R/W/X are zero, the PTE is a pointer to the next level
+ * of the page table; otherwise, it is a leaf PTE.
+ */
+#define _PAGE_LEAF (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
+
+#endif /* _ASM_RISCV_PGTABLE_BITS_H */

Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S

@@ -10,8 +10,9 @@
  * See the Mulan PSL v2 for more details.
  */
 
-/* #include <asm/csr.h> */
+#include <asm/csr.h>
 #include "core.h"
+#include "memlayout.h"
 
 #define HCR_VALUE (1 << 31)
 #define SPSR_EL2_VALUE (7 << 6) | (5 << 0)
@@ -23,19 +24,60 @@
 
 
 _boot_start:
+    /* Mask all interrupts */
+    csrw CSR_IE, zero
+    csrw CSR_IP, zero
+
+    csrr t0, sstatus
+    srli t0, t0, 8
+    andi t0, t0, 1
+    beqz t0, switch_to_s_mode
+
+    j continue_execution
+
+    switch_to_s_mode:
+    li t2, 0x100
+    csrw sstatus, t2
+
+    j continue_execution
+
+continue_execution:
     j primary_cpu_init
-    j .
 
 primary_cpu_init:
     la t0, boot_start_addr
     la t1, boot_end_addr
     li t2, 0
-  
+
-clear_loop:
+clear_bss_sec:
-    bge t0, t1, clear_done
+    bge t0, t1, clear_bss_sec_done
     sb t2, 0(t0)
     addi t0, t0, 4
-    j clear_loop
+    j clear_bss_sec
-  
+
-clear_done:
+clear_bss_sec_done:
+
+	/* Clear BSS for flat non-ELF images */
+	la a3, __bss_start
+	la a4, __bss_end
+	ble a4, a3, clear_bss_done
+clear_bss:
+	sd zero, (a3)
+	add a3, a3, RISCV_SZPTR
+	blt a3, a4, clear_bss
+
+clear_bss_done:
+
     j bootmain
+
+/*
+.global enable_mmu_relocate
+enable_mmu_relocate:
+    la a2, boot_l2pgdir
+    srl a2, a2, PAGE_SHIFT
+    li a1, SATP_MODE
+    or a2, a2, a1
+    sfence.vma
+    csrw CSR_SATP, a2
+    ret
+*/

Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/config.mk

@@ -1,16 +1,15 @@
-# export CROSS_COMPILE ?= riscv64-linux-gnu-
 export CROSS_COMPILE ?= riscv64-unknown-elf-
 export ARCH = riscv
 
 # export KBUILD_CFLAGS := -Wall -Wundef -Werror=strict-prototypes -Wno-trigraphs -fno-strict-aliasing -fno-common -fshort-wchar -fno-PIE -Werror=implicit-function-declaration -Werror=implicit-int -Werror=return-type -Wno-format-security -std=gnu89 -Wno-sign-compare -fno-asynchronous-unwind-tables -fno-delete-null-pointer-checks -fno-stack-protector   -Wno-main   -fomit-frame-pointer   -Wdeclaration-after-statement -Wvla -Wno-pointer-sign   -Wno-array-bounds   -fno-strict-overflow -fno-stack-check -Werror=date-time
 export KBUILD_CFLAGS := -Wall -Wundef -Wno-trigraphs -fno-strict-aliasing -fno-common -fshort-wchar -fno-PIE -Werror=implicit-function-declaration -Werror=implicit-int -Werror=return-type -Wno-format-security -std=gnu89 -Wno-sign-compare -fno-asynchronous-unwind-tables -fno-delete-null-pointer-checks -fno-stack-protector   -Wno-main   -fomit-frame-pointer  -Wvla -Wno-pointer-sign   -Wno-array-bounds   -fno-strict-overflow -fno-stack-check -Werror=date-time    
 export KBUILD_CPPFLAGS := -D__KERNEL__  
-export KBUILD_AFLAGS := -D__ASSEMBLY__ -fno-PIE -m64 
+export KBUILD_AFLAGS :=
+export CHECKFLAGS += -D__riscv -D__riscv_xlen=64
 
 export DEVICE := 
-export CFLAGS := $(KBUILD_CFLAGS) -std=c11
+export CFLAGS := $(KBUILD_CFLAGS) $(KBUILD_AFLAGS) $(CHECKFLAGS) -std=c11
 # .vmlinux.cmd:1:cmd_vmlinux := sh scripts/link-vmlinux.sh "riscv64-linux-gnu-ld" " -melf64lriscv" " --build-id=sha1";
-#export LFLAGS := -melf64lriscv --build-id=sha1 $(KERNEL_ROOT)/hardkernel/arch/riscv/preboot_for_jh7110/jh7110.lds
 export LFLAGS := -T $(KERNEL_ROOT)/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds
 export CXXFLAGS := 
 

Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/cortex.S

@@ -16,10 +16,12 @@ Modification:
     .section ".text","ax"
 
     .global cpu_get_current
+
   # int cpu_get_current(void)@
   # get current CPU ID
     .func cpu_get_current
 cpu_get_current:
+    li a0, 0
     ret
     .endfunc
 

Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds

@@ -35,7 +35,7 @@
  * @author AIIT XUOS Lab
  * @date 2024.10.10
  */ 
-
+OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", "elf64-littleriscv")
 OUTPUT_ARCH(riscv)
 /* ENTRY(_start) */
 ENTRY( _boot_start )
@@ -43,17 +43,11 @@ ENTRY( _boot_start )
 BOOT_STACK_SIZE = 0x4000;
 MEMORY {
   phy_ddr3 (rwx)      : ORIGIN = 0x40200000, LENGTH = 1024M
-  vir_ddr3 (rwx)      : ORIGIN = 0x000000601040E000, LENGTH = 1024M
+  vir_ddr3 (rwx)      : ORIGIN = 0x0000000040800000, LENGTH = 1024M
 }
 
-
 SECTIONS
 {
-/* . = ((((-1))) - 0x80000000 + 1);
- _start = .;
- .head.text : AT(ADDR(.head.text) - ((((-1))) - 0x80000000 + 1)) { KEEP(*(.head.text)) }
-*/
-
   .start_sec : {
 	. = ORIGIN(phy_ddr3);
 	/* initialization start checkpoint. */
@@ -89,11 +83,12 @@ SECTIONS
 	PROVIDE(boot_end_addr = .);
   } > phy_ddr3
 
-  /* AT: 0x40200000 + 0x0041C000 */
+  /* AT: phy_ddr3 + .start_sec size */
-  .text : AT(0x4061C000) {
+  .text : AT(0x40800000) {
     . = ALIGN(0x1000);
     *(.text .text.* .gnu.linkonce.t.*)
-  }
+  } > vir_ddr3
+
   . = ALIGN(0x1000);
   .data : {
     *(.data .data.*)
@@ -112,17 +107,20 @@ SECTIONS
 		PROVIDE(_binary_default_fs_end = .);
     PROVIDE(__init_array_start = .);
     PROVIDE(__init_array_end = .);
-  }
+  } > vir_ddr3
+
+  . = ALIGN(0x1000);
+  _image_size = . - ORIGIN(phy_ddr3);
 
   . = ALIGN(0x1000);
   .bss : {
     PROVIDE(kernel_data_begin = .);
-    PROVIDE(__bss_start__ = .);
+    PROVIDE(__bss_start = .);
 		*(.bss .bss.* COMMON)
     . = ALIGN(0x1000);
-		PROVIDE(__bss_end__ = .);
+		PROVIDE(__bss_end = .);
 	  PROVIDE(kernel_data_end = .);
-  }
+  } > vir_ddr3
 
  . = ALIGN((1 << 21));
  .sdata : {

Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c

@@ -33,6 +33,8 @@ Modification:
 #include "pagetable.h"
 #include "registers.h"
 #include "ns16550.h"
+#include <asm/csr.h>
+#include <asm/pgtable-bits.h>
 
 #include <stdint.h>
 #include <string.h>
@@ -41,11 +43,9 @@ extern uint64_t kernel_data_end[];
 extern uint64_t kernel_data_begin[];
 
 // clang-format off
-#define L2_TYPE_TAB         2
+#define L2_PTE_VALID        (1 << 0)
-#define L2_PTE_VALID        1
 
-#define L3_TYPE_TAB         2
+#define L3_PTE_VALID        (1 << 0)
-#define L3_PTE_VALID        1
 
 #define L4_TYPE_PAGE        (3 << 0)
 #define L4_PTE_DEV          ((0b00) << 2) // Device memory
@@ -58,8 +58,18 @@ extern uint64_t kernel_data_begin[];
 
 #define IDX_MASK            (0b111111111)
 #define L3_PDE_INDEX(idx)   ((idx << LEVEL3_PDE_SHIFT) & L3_IDX_MASK)
-// clang-format on
 
+#define _PAGE_KERNEL		(_PAGE_READ \
+				| _PAGE_WRITE \
+				| _PAGE_PRESENT \
+				| _PAGE_ACCESSED \
+				| _PAGE_DIRTY \
+				| _PAGE_GLOBAL)
+#define PAGE_KERNEL		(_PAGE_KERNEL)
+#define PAGE_KERNEL_READ	(_PAGE_KERNEL & ~_PAGE_WRITE)
+#define PAGE_KERNEL_EXEC	(_PAGE_KERNEL | _PAGE_EXEC)
+
+// clang-format on
 uint64_t boot_l2pgdir[NUM_LEVEL2_PDE] __attribute__((aligned(0x1000))) = { 0 };
 
 uint64_t boot_dev_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 };
@@ -73,38 +83,33 @@ static void build_boot_pgdir()
     static bool built = false;
     if (!built) {
         uint64_t dev_phy_mem_base = DEV_PHYMEM_BASE;
+        uint64_t kern_phy_mem_base = PHY_MEM_BASE;
+        uint64_t cur_mem_paddr;
 
         // dev mem
-        boot_l2pgdir[(dev_phy_mem_base >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
+        boot_l2pgdir[(dev_phy_mem_base >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (((uint64_t)boot_dev_l3pgdir >> PAGE_SHIFT) << _PAGE_PFN_SHIFT) | _PAGE_TABLE;
-        boot_l2pgdir[(MMIO_P2V_WO(dev_phy_mem_base) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
+        boot_l2pgdir[(MMIO_P2V_WO(dev_phy_mem_base) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (((uint64_t)boot_dev_l3pgdir >> PAGE_SHIFT) << _PAGE_PFN_SHIFT) | _PAGE_TABLE;
 
-        uint64_t cur_mem_paddr = ALIGNDOWN((uint64_t)DEV_PHYMEM_BASE, LEVEL2_PDE_SIZE);
+        cur_mem_paddr = ALIGNDOWN(dev_phy_mem_base, LEVEL2_PDE_SIZE);
         for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) {
-            boot_dev_l3pgdir[i] = (uint64_t)boot_dev_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID;
+            boot_dev_l3pgdir[i] = (((uint64_t)boot_dev_l4pgdirs[i] >> PAGE_SHIFT) << _PAGE_PFN_SHIFT) | _PAGE_TABLE;
 
             for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) {
-                boot_dev_l4pgdirs[i][j] = cur_mem_paddr | L4_TYPE_PAGE | L4_PTE_DEV | L4_PTE_AF | L4_PTE_XN;
+                boot_dev_l4pgdirs[i][j] = ((cur_mem_paddr >> PAGE_SHIFT) << _PAGE_PFN_SHIFT) | PAGE_KERNEL;
-                if (cur_mem_paddr >= DEV_PHYMEM_BASE && cur_mem_paddr < DEV_PHYMEM_BASE + DEV_MEM_SIZE) {
-                    boot_dev_l4pgdirs[i][j] = cur_mem_paddr | 0x403;
-                } else {
-                    boot_dev_l4pgdirs[i][j] = cur_mem_paddr | 0x403;
-                }
-
                 cur_mem_paddr += PAGE_SIZE;
             }
         }
 
         // identical mem
-        boot_l2pgdir[(PHY_MEM_BASE >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
+        boot_l2pgdir[(kern_phy_mem_base >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (((uint64_t)boot_kern_l3pgdir >> PAGE_SHIFT) << _PAGE_PFN_SHIFT) | _PAGE_TABLE;
-        boot_l2pgdir[(P2V_WO(PHY_MEM_BASE) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
+        boot_l2pgdir[(P2V_WO(kern_phy_mem_base) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (((uint64_t)boot_kern_l3pgdir >> PAGE_SHIFT) << _PAGE_PFN_SHIFT) | _PAGE_TABLE;
 
-        cur_mem_paddr = ALIGNDOWN((uint64_t)0x00000000ULL, PAGE_SIZE);
+        cur_mem_paddr = ALIGNDOWN(kern_phy_mem_base, PAGE_SIZE);
         for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) {
-            boot_kern_l3pgdir[i] = (uint64_t)boot_kern_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID;
+            boot_kern_l3pgdir[i] = (((uint64_t)boot_kern_l4pgdirs[i] >> PAGE_SHIFT) << _PAGE_PFN_SHIFT)  | _PAGE_TABLE;
 
             for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) {
-                boot_kern_l4pgdirs[i][j] = cur_mem_paddr | 0x713;
+                boot_kern_l4pgdirs[i][j] = ((cur_mem_paddr >> PAGE_SHIFT) << _PAGE_PFN_SHIFT) | PAGE_KERNEL;
-
                 cur_mem_paddr += PAGE_SIZE;
             }
         }
@@ -113,39 +118,43 @@ static void build_boot_pgdir()
     }
 }
 
-static void load_boot_pgdir()
+static inline void local_flush_tlb_all(void)
 {
-
+    __asm__ __volatile__ ("sfence.vma" : : : "memory");
-    TTBR0_W((uintptr_t)boot_l2pgdir);
-    TTBR1_W(0);
-
-#define TCR_TRUE_VALUE (0x0000000080813519ULL)
-    uint64_t tcr = 0;
-    TCR_R(tcr);
-    tcr &= (uint64_t)~0xFF;
-    tcr |= 0x19;
-    TCR_W(tcr);
-
-    CLEARTLB(0);
-    ISB();
 }
 
+static void load_boot_pgdir()
+{
+    unsigned long satp_val = (unsigned long)(((uintptr_t)boot_l2pgdir >> PAGE_SHIFT) | SATP_MODE);
+    unsigned long status;
+
+    status = csr_read(CSR_STATUS);
+    if( !(status & 0x100) ) {
+        _debug_uart_printascii("current is not S mode\n");
+    }
+#if 0    //to debug
+    csr_write(CSR_SATP, ((uintptr_t)boot_l2pgdir >> PAGE_SHIFT) | SATP_MODE);
+#endif
+}
 
 extern void main(void);
 static bool _bss_inited = false;
 void bootmain()
 {
     _debug_uart_init();
-#if 0
+    _debug_uart_printascii("bootmain start.\n");
+
     build_boot_pgdir();
     load_boot_pgdir();
-//    __asm__ __volatile__("add sp, sp, %0" ::"r"(KERN_OFFSET));
+//    _debug_uart_base_map();
+    _debug_uart_printascii("boot pgdir success\n");
+
+    __asm__ __volatile__("addi sp, sp, %0" ::"i"(KERN_OFFSET));
     if (!_bss_inited) {
         memset(&kernel_data_begin, 0x00, (size_t)((uint64_t)kernel_data_end - (uint64_t)kernel_data_begin));
         _bss_inited = true;
     }
 
     main();
-#endif
 }
 

Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h

@@ -15,7 +15,7 @@
  * @brief virtual memory and physical memory layout
  * @version 1.0
  * @author AIIT XUOS Lab
- * @date 2024-04-25
+ * @date 2024-10-31
  */
 /*************************************************
 File name: memlayout.h
@@ -33,11 +33,11 @@ Modification:
 
 #define ARCH_BIT        64
 
-/* A55 physical memory layout */
+/* physical memory layout */
-#define PHY_MEM_BASE            (0x0000000010000000ULL)
+#define PHY_MEM_BASE            (0x0000000040200000ULL)
-#define PHY_USER_FREEMEM_BASE   (0x0000000040000000ULL)
+#define PHY_USER_FREEMEM_BASE   (0x0000000080000000ULL)
-#define PHY_USER_FREEMEM_TOP    (0x00000000e0000000ULL)
+#define PHY_USER_FREEMEM_TOP    (0x00000000F0000000ULL)
-#define PHY_MEM_STOP            (0x00000000e0000000ULL)
+#define PHY_MEM_STOP            (0x00000000F0000000ULL)
 
 /* PTE-PAGE_SIZE */
 #define LEVEL4_PTE_SHIFT    12
@@ -57,24 +57,25 @@ Modification:
 #define NUM_LEVEL4_PTE      (1 << (LEVEL3_PDE_SHIFT - LEVEL4_PTE_SHIFT)) // how many PTE in a PT
 #define NUM_TOPLEVEL_PDE    NUM_LEVEL2_PDE 
 
+#define PAGE_SHIFT          LEVEL4_PTE_SHIFT
 #define PAGE_SIZE           LEVEL4_PTE_SIZE
 #define MAX_NR_FREE_PAGES   ((PHY_USER_FREEMEM_BASE - PHY_MEM_BASE) >> LEVEL4_PTE_SHIFT)
 
 /* Deivce memory layout */
-#define DEV_PHYMEM_BASE     (0x00000000F0000000ULL)
+#define DEV_PHYMEM_BASE     (0x0000000010000000ULL)
-#define DEV_VRTMEM_BASE     (0x00000040F0000000ULL)
+#define DEV_VRTMEM_BASE     (0x0000001010000000ULL)
-#define DEV_MEM_SIZE        (0x0000000010000000ULL)
+#define DEV_MEM_SIZE        (0x0000000030040000ULL)
 
 /* User memory layout */
 #define USER_STACK_SIZE     PAGE_SIZE
-#define USER_MEM_BASE       (0x0000000000000000ULL)
+#define USER_MEM_BASE       (0x0000002000000000ULL)
-#define USER_MEM_TOP        (0x0000004000000000ULL)
+#define USER_MEM_TOP        (0x0000008000000000ULL)
 #define USER_IPC_SPACE_BASE (0x0000003000000000ULL)
 #define USER_IPC_USE_ALLOCATOR_WATERMARK    (0x0000003000010000ULL)
 #define USER_IPC_SPACE_TOP  (USER_IPC_SPACE_BASE + 0x10000000ULL) 
 
 /* Kernel memory layout */
-#define KERN_MEM_BASE       (0x0000006010000000ULL) // First kernel virtual address
+#define KERN_MEM_BASE       (0x0000000000000000ULL + PHY_MEM_BASE) // First kernel virtual address
 #define KERN_OFFSET         (KERN_MEM_BASE - PHY_MEM_BASE)
 
 #define V2P(a) (((uint64_t)(a)) - KERN_OFFSET)

Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h

@@ -214,5 +214,6 @@ void _debug_uart_init(void);
 void _debug_uart_putc(int ch);
 int _debug_uart_getc(void);
 void _debug_uart_printascii(const char *str);
+void _debug_uart_base_map(void);
 
 #endif /* __ns16550_h */

Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c

@@ -5,6 +5,7 @@
  */
 
 #include <ns16550.h>
+#include "mmio_access.h"
 
 struct ns16550 g_ns16550_com_port = {0};
 struct ns16550_plat g_ns16550_plat = {0};
@@ -12,7 +13,7 @@ struct ns16550_plat g_ns16550_plat = {0};
 #define CONFIG_SYS_NS16550_UART_BASE	0x10000000
 #define CONFIG_BAUDRATE					115200
 #define CONFIG_SYS_NS16550_CLK			24000000
-
+#define CONFIG_SYS_NS16550_UART_BASE_MAP	 MMIO_P2V_WO(CONFIG_SYS_NS16550_UART_BASE)
 
 #define UART_LCRVAL UART_LCR_8N1		/* 8 data, 1 stop, no parity */
 #define UART_MCRVAL (UART_MCR_DTR | \
@@ -136,11 +137,7 @@ int ns16550_tstc(struct ns16550 *com_port)
 
 static int ns16550_serial_assign_base(struct ns16550_plat *plat, unsigned long base)
 {
-#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
 	plat->base = base;
-#else
-	plat->base = (unsigned long)map_physmem(base, 0, MAP_NOCACHE);
-#endif
 	return 0;
 }
 
@@ -180,7 +177,6 @@ static void ns16550_serial_setbrg(int baudrate)
 	ns16550_setbrg(com_port, clock_divisor);
 }
 
-
 void _debug_uart_init(void)
 {
 	int baudrate = CONFIG_BAUDRATE;
@@ -190,9 +186,21 @@ void _debug_uart_init(void)
 	_debug_uart_printascii("_debug_uart_init success.\n");
 }
 
+void _debug_uart_base_map(void)
+{
+	struct ns16550_plat *plat = &g_ns16550_plat;
+	unsigned long  addr;
+
+	addr = CONFIG_SYS_NS16550_UART_BASE_MAP;
+	ns16550_serial_assign_base(plat, addr);
+	_debug_uart_printascii("_debug_uart_init_mapped success.\n");
+}
+
 void _debug_uart_putc(int ch)
 {
     struct ns16550* com_port = &g_ns16550_com_port;
+    if (ch == '\n')
+        ns16550_putc(com_port, '\r');
     ns16550_putc(com_port, ch);
 }
 
@@ -213,4 +221,4 @@ void _debug_uart_printascii(const char *str)
 {
 	while (*str)
 		_printch(*str++);
-}
+}

Ubiquitous/XiZi_AIoT/path_kernel.mk

@@ -56,8 +56,9 @@ endif
 
 ifeq ($(BOARD), jh7110)
 KERNELPATHS += \
-	-I$(KERNEL_ROOT)/hardkernel/arch/riscv/rv64gc/preboot_for_$(BOARD)/include \
 	-I$(KERNEL_ROOT)/hardkernel/arch/riscv/rv64gc/ \
+	-I$(KERNEL_ROOT)/hardkernel/arch/riscv/rv64gc/include \
+	-I$(KERNEL_ROOT)/hardkernel/arch/riscv/rv64gc/preboot_for_$(BOARD)/include \
 	-I$(KERNEL_ROOT)/hardkernel/cache/L1/riscv/rv64gc/ \
 	-I$(KERNEL_ROOT)/hardkernel/clock/riscv/rv64gc/$(BOARD)/include \
 	-I$(KERNEL_ROOT)/hardkernel/intr/riscv/rv64gc/ \