Modify plic

Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/clock.c

@@ -11,40 +11,25 @@
  */
 #include "actracer.h"
 #include "core.h"
-#include "generic_timer.h"
 
 #include "clock_common_op.h"
 #include "clint.h"
 
-
+//TODO:
-// armv8 generic timer driver
-#define CNTV_CTL_ENABLE (1 << 0)
-#define CNTV_CTL_IMASK (1 << 1)
-#define CNTV_CTL_ISTATUS (1 << 2)
-
 static void enable_timer()
 {
-    uint32_t c = r_cntp_ctl_el0();
+    ;
-    c |= CNTV_CTL_ENABLE;
-    c &= ~CNTV_CTL_IMASK;
-    w_cntp_ctl_el0(c);
 }
 
 static void disable_timer()
 {
-    uint32_t c = r_cntp_ctl_el0();
+    ;
-    c |= CNTV_CTL_IMASK;
-    c &= ~CNTV_CTL_ENABLE;
-    w_cntp_ctl_el0(c);
 }
 
 static void reload_timer()
 {
     // interval 1ms
-    static uint32_t ms = 1;
+    ;
-    uint32_t interval = ms * 1000;
-    uint32_t interval_clk = interval * (r_cntfrq_el0() / 1000000);
-    w_cntp_tval_el0(interval_clk);
 }
 
 
@@ -63,12 +48,12 @@ static uint32_t _get_clock_int()
 
 static uint64_t _get_tick()
 {
-    return r_cntvct_el0();
+    return 0;
 }
 
 static uint64_t _get_second()
 {
-    return _get_tick() / r_cntfrq_el0();
+    return 0;
 }
 
 static bool _is_timer_expired()

Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/include/generic_timer.h

@@ -1,54 +0,0 @@
-/*
- * Copyright (c) 2020 AIIT XUOS Lab
- * XiUOS is licensed under Mulan PSL v2.
- * You can use this software according to the terms and conditions of the Mulan PSL v2.
- * You may obtain a copy of Mulan PSL v2 at:
- *        http://license.coscl.org.cn/MulanPSL2
- * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
- * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
- * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
- * See the Mulan PSL v2 for more details.
- */
-#pragma once
-
-#include <stddef.h>
-#include <stdint.h>
-
-// armv8 generic timer
-static inline uint32_t r_cntp_ctl_el0()
-{
-    uint32_t x;
-//    __asm__ volatile("mrs %0, cntp_ctl_el0" : "=r"(x));
-    return x;
-}
-
-static inline void w_cntp_ctl_el0(uint32_t x)
-{
-//    __asm__ volatile("msr cntp_ctl_el0, %0" : : "r"(x));
-}
-
-static inline uint32_t r_cntp_tval_el0()
-{
-    uint32_t x;
-//    __asm__ volatile("mrs %0, cntp_tval_el0" : "=r"(x));
-    return x;
-}
-
-static inline void w_cntp_tval_el0(uint32_t x)
-{
-//    __asm__ volatile("msr cntp_tval_el0, %0" : : "r"(x));
-}
-
-static inline uint64_t r_cntvct_el0()
-{
-    uint64_t x;
-//    __asm__ volatile("mrs %0, cntvct_el0" : "=r"(x));
-    return x;
-}
-
-static inline uint32_t r_cntfrq_el0()
-{
-    uint32_t x;
-//    __asm__ volatile("mrs %0, cntfrq_el0" : "=r"(x));
-    return x;
-}

Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/error_debug.c

@@ -41,8 +41,6 @@ Modification:
 #include <stddef.h>
 #include <stdint.h>
 
-#include "exception_registers.h"
-
 #include "assert.h"
 #include "core.h"
 #include "log.h"

Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/exception_registers.h

@@ -1,68 +0,0 @@
-/*
- * Copyright (c) 2020 AIIT XUOS Lab
- * XiUOS is licensed under Mulan PSL v2.
- * You can use this software according to the terms and conditions of the Mulan PSL v2.
- * You may obtain a copy of Mulan PSL v2 at:
- *        http://license.coscl.org.cn/MulanPSL2
- * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
- * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
- * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
- * See the Mulan PSL v2 for more details.
- */
-/**
- * @file exception_registers.h
- * @brief exception registers
- * @version 1.0
- * @author AIIT XUOS Lab
- * @date 2024.05.09
- */
-
-static inline void w_vbar_el1(uint64_t x)
-{
-//    __asm__ volatile("msr vbar_el1, %0" : : "r"(x));
-}
-
-static inline uint64_t r_esr_el1()
-{
-    uint64_t x;
-//    __asm__ volatile("mrs %0, esr_el1" : "=r"(x));
-    return x;
-}
-
-static inline void w_esr_el1(uint64_t x)
-{
-//    __asm__ volatile("msr esr_el1, %0" : : "r"(x));
-}
-
-static inline uint64_t r_elr_el1()
-{
-    uint64_t x;
-//    __asm__ volatile("mrs %0, elr_el1" : "=r"(x));
-    return x;
-}
-
-static inline uint64_t r_far_el1()
-{
-    uint64_t x;
-//    __asm__ volatile("mrs %0, far_el1" : "=r"(x));
-    return x;
-}
-
-static inline uint64_t daif()
-{
-    uint64_t x;
-//    __asm__ volatile("mrs %0, daif" : "=r"(x));
-    return x;
-}
-
-// enable interrupts(irq)
-static inline void intr_on()
-{
-//    __asm__ volatile("msr daifclr, #0xf" ::: "memory");
-}
-
-// disable interrupts(irq)
-static inline void intr_off()
-{
-//    __asm__ volatile("msr daifset, #0xf" ::: "memory");
-}

Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c

@@ -20,20 +20,25 @@ extern unsigned long boot_cpu_hartid;
 #define CPU_TO_HART(cpu) ((2 * cpu) + 2)
 
 
+//TODO: to debug
 void plic_set_priority(int hwirq, int pro)
 {
+#if 0
     unsigned int reg = PLIC_PRIORITY(hwirq);
     writel(pro, reg);
+#endif
 }
 
+//TODO: to debug
 void plic_enable_irq(int cpu, int hwirq, int enable)
 {
+#if 0
     unsigned int hwirq_mask = 1 << (hwirq % 32);
     int hart = CPU_TO_HART(cpu);
     unsigned int reg = PLIC_MENABLE(hart) + 4 * (hwirq / 32);
 
 //    printk("plic_enable_irq hwirq=%d\n", hwirq);
-#if 0
+
     if (enable) {
         writel(readl(reg) | hwirq_mask, reg);
     }
@@ -47,11 +52,12 @@ void plic_enable_irq(int cpu, int hwirq, int enable)
 //Refer to linux/drivers/irqchip/irq-sifive-plic.c
 int plic_init(void)
 {
+#if 0
     int i;
     int hwirq;
 
 //    printk("plic_init boot_cpu_hartid=%lu\n", boot_cpu_hartid);
-#if 0
+
     for (i = 0; i < MAX_CPUS; i++) {
         writel(0, PLIC_MTHRESHOLD(CPU_TO_HART(i)));
 
@@ -67,12 +73,14 @@ int plic_init(void)
 
 void plic_handle_irq(struct pt_regs *regs)
 {
+#if 0
     int hwirq;
     int hart = CPU_TO_HART(0);
     unsigned int claim_reg = PLIC_MCLAIM(hart);
     csr_clear(CSR_IE, IE_EIE);
     //TODO
     csr_set(CSR_IE, IE_EIE);
+#endif
 }
 
 void plic_init_hart(uint32_t cpu_id)
@@ -89,3 +97,13 @@ void plic_write_end_of_irq(uint32_t x)
 {
     ;
 }
+
+void intr_on(void)
+{
+    ;
+}
+
+void intr_off(void)
+{
+    ;
+}

Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h

@@ -20,5 +20,7 @@ void plic_handle_irq(struct pt_regs *regs);
 void plic_init_hart(uint32_t cpu_id);
 uint32_t plic_read_irq_ack(void);
 void plic_write_end_of_irq(uint32_t x);
+void intr_on(void);
+void intr_off(void);
 
 #endif /* _RISCV_PLIC_H */

Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c

@@ -28,8 +28,6 @@ Modification:
 *************************************************/
 #include <stdint.h>
 
-#include "exception_registers.h"
-
 #include "assert.h"
 #include "core.h"
 #include "multicores.h"
@@ -48,21 +46,25 @@ extern void iabort_handler(struct trapframe* r);
 
 void kernel_abort_handler(struct trapframe* tf)
 {
-    uint64_t esr = r_esr_el1();
+    uint64_t ec = tf->cause;
-    switch ((esr >> 0x1A) & 0x3F) {
+
-    case 0b100100:
+    switch (ec) {
-    case 0b100101:
+    case 0:
-        dabort_handler(tf);
+    case 1:
-        break;
+    case 2:
-    case 0b100000:
+    case 12:
-    case 0b100001:
         iabort_handler(tf);
         break;
+    case 4:
+    case 5:
+    case 6:
+    case 7:
+    case 13:
+    case 15:
+        dabort_handler(tf);
+        break;
     default: {
-        uint64_t ec = (esr >> 26) & 0x3f;
+        ERROR("tf->cause: %016lx\n", tf->cause);
-        uint64_t iss = esr & 0x1ffffff;
-        ERROR("esr:  %016lx %016lx %016lx\n", esr, ec, iss);
-        ERROR("elr = %016lx far = %016lx\n", r_elr_el1(), r_far_el1());
         ERROR("Current Task: %s.\n", cur_cpu()->task->name);
         panic("Unimplemented Error Occured.\n");
     }

Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c

@@ -30,7 +30,7 @@ Modification:
 
 #include "core.h"
 #include "cortex.h"
-#include "exception_registers.h"
+
 #include "trap_common.h"
 
 #include "log.h"