From 0fa8ff53684a8d2bd7a11cd5efdc3a2551129fa7 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Mon, 7 Apr 2025 17:44:27 +0800 Subject: [PATCH] Add ch569 SRC from CH569EVT.ZIP --- .../arch/risc-v/ch569w/RVMSIS/core_riscv.c | 334 +++ .../arch/risc-v/ch569w/RVMSIS/core_riscv.h | 591 ++++ .../Peripheral/inc/CH56xSFR.h | 2528 +++++++++++++++++ .../Peripheral/inc/CH56x_bus8.h | 48 + .../Peripheral/inc/CH56x_clk.h | 44 + .../Peripheral/inc/CH56x_common.h | 62 + .../Peripheral/inc/CH56x_dvp.h | 72 + .../Peripheral/inc/CH56x_ecdc.h | 67 + .../Peripheral/inc/CH56x_emmc.h | 147 + .../Peripheral/inc/CH56x_eth.h | 1942 +++++++++++++ .../Peripheral/inc/CH56x_gpio.h | 144 + .../Peripheral/inc/CH56x_hspi.h | 43 + .../Peripheral/inc/CH56x_pwm.h | 70 + .../Peripheral/inc/CH56x_pwr.h | 59 + .../Peripheral/inc/CH56x_spi.h | 118 + .../Peripheral/inc/CH56x_sys.h | 64 + .../Peripheral/inc/CH56x_timer.h | 155 + .../Peripheral/inc/CH56x_uart.h | 136 + .../Peripheral/src/CH56x_bus8.c | 57 + .../Peripheral/src/CH56x_clk.c | 115 + .../Peripheral/src/CH56x_dvp.c | 132 + .../Peripheral/src/CH56x_ecdc.c | 182 ++ .../Peripheral/src/CH56x_emmc.c | 870 ++++++ .../Peripheral/src/CH56x_eth.c | 315 ++ .../Peripheral/src/CH56x_gpio.c | 523 ++++ .../Peripheral/src/CH56x_hspi.c | 75 + .../Peripheral/src/CH56x_pwm.c | 76 + .../Peripheral/src/CH56x_pwr.c | 173 ++ .../Peripheral/src/CH56x_spi.c | 579 ++++ .../Peripheral/src/CH56x_sys.c | 198 ++ .../Peripheral/src/CH56x_timer.c | 269 ++ .../Peripheral/src/CH56x_uart.c | 548 ++++ 32 files changed, 10736 insertions(+) create mode 100644 Ubiquitous/XiZi_IIoT/arch/risc-v/ch569w/RVMSIS/core_riscv.c create mode 100644 Ubiquitous/XiZi_IIoT/arch/risc-v/ch569w/RVMSIS/core_riscv.h create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56xSFR.h create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_bus8.h create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_clk.h create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_common.h create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_dvp.h create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_ecdc.h create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_emmc.h create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_eth.h create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_gpio.h create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_hspi.h create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_pwm.h create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_pwr.h create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_spi.h create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_sys.h create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_timer.h create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_uart.h create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_bus8.c create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_clk.c create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_dvp.c create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_ecdc.c create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_emmc.c create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_eth.c create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_gpio.c create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_hspi.c create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_pwm.c create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_pwr.c create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_spi.c create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_sys.c create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_timer.c create mode 100644 Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_uart.c diff --git a/Ubiquitous/XiZi_IIoT/arch/risc-v/ch569w/RVMSIS/core_riscv.c b/Ubiquitous/XiZi_IIoT/arch/risc-v/ch569w/RVMSIS/core_riscv.c new file mode 100644 index 000000000..6b9ea37b1 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/arch/risc-v/ch569w/RVMSIS/core_riscv.c @@ -0,0 +1,334 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : core_riscv.c +* Author : WCH +* Version : V1.0.1 +* Date : 2023/11/11 +* Description : RISC-V V3 Core Peripheral Access Layer Source File for CH56x +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/********************************************************************* + * @fn __get_MSTATUS + * + * @brief Return the Machine Status Register + * + * @return mstatus value + */ +uint32_t __get_MSTATUS(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mstatus" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MSTATUS + * + * @brief Set the Machine Status Register + * + * @param value - set mstatus value + * + * @return none + */ +void __set_MSTATUS(uint32_t value) +{ + __ASM volatile ("csrw mstatus, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MISA + * + * @brief Return the Machine ISA Register + * + * @return misa value + */ +uint32_t __get_MISA(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "misa" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MISA + * + * @brief Set the Machine ISA Register + * + * @param value - set misa value + * + * @return none + */ +void __set_MISA(uint32_t value) +{ + __ASM volatile ("csrw misa, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MIE + * + * @brief Return the Machine Interrupt Enable Register + * + * @return mie value + */ +uint32_t __get_MIE(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mie" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MISA + * + * @brief Set the Machine ISA Register + * + * @param value - set mie value + * + * @return none + */ +void __set_MIE(uint32_t value) +{ + __ASM volatile ("csrw mie, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MTVEC + * + * @brief Return the Machine Trap-Vector Base-Address Register + * + * @return mtvec value + */ +uint32_t __get_MTVEC(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mtvec" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MTVEC + * + * @brief Set the Machine Trap-Vector Base-Address Register + * + * @param value - set mtvec value + * + * @return none + */ +void __set_MTVEC(uint32_t value) +{ + __ASM volatile ("csrw mtvec, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MSCRATCH + * + * @brief Return the Machine Seratch Register + * + * @return mscratch value + */ +uint32_t __get_MSCRATCH(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mscratch" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MSCRATCH + * + * @brief Set the Machine Seratch Register + * + * @param value - set mscratch value + * + * @return none + */ +void __set_MSCRATCH(uint32_t value) +{ + __ASM volatile ("csrw mscratch, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MEPC + * + * @brief Return the Machine Exception Program Register + * + * @return mepc value + */ +uint32_t __get_MEPC(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mepc" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Exception Program Register + * + * @return mepc value + */ +void __set_MEPC(uint32_t value) +{ + __ASM volatile ("csrw mepc, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MCAUSE + * + * @brief Return the Machine Cause Register + * + * @return mcause value + */ +uint32_t __get_MCAUSE(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mcause" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Cause Register + * + * @return mcause value + */ +void __set_MCAUSE(uint32_t value) +{ + __ASM volatile ("csrw mcause, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MTVAL + * + * @brief Return the Machine Trap Value Register + * + * @return mtval value + */ +uint32_t __get_MTVAL(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mtval" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MTVAL + * + * @brief Set the Machine Trap Value Register + * + * @return mtval value + */ +void __set_MTVAL(uint32_t value) +{ + __ASM volatile ("csrw mtval, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MVENDORID + * + * @brief Return Vendor ID Register + * + * @return mvendorid value + */ +uint32_t __get_MVENDORID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MARCHID + * + * @brief Return Machine Architecture ID Register + * + * @return marchid value + */ +uint32_t __get_MARCHID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "marchid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MIMPID + * + * @brief Return Machine Implementation ID Register + * + * @return mimpid value + */ +uint32_t __get_MIMPID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mimpid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MHARTID + * + * @brief Return Hart ID Register + * + * @return mhartid value + */ +uint32_t __get_MHARTID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mhartid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_SP + * + * @brief Return SP Register + * + * @return SP value + */ +uint32_t __get_SP(void) +{ + uint32_t result; + + asm volatile ( "mv %0," "sp" : "=r"(result) : ); + return (result); +} + diff --git a/Ubiquitous/XiZi_IIoT/arch/risc-v/ch569w/RVMSIS/core_riscv.h b/Ubiquitous/XiZi_IIoT/arch/risc-v/ch569w/RVMSIS/core_riscv.h new file mode 100644 index 000000000..1a36561a6 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/arch/risc-v/ch569w/RVMSIS/core_riscv.h @@ -0,0 +1,591 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : core_riscv.h +* Author : WCH +* Version : V1.0.1 +* Date : 2023/11/11 +* Description : RISC-V V3 Core Peripheral Access Layer Header File for CH56x +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CORE_RISCV_H__ +#define __CORE_RISCV_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include +#include "CH56xSFR.H" + +/* IO definitions */ +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ +#define RV_STATIC_INLINE static inline + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ +typedef struct __attribute__((packed)) { + __I UINT32 ISR[8]; + __I UINT32 IPR[8]; + __IO UINT32 ITHRESDR; + __IO UINT32 VTFBADDRR; + __IO UINT32 CFGR; + __I UINT32 GISR; + UINT8 RESERVED0[0x10]; + __IO UINT32 VTFADDRR[4]; + UINT8 RESERVED1[0x90]; + __O UINT32 IENR[8]; + UINT8 RESERVED2[0x60]; + __O UINT32 IRER[8]; + UINT8 RESERVED3[0x60]; + __O UINT32 IPSR[8]; + UINT8 RESERVED4[0x60]; + __O UINT32 IPRR[8]; + UINT8 RESERVED5[0x60]; + __IO UINT32 IACTR[8]; + UINT8 RESERVED6[0xE0]; + __IO UINT8 IPRIOR[256]; + UINT8 RESERVED7[0x810]; + __IO UINT32 SCTLR; +}PFIC_Type; + +#define FIBADDRR VTFBADDRR +#define FIOFADDRR VTFADDRR + + +/* memory mapped structure for SysTick */ +typedef struct __attribute__((packed)) +{ + __IO UINT32 CTLR; + __IO UINT64 CNT; + __IO UINT64 CMP; + __IO UINT32 CNTFG; +}SysTick_Type; + + +#define PFIC ((PFIC_Type *) 0xE000E000 ) +#define SysTick ((SysTick_Type *) 0xE000F000) + +#define PFIC_KEY1 ((UINT32)0xFA050000) +#define PFIC_KEY2 ((UINT32)0xBCAF0000) +#define PFIC_KEY3 ((UINT32)0xBEEF0000) + +/********************************************************************* + * @fn __enable_irq + * This function is only used for Machine mode. + * + * @brief Enable Global Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq() +{ + __asm volatile ("csrs mstatus, %0" : : "r" (0x88) ); +} + +/********************************************************************* + * @fn __disable_irq + * This function is only used for Machine mode. + * + * @brief Disable Global Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq() +{ + __asm volatile ("csrc mstatus, %0" : : "r" (0x88) ); +} + +/********************************************************************* + * @fn __NOP + * + * @brief nop + * + * @return none + */ +RV_STATIC_INLINE void __NOP() +{ + __asm volatile ("nop"); +} + +/********************************************************************* + * @fn PFIC_EnableIRQ + * + * @brief Enable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +RV_STATIC_INLINE void PFIC_EnableIRQ(IRQn_Type IRQn) +{ + PFIC->IENR[((UINT32)(IRQn) >> 5)] = (1 << ((UINT32)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn PFIC_DisableIRQ + * + * @brief Disable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +RV_STATIC_INLINE void PFIC_DisableIRQ(IRQn_Type IRQn) +{ + UINT32 t; + + t = PFIC->ITHRESDR; + PFIC->ITHRESDR = 0x10; + PFIC->IRER[((UINT32)(IRQn) >> 5)] = (1 << ((UINT32)(IRQn) & 0x1F)); + PFIC->ITHRESDR = t; +} + +/********************************************************************* + * @fn PFIC_GetStatusIRQ + * + * @brief Get Interrupt Enable State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Enable + * 0 - Interrupt Disable + */ +RV_STATIC_INLINE UINT32 PFIC_GetStatusIRQ(IRQn_Type IRQn) +{ + return((UINT32) ((PFIC->ISR[(UINT32)(IRQn) >> 5] & (1 << ((UINT32)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn PFIC_GetPendingIRQ + * + * @brief Get Interrupt Pending State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Pending Enable + * 0 - Interrupt Pending Disable + */ +RV_STATIC_INLINE UINT32 PFIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((UINT32) ((PFIC->IPR[(UINT32)(IRQn) >> 5] & (1 << ((UINT32)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn PFIC_SetPendingIRQ + * + * @brief Set Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +RV_STATIC_INLINE void PFIC_SetPendingIRQ(IRQn_Type IRQn){ + PFIC->IPSR[((UINT32)(IRQn) >> 5)] = (1 << ((UINT32)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn PFIC_ClearPendingIRQ + * + * @brief Clear Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +RV_STATIC_INLINE void PFIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + PFIC->IPRR[((UINT32)(IRQn) >> 5)] = (1 << ((UINT32)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn PFIC_GetActive + * + * @brief Get Interrupt Active State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Active + * 0 - Interrupt No Active + */ +RV_STATIC_INLINE UINT32 PFIC_GetActive(IRQn_Type IRQn) +{ + return((UINT32)((PFIC->IACTR[(UINT32)(IRQn) >> 5] & (1 << ((UINT32)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn PFIC_SetPriority + * + * @brief Set Interrupt Priority + * + * @param IRQn - Interrupt Numbers + * interrupt nesting enable(PFIC->CFGR bit1 = 0) + * priority - bit[7] - Preemption Priority + * bit[6:4] - Sub priority + * bit[3:0] - Reserve + * interrupt nesting disable(PFIC->CFGR bit1 = 1) + * priority - bit[7:4] - Sub priority + * bit[3:0] - Reserve + * @return none + */ +RV_STATIC_INLINE void PFIC_SetPriority(IRQn_Type IRQn, UINT8 priority) +{ + PFIC->IPRIOR[(UINT32)(IRQn)] = priority; +} + +/********************************************************************* + * @fn __WFI + * + * @brief Wait for Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void) +{ + PFIC->SCTLR &= ~(1<<3); // wfi + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn _SEV + * + * @brief Set Event + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void) +{ + PFIC->SCTLR |= (1<<3)|(1<<5); +} + +/********************************************************************* + * @fn _WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void) +{ + PFIC->SCTLR |= (1<<3); + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn __WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) +{ + _SEV(); + _WFE(); + _WFE(); +} + +/********************************************************************* + * @fn PFIC_SetFastIRQ + * + * @brief Set VTF Interrupt + * + * @param add - VTF interrupt service function base address. + * IRQn - Interrupt Numbers + * num - VTF Interrupt Numbers + * + * @return none + */ +RV_STATIC_INLINE void PFIC_SetFastIRQ(UINT32 addr, IRQn_Type IRQn, UINT8 num){ + if(num > 3) return ; + PFIC->VTFBADDRR = addr; + PFIC->VTFADDRR[num] = ((UINT32)IRQn<<24)|(addr&0xfffff); +} + +/********************************************************************* + * @fn PFIC_SystemReset + * + * @brief Initiate a system reset request + * + * @return none + */ +RV_STATIC_INLINE void PFIC_SystemReset(void){ + PFIC->CFGR = PFIC_KEY3|(1<<7); +} + +/********************************************************************* + * @fn PFIC_HaltPushCfg + * + * @brief Enable Hardware Stack + * + * @param NewState - DISABLE or ENABLE + + * @return none + */ +RV_STATIC_INLINE void PFIC_HaltPushCfg(FunctionalState NewState) +{ + if (NewState != DISABLE) + { + PFIC->CFGR = PFIC_KEY1; + } + else + { + PFIC->CFGR = PFIC_KEY1|(1<<0); + } +} + +/********************************************************************* + * @fn PFIC_INTNestCfg + * + * @brief Enable Interrupt Nesting + * + * @param NewState - DISABLE or ENABLE + + * @return none + */ +RV_STATIC_INLINE void PFIC_INTNestCfg(FunctionalState NewState) +{ + if (NewState != DISABLE) + { + PFIC->CFGR = PFIC_KEY1; + } + else + { + PFIC->CFGR = PFIC_KEY1|(1<<1); + } +} + +/********************************************************************* + * @fn __AMOADD_W + * + * @brief Atomic Add with 32bit value + * Atomically ADD 32bit value with value in memory using amoadd.d. + * addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ADDed + * + * @return return memory value + add value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoadd.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOAND_W + * + * @brief Atomic And with 32bit value + * Atomically AND 32bit value with value in memory using amoand.d. + * addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ANDed + * + * @return return memory value & and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoand.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMAX_W + * + * @brief Atomic signed MAX with 32bit value + * Atomically signed max compare 32bit value with value in memory using amomax.d. + * addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return the bigger value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amomax.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMAXU_W + * + * @brief Atomic unsigned MAX with 32bit value + * Atomically unsigned max compare 32bit value with value in memory using amomaxu.d. + * addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return return the bigger value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value) +{ + uint32_t result; + + __asm volatile ("amomaxu.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMIN_W + * + * @brief Atomic signed MIN with 32bit value + * Atomically signed min compare 32bit value with value in memory using amomin.d. + * addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return the smaller value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amomin.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMINU_W + * + * @brief Atomic unsigned MIN with 32bit value + * Atomically unsigned min compare 32bit value with value in memory using amominu.d. + * addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return the smaller value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value) +{ + uint32_t result; + + __asm volatile ("amominu.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOOR_W + * + * @brief Atomic OR with 32bit value + * Atomically OR 32bit value with value in memory using amoor.d. + * addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ORed + * + * @return return memory value | and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoor.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOSWAP_W + * + * @brief Atomically swap new 32bit value into memory using amoswap.d. + * addr - Address pointer to data, address need to be 4byte aligned + * newval - New value to be stored into the address + * + * @return return the original value in memory + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval) +{ + uint32_t result; + + __asm volatile ("amoswap.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(newval) : "memory"); + return result; +} + +/********************************************************************* + * @fn __AMOXOR_W + * + * @brief Atomic XOR with 32bit value + * Atomically XOR 32bit value with value in memory using amoxor.d. + * addr - Address pointer to data, address need to be 4byte aligned + * value - value to be XORed + * + * @return return memory value ^ and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoxor.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFFFFFFFFFFF) +#define SysTick_CTRL_RELOAD_Msk (1 << 8) +#define SysTick_CTRL_CLKSOURCE_Msk (1 << 2) +#define SysTick_CTRL_TICKINT_Msk (1 << 1) +#define SysTick_CTRL_ENABLE_Msk (1 << 0) + + +RV_STATIC_INLINE uint32_t SysTick_Config( UINT64 ticks ) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->CMP = ticks - 1; /* set reload register */ + PFIC_EnableIRQ( SysTick_IRQn ); + SysTick->CTLR = SysTick_CTRL_RELOAD_Msk | + SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + + +/* Core_Exported_Functions */ +extern uint32_t __get_MSTATUS(void); +extern void __set_MSTATUS(uint32_t value); +extern uint32_t __get_MISA(void); +extern void __set_MISA(uint32_t value); +extern uint32_t __get_MIE(void); +extern void __set_MIE(uint32_t value); +extern uint32_t __get_MTVEC(void); +extern void __set_MTVEC(uint32_t value); +extern uint32_t __get_MSCRATCH(void); +extern void __set_MSCRATCH(uint32_t value); +extern uint32_t __get_MEPC(void); +extern void __set_MEPC(uint32_t value); +extern uint32_t __get_MCAUSE(void); +extern void __set_MCAUSE(uint32_t value); +extern uint32_t __get_MTVAL(void); +extern void __set_MTVAL(uint32_t value); +extern uint32_t __get_MVENDORID(void); +extern uint32_t __get_MARCHID(void); +extern uint32_t __get_MIMPID(void); +extern uint32_t __get_MHARTID(void); +extern uint32_t __get_SP(void); + +#ifdef __cplusplus +} +#endif + + +#endif + + + + + diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56xSFR.h b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56xSFR.h new file mode 100644 index 000000000..11aa27164 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56xSFR.h @@ -0,0 +1,2528 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : CH56xSFR.h +* Author : WCH +* Version : V1.0 +* Date : 2024/01/15 +* Description : +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + +#ifndef __BASE_TYPE__ +#define __BASE_TYPE__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* CH569 Standard Peripheral Library version number */ +#define __CH569_STDPERIPH_VERSION_MAIN (0x01) /* [15:8] main version */ +#define __CH569_STDPERIPH_VERSION_SUB (0x09) /* [7:0] sub version */ +#define __CH569_STDPERIPH_VERSION ((__CH564_STDPERIPH_VERSION_MAIN << 8)\ + | (__CH564_STDPERIPH_VERSION_SUB << 0)) + +/* ********************************************************************************************************************* */ +/* Base types & constants */ + +#ifndef TRUE + #define TRUE 1 + #define FALSE 0 +#endif +#ifndef NULL + #define NULL 0 +#endif + +#ifndef VOID + #define VOID void +#endif +#ifndef CONST + #define CONST const +#endif +#ifndef BOOL +typedef unsigned char BOOL; +#endif +#ifndef BOOLEAN +typedef unsigned char BOOLEAN; +#endif +#ifndef CHAR +typedef char CHAR; +#endif +#ifndef INT8 +typedef char INT8; +#endif +#ifndef INT16 +typedef short INT16; +#endif +#ifndef INT32 +typedef long INT32; +#endif +#ifndef INT64 +typedef long long INT64; +#endif +#ifndef UINT8 +typedef unsigned char UINT8; +#endif +#ifndef UINT16 +typedef unsigned short UINT16; +#endif +#ifndef UINT32 +typedef unsigned long UINT32; +#endif +#ifndef UINT64 +typedef unsigned long long UINT64; +#endif +#ifndef UINT8V +typedef unsigned char volatile UINT8V; +#endif +#ifndef UINT16V +typedef unsigned short volatile UINT16V; +#endif +#ifndef UINT32V +typedef unsigned long volatile UINT32V; +#endif +#ifndef UINT64V +typedef unsigned long long volatile UINT64V; +#endif + +#ifndef PVOID +typedef void *PVOID; +#endif +#ifndef PCHAR +typedef char *PCHAR; +#endif +#ifndef PCHAR +typedef const char *PCCHAR; +#endif +#ifndef PINT8 +typedef char *PINT8; +#endif +#ifndef PINT16 +typedef short *PINT16; +#endif +#ifndef PINT32 +typedef long *PINT32; +#endif +#ifndef PUINT8 +typedef unsigned char *PUINT8; +#endif +#ifndef PUINT16 +typedef unsigned short *PUINT16; +#endif +#ifndef PUINT32 +typedef unsigned long *PUINT32; +#endif +#ifndef PUINT8V +typedef volatile unsigned char *PUINT8V; +#endif +#ifndef PUINT16V +typedef volatile unsigned short *PUINT16V; +#endif +#ifndef PUINT32V +typedef volatile unsigned long *PUINT32V; +#endif + +/* ********************************************************************************************************************* */ +/* Base macros */ + +#ifndef min + #define min(a, b) (((a) < (b)) ? (a) : (b)) +#endif +#ifndef max + #define max(a, b) (((a) > (b)) ? (a) : (b)) +#endif + +#ifdef DEBUG + #define PRINT(X...) printf(X) +#else + #define PRINT(X...) +#endif + +/* Calculate the byte offset of a field in a structure of type */ +#define FIELD_OFFSET(Type, Field) ((UINT16) & (((Type *)0)->Field)) + +/* Calculate the size of a field in a structure of type */ +#define FIELD_SIZE(Type, Field) (sizeof(((Type *)0)->Field)) + +/* An expression that yields the type of a field in a struct */ +#define FIELD_TYPE(Type, Field) (((Type *)0)->Field) + +/* Return the number of elements in a statically sized array */ +#define NUMBER_OF(Array) (sizeof(Array) / sizeof((Array)[0])) +#define NUMBER_OF_FIELD(Type, Field) (NUMBER_OF(FIELD_TYPE(Type, Field))) + +#ifdef __cplusplus +} +#endif + +#endif // __BASE_TYPE__ + +#ifndef __CH56xGPSFR_H__ +#define __CH56xGPSFR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* ********************************************************************************************************************* */ + +// Address Space +// CODE: 00000000H - 0007FFFFH 512KB +// DATA: 20000000H - 20003FFFH 16KB +// DATAX: 20020000H - 20037FFFH 96KB (Min:32KB, Max:96KB) +// SFR: 40000000H - 4000FFFFH 64KB +// BUS: 80000000H - 80007FFFH 32KB +// +// SFR: 40000000H - 4000FFFFH, 64KB +// SYS: +1000H - 13FFH, include base configuration, interrupt, GPIO, etc... +// TMR0: +2000H - 23FFH +// TMR1: +2400H - 27FFH +// TMR2: +2800H - 2BFFH +// UART0: +3000H - 33FFH +// UART1: +3400H - 37FFH +// UART2: +3800H - 3BFFH +// UART3: +3C00H - 3FFFH +// SPI0: +4000H - 43FFH +// SPI1: +4400H - 47FFH +// PWMX: +5000H - 53FFH +// HSPI: +6000H - 63FFH +// ECDC: +7000H - 73FFH +// USBSS: +8000H - 83FFH +// USBHS: +9000H - 93FFH +// EMMC: +A000H - A3FFH +// SERDES: +B000H - B3FFH +// ETH: +C000H - D3FFH +// DVP: +E000H - E3FFH + +// Register Bit Attribute / Bit Access Type +// RF: Read only for Fixed value +// RO: Read Only (internal change) +// RZ: Read only with auto clear Zero +// WO: Write Only (read zero or different) +// WA: Write only under safe Accessing mode (read zero or different) +// WZ: Write only with auto clear Zero +// RW: Read / Write +// RWA: Read / Write under safe Accessing mode +// RW1: Read / Write 1 to Clear + +/* Register name rule: + R32_* for 32 bits register (UINT32,ULONG) + R16_* for 16 bits register (UINT16,USHORT) + R8_* for 8 bits register (UINT8,UCHAR) + RB_* for bit or bit mask of 8 bit register + BA_* for base address point + b* for GPIO bit mask + Others for register address offset */ + +/* ********************************************************************************************************************* */ + +/* System: safe accessing register */ +#define R32_SAFE_ACCESS (*((PUINT32V)0x40001000)) // RW, safe accessing +#define R8_SAFE_ACCESS_SIG (*((PUINT8V)0x40001000)) // WO, safe accessing sign register, must write 0x57 then 0xA8 to enter safe accessing mode +#define RB_SAFE_ACC_MODE 0x03 // RO, current safe accessing mode: 11=safe/unlocked (SAM), other=locked (00..01..10..11) +#define RB_SAFE_ACC_TIMER 0x70 // RO, safe accessing timer bit mask (16*clock number) +#define R8_CHIP_ID (*((PUINT8V)0x40001001)) // RF, chip ID register, always is ID_CH569W +#define R8_SAFE_ACCESS_ID (*((PUINT8V)0x40001002)) // RF, safe accessing ID register, always 0x02 +#define R8_WDOG_COUNT (*((PUINT8V)0x40001003)) // RW, watch-dog count, count by clock frequency Fsys/524288 + +/* System: global configuration register */ +#define R32_GLOBAL_CONFIG (*((PUINT32V)0x40001004)) // RW, global configuration +#define R8_GLOB_ROM_CFG (*((PUINT8V)0x40001004)) // RWA, flash ROM configuration, SAM and bit7:6 must write 1:0 +#define RB_ROM_EXT_RE 0x01 // RWA, enable flash ROM being read by external programmer: 0=reading protect, 1=enable read +#define RB_CODE_RAM_WE 0x02 // RWA, enable code RAM being write: 0=writing protect, 1=enable write +#define RB_ROM_DATA_WE 0x04 // RWA, enable flash ROM data area being erase/write: 0=writing protect, 1=enable program and erase +#define RB_ROM_CODE_WE 0x08 // RWA, enable flash ROM code & data area being erase/write: 0=writing protect, 1=enable program and erase +#define RB_ROM_CODE_OFS 0x10 // RWA, +//#define RB_GLOB_BOOT_APP 0x10 // RO, boot loader action status +#define R8_RST_BOOT_STAT (*((PUINT8V)0x40001005)) // RO, reset status and boot/debug status, bit7:6 always are 1:1 +#define RB_RESET_FLAG 0x03 // RO: recent reset flag +#define RST_FLAG_SW 0x00 +#define RST_FLAG_POR 0x01 +#define RST_FLAG_WDOG 0x02 +#define RST_FLAG_PIN 0x03 +// RB_RESET_FLAG: recent reset flag +// 00 - software reset, by RB_SOFTWARE_RESET=1 @(RB_BOOT_LOADER=0 or RB_WDOG_RST_EN=1), or set reset request from PFIC +// 01 - power on reset +// 10 - watch-dog timer overflow reset, or CORE LOCKUP reset +// 11 - external manual reset by RST# pin input low +#define RB_CFG_RESET_EN 0x04 // RO, manual reset input enable status +#define RB_CFG_BOOT_EN 0x08 // RO, boot-loader enable status +#define RB_CFG_DEBUG_EN 0x10 // RO, debug enable status +#define RB_BOOT_LOADER 0x20 // RO, indicate boot loader status: 0=application status (by software reset), 1=boot loader status +#define R8_RST_WDOG_CTRL (*((PUINT8V)0x40001006)) // RWA, reset and watch-dog control, SAM and bit7:6 must write 0:1 +#define RB_SOFTWARE_RESET 0x01 // WA/WZ, global software reset, high action, auto clear +#define RB_WDOG_RST_EN 0x02 // RWA, enable watch-dog reset if watch-dog timer overflow: 0=as timer only, 1=enable reset if timer overflow +#define RB_WDOG_INT_EN 0x04 // RWA, watch-dog interrupt enable or INT_ID_WDOG interrupt source selection: 0=software interrupt, 1=from watch-dog timer overflow +#define RB_WDOG_INT_FLAG 0x10 // RW1, watch-dog timer overflow interrupt flag, cleared by RW1 or reload watch-dog count +#define R8_GLOB_RESET_KEEP (*((PUINT8V)0x40001007)) // RW, value keeper during global reset + +/* System: clock configuration register */ +#define R32_CLOCK_CONFIG (*((PUINT32V)0x40001008)) // RWA, clock configuration, SAM +#define R8_CLK_PLL_DIV (*((PUINT8V)0x40001008)) // RWA, output clock divider from PLL, only low 4 bit, SAM and bit7:6 must write 0:1 +#define R8_CLK_CFG_CTRL (*((PUINT8V)0x4000100A)) // RWA, clock control, SAM and bit7:6 must write 1:0 +#define RB_CLK_PLL_SLEEP 0x01 // RWA, PLL sleep control: 0=PLL run, 1=PLL sleep +#define RB_CLK_SEL_PLL 0x02 // RWA, clock source selection: 0=oscillator 30MHz, 1=PLL 300MHz/480MHz +// OSC_FREQ = 30MHz +// PLL_FREQ = 300MHz/480MHz +// SRC_FREQ = RB_CLK_SEL_PLL ? PLL_FREQ : OSC_FREQ +// SYS_FREQ = SRC_FREQ / R8_CLK_PLL_DIV, 2MHz ~ 120MHz +// default: SRC_FREQ = 30MHz/2 = 15MHz +#define R8_CLK_MOD_AUX (*((PUINT8V)0x4000100B)) // RWA, clock mode aux register +#define RB_SRC_125M_MSK 0x03 // RWA, ETH 125MHz clock enable, high enable,[1]: clock from pin_pa[16], [0]: clock from USB_PHY PCLK(125MHz) +#define RB_EXT_125M_EN 0x02 +#define RB_INT_125M_EN 0x01 +#define RB_MCO_SEL_MSK 0x0C // RWA, MCO output selection: 00=125M, 01=25M, 1x=2.5M +#define RB_SEL_125M 0x00 +#define RB_SEL_25M 0x04 +#define RB_SEL_2P5M 0x08 +#define RB_MCO_EN 0x10 // RWA, MCO output enable, high action + +/* System: sleep control register */ +#define R32_SLEEP_CONTROL (*((PUINT32V)0x4000100C)) // RWA, sleep control, SAM +#define R8_SLP_CLK_OFF0 (*((PUINT8V)0x4000100C)) // RWA, sleep clock off control byte 0, SAM +#define RB_SLP_CLK_TMR0 0x01 // RWA, sleep TMR0 clock +#define RB_SLP_CLK_TMR1 0x02 // RWA, sleep TMR1 clock +#define RB_SLP_CLK_TMR2 0x04 // RWA, sleep TMR2 clock +#define RB_SLP_CLK_PWMX 0x08 // RWA, sleep PWMX clock +#define RB_SLP_CLK_UART0 0x10 // RWA, sleep UART0 clock +#define RB_SLP_CLK_UART1 0x20 // RWA, sleep UART1 clock +#define RB_SLP_CLK_UART2 0x40 // RWA, sleep UART2 clock +#define RB_SLP_CLK_UART3 0x80 // RWA, sleep UART3 clock +#define R8_SLP_CLK_OFF1 (*((PUINT8V)0x4000100D)) // RWA, sleep clock off control byte 1, SAM +#define RB_SLP_CLK_SPI0 0x01 // RWA, sleep SPI0 clock +#define RB_SLP_CLK_SPI1 0x02 // RWA, sleep SPI1 clock +#define RB_SLP_CLK_EMMC 0x04 // RWA, sleep EMMC clock +#define RB_SLP_CLK_HSPI 0x08 // RWA, sleep HSPI clock +#define RB_SLP_CLK_USBHS 0x10 // RWA, sleep USBHS clock +#define RB_SLP_CLK_USBSS 0x20 // RWA, sleep USBSS clock +#define RB_SLP_CLK_SERD 0x40 // RWA, sleep SERDES clock +#define RB_SLP_CLK_DVP 0x80 // RWA, sleep DVP clock +#define R8_SLP_WAKE_CTRL (*((PUINT8V)0x4000100E)) // RWA, wake control, SAM +#define RB_SLP_USBHS_WAKE 0x01 // RWA, enable USBHS waking +#define RB_SLP_USBSS_WAKE 0x02 // RWA, enable USBSS waking +#define RB_SLP_CLK_ETH 0x04 // RWA, sleep ETH clock +#define RB_SLP_CLK_ECDC 0x08 // RWA, sleep ECDC CLOCK +#define RB_SLP_GPIO_WAKE 0x10 // RWA, enable GPIO waking +#define RB_SLP_ETH_WAKE 0x20 // RWA, enable Eth waking +#define R8_SLP_POWER_CTRL (*((PUINT8V)0x4000100F)) // RWA, power control, SAM +#define RB_SLP_USBHS_PWRDN 0x01 // RWA, enable USBHS power down + +/* System: port and bus configuration register */ +#define R32_PORT_CONFIG (*((PUINT32V)0x40001010)) // RW, port and bus configuration +#define R8_XBUS_CONFIG (*((PUINT8V)0x40001010)) // RW, external bus configuration +#define RB_XBUS_ENABLE 0x01 // RW, external bus enable: 0=disable, 1=enable bRD and bWR, enable PA[7:0] as parallel DATA port +#define RB_XBUS_ADDR_OE 0x0C // RW, external bus address output enable: 00=none, 01=PB[5:0], 10=PB[9:0], 11=PB[14:0] +#define RB_XBUS_WIDTH 0x30 // RW, external bus access pulse width: 00=3 clocks, 01=5 clocks, 10= 9 clocks, 11=16 clocks +#define RB_XBUS_HOLD 0x40 // RW, external bus hold time: 0=2 clocks, 1=3 clocks +#define RB_XBUS_SETUP 0x80 // RW, external bus setup time: 0=2 clocks, 1=3 clocks +#define R8_PIN_ALTERNATE (*((PUINT8V)0x40001012)) // RW, alternate pin control +#define RB_PIN_MII 0x01 // RW, ETH mii interface selection: 0=MII interface, 1=RGMII interface +#define RB_PIN_TMR1 0x02 // RW, TMR1 alternate pin enable: 0=TMR1/PWM5/CAP1 on PA[4], 1=TMR1X/PWM5X/CAP1X on PB[0] +#define RB_PIN_TMR2 0x04 // RW, TMR2 alternate pin enable: 0=TMR2/PWM6/CAP2 on PA[6], 1=TMR2X/PWM6X/CAP2X on PB[3] +#define RB_PIN_UART0 0x10 // RW, RXD0/TXD0 alternate pin enable: 0=RXD1/TXD1 on PB[5]/PB[6], 1=RXD1X/TXD1X on PA[5]/PA[6] + +/* System: Serdes Analog parameter control register */ +#define R16_SERD_ANA_CFG1 (*((PUINT16V)0x40001020)) //RWA, Serdes Analog parameter configuration1 +#define R32_SERD_ANA_CFG2 (*((PUINT32V)0x40001024)) //RWA, Serdes Analog parameter configuration2 + +/* System: GPIO interrupt control register */ +#define R32_GPIO_INT_CTRL (*((PUINT32V)0x4000101C)) // RW, GPIO interrupt control +#define R8_GPIO_INT_FLAG (*((PUINT8V)0x4000101C)) // RW1, GPIO interrupt flag +#define R8_GPIO_INT_ENABLE (*((PUINT8V)0x4000101D)) // RW, GPIO interrupt enable +#define R8_GPIO_INT_MODE (*((PUINT8V)0x4000101E)) // RW, GPIO interrupt mode: 0=level action, 1=edge action +#define R8_GPIO_INT_POLAR (*((PUINT8V)0x4000101F)) // RW, GPIO interrupt polarity: 0=normal(low_level/fall_edge), 1=invert(high_level/rise_edge) + +/* GPIO interrupt control register address offset and bit define */ +#define BA_GPIO_INT_CTRL ((PUINT8V)0x4000101C) // point GPIO interrupt base address +#define GPIO_INT_FLAG 0x00 +#define GPIO_INT_ENABLE 0x01 +#define GPIO_INT_MODE 0x02 +#define GPIO_INT_POLAR 0x03 +#define RB_GPIO_PA2 0x01 +#define RB_GPIO_PA3 0x02 +#define RB_GPIO_PA4 0x04 +#define RB_GPIO_PB3 0x08 +#define RB_GPIO_PB4 0x10 +#define RB_GPIO_PB11 0x20 +#define RB_GPIO_PB12 0x40 +#define RB_GPIO_PB15 0x80 + +/* GPIO PA register */ +#define R32_PA_DIR (*((PUINT32V)0x40001040)) // RW, GPIO PA I/O direction: 0=in, 1=out +#define R8_PA_DIR_0 (*((PUINT8V)0x40001040)) // RW, GPIO PA I/O direction byte 0 +#define R8_PA_DIR_1 (*((PUINT8V)0x40001041)) // RW, GPIO PA I/O direction byte 1 +#define R8_PA_DIR_2 (*((PUINT8V)0x40001042)) // RW, GPIO PA I/O direction byte 2 +#define R32_PA_PIN (*((PUINT32V)0x40001044)) // RO, GPIO PA input +#define R8_PA_PIN_0 (*((PUINT8V)0x40001044)) // RO, GPIO PA input byte 0 +#define R8_PA_PIN_1 (*((PUINT8V)0x40001045)) // RO, GPIO PA input byte 1 +#define R8_PA_PIN_2 (*((PUINT8V)0x40001046)) // RO, GPIO PA input byte 2 +#define R32_PA_OUT (*((PUINT32V)0x40001048)) // RW, GPIO PA output +#define R8_PA_OUT_0 (*((PUINT8V)0x40001048)) // RW, GPIO PA output byte 0 +#define R8_PA_OUT_1 (*((PUINT8V)0x40001049)) // RW, GPIO PA output byte 1 +#define R8_PA_OUT_2 (*((PUINT8V)0x4000104A)) // RW, GPIO PA output byte 2 +#define R32_PA_CLR (*((PUINT32V)0x4000104C)) // WZ, GPIO PA clear output: 0=keep, 1=clear +#define R8_PA_CLR_0 (*((PUINT8V)0x4000104C)) // WZ, GPIO PA clear output byte 0 +#define R8_PA_CLR_1 (*((PUINT8V)0x4000104D)) // WZ, GPIO PA clear output byte 1 +#define R8_PA_CLR_2 (*((PUINT8V)0x4000104E)) // WZ, GPIO PA clear output byte 2 +#define R32_PA_PU (*((PUINT32V)0x40001050)) // RW, GPIO PA pullup resistance enable +#define R8_PA_PU_0 (*((PUINT8V)0x40001050)) // RW, GPIO PA pullup resistance enable byte 0 +#define R8_PA_PU_1 (*((PUINT8V)0x40001051)) // RW, GPIO PA pullup resistance enable byte 1 +#define R8_PA_PU_2 (*((PUINT8V)0x40001052)) // RW, GPIO PA pullup resistance enable byte 2 +#define R32_PA_PD (*((PUINT32V)0x40001054)) // RW, GPIO PA output open-drain & input pulldown resistance enable +#define R8_PA_PD_0 (*((PUINT8V)0x40001054)) // RW, GPIO PA output open-drain & input pulldown resistance enable byte 0 +#define R8_PA_PD_1 (*((PUINT8V)0x40001055)) // RW, GPIO PA output open-drain & input pulldown resistance enable byte 1 +#define R8_PA_PD_2 (*((PUINT8V)0x40001056)) // RW, GPIO PA output open-drain & input pulldown resistance enable byte 2 +#define R32_PA_DRV (*((PUINT32V)0x40001058)) // RW, GPIO PA driving capability: 0=8mA, 1=16mA +#define R8_PA_DRV_0 (*((PUINT8V)0x40001058)) // RW, GPIO PA driving capability byte 0 +#define R8_PA_DRV_1 (*((PUINT8V)0x40001059)) // RW, GPIO PA driving capability byte 1 +#define R8_PA_DRV_2 (*((PUINT8V)0x4000105A)) // RW, GPIO PA driving capability byte 2 +#define R32_PA_SMT (*((PUINT32V)0x4000105C)) // RW, GPIO PA output slew rate & input schmitt trigger: 0=fast,normal, 1=slow,schmitt +#define R8_PA_SMT_0 (*((PUINT8V)0x4000105C)) // RW, GPIO PA output slew rate & input schmitt trigger byte 0 +#define R8_PA_SMT_1 (*((PUINT8V)0x4000105D)) // RW, GPIO PA output slew rate & input schmitt trigger byte 1 +#define R8_PA_SMT_2 (*((PUINT8V)0x4000105E)) // RW, GPIO PA output slew rate & input schmitt trigger byte 2 + +/* GPIO PB register */ +#define R32_PB_DIR (*((PUINT32V)0x40001060)) // RW, GPIO PB I/O direction: 0=in, 1=out +#define R8_PB_DIR_0 (*((PUINT8V)0x40001060)) // RW, GPIO PB I/O direction byte 0 +#define R8_PB_DIR_1 (*((PUINT8V)0x40001061)) // RW, GPIO PB I/O direction byte 1 +#define R8_PB_DIR_2 (*((PUINT8V)0x40001062)) // RW, GPIO PB I/O direction byte 2 +#define R8_PB_DIR_3 (*((PUINT8V)0x40001063)) // RW, GPIO PB I/O direction byte 3 +#define R32_PB_PIN (*((PUINT32V)0x40001064)) // RO, GPIO PB input +#define R8_PB_PIN_0 (*((PUINT8V)0x40001064)) // RO, GPIO PB input byte 0 +#define R8_PB_PIN_1 (*((PUINT8V)0x40001065)) // RO, GPIO PB input byte 1 +#define R8_PB_PIN_2 (*((PUINT8V)0x40001066)) // RO, GPIO PB input byte 2 +#define R8_PB_PIN_3 (*((PUINT8V)0x40001067)) // RO, GPIO PB input byte 3 +#define R32_PB_OUT (*((PUINT32V)0x40001068)) // RW, GPIO PB output +#define R8_PB_OUT_0 (*((PUINT8V)0x40001068)) // RW, GPIO PB output byte 0 +#define R8_PB_OUT_1 (*((PUINT8V)0x40001069)) // RW, GPIO PB output byte 1 +#define R8_PB_OUT_2 (*((PUINT8V)0x4000106A)) // RW, GPIO PB output byte 2 +#define R8_PB_OUT_3 (*((PUINT8V)0x4000106B)) // RW, GPIO PB output byte 3 +#define R32_PB_CLR (*((PUINT32V)0x4000106C)) // WZ, GPIO PB clear output: 0=keep, 1=clear +#define R8_PB_CLR_0 (*((PUINT8V)0x4000106C)) // WZ, GPIO PB clear output byte 0 +#define R8_PB_CLR_1 (*((PUINT8V)0x4000106D)) // WZ, GPIO PB clear output byte 1 +#define R8_PB_CLR_2 (*((PUINT8V)0x4000106E)) // WZ, GPIO PB clear output byte 2 +#define R8_PB_CLR_3 (*((PUINT8V)0x4000106F)) // WZ, GPIO PB clear output byte 3 +#define R32_PB_PU (*((PUINT32V)0x40001070)) // RW, GPIO PB pullup resistance enable +#define R8_PB_PU_0 (*((PUINT8V)0x40001070)) // RW, GPIO PB pullup resistance enable byte 0 +#define R8_PB_PU_1 (*((PUINT8V)0x40001071)) // RW, GPIO PB pullup resistance enable byte 1 +#define R8_PB_PU_2 (*((PUINT8V)0x40001072)) // RW, GPIO PB pullup resistance enable byte 2 +#define R8_PB_PU_3 (*((PUINT8V)0x40001073)) // RW, GPIO PB pullup resistance enable byte 3 +#define R32_PB_PD (*((PUINT32V)0x40001074)) // RW, GPIO PB output open-drain & input pulldown resistance enable +#define R8_PB_PD_0 (*((PUINT8V)0x40001074)) // RW, GPIO PB output open-drain & input pulldown resistance enable byte 0 +#define R8_PB_PD_1 (*((PUINT8V)0x40001075)) // RW, GPIO PB output open-drain & input pulldown resistance enable byte 1 +#define R8_PB_PD_2 (*((PUINT8V)0x40001076)) // RW, GPIO PB output open-drain & input pulldown resistance enable byte 2 +#define R8_PB_PD_3 (*((PUINT8V)0x40001077)) // RW, GPIO PB output open-drain & input pulldown resistance enable byte 3 +#define R32_PB_DRV (*((PUINT32V)0x40001078)) // RW, GPIO PB driving capability: 0=8mA, 1=16mA +#define R8_PB_DRV_0 (*((PUINT8V)0x40001078)) // RW, GPIO PB driving capability byte 0 +#define R8_PB_DRV_1 (*((PUINT8V)0x40001079)) // RW, GPIO PB driving capability byte 1 +#define R8_PB_DRV_2 (*((PUINT8V)0x4000107A)) // RW, GPIO PB driving capability byte 2 +#define R8_PB_DRV_3 (*((PUINT8V)0x4000107B)) // RW, GPIO PB driving capability byte 3 +#define R32_PB_SMT (*((PUINT32V)0x4000107C)) // RW, GPIO PB output slew rate & input schmitt trigger: 0=fast,normal, 1=slow,schmitt +#define R8_PB_SMT_0 (*((PUINT8V)0x4000107C)) // RW, GPIO PB output slew rate & input schmitt trigger byte 0 +#define R8_PB_SMT_1 (*((PUINT8V)0x4000107D)) // RW, GPIO PB output slew rate & input schmitt trigger byte 1 +#define R8_PB_SMT_2 (*((PUINT8V)0x4000107E)) // RW, GPIO PB output slew rate & input schmitt trigger byte 2 +#define R8_PB_SMT_3 (*((PUINT8V)0x4000107F)) // RW, GPIO PB output slew rate & input schmitt trigger byte 3 + +/* GPIO register address offset and bit define */ +#define BA_PA ((PUINT8V)0x40001040) // point GPIO PA base address +#define BA_PB ((PUINT8V)0x40001060) // point GPIO PB base address +#define GPIO_DIR 0x00 +#define GPIO_DIR_0 0x00 +#define GPIO_DIR_1 0x01 +#define GPIO_DIR_2 0x02 +#define GPIO_DIR_3 0x03 +#define GPIO_PIN 0x04 +#define GPIO_PIN_0 0x04 +#define GPIO_PIN_1 0x05 +#define GPIO_PIN_2 0x06 +#define GPIO_PIN_3 0x07 +#define GPIO_OUT 0x08 +#define GPIO_OUT_0 0x08 +#define GPIO_OUT_1 0x09 +#define GPIO_OUT_2 0x0A +#define GPIO_OUT_3 0x0B +#define GPIO_CLR 0x0C +#define GPIO_CLR_0 0x0C +#define GPIO_CLR_1 0x0D +#define GPIO_CLR_2 0x0E +#define GPIO_CLR_3 0x0F +#define GPIO_PU 0x10 +#define GPIO_PU_0 0x10 +#define GPIO_PU_1 0x11 +#define GPIO_PU_2 0x12 +#define GPIO_PU_3 0x13 +#define GPIO_PD 0x14 +#define GPIO_PD_0 0x14 +#define GPIO_PD_1 0x15 +#define GPIO_PD_2 0x16 +#define GPIO_PD_3 0x17 +#define GPIO_DRV 0x18 +#define GPIO_DRV_0 0x18 +#define GPIO_DRV_1 0x19 +#define GPIO_DRV_2 0x1A +#define GPIO_DRV_3 0x1B +#define GPIO_SMT 0x1C +#define GPIO_SMT_0 0x1C +#define GPIO_SMT_1 0x1D +#define GPIO_SMT_2 0x1E +#define GPIO_SMT_3 0x1F + +/* GPIO alias name */ +/* GPIOA */ +#define bHSPI6 (1 << 0) // PA0 +#define bSDD5 (1 << 0) // PA0 +#define bDVP3 (1 << 0) // PA0 +#define bHSPI5 (1 << 1) // PA1 +#define bSDD6 (1 << 1) // PA1 +#define bDVP2 (1 << 1) // PA1 +#define bHSPI4 (1 << 2) // PA2 +#define bRXD2 (1 << 2) // PA2 +#define bSDD7 (1 << 2) // PA2 +#define bDVP1 (1 << 2) // PA2 +#define bHSPI3 (1 << 3) // PA3 +#define bTXD2 (1 << 3) // PA3 +#define bDVP0 (1 << 3) // PA3 +#define bHSPI1 (1 << 4) // PA4 +#define bPWM1 (1 << 4) // PA4 +#define bTMR2 (1 << 4) // PA4 +#define bCAP2 bTMR2 +#define bPWM6 bTMR2 +#define bVSYNC (1 << 4) // PA4 +#define bHSPI0 (1 << 5) // PA5 +#define bRXD0X (1 << 5) // PA5 +#define bHSYNC (1 << 5) // PA5 +#define bHSPIRV (1 << 6) // PA6 +#define bTXD0X (1 << 6) // PA6 +#define bPCLK (1 << 6) // PA6 +#define bRXD1 (1 << 7) // PA7 +#define bTXD1 (1 << 8) // PA8 +#define bBUSRD (1 << 8) // PA8 +#define bHSPITRQ (1 << 9) // PA9 +#define bTMR0 (1 << 9) // PA9 +#define bCAP0 bTMR0 +#define bPWM4 bTMR0 +#define bBUSWR (1 << 9) // PA9 +#define bHSPITAK (1 << 10) // PA10 +#define bDBGCK (1 << 10) // PA10 +#define bHSPITCK (1 << 11) // PA11 +#define bDBGIO (1 << 11) // PA11 +#define bSCS0 (1 << 12) // PA12 +#define bSCK0 (1 << 13) // PA13 +#define bMOSI0 (1 << 14) // PA14 +#define bMISO0 (1 << 15) // PA15 +#define bHSPI24 (1 << 16) // PA16 +#define bEMCI (1 << 16) // PA16 +#define bHSPI12 (1 << 17) // PA17 +#define bHSPIRAT (1 << 18) // PA18 +#define bHSPIRCK (1 << 19) // PA19 +#define bHSPI19 (1 << 20) // PA20 +#define bEMCO (1 << 20) // PA20 +#define bHSPITV (1 << 21) // PA21 +#define bHSPI2 (1 << 22) // PA22 +#define bHSPITRY (1 << 23) // PA23 + +/* GPIOB */ +#define bHSPI16 (1 << 0) // PB0 +#define bTMR1X (1 << 0) // PB0 +#define bCAP1X bTMR1X +#define bPWM5X bTMR1X +#define bMDIO (1 << 0) // PB0 +#define bHSPI17 (1 << 1) // PB1 +#define bPWM2 (1 << 1) // PB1 +#define bMDCK (1 << 1) // PB1 +#define bHSPI18 (1 << 2) // PB2 +#define bPWM3 (1 << 2) // PB2 +#define bETHT3 (1 << 2) // PB2 +#define bHSPI20 (1 << 3) // PB3 +#define bTMR2X (1 << 3) // PB3 +#define bCAP2X bTMR2X +#define bPWM6X bTMR2X +#define bRXD3 (1 << 3) // PB3 +#define bETHT2 (1 << 3) // PB3 +#define bHSPI21 (1 << 4) // PB4 +#define bTXD3 (1 << 4) // PB4 +#define bETHT1 (1 << 4) // PB4 +#define bHSPI22 (1 << 5) // PB5 +#define bRXD0 (1 << 5) // PB5 +#define bETHT0 (1 << 5) // PB5 +#define bHSPI23 (1 << 6) // PB6 +#define bTXD0 (1 << 6) // PB6 +#define bETHTEN (1 << 6) // PB6 +#define bHSPI25 (1 << 7) // PB7 +#define bDSR (1 << 7) // PB7 +#define bETHTC (1 << 7) // PB7 +#define bHSPI26 (1 << 8) // PB8 +#define bRI (1 << 8) // PB8 +#define bETHRC (1 << 8) // PB8 +#define bHSPI27 (1 << 9) // PB9 +#define bDCD (1 << 9) // PB9 +#define bETHR3 (1 << 9) // PB9 +#define bHSPI28 (1 << 10) // PB10 +#define bDTR (1 << 10) // PB10 +#define bETHR2 (1 << 10) // PB10 +#define bHSPI29 (1 << 11) // PB11 +#define bSCS1 (1 << 11) // PB11 +#define bCTS (1 << 11) // PB11 +#define bETHR1 (1 << 11) // PB11 +#define bHSPI30 (1 << 12) // PB12 +#define bSCK1 (1 << 12) // PB12 +#define bRTS (1 << 12) // PB12 +#define bETHR0 (1 << 12) // PB12 +#define bHSPI31 (1 << 13) // PB13 +#define bMOSI1 (1 << 13) // PB13 +#define bETHRDV (1 << 13) // PB13 +#define bHSPI15 (1 << 14) // PB14 +#define bMISO1 (1 << 14) // PB14 +#define bSDCK (1 << 14) // PB14 +#define bDVP11 (1 << 14) // PB14 +#define bHSPI14 (1 << 15) // PB15 +#define bTMR1 (1 << 15) // PB15 +#define bCAP1 bTMR1 +#define bPWM5 bTMR1 +#define bPWM0 (1 << 15) // PB15 +#define bDVP10 (1 << 15) // PB15 +#define bHSPI13 (1 << 16) // PB16 +#define bSDCMD (1 << 16) // PB16 +#define bDVP9 (1 << 16) // PB16 +#define bHSPI11 (1 << 17) // PB17 +#define bSDD0 (1 << 17) // PB17 +#define bDVP8 (1 << 17) // PB17 +#define bHSPI10 (1 << 18) // PB18 +#define bSDD1 (1 << 18) // PB18 +#define bDVP7 (1 << 18) // PB18 +#define bHSPI9 (1 << 19) // PB19 +#define bSDD2 (1 << 19) // PB19 +#define bDVP6 (1 << 19) // PB19 +#define bHSPI8 (1 << 20) // PB20 +#define bSDD3 (1 << 20) // PB20 +#define bDVP5 (1 << 20) // PB20 +#define bHSPI7 (1 << 21) // PB21 +#define bSDD4 (1 << 21) // PB21 +#define bDVP4 (1 << 21) // PB21 + +/* Timer0 register */ +#define R32_TMR0_CONTROL (*((PUINT32V)0x40002000)) // RW, TMR0 control +#define R8_TMR0_CTRL_MOD (*((PUINT8V)0x40002000)) // RW, TMR0 mode control +#define R8_TMR0_INTER_EN (*((PUINT8V)0x40002002)) // RW, TMR0 interrupt enable +#define R32_TMR0_STATUS (*((PUINT32V)0x40002004)) // RW, TMR0 status +#define R8_TMR0_INT_FLAG (*((PUINT8V)0x40002006)) // RW1, TMR0 interrupt flag +#define R8_TMR0_FIFO_COUNT (*((PUINT8V)0x40002007)) // RO, TMR0 FIFO count status +#define R32_TMR0_COUNT (*((PUINT32V)0x40002008)) // RO, TMR0 current count +#define R16_TMR0_COUNT (*((PUINT16V)0x40002008)) // RO, TMR0 current count +#define R8_TMR0_COUNT (*((PUINT8V)0x40002008)) // RO, TMR0 current count +#define R32_TMR0_CNT_END (*((PUINT32V)0x4000200C)) // RW, TMR0 end count value, only low 26 bit +#define R32_TMR0_FIFO (*((PUINT32V)0x40002010)) // RO/WO, TMR0 FIFO register, only low 26 bit +#define R16_TMR0_FIFO (*((PUINT16V)0x40002010)) // RO/WO, TMR0 FIFO register +#define R8_TMR0_FIFO (*((PUINT8V)0x40002010)) // RO/WO, TMR0 FIFO register + +/* Timer1 register */ +#define R32_TMR1_CONTROL (*((PUINT32V)0x40002400)) // RW, TMR1 control +#define R8_TMR1_CTRL_MOD (*((PUINT8V)0x40002400)) // RW, TMR1 mode control +#define R8_TMR1_CTRL_DMA (*((PUINT8V)0x40002401)) // RW, TMR1 DMA control +#define R8_TMR1_INTER_EN (*((PUINT8V)0x40002402)) // RW, TMR1 interrupt enable +#define R32_TMR1_STATUS (*((PUINT32V)0x40002404)) // RW, TMR1 status +#define R8_TMR1_INT_FLAG (*((PUINT8V)0x40002406)) // RW1, TMR1 interrupt flag +#define R8_TMR1_FIFO_COUNT (*((PUINT8V)0x40002407)) // RO, TMR1 FIFO count status +#define R32_TMR1_COUNT (*((PUINT32V)0x40002408)) // RO, TMR1 current count +#define R16_TMR1_COUNT (*((PUINT16V)0x40002408)) // RO, TMR1 current count +#define R8_TMR1_COUNT (*((PUINT8V)0x40002408)) // RO, TMR1 current count +#define R32_TMR1_CNT_END (*((PUINT32V)0x4000240C)) // RW, TMR1 end count value, only low 26 bit +#define R32_TMR1_FIFO (*((PUINT32V)0x40002410)) // RO/WO, TMR1 FIFO register, only low 26 bit +#define R16_TMR1_FIFO (*((PUINT16V)0x40002410)) // RO/WO, TMR1 FIFO register +#define R8_TMR1_FIFO (*((PUINT8V)0x40002410)) // RO/WO, TMR1 FIFO register +#define R32_TMR1_DMA_NOW (*((PUINT32V)0x40002414)) // RW, TMR1 DMA current address +//#define R16_TMR1_DMA_NOW (*((PUINT16V)0x40002414)) // RW, TMR1 DMA current address +#define R32_TMR1_DMA_BEG (*((PUINT32V)0x40002418)) // RW, TMR1 DMA begin address +//#define R16_TMR1_DMA_BEG (*((PUINT16V)0x40002418)) // RW, TMR1 DMA begin address +#define R32_TMR1_DMA_END (*((PUINT32V)0x4000241C)) // RW, TMR1 DMA end address +//#define R16_TMR1_DMA_END (*((PUINT16V)0x4000241C)) // RW, TMR1 DMA end address + +/* Timer2 register */ +#define R32_TMR2_CONTROL (*((PUINT32V)0x40002800)) // RW, TMR2 control +#define R8_TMR2_CTRL_MOD (*((PUINT8V)0x40002800)) // RW, TMR2 mode control +#define R8_TMR2_CTRL_DMA (*((PUINT8V)0x40002801)) // RW, TMR2 DMA control +#define R8_TMR2_INTER_EN (*((PUINT8V)0x40002802)) // RW, TMR2 interrupt enable +#define R32_TMR2_STATUS (*((PUINT32V)0x40002804)) // RW, TMR2 status +#define R8_TMR2_INT_FLAG (*((PUINT8V)0x40002806)) // RW1, TMR2 interrupt flag +#define R8_TMR2_FIFO_COUNT (*((PUINT8V)0x40002807)) // RO, TMR2 FIFO count status +#define R32_TMR2_COUNT (*((PUINT32V)0x40002808)) // RO, TMR2 current count +#define R16_TMR2_COUNT (*((PUINT16V)0x40002808)) // RO, TMR2 current count +#define R8_TMR2_COUNT (*((PUINT8V)0x40002808)) // RO, TMR2 current count +#define R32_TMR2_CNT_END (*((PUINT32V)0x4000280C)) // RW, TMR2 end count value, only low 26 bit +#define R32_TMR2_FIFO (*((PUINT32V)0x40002810)) // RO/WO, TMR2 FIFO register, only low 26 bit +#define R16_TMR2_FIFO (*((PUINT16V)0x40002810)) // RO/WO, TMR2 FIFO register +#define R8_TMR2_FIFO (*((PUINT8V)0x40002810)) // RO/WO, TMR2 FIFO register +#define R32_TMR2_DMA_NOW (*((PUINT32V)0x40002814)) // RW, TMR2 DMA current address +//#define R16_TMR2_DMA_NOW (*((PUINT16V)0x40002814)) // RW, TMR2 DMA current address +#define R32_TMR2_DMA_BEG (*((PUINT32V)0x40002818)) // RW, TMR2 DMA begin address +//#define R16_TMR2_DMA_BEG (*((PUINT16V)0x40002818)) // RW, TMR2 DMA begin address +#define R32_TMR2_DMA_END (*((PUINT32V)0x4000281C)) // RW, TMR2 DMA end address +//#define R16_TMR2_DMA_END (*((PUINT16V)0x4000281C)) // RW, TMR2 DMA end address + +/* Timer register address offset and bit define */ +#define TMR_FIFO_SIZE 8 // timer FIFO size (depth) +#define BA_TMR0 ((PUINT8V)0x40002000) // point TMR0 base address +#define BA_TMR1 ((PUINT8V)0x40002400) // point TMR1 base address +#define BA_TMR2 ((PUINT8V)0x40002800) // point TMR2 base address +#define TMR_CTRL_MOD 0 +#define RB_TMR_MODE_IN 0x01 // RW, timer in mode: 0=timer/PWM, 1=capture/count +#define RB_TMR_ALL_CLEAR 0x02 // RW, force clear timer FIFO and count +#define RB_TMR_COUNT_EN 0x04 // RW, timer count enable +#define RB_TMR_OUT_EN 0x08 // RW, timer output enable +#define RB_TMR_OUT_POLAR 0x10 // RW, timer PWM output polarity: 0=default low and high action, 1=default high and low action +#define RB_TMR_CAP_COUNT 0x10 // RW, count sub-mode if RB_TMR_MODE_IN=1: 0=capture, 1=count +#define RB_TMR_PWM_REPEAT 0xC0 // RW, timer PWM repeat mode: 00=1, 01=4, 10=8, 11-16 +#define RB_TMR_CAP_EDGE 0xC0 // RW, timer capture edge mode: 00=disable, 01=edge change, 10=fall to fall, 11-rise to rise +#define TMR_CTRL_DMA 1 +#define RB_TMR_DMA_ENABLE 0x01 // RW, timer1/2 DMA enable +#define RB_TMR_DMA_LOOP 0x04 // RW, timer1/2 DMA address loop enable +#define TMR_INTER_EN 2 +#define RB_TMR_IE_CYC_END 0x01 // RW, enable interrupt for timer capture count timeout or PWM cycle end +#define RB_TMR_IE_DATA_ACT 0x02 // RW, enable interrupt for timer capture input action or PWM trigger +#define RB_TMR_IE_FIFO_HF 0x04 // RW, enable interrupt for timer FIFO half (capture fifo >=4 or PWM fifo <=3) +#define RB_TMR_IE_DMA_END 0x08 // RW, enable interrupt for timer1/2 DMA completion +#define RB_TMR_IE_FIFO_OV 0x10 // RW, enable interrupt for timer FIFO overflow +#define TMR_INT_FLAG 6 +#define RB_TMR_IF_CYC_END 0x01 // RW1, interrupt flag for timer capture count timeout or PWM cycle end +#define RB_TMR_IF_DATA_ACT 0x02 // RW1, interrupt flag for timer capture input action or PWM trigger +#define RB_TMR_IF_FIFO_HF 0x04 // RW1, interrupt flag for timer FIFO half (capture fifo >=4 or PWM fifo <=3) +#define RB_TMR_IF_DMA_END 0x08 // RW1, interrupt flag for timer1/2 DMA completion +#define RB_TMR_IF_FIFO_OV 0x10 // RW1, interrupt flag for timer FIFO overflow +#define TMR_FIFO_COUNT 7 +#define TMR_COUNT 0x08 +#define TMR_CNT_END 0x0C +#define TMR_FIFO 0x10 +#define TMR_DMA_NOW 0x14 +#define TMR_DMA_BEG 0x18 +#define TMR_DMA_END 0x1C + +/* UART0 register */ +#define R32_UART0_CTRL (*((PUINT32V)0x40003000)) // RW, UART0 control +#define R8_UART0_MCR (*((PUINT8V)0x40003000)) // RW, UART0 modem control +#define R8_UART0_IER (*((PUINT8V)0x40003001)) // RW, UART0 interrupt enable +#define R8_UART0_FCR (*((PUINT8V)0x40003002)) // RW, UART0 FIFO control +#define R8_UART0_LCR (*((PUINT8V)0x40003003)) // RW, UART0 line control +#define R32_UART0_STAT (*((PUINT32V)0x40003004)) // RO, UART0 status +#define R8_UART0_IIR (*((PUINT8V)0x40003004)) // RO, UART0 interrupt identification +#define R8_UART0_LSR (*((PUINT8V)0x40003005)) // RO, UART0 line status +#define R8_UART0_MSR (*((PUINT8V)0x40003006)) // RO, UART0 modem status +#define R32_UART0_FIFO (*((PUINT32V)0x40003008)) // RW, UART0 data or FIFO port +#define R8_UART0_RBR (*((PUINT8V)0x40003008)) // RO, UART0 receiver buffer, receiving byte +#define R8_UART0_THR (*((PUINT8V)0x40003008)) // WO, UART0 transmitter holding, transmittal byte +#define R8_UART0_RFC (*((PUINT8V)0x4000300A)) // RO, UART0 receiver FIFO count +#define R8_UART0_TFC (*((PUINT8V)0x4000300B)) // RO, UART0 transmitter FIFO count +#define R32_UART0_SETUP (*((PUINT32V)0x4000300C)) // RW, UART0 setup +#define R16_UART0_DL (*((PUINT16V)0x4000300C)) // RW, UART0 divisor latch +#define R8_UART0_DLL (*((PUINT8V)0x4000300C)) // RW, UART0 divisor latch LSB byte +#define R8_UART0_DLM (*((PUINT8V)0x4000300D)) // RW, UART0 divisor latch MSB byte +#define R8_UART0_DIV (*((PUINT8V)0x4000300E)) // RW, UART0 pre-divisor latch byte, only low 7 bit, from 1 to 0/128 +#define R8_UART0_ADR (*((PUINT8V)0x4000300F)) // RW, UART0 slave address: 0xFF=disable, other=enable + +/* UART1 register */ +#define R32_UART1_CTRL (*((PUINT32V)0x40003400)) // RW, UART1 control +#define R8_UART1_MCR (*((PUINT8V)0x40003400)) // RW, UART1 modem control +#define R8_UART1_IER (*((PUINT8V)0x40003401)) // RW, UART1 interrupt enable +#define R8_UART1_FCR (*((PUINT8V)0x40003402)) // RW, UART1 FIFO control +#define R8_UART1_LCR (*((PUINT8V)0x40003403)) // RW, UART1 line control +#define R32_UART1_STAT (*((PUINT32V)0x40003404)) // RO, UART1 status +#define R8_UART1_IIR (*((PUINT8V)0x40003404)) // RO, UART1 interrupt identification +#define R8_UART1_LSR (*((PUINT8V)0x40003405)) // RO, UART1 line status +#define R32_UART1_FIFO (*((PUINT32V)0x40003408)) // RW, UART1 data or FIFO port +#define R8_UART1_RBR (*((PUINT8V)0x40003408)) // RO, UART1 receiver buffer, receiving byte +#define R8_UART1_THR (*((PUINT8V)0x40003408)) // WO, UART1 transmitter holding, transmittal byte +#define R8_UART1_RFC (*((PUINT8V)0x4000340A)) // RO, UART1 receiver FIFO count +#define R8_UART1_TFC (*((PUINT8V)0x4000340B)) // RO, UART1 transmitter FIFO count +#define R32_UART1_SETUP (*((PUINT32V)0x4000340C)) // RW, UART1 setup +#define R16_UART1_DL (*((PUINT16V)0x4000340C)) // RW, UART1 divisor latch +#define R8_UART1_DLL (*((PUINT8V)0x4000340C)) // RW, UART1 divisor latch LSB byte +#define R8_UART1_DLM (*((PUINT8V)0x4000340D)) // RW, UART1 divisor latch MSB byte +#define R8_UART1_DIV (*((PUINT8V)0x4000340E)) // RW, UART1 pre-divisor latch byte, only low 7 bit, from 1 to 0/128 + +/* UART2 register */ +#define R32_UART2_CTRL (*((PUINT32V)0x40003800)) // RW, UART2 control +#define R8_UART2_MCR (*((PUINT8V)0x40003800)) // RW, UART2 modem control +#define R8_UART2_IER (*((PUINT8V)0x40003801)) // RW, UART2 interrupt enable +#define R8_UART2_FCR (*((PUINT8V)0x40003802)) // RW, UART2 FIFO control +#define R8_UART2_LCR (*((PUINT8V)0x40003803)) // RW, UART2 line control +#define R32_UART2_STAT (*((PUINT32V)0x40003804)) // RO, UART2 status +#define R8_UART2_IIR (*((PUINT8V)0x40003804)) // RO, UART2 interrupt identification +#define R8_UART2_LSR (*((PUINT8V)0x40003805)) // RO, UART2 line status +#define R32_UART2_FIFO (*((PUINT32V)0x40003808)) // RW, UART2 data or FIFO port +#define R8_UART2_RBR (*((PUINT8V)0x40003808)) // RO, UART2 receiver buffer, receiving byte +#define R8_UART2_THR (*((PUINT8V)0x40003808)) // WO, UART2 transmitter holding, transmittal byte +#define R8_UART2_RFC (*((PUINT8V)0x4000380A)) // RO, UART2 receiver FIFO count +#define R8_UART2_TFC (*((PUINT8V)0x4000380B)) // RO, UART2 transmitter FIFO count +#define R32_UART2_SETUP (*((PUINT32V)0x4000380C)) // RW, UART2 setup +#define R16_UART2_DL (*((PUINT16V)0x4000380C)) // RW, UART2 divisor latch +#define R8_UART2_DLL (*((PUINT8V)0x4000380C)) // RW, UART2 divisor latch LSB byte +#define R8_UART2_DLM (*((PUINT8V)0x4000380D)) // RW, UART2 divisor latch MSB byte +#define R8_UART2_DIV (*((PUINT8V)0x4000380E)) // RW, UART2 pre-divisor latch byte, only low 7 bit, from 1 to 0/128 + +/* UART3 register */ +#define R32_UART3_CTRL (*((PUINT32V)0x40003C00)) // RW, UART3 control +#define R8_UART3_MCR (*((PUINT8V)0x40003C00)) // RW, UART3 modem control +#define R8_UART3_IER (*((PUINT8V)0x40003C01)) // RW, UART3 interrupt enable +#define R8_UART3_FCR (*((PUINT8V)0x40003C02)) // RW, UART3 FIFO control +#define R8_UART3_LCR (*((PUINT8V)0x40003C03)) // RW, UART3 line control +#define R32_UART3_STAT (*((PUINT32V)0x40003C04)) // RO, UART3 status +#define R8_UART3_IIR (*((PUINT8V)0x40003C04)) // RO, UART3 interrupt identification +#define R8_UART3_LSR (*((PUINT8V)0x40003C05)) // RO, UART3 line status +#define R32_UART3_FIFO (*((PUINT32V)0x40003C08)) // RW, UART3 data or FIFO port +#define R8_UART3_RBR (*((PUINT8V)0x40003C08)) // RO, UART3 receiver buffer, receiving byte +#define R8_UART3_THR (*((PUINT8V)0x40003C08)) // WO, UART3 transmitter holding, transmittal byte +#define R8_UART3_RFC (*((PUINT8V)0x40003C0A)) // RO, UART3 receiver FIFO count +#define R8_UART3_TFC (*((PUINT8V)0x40003C0B)) // RO, UART3 transmitter FIFO count +#define R32_UART3_SETUP (*((PUINT32V)0x40003C0C)) // RW, UART3 setup +#define R16_UART3_DL (*((PUINT16V)0x40003C0C)) // RW, UART3 divisor latch +#define R8_UART3_DLL (*((PUINT8V)0x40003C0C)) // RW, UART3 divisor latch LSB byte +#define R8_UART3_DLM (*((PUINT8V)0x40003C0D)) // RW, UART3 divisor latch MSB byte +#define R8_UART3_DIV (*((PUINT8V)0x40003C0E)) // RW, UART3 pre-divisor latch byte, only low 7 bit, from 1 to 0/128 + +/* UART register address offset and bit define */ +#define UART_FIFO_SIZE 8 // UART FIFO size (depth) +#define UART_RECV_RDY_SZ 7 // the max FIFO trigger level for UART receiver data available +#define BA_UART0 ((PUINT8V)0x40003000) // point UART0 base address +#define BA_UART1 ((PUINT8V)0x40003400) // point UART1 base address +#define BA_UART2 ((PUINT8V)0x40003800) // point UART2 base address +#define BA_UART3 ((PUINT8V)0x40003C00) // point UART3 base address +#define UART_MCR 0 +#define RB_MCR_DTR 0x01 // RW, UART0 control DTR +#define RB_MCR_RTS 0x02 // RW, UART0 control RTS +#define RB_MCR_OUT1 0x04 // RW, UART0 control OUT1 +#define RB_MCR_OUT2 0x08 // RW, UART control OUT2 +#define RB_MCR_INT_OE 0x08 // RW, UART interrupt output enable +#define RB_MCR_LOOP 0x10 // RW, UART0 enable local loop back +#define RB_MCR_AU_FLOW_EN 0x20 // RW, UART0 enable autoflow control +#define RB_MCR_TNOW 0x40 // RW, UART0 enable TNOW output on DTR pin +#define RB_MCR_HALF 0x80 // RW, UART0 enable half-duplex +#define UART_IER 1 +#define RB_IER_RECV_RDY 0x01 // RW, UART interrupt enable for receiver data ready +#define RB_IER_THR_EMPTY 0x02 // RW, UART interrupt enable for THR empty +#define RB_IER_LINE_STAT 0x04 // RW, UART interrupt enable for receiver line status +#define RB_IER_MODEM_CHG 0x08 // RW, UART0 interrupt enable for modem status change +#define RB_IER_DTR_EN 0x10 // RW, UART0 DTR/TNOW output pin enable +#define RB_IER_RTS_EN 0x20 // RW, UART0 RTS output pin enable +#define RB_IER_TXD_EN 0x40 // RW, UART TXD pin enable +#define RB_IER_RESET 0x80 // WZ, UART software reset control, high action, auto clear +#define UART_FCR 2 +#define RB_FCR_FIFO_EN 0x01 // RW, UART FIFO enable +#define RB_FCR_RX_FIFO_CLR 0x02 // WZ, clear UART receiver FIFO, high action, auto clear +#define RB_FCR_TX_FIFO_CLR 0x04 // WZ, clear UART transmitter FIFO, high action, auto clear +#define RB_FCR_FIFO_TRIG 0xC0 // RW, UART receiver FIFO trigger level: 00-1byte, 01-2bytes, 10-4bytes, 11-7bytes +#define UART_LCR 3 +#define RB_LCR_WORD_SZ 0x03 // RW, UART word bit length: 00-5bit, 01-6bit, 10-7bit, 11-8bit +#define RB_LCR_STOP_BIT 0x04 // RW, UART stop bit length: 0-1bit, 1-2bit +#define RB_LCR_PAR_EN 0x08 // RW, UART parity enable +#define RB_LCR_PAR_MOD 0x30 // RW, UART parity mode: 00-odd, 01-even, 10-mark, 11-space +#define RB_LCR_BREAK_EN 0x40 // RW, UART break control enable +#define RB_LCR_DLAB 0x80 // RW, UART reserved bit +#define RB_LCR_GP_BIT 0x80 // RW, UART general purpose bit +#define UART_IIR 4 +#define RB_IIR_NO_INT 0x01 // RO, UART no interrupt flag: 0=interrupt action, 1=no interrupt +#define RB_IIR_INT_MASK 0x0F // RO, UART interrupt flag bit mask +#define RB_IIR_FIFO_ID 0xC0 // RO, UART FIFO enabled flag +#define UART_LSR 5 +#define RB_LSR_DATA_RDY 0x01 // RO, UART receiver fifo data ready status +#define RB_LSR_OVER_ERR 0x02 // RZ, UART receiver overrun error +#define RB_LSR_PAR_ERR 0x04 // RZ, UART receiver parity error +#define RB_LSR_FRAME_ERR 0x08 // RZ, UART receiver frame error +#define RB_LSR_BREAK_ERR 0x10 // RZ, UART receiver break error +#define RB_LSR_TX_FIFO_EMP 0x20 // RO, UART transmitter fifo empty status +#define RB_LSR_TX_ALL_EMP 0x40 // RO, UART transmitter all empty status +#define RB_LSR_ERR_RX_FIFO 0x80 // RO, indicate error in UART receiver fifo +#define UART_MSR 6 +#define RB_MSR_CTS_CHG 0x01 // RZ, UART0 CTS changed status, high action +#define RB_MSR_DSR_CHG 0x02 // RZ, UART0 DSR changed status, high action +#define RB_MSR_RI_CHG 0x04 // RZ, UART0 RI changed status, high action +#define RB_MSR_DCD_CHG 0x08 // RZ, UART0 DCD changed status, high action +#define RB_MSR_CTS 0x10 // RO, UART0 CTS action status +#define RB_MSR_DSR 0x20 // RO, UART0 DSR action status +#define RB_MSR_RI 0x40 // RO, UART0 RI action status +#define RB_MSR_DCD 0x80 // RO, UART0 DCD action status +#define UART_RBR 8 +#define UART_THR 8 +#define UART_RFC 0x0A +#define UART_TFC 0x0B +#define UART_DLL 0x0C +#define UART_DLM 0x0D +#define UART_DIV 0x0E +#define UART_ADR 0x0F + +/* UART interrupt identification values for IIR bits 3:0 */ +#define UART_II_SLV_ADDR 0x0E // RO, UART0 slave address match +#define UART_II_LINE_STAT 0x06 // RO, UART interrupt by receiver line status +#define UART_II_RECV_RDY 0x04 // RO, UART interrupt by receiver data available +#define UART_II_RECV_TOUT 0x0C // RO, UART interrupt by receiver fifo timeout +#define UART_II_THR_EMPTY 0x02 // RO, UART interrupt by THR empty +#define UART_II_MODEM_CHG 0x00 // RO, UART0 interrupt by modem status change +#define UART_II_NO_INTER 0x01 // RO, no UART interrupt is pending + +/* SPI0 register */ +#define R32_SPI0_CONTROL (*((PUINT32V)0x40004000)) // RW, SPI0 control +#define R8_SPI0_CTRL_MOD (*((PUINT8V)0x40004000)) // RW, SPI0 mode control +#define R8_SPI0_CTRL_CFG (*((PUINT8V)0x40004001)) // RW, SPI0 configuration control +#define R8_SPI0_INTER_EN (*((PUINT8V)0x40004002)) // RW, SPI0 interrupt enable +#define R8_SPI0_CLOCK_DIV (*((PUINT8V)0x40004003)) // RW, SPI0 master clock divisor +#define R8_SPI0_SLAVE_PRE (*((PUINT8V)0x40004003)) // RW, SPI0 slave preset value +#define R32_SPI0_STATUS (*((PUINT32V)0x40004004)) // RW, SPI0 status +#define R8_SPI0_BUFFER (*((PUINT8V)0x40004004)) // RO, SPI0 data buffer +#define R8_SPI0_RUN_FLAG (*((PUINT8V)0x40004005)) // RO, SPI0 work flag +#define R8_SPI0_INT_FLAG (*((PUINT8V)0x40004006)) // RW1, SPI0 interrupt flag +#define R8_SPI0_FIFO_COUNT (*((PUINT8V)0x40004007)) // RO, SPI0 FIFO count status +#define R32_SPI0_TOTAL_CNT (*((PUINT32V)0x4000400C)) // RW, SPI0 total byte count, only low 12 bit +#define R16_SPI0_TOTAL_CNT (*((PUINT16V)0x4000400C)) // RW, SPI0 total byte count, only low 12 bit +#define R32_SPI0_FIFO (*((PUINT32V)0x40004010)) // RW, SPI0 FIFO register +#define R8_SPI0_FIFO (*((PUINT8V)0x40004010)) // RO/WO, SPI0 FIFO register +#define R8_SPI0_FIFO_COUNT1 (*((PUINT8V)0x40004013)) // RO, SPI0 FIFO count status +#define R32_SPI0_DMA_NOW (*((PUINT32V)0x40004014)) // RW, SPI0 DMA current address +//#define R16_SPI0_DMA_NOW (*((PUINT16V)0x40004014)) // RW, SPI0 DMA current address +#define R32_SPI0_DMA_BEG (*((PUINT32V)0x40004018)) // RW, SPI0 DMA begin address +//#define R16_SPI0_DMA_BEG (*((PUINT16V)0x40004018)) // RW, SPI0 DMA begin address +#define R32_SPI0_DMA_END (*((PUINT32V)0x4000401C)) // RW, SPI0 DMA end address +//#define R16_SPI0_DMA_END (*((PUINT16V)0x4000401C)) // RW, SPI0 DMA end address + +/* SPI1 register */ +#define R32_SPI1_CONTROL (*((PUINT32V)0x40004400)) // RW, SPI1 control +#define R8_SPI1_CTRL_MOD (*((PUINT8V)0x40004400)) // RW, SPI1 mode control +#define R8_SPI1_CTRL_CFG (*((PUINT8V)0x40004401)) // RW, SPI1 configuration c +#define R8_SPI1_INTER_EN (*((PUINT8V)0x40004402)) // RW, SPI1 interrupt enabl +#define R8_SPI1_CLOCK_DIV (*((PUINT8V)0x40004403)) // RW, SPI1 master clock di +#define R8_SPI1_SLAVE_PRE (*((PUINT8V)0x40004403)) // RW, SPI1 slave preset va +#define R32_SPI1_STATUS (*((PUINT32V)0x40004404)) // RW, SPI1 status +#define R8_SPI1_BUFFER (*((PUINT8V)0x40004404)) // RO, SPI1 data buffer +#define R8_SPI1_RUN_FLAG (*((PUINT8V)0x40004405)) // RO, SPI1 work flag +#define R8_SPI1_INT_FLAG (*((PUINT8V)0x40004406)) // RW1, SPI1 interrupt flag +#define R8_SPI1_FIFO_COUNT (*((PUINT8V)0x40004407)) // RO, SPI1 FIFO count stat +#define R32_SPI1_TOTAL_CNT (*((PUINT32V)0x4000440C)) // RW, SPI1 total byte coun +#define R16_SPI1_TOTAL_CNT (*((PUINT16V)0x4000440C)) // RW, SPI1 total byte coun +#define R32_SPI1_FIFO (*((PUINT32V)0x40004410)) // RW, SPI1 FIFO register +#define R8_SPI1_FIFO (*((PUINT8V)0x40004410)) // RO/WO, SPI1 FIFO registe +#define R8_SPI1_FIFO_COUNT1 (*((PUINT8V)0x40004413)) // RO, SPI1 FIFO count stat +#define R32_SPI1_DMA_NOW (*((PUINT32V)0x40004414)) // RW, SPI1 DMA current add +//#define R16_SPI1_DMA_NOW (*((PUINT16V)0x40004414)) // RW, SPI1 DMA current add +#define R32_SPI1_DMA_BEG (*((PUINT32V)0x40004418)) // RW, SPI1 DMA begin addre +//#define R16_SPI1_DMA_BEG (*((PUINT16V)0x40004418)) // RW, SPI1 DMA begin addre +#define R32_SPI1_DMA_END (*((PUINT32V)0x4000441C)) // RW, SPI1 DMA end address +//#define R16_SPI1_DMA_END (*((PUINT16V)0x4000441C)) // RW, SPI1 DMA end address + +/* SPI register address offset and bit define */ +#define SPI_FIFO_SIZE 8 // SPI FIFO size (depth) +#define BA_SPI0 ((PUINT8V)0x40004000) // point SPI0 base address +#define BA_SPI1 ((PUINT8V)0x40004400) // point SPI1 base address +#define SPI_CTRL_MOD 0 +#define RB_SPI_MODE_SLAVE 0x01 // RW, SPI slave mode: 0=master/host, 1=slave/device +#define RB_SPI_ALL_CLEAR 0x02 // RW, force clear SPI FIFO and count +#define RB_SPI_2WIRE_MOD 0x04 // RW, SPI enable 2 wire mode: 0=3wire(SCK,MOSI,MISO), 1=2wire(SCK,MISO=MXSX) +#define RB_SPI_MST_SCK_MOD 0x08 // RW, SPI master clock mode: 0=mode 0, 1=mode 3 +#define RB_SPI_SLV_CMD_MOD 0x08 // RW, SPI slave command mode: 0=byte stream, 1=first byte command +#define RB_SPI_FIFO_DIR 0x10 // RW, SPI FIFO direction: 0=out(write @master mode), 1=in(read @master mode) +#define RB_SPI_SCK_OE 0x20 // RW, SPI SCK output enable +#define RB_SPI_MOSI_OE 0x40 // RW, SPI MOSI output enable +#define RB_SPI1_SDO_OE 0x40 // RW, SPI1 SDO output enable +#define RB_SPI_MISO_OE 0x80 // RW, SPI MISO output enable +#define RB_SPI1_SDI_OE 0x80 // RW, SPI1 SDI output enable, SPI1 enable 2 wire mode: 0=3wire(SCK1,SDO,SDI), 1=2wire(SCK1,SDI=SDX) +#define SPI_CTRL_CFG 1 +#define RB_SPI_DMA_ENABLE 0x01 // RW, SPI DMA enable +#define RB_SPI_DMA_LOOP 0x04 // RW, SPI DMA address loop enable +#define RB_SPI_AUTO_IF 0x10 // RW, enable buffer/FIFO accessing to auto clear RB_SPI_IF_BYTE_END interrupt flag +#define RB_SPI_BIT_ORDER 0x20 // RW, SPI bit data order: 0=MSB first, 1=LSB first +#define SPI_INTER_EN 2 +#define RB_SPI_IE_CNT_END 0x01 // RW, enable interrupt for SPI total byte count end +#define RB_SPI_IE_BYTE_END 0x02 // RW, enable interrupt for SPI byte exchanged +#define RB_SPI_IE_FIFO_HF 0x04 // RW, enable interrupt for SPI FIFO half +#define RB_SPI_IE_DMA_END 0x08 // RW, enable interrupt for SPI DMA completion +#define RB_SPI_IE_FIFO_OV 0x10 // RW, enable interrupt for SPI FIFO overflow +#define RB_SPI_IE_FST_BYTE 0x80 // RW, enable interrupt for SPI slave mode first byte received +#define SPI_CLOCK_DIV 3 +#define SPI_SLAVE_PRESET 3 +#define SPI_BUFFER 4 +#define SPI_RUN_FLAG 5 +#define RB_SPI_SLV_CMD_ACT 0x10 // RO, SPI slave command flag +#define RB_SPI_FIFO_READY 0x20 // RO, SPI FIFO ready status +#define RB_SPI_SLV_CS_LOAD 0x40 // RO, SPI slave chip-select loading status +#define RB_SPI_SLV_SELECT 0x80 // RO, SPI slave selection status +#define SPI_INT_FLAG 6 +#define RB_SPI_IF_CNT_END 0x01 // RW1, interrupt flag for SPI total byte count end +#define RB_SPI_IF_BYTE_END 0x02 // RW1, interrupt flag for SPI byte exchanged +#define RB_SPI_IF_FIFO_HF 0x04 // RW1, interrupt flag for SPI FIFO half (RB_SPI_FIFO_DIR ? >=4bytes : <4bytes) +#define RB_SPI_IF_DMA_END 0x08 // RW1, interrupt flag for SPI DMA completion +#define RB_SPI_IF_FIFO_OV 0x10 // RW1, interrupt flag for SPI FIFO overflow +#define RB_SPI_FREE 0x40 // RO, current SPI free status +#define RB_SPI_IF_FST_BYTE 0x80 // RW1, interrupt flag for SPI slave mode first byte received +#define SPI_FIFO_COUNT 7 +#define SPI_TOTAL_CNT 0x0C +#define SPI_FIFO 0x10 +#define SPI_DMA_NOW 0x14 +#define SPI_DMA_BEG 0x18 +#define SPI_DMA_END 0x1C + +/* PWM0/1/2/3 register */ +#define R32_PWM_CONTROL (*((PUINT32V)0x40005000)) // RW, PWM control +#define R8_PWM_CTRL_MOD (*((PUINT8V)0x40005000)) // RW, PWM mode control +#define R8_PWM_CTRL_CFG (*((PUINT8V)0x40005001)) // RW, PWM configuration control +#define R8_PWM_CLOCK_DIV (*((PUINT8V)0x40005002)) // RW, PWM clock divisor +#define R32_PWM_DATA (*((PUINT32V)0x40005004)) // RW, PWM data holding +#define R8_PWM0_DATA (*((PUINT8V)0x40005004)) // RW, PWM0 data holding +#define R8_PWM1_DATA (*((PUINT8V)0x40005005)) // RW, PWM1 data holding +#define R8_PWM2_DATA (*((PUINT8V)0x40005006)) // RW, PWM2 data holding +#define R8_PWM3_DATA (*((PUINT8V)0x40005007)) // RW, PWM3 data holding + +/* PWM0/1/2/3 register address offset and bit define */ +#define BA_PWMX ((PUINT8V)0x40005000) // point PWM0/1/2/3 base address +#define PWM_CTRL_MOD 0 +#define RB_PWM0_OUT_EN 0x01 // RW, PWM0 output enable +#define RB_PWM1_OUT_EN 0x02 // RW, PWM1 output enable +#define RB_PWM2_OUT_EN 0x04 // RW, PWM2 output enable +#define RB_PWM3_OUT_EN 0x08 // RW, PWM3 output enable +#define RB_PWM0_POLAR 0x10 // RW, PWM0 output polarity: 0=default low and high action, 1=default high and low action +#define RB_PWM1_POLAR 0x20 // RW, PWM1 output polarity: 0=default low and high action, 1=default high and low action +#define RB_PWM2_POLAR 0x40 // RW, PWM2 output polarity: 0=default low and high action, 1=default high and low action +#define RB_PWM3_POLAR 0x80 // RW, PWM3 output polarity: 0=default low and high action, 1=default high and low action +#define PWM_CTRL_CFG 1 +#define RB_PWM_CYCLE_SEL 0x01 // RW, PWM cycle selection: 0=256 clocks, 1=255 clocks +#define PWM_CLOCK_DIV 2 +#define PWM0_DATA_HOLD 4 +#define PWM1_DATA_HOLD 5 +#define PWM2_DATA_HOLD 6 +#define PWM3_DATA_HOLD 7 + +/* HSPI register */ +#define R32_HSPI_CR (*((PUINT32V)0x40006000)) // RW, parallel if control +#define R8_HSPI_CFG (*((PUINT8V)0x40006000)) // RW, parallel if tx/rx cfg +#define R8_HSPI_CTRL (*((PUINT8V)0x40006001)) // RW, parallel if tx/rx control +#define R8_HSPI_INT_EN (*((PUINT8V)0x40006002)) // RW, parallel if interrupt enable register +#define R8_HSPI_AUX (*((PUINT8V)0x40006003)) // RW, parallel if aux +#define R32_HSPI_TX_ADDR0 (*((PUINT32V)0x40006004)) // RW, parallel if dma tx addr0 +#define R32_HSPI_TX_ADDR1 (*((PUINT32V)0x40006008)) // RW, parallel if dma tx addr1 +#define R32_HSPI_RX_ADDR0 (*((PUINT32V)0x4000600C)) // RW, parallel if dma rx addr0 +#define R32_HSPI_RX_ADDR1 (*((PUINT32V)0x40006010)) // RW, parallel if dma rx addr1 +#define R16_HSPI_DMA_LEN0 (*((PUINT16V)0x40006014)) // RW, parallel if dma length0 +#define R16_HSPI_RX_LEN0 (*((PUINT16V)0x40006016)) // RO, parallel if receive length0 +#define R16_HSPI_DMA_LEN1 (*((PUINT16V)0x40006018)) // RW, parallel if dma length1 +#define R16_HSPI_RX_LEN1 (*((PUINT16V)0x4000601A)) // RO, parallel if receive length1 +#define R16_HSPI_BURST_CFG (*((PUINT16V)0x4000601C)) // RW, parallel if tx burst config register +#define R8_HSPI_BURST_CNT (*((PUINT8V)0x4000601E)) // RO, parallel if tx burst count +#define R32_HSPI_UDF0 (*((PUINT32V)0x40006020)) // RW, parallel if +#define R32_HSPI_UDF1 (*((PUINT32V)0x40006024)) // RW, parallel if +#define R32_HSPI_STATUS (*((PUINT32V)0x40006028)) // RW, parallel if status +#define R8_HSPI_INT_FLAG (*((PUINT8V)0x40006028)) // RW1, parallel if interrupt flag +#define R8_HSPI_RTX_STATUS (*((PUINT8V)0x40006029)) // RO, parallel rtx status +#define R8_HSPI_TX_SC (*((PUINT8V)0x4000602A)) // RW, parallel TX sequence ctrl +#define R8_HSPI_RX_SC (*((PUINT8V)0x4000602B)) // RW, parallel RX sequence ctrl + +/* HSPI register address offset and bit define */ +#define HSPI_RTX_CFG 0 +#define RB_HSPI_MODE 0x01 // RW, parallel if mode: 1=UP, 0=DOWN +#define RB_HSPI_DUALDMA 0x02 // RW, parallel if dualdma mode enable +#define RB_HSPI_MSK_SIZE 0x0C // RW, parallel if data mode +#define RB_HSPI_DAT8_MOD 0x00 // RW, 00=8bits mode +#define RB_HSPI_DAT16_MOD 0x04 // RW, 01=16bits mode +#define RB_HSPI_DAT32_MOD 0x08 // RW, 10=32bits mode +#define RB_HSPI_TX_TOG_EN 0x20 // RW, parallel if tx addr toggle enable +#define RB_HSPI_RX_TOG_EN 0x40 // RW, parallel if rx addr toggle enable +#define RB_HSPI_HW_ACK 0x80 // RW, parallel if tx ack by hardware +#define HSPI_RTX_CTRL 1 +#define RB_HSPI_ENABLE 0x01 // RW, parallel if enable +#define RB_HSPI_DMA_EN 0x02 // RW, parallel if dma enable +#define RB_HSPI_SW_ACT 0x04 // RW, parallel if transmit software trigger +#define RB_HSPI_ALL_CLR 0x08 // RW, parallel if all clear +#define RB_HSPI_TRX_RST 0x10 // RW, parallel if tx and rx logic clear, high action +#define HSPI_INT_EN 2 +#define RB_HSPI_IE_T_DONE 0x01 // RW, parallel if transmit done interrupt enable +#define RB_HSPI_IE_R_DONE 0x02 // RW, parallel if receive done interrupt enable +#define RB_HSPI_IE_FIFO_OV 0x04 // RW, parallel if fifo overflow interrupt enable +#define RB_HSPI_IE_B_DONE 0x08 // RW, RW, parallel if tx burst done interrupt enable +#define HSPI_RTX_AUX 3 +#define RB_HSPI_TCK_MOD 0x01 // RW, parallel if tx clk polar control, 0=not invert, 1=invert +#define RB_HSPI_RCK_MOD 0x02 // RW, parallel if rx clk polar control, 0=not invert, 1=invert +#define RB_HSPI_ACK_TX_MOD 0x04 // RW, parallel if tx ack mode cfg, 0=ram write done to send, 1=delay done to send +#define RB_HSPI_ACK_CNT_SEL 0x18 // RW, delay time of parallel if send ack when receive done +#define RB_ACK_CNT_2 0x00 // RW, delay 2 clock to send ack +#define RB_ACK_CNT_4 0x08 // RW, delay 4 clock to send ack +#define RB_ACK_CNT_6 0x10 // RW, delay 6 clock to send ack +#define RB_ACK_CNT_8 0x18 // RW, delay 8 clock to send ack +#define RB_HSPI_REQ_FT 0x20 // RW, enable fast DMA request +#define HSPI_TX_ADDR0 4 +#define HSPI_TX_ADDR1 5 +#define HSPI_RX_ADDR0 6 +#define HSPI_RX_ADDR1 7 +#define HSPI_BURST_CFG 8 +#define RB_HSPI_BURST_EN 0x0001 // RW, burst transmit enable +#define RB_HSPI_BURST_LEN 0xFF00 // RW, burst transmit length +#define HSPI_UDF0 9 +#define HSPI_UDF1 10 +#define HSPI_INT_FLAG 11 +#define RB_HSPI_IF_T_DONE 0x01 // RW1, interrupt flag for parallel if transmit done +#define RB_HSPI_IF_R_DONE 0x02 // RW1, interrupt flag for parallel if receive done +#define RB_HSPI_IF_FIFO_OV 0x04 // RW1, interrupt flag for parallel if FIFO overflow +#define RB_HSPI_IF_B_DONE 0x08 // RW1, interrupt flag for parallel if tx burst done +#define HSPI_RTX_STATUS 12 +//#define RB_HSPI_TX_OK 0x01 // RO, data transmit OK (received ack) +#define RB_HSPI_CRC_ERR 0x02 // RO, CRC error occur +#define RB_HSPI_NUM_MIS 0x04 // RO, rx and tx sequence number mismatch +#define HSPI_TX_SC 13 +#define RB_HSPI_TX_NUM 0x0F // RW, parallel if tx sequence num +#define RB_HSPI_TX_TOG 0x10 // RW, parallel if tx addr toggle flag +#define HSPI_RX_SC 14 +#define RB_HSPI_RX_NUM 0x0F // RW, parallel if rx sequence num +#define RB_HSPI_RX_TOG 0x10 // RW, parallel if rx addr toggle flag + +/* DVP registr */ +#define R32_DVP_CR (*((PUINT32V)0x4000E000)) // RW, DVP control register +#define R8_DVP_CR0 (*((PUINT8V)0x4000E000)) // RW, DVP control register0 +#define R8_DVP_CR1 (*((PUINT8V)0x4000E001)) // RW, DVP control register1 +#define R8_DVP_INT_EN (*((PUINT8V)0x4000E002)) // RW, DVP interrupt enable register +#define R16_DVP_ROW_NUM (*((PUINT16V)0x4000E004)) // RW, DVP row number of a frame indicator register +#define R16_DVP_COL_NUM (*((PUINT16V)0x4000E006)) // RW, DVP col number of a frame indicator register +#define R32_DVP_DMA_BUF0 (*((PUINT32V)0x4000E008)) // RW, DVP dma buffer0 addr +#define R32_DVP_DMA_BUF1 (*((PUINT32V)0x4000E00c)) // RW, DVP dma buffer1 addr +#define R32_DVP_STATUS (*((PUINT32V)0x4000E010)) +#define R8_DVP_INT_FLAG (*((PUINT8V)0x4000E010)) // RW1, DVP interrupt flag register +#define R8_DVP_FIFO_ST (*((PUINT8V)0x4000E011)) // RO, DVP receive fifo status +#define R16_DVP_ROW_CNT (*((PUINT16V)0x4000E014)) // RO, DVP row count value +#define R16_DVP_COL_CNT (*((PUINT16V)0x4000E016)) // RO, DVP col count value + +/* DVP register address offset and bit define */ +#define DVP_CR0 0 +#define RB_DVP_ENABLE 0x01 // RW, DVP enable +#define RB_DVP_V_POLAR 0x02 // RW, DVP VSYNC polarity control: 1 = invert, 0 = not invert +#define RB_DVP_H_POLAR 0x04 // RW, DVP HSYNC polarity control: 1 = invert, 0 = not invert +#define RB_DVP_P_POLAR 0x08 // RW, DVP PCLK polarity control: 1 = invert, 0 = not invert +#define RB_DVP_MSK_DAT_MOD 0x30 +#define RB_DVP_D8_MOD 0x00 // RW, DVP 8bits data mode +#define RB_DVP_D10_MOD 0x10 // RW, DVP 10bits data mode +#define RB_DVP_D12_MOD 0x20 // RW, DVP 12bits data mode +#define RB_DVP_JPEG 0x40 // RW, DVP JPEG mode +#define RB_DVP_RAW_CM 0x80 // RW, DVP row count mode: 1 = count on falling edge of HSYNC, 0 = count on the end of col count +#define DVP_CR1 1 +#define RB_DVP_DMA_EN 0x01 // RW, DVP dma enable +#define RB_DVP_ALL_CLR 0x02 // RW, DVP all clear, high action +#define RB_DVP_RCV_CLR 0x04 // RW, DVP receive logic clear, high action +#define RB_DVP_BUF_TOG 0x08 // RW, DVP bug toggle by software, write 1 to toggle, ignored writing 0 +#define DVP_INT_EN 2 +#define RB_DVP_IE_STR_FRM 0x01 // RW, DVP frame start interrupt enable +#define RB_DVP_IE_ROW_DONE 0x02 // RW, DVP row received done interrupt enable +#define RB_DVP_IE_FRM_DONE 0x04 // RW, DVP frame received done interrupt enable +#define RB_DVP_IE_FIFO_OV 0x08 // RW, DVP receive fifo overflow interrupt enable +#define RB_DVP_IE_STP_FRM 0x10 // RW, DVP frame stop interrupt enable +#define DVP_ROW_NUM 3 +#define DVP_DMA_BUF0 4 +#define DVP_DMA_BUF1 5 +#define DVP_INT_FLAG 6 +#define RB_DVP_IF_STR_FRM 0x01 // RW1, interrupt flag for DVP frame start +#define RB_DVP_IF_ROW_DONE 0x02 // RW1, interrupt flag for DVP row receive done +#define RB_DVP_IF_FRM_DONE 0x04 // RW1, interrupt flag for DVP frame receive done +#define RB_DVP_IF_FIFO_OV 0x08 // RW1, interrupt flag for DVP receive fifo overflow +#define RB_DVP_IF_STP_FRM 0x10 // RW1, interrupt flag for DVP frame stop +#define DVP_FIFO_ST 7 +#define RB_DVP_FIFO_RDY 0x01 // RO, DVP receive fifo ready +#define RB_DVP_FIFO_FULL 0x02 // RO, DVP receive fifo full +#define RB_DVP_FIFO_OV 0x04 // RO, DVP receive fifo overflow +#define RB_DVP_MSK_FIFO_CNT 0x70 // RO, DVP receive fifo count +#define DVP_ROW_CNT 8 +#define DVP_COL_CNT 9 + +/* SPI Flash register */ +#define R32_SPI_ROM_CTRL (*((PUINT32V)0x40001018)) +#define R8_SPI_ROM_DATA (*((PUINT8V)0x40001018)) //RW +#define R16_SPI_ROM_CR (*((PUINT16V)0x4000101A)) //RW + +/* SPI Flash register address offset and bit define */ +#define SPI_ROM_DATA 0 +#define SPI_ROM_CR 1 +#define RB_ROM_SCS 0x0001 +#define RB_ROM_SIO0_OE 0x0002 +#define RB_ROM_RD_EN 0x0004 +#define RB_ROM_WR8 0x0008 +#define RB_ROM_DES_LONG 0x0100 + +/* EMMC register */ +#define R16_EMMC_CLK_DIV (*((PUINT16V)(0x4000A038))) // SD clock divider register, [4:0]:divisor, sdclk1 = 480m/[4:0], default divisor is 20 + // [8]:clk_oe, [8]==1 indicate supply SDCLK to sdcard, [8]==0 indicate close SDCLK, default clk_oe is 0 + // [9]:sel_25m_100m, select 400k or 25~100m as SDCLK, [9]==1 indicate SDCLK = 480m/[4:0], [9]==0 indicate SDCLK = 480/[4:0]/64, default is 1 +#define R32_EMMC_ARGUMENT (*((PUINT32V)(0x4000A000))) // SD 32bits command argument register +#define R16_EMMC_CMD_SET (*((PUINT16V)(0x4000A004))) // SD 16bits cmd setting register, [5:0] is the command index, [9:8] indicate the response tye, [10]==1 indicate need to check the response CRC7, [11]==1 indicate need to check the index of the response +#define R32_EMMC_RESPONSE0 (*((PUINT32V)(0x4000A008))) // SD 128bits response register, [31:0] 32bits +#define R32_EMMC_RESPONSE1 (*((PUINT32V)(0x4000A00c))) // SD 128bits response register, [63:32] 32bits +#define R32_EMMC_RESPONSE2 (*((PUINT32V)(0x4000A010))) // SD 128bits response register, [95:64] 32bits +#define R32_EMMC_RESPONSE3 (*((PUINT32V)(0x4000A014))) // SD 128bits response register, [127:96] 32bits, when response length is 48, the 32bit response data is stored in this register +#define R8_EMMC_CONTROL (*((PUINT8V)(0x4000A018))) // SD 8bits control register, [1:0] number of data line will operate, [2]==1 soft reset all the inner logic, [3]==1 enable DMA, [4]==1 reset inner data tran/recv logic, [5]==1 @negedge sample cmd/dat[7:0] lines +#define R8_EMMC_TIMEOUT (*((PUINT8V)(0x4000A01c))) // SD 8bits data timeout value, the real timeout time is 4194304*Tsdclk*value +#define R32_EMMC_STATUS (*((PUINT32V)(0x4000A020))) // SD status:[15:0] number of current successfull tran/recv blocks, [16] current sd cmd line level, [17] current sd dat[0] line level +#define R16_EMMC_INT_FG (*((PUINT16V)(0x4000A024))) // SD 16bits interrupt flag register +#define R16_EMMC_INT_EN (*((PUINT16V)(0x4000A028))) // SD 16bits interrupt enable register +#define R32_EMMC_DMA_BEG1 (*((PUINT32V)(0x4000A02C))) // SD 16bits DMA start address register when to operate +#define R32_EMMC_BLOCK_CFG (*((PUINT32V)(0x4000A030))) // SD 32bits data counter, [15:0] number of blocks this time will tran/recv, [27:16] block sise(byte number) of every block in this time tran/recv +#define R32_EMMC_TRAN_MODE (*((PUINT32V)(0x4000A034))) // SD TRANSFER MODE register, [0] direction of this time, 1-write sd, 0-read sd, [1] stop at block gap when multiple wr/rd, [2] this time is eMMC boot mode operation +#define R32_EMMC_DMA_BEG2 (*((PUINT32V)(0x4000A03C))) + +/* EMMC register address offset and bit define */ +#define EMMC_CLK_DIV 0x38 +#define RB_EMMC_PHASEINV 0x400 // invert chip output sdclk phase +#define RB_EMMC_CLKMode 0x200 // 1:25-100m 0:400k +#define RB_EMMC_CLKOE 0x100 // chip output sdclk oe +#define RB_EMMC_DIV_MASK 0x1F // clk div +#define EMMC_ARGUMENT 0x00 +#define EMMC_CMD_SET 0x04 +#define RB_EMMC_CKIDX 0x800 +#define RB_EMMC_CKCRC 0x400 +#define RB_EMMC_RPTY_MASK 0x300 +#define RB_EMMC_CMDIDX_MASK 0x3F +#define EMMC_RESPONSE0 0x08 +#define EMMC_RESPONSE1 0x0c +#define EMMC_RESPONSE2 0x10 +#define EMMC_RESPONSE3 0x14 +#define EMMC_WRITE_CONT 0x14 +#define EMMC_CONTROL 0x18 +#define RB_EMMC_NEGSMP 0x0020 // controller use nagedge sample cmd, dat[7:0], when use UHS-I mode, timing is difficult to meet, use the negedge will be better, default is @posedge sample +#define RB_EMMC_RST_LGC 0x0010 // reset the data tran/recv logic, this bit is useful when block CRC error in multiple rd/wr situation, default is valid +#define RB_EMMC_DMAEN 0x0008 // enable the dma, if the 1# 2# 3# controller is to be used, should also open the 0# dma enable, 0# dma work as the whole enable, default dma is closed +#define RB_EMMC_ALL_CLR 0x0004 // reset all the inner logic, default is valid +#define RB_EMMC_LW_MASK 0x0003 +#define bLW_OP_DAT8 0x0002 // use data line [7:0], can be set only in 0# 2# controller +#define bLW_OP_DAT4 0x0001 // use data line [3:0], the default is this value +#define bLW_OP_DAT0 0x0000 // use data line [0] only +#define EMMC_TIMEOUT 0x1C +#define RB_EMMC_TOCNT_MASK 0x000F +#define EMMC_STATUS 0x20 // SD status +#define RB_EMMC_DAT0STA 0x20000 // indicate dat[0] line is high level now +#define RB_EMMC_CMDSTA 0x10000 // indicate cmd line is high level now +#define EMMC_INT_FG 0x24 +#define RB_EMMC_IF_SDIOINT 0x200 // interrupt from SDIO card inside +#define RB_EMMC_IF_FIFO_OV 0x100 // fifo overflow, when write sd, indicate empty overflow, when read sd, indicate full overflow +#define RB_EMMC_IF_BKGAP 0x080 // every block gap interrupt when multiple read/write, allow drive change the DMA address at this moment +#define RB_EMMC_IF_TRANDONE 0x040 // all the blocks have been tran/recv successfully +#define RB_EMMC_IF_TRANERR 0x020 // last block have encountered a CRC error +#define RB_EMMC_IF_DATTMO 0x010 // data line busy timeout +#define RB_EMMC_IF_CMDDONE 0x008 // when cmd hasn't response, indicate cmd has been sent, when cmd has a response, indicate cmd has bee sent and has received the response +#define RB_EMMC_IF_REIDX_ER 0x004 // indicate INDEX error of the response +#define RB_EMMC_IF_RECRC_WR 0x002 // indicate CRC error of the response +#define RB_EMMC_IF_RE_TMOUT 0x001 // indicate when expect the response, timeout +#define EMMC_INT_EN 0x28 // interrupt enable +#define RB_EMMC_IE_SDIOINT 0x200 +#define RB_EMMC_IE_FIFO_OV 0x100 +#define RB_EMMC_IE_BKGAP 0x080 +#define RB_EMMC_IE_TRANDONE 0x040 +#define RB_EMMC_IE_TRANERR 0x020 +#define RB_EMMC_IE_DATTMO 0x010 +#define RB_EMMC_IE_CMDDONE 0x008 +#define RB_EMMC_IE_REIDX_ER 0x004 +#define RB_EMMC_IE_RECRC_WR 0x002 +#define RB_EMMC_IE_RE_TMOUT 0x001 +#define EMMC_DMA_BEG1 0x2c +#define RB_EMMC_DMAAD1_MASK 0x1FFFF +#define EMMC_BLOCK_CFG 0x30 +#define RB_EMMC_BKSIZE_MASK 0x01FF0000 +#define RB_EMMC_BKNUM_MASK 0xFFFF +#define EMMC_TRAN_MODE 0x34 // tran mode +#define RB_EMMC_DULEDMA_EN 0x10000 // enable double buffer dma +#define RB_EMMC_DMATN_CNT 0x7f00 +#define RB_EMMC_FIFO_RDY 0x00c0 +#define RB_EMMC_AUTOGAPSTOP 0x00010 // enable auto set bTM_GAP_STOP when tran start +#define RB_EMMC_MODE_BOOT 0x00004 // enable emmc boot mode +#define RB_EMMC_GAP_STOP 0x00002 // set gap stop +#define RB_EMMC_DMA_DIR 0x00001 // set direction is controller to emmc card + +/* ECED AES/SM4 register */ +#define R16_ECEC_CTRL (*((PUINT16V)(0x40007000))) +#define RB_ECDC_DAT_MOD 0x02000 // source data and result data is bit endian +#define RB_ECDC_KLEN_MASK 0x0C00 +#define RB_ECDC_CIPHER_MOD 0x0200 // 1:CTR mode 0:ECB mode +#define RB_ECDC_ALGRM_MOD 0x0100 // 1:AES 0:SM4 +#define RB_ECDC_WRSRAM_EN 0x0080 // module dma enable +#define RB_ECDC_CLKDIV_MASK 0x0030 +#define RB_ECDC_MODE_SEL 0x0008 // 1:decryption mode 0:encryption mode +#define RB_ECDC_WRPERI_EN 0x0004 // when read data from dma, 1:encrypt/decrypt 0:no action +#define RB_ECDC_RDPERI_EN 0x0002 // when write data to dma, 1:encrypt/decrypt 0:no action +#define RB_ECDC_KEYEX_EN 0x0001 // enable key expansion + +#define R8_ECDC_INT_EN (*((PUINT8V)(0x40007002))) +#define RB_ECDC_IE_WRSRAM 0x04 // interrupt en +#define RB_ECDC_IE_SINGLE 0x02 // interrupt en +#define RB_ECDC_IE_EKDONE 0x01 // interrupt en + +#define R8_ECDC_INT_FG (*((PUINT8V)(0x40007006))) +#define RB_ECDC_IF_WRSRAM 0x04 // interrupt en +#define RB_ECDC_IF_SINGLE 0x02 // interrupt en +#define RB_ECDC_IF_EKDONE 0x01 // interrupt en + +// the following 8*32-bit registers are used to store 128/192/256-bit key +#define R32_ECDC_KEY_255T224 (*((PUINT32V)(0x40007008))) +#define R32_ECDC_KEY_223T192 (*((PUINT32V)(0x4000700c))) +#define R32_ECDC_KEY_191T160 (*((PUINT32V)(0x40007010))) +#define R32_ECDC_KEY_159T128 (*((PUINT32V)(0x40007014))) +#define R32_ECDC_KEY_127T96 (*((PUINT32V)(0x40007018))) +#define R32_ECDC_KEY_95T64 (*((PUINT32V)(0x4000701c))) +#define R32_ECDC_KEY_63T32 (*((PUINT32V)(0x40007020))) +#define R32_ECDC_KEY_31T0 (*((PUINT32V)(0x40007024))) + +// the following 4*32-bit registers are used to store initial vector for CTR mode +#define R32_ECDC_IV_127T96 (*((PUINT32V)(0x40007028))) +#define R32_ECDC_IV_95T64 (*((PUINT32V)(0x4000702c))) +#define R32_ECDC_IV_63T32 (*((PUINT32V)(0x40007030))) +#define R32_ECDC_IV_31T0 (*((PUINT32V)(0x40007034))) + +#define R32_ECDC_SGSD_127T96 (*((PUINT32V)(0x40007040))) +#define R32_ECDC_SGSD_95T64 (*((PUINT32V)(0x40007044))) +#define R32_ECDC_SGSD_63T32 (*((PUINT32V)(0x40007048))) +#define R32_ECDC_SGSD_31T0 (*((PUINT32V)(0x4000704C))) + +#define R32_ECDC_SGRT_127T96 (*((PUINT32V)(0x40007050))) +#define R32_ECDC_SGRT_95T64 (*((PUINT32V)(0x40007054))) +#define R32_ECDC_SGRT_63T32 (*((PUINT32V)(0x40007058))) +#define R32_ECDC_SGRT_31T0 (*((PUINT32V)(0x4000705C))) + +#define R32_ECDC_SRAM_ADDR (*((PUINT32V)(0x40007060))) +#define R32_ECDC_SRAM_LEN (*((PUINT32V)(0x40007064))) + +/* Address space define */ +#define BA_CODE ((PUINT32)0x00000000) // point code base address +#define SZ_CODE 0x00080000 // code size, Min:32KB, Max:96KB +#define BA_SFR ((PUINT32)0x40000000) // point SFR base address +#define SZ_SFR 0x00010000 // SFR size +#define BA_RAM ((PUINT32)0x20000000) // point RAM base address +#define SZ_RAM 0x00004000 // RAM size +#define BA_RAMX ((PUINT32)0x20020000) // point RAMX base address +#define SZ_RAMX 0x00018000 // RAMX size, Min:32KB, Max:96KB +#define BA_XBUS ((PUINT32)0x80000000) // point XBUS base address +#define SZ_XBUS 0x00008000 // XBUS size + +/*----- Reference Information --------------------------------------------*/ +#define ID_CH569W 0x71 // chip ID for CH569W +#define ID_CH565W 0x73 // chip ID for CH565W + +/* Interrupt routine address and interrupt number */ +#define INT_ID_WDOG 16 // interrupt number for watch-dog timer or software +#define INT_ID_TMR0 17 // interrupt number for timer0 +#define INT_ID_GPIO 18 // interrupt number for GPIO +#define INT_ID_SPI0 19 // interrupt number for SPI0 +#define INT_ID_USBSS 20 // interrupt number for USBSS +#define INT_ID_LINK 21 // interrupt number for USBSS Linklayer +#define INT_ID_TMR1 22 // interrupt number for timer1 +#define INT_ID_TMR2 23 // interrupt number for timer2 +#define INT_ID_UART0 24 // interrupt number for UART0 +#define INT_ID_USBHS 25 // interrupt number for USBHS +#define INT_ID_EMMC 26 // interrupt number for EMMC +#define INT_ID_DVP 27 // interrupt number for DVP +#define INT_ID_HSPI 28 // interrupt number for HSPI +#define INT_ID_SPI1 29 // interrupt number for SPI1 +#define INT_ID_UART1 30 // interrupt number for UART1 +#define INT_ID_UART2 31 // interrupt number for UART2 +#define INT_ID_UART3 32 // interrupt number for UART3 +#define INT_ID_SERDES 33 // interrupt number for SERDES +#define INT_ID_ETH 34 // interrupt number for ETH +#define INT_ID_PMT 35 // interrupt number for ETH power management +#define INT_ID_ECDC 36 // interrupt number for ECDC + +#define INT_VEC_ENTRY_SZ 4 // size of each interrupt vector entry +#define INT_ADDR_WDOG (INT_ID_WDOG * INT_VEC_ENTRY_SZ) // interrupt vector address for watch-dog timer or software +#define INT_ADDR_TMR0 (INT_ID_TMR0 * INT_VEC_ENTRY_SZ) // interrupt vector address for TMR0 +#define INT_ADDR_GPIO (INT_ID_GPIO * INT_VEC_ENTRY_SZ) // interrupt vector address for GPIO +#define INT_ADDR_SPI0 (INT_ID_SPI0 * INT_VEC_ENTRY_SZ) // interrupt vector address for SPI0 +#define INT_ADDR_USBSS (INT_ID_USBSS * INT_VEC_ENTRY_SZ) // interrupt vector address for USBSS +#define INT_ADDR_LINK (INT_ID_LINK * INT_VEC_ENTRY_SZ) // interrupt vector address for USBSS Linklayer +#define INT_ADDR_TMR1 (INT_ID_TMR1 * INT_VEC_ENTRY_SZ) // interrupt vector address for TMR1 +#define INT_ADDR_TMR2 (INT_ID_TMR2 * INT_VEC_ENTRY_SZ) // interrupt vector address for TMR2 +#define INT_ADDR_UART0 (INT_ID_UART0 * INT_VEC_ENTRY_SZ) // interrupt vector address for UART0 +#define INT_ADDR_USBHS (INT_ID_USBHS * INT_VEC_ENTRY_SZ) // interrupt vector address for USBHS +#define INT_ADDR_EMMC (INT_ID_EMMC * INT_VEC_ENTRY_SZ) // interrupt vector address for EMMC +#define INT_ADDR_DVP (INT_ID_DVP * INT_VEC_ENTRY_SZ) // interrupt vector address for DVP +#define INT_ADDR_HSPI (INT_ID_HSPI * INT_VEC_ENTRY_SZ) // interrupt vector address for HSPI +#define INT_ADDR_SPI1 (INT_ID_SPI1 * INT_VEC_ENTRY_SZ) // interrupt vector address for SPI1 +#define INT_ADDR_UART1 (INT_ID_UART1 * INT_VEC_ENTRY_SZ) // interrupt vector address for UART1 +#define INT_ADDR_UART2 (INT_ID_UART2 * INT_VEC_ENTRY_SZ) // interrupt vector address for UART2 +#define INT_ADDR_UART3 (INT_ID_UART3 * INT_VEC_ENTRY_SZ) // interrupt vector address for UART3 +#define INT_ADDR_SERDES (INT_ID_SERDES * INT_VEC_ENTRY_SZ) // interrupt vector address for SERDES +#define INT_ADDR_ETH (INT_ID_ETH * INT_VEC_ENTRY_SZ) // interrupt vector address for ETH +#define INT_ADDR_PMT (INT_ID_PMT * INT_VEC_ENTRY_SZ) // interrupt vector address for ETH power management +#define INT_ADDR_ECDC (INT_ID_ECDC * INT_VEC_ENTRY_SZ) // interrupt vector address for ECDC + +#ifndef TABLE_IRQN +typedef enum IRQn +{ + Reset_IRQn = 1, + NMI_IRQn = 2, /*!< Non Maskable Interrupt */ + EXC_IRQn = 3, /*!< Exceptions Interrupt */ + SysTick_IRQn = 12, /*!< System timer Interrupt */ + SWI_IRQn = 14, /*!< software Interrupt */ + WDOG_IRQn = 16, + TMR0_IRQn = 17, + GPIO_IRQn = 18, + SPI0_IRQn = 19, + USBSS_IRQn = 20, + LINK_IRQn = 21, + TMR1_IRQn = 22, + TMR2_IRQn = 23, + UART0_IRQn = 24, + USBHS_IRQn = 25, + EMMC_IRQn = 26, + DVP_IRQn = 27, + HSPI_IRQn = 28, + SPI1_IRQn = 29, + UART1_IRQn = 30, + UART2_IRQn = 31, + UART3_IRQn = 32, + SERDES_IRQn = 33, + ETH_IRQn = 34, + PMT_IRQn = 35, + ECDC_IRQn = 36, +} IRQn_Type; +#endif + +#ifdef __cplusplus +} +#endif + +#endif // __CH56xGPSFR_H__ + +#ifndef __CH56xUSBSFR_H__ +#define __CH56xUSBSFR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* usb addresses */ +#define USB_BASE_ADDR (0x40009000) + +#define R32_USB_CONTROL (*((PUINT32V)(USB_BASE_ADDR + 0x000))) // USB control & interrupt enable & device address +#define R8_USB_CTRL (*((PUINT8V)(USB_BASE_ADDR + 0x000))) // USB base control +#define R8_UHOST_CTRL (*((PUINT8V)(USB_BASE_ADDR + 0x001))) // USB actual speed +#define R8_USB_INT_EN (*((PUINT8V)(USB_BASE_ADDR + 0x002))) // USB interrupt enable +#define R8_USB_DEV_AD (*((PUINT8V)(USB_BASE_ADDR + 0x003))) // USB device address +#define R32_USB_FRAME_NO (*((PUINT32V)(USB_BASE_ADDR + 0x004))) +#define R16_USB_FRAME_NO (*((PUINT16V)(USB_BASE_ADDR + 0x004))) +#define R8_USB_SUSPEND (*((PUINT8V)(USB_BASE_ADDR + 0x006))) +#define R32_USB_STATUS (*((PUINT32V)(USB_BASE_ADDR + 0x008))) // USB miscellaneous status & interrupt flag & interrupt status +#define R8_USB_SPD_TYPE (*((PUINT8V)(USB_BASE_ADDR + 0x008))) // USB actual speed +#define R8_USB_MIS_ST (*((PUINT8V)(USB_BASE_ADDR + 0x009))) // USB miscellaneous status +#define R8_USB_INT_FG (*((PUINT8V)(USB_BASE_ADDR + 0x00a))) // USB interrupt flag +#define R8_USB_INT_ST (*((PUINT8V)(USB_BASE_ADDR + 0x00b))) // USB interrupt status +#define R16_USB_RX_LEN (*((PUINT16V)(USB_BASE_ADDR + 0x00c))) // USB receiving length +#define R32_USB_BUF_MODE (*((PUINT32V)(USB_BASE_ADDR + 0x010))) // USB endpoint buffer mode +#define R8_UEP4_1_MOD (*((PUINT8V)(USB_BASE_ADDR + 0x010))) // endpoint 4/1 mode +#define R8_UEP2_3_MOD (*((PUINT8V)(USB_BASE_ADDR + 0x011))) // endpoint 2/3 mode +#define R8_UEP5_6_MOD (*((PUINT8V)(USB_BASE_ADDR + 0x012))) // endpoint 5/6 mode +#define R8_UEP7_MOD (*((PUINT8V)(USB_BASE_ADDR + 0x013))) // endpoint 7 mode +#define R8_UH_EP_MOD R8_UEP2_3_MOD // host endpoint mode +#define R32_UEP0_RT_DMA (*((PUINT32V)(USB_BASE_ADDR + 0x014))) // endpoint 0 DMA RX buffer address +#define R32_UEP1_RX_DMA (*((PUINT32V)(USB_BASE_ADDR + 0x018))) // endpoint 1 DMA RX buffer address +#define R32_UEP2_RX_DMA (*((PUINT32V)(USB_BASE_ADDR + 0x01c))) // endpoint 2 DMA RX buffer address +#define R32_UEP3_RX_DMA (*((PUINT32V)(USB_BASE_ADDR + 0x020))) // endpoint 3 DMA RX buffer address +#define R32_UEP4_RX_DMA (*((PUINT32V)(USB_BASE_ADDR + 0x024))) // endpoint 4 DMA RX buffer address +#define R32_UEP5_RX_DMA (*((PUINT32V)(USB_BASE_ADDR + 0x028))) // endpoint 5 DMA RX buffer address +#define R32_UEP6_RX_DMA (*((PUINT32V)(USB_BASE_ADDR + 0x02C))) // endpoint 6 DMA RX buffer address +#define R32_UEP7_RX_DMA (*((PUINT32V)(USB_BASE_ADDR + 0x030))) // endpoint 7 DMA RX buffer address +#define R32_UH_RX_DMA R32_UEP2_RX_DMA // host rx endpoint buffer high address +#define R32_UH_TX_DMA R32_UEP3_TX_DMA // host tx endpoint buffer high address +#define R32_UEP1_TX_DMA (*((PUINT32V)(USB_BASE_ADDR + 0x034))) // endpoint 1 DMA TX buffer address +#define R32_UEP2_TX_DMA (*((PUINT32V)(USB_BASE_ADDR + 0x038))) // endpoint 2 DMA TX buffer address +#define R32_UEP3_TX_DMA (*((PUINT32V)(USB_BASE_ADDR + 0x03C))) // endpoint 3 DMA TX buffer address +#define R32_UEP4_TX_DMA (*((PUINT32V)(USB_BASE_ADDR + 0x040))) // endpoint 4 DMA TX buffer address +#define R32_UEP5_TX_DMA (*((PUINT32V)(USB_BASE_ADDR + 0x044))) // endpoint 5 DMA TX buffer address +#define R32_UEP6_TX_DMA (*((PUINT32V)(USB_BASE_ADDR + 0x048))) // endpoint 6 DMA TX buffer address +#define R32_UEP7_TX_DMA (*((PUINT32V)(USB_BASE_ADDR + 0x04C))) // endpoint 7 DMA TX buffer address +#define R16_UEP0_MAX_LEN (*((PUINT16V)(USB_BASE_ADDR + 0x050))) +#define R16_UEP1_MAX_LEN (*((PUINT16V)(USB_BASE_ADDR + 0x054))) +#define R16_UEP2_MAX_LEN (*((PUINT16V)(USB_BASE_ADDR + 0x058))) +#define R16_UEP3_MAX_LEN (*((PUINT16V)(USB_BASE_ADDR + 0x05C))) +#define R16_UEP4_MAX_LEN (*((PUINT16V)(USB_BASE_ADDR + 0x060))) +#define R16_UEP5_MAX_LEN (*((PUINT16V)(USB_BASE_ADDR + 0x064))) +#define R16_UEP6_MAX_LEN (*((PUINT16V)(USB_BASE_ADDR + 0x068))) +#define R16_UEP7_MAX_LEN (*((PUINT16V)(USB_BASE_ADDR + 0x06C))) +#define R16_UH_RX_MAX_LEN R16_UEP2_MAX_LEN +#define R32_USB_EP0_CTRL (*((PUINT32V)(USB_BASE_ADDR + 0x070))) // endpoint 0 control & transmittal length +#define R16_UEP0_T_LEN (*((PUINT16V)(USB_BASE_ADDR + 0x070))) // endpoint 0 transmittal length +#define R8_UEP0_TX_CTRL (*((PUINT8V)(USB_BASE_ADDR + 0x072))) // endpoint 0 tx control +#define R8_UEP0_RX_CTRL (*((PUINT8V)(USB_BASE_ADDR + 0x073))) // endpoint 0 rx control + +#define R32_USB_EP1_CTRL (*((PUINT32V)(USB_BASE_ADDR + 0x074))) // endpoint 1 control & transmittal length +#define R16_UEP1_T_LEN (*((PUINT16V)(USB_BASE_ADDR + 0x074))) // endpoint 1 transmittal length +#define R8_UEP1_TX_CTRL (*((PUINT8V)(USB_BASE_ADDR + 0x076))) // endpoint 1 control +#define R8_UEP1_RX_CTRL (*((PUINT8V)(USB_BASE_ADDR + 0x077))) // endpoint 1 control + +//#define R8_UH_SETUP R8_UEP1_TX_CTRL // host aux setup +#define R32_USB_EP2_CTRL (*((PUINT32V)(USB_BASE_ADDR + 0x078))) // endpoint 2 control & transmittal length +#define R16_UEP2_T_LEN (*((PUINT16V)(USB_BASE_ADDR + 0x078))) // endpoint 2 transmittal length +#define R8_UEP2_TX_CTRL (*((PUINT8V)(USB_BASE_ADDR + 0x07A))) // endpoint 2 control +#define R8_UEP2_RX_CTRL (*((PUINT8V)(USB_BASE_ADDR + 0x07B))) // endpoint 2 control + +#define R16_UH_EP_PID R16_UEP2_T_LEN // host endpoint and PID +#define R8_UH_RX_CTRL R8_UEP2_RX_CTRL // host receiver endpoint control +#define R32_USB_EP3_CTRL (*((PUINT32V)(USB_BASE_ADDR + 0x07C))) // endpoint 3 control & transmittal length +#define R16_UEP3_T_LEN (*((PUINT16V)(USB_BASE_ADDR + 0x07C))) // endpoint 3 transmittal length +#define R8_UEP3_TX_CTRL (*((PUINT8V)(USB_BASE_ADDR + 0x07E))) // endpoint 3 control +#define R8_UEP3_RX_CTRL (*((PUINT8V)(USB_BASE_ADDR + 0x07F))) // endpoint 3 control + +#define R16_UH_TX_LEN R16_UEP3_T_LEN // host transmittal endpoint transmittal length +#define R8_UH_TX_CTRL R8_UEP3_TX_CTRL // host transmittal endpoint control + +#define R32_USB_EP4_CTRL (*((PUINT32V)(USB_BASE_ADDR + 0x080))) // endpoint 4 control & transmittal length +#define R16_UEP4_T_LEN (*((PUINT16V)(USB_BASE_ADDR + 0x080))) // endpoint 4 transmittal length +#define R8_UEP4_TX_CTRL (*((PUINT8V)(USB_BASE_ADDR + 0x082))) // endpoint 4 control +#define R8_UEP4_RX_CTRL (*((PUINT8V)(USB_BASE_ADDR + 0x083))) // endpoint 4 control + +#define R16_UH_SPLIT_DATA R16_UEP4_T_LEN + +#define R32_USB_EP5_CTRL (*((PUINT32V)(USB_BASE_ADDR + 0x084))) // endpoint 5 control & transmittal length +#define R16_UEP5_T_LEN (*((PUINT16V)(USB_BASE_ADDR + 0x084))) // endpoint 5 transmittal length +#define R8_UEP5_TX_CTRL (*((PUINT8V)(USB_BASE_ADDR + 0x086))) // endpoint 5 control +#define R8_UEP5_RX_CTRL (*((PUINT8V)(USB_BASE_ADDR + 0x087))) // endpoint 5 control + +#define R32_USB_EP6_CTRL (*((PUINT32V)(USB_BASE_ADDR + 0x088))) // endpoint 6 control & transmittal length +#define R16_UEP6_T_LEN (*((PUINT16V)(USB_BASE_ADDR + 0x088))) // endpoint 6 transmittal length +#define R8_UEP6_TX_CTRL (*((PUINT8V)(USB_BASE_ADDR + 0x08A))) // endpoint 6 control +#define R8_UEP6_RX_CTRL (*((PUINT8V)(USB_BASE_ADDR + 0x08B))) // endpoint 6 control + +#define R32_USB_EP7_CTRL (*((PUINT32V)(USB_BASE_ADDR + 0x08C))) // endpoint 7 control & transmittal length +#define R16_UEP7_T_LEN (*((PUINT16V)(USB_BASE_ADDR + 0x08C))) // endpoint 7 transmittal length +#define R8_UEP7_TX_CTRL (*((PUINT8V)(USB_BASE_ADDR + 0x08E))) // endpoint 7 control +#define R8_UEP7_RX_CTRL (*((PUINT8V)(USB_BASE_ADDR + 0x08F))) // endpoint 7 control + +/* USB register address offset and bit define */ + +/* USB base control registers: R8_USB_CTRL */ +#define RB_USB_HOST_MODE 0x80 // enable USB host mode: 0=device mode, 1=host mode +#define RB_USB_SPTP_MASK 0x60 // enable USB low speed: 00=full speed, 01=high speed, 10 =low speed +#define UCST_FS 0x00 +#define UCST_HS 0x20 +#define UCST_LS 0x40 +#define RB_DEV_PU_EN 0x10 // USB device enable and internal pullup resistance enable +#define RB_USB_INT_BUSY 0x08 // enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid +#define RB_USB_RESET_SIE 0x04 // force reset USB SIE, need software clear +#define RB_USB_CLR_ALL 0x02 // force clear FIFO and count of USB +#define RB_USB_DMA_EN 0x01 // DMA enable and DMA interrupt enable for USB + +/* USB interrupt enable registers: R8_USB_INT_EN */ +#define RB_USB_IE_DEV_NAK 0x80 // enable interrupt for NAK responded for USB device mode +#define RB_USB_IE_ISOACT 0x40 +#define RB_USB_IE_SETUPACT 0x20 +#define RB_USB_IE_FIFOOV 0x10 // enable interrupt for FIFO overflow +#define RB_USB_IE_SOF 0x08 // enable interrupt for host SOF timer action for USB host mode +#define RB_USB_IE_SUSPEND 0x04 // enable interrupt for USB suspend or resume event +#define RB_USB_IE_TRANS 0x02 // enable interrupt for USB transfer completion +#define RB_USB_IE_DETECT 0x01 // enable interrupt for USB device detected event for USB host mode +#define RB_USB_IE_BUSRST 0x01 // enable interrupt for USB bus reset event for USB device mode + +/* R8_USB_SUSPEND */ +//#define bUS_WAKE_UP 0x04 // wake up from suspend +#define RB_DEV_WAKEUP 0x02 //remote resume + +/* R8_USB_SPD_TYPE */ +#define RB_USBSPEED_MASK 0x03 +#define UST_FS 0x00 // USB_SPD_TYPE is full speed +#define UST_HS 0x01 // USB_SPD_TYPE is high speed +#define UST_LS 0x02 // USB_SPD_TYPE is low speed + +/* ReadOnly, USB miscellaneous status registers: R8_USB_MIS_ST */ +#define RB_USB_SOF_PRES 0x80 // ReadOnly: indicate host SOF timer presage status +#define RB_USB_SOF_ACT 0x40 // ReadOnly: indicate host SOF timer action status for USB host +#define RB_USB_SIE_FREE 0x20 // ReadOnly: indicate USB SIE free status +#define RB_USB_FIFO_RDY 0x10 // ReadOnly: indicate USB receiving FIFO ready status (not empty) +#define RB_USBBUS_RESET 0x08 // ReadOnly: indicate USB bus reset status +#define RB_USBBUS_SUSPEND 0x04 // ReadOnly: indicate USB suspend status +#define RB_USB_ATTACH 0x02 // ReadOnly: indicate device attached status on USB hub DP/DM +#define RB_USB_SPLIT_EN 0x01 // ReadOnly: indicate host allow SPLIT packet + +/* USB interrupt flag registers: R8_USB_INT_FG */ +#define RB_USB_IF_ISOACT 0x40 +#define RB_USB_IF_SETUOACT 0x20 +#define RB_USB_IF_FIFOOV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear +#define RB_USB_IF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear +#define RB_USB_IF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear +#define RB_USB_IF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear +#define RB_USB_IF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear +#define RB_USB_IF_BUSRST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear + +/* ReadOnly, USB interrupt status registers: R8_USB_INT_ST */ +#define RB_USB_ST_NAK 0x80 // ReadOnly: indicate current USB transfer is NAK received for USB device mode +#define RB_USB_ST_TOGOK 0x40 // ReadOnly: indicate current USB transfer toggle is OK +#define RB_DEV_TOKEN_MASK 0x30 // ReadOnly: bit mask of current token PID code received for USB device mode +#define RB_DEV_ENDP_MASK 0x0F // ReadOnly: bit mask of current transfer endpoint number for USB device mode +#define RB_HOST_RES_MASK 0x0F // ReadOnly: bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received + +#define UIS_TOKEN_OUT 0x00 +#define UIS_TOKEN_SOF 0x10 +#define UIS_TOKEN_IN 0x20 +#define UIS_TOKEN_SETUP 0x30 +// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode +// 00: OUT token PID received +// 01: SOF token PID received +// 10: IN token PID received +// 11: SETUP token PID received + +/* USB device endpoint 1/4 buffer mode registers: R8_UEP4_1_MOD */ +#define RB_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) +#define RB_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) +#define RB_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 +// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA +// 0 0 x: disable endpoint and disable buffer +// 1 0 0: 512 bytes buffer for receiving (OUT endpoint) +// 1 0 1: dual 512 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=1024bytes +// 0 1 0: 512 bytes buffer for transmittal (IN endpoint) +// 0 1 1: dual 512 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=1024bytes +// 1 1 0: 512 bytes buffer for receiving (OUT endpoint) + 512 bytes buffer for transmittal (IN endpoint), total=1024bytes +// 1 1 1: dual 512 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 512 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=2048bytes +#define RB_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) +#define RB_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) +#define RB_UEP4_BUF_MOD 0x01 // buffer mode of USB endpoint 4 + +/* USB device endpoint 2/3 buffer mode registers: R8_UEP2_3_MOD */ +#define RB_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) +#define RB_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) +#define RB_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 +#define RB_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) +#define RB_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) +#define RB_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 + +/* USB device endpoint 5/6 buffer mode registers: R8_UEP5_6_MOD */ +#define RB_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT) +#define RB_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN) +#define RB_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6 +#define RB_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT) +#define RB_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN) +#define RB_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5 + +/* USB device endpoint 7 buffer mode registers: R8_UEP7_MOD */ +#define RB_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT) +#define RB_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN) +#define RB_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7 + +/* R8_UEPn_TX_CTRL n=0-15 */ +#define RB_UEP_T_AUTOTOG 0x20 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define RB_UEP_T_TOG_MASK 0x18 // prepared data toggle flag of USB endpoint X transmittal (IN): 00=DATA0, 01=DATA1, 10=DATA2, 11=MDATA +#define RB_UEP_T_TOG_0 (0 << 3) +#define RB_UEP_T_TOG_1 (1 << 3) +#define RB_UEP_T_TOG_2 (2 << 3) +#define RB_UEP_T_TOG_M (3 << 3) +#define RB_UEP_TRES_NO (0x04) // expected no response, 1=enable, 0=disable, for non-zero endpoint isochronous transactions +#define RB_UEP_TRES_MASK (0x03) // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define UEP_T_RES_ACK 0x00 +#define UEP_T_RES_NAK 0x02 +#define UEP_T_RES_STALL 0x03 +// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) +// 00: ACK (ready) +// 10: NAK (busy) +// 11: STALL (error) + +/* R8_UEPn_RX_CTRL n=0-15 */ +#define RB_UEP_R_AUTOTOG 0x20 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define RB_UEP_R_TOG_MASK 0x18 // expected data toggle flag of USB endpoint X receiving (OUT): 00s=DATA0, 01=DATA1, 10=DATA2, 11=MDATA +#define RB_UEP_R_TOG_0 (0 << 3) +#define RB_UEP_R_TOG_1 (1 << 3) +#define RB_UEP_R_TOG_2 (2 << 3) +#define RB_UEP_R_TOG_M (3 << 3) +#define RB_UEP_RRES_NO (0x04) // prepared no response, 1=enable, 0=disable, for non-zero endpoint isochronous transactions +#define RB_UEP_RRES_MASK (0x03) // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define UEP_R_RES_ACK (0x00) +#define UEP_R_RES_NAK (0x02) +#define UEP_R_RES_STALL (0x03) +#define UEP_R_RES_NYET (0x01) +// bUEP_R_RES1 & bUEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) +// 00: ACK (ready) +// 10: NAK (busy) +// 11: STALL (error) +// 01: NYET + +// bUEP_T_TOG1 & bUEP_T_TOG0 / bUEP_R_TOG1 & bUEP_R_TOG0 : toggle flag +#define UEP_DATA0 (0x00 << 3) +#define UEP_DATA1 (0x01 << 3) +#define UEP_DATA2 (0x02 << 3) +#define UEP_MDATA (0x03 << 3) + +/* R8_UHOST_CTRL */ +#define RB_UH_AUTOSOF_EN 0x80 // USB host automatic SOF enable +#define RB_UH_BUS_RESUME 0x04 +#define RB_UH_BUS_SUSPEND 0x02 +#define RB_UH_BUS_RESET 0x01 + +/* USB host buffer mode registers: R8_UH_EP_MOD */ +#define RB_UH_TX_EN 0x40 // enable USB host OUT endpoint transmittal +//#define bUH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint +// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 512 bytes buffer for transmittal (OUT endpoint) +// 1 1: dual 512 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=1024bytes +#define RB_UH_RX_EN 0x08 // enable USB host IN endpoint receiving +//#define bUH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint +// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 512 bytes buffer for receiving (IN endpoint) +// 1 1: dual 512 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=1024bytes + +/* USB host PID registers: R16_UH_EP_PID */ +#define RB_UH_TOKEN_MASK 0xF0 // bit mask of token PID for USB host transfer +#define RB_UH_EPNUM_MASK 0x0F // bit mask of endpoint number for USB host transfer + +/* USB host RX control registers: R8_UH_RX_CTRL */ +#define RB_UH_RDATA_NO 0x40 // expect no data packet, for high speed hub in host mode +#define RB_UH_R_AUTOTOG 0x20 // enable automatic toggle after successful receiver completion: 0=manual toggle, 1=automatic toggle +#define RB_UH_R_TOG_MASK 0x18 // expected data toggle flag of host receiving (IN): 00=DATA0, 01=DATA1, 10=DATA2, 11=MDATA +#define RB_UH_RRES_NO 0x04 // prepared no response, 1=enable, 0=disable, for non-zero endpoint isochronous transactions +#define RB_UH_RRES_MASK 0x03 // prepared handshake response type for host receiving (IN) +// bUH_R_RES1 & bUH_R_RES0: handshake response type for host receiving (IN) +// 00: ACK (ready) +// 10: NAK (busy) +// 11: STALL (error) + +/* USB host TX control registers: R8_UH_TX_CTRL */ +#define RB_UH_TDATA_NO 0x40 // prepared no data packet, for high speed hub in host mode +#define RB_UH_T_AUTOTOG 0x20 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define RB_UH_T_TOG_MASK 0x18 // prepared data toggle flag of host transmittal (SETUP/OUT): 00=DATA0, 01=DATA1, 10=DATA2, 11=MDATA +#define RB_UH_TRES_NO 0x04 // expected no response, 1=enable, 0=disable, for non-zero endpoint isochronous transactions +#define RB_UH_TRES_MASK 0x03 // expected handshake response type for host transmittal (SETUP/OUT) +// bUH_T_RES1 & bUH_T_RES0: expected handshake response type for host transmittal (SETUP/OUT) +// 00: ACK (ready) +// 10: NAK (busy) +// 11: STALL (error) +// 01: NYET + +// toggle flag +#define UH_DATA0 (0x00 << 3) +#define UH_DATA1 (0x01 << 3) +#define UH_DATA2 (0x02 << 3) +#define UH_MDATA (0x03 << 3) + +// handshake response +#define UH_ACK 0x00 +#define UH_NAK 0x02 +#define UH_STALL 0x03 +#define UH_NYET 0x01 + +/******************************************************************************/ +/* USB 3.0 */ +/******************************************************************************/ +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif + +#define USBSS_BASE (0x40008000) + +typedef struct __PACKED +{ + UINT32V LINK_CFG; + UINT32V LINK_CTRL; + UINT32V LINK_INT_CTRL; + UINT32V LINK_INT_FLAG; + UINT32V LINK_STATUS; + UINT32V LINK_HP_BUF_CTRL; + UINT32V LINK_ERR_STATUS; + UINT32V LINK_ERR_CNT; + UINT32V USB_CONTROL; + UINT32V USB_STATUS; + UINT32V HOST_STATUS; + UINT32V USB_RX_LEN; + UINT32V USB_ITP; + UINT32V USB_ITP_ADJ; + UINT32V LINK_ISO_DLY; + UINT32V LINK_STREAM_ID; + UINT32V LINK_ROUTE_STRING; + UINT32V USB_FC_CTRL; + UINT32V LMP_TX_DATA0; + UINT32V LMP_TX_DATA1; + UINT32V LMP_TX_DATA2; + UINT32V LMP_PORT_CAP; + UINT32V LMP_RX_DATA0; + UINT32V LMP_RX_DATA1; + UINT32V LMP_RX_DATA2; + UINT32V TP_RX_DATA0; + UINT32V TP_RX_DATA1; + UINT32V TP_RX_DATA2; + UINT32V UEP_CFG; + UINT32V UEP0_DMA; + UINT32V UEP0_RX_CTRL; + UINT32V UEP0_TX_CTRL; + UINT32V UEP1_TX_DMA; + UINT32V UEP1_RX_DMA; + UINT32V UEP1_RX_CTRL; + UINT32V UEP1_TX_CTRL; + UINT32V UEP2_RX_DMA; + UINT32V UEP2_TX_DMA; + UINT32V UEP2_RX_CTRL; + UINT32V UEP2_TX_CTRL; + UINT32V UEP3_TX_DMA; + UINT32V UEP3_RX_DMA; + UINT32V UEP3_RX_CTRL; + UINT32V UEP3_TX_CTRL; + UINT32V UEP4_TX_DMA; + UINT32V UEP4_RX_DMA; + UINT32V UEP4_RX_CTRL; + UINT32V UEP4_TX_CTRL; + UINT32V UEP5_TX_DMA; + UINT32V UEP5_RX_DMA; + UINT32V UEP5_RX_CTRL; + UINT32V UEP5_TX_CTRL; + UINT32V UEP6_TX_DMA; + UINT32V UEP6_RX_DMA; + UINT32V UEP6_RX_CTRL; + UINT32V UEP6_TX_CTRL; + UINT32V UEP7_TX_DMA; + UINT32V UEP7_RX_DMA; + UINT32V UEP7_RX_CTRL; + UINT32V UEP7_TX_CTRL; + UINT32V UX_EXIT_TIMER; + +} USBSS_TypeDef; + +typedef struct __PACKED +{ + UINT32V LINK_CFG; + UINT32V LINK_CTRL; + UINT32V LINK_INT_CTRL; + UINT32V LINK_INT_FLAG; + UINT32V LINK_STATUS; + UINT32V LINK_HP_BUF_CTRL; + UINT32V LINK_ERR_STATUS; + UINT32V LINK_ERR_CNT; + UINT32V USB_CONTROL; + UINT32V USB_STATUS; + UINT32V HOST_STATUS; + UINT32V USB_RX_LEN; + UINT32V USB_ITP; + UINT32V USB_ITP_ADJ; + UINT32V LINK_ISO_DLY; + UINT32V LINK_STREAM_ID; + UINT32V LINK_ROUTE_STRING; + UINT32V USB_FC_CTRL; + UINT32V LMP_TX_DATA0; + UINT32V LMP_TX_DATA1; + UINT32V LMP_TX_DATA2; + UINT32V LMP_PORT_CAP; + UINT32V LMP_RX_DATA0; + UINT32V LMP_RX_DATA1; + UINT32V LMP_RX_DATA2; + UINT32V TP_RX_DATA0; + UINT32V TP_RX_DATA1; + UINT32V TP_RX_DATA2; + UINT32V UEP_CFG; + UINT32V reserved0; + UINT32V reserved1; + UINT32V reserved2; + UINT32V UH_TX_DMA; + UINT32V UH_RX_DMA; + UINT32V UH_RX_CTRL; + UINT32V UH_TX_CTRL; +} USBSSH_TypeDef; + +#define USBSS ((USBSS_TypeDef *)USBSS_BASE) +#define USBSSH ((USBSSH_TypeDef *)USBSS_BASE) + +#ifdef __cplusplus +} +#endif + +#endif // __CH56xUSBSFR_H__ + +#ifndef __USB_TYPE__ +#define __USB_TYPE__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Connection device speed definition */ +#define USB_DEV_SPEED_LS 0x01 /* Currently a low-speed device */ +#define USB_DEV_SPEED_FS 0x00 /* Currently full speed device */ +#define USB_DEV_SPEED_HS 0x02 + +/* USB PID */ +#ifndef USB_PID_SETUP + #define USB_PID_NULL 0x00 /* reserved PID */ + #define USB_PID_PING 0x04 + #define USB_PID_SOF 0x05 + #define USB_PID_SETUP 0x0D + #define USB_PID_IN 0x09 + #define USB_PID_OUT 0x01 + #define USB_PID_ACK 0x02 + #define USB_PID_NAK 0x0A + #define USB_PID_STALL 0x0E + #define USB_PID_NYET 0x06 + #define USB_PID_DATA0 0x03 + #define USB_PID_DATA1 0x0B + #define USB_PID_PRE 0x0C + #define USB_PID_ERR 0x0C + #define USB_PID_SPLIT 0x08 + #define USB_PID_DATA0 0x03 + #define USB_PID_DATA1 0x0B + #define USB_PID_DATA2 0x07 + #define USB_PID_MDATA 0x0F +#endif + +/* USB standard device request code */ +#ifndef USB_GET_DESCRIPTOR + #define USB_GET_STATUS 0x00 + #define USB_CLEAR_FEATURE 0x01 + #define USB_SET_FEATURE 0x03 + #define USB_SET_ADDRESS 0x05 + #define USB_GET_DESCRIPTOR 0x06 + #define USB_SET_DESCRIPTOR 0x07 + #define USB_GET_CONFIGURATION 0x08 + #define USB_SET_CONFIGURATION 0x09 + #define USB_GET_INTERFACE 0x0A + #define USB_SET_INTERFACE 0x0B + #define USB_SYNCH_FRAME 0x0C +#endif + +/* USB hub class request code */ +#ifndef HUB_GET_DESCRIPTOR + #define HUB_GET_STATUS 0x00 + #define HUB_CLEAR_FEATURE 0x01 + #define HUB_GET_STATE 0x02 + #define HUB_SET_FEATURE 0x03 + #define HUB_GET_DESCRIPTOR 0x06 + #define HUB_SET_DESCRIPTOR 0x07 +#endif + +/* USB HID class request code */ +#ifndef HID_GET_REPORT + #define HID_GET_REPORT 0x01 + #define HID_GET_IDLE 0x02 + #define HID_GET_PROTOCOL 0x03 + #define HID_SET_REPORT 0x09 + #define HID_SET_IDLE 0x0A + #define HID_SET_PROTOCOL 0x0B +#endif + +/* Bit define for USB request type */ +#ifndef USB_REQ_TYP_MASK + #define USB_REQ_TYP_IN 0x80 /* control IN, device to host */ + #define USB_REQ_TYP_OUT 0x00 /* control OUT, host to device */ + #define USB_REQ_TYP_READ 0x80 /* control read, device to host */ + #define USB_REQ_TYP_WRITE 0x00 /* control write, host to device */ + #define USB_REQ_TYP_MASK 0x60 /* bit mask of request type */ + #define USB_REQ_TYP_STANDARD 0x00 + #define USB_REQ_TYP_CLASS 0x20 + #define USB_REQ_TYP_VENDOR 0x40 + #define USB_REQ_TYP_RESERVED 0x60 + #define USB_REQ_RECIP_MASK 0x1F /* bit mask of request recipient */ + #define USB_REQ_RECIP_DEVICE 0x00 + #define USB_REQ_RECIP_INTERF 0x01 + #define USB_REQ_RECIP_ENDP 0x02 + #define USB_REQ_RECIP_OTHER 0x03 +#endif + +/* USB request type for hub class request */ +#ifndef HUB_GET_HUB_DESCRIPTOR + #define HUB_CLEAR_HUB_FEATURE 0x20 + #define HUB_CLEAR_PORT_FEATURE 0x23 + #define HUB_GET_BUS_STATE 0xA3 + #define HUB_GET_HUB_DESCRIPTOR 0xA0 + #define HUB_GET_HUB_STATUS 0xA0 + #define HUB_GET_PORT_STATUS 0xA3 + #define HUB_SET_HUB_DESCRIPTOR 0x20 + #define HUB_SET_HUB_FEATURE 0x20 + #define HUB_SET_PORT_FEATURE 0x23 +#endif + +/* Hub class feature selectors */ +#ifndef HUB_PORT_RESET + #define HUB_C_HUB_LOCAL_POWER 0 + #define HUB_C_HUB_OVER_CURRENT 1 + #define HUB_PORT_CONNECTION 0 + #define HUB_PORT_ENABLE 1 + #define HUB_PORT_SUSPEND 2 + #define HUB_PORT_OVER_CURRENT 3 + #define HUB_PORT_RESET 4 + #define HUB_PORT_POWER 8 + #define HUB_PORT_LOW_SPEED 9 + #define HUB_C_PORT_CONNECTION 16 + #define HUB_C_PORT_ENABLE 17 + #define HUB_C_PORT_SUSPEND 18 + #define HUB_C_PORT_OVER_CURRENT 19 + #define HUB_C_PORT_RESET 20 +#endif + +/* USB descriptor type */ +#ifndef USB_DESCR_TYP_DEVICE + #define USB_DESCR_TYP_DEVICE 0x01 + #define USB_DESCR_TYP_CONFIG 0x02 + #define USB_DESCR_TYP_STRING 0x03 + #define USB_DESCR_TYP_INTERF 0x04 + #define USB_DESCR_TYP_ENDP 0x05 + #define USB_DESCR_TYP_QUALIF 0x06 + #define USB_DESCR_TYP_SPEED 0x07 + #define USB_DESCR_TYP_OTG 0x09 + #define USB_DESCR_TYP_HID 0x21 + #define USB_DESCR_TYP_REPORT 0x22 + #define USB_DESCR_TYP_PHYSIC 0x23 + #define USB_DESCR_TYP_CS_INTF 0x24 + #define USB_DESCR_TYP_CS_ENDP 0x25 + #define USB_DESCR_TYP_HUB 0x29 +#endif + +/* USB device class */ +#ifndef USB_DEV_CLASS_HUB + #define USB_DEV_CLASS_RESERVED 0x00 + #define USB_DEV_CLASS_AUDIO 0x01 + #define USB_DEV_CLASS_COMMUNIC 0x02 + #define USB_DEV_CLASS_HID 0x03 + #define USB_DEV_CLASS_MONITOR 0x04 + #define USB_DEV_CLASS_PHYSIC_IF 0x05 + #define USB_DEV_CLASS_POWER 0x06 + #define USB_DEV_CLASS_PRINTER 0x07 + #define USB_DEV_CLASS_STORAGE 0x08 + #define USB_DEV_CLASS_HUB 0x09 + #define USB_DEV_CLASS_VEN_SPEC 0xFF +#endif + +/* USB endpoint type and attributes */ +#ifndef USB_ENDP_TYPE_MASK + #define USB_ENDP_DIR_MASK 0x80 + #define USB_ENDP_ADDR_MASK 0x0F + #define USB_ENDP_TYPE_MASK 0x03 + #define USB_ENDP_TYPE_CTRL 0x00 + #define USB_ENDP_TYPE_ISOCH 0x01 + #define USB_ENDP_TYPE_BULK 0x02 + #define USB_ENDP_TYPE_INTER 0x03 +#endif + +#ifndef USB_DEVICE_ADDR + #define USB_DEVICE_ADDR 0x02 /* Default USB device address */ +#endif +#ifndef DEFAULT_ENDP0_SIZE + #define DEFAULT_ENDP0_SIZE 8 /* default maximum packet size for endpoint 0 */ +#endif +#ifndef MAX_PACKET_SIZE + #define MAX_PACKET_SIZE 512 /* maximum packet size */ +#endif +#ifndef USB_BO_CBW_SIZE + #define USB_BO_CBW_SIZE 0x1F /* Total length of command block CBW */ + #define USB_BO_CSW_SIZE 0x0D /* The total length of the command status block CSW */ +#endif +#ifndef USB_BO_CBW_SIG0 + #define USB_BO_CBW_SIG0 0x55 /* Command block CBW identification flag 'USBC' */ + #define USB_BO_CBW_SIG1 0x53 + #define USB_BO_CBW_SIG2 0x42 + #define USB_BO_CBW_SIG3 0x43 + #define USB_BO_CSW_SIG0 0x55 /* Command status block CSW identification flag 'USBS' */ + #define USB_BO_CSW_SIG1 0x53 + #define USB_BO_CSW_SIG2 0x42 + #define USB_BO_CSW_SIG3 0x53 +#endif + +#ifndef USB_SETUP_REQ +typedef struct __PACKED _USB_SETUP_REQ +{ + UINT8 bRequestType; + UINT8 bRequest; + UINT16 wValue; + UINT16 wIndex; + UINT16 wLength; +} USB_SETUP_REQ, *PUSB_SETUP_REQ; +#endif + +#ifndef USB_DEV_DESCR +typedef struct __PACKED _USB_DEVICE_DESCR +{ + UINT8 bLength; + UINT8 bDescriptorType; + UINT16 bcdUSB; + UINT8 bDeviceClass; + UINT8 bDeviceSubClass; + UINT8 bDeviceProtocol; + UINT8 bMaxPacketSize0; + UINT16 idVendor; + UINT16 idProduct; + UINT16 bcdDevice; + UINT8 iManufacturer; + UINT8 iProduct; + UINT8 iSerialNumber; + UINT8 bNumConfigurations; +} USB_DEV_DESCR, *PUSB_DEV_DESCR; +#endif + +#ifndef USB_CFG_DESCR +typedef struct __PACKED _USB_CONFIG_DESCR +{ + UINT8 bLength; + UINT8 bDescriptorType; + UINT16 wTotalLength; + UINT8 bNumInterfaces; + UINT8 bConfigurationValue; + UINT8 iConfiguration; + UINT8 bmAttributes; + UINT8 MaxPower; +} USB_CFG_DESCR, *PUSB_CFG_DESCR; +#endif + +#ifndef USB_ITF_DESCR +typedef struct __PACKED _USB_INTERF_DESCR +{ + UINT8 bLength; + UINT8 bDescriptorType; + UINT8 bInterfaceNumber; + UINT8 bAlternateSetting; + UINT8 bNumEndpoints; + UINT8 bInterfaceClass; + UINT8 bInterfaceSubClass; + UINT8 bInterfaceProtocol; + UINT8 iInterface; +} USB_ITF_DESCR, *PUSB_ITF_DESCR; +#endif + +#ifndef USB_ENDP_DESCR +typedef struct __PACKED _USB_ENDPOINT_DESCR +{ + UINT8 bLength; + UINT8 bDescriptorType; + UINT8 bEndpointAddress; + UINT8 bmAttributes; + UINT8 wMaxPacketSizeL; + UINT8 wMaxPacketSizeH; + UINT8 bInterval; +} USB_ENDP_DESCR, *PUSB_ENDP_DESCR; +#endif + +#ifndef USB_CFG_DESCR_LONG +typedef struct __PACKED _USB_CONFIG_DESCR_LONG +{ + USB_CFG_DESCR cfg_descr; + USB_ITF_DESCR itf_descr; + USB_ENDP_DESCR endp_descr[2]; +} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG; +#endif + +#ifndef USB_HUB_DESCR +typedef struct __PACKED _USB_HUB_DESCR +{ + UINT8 bDescLength; + UINT8 bDescriptorType; + UINT8 bNbrPorts; + UINT8 wHubCharacteristicsL; + UINT8 wHubCharacteristicsH; + UINT8 bPwrOn2PwrGood; + UINT8 bHubContrCurrent; + UINT8 DeviceRemovable; + UINT8 PortPwrCtrlMask; +} USB_HUB_DESCR, *PUSB_HUB_DESCR; +#endif + +#ifndef USB_HID_DESCR +typedef struct __PACKED _USB_HID_DESCR +{ + UINT8 bLength; + UINT8 bDescriptorType; + UINT8 bcdHIDL; + UINT8 bcdHIDH; + UINT8 bCountryCode; + UINT8 bNumDescriptors; + UINT8 bDescriptorTypeX; + UINT8 wDescriptorLengthL; + UINT8 wDescriptorLengthH; +} USB_HID_DESCR, *PUSB_HID_DESCR; +#endif + +#ifndef USB_DEV_QUAL_DESCR +typedef struct __PACKED _USB_DEVICE_QUALIFIER_DESCRIPTOR +{ + UINT8 bLength; + UINT8 bDescriptorType; + UINT8 bcdUSBL; + UINT8 bcdUSBH; + UINT8 bDeviceClass; + UINT8 bDeviceSubClass; + UINT8 bDeviceProtocol; + UINT8 bMaxPacketSize0; + UINT8 bNumConfigurations; + UINT8 bReserved; +} USB_DEV_QUAL_DESCR, *PUSB_DEV_QUAL_DESCR; +#endif + +#ifndef USB_CFG_PWR_DESCR +typedef struct __PACKED _USB_CONFIGURATION_POWER_DESCRIPTOR +{ + UINT8 bLength; + UINT8 bDescriptorType; + UINT8 SelfPowerConsumedD0[3]; + UINT8 bPowerSummaryId; + UINT8 bBusPowerSavingD1; + UINT8 bSelfPowerSavingD1; + UINT8 bBusPowerSavingD2; + UINT8 bSelfPowerSavingD2; + UINT8 bBusPowerSavingD3; + UINT8 bSelfPowerSavingD3; + UINT8 TransitionTimeFromD1L; + UINT8 TransitionTimeFromD1H; + UINT8 TransitionTimeFromD2L; + UINT8 TransitionTimeFromD2H; + UINT8 TransitionTimeFromD3L; + UINT8 TransitionTimeFromD3H; +} USB_CFG_PWR_DESCR, *PUSB_CFG_PWR_DESCR; +#endif + +#ifndef USB_ITF_PWR_DESCR +typedef struct __PACKED _USB_INTERFACE_POWER_DESCRIPTOR +{ + UINT8 bLength; + UINT8 bDescriptorType; + UINT8 bmCapabilitiesFlags; + UINT8 bBusPowerSavingD1; + UINT8 bSelfPowerSavingD1; + UINT8 bBusPowerSavingD2; + UINT8 bSelfPowerSavingD2; + UINT8 bBusPowerSavingD3; + UINT8 bSelfPowerSavingD3; + UINT8 TransitionTimeFromD1L; + UINT8 TransitionTimeFromD1H; + UINT8 TransitionTimeFromD2L; + UINT8 TransitionTimeFromD2H; + UINT8 TransitionTimeFromD3L; + UINT8 TransitionTimeFromD3H; +} USB_ITF_PWR_DESCR, *PUSB_ITF_PWR_DESCR; +#endif + +#define USB_BO_CBW_SIG 0x43425355 /* Command block CBW identification flag 'USBC' */ +#define USB_BO_CSW_SIG 0x53425355 /* Command status block CSW identification flag 'USBS' */ + +typedef struct __PACKED _UDISK_BOC_CBW +{ + UINT32 mCBW_Sig; + UINT32 mCBW_Tag; + UINT32 mCBW_DataLen; /* Input: data transfer length */ + UINT8 mCBW_Flag; /* Input: flags such as transmission direction */ + UINT8 mCBW_LUN; + UINT8 mCBW_CB_Len; /* Input: the length of the command block, valid values are 1 to 16 */ + UINT8 mCBW_CB_Buf[16]; /* Input: command block, the buffer is up to 16 bytes */ +} UDISK_BOC_CBW, *PUDISK_BOC_CBW; + +typedef struct __PACKED _UDISK_BOC_CSW +{ + UINT32 mCSW_Sig; + UINT32 mCSW_Tag; + UINT32 mCSW_Residue; /* Return: remaining data length */ + UINT8 mCSW_Status; /* Return: command execution result status */ +} UDISK_BOC_CSW, *PUDISK_BOC_CSW; + +#ifdef __cplusplus +} +#endif + +#endif // __USB_TYPE__ + +#ifndef __CH56xSDSSFR_H__ +#define __CH56xSDSSFR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define SERDES_BASE (0x4000B000) + +typedef struct +{ + UINT32V SDS_CTRL; + UINT32V SDS_INT_EN; + UINT32V SDS_STATUS; + UINT32V SDS_RTX_CTRL; + UINT32V SDS_RX_LEN0; + UINT32V SDS_DATA0; + UINT32V SDS_DMA0; + UINT32V SDS_RX_LEN1; + UINT32V SDS_DATA1; + UINT32V SDS_DMA1; +} SDS_TypeDef; + +#define SDS ((SDS_TypeDef *)SERDES_BASE) + +#ifdef __cplusplus +} +#endif + +#endif // __CH56xSDSSFR_H__ + +#ifndef __CH56xETHSFR_H__ +#define __CH56xETHSFR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define ETH_BASE (0x4000C000) + +/** + * @brief ETH MAC Init structure definition + * @note The user should not configure all the ETH_InitTypeDef structure's fields. + * By calling the ETH_StructInit function the structure fields are set to their default values. + * Only the parameters that will be set to a non-default value should be configured. + */ + +#define PHY_10M_EN 0 +#define ETHMAC_Mode 0x00 //01: 100M 00: 10M 10:1000M +#define TB_NUM 0x08 + +#define DMA_TPS_Mask ((UINT32)0x00700000) +#define DMA_RPS_Mask ((UINT32)0x000E0000) + +typedef struct +{ + /** + * @brief / * MAC + */ + UINT32 ETH_AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY + The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) + and the mode (half/full-duplex). + This parameter can be a value of @ref ETH_AutoNegotiation */ + + UINT32 ETH_Watchdog; /*!< Selects or not the Watchdog timer + When enabled, the MAC allows no more then 2048 bytes to be received. + When disabled, the MAC can receive up to 16384 bytes. + This parameter can be a value of @ref ETH_watchdog */ + + UINT32 ETH_Jabber; /*!< Selects or not Jabber timer + When enabled, the MAC allows no more then 2048 bytes to be sent. + When disabled, the MAC can send up to 16384 bytes. + This parameter can be a value of @ref ETH_Jabber */ + + UINT32 ETH_InterFrameGap; /*!< Selects the minimum IFG between frames during transmission + This parameter can be a value of @ref ETH_Inter_Frame_Gap */ + + UINT32 ETH_CarrierSense; /*!< Selects or not the Carrier Sense + This parameter can be a value of @ref ETH_Carrier_Sense */ + + UINT32 ETH_Speed; /*!< Sets the Ethernet speed: 10/100 Mbps + This parameter can be a value of @ref ETH_Speed */ + + UINT32 ETH_ReceiveOwn; /*!< Selects or not the ReceiveOwn + ReceiveOwn allows the reception of frames when the TX_EN signal is asserted + in Half-Duplex mode + This parameter can be a value of @ref ETH_Receive_Own */ + + UINT32 ETH_LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode + This parameter can be a value of @ref ETH_Loop_Back_Mode */ + + UINT32 ETH_Mode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode + This parameter can be a value of @ref ETH_Duplex_Mode */ + + UINT32 ETH_ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. + This parameter can be a value of @ref ETH_Checksum_Offload */ + + UINT32 ETH_RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, + when a colision occurs (Half-Duplex mode) + This parameter can be a value of @ref ETH_Retry_Transmission */ + + UINT32 ETH_AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping + This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ + + UINT32 ETH_BackOffLimit; /*!< Selects the BackOff limit value + This parameter can be a value of @ref ETH_Back_Off_Limit */ + + UINT32 ETH_DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode) + This parameter can be a value of @ref ETH_Deferral_Check */ + + UINT32 ETH_ReceiveAll; /*!< Selects or not all frames reception by the MAC (No fitering) + This parameter can be a value of @ref ETH_Receive_All */ + + UINT32 ETH_SourceAddrFilter; /*!< Selects the Source Address Filter mode + This parameter can be a value of @ref ETH_Source_Addr_Filter */ + + UINT32 ETH_PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) + This parameter can be a value of @ref ETH_Pass_Control_Frames */ + + UINT32 ETH_BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames + This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ + + UINT32 ETH_DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames + This parameter can be a value of @ref ETH_Destination_Addr_Filter */ + + UINT32 ETH_PromiscuousMode; /*!< Selects or not the Promiscuous Mode + This parameter can be a value of @ref ETH_Promiscuous_Mode */ + + UINT32 ETH_MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter + This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ + + UINT32 ETH_UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter + This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ + + UINT32 ETH_HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. */ + + UINT32 ETH_HashTableLow; /*!< This field holds the lower 32 bits of Hash table. */ + + UINT32 ETH_PauseTime; /*!< This field holds the value to be used in the Pause Time field in the + transmit control frame */ + + UINT32 ETH_ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames + This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ + + UINT32 ETH_PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for + automatic retransmission of PAUSE Frame + This parameter can be a value of @ref ETH_Pause_Low_Threshold */ + + UINT32 ETH_UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 + unicast address and unique multicast address) + This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ + + UINT32 ETH_ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and + disable its transmitter for a specified time (Pause Time) + This parameter can be a value of @ref ETH_Receive_Flow_Control */ + + UINT32 ETH_TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) + or the MAC back-pressure operation (Half-Duplex mode) + This parameter can be a value of @ref ETH_Transmit_Flow_Control */ + + UINT32 ETH_VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for + comparison and filtering + This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ + + UINT32 ETH_VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */ + + /** + * @brief / * DMA + */ + + UINT32 ETH_DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames + This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ + + UINT32 ETH_ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode + This parameter can be a value of @ref ETH_Receive_Store_Forward */ + + UINT32 ETH_FlushReceivedFrame; /*!< Enables or disables the flushing of received frames + This parameter can be a value of @ref ETH_Flush_Received_Frame */ + + UINT32 ETH_TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode + This parameter can be a value of @ref ETH_Transmit_Store_Forward */ + + UINT32 ETH_TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control + This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ + + UINT32 ETH_ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames + This parameter can be a value of @ref ETH_Forward_Error_Frames */ + + UINT32 ETH_ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error + and length less than 64 bytes) including pad-bytes and CRC) + This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ + + UINT32 ETH_ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO + This parameter can be a value of @ref ETH_Receive_Threshold_Control */ + + UINT32 ETH_SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second + frame of Transmit data even before obtaining the status for the first frame. + This parameter can be a value of @ref ETH_Second_Frame_Operate */ + + UINT32 ETH_AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats + This parameter can be a value of @ref ETH_Address_Aligned_Beats */ + + UINT32 ETH_FixedBurst; /*!< Enables or disables the HB Master interface fixed burst transfers + This parameter can be a value of @ref ETH_Fixed_Burst */ + + UINT32 ETH_RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction + This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ + + UINT32 ETH_TxDMABurstLength; /*!< Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction + This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ + + UINT32 ETH_DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) */ + + UINT32 ETH_DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration + This parameter can be a value of @ref ETH_DMA_Arbitration */ +} ETH_InitTypeDef; + +/**--------------------------------------------------------------------------**/ +/** + * @brief DMA descriptors types + */ +/**--------------------------------------------------------------------------**/ + +/** + * @brief ETH DMA Desciptors data structure definition + */ +typedef struct +{ + UINT32 Status; /*!< Status */ + UINT32 ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ + UINT32 Buffer1Addr; /*!< Buffer1 address pointer */ + UINT32 Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ +} ETH_DMADESCTypeDef; + +/** + * @} + */ + +/** @defgroup ETH_Exported_Constants + * @{ + */ + +/** + * @brief Uncomment the line below if you want to use user defined Delay function + * (for precise timing), otherwise default _eth_delay_ function defined within + * this driver is used (less precise timing). + */ +/* #define USE_Delay */ + +#ifdef USE_Delay + #include "main.h" + #define _eth_delay_ Delay /*!< User can provide more timing precise _eth_delay_ function */ +#else + #define _eth_delay_ ETH_Delay /*!< Default _eth_delay_ function with less precise timing */ +#endif + +/**--------------------------------------------------------------------------**/ +/** + * @brief ETH Frames defines + */ +/**--------------------------------------------------------------------------**/ + +/** @defgroup ENET_Buffers_setting + * @{ + */ +#define ETH_MAX_PACKET_SIZE 1536 /*!< ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */ +#define ETH_HEADER 14 /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC 4 /*!< Ethernet CRC */ +#define ETH_EXTRA 2 /*!< Extra bytes in some cases */ +#define VLAN_TAG 4 /*!< optional 802.1q VLAN Tag */ +#define MIN_ETH_PAYLOAD 46 /*!< Minimum Ethernet payload size */ +#define MAX_ETH_PAYLOAD 1500 /*!< Maximum Ethernet payload size */ +#define JUMBO_FRAME_PAYLOAD 9000 /*!< Jumbo frame payload size */ + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet DMA descriptors registers bits definition + */ +/**--------------------------------------------------------------------------**/ + +/** +@code + DMA Tx Desciptor + ----------------------------------------------------------------------------------------------- + TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | + ----------------------------------------------------------------------------------------------- + TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | + ----------------------------------------------------------------------------------------------- + TDES2 | Buffer1 Address [31:0] | + ----------------------------------------------------------------------------------------------- + TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + ----------------------------------------------------------------------------------------------- +@endcode +*/ + +/** + * @brief Bit definition of TDES0 register: DMA Tx descriptor status register + */ +#define ETH_DMATxDesc_OWN ((UINT32)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMATxDesc_IC ((UINT32)0x40000000) /*!< Interrupt on Completion */ +#define ETH_DMATxDesc_LS ((UINT32)0x20000000) /*!< Last Segment */ +#define ETH_DMATxDesc_FS ((UINT32)0x10000000) /*!< First Segment */ +#define ETH_DMATxDesc_DC ((UINT32)0x08000000) /*!< Disable CRC */ +#define ETH_DMATxDesc_DP ((UINT32)0x04000000) /*!< Disable Padding */ +#define ETH_DMATxDesc_TTSE ((UINT32)0x02000000) /*!< Transmit Time Stamp Enable */ +#define ETH_DMATxDesc_CIC ((UINT32)0x00C00000) /*!< Checksum Insertion Control: 4 cases */ +#define ETH_DMATxDesc_CIC_ByPass ((UINT32)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */ +#define ETH_DMATxDesc_CIC_IPV4Header ((UINT32)0x00400000) /*!< IPV4 header Checksum Insertion */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((UINT32)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((UINT32)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ +#define ETH_DMATxDesc_TER ((UINT32)0x00200000) /*!< Transmit End of Ring */ +#define ETH_DMATxDesc_TCH ((UINT32)0x00100000) /*!< Second Address Chained */ +#define ETH_DMATxDesc_TTSS ((UINT32)0x00020000) /*!< Tx Time Stamp Status */ +#define ETH_DMATxDesc_IHE ((UINT32)0x00010000) /*!< IP Header Error */ +#define ETH_DMATxDesc_ES ((UINT32)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ +#define ETH_DMATxDesc_JT ((UINT32)0x00004000) /*!< Jabber Timeout */ +#define ETH_DMATxDesc_FF ((UINT32)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due */ + +#ifdef __cplusplus +} +#endif + +#endif // __CH56xETHSFR_H__ diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_bus8.h b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_bus8.h new file mode 100644 index 000000000..3a5935d5c --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_bus8.h @@ -0,0 +1,48 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : CH56x_bus8.h +* Author : WCH +* Version : V1.0 +* Date : 2020/07/31 +* Description : +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + + +#ifndef __CH56x_BUS8_H__ +#define __CH56x_BUS8_H__ + +#ifdef __cplusplus + extern "C" { +#endif + + +#define ADDR_NONE 0x00 +#define ADDR_6 0x04 +#define ADDR_10 0x08 +#define ADDR_15 0x0c + +#define WIDTH_3 0x00 +#define WIDTH_5 0x10 +#define WIDTH_9 0x20 +#define WIDTH_16 0x30 + +#define HOLD_2 0x00 +#define HOLD_3 0x40 + +#define SETUP_2 0x00 +#define SETUP_3 0x80 + + +void BUS8_Init(UINT8 addroe, UINT8 width, UINT8 hold, UINT8 setup); + + + +#ifdef __cplusplus +} +#endif + +#endif // __CH56x_BUS8_H__ + diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_clk.h b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_clk.h new file mode 100644 index 000000000..994cce8e0 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_clk.h @@ -0,0 +1,44 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : CH56x_clk.h +* Author : WCH +* Version : V1.0 +* Date : 2020/07/31 +* Description : +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + + +#ifndef __CH56x_CLK_H__ +#define __CH56x_CLK_H__ + +#ifdef __cplusplus + extern "C" { +#endif + + +enum +{ + CLK_SOURCE_PLL_15MHz = 15, //Power-on default + CLK_SOURCE_PLL_30MHz = 30, + CLK_SOURCE_PLL_60MHz = 60, + CLK_SOURCE_PLL_80MHz = 80, + CLK_SOURCE_PLL_96MHz = 96, + CLK_SOURCE_PLL_120MHz = 120, + +}; + + +void SystemInit(uint32_t systemclck); /* System clock initialization */ +UINT32 GetSysClock( void ); /* Get the current system clock */ + + + +#ifdef __cplusplus +} +#endif + +#endif // __CH56x_CLK_H__ + diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_common.h b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_common.h new file mode 100644 index 000000000..bbfc447cf --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_common.h @@ -0,0 +1,62 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : CH56x_COMM.h +* Author : WCH +* Version : V1.0 +* Date : 2020/07/31 +* Description : +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + + +#ifndef __CH56x_COMM_H__ +#define __CH56x_COMM_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "stdio.h" +#include "string.h" +#include "core_riscv.h" +#include "CH56x_sys.h" +#include "CH56x_clk.h" +#include "CH56x_uart.h" +#include "CH56x_gpio.h" +#include "CH56x_pwm.h" +#include "CH56x_timer.h" +#include "CH56x_spi.h" +#include "CH56x_hspi.h" +#include "CH56x_dvp.h" +#include "CH56x_bus8.h" +#include "CH56x_ecdc.h" +#include "CH56x_pwr.h" +#include "CH56x_emmc.h" +#include "CH56x_eth.h" + + +/* UART Printf Definition */ +#define Debug_UART0 0 +#define Debug_UART1 1 +#define Debug_UART2 2 +#define Debug_UART3 3 + +/* SystemCoreClock */ +#ifndef FREQ_SYS +#define FREQ_SYS 80000000 +#endif + + +#define DelayMs(x) mDelaymS(x) +#define DelayUs(x) mDelayuS(x) + + + +#ifdef __cplusplus +} +#endif + +#endif // __CH56x_COMM_H__ + diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_dvp.h b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_dvp.h new file mode 100644 index 000000000..475252489 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_dvp.h @@ -0,0 +1,72 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : CH56x_dvp.c +* Author : WCH +* Version : V1.0 +* Date : 2020/07/31 +* Description : +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + + +#ifndef __CH56x_DVP_H__ +#define __CH56x_DVP_H__ + +#ifdef __cplusplus + extern "C" { +#endif + + +/** + * @brief DVP Data Mode + */ +typedef enum +{ + Video_Mode = 0, + JPEG_Mode, +}DVP_Data_ModeTypeDef; + + +/** + * @brief DVP DMA + */ +typedef enum +{ + DVP_DMA_Disable = 0, + DVP_DMA_Enable, +}DVP_DMATypeDef; + +/** + * @brief DVP FLAG and FIFO Reset + */ +typedef enum +{ + DVP_FLAG_FIFO_RESET_Disable = 0, + DVP_FLAG_FIFO_RESET_Enable, +}DVP_FLAG_FIFO_RESETTypeDef; + +/** + * @brief DVP RX Reset + */ +typedef enum +{ + DVP_RX_RESET_Disable = 0, + DVP_RX_RESET_Enable, +}DVP_RX_RESETTypeDef; + + + +void DVP_INTCfg( UINT8 s, UINT8 i ); +void DVP_Mode( UINT8 s, DVP_Data_ModeTypeDef i); +void DVP_Cfg( DVP_DMATypeDef s, DVP_FLAG_FIFO_RESETTypeDef i, DVP_RX_RESETTypeDef j); + + + +#ifdef __cplusplus +} +#endif + +#endif // __CH56x_DVP_H__ + diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_ecdc.h b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_ecdc.h new file mode 100644 index 000000000..ffe44c0ee --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_ecdc.h @@ -0,0 +1,67 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : CH56x_ecdc.h +* Author : WCH +* Version : V1.0 +* Date : 2020/07/31 +* Description : +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + + +#ifndef __CH56x_ECDC_H__ +#define __CH56x_ECDC_H__ + +#ifdef __cplusplus + extern "C" { +#endif + + +/* Encryption and decryption mode */ +#define MODE_SM4_ECB 0 +#define MODE_AES_ECB 1 +#define MODE_SM4_CTR 2 +#define MODE_AES_CTR 3 + +/* endian mode */ +#define MODE_BIG_ENDIAN 1 +#define MODE_LITTLE_ENDIAN 0 + +/* key length */ +#define KEYLENGTH_128BIT 0 +#define KEYLENGTH_192BIT 1 +#define KEYLENGTH_256BIT 2 + +/* Encryption and decryption speed */ +#define ECDCCLK_DISABLE 1 +#define ECDCCLK_240MHZ 2 +#define ECDCCLK_160MHZ 3 + +/* direction and mode */ +#define SELFDMA_ENCRY 0x84 +#define SELFDMA_DECRY 0x8c +#define SINGLEREGISTER_ENCRY PERIPHERAL_TO_RAM_ENCRY +#define SINGLEREGISTER_DECRY PERIPHERAL_TO_RAM_DECRY +#define PERIPHERAL_TO_RAM_ENCRY 0x02 +#define PERIPHERAL_TO_RAM_DECRY 0x0a +#define RAM_TO_PERIPHERAL_ENCRY 0x04 +#define RAM_TO_PERIPHERAL_DECRY 0x0c + +void ECDC_Init( UINT8 ecdcmode, UINT8 clkmode, UINT8 keylen, PUINT32 pkey, PUINT32 pcount ); +void ECDC_SetKey( PUINT32 pkey, UINT8 keylen ); +void ECDC_SetCount( PUINT32 pcount ); +void ECDC_Excute( UINT8 excutemode, UINT8 endianmode ); +void ECDC_SingleRegister( PUINT32 pWdatbuff, PUINT32 pRdatbuff ); +void ECDC_SelfDMA( UINT32 ram_addr, UINT32 ram_len ); +void ECDC_RloadCount( UINT8 excutemode, UINT8 endianmode, PUINT32 pcount ); + + + +#ifdef __cplusplus +} +#endif + +#endif // __CH56x_ECDC_H__ + diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_emmc.h b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_emmc.h new file mode 100644 index 000000000..dfb4c5cd4 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_emmc.h @@ -0,0 +1,147 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : CH56x_emmc.h +* Author : WCH +* Version : V1.0 +* Date : 2020/07/31 +* Description : +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + +#ifndef __CH56x_EMMC_H__ +#define __CH56x_EMMC_H__ + +#ifdef __cplusplus + extern "C" { +#endif + + +/* CMD code */ +#define EMMC_CMD0 0 /* rsp:none */ +#define EMMC_CMD1 1 /* rsp:R3 SEND_OP_COND */ +#define EMMC_CMD2 2 /* rsp:R2 ALL_SEND_CID */ +#define EMMC_CMD3 3 /* rsp:R6 SEND_RELATIVE_ADDR */ +#define EMMC_CMD6 6 /* rsp: */ +#define EMMC_CMD7 7 /* rsp:Rb1 */ +#define EMMC_CMD8 8 /* rsp:R7 */ +#define EMMC_CMD9 9 /* rsp: */ +#define EMMC_CMD11 11 /* rsp: */ +#define EMMC_CMD12 12 /* rsp: */ +#define EMMC_CMD13 13 +#define EMMC_CMD17 17 /* rsp: READ_SINGLE_BLOCK */ +#define EMMC_CMD18 18 /* rsp: READ_MULTIPLE_BLOCK */ +#define EMMC_CMD24 24 /* rsp: WRITE_BLOCK */ +#define EMMC_CMD25 25 /* rsp: WRITE_MILTIPLE_BLOCK */ +#define EMMC_CMD41 41 /* rsp: */ +#define EMMC_CMD55 55 /* rsp: */ + +/* operation status */ +#define CMD_NULL 0x00 +#define CMD_SUCCESS 0x01 +#define CMD_FAILED 0x02 +#define OP_SUCCESS CMD_SUCCESS +#define OP_FAILED CMD_FAILED +#define OP_INVALID_ADD 0x21 //invalid address + +/* connection status*/ +#define EMMCDisconnect 0 +#define EMMCConnect 1 + + +/* operation on EMMC */ +#define EMMCCardSatus_Idle 0 /* EMMC on free */ +#define EMMCCardSatus_SendSingleReadCmd 1 /* send command:read single */ +#define EMMCCardSatus_SendMultReadCmd 2 /* send command:read multiple */ +#define EMMCCardSatus_SendSingleWriteCmd 3 /* send command:write single */ +#define EMMCCardSatus_SendMultWriteCmd 4 /* send command:write multiple */ +#define EMMCCardSatus_SingleReadData 5 /* on reading single */ +#define EMMCCardSatus_MultReadData 6 /* on reading multiple */ +#define EMMCCardSatus_SingleWriteData 7 /* on writing single */ +#define EMMCCardSatus_MultWriteData 8 /* on writing multiple */ +#define EMMCCardSatus_SingleReadComp 9 /* read single done */ +#define EMMCCardSatus_MultReadComp 10 /* read multiple done */ +#define EMMCCardSatus_SingleWriteComp 11 /* write single done */ +#define EMMCCardSatus_MultWriteComp 12 /* write multiple done */ + +/* EMMC type */ +#define EMMCIO_CAPACITY_SD_CARD_V1_1 0 +#define EMMCIO_CAPACITY_SD_CARD_V2_0 1 +#define EMMCIO_HIGH_CAPACITY_SD_CARD 2 +/* EMMC useful voltage type */ +#define EMMCCardVolt_3_3 (1<<0) +#define EMMCCardVolt_1_8 (1<<1) + +#define EMMCPLUGIN (1<<12) + +/* EMMC information */ +typedef struct _EMMC_PARAMETER{ +UINT8 EMMCLinkSatus; // connecting type +UINT8 EMMCCardSatus; // EMMC operation status +UINT8 EMMCType; // EMMC type +UINT8 EMMCVoltageMode; // EMMC useful voltage type bit0:3.3v bit1:1.8v +UINT32 EMMC_CID[4]; +UINT32 EMMC_CSD[4]; +UINT16 EMMC_RCA; // relative address +UINT16 EMMCSecSize; // single section capacity +UINT32 EMMCSecNum; // capacity of section + +UINT8 EMMCOpErr; // latest error status + +}EMMC_PARAMETER, *PSD_PARAMETER; + + +//#define RESP_TYPE_48 (0<<8) +#define RESP_TYPE_136 (1<<8) +#define RESP_TYPE_48 (2<<8) +#define RESP_TYPE_R1b (3<<8) + + +/* EMMC CLK SET */ +#define EMMCCLK_48 10 +#define EMMCCLK_60 8 +#define EMMCCLK_80 6 +#define EMMCCLK_96 5 +#define LOWEMMCCLK 0x1F +#define DEFAULTSDCLK EMMCCLK_48 +#define HIGHEMMCCLK EMMCCLK_96 + +/* EMMCIO power */ +#define EMMCIOSetPower_3_3 (R32_PA_CLR |= (1<<3)) /* PA3=0 SDIO power = 3.3v */ +#define EMMCIOSetPower_1_8 (R32_PA_OUT |= (1<<3)) /* PA3=1 SDIO EMMC*/ + + +#define EMMCSendCmd(a, b) {R32_EMMC_ARGUMENT = a; R16_EMMC_CMD_SET = b;} +#define EMMCDat0Sta (R32_EMMC_STATUS&(1<<17)) /* EMMC data0 status */ + +extern UINT8 EMMCIO0Init( void ); +extern UINT8 CheckCMDComp( PSD_PARAMETER pEMMCPara ); +extern void EMMCResetIdle( PSD_PARAMETER pEMMCPara ); +extern UINT8 EMMCReadOCR( PSD_PARAMETER pEMMCPara); +extern UINT8 EMMCReadCID( PSD_PARAMETER pEMMCPara ); +extern UINT8 EMMCSetRCA( PSD_PARAMETER pEMMCPara ); +extern UINT8 EMMCReadCSD( PSD_PARAMETER pEMMCPara ); +extern UINT8 SelectEMMCCard(PSD_PARAMETER pEMMCPara); +extern UINT8 ReadEMMCStatus(PSD_PARAMETER pEMMCPara); +extern UINT8 EMMCSetBusWidth(PSD_PARAMETER pEMMCPara, UINT8 bus_mode); +extern UINT8 EMMCSetHighSpeed(PSD_PARAMETER pEMMCPara); +extern UINT8 EMMCCardConfig( PSD_PARAMETER pEMMCPara ); +extern UINT8 EMMCIOTransErrorDeal( PSD_PARAMETER pEMMCPara ); +extern UINT8 EMMCCardReadEXCSD( PSD_PARAMETER pEMMCPara, PUINT8 pRdatbuf ); +extern UINT8 AES_EMMCWriteMulSec( PSD_PARAMETER pEMMCPara, PUINT32 pReqnum, PUINT32 pWdatbuf, UINT32 Lbaaddr, UINT8 excutemode, UINT8 endianmode, PUINT32 pcount); +extern UINT8 AES_EMMCReadMulSec( PSD_PARAMETER pEMMCPara, PUINT32 pReqnum, PUINT32 pRdatbuf, UINT32 Lbaaddr, UINT8 excutemode, UINT8 endianmode, PUINT32 pcount); +UINT8 EMMCCardReadOneSec( PSD_PARAMETER pEMMCPara, PUINT8 pRdatbuf, UINT32 Lbaaddr ); +UINT8 EMMCCardReadMulSec( PSD_PARAMETER pEMMCPara, PUINT16 pReqnum, PUINT8 pRdatbuf, UINT32 Lbaaddr ); +UINT8 EMMCCardWriteMulSec( PSD_PARAMETER pEMMCPara, PUINT16 pReqnum, PUINT8 pWdatbuf, UINT32 Lbaaddr ); + + + +#ifdef __cplusplus +} +#endif + +#endif //__CH56X_EMMC_H__ + + + diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_eth.h b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_eth.h new file mode 100644 index 000000000..83a83ed43 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_eth.h @@ -0,0 +1,1942 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch56x_eth.h +* Author : WCH +* Version : V1.0.0 +* Date : 2023/03/03 +* Description : This file contains all the functions prototypes for the +* ETH firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + + +#ifndef __CH56x_ETH_H +#define __CH56x_ETH_H + +#ifdef __cplusplus + extern "C" { +#endif + + +#include "CH56xSFR.h" +#include "core_riscv.h" +#include "CH56x_common.h" + +#ifndef uint16_t +typedef unsigned short uint16_t; +#endif + +#ifndef uint8_t +typedef unsigned char uint8_t ; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifndef __IO +#define __IO volatile +#endif + + +/*-------------------------------CH565/569 register table----------------------------------*/ +typedef struct +{ + __IO unsigned int MACCR; + __IO unsigned int MACFFR; + __IO unsigned int MACHTHR; + __IO unsigned int MACHTLR; + __IO unsigned int MACMIIAR; + __IO unsigned int MACMIIDR; + __IO unsigned int MACFCR; + __IO unsigned int MACVLANTR; + unsigned int RESERVED0[2]; + __IO unsigned int MACRWUFFR; + __IO unsigned int MACPMTCSR; + unsigned int RESERVED1[2]; + __IO unsigned int MACSR; + __IO unsigned int MACIMR; + __IO unsigned int MACA0HR; + __IO unsigned int MACA0LR; + __IO unsigned int MACA1HR; + __IO unsigned int MACA1LR; + __IO unsigned int MACA2HR; + __IO unsigned int MACA2LR; + __IO unsigned int MACA3HR; + __IO unsigned int MACA3LR; + unsigned int RESERVED2[40]; + __IO unsigned int MMCCR; + __IO unsigned int MMCRIR; + __IO unsigned int MMCTIR; + __IO unsigned int MMCRIMR; + __IO unsigned int MMCTIMR; + unsigned int RESERVED3[14]; + __IO unsigned int MMCTGFSCCR; + __IO unsigned int MMCTGFMSCCR; + unsigned int RESERVED4[5]; + __IO unsigned int MMCTGFCR; + unsigned int RESERVED5[10]; + __IO unsigned int MMCRFCECR; + __IO unsigned int MMCRFAECR; + unsigned int RESERVED6[10]; + __IO unsigned int MMCRGUFCR; + unsigned int RESERVED7[334]; + /* PTP is not supported yet */ + __IO unsigned int PTPTSCR; + __IO unsigned int PTPSSIR; + __IO unsigned int PTPTSHR; + __IO unsigned int PTPTSLR; + __IO unsigned int PTPTSHUR; + __IO unsigned int PTPTSLUR; + __IO unsigned int PTPTSAR; + __IO unsigned int PTPTTHR; + __IO unsigned int PTPTTLR; + __IO unsigned int RESERVED8; + __IO unsigned int PTPTSSR; + + unsigned int RESERVED9[565]; + __IO unsigned int DMABMR; + __IO unsigned int DMATPDR; + __IO unsigned int DMARPDR; + __IO unsigned int DMARDLAR; + __IO unsigned int DMATDLAR; + __IO unsigned int DMASR; + __IO unsigned int DMAOMR; + __IO unsigned int DMAIER; + __IO unsigned int DMAMFBOCR; + __IO unsigned int DMARSWTR; + unsigned int RESERVED10[8]; + __IO unsigned int DMACHTDR; + __IO unsigned int DMACHRDR; + __IO unsigned int DMACHTBAR; + __IO unsigned int DMACHRBAR; +} ETH_TypeDef; + +#define ETH ((ETH_TypeDef*)ETH_BASE) + +/******************************************************************************/ +/* */ +/* Ethernet MAC Registers bits definitions */ +/* */ +/******************************************************************************/ +/* Bit definition for Ethernet MAC Control Register register */ +#define ETH_MACCR_WD ((unsigned int)0x00800000) /* Watchdog disable */ +#define ETH_MACCR_JD ((unsigned int)0x00400000) /* Jabber disable */ +#define ETH_MACCR_IFG ((unsigned int)0x000E0000) /* Inter-frame gap */ +#define ETH_MACCR_IFG_96Bit ((unsigned int)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ +#define ETH_MACCR_IFG_88Bit ((unsigned int)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ +#define ETH_MACCR_IFG_80Bit ((unsigned int)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ +#define ETH_MACCR_IFG_72Bit ((unsigned int)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ +#define ETH_MACCR_IFG_64Bit ((unsigned int)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ +#define ETH_MACCR_IFG_56Bit ((unsigned int)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ +#define ETH_MACCR_IFG_48Bit ((unsigned int)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ +#define ETH_MACCR_IFG_40Bit ((unsigned int)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ +#define ETH_MACCR_CSD ((unsigned int)0x00010000) /* Carrier sense disable (during transmission) */ +#define ETH_MACCR_FES ((unsigned int)0x00004000) /* Fast ethernet speed */ +#define ETH_MACCR_ROD ((unsigned int)0x00002000) /* Receive own disable */ +#define ETH_MACCR_LM ((unsigned int)0x00001000) /* loopback mode */ +#define ETH_MACCR_DM ((unsigned int)0x00000800) /* Duplex mode */ +#define ETH_MACCR_IPCO ((unsigned int)0x00000400) /* IP Checksum offload */ +#define ETH_MACCR_RD ((unsigned int)0x00000200) /* Retry disable */ +#define ETH_MACCR_APCS ((unsigned int)0x00000080) /* Automatic Pad/CRC stripping */ +#define ETH_MACCR_BL ((unsigned int)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before reschedulinga transmission attempt during retries after a collision: 0 =< r <2^k */ +#define ETH_MACCR_BL_10 ((unsigned int)0x00000000) /* k = min (n, 10) */ +#define ETH_MACCR_BL_8 ((unsigned int)0x00000020) /* k = min (n, 8) */ +#define ETH_MACCR_BL_4 ((unsigned int)0x00000040) /* k = min (n, 4) */ +#define ETH_MACCR_BL_1 ((unsigned int)0x00000060) /* k = min (n, 1) */ +#define ETH_MACCR_DC ((unsigned int)0x00000010) /* Defferal check */ +#define ETH_MACCR_TE ((unsigned int)0x00000008) /* Transmitter enable */ +#define ETH_MACCR_RE ((unsigned int)0x00000004) /* Receiver enable */ + +/* Bit definition for Ethernet MAC Frame Filter Register */ +#define ETH_MACFFR_RA ((unsigned int)0x80000000) /* Receive all */ +#define ETH_MACFFR_HPF ((unsigned int)0x00000400) /* Hash or perfect filter */ +#define ETH_MACFFR_SAF ((unsigned int)0x00000200) /* Source address filter enable */ +#define ETH_MACFFR_SAIF ((unsigned int)0x00000100) /* SA inverse filtering */ +#define ETH_MACFFR_PCF ((unsigned int)0x000000C0) /* Pass control frames: 3 cases */ +#define ETH_MACFFR_PCF_BlockAll ((unsigned int)0x00000040) /* MAC filters all control frames from reaching the application */ +#define ETH_MACFFR_PCF_ForwardAll ((unsigned int)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ +#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((unsigned int)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ +#define ETH_MACFFR_BFD ((unsigned int)0x00000020) /* Broadcast frame disable */ +#define ETH_MACFFR_PAM ((unsigned int)0x00000010) /* Pass all mutlicast */ +#define ETH_MACFFR_DAIF ((unsigned int)0x00000008) /* DA Inverse filtering */ +#define ETH_MACFFR_HM ((unsigned int)0x00000004) /* Hash multicast */ +#define ETH_MACFFR_HU ((unsigned int)0x00000002) /* Hash unicast */ +#define ETH_MACFFR_PM ((unsigned int)0x00000001) /* Promiscuous mode */ + +/* Bit definition for Ethernet MAC Hash Table High Register */ +#define ETH_MACHTHR_HTH ((unsigned int)0xFFFFFFFF) /* Hash table high */ + +/* Bit definition for Ethernet MAC Hash Table Low Register */ +#define ETH_MACHTLR_HTL ((unsigned int)0xFFFFFFFF) /* Hash table low */ + +/* Bit definition for Ethernet MAC MII Address Register */ +#define ETH_MACMIIAR_PA ((unsigned int)0x0000F800) /* Physical layer address */ +#define ETH_MACMIIAR_MR ((unsigned int)0x000007C0) /* MII register in the selected PHY */ +#define ETH_MACMIIAR_CR ((unsigned int)0x0000001C) /* CR clock range: 6 cases */ +#define ETH_MACMIIAR_CR_Div42 ((unsigned int)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ +#define ETH_MACMIIAR_CR_Div62 ((unsigned int)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */ +#define ETH_MACMIIAR_CR_Div16 ((unsigned int)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ +#define ETH_MACMIIAR_CR_Div26 ((unsigned int)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ +#define ETH_MACMIIAR_CR_Div102 ((unsigned int)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */ +#define ETH_MACMIIAR_MW ((unsigned int)0x00000002) /* MII write */ +#define ETH_MACMIIAR_MB ((unsigned int)0x00000001) /* MII busy */ + +/* Bit definition for Ethernet MAC MII Data Register */ +#define ETH_MACMIIDR_MD ((unsigned int)0x0000FFFF) /* MII data: read/write data from/to PHY */ + +/* Bit definition for Ethernet MAC Flow Control Register */ +#define ETH_MACFCR_PT ((unsigned int)0xFFFF0000) /* Pause time */ +#define ETH_MACFCR_ZQPD ((unsigned int)0x00000080) /* Zero-quanta pause disable */ +#define ETH_MACFCR_PLT ((unsigned int)0x00000030) /* Pause low threshold: 4 cases */ +#define ETH_MACFCR_PLT_Minus4 ((unsigned int)0x00000000) /* Pause time minus 4 slot times */ +#define ETH_MACFCR_PLT_Minus28 ((unsigned int)0x00000010) /* Pause time minus 28 slot times */ +#define ETH_MACFCR_PLT_Minus144 ((unsigned int)0x00000020) /* Pause time minus 144 slot times */ +#define ETH_MACFCR_PLT_Minus256 ((unsigned int)0x00000030) /* Pause time minus 256 slot times */ +#define ETH_MACFCR_UPFD ((unsigned int)0x00000008) /* Unicast pause frame detect */ +#define ETH_MACFCR_RFCE ((unsigned int)0x00000004) /* Receive flow control enable */ +#define ETH_MACFCR_TFCE ((unsigned int)0x00000002) /* Transmit flow control enable */ +#define ETH_MACFCR_FCBBPA ((unsigned int)0x00000001) /* Flow control busy/backpressure activate */ + +/* Bit definition for Ethernet MAC VLAN Tag Register */ +#define ETH_MACVLANTR_VLANTC ((unsigned int)0x00010000) /* 12-bit VLAN tag comparison */ +#define ETH_MACVLANTR_VLANTI ((unsigned int)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ + +/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ +#define ETH_MACRWUFFR_D ((unsigned int)0xFFFFFFFF) /* Wake-up frame filter register data */ +/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. +Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ +/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask +Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask +Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask +Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask +Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - + RSVD - Filter1 Command - RSVD - Filter0 Command +Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset +Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 +Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ + +/* Bit definition for Ethernet MAC PMT Control and Status Register */ +#define ETH_MACPMTCSR_WFFRPR ((unsigned int)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ +#define ETH_MACPMTCSR_GU ((unsigned int)0x00000200) /* Global Unicast */ +#define ETH_MACPMTCSR_WFR ((unsigned int)0x00000040) /* Wake-Up Frame Received */ +#define ETH_MACPMTCSR_MPR ((unsigned int)0x00000020) /* Magic Packet Received */ +#define ETH_MACPMTCSR_WFE ((unsigned int)0x00000004) /* Wake-Up Frame Enable */ +#define ETH_MACPMTCSR_MPE ((unsigned int)0x00000002) /* Magic Packet Enable */ +#define ETH_MACPMTCSR_PD ((unsigned int)0x00000001) /* Power Down */ + +/* Bit definition for Ethernet MAC Status Register */ +#define ETH_MACSR_TSTS ((unsigned int)0x00000200) /* Time stamp trigger status */ +#define ETH_MACSR_MMCTS ((unsigned int)0x00000040) /* MMC transmit status */ +#define ETH_MACSR_MMMCRS ((unsigned int)0x00000020) /* MMC receive status */ +#define ETH_MACSR_MMCS ((unsigned int)0x00000010) /* MMC status */ +#define ETH_MACSR_PMTS ((unsigned int)0x00000008) /* PMT status */ + +/* Bit definition for Ethernet MAC Interrupt Mask Register */ +#define ETH_MACIMR_TSTIM ((unsigned int)0x00000200) /* Time stamp trigger interrupt mask */ +#define ETH_MACIMR_PMTIM ((unsigned int)0x00000008) /* PMT interrupt mask */ + +/* Bit definition for Ethernet MAC Address0 High Register */ +#define ETH_MACA0HR_MACA0H ((unsigned int)0x0000FFFF) /* MAC address0 high */ + +/* Bit definition for Ethernet MAC Address0 Low Register */ +#define ETH_MACA0LR_MACA0L ((unsigned int)0xFFFFFFFF) /* MAC address0 low */ + +/* Bit definition for Ethernet MAC Address1 High Register */ +#define ETH_MACA1HR_AE ((unsigned int)0x80000000) /* Address enable */ +#define ETH_MACA1HR_SA ((unsigned int)0x40000000) /* Source address */ +#define ETH_MACA1HR_MBC ((unsigned int)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ +#define ETH_MACA1HR_MBC_HBits15_8 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MACA1HR_MBC_HBits7_0 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MACA1HR_MBC_LBits31_24 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MACA1HR_MBC_LBits23_16 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MACA1HR_MBC_LBits15_8 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MACA1HR_MBC_LBits7_0 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACA1HR_MACA1H ((unsigned int)0x0000FFFF) /* MAC address1 high */ + +/* Bit definition for Ethernet MAC Address1 Low Register */ +#define ETH_MACA1LR_MACA1L ((unsigned int)0xFFFFFFFF) /* MAC address1 low */ + +/* Bit definition for Ethernet MAC Address2 High Register */ +#define ETH_MACA2HR_AE ((unsigned int)0x80000000) /* Address enable */ +#define ETH_MACA2HR_SA ((unsigned int)0x40000000) /* Source address */ +#define ETH_MACA2HR_MBC ((unsigned int)0x3F000000) /* Mask byte control */ +#define ETH_MACA2HR_MBC_HBits15_8 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MACA2HR_MBC_HBits7_0 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MACA2HR_MBC_LBits31_24 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MACA2HR_MBC_LBits23_16 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MACA2HR_MBC_LBits15_8 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MACA2HR_MBC_LBits7_0 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [70] */ +#define ETH_MACA2HR_MACA2H ((unsigned int)0x0000FFFF) /* MAC address1 high */ + +/* Bit definition for Ethernet MAC Address2 Low Register */ +#define ETH_MACA2LR_MACA2L ((unsigned int)0xFFFFFFFF) /* MAC address2 low */ + +/* Bit definition for Ethernet MAC Address3 High Register */ +#define ETH_MACA3HR_AE ((unsigned int)0x80000000) /* Address enable */ +#define ETH_MACA3HR_SA ((unsigned int)0x40000000) /* Source address */ +#define ETH_MACA3HR_MBC ((unsigned int)0x3F000000) /* Mask byte control */ +#define ETH_MACA3HR_MBC_HBits15_8 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MACA3HR_MBC_HBits7_0 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MACA3HR_MBC_LBits31_24 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MACA3HR_MBC_LBits23_16 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MACA3HR_MBC_LBits15_8 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MACA3HR_MBC_LBits7_0 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [70] */ +#define ETH_MACA3HR_MACA3H ((unsigned int)0x0000FFFF) /* MAC address3 high */ + +/* Bit definition for Ethernet MAC Address3 Low Register */ +#define ETH_MACA3LR_MACA3L ((unsigned int)0xFFFFFFFF) /* MAC address3 low */ + +/******************************************************************************/ +/* Ethernet MMC Registers bits definition */ +/******************************************************************************/ + +/* Bit definition for Ethernet MMC Contol Register */ +#define ETH_MMCCR_MCFHP ((unsigned int)0x00000020) /* MMC counter Full-Half preset */ +#define ETH_MMCCR_MCP ((unsigned int)0x00000010) /* MMC counter preset */ +#define ETH_MMCCR_MCF ((unsigned int)0x00000008) /* MMC Counter Freeze */ +#define ETH_MMCCR_ROR ((unsigned int)0x00000004) /* Reset on Read */ +#define ETH_MMCCR_CSR ((unsigned int)0x00000002) /* Counter Stop Rollover */ +#define ETH_MMCCR_CR ((unsigned int)0x00000001) /* Counters Reset */ + +/* Bit definition for Ethernet MMC Receive Interrupt Register */ +#define ETH_MMCRIR_RGUFS ((unsigned int)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIR_RFAES ((unsigned int)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIR_RFCES ((unsigned int)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Transmit Interrupt Register */ +#define ETH_MMCTIR_TGFS ((unsigned int)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFMSCS ((unsigned int)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFSCS ((unsigned int)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ +#define ETH_MMCRIMR_RGUFM ((unsigned int)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFAEM ((unsigned int)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFCEM ((unsigned int)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ +#define ETH_MMCTIMR_TGFM ((unsigned int)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFMSCM ((unsigned int)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFSCM ((unsigned int)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ +#define ETH_MMCTGFSCCR_TGFSCC ((unsigned int)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ + +/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ +#define ETH_MMCTGFMSCCR_TGFMSCC ((unsigned int)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ + +/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ +#define ETH_MMCTGFCR_TGFC ((unsigned int)0xFFFFFFFF) /* Number of good frames transmitted. */ + +/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ +#define ETH_MMCRFCECR_RFCEC ((unsigned int)0xFFFFFFFF) /* Number of frames received with CRC error. */ + +/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ +#define ETH_MMCRFAECR_RFAEC ((unsigned int)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ + +/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ +#define ETH_MMCRGUFCR_RGUFC ((unsigned int)0xFFFFFFFF) /* Number of good unicast frames received. */ + +/******************************************************************************/ +/* Ethernet PTP Registers bits definition */ +/******************************************************************************/ +/* PTP is not supported yet */ +/* Bit definition for Ethernet PTP Time Stamp Contol Register */ +#define ETH_PTPTSCR_TSCNT ((unsigned int)0x00030000) /* Time stamp clock node type */ +#define ETH_PTPTSSR_TSSMRME ((unsigned int)0x00008000) /* Time stamp snapshot for message relevant to master enable */ +#define ETH_PTPTSSR_TSSEME ((unsigned int)0x00004000) /* Time stamp snapshot for event message enable */ +#define ETH_PTPTSSR_TSSIPV4FE ((unsigned int)0x00002000) /* Time stamp snapshot for IPv4 frames enable */ +#define ETH_PTPTSSR_TSSIPV6FE ((unsigned int)0x00001000) /* Time stamp snapshot for IPv6 frames enable */ +#define ETH_PTPTSSR_TSSPTPOEFE ((unsigned int)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */ +#define ETH_PTPTSSR_TSPTPPSV2E ((unsigned int)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */ +#define ETH_PTPTSSR_TSSSR ((unsigned int)0x00000200) /* Time stamp Sub-seconds rollover */ +#define ETH_PTPTSSR_TSSARFE ((unsigned int)0x00000100) /* Time stamp snapshot for all received frames enable */ + +#define ETH_PTPTSCR_TSARU ((unsigned int)0x00000020) /* Addend register update */ +#define ETH_PTPTSCR_TSITE ((unsigned int)0x00000010) /* Time stamp interrupt trigger enable */ +#define ETH_PTPTSCR_TSSTU ((unsigned int)0x00000008) /* Time stamp update */ +#define ETH_PTPTSCR_TSSTI ((unsigned int)0x00000004) /* Time stamp initialize */ +#define ETH_PTPTSCR_TSFCU ((unsigned int)0x00000002) /* Time stamp fine or coarse update */ +#define ETH_PTPTSCR_TSE ((unsigned int)0x00000001) /* Time stamp enable */ + +/* Bit definition for Ethernet PTP Sub-Second Increment Register */ +#define ETH_PTPSSIR_STSSI ((unsigned int)0x000000FF) /* System time Sub-second increment value */ + +/* Bit definition for Ethernet PTP Time Stamp High Register */ +#define ETH_PTPTSHR_STS ((unsigned int)0xFFFFFFFF) /* System Time second */ + +/* Bit definition for Ethernet PTP Time Stamp Low Register */ +#define ETH_PTPTSLR_STPNS ((unsigned int)0x80000000) /* System Time Positive or negative time */ +#define ETH_PTPTSLR_STSS ((unsigned int)0x7FFFFFFF) /* System Time sub-seconds */ + +/* Bit definition for Ethernet PTP Time Stamp High Update Register */ +#define ETH_PTPTSHUR_TSUS ((unsigned int)0xFFFFFFFF) /* Time stamp update seconds */ + +/* Bit definition for Ethernet PTP Time Stamp Low Update Register */ +#define ETH_PTPTSLUR_TSUPNS ((unsigned int)0x80000000) /* Time stamp update Positive or negative time */ +#define ETH_PTPTSLUR_TSUSS ((unsigned int)0x7FFFFFFF) /* Time stamp update sub-seconds */ + +/* Bit definition for Ethernet PTP Time Stamp Addend Register */ +#define ETH_PTPTSAR_TSA ((unsigned int)0xFFFFFFFF) /* Time stamp addend */ + +/* Bit definition for Ethernet PTP Target Time High Register */ +#define ETH_PTPTTHR_TTSH ((unsigned int)0xFFFFFFFF) /* Target time stamp high */ + +/* Bit definition for Ethernet PTP Target Time Low Register */ +#define ETH_PTPTTLR_TTSL ((unsigned int)0xFFFFFFFF) /* Target time stamp low */ + +/* Bit definition for Ethernet PTP Time Stamp Status Register */ +#define ETH_PTPTSSR_TSTTR ((unsigned int)0x00000020) /* Time stamp target time reached */ +#define ETH_PTPTSSR_TSSO ((unsigned int)0x00000010) /* Time stamp seconds overflow */ + +/******************************************************************************/ +/* Ethernet DMA Registers bits definition */ +/******************************************************************************/ + +/* Bit definition for Ethernet DMA Bus Mode Register */ +#define ETH_DMABMR_AAB ((unsigned int)0x02000000) /* Address-Aligned beats */ +#define ETH_DMABMR_FPM ((unsigned int)0x01000000) /* 4xPBL mode */ +#define ETH_DMABMR_USP ((unsigned int)0x00800000) /* Use separate PBL */ +#define ETH_DMABMR_RDP ((unsigned int)0x007E0000) /* RxDMA PBL */ +#define ETH_DMABMR_RDP_1Beat ((unsigned int)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ +#define ETH_DMABMR_RDP_2Beat ((unsigned int)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ +#define ETH_DMABMR_RDP_4Beat ((unsigned int)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_DMABMR_RDP_8Beat ((unsigned int)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_DMABMR_RDP_16Beat ((unsigned int)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_DMABMR_RDP_32Beat ((unsigned int)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_DMABMR_RDP_4xPBL_4Beat ((unsigned int)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_DMABMR_RDP_4xPBL_8Beat ((unsigned int)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_DMABMR_RDP_4xPBL_16Beat ((unsigned int)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_DMABMR_RDP_4xPBL_32Beat ((unsigned int)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_DMABMR_RDP_4xPBL_64Beat ((unsigned int)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ +#define ETH_DMABMR_RDP_4xPBL_128Beat ((unsigned int)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ +#define ETH_DMABMR_FB ((unsigned int)0x00010000) /* Fixed Burst */ +#define ETH_DMABMR_RTPR ((unsigned int)0x0000C000) /* Rx Tx priority ratio */ +#define ETH_DMABMR_RTPR_1_1 ((unsigned int)0x00000000) /* Rx Tx priority ratio */ +#define ETH_DMABMR_RTPR_2_1 ((unsigned int)0x00004000) /* Rx Tx priority ratio */ +#define ETH_DMABMR_RTPR_3_1 ((unsigned int)0x00008000) /* Rx Tx priority ratio */ +#define ETH_DMABMR_RTPR_4_1 ((unsigned int)0x0000C000) /* Rx Tx priority ratio */ +#define ETH_DMABMR_PBL ((unsigned int)0x00003F00) /* Programmable burst length */ +#define ETH_DMABMR_PBL_1Beat ((unsigned int)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ +#define ETH_DMABMR_PBL_2Beat ((unsigned int)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ +#define ETH_DMABMR_PBL_4Beat ((unsigned int)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_DMABMR_PBL_8Beat ((unsigned int)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_DMABMR_PBL_16Beat ((unsigned int)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_DMABMR_PBL_32Beat ((unsigned int)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_DMABMR_PBL_4xPBL_4Beat ((unsigned int)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_DMABMR_PBL_4xPBL_8Beat ((unsigned int)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_DMABMR_PBL_4xPBL_16Beat ((unsigned int)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_DMABMR_PBL_4xPBL_32Beat ((unsigned int)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_DMABMR_PBL_4xPBL_64Beat ((unsigned int)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ +#define ETH_DMABMR_PBL_4xPBL_128Beat ((unsigned int)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +#define ETH_DMABMR_EDE ((unsigned int)0x00000080) /* Enhanced Descriptor Enable */ +#define ETH_DMABMR_DSL ((unsigned int)0x0000007C) /* Descriptor Skip Length */ +#define ETH_DMABMR_DA ((unsigned int)0x00000002) /* DMA arbitration scheme */ +#define ETH_DMABMR_SR ((unsigned int)0x00000001) /* Software reset */ + +/* Bit definition for Ethernet DMA Transmit Poll Demand Register */ +#define ETH_DMATPDR_TPD ((unsigned int)0xFFFFFFFF) /* Transmit poll demand */ + +/* Bit definition for Ethernet DMA Receive Poll Demand Register */ +#define ETH_DMARPDR_RPD ((unsigned int)0xFFFFFFFF) /* Receive poll demand */ + +/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ +#define ETH_DMARDLAR_SRL ((unsigned int)0xFFFFFFFF) /* Start of receive list */ + +/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ +#define ETH_DMATDLAR_STL ((unsigned int)0xFFFFFFFF) /* Start of transmit list */ + +/* Bit definition for Ethernet DMA Status Register */ +#define ETH_DMASR_TSTS ((unsigned int)0x20000000) /* Time-stamp trigger status */ +#define ETH_DMASR_PMTS ((unsigned int)0x10000000) /* PMT status */ +#define ETH_DMASR_MMCS ((unsigned int)0x08000000) /* MMC status */ +#define ETH_DMASR_EBS ((unsigned int)0x03800000) /* Error bits status */ +/* combination with EBS[2:0] for GetFlagStatus function */ +#define ETH_DMASR_EBS_DescAccess ((unsigned int)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ +#define ETH_DMASR_EBS_ReadTransf ((unsigned int)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ +#define ETH_DMASR_EBS_DataTransfTx ((unsigned int)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMASR_TPS ((unsigned int)0x00700000) /* Transmit process state */ +#define ETH_DMASR_TPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ +#define ETH_DMASR_TPS_Fetching ((unsigned int)0x00100000) /* Running - fetching the Tx descriptor */ +#define ETH_DMASR_TPS_Waiting ((unsigned int)0x00200000) /* Running - waiting for status */ +#define ETH_DMASR_TPS_Reading ((unsigned int)0x00300000) /* Running - reading the data from host memory */ +#define ETH_DMASR_TPS_Suspended ((unsigned int)0x00600000) /* Suspended - Tx Descriptor unavailabe */ +#define ETH_DMASR_TPS_Closing ((unsigned int)0x00700000) /* Running - closing Rx descriptor */ +#define ETH_DMASR_RPS ((unsigned int)0x000E0000) /* Receive process state */ +#define ETH_DMASR_RPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ +#define ETH_DMASR_RPS_Fetching ((unsigned int)0x00020000) /* Running - fetching the Rx descriptor */ +#define ETH_DMASR_RPS_Waiting ((unsigned int)0x00060000) /* Running - waiting for packet */ +#define ETH_DMASR_RPS_Suspended ((unsigned int)0x00080000) /* Suspended - Rx Descriptor unavailable */ +#define ETH_DMASR_RPS_Closing ((unsigned int)0x000A0000) /* Running - closing descriptor */ +#define ETH_DMASR_RPS_Queuing ((unsigned int)0x000E0000) /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_NIS ((unsigned int)0x00010000) /* Normal interrupt summary */ +#define ETH_DMASR_AIS ((unsigned int)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMASR_ERS ((unsigned int)0x00004000) /* Early receive status */ +#define ETH_DMASR_FBES ((unsigned int)0x00002000) /* Fatal bus error status */ +#define ETH_DMASR_ETS ((unsigned int)0x00000400) /* Early transmit status */ +#define ETH_DMASR_RWTS ((unsigned int)0x00000200) /* Receive watchdog timeout status */ +#define ETH_DMASR_RPSS ((unsigned int)0x00000100) /* Receive process stopped status */ +#define ETH_DMASR_RBUS ((unsigned int)0x00000080) /* Receive buffer unavailable status */ +#define ETH_DMASR_RS ((unsigned int)0x00000040) /* Receive status */ +#define ETH_DMASR_TUS ((unsigned int)0x00000020) /* Transmit underflow status */ +#define ETH_DMASR_ROS ((unsigned int)0x00000010) /* Receive overflow status */ +#define ETH_DMASR_TJTS ((unsigned int)0x00000008) /* Transmit jabber timeout status */ +#define ETH_DMASR_TBUS ((unsigned int)0x00000004) /* Transmit buffer unavailable status */ +#define ETH_DMASR_TPSS ((unsigned int)0x00000002) /* Transmit process stopped status */ +#define ETH_DMASR_TS ((unsigned int)0x00000001) /* Transmit status */ + +/* Bit definition for Ethernet DMA Operation Mode Register */ +#define ETH_DMAOMR_DTCEFD ((unsigned int)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ +#define ETH_DMAOMR_RSF ((unsigned int)0x02000000) /* Receive store and forward */ +#define ETH_DMAOMR_DFRF ((unsigned int)0x01000000) /* Disable flushing of received frames */ +#define ETH_DMAOMR_TSF ((unsigned int)0x00200000) /* Transmit store and forward */ +#define ETH_DMAOMR_FTF ((unsigned int)0x00100000) /* Flush transmit FIFO */ +#define ETH_DMAOMR_TTC ((unsigned int)0x0001C000) /* Transmit threshold control */ +#define ETH_DMAOMR_TTC_64Bytes ((unsigned int)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ +#define ETH_DMAOMR_TTC_128Bytes ((unsigned int)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ +#define ETH_DMAOMR_TTC_192Bytes ((unsigned int)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ +#define ETH_DMAOMR_TTC_256Bytes ((unsigned int)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ +#define ETH_DMAOMR_TTC_40Bytes ((unsigned int)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ +#define ETH_DMAOMR_TTC_32Bytes ((unsigned int)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ +#define ETH_DMAOMR_TTC_24Bytes ((unsigned int)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ +#define ETH_DMAOMR_TTC_16Bytes ((unsigned int)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ +#define ETH_DMAOMR_ST ((unsigned int)0x00002000) /* Start/stop transmission command */ +#define ETH_DMAOMR_FEF ((unsigned int)0x00000080) /* Forward error frames */ +#define ETH_DMAOMR_FUGF ((unsigned int)0x00000040) /* Forward undersized good frames */ +#define ETH_DMAOMR_RTC ((unsigned int)0x00000018) /* receive threshold control */ +#define ETH_DMAOMR_RTC_64Bytes ((unsigned int)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ +#define ETH_DMAOMR_RTC_32Bytes ((unsigned int)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ +#define ETH_DMAOMR_RTC_96Bytes ((unsigned int)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ +#define ETH_DMAOMR_RTC_128Bytes ((unsigned int)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ +#define ETH_DMAOMR_OSF ((unsigned int)0x00000004) /* operate on second frame */ +#define ETH_DMAOMR_SR ((unsigned int)0x00000002) /* Start/stop receive */ + +/* Bit definition for Ethernet DMA Interrupt Enable Register */ +#define ETH_DMAIER_NISE ((unsigned int)0x00010000) /* Normal interrupt summary enable */ +#define ETH_DMAIER_AISE ((unsigned int)0x00008000) /* Abnormal interrupt summary enable */ +#define ETH_DMAIER_ERIE ((unsigned int)0x00004000) /* Early receive interrupt enable */ +#define ETH_DMAIER_FBEIE ((unsigned int)0x00002000) /* Fatal bus error interrupt enable */ +#define ETH_DMAIER_ETIE ((unsigned int)0x00000400) /* Early transmit interrupt enable */ +#define ETH_DMAIER_RWTIE ((unsigned int)0x00000200) /* Receive watchdog timeout interrupt enable */ +#define ETH_DMAIER_RPSIE ((unsigned int)0x00000100) /* Receive process stopped interrupt enable */ +#define ETH_DMAIER_RBUIE ((unsigned int)0x00000080) /* Receive buffer unavailable interrupt enable */ +#define ETH_DMAIER_RIE ((unsigned int)0x00000040) /* Receive interrupt enable */ +#define ETH_DMAIER_TUIE ((unsigned int)0x00000020) /* Transmit Underflow interrupt enable */ +#define ETH_DMAIER_ROIE ((unsigned int)0x00000010) /* Receive Overflow interrupt enable */ +#define ETH_DMAIER_TJTIE ((unsigned int)0x00000008) /* Transmit jabber timeout interrupt enable */ +#define ETH_DMAIER_TBUIE ((unsigned int)0x00000004) /* Transmit buffer unavailable interrupt enable */ +#define ETH_DMAIER_TPSIE ((unsigned int)0x00000002) /* Transmit process stopped interrupt enable */ +#define ETH_DMAIER_TIE ((unsigned int)0x00000001) /* Transmit interrupt enable */ + +/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ +#define ETH_DMAMFBOCR_OFOC ((unsigned int)0x10000000) /* Overflow bit for FIFO overflow counter */ +#define ETH_DMAMFBOCR_MFA ((unsigned int)0x0FFE0000) /* Number of frames missed by the application */ +#define ETH_DMAMFBOCR_OMFC ((unsigned int)0x00010000) /* Overflow bit for missed frame counter */ +#define ETH_DMAMFBOCR_MFC ((unsigned int)0x0000FFFF) /* Number of frames missed by the controller */ + +/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ +#define ETH_DMACHTDR_HTDAP ((unsigned int)0xFFFFFFFF) /* Host transmit descriptor address pointer */ + +/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ +#define ETH_DMACHRDR_HRDAP ((unsigned int)0xFFFFFFFF) /* Host receive descriptor address pointer */ + +/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ +#define ETH_DMACHTBAR_HTBAP ((unsigned int)0xFFFFFFFF) /* Host transmit buffer address pointer */ + +/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ +#define ETH_DMACHRBAR_HRBAP ((unsigned int)0xFFFFFFFF) /* Host receive buffer address pointer */ + +#define PHY_RESET_DELAY ((uint32_t)0x000FFFFF) +#define PHY_CONFIG_DELAY ((uint32_t)0x00FFFFFF) +#define PHY_BMCR 0x00 +#define PHY_BMSR 0x01 +#define PHY_SR 0X11 +#define PHY_DUPLEX_STATUS (1<<13) +#define PHY_SPEED_STATUS (0XC000) + +/**--------------------------------------------------------------------------**/ +/** +* @brief Ethernet DMA descriptors registers bits definition +*/ +/**--------------------------------------------------------------------------**/ + +/** +@code +DMA Tx Desciptor +----------------------------------------------------------------------------------------------- +TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | +----------------------------------------------------------------------------------------------- +TDES1 | Reserved[31:13] | Buffer1 ByteCount[12:0] | +----------------------------------------------------------------------------------------------- +TDES2 | Buffer1 Address [31:0] | +----------------------------------------------------------------------------------------------- +TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | +----------------------------------------------------------------------------------------------- +@endcode +*/ + +/** +* @brief Bit definition of TDES0 register: DMA Tx descriptor status register +*/ +#ifndef ETH_DMATxDesc_OWN +#define ETH_DMATxDesc_OWN ((unsigned int)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMATxDesc_IC ((unsigned int)0x40000000) /*!< Interrupt on Completion */ +#define ETH_DMATxDesc_LS ((unsigned int)0x20000000) /*!< Last Segment */ +#define ETH_DMATxDesc_FS ((unsigned int)0x10000000) /*!< First Segment */ +#define ETH_DMATxDesc_DC ((unsigned int)0x08000000) /*!< Disable CRC */ +#define ETH_DMATxDesc_DP ((unsigned int)0x04000000) /*!< Disable Padding */ +#define ETH_DMATxDesc_TTSE ((unsigned int)0x02000000) /*!< Transmit Time Stamp Enable */ +#define ETH_DMATxDesc_CIC ((unsigned int)0x00C00000) /*!< Checksum Insertion Control: 4 cases */ +#define ETH_DMATxDesc_CIC_ByPass ((unsigned int)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */ +#define ETH_DMATxDesc_CIC_IPV4Header ((unsigned int)0x00400000) /*!< IPV4 header Checksum Insertion */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((unsigned int)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((unsigned int)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ +#define ETH_DMATxDesc_TER ((unsigned int)0x00200000) /*!< Transmit End of Ring */ +#define ETH_DMATxDesc_TCH ((unsigned int)0x00100000) /*!< Second Address Chained */ +#define ETH_DMATxDesc_TTSS ((unsigned int)0x00020000) /*!< Tx Time Stamp Status */ +#define ETH_DMATxDesc_IHE ((unsigned int)0x00010000) /*!< IP Header Error */ +#define ETH_DMATxDesc_ES ((unsigned int)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ +#define ETH_DMATxDesc_JT ((unsigned int)0x00004000) /*!< Jabber Timeout */ +#define ETH_DMATxDesc_FF ((unsigned int)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ +#endif +#define ETH_DMATxDesc_PCE ((unsigned int)0x00001000) /*!< Payload Checksum Error */ +#define ETH_DMATxDesc_LCA ((unsigned int)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */ +#define ETH_DMATxDesc_NC ((unsigned int)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */ +#define ETH_DMATxDesc_LCO ((unsigned int)0x00000200) /*!< Late Collision: transmission aborted due to collision */ +#define ETH_DMATxDesc_EC ((unsigned int)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */ +#define ETH_DMATxDesc_VF ((unsigned int)0x00000080) /*!< VLAN Frame */ +#define ETH_DMATxDesc_CC ((unsigned int)0x00000078) /*!< Collision Count */ +#define ETH_DMATxDesc_ED ((unsigned int)0x00000004) /*!< Excessive Deferral */ +#define ETH_DMATxDesc_UF ((unsigned int)0x00000002) /*!< Underflow Error: late data arrival from the memory */ +#define ETH_DMATxDesc_DB ((unsigned int)0x00000001) /*!< Deferred Bit */ + +/** +* @brief Bit definition of TDES1 register +*/ +#define ETH_DMATxDesc_TBS2 ((unsigned int)0x1FFF0000) /*!< Transmit Buffer2 Size */ +#define ETH_DMATxDesc_TBS1 ((unsigned int)0x00001FFF) /*!< Transmit Buffer1 Size */ + +/** +* @brief Bit definition of TDES2 register +*/ +#define ETH_DMATxDesc_B1AP ((unsigned int)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ + +/** +* @brief Bit definition of TDES3 register +*/ +#define ETH_DMATxDesc_B2AP ((unsigned int)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ + +/** +* @} +*/ + + +/** @defgroup DMA_Rx_descriptor +* @{ +*/ + +/** +@code +DMA Rx Descriptor +-------------------------------------------------------------------------------------------------------------------- +RDES0 | OWN(31) | Status [30:0] | +--------------------------------------------------------------------------------------------------------------------- +RDES1 | DIC(31) | Reserved(31:16)| RER(15)| Reserved(14:13) | Buffer1 ByteCount[12:0] | +--------------------------------------------------------------------------------------------------------------------- +RDES2 | Buffer1 Address [31:0] | +--------------------------------------------------------------------------------------------------------------------- +RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | +--------------------------------------------------------------------------------------------------------------------- +@endcode +*/ + +/** +* @brief Bit definition of RDES0 register: DMA Rx descriptor status register +*/ +#define ETH_DMARxDesc_OWN ((unsigned int)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMARxDesc_AFM ((unsigned int)0x40000000) /*!< DA Filter Fail for the rx frame */ +#define ETH_DMARxDesc_FL ((unsigned int)0x3FFF0000) /*!< Receive descriptor frame length */ +#define ETH_DMARxDesc_ES ((unsigned int)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ +#define ETH_DMARxDesc_DE ((unsigned int)0x00004000) /*!< Descriptor error: no more descriptors for receive frame */ +#define ETH_DMARxDesc_SAF ((unsigned int)0x00002000) /*!< SA Filter Fail for the received frame */ +#define ETH_DMARxDesc_LE ((unsigned int)0x00001000) /*!< Frame size not matching with length field */ +#define ETH_DMARxDesc_OE ((unsigned int)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */ +#define ETH_DMARxDesc_VLAN ((unsigned int)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */ +#define ETH_DMARxDesc_FS ((unsigned int)0x00000200) /*!< First descriptor of the frame */ +#define ETH_DMARxDesc_LS ((unsigned int)0x00000100) /*!< Last descriptor of the frame */ +#define ETH_DMARxDesc_IPV4HCE ((unsigned int)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ +#define ETH_DMARxDesc_LC ((unsigned int)0x00000040) /*!< Late collision occurred during reception */ +#define ETH_DMARxDesc_FT ((unsigned int)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */ +#define ETH_DMARxDesc_RWT ((unsigned int)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ +#define ETH_DMARxDesc_RE ((unsigned int)0x00000008) /*!< Receive error: error reported by MII interface */ +#define ETH_DMARxDesc_DBE ((unsigned int)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */ +#define ETH_DMARxDesc_CE ((unsigned int)0x00000002) /*!< CRC error */ +#define ETH_DMARxDesc_MAMPCE ((unsigned int)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ + +/** +* @brief Bit definition of RDES1 register /* DMA不会使用下述的位 +*/ +#define ETH_DMARxDesc_DIC ((unsigned int)0x80000000) /*!< Disable Interrupt on Completion */ +//#define ETH_DMARxDesc_RBS2 ((unsigned int)0x1FFF0000) /*!< Receive Buffer2 Size */ +#define ETH_DMARxDesc_RER ((unsigned int)0x00008000) /*!< Receive End of Ring */ +//#define ETH_DMARxDesc_RCH ((unsigned int)0x00004000) /*!< Second Address Chained */ +//#define ETH_DMARxDesc_RBS1 ((unsigned int)0x00001FFF) /*!< Receive Buffer1 Size */ + +/** +* @brief Bit definition of RDES2 register +*/ +#define ETH_DMARxDesc_B1AP ((unsigned int)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ + +/** +* @brief Bit definition of RDES3 register +*/ +#define ETH_DMARxDesc_B2AP ((unsigned int)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ + +/**--------------------------------------------------------------------------**/ +/** +* @brief Description of common PHY registers +*/ +/**--------------------------------------------------------------------------**/ + +/** +* @} +*/ + +/** @defgroup PHY_Read_write_Timeouts +* @{ +*/ +#define PHY_READ_TO ((unsigned int)0x0004FFFF) +#define PHY_WRITE_TO ((unsigned int)0x0004FFFF) + +/** +* @} +*/ + +/** @defgroup PHY_Register_address +* @{ +*/ +#define PHY_BCR 0 /*!< Transceiver Basic Control Register */ +#define PHY_BSR 1 /*!< Transceiver Basic Status Register */ + +#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20) +#define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \ + ((REG) == PHY_BSR) || \ + ((REG) == PHY_SR)) +/** +* @} +*/ + +/** @defgroup PHY_basic_Control_register +* @{ +*/ +#define PHY_Reset ((uint16_t)0x8000) /*!< PHY Reset */ +#define PHY_Loopback ((uint16_t)0x4000) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AutoNegotiation ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ +#define PHY_Restart_AutoNegotiation ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ +#define PHY_Powerdown ((uint16_t)0x0800) /*!< Select the power down mode */ +#define PHY_Isolate ((uint16_t)0x0400) /*!< Isolate PHY from MII */ + +/** +* @} +*/ + +/** @defgroup PHY_basic_status_register +* @{ +*/ +#define PHY_AutoNego_Complete ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ +#define PHY_Linked_Status ((uint16_t)0x0004) /*!< Valid link established */ +#define PHY_Jabber_detection ((uint16_t)0x0002) /*!< Jabber condition detected */ + +/** +* @} +*/ + +/**--------------------------------------------------------------------------**/ +/** +* @brief MAC defines +*/ +/**--------------------------------------------------------------------------**/ + +/** @defgroup ETH_AutoNegotiation +* @{ +*/ +#define ETH_AutoNegotiation_Enable ((unsigned int)0x00000001) +#define ETH_AutoNegotiation_Disable ((unsigned int)0x00000000) +#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \ + ((CMD) == ETH_AutoNegotiation_Disable)) + +/** +* @} +*/ + +/** @defgroup ETH_watchdog +* @{ +*/ +#define ETH_Watchdog_Enable ((unsigned int)0x00000000) +#define ETH_Watchdog_Disable ((unsigned int)0x00800000) +#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \ + ((CMD) == ETH_Watchdog_Disable)) + +/** +* @} +*/ + +/** @defgroup ETH_Jabber +* @{ +*/ +#define ETH_Jabber_Enable ((unsigned int)0x00000000) +#define ETH_Jabber_Disable ((unsigned int)0x00400000) +#define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \ + ((CMD) == ETH_Jabber_Disable)) + +/** +* @} +*/ + +/** @defgroup ETH_Inter_Frame_Gap +* @{ +*/ +#define ETH_InterFrameGap_96Bit ((unsigned int)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */ +#define ETH_InterFrameGap_88Bit ((unsigned int)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */ +#define ETH_InterFrameGap_80Bit ((unsigned int)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */ +#define ETH_InterFrameGap_72Bit ((unsigned int)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */ +#define ETH_InterFrameGap_64Bit ((unsigned int)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */ +#define ETH_InterFrameGap_56Bit ((unsigned int)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */ +#define ETH_InterFrameGap_48Bit ((unsigned int)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */ +#define ETH_InterFrameGap_40Bit ((unsigned int)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */ +#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_InterFrameGap_96Bit) || \ + ((GAP) == ETH_InterFrameGap_88Bit) || \ + ((GAP) == ETH_InterFrameGap_80Bit) || \ + ((GAP) == ETH_InterFrameGap_72Bit) || \ + ((GAP) == ETH_InterFrameGap_64Bit) || \ + ((GAP) == ETH_InterFrameGap_56Bit) || \ + ((GAP) == ETH_InterFrameGap_48Bit) || \ + ((GAP) == ETH_InterFrameGap_40Bit)) + +/** +* @} +*/ + +/** @defgroup ETH_Carrier_Sense +* @{ +*/ +#define ETH_CarrierSense_Enable ((unsigned int)0x00000000) +#define ETH_CarrierSense_Disable ((unsigned int)0x00010000) +#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \ + ((CMD) == ETH_CarrierSense_Disable)) + +/** +* @} +*/ + +/** @defgroup ETH_Speed +* @{ +*/ +#define ETH_Speed_10M ((unsigned int)0x00000000) +#define ETH_Speed_100M ((unsigned int)0x00004000) +#define ETH_Speed_1000M ((unsigned int)0x00008000) +#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \ + ((SPEED) == ETH_Speed_100M))|| \ + ((SPEED) == ETH_Speed_1000M)) + +/** +* @} +*/ + +/** @defgroup ETH_Receive_Own +* @{ +*/ +#define ETH_ReceiveOwn_Enable ((unsigned int)0x00000000) +#define ETH_ReceiveOwn_Disable ((unsigned int)0x00002000) +#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \ + ((CMD) == ETH_ReceiveOwn_Disable)) + +/** +* @} +*/ + +/** @defgroup ETH_Loop_Back_Mode +* @{ +*/ +#define ETH_LoopbackMode_Enable ((unsigned int)0x00001000) +#define ETH_LoopbackMode_Disable ((unsigned int)0x00000000) +#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \ + ((CMD) == ETH_LoopbackMode_Disable)) + +/** +* @} +*/ + +/** @defgroup ETH_Duplex_Mode +* @{ +*/ +#define ETH_Mode_FullDuplex ((unsigned int)0x00000800) +#define ETH_Mode_HalfDuplex ((unsigned int)0x00000000) +#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_Mode_FullDuplex) || \ + ((MODE) == ETH_Mode_HalfDuplex)) + +/** +* @} +*/ + +/** @defgroup ETH_Checksum_Offload +* @{ +*/ +#define ETH_ChecksumOffload_Enable ((unsigned int)0x00000400) +#define ETH_ChecksumOffload_Disable ((unsigned int)0x00000000) +#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_ChecksumOffload_Enable) || \ + ((CMD) == ETH_ChecksumOffload_Disable)) + +/** +* @} +*/ + +/** @defgroup ETH_Retry_Transmission +* @{ +*/ +#define ETH_RetryTransmission_Enable ((unsigned int)0x00000000) +#define ETH_RetryTransmission_Disable ((unsigned int)0x00000200) +#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RetryTransmission_Enable) || \ + ((CMD) == ETH_RetryTransmission_Disable)) + +/** +* @} +*/ + +/** @defgroup ETH_Automatic_Pad_CRC_Strip +* @{ +*/ +#define ETH_AutomaticPadCRCStrip_Enable ((unsigned int)0x00000080) +#define ETH_AutomaticPadCRCStrip_Disable ((unsigned int)0x00000000) +#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AutomaticPadCRCStrip_Enable) || \ + ((CMD) == ETH_AutomaticPadCRCStrip_Disable)) + +/** +* @} +*/ + +/** @defgroup ETH_Back_Off_Limit +* @{ +*/ +#define ETH_BackOffLimit_10 ((unsigned int)0x00000000) +#define ETH_BackOffLimit_8 ((unsigned int)0x00000020) +#define ETH_BackOffLimit_4 ((unsigned int)0x00000040) +#define ETH_BackOffLimit_1 ((unsigned int)0x00000060) +#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BackOffLimit_10) || \ + ((LIMIT) == ETH_BackOffLimit_8) || \ + ((LIMIT) == ETH_BackOffLimit_4) || \ + ((LIMIT) == ETH_BackOffLimit_1)) + +/** +* @} +*/ + +/** @defgroup ETH_Deferral_Check +* @{ +*/ +#define ETH_DeferralCheck_Enable ((unsigned int)0x00000010) +#define ETH_DeferralCheck_Disable ((unsigned int)0x00000000) +#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DeferralCheck_Enable) || \ + ((CMD) == ETH_DeferralCheck_Disable)) + +/** +* @} +*/ + +/** @defgroup ETH_Receive_All +* @{ +*/ +#define ETH_ReceiveAll_Enable ((unsigned int)0x80000000) +#define ETH_ReceiveAll_Disable ((unsigned int)0x00000000) +#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_ReceiveAll_Enable) || \ + ((CMD) == ETH_ReceiveAll_Disable)) + +/** +* @} +*/ + +/** @defgroup ETH_Source_Addr_Filter +* @{ +*/ +#define ETH_SourceAddrFilter_Normal_Enable ((unsigned int)0x00000200) +#define ETH_SourceAddrFilter_Inverse_Enable ((unsigned int)0x00000300) +#define ETH_SourceAddrFilter_Disable ((unsigned int)0x00000000) +#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SourceAddrFilter_Normal_Enable) || \ + ((CMD) == ETH_SourceAddrFilter_Inverse_Enable) || \ + ((CMD) == ETH_SourceAddrFilter_Disable)) + +/** +* @} +*/ + +/** @defgroup ETH_Pass_Control_Frames +* @{ +*/ +#define ETH_PassControlFrames_BlockAll ((unsigned int)0x00000040) /*!< MAC filters all control frames from reaching the application */ +#define ETH_PassControlFrames_ForwardAll ((unsigned int)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */ +#define ETH_PassControlFrames_ForwardPassedAddrFilter ((unsigned int)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */ +#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PassControlFrames_BlockAll) || \ + ((PASS) == ETH_PassControlFrames_ForwardAll) || \ + ((PASS) == ETH_PassControlFrames_ForwardPassedAddrFilter)) + +/** +* @} +*/ + +/** @defgroup ETH_Broadcast_Frames_Reception +* @{ +*/ +#define ETH_BroadcastFramesReception_Enable ((unsigned int)0x00000000) +#define ETH_BroadcastFramesReception_Disable ((unsigned int)0x00000020) +#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BroadcastFramesReception_Enable) || \ + ((CMD) == ETH_BroadcastFramesReception_Disable)) + +/** +* @} +*/ + +/** @defgroup ETH_Destination_Addr_Filter +* @{ +*/ +#define ETH_DestinationAddrFilter_Normal ((unsigned int)0x00000000) +#define ETH_DestinationAddrFilter_Inverse ((unsigned int)0x00000008) +#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DestinationAddrFilter_Normal) || \ + ((FILTER) == ETH_DestinationAddrFilter_Inverse)) + +/** +* @} +*/ + +/** @defgroup ETH_Promiscuous_Mode +* @{ +*/ +#define ETH_PromiscuousMode_Enable ((unsigned int)0x00000001) +#define ETH_PromiscuousMode_Disable ((unsigned int)0x00000000) +#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PromiscuousMode_Enable) || \ + ((CMD) == ETH_PromiscuousMode_Disable)) + +/** +* @} +*/ + +/** @defgroup ETH_Multicast_Frames_Filter +* @{ +*/ +#define ETH_MulticastFramesFilter_PerfectHashTable ((unsigned int)0x00000404) +#define ETH_MulticastFramesFilter_HashTable ((unsigned int)0x00000004) +#define ETH_MulticastFramesFilter_Perfect ((unsigned int)0x00000000) +#define ETH_MulticastFramesFilter_None ((unsigned int)0x00000010) +#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MulticastFramesFilter_PerfectHashTable) || \ + ((FILTER) == ETH_MulticastFramesFilter_HashTable) || \ + ((FILTER) == ETH_MulticastFramesFilter_Perfect) || \ + ((FILTER) == ETH_MulticastFramesFilter_None)) + + +/** +* @} +*/ + +/** @defgroup ETH_Unicast_Frames_Filter +* @{ +*/ +#define ETH_UnicastFramesFilter_PerfectHashTable ((unsigned int)0x00000402) +#define ETH_UnicastFramesFilter_HashTable ((unsigned int)0x00000002) +#define ETH_UnicastFramesFilter_Perfect ((unsigned int)0x00000000) +#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UnicastFramesFilter_PerfectHashTable) || \ + ((FILTER) == ETH_UnicastFramesFilter_HashTable) || \ + ((FILTER) == ETH_UnicastFramesFilter_Perfect)) + +/** +* @} +*/ + +/** @defgroup ETH_Pause_Time +* @{ +*/ +#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF) + +/** +* @} +*/ + +/** @defgroup ETH_Zero_Quanta_Pause +* @{ +*/ +#define ETH_ZeroQuantaPause_Enable ((unsigned int)0x00000000) +#define ETH_ZeroQuantaPause_Disable ((unsigned int)0x00000080) +#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZeroQuantaPause_Enable) || \ + ((CMD) == ETH_ZeroQuantaPause_Disable)) +/** +* @} +*/ + +/** @defgroup ETH_Pause_Low_Threshold +* @{ +*/ +#define ETH_PauseLowThreshold_Minus4 ((unsigned int)0x00000000) /*!< Pause time minus 4 slot times */ +#define ETH_PauseLowThreshold_Minus28 ((unsigned int)0x00000010) /*!< Pause time minus 28 slot times */ +#define ETH_PauseLowThreshold_Minus144 ((unsigned int)0x00000020) /*!< Pause time minus 144 slot times */ +#define ETH_PauseLowThreshold_Minus256 ((unsigned int)0x00000030) /*!< Pause time minus 256 slot times */ +#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PauseLowThreshold_Minus4) || \ + ((THRESHOLD) == ETH_PauseLowThreshold_Minus28) || \ + ((THRESHOLD) == ETH_PauseLowThreshold_Minus144) || \ + ((THRESHOLD) == ETH_PauseLowThreshold_Minus256)) + +/** +* @} +*/ + +/** @defgroup ETH_Unicast_Pause_Frame_Detect +* @{ +*/ +#define ETH_UnicastPauseFrameDetect_Enable ((unsigned int)0x00000008) +#define ETH_UnicastPauseFrameDetect_Disable ((unsigned int)0x00000000) +#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UnicastPauseFrameDetect_Enable) || \ + ((CMD) == ETH_UnicastPauseFrameDetect_Disable)) + +/** +* @} +*/ + +/** @defgroup ETH_Receive_Flow_Control +* @{ +*/ +#define ETH_ReceiveFlowControl_Enable ((unsigned int)0x00000004) +#define ETH_ReceiveFlowControl_Disable ((unsigned int)0x00000000) +#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_ReceiveFlowControl_Enable) || \ + ((CMD) == ETH_ReceiveFlowControl_Disable)) + +/** +* @} +*/ + +/** @defgroup ETH_Transmit_Flow_Control +* @{ +*/ +#define ETH_TransmitFlowControl_Enable ((unsigned int)0x00000002) +#define ETH_TransmitFlowControl_Disable ((unsigned int)0x00000000) +#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TransmitFlowControl_Enable) || \ + ((CMD) == ETH_TransmitFlowControl_Disable)) + +/** +* @} +*/ + +/** @defgroup ETH_VLAN_Tag_Comparison +* @{ +*/ +#define ETH_VLANTagComparison_12Bit ((unsigned int)0x00010000) +#define ETH_VLANTagComparison_16Bit ((unsigned int)0x00000000) +#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTagComparison_12Bit) || \ + ((COMPARISON) == ETH_VLANTagComparison_16Bit)) +#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF) + +/** +* @} +*/ + +/** @defgroup ETH_MAC_Flags +* @{ +*/ +#define ETH_MAC_FLAG_TST ((unsigned int)0x00000200) /*!< Time stamp trigger flag (on MAC) */ +#define ETH_MAC_FLAG_MMCT ((unsigned int)0x00000040) /*!< MMC transmit flag */ +#define ETH_MAC_FLAG_MMCR ((unsigned int)0x00000020) /*!< MMC receive flag */ +#define ETH_MAC_FLAG_MMC ((unsigned int)0x00000010) /*!< MMC flag (on MAC) */ +#define ETH_MAC_FLAG_PMT ((unsigned int)0x00000008) /*!< PMT flag (on MAC) */ +#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ + ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ + ((FLAG) == ETH_MAC_FLAG_PMT)) +/** +* @} +*/ + +/** @defgroup ETH_MAC_Interrupts +* @{ +*/ +#define ETH_MAC_IT_TST ((unsigned int)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */ +#define ETH_MAC_IT_MMCT ((unsigned int)0x00000040) /*!< MMC transmit interrupt */ +#define ETH_MAC_IT_MMCR ((unsigned int)0x00000020) /*!< MMC receive interrupt */ +#define ETH_MAC_IT_MMC ((unsigned int)0x00000010) /*!< MMC interrupt (on MAC) */ +#define ETH_MAC_IT_PMT ((unsigned int)0x00000008) /*!< PMT interrupt (on MAC) */ +#define IS_ETH_MAC_IT(IT) ((((IT) & (unsigned int)0xFFFFFDF7) == 0x00) && ((IT) != 0x00)) +#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ + ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ + ((IT) == ETH_MAC_IT_PMT)) +/** +* @} +*/ + +/** @defgroup ETH_MAC_addresses +* @{ +*/ +#define ETH_MAC_Address0 ((unsigned int)0x00000000) +#define ETH_MAC_Address1 ((unsigned int)0x00000008) +#define ETH_MAC_Address2 ((unsigned int)0x00000010) +#define ETH_MAC_Address3 ((unsigned int)0x00000018) +#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_Address0) || \ + ((ADDRESS) == ETH_MAC_Address1) || \ + ((ADDRESS) == ETH_MAC_Address2) || \ + ((ADDRESS) == ETH_MAC_Address3)) +#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_Address1) || \ + ((ADDRESS) == ETH_MAC_Address2) || \ + ((ADDRESS) == ETH_MAC_Address3)) +/** +* @} +*/ + +/** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames +* @{ +*/ +#define ETH_MAC_AddressFilter_SA ((unsigned int)0x00000000) +#define ETH_MAC_AddressFilter_DA ((unsigned int)0x00000008) +#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_AddressFilter_SA) || \ + ((FILTER) == ETH_MAC_AddressFilter_DA)) +/** +* @} +*/ + +/** @defgroup ETH_MAC_addresses_filter_Mask_bytes +* @{ +*/ +#define ETH_MAC_AddressMask_Byte6 ((unsigned int)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte5 ((unsigned int)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */ +#define ETH_MAC_AddressMask_Byte4 ((unsigned int)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */ +#define ETH_MAC_AddressMask_Byte3 ((unsigned int)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */ +#define ETH_MAC_AddressMask_Byte2 ((unsigned int)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte1 ((unsigned int)0x01000000) /*!< Mask MAC Address low reg bits [70] */ +#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_AddressMask_Byte6) || \ + ((MASK) == ETH_MAC_AddressMask_Byte5) || \ + ((MASK) == ETH_MAC_AddressMask_Byte4) || \ + ((MASK) == ETH_MAC_AddressMask_Byte3) || \ + ((MASK) == ETH_MAC_AddressMask_Byte2) || \ + ((MASK) == ETH_MAC_AddressMask_Byte1)) + +/**--------------------------------------------------------------------------**/ +/** +* @brief Ethernet DMA Descriptors defines +*/ +/**--------------------------------------------------------------------------**/ +/** +* @} +*/ + +/** @defgroup ETH_DMA_Tx_descriptor_flags +* @{ +*/ +#define IS_ETH_DMATxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATxDesc_OWN) || \ + ((FLAG) == ETH_DMATxDesc_IC) || \ + ((FLAG) == ETH_DMATxDesc_LS) || \ + ((FLAG) == ETH_DMATxDesc_FS) || \ + ((FLAG) == ETH_DMATxDesc_DC) || \ + ((FLAG) == ETH_DMATxDesc_DP) || \ + ((FLAG) == ETH_DMATxDesc_TTSE) || \ + ((FLAG) == ETH_DMATxDesc_TER) || \ + ((FLAG) == ETH_DMATxDesc_TCH) || \ + ((FLAG) == ETH_DMATxDesc_TTSS) || \ + ((FLAG) == ETH_DMATxDesc_IHE) || \ + ((FLAG) == ETH_DMATxDesc_ES) || \ + ((FLAG) == ETH_DMATxDesc_JT) || \ + ((FLAG) == ETH_DMATxDesc_FF) || \ + ((FLAG) == ETH_DMATxDesc_PCE) || \ + ((FLAG) == ETH_DMATxDesc_LCA) || \ + ((FLAG) == ETH_DMATxDesc_NC) || \ + ((FLAG) == ETH_DMATxDesc_LCO) || \ + ((FLAG) == ETH_DMATxDesc_EC) || \ + ((FLAG) == ETH_DMATxDesc_VF) || \ + ((FLAG) == ETH_DMATxDesc_CC) || \ + ((FLAG) == ETH_DMATxDesc_ED) || \ + ((FLAG) == ETH_DMATxDesc_UF) || \ + ((FLAG) == ETH_DMATxDesc_DB)) + +/** +* @} +*/ + +/** @defgroup ETH_DMA_Tx_descriptor_segment +* @{ +*/ +#define ETH_DMATxDesc_LastSegment ((unsigned int)0x40000000) /*!< Last Segment */ +#define ETH_DMATxDesc_FirstSegment ((unsigned int)0x20000000) /*!< First Segment */ +#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATxDesc_LastSegment) || \ + ((SEGMENT) == ETH_DMATxDesc_FirstSegment)) + +/** +* @} +*/ + +/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control +* @{ +*/ +#define ETH_DMATxDesc_ChecksumByPass ((unsigned int)0x00000000) /*!< Checksum engine bypass */ +#define ETH_DMATxDesc_ChecksumIPV4Header ((unsigned int)0x00400000) /*!< IPv4 header checksum insertion */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((unsigned int)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((unsigned int)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ +#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATxDesc_ChecksumByPass) || \ + ((CHECKSUM) == ETH_DMATxDesc_ChecksumIPV4Header) || \ + ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPSegment) || \ + ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPFull)) +/** +* @brief ETH DMA Tx Desciptor buffer size +*/ +#define IS_ETH_DMATxDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF) + +/** +* @} +*/ + +/** @defgroup ETH_DMA_Rx_descriptor_flags +* @{ +*/ +#define IS_ETH_DMARxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARxDesc_OWN) || \ + ((FLAG) == ETH_DMARxDesc_AFM) || \ + ((FLAG) == ETH_DMARxDesc_ES) || \ + ((FLAG) == ETH_DMARxDesc_DE) || \ + ((FLAG) == ETH_DMARxDesc_SAF) || \ + ((FLAG) == ETH_DMARxDesc_LE) || \ + ((FLAG) == ETH_DMARxDesc_OE) || \ + ((FLAG) == ETH_DMARxDesc_VLAN) || \ + ((FLAG) == ETH_DMARxDesc_FS) || \ + ((FLAG) == ETH_DMARxDesc_LS) || \ + ((FLAG) == ETH_DMARxDesc_IPV4HCE) || \ + ((FLAG) == ETH_DMARxDesc_LC) || \ + ((FLAG) == ETH_DMARxDesc_FT) || \ + ((FLAG) == ETH_DMARxDesc_RWT) || \ + ((FLAG) == ETH_DMARxDesc_RE) || \ + ((FLAG) == ETH_DMARxDesc_DBE) || \ + ((FLAG) == ETH_DMARxDesc_CE) || \ + ((FLAG) == ETH_DMARxDesc_MAMPCE)) + +/* ETHERNET DMA PTP Rx descriptor extended flags --------------------------------*/ +#define IS_ETH_DMAPTPRxDESC_GET_EXTENDED_FLAG(FLAG) (((FLAG) == ETH_DMAPTPRxDesc_PTPV) || \ + ((FLAG) == ETH_DMAPTPRxDesc_PTPFT) || \ + ((FLAG) == ETH_DMAPTPRxDesc_PTPMT) || \ + ((FLAG) == ETH_DMAPTPRxDesc_IPV6PR) || \ + ((FLAG) == ETH_DMAPTPRxDesc_IPV4PR) || \ + ((FLAG) == ETH_DMAPTPRxDesc_IPCB) || \ + ((FLAG) == ETH_DMAPTPRxDesc_IPPE) || \ + ((FLAG) == ETH_DMAPTPRxDesc_IPHE) || \ + ((FLAG) == ETH_DMAPTPRxDesc_IPPT)) + +/** +* @} +*/ + +/** @defgroup ETH_DMA_Rx_descriptor_buffers_ +* @{ +*/ +#define ETH_DMARxDesc_Buffer1 ((unsigned int)0x00000000) /*!< DMA Rx Desc Buffer1 */ +#define ETH_DMARxDesc_Buffer2 ((unsigned int)0x00000001) /*!< DMA Rx Desc Buffer2 */ +#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARxDesc_Buffer1) || \ + ((BUFFER) == ETH_DMARxDesc_Buffer2)) + +/**--------------------------------------------------------------------------**/ +/** +* @brief Ethernet DMA defines +*/ +/**--------------------------------------------------------------------------**/ +/** +* @} +*/ + +/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame +* @{ +*/ +#define ETH_DropTCPIPChecksumErrorFrame_Enable ((unsigned int)0x00000000) +#define ETH_DropTCPIPChecksumErrorFrame_Disable ((unsigned int)0x04000000) +#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DropTCPIPChecksumErrorFrame_Enable) || \ + ((CMD) == ETH_DropTCPIPChecksumErrorFrame_Disable)) +/** +* @} +*/ + +/** @defgroup ETH_Receive_Store_Forward +* @{ +*/ +#define ETH_ReceiveStoreForward_Enable ((unsigned int)0x02000000) +#define ETH_ReceiveStoreForward_Disable ((unsigned int)0x00000000) +#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_ReceiveStoreForward_Enable) || \ + ((CMD) == ETH_ReceiveStoreForward_Disable)) +/** +* @} +*/ + +/** @defgroup ETH_Flush_Received_Frame +* @{ +*/ +#define ETH_FlushReceivedFrame_Enable ((unsigned int)0x00000000) +#define ETH_FlushReceivedFrame_Disable ((unsigned int)0x01000000) +#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FlushReceivedFrame_Enable) || \ + ((CMD) == ETH_FlushReceivedFrame_Disable)) +/** +* @} +*/ + +/** @defgroup ETH_Transmit_Store_Forward +* @{ +*/ +#define ETH_TransmitStoreForward_Enable ((unsigned int)0x00200000) +#define ETH_TransmitStoreForward_Disable ((unsigned int)0x00000000) +#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TransmitStoreForward_Enable) || \ + ((CMD) == ETH_TransmitStoreForward_Disable)) +/** +* @} +*/ + +/** @defgroup ETH_Transmit_Threshold_Control +* @{ +*/ +#define ETH_TransmitThresholdControl_64Bytes ((unsigned int)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ +#define ETH_TransmitThresholdControl_128Bytes ((unsigned int)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ +#define ETH_TransmitThresholdControl_192Bytes ((unsigned int)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ +#define ETH_TransmitThresholdControl_256Bytes ((unsigned int)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ +#define ETH_TransmitThresholdControl_40Bytes ((unsigned int)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ +#define ETH_TransmitThresholdControl_32Bytes ((unsigned int)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ +#define ETH_TransmitThresholdControl_24Bytes ((unsigned int)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ +#define ETH_TransmitThresholdControl_16Bytes ((unsigned int)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ +#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TransmitThresholdControl_64Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_128Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_192Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_256Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_40Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_32Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_24Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_16Bytes)) +/** +* @} +*/ + +/** @defgroup ETH_Forward_Error_Frames +* @{ +*/ +#define ETH_ForwardErrorFrames_Enable ((unsigned int)0x00000080) +#define ETH_ForwardErrorFrames_Disable ((unsigned int)0x00000000) +#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_ForwardErrorFrames_Enable) || \ + ((CMD) == ETH_ForwardErrorFrames_Disable)) +/** +* @} +*/ + +/** @defgroup ETH_Forward_Undersized_Good_Frames +* @{ +*/ +#define ETH_ForwardUndersizedGoodFrames_Enable ((unsigned int)0x00000040) +#define ETH_ForwardUndersizedGoodFrames_Disable ((unsigned int)0x00000000) +#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_ForwardUndersizedGoodFrames_Enable) || \ + ((CMD) == ETH_ForwardUndersizedGoodFrames_Disable)) + +/** +* @} +*/ + +/** @defgroup ETH_Receive_Threshold_Control +* @{ +*/ +#define ETH_ReceiveThresholdControl_64Bytes ((unsigned int)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ +#define ETH_ReceiveThresholdControl_32Bytes ((unsigned int)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ +#define ETH_ReceiveThresholdControl_96Bytes ((unsigned int)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ +#define ETH_ReceiveThresholdControl_128Bytes ((unsigned int)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ +#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_ReceiveThresholdControl_64Bytes) || \ + ((THRESHOLD) == ETH_ReceiveThresholdControl_32Bytes) || \ + ((THRESHOLD) == ETH_ReceiveThresholdControl_96Bytes) || \ + ((THRESHOLD) == ETH_ReceiveThresholdControl_128Bytes)) +/** +* @} +*/ + +/** @defgroup ETH_Second_Frame_Operate +* @{ +*/ +#define ETH_SecondFrameOperate_Enable ((unsigned int)0x00000004) +#define ETH_SecondFrameOperate_Disable ((unsigned int)0x00000000) +#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SecondFrameOperate_Enable) || \ + ((CMD) == ETH_SecondFrameOperate_Disable)) + +/** +* @} +*/ + +/** @defgroup ETH_Address_Aligned_Beats +* @{ +*/ +#define ETH_AddressAlignedBeats_Enable ((unsigned int)0x02000000) +#define ETH_AddressAlignedBeats_Disable ((unsigned int)0x00000000) +#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_AddressAlignedBeats_Enable) || \ + ((CMD) == ETH_AddressAlignedBeats_Disable)) +/** +* @} +*/ + +/** @defgroup ETH_Fixed_Burst +* @{ +*/ +#define ETH_FixedBurst_Enable ((unsigned int)0x00010000) +#define ETH_FixedBurst_Disable ((unsigned int)0x00000000) +#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FixedBurst_Enable) || \ + ((CMD) == ETH_FixedBurst_Disable)) + +/** +* @} +*/ + +/** @defgroup ETH_Rx_DMA_Burst_Length +* @{ +*/ +#define ETH_RxDMABurstLength_1Beat ((unsigned int)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ +#define ETH_RxDMABurstLength_2Beat ((unsigned int)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ +#define ETH_RxDMABurstLength_4Beat ((unsigned int)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_8Beat ((unsigned int)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_16Beat ((unsigned int)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_32Beat ((unsigned int)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RxDMABurstLength_4xPBL_4Beat ((unsigned int)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_4xPBL_8Beat ((unsigned int)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_4xPBL_16Beat ((unsigned int)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_4xPBL_32Beat ((unsigned int)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RxDMABurstLength_4xPBL_64Beat ((unsigned int)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ +#define ETH_RxDMABurstLength_4xPBL_128Beat ((unsigned int)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ + +#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RxDMABurstLength_1Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_2Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_8Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_16Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_32Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_4Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_8Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_16Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_32Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_64Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_128Beat)) + +/** +* @} +*/ + +/** @defgroup ETH_Tx_DMA_Burst_Length +* @{ +*/ +#define ETH_TxDMABurstLength_1Beat ((unsigned int)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ +#define ETH_TxDMABurstLength_2Beat ((unsigned int)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ +#define ETH_TxDMABurstLength_4Beat ((unsigned int)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_8Beat ((unsigned int)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_16Beat ((unsigned int)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_32Beat ((unsigned int)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TxDMABurstLength_4xPBL_4Beat ((unsigned int)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_4xPBL_8Beat ((unsigned int)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_4xPBL_16Beat ((unsigned int)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_4xPBL_32Beat ((unsigned int)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TxDMABurstLength_4xPBL_64Beat ((unsigned int)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ +#define ETH_TxDMABurstLength_4xPBL_128Beat ((unsigned int)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ + +#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TxDMABurstLength_1Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_2Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_8Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_16Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_32Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_4Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_8Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_16Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_32Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_64Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_128Beat)) +/** +* @brief ETH DMA Descriptor SkipLength +*/ +#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F) + +/** +* @} +*/ + +/** @defgroup ETH_DMA_Arbitration +* @{ +*/ +#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((unsigned int)0x00000000) +#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((unsigned int)0x00004000) +#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((unsigned int)0x00008000) +#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((unsigned int)0x0000C000) +#define ETH_DMAArbitration_RxPriorTx ((unsigned int)0x00000002) +#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_1_1) || \ + ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_2_1) || \ + ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_3_1) || \ + ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_4_1) || \ + ((RATIO) == ETH_DMAArbitration_RxPriorTx)) +/** +* @} +*/ + +/** @defgroup ETH_DMA_Flags +* @{ +*/ +#define ETH_DMA_FLAG_TST ((unsigned int)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_FLAG_PMT ((unsigned int)0x10000000) /*!< PMT interrupt (on DMA) */ +#define ETH_DMA_FLAG_MMC ((unsigned int)0x08000000) /*!< MMC interrupt (on DMA) */ +#define ETH_DMA_FLAG_DataTransferError ((unsigned int)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMA_FLAG_ReadWriteError ((unsigned int)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */ +#define ETH_DMA_FLAG_AccessError ((unsigned int)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */ +#define ETH_DMA_FLAG_NIS ((unsigned int)0x00010000) /*!< Normal interrupt summary flag */ +#define ETH_DMA_FLAG_AIS ((unsigned int)0x00008000) /*!< Abnormal interrupt summary flag */ +#define ETH_DMA_FLAG_ER ((unsigned int)0x00004000) /*!< Early receive flag */ +#define ETH_DMA_FLAG_FBE ((unsigned int)0x00002000) /*!< Fatal bus error flag */ +#define ETH_DMA_FLAG_ET ((unsigned int)0x00000400) /*!< Early transmit flag */ +#define ETH_DMA_FLAG_RWT ((unsigned int)0x00000200) /*!< Receive watchdog timeout flag */ +#define ETH_DMA_FLAG_RPS ((unsigned int)0x00000100) /*!< Receive process stopped flag */ +#define ETH_DMA_FLAG_RBU ((unsigned int)0x00000080) /*!< Receive buffer unavailable flag */ +#define ETH_DMA_FLAG_R ((unsigned int)0x00000040) /*!< Receive flag */ +#define ETH_DMA_FLAG_TU ((unsigned int)0x00000020) /*!< Underflow flag */ +#define ETH_DMA_FLAG_RO ((unsigned int)0x00000010) /*!< Overflow flag */ +#define ETH_DMA_FLAG_TJT ((unsigned int)0x00000008) /*!< Transmit jabber timeout flag */ +#define ETH_DMA_FLAG_TBU ((unsigned int)0x00000004) /*!< Transmit buffer unavailable flag */ +#define ETH_DMA_FLAG_TPS ((unsigned int)0x00000002) /*!< Transmit process stopped flag */ +#define ETH_DMA_FLAG_T ((unsigned int)0x00000001) /*!< Transmit flag */ + +#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (unsigned int)0xFFFE1800) == 0x00) && ((FLAG) != 0x00)) +#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ + ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DataTransferError) || \ + ((FLAG) == ETH_DMA_FLAG_ReadWriteError) || ((FLAG) == ETH_DMA_FLAG_AccessError) || \ + ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ + ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ + ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ + ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ + ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ + ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ + ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ + ((FLAG) == ETH_DMA_FLAG_T)) +/** +* @} +*/ + +/** @defgroup ETH_DMA_Interrupts +* @{ +*/ +#define ETH_DMA_IT_TST ((unsigned int)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_IT_PMT ((unsigned int)0x10000000) /*!< PMT interrupt (on DMA) */ +#define ETH_DMA_IT_MMC ((unsigned int)0x08000000) /*!< MMC interrupt (on DMA) */ +#define ETH_DMA_IT_NIS ((unsigned int)0x00010000) /*!< Normal interrupt summary */ +#define ETH_DMA_IT_AIS ((unsigned int)0x00008000) /*!< Abnormal interrupt summary */ +#define ETH_DMA_IT_ER ((unsigned int)0x00004000) /*!< Early receive interrupt */ +#define ETH_DMA_IT_FBE ((unsigned int)0x00002000) /*!< Fatal bus error interrupt */ +#define ETH_DMA_IT_ET ((unsigned int)0x00000400) /*!< Early transmit interrupt */ +#define ETH_DMA_IT_RWT ((unsigned int)0x00000200) /*!< Receive watchdog timeout interrupt */ +#define ETH_DMA_IT_RPS ((unsigned int)0x00000100) /*!< Receive process stopped interrupt */ +#define ETH_DMA_IT_RBU ((unsigned int)0x00000080) /*!< Receive buffer unavailable interrupt */ +#define ETH_DMA_IT_R ((unsigned int)0x00000040) /*!< Receive interrupt */ +#define ETH_DMA_IT_TU ((unsigned int)0x00000020) /*!< Underflow interrupt */ +#define ETH_DMA_IT_RO ((unsigned int)0x00000010) /*!< Overflow interrupt */ +#define ETH_DMA_IT_TJT ((unsigned int)0x00000008) /*!< Transmit jabber timeout interrupt */ +#define ETH_DMA_IT_TBU ((unsigned int)0x00000004) /*!< Transmit buffer unavailable interrupt */ +#define ETH_DMA_IT_TPS ((unsigned int)0x00000002) /*!< Transmit process stopped interrupt */ +#define ETH_DMA_IT_T ((unsigned int)0x00000001) /*!< Transmit interrupt */ + +#define IS_ETH_DMA_IT(IT) ((((IT) & (unsigned int)0xFFFE1800) == 0x00) && ((IT) != 0x00)) +#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ + ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ + ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ + ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ + ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ + ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ + ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ + ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ + ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) + +/** +* @} +*/ + +/** @defgroup ETH_DMA_transmit_process_state_ +* @{ +*/ +#define ETH_DMA_TransmitProcess_Stopped ((unsigned int)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */ +#define ETH_DMA_TransmitProcess_Fetching ((unsigned int)0x00100000) /*!< Running - fetching the Tx descriptor */ +#define ETH_DMA_TransmitProcess_Waiting ((unsigned int)0x00200000) /*!< Running - waiting for status */ +#define ETH_DMA_TransmitProcess_Reading ((unsigned int)0x00300000) /*!< Running - reading the data from host memory */ +#define ETH_DMA_TransmitProcess_Suspended ((unsigned int)0x00600000) /*!< Suspended - Tx Descriptor unavailable */ +#define ETH_DMA_TransmitProcess_Closing ((unsigned int)0x00700000) /*!< Running - closing Rx descriptor */ + +/** +* @} +*/ + + +/** @defgroup ETH_DMA_receive_process_state_ +* @{ +*/ +#define ETH_DMA_ReceiveProcess_Stopped ((unsigned int)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */ +#define ETH_DMA_ReceiveProcess_Fetching ((unsigned int)0x00020000) /*!< Running - fetching the Rx descriptor */ +#define ETH_DMA_ReceiveProcess_Waiting ((unsigned int)0x00060000) /*!< Running - waiting for packet */ +#define ETH_DMA_ReceiveProcess_Suspended ((unsigned int)0x00080000) /*!< Suspended - Rx Descriptor unavailable */ +#define ETH_DMA_ReceiveProcess_Closing ((unsigned int)0x000A0000) /*!< Running - closing descriptor */ +#define ETH_DMA_ReceiveProcess_Queuing ((unsigned int)0x000E0000) /*!< Running - queuing the receive frame into host memory */ + +/** +* @} +*/ + +/** @defgroup ETH_DMA_overflow_ +* @{ +*/ +#define ETH_DMA_Overflow_RxFIFOCounter ((unsigned int)0x10000000) /*!< Overflow bit for FIFO overflow counter */ +#define ETH_DMA_Overflow_MissedFrameCounter ((unsigned int)0x00010000) /*!< Overflow bit for missed frame counter */ +#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_Overflow_RxFIFOCounter) || \ + ((OVERFLOW) == ETH_DMA_Overflow_MissedFrameCounter)) + +/**--------------------------------------------------------------------------**/ +/** +* @brief Ethernet PMT defines +*/ +/**--------------------------------------------------------------------------**/ +/** +* @} +*/ + +/** @defgroup ETH_PMT_Flags +* @{ +*/ +#define ETH_PMT_FLAG_WUFFRPR ((unsigned int)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */ +#define ETH_PMT_FLAG_WUFR ((unsigned int)0x00000040) /*!< Wake-Up Frame Received */ +#define ETH_PMT_FLAG_MPR ((unsigned int)0x00000020) /*!< Magic Packet Received */ +#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ + ((FLAG) == ETH_PMT_FLAG_MPR)) + +/**--------------------------------------------------------------------------**/ +/** +* @brief Ethernet MMC defines +*/ +/**--------------------------------------------------------------------------**/ +/** +* @} +*/ + +/** @defgroup ETH_MMC_Tx_Interrupts +* @{ +*/ +#define ETH_MMC_IT_TGF ((unsigned int)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFMSC ((unsigned int)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFSC ((unsigned int)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */ + +/** +* @} +*/ + +/** @defgroup ETH_MMC_Rx_Interrupts +* @{ +*/ +#define ETH_MMC_IT_RGUF ((unsigned int)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMC_IT_RFAE ((unsigned int)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */ +#define ETH_MMC_IT_RFCE ((unsigned int)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */ +#define IS_ETH_MMC_IT(IT) (((((IT) & (unsigned int)0xFFDF3FFF) == 0x00) || (((IT) & (unsigned int)0xEFFDFF9F) == 0x00)) && \ + ((IT) != 0x00)) +#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ + ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ + ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) +/** +* @} +*/ + +/** @defgroup ETH_MMC_Registers +* @{ +*/ +#define ETH_MMCCR ((unsigned int)0x00000100) /*!< MMC CR register */ +#define ETH_MMCRIR ((unsigned int)0x00000104) /*!< MMC RIR register */ +#define ETH_MMCTIR ((unsigned int)0x00000108) /*!< MMC TIR register */ +#define ETH_MMCRIMR ((unsigned int)0x0000010C) /*!< MMC RIMR register */ +#define ETH_MMCTIMR ((unsigned int)0x00000110) /*!< MMC TIMR register */ +#define ETH_MMCTGFSCCR ((unsigned int)0x0000014C) /*!< MMC TGFSCCR register */ +#define ETH_MMCTGFMSCCR ((unsigned int)0x00000150) /*!< MMC TGFMSCCR register */ +#define ETH_MMCTGFCR ((unsigned int)0x00000168) /*!< MMC TGFCR register */ +#define ETH_MMCRFCECR ((unsigned int)0x00000194) /*!< MMC RFCECR register */ +#define ETH_MMCRFAECR ((unsigned int)0x00000198) /*!< MMC RFAECR register */ +#define ETH_MMCRGUFCR ((unsigned int)0x000001C4) /*!< MMC RGUFCR register */ + +/** +* @brief ETH MMC registers +*/ +#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \ + ((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \ + ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \ + ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \ + ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \ + ((REG) == ETH_MMCRGUFCR)) + +/**--------------------------------------------------------------------------**/ +/** +* @brief Ethernet PTP defines +*/ +/**--------------------------------------------------------------------------**/ +/** +* @} +*/ + +/** @defgroup ETH_PTP_time_update_method +* @{ +*/ +#define ETH_PTP_FineUpdate ((unsigned int)0x00000001) /*!< Fine Update method */ +#define ETH_PTP_CoarseUpdate ((unsigned int)0x00000000) /*!< Coarse Update method */ +#define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FineUpdate) || \ + ((UPDATE) == ETH_PTP_CoarseUpdate)) + +/** +* @} +*/ + + +/** @defgroup ETH_PTP_Flags +* @{ +*/ +#define ETH_PTP_FLAG_TSARU ((unsigned int)0x00000020) /*!< Addend Register Update */ +#define ETH_PTP_FLAG_TSITE ((unsigned int)0x00000010) /*!< Time Stamp Interrupt Trigger */ +#define ETH_PTP_FLAG_TSSTU ((unsigned int)0x00000008) /*!< Time Stamp Update */ +#define ETH_PTP_FLAG_TSSTI ((unsigned int)0x00000004) /*!< Time Stamp Initialize */ + +#define ETH_PTP_FLAG_TSTTR ((unsigned int)0x10000002) /* Time stamp target time reached */ +#define ETH_PTP_FLAG_TSSO ((unsigned int)0x10000001) /* Time stamp seconds overflow */ + +#define IS_ETH_PTP_GET_FLAG(FLAG) (((FLAG) == ETH_PTP_FLAG_TSARU) || \ + ((FLAG) == ETH_PTP_FLAG_TSITE) || \ + ((FLAG) == ETH_PTP_FLAG_TSSTU) || \ + ((FLAG) == ETH_PTP_FLAG_TSSTI) || \ + ((FLAG) == ETH_PTP_FLAG_TSTTR) || \ + ((FLAG) == ETH_PTP_FLAG_TSSO)) + +/** +* @brief ETH PTP subsecond increment +*/ +#define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF) + +/** +* @} +*/ + + +/** @defgroup ETH_PTP_time_sign +* @{ +*/ +#define ETH_PTP_PositiveTime ((unsigned int)0x00000000) /*!< Positive time value */ +#define ETH_PTP_NegativeTime ((unsigned int)0x80000000) /*!< Negative time value */ +#define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_PositiveTime) || \ + ((SIGN) == ETH_PTP_NegativeTime)) + +/** +* @brief ETH PTP time stamp low update +*/ +#define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF) + +/** +* @brief ETH PTP registers +*/ +#define ETH_PTPTSCR ((unsigned int)0x00000700) /*!< PTP TSCR register */ +#define ETH_PTPSSIR ((unsigned int)0x00000704) /*!< PTP SSIR register */ +#define ETH_PTPTSHR ((unsigned int)0x00000708) /*!< PTP TSHR register */ +#define ETH_PTPTSLR ((unsigned int)0x0000070C) /*!< PTP TSLR register */ +#define ETH_PTPTSHUR ((unsigned int)0x00000710) /*!< PTP TSHUR register */ +#define ETH_PTPTSLUR ((unsigned int)0x00000714) /*!< PTP TSLUR register */ +#define ETH_PTPTSAR ((unsigned int)0x00000718) /*!< PTP TSAR register */ +#define ETH_PTPTTHR ((unsigned int)0x0000071C) /*!< PTP TTHR register */ +#define ETH_PTPTTLR ((unsigned int)0x00000720) /* PTP TTLR register */ + +#define ETH_PTPTSSR ((unsigned int)0x00000728) /* PTP TSSR register */ + +#define IS_ETH_PTP_REGISTER(REG) (((REG) == ETH_PTPTSCR) || ((REG) == ETH_PTPSSIR) || \ + ((REG) == ETH_PTPTSHR) || ((REG) == ETH_PTPTSLR) || \ + ((REG) == ETH_PTPTSHUR) || ((REG) == ETH_PTPTSLUR) || \ + ((REG) == ETH_PTPTSAR) || ((REG) == ETH_PTPTTHR) || \ + ((REG) == ETH_PTPTTLR) || ((REG) == ETH_PTPTSSR)) + +/** +* @brief ETHERNET PTP clock +*/ +#define ETH_PTP_OrdinaryClock ((unsigned int)0x00000000) /* Ordinary Clock */ +#define ETH_PTP_BoundaryClock ((unsigned int)0x00010000) /* Boundary Clock */ +#define ETH_PTP_EndToEndTransparentClock ((unsigned int)0x00020000) /* End To End Transparent Clock */ +#define ETH_PTP_PeerToPeerTransparentClock ((unsigned int)0x00030000) /* Peer To Peer Transparent Clock */ + +#define IS_ETH_PTP_TYPE_CLOCK(CLOCK) (((CLOCK) == ETH_PTP_OrdinaryClock) || \ + ((CLOCK) == ETH_PTP_BoundaryClock) || \ + ((CLOCK) == ETH_PTP_EndToEndTransparentClock) || \ + ((CLOCK) == ETH_PTP_PeerToPeerTransparentClock)) +/** +* @brief ETHERNET snapshot +*/ +#define ETH_PTP_SnapshotMasterMessage ((unsigned int)0x00008000) /* Time stamp snapshot for message relevant to master enable */ +#define ETH_PTP_SnapshotEventMessage ((unsigned int)0x00004000) /* Time stamp snapshot for event message enable */ +#define ETH_PTP_SnapshotIPV4Frames ((unsigned int)0x00002000) /* Time stamp snapshot for IPv4 frames enable */ +#define ETH_PTP_SnapshotIPV6Frames ((unsigned int)0x00001000) /* Time stamp snapshot for IPv6 frames enable */ +#define ETH_PTP_SnapshotPTPOverEthernetFrames ((unsigned int)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */ +#define ETH_PTP_SnapshotAllReceivedFrames ((unsigned int)0x00000100) /* Time stamp snapshot for all received frames enable */ + +#define IS_ETH_PTP_SNAPSHOT(SNAPSHOT) (((SNAPSHOT) == ETH_PTP_SnapshotMasterMessage) || \ + ((SNAPSHOT) == ETH_PTP_SnapshotEventMessage) || \ + ((SNAPSHOT) == ETH_PTP_SnapshotIPV4Frames) || \ + ((SNAPSHOT) == ETH_PTP_SnapshotIPV6Frames) || \ + ((SNAPSHOT) == ETH_PTP_SnapshotPTPOverEthernetFrames) || \ + ((SNAPSHOT) == ETH_PTP_SnapshotAllReceivedFrames)) + +/** +* @} +*/ +/* ETHERNET MAC address offsets */ +#define ETH_MAC_ADDR_HBASE (ETH_BASE + 0x40) /* ETHERNET MAC address high offset */ +#define ETH_MAC_ADDR_LBASE (ETH_BASE + 0x44) /* ETHERNET MAC address low offset */ + +/* ETHERNET MACMIIAR register Mask */ +#define MACMIIAR_CR_MASK ((unsigned int)0xFFFFFFE3) + +/* ETHERNET MACCR register Mask */ +#define MACCR_CLEAR_MASK ((unsigned int)0xFF20810F) + +/* ETHERNET MACFCR register Mask */ +#define MACFCR_CLEAR_MASK ((unsigned int)0x0000FF41) + + +/* ETHERNET DMAOMR register Mask */ +#define DMAOMR_CLEAR_MASK ((unsigned int)0xF8DE3F23) + + +/* ETHERNET Remote Wake-up frame register length */ +#define ETH_WAKEUP_REGISTER_LENGTH 8 + +/* ETHERNET Missed frames counter Shift */ +#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17 + +/* ETHERNET DMA Tx descriptors Collision Count Shift */ +#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3 + +/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ +#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16 + +/* ETHERNET DMA Rx descriptors Frame Length Shift */ +#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16 + +/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ +#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16 + +/* ETHERNET errors */ +#define ETH_ERROR ((unsigned int)0) +#define ETH_SUCCESS ((unsigned int)1) + +#endif +/** +* @} +*/ +void ETH_SoftwareReset(void); +void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT); +void ETH_StructInit(ETH_InitTypeDef *ETH_InitStruct); +void RGMII_TXC_Delay(uint8_t clock_polarity,uint8_t delay_time); +uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg); +void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState); +uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue); +void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount); +void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); + +#ifdef __cplusplus +} +#endif + + diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_gpio.h b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_gpio.h new file mode 100644 index 000000000..ddb5235ad --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_gpio.h @@ -0,0 +1,144 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : CH56x_gpio.h +* Author : WCH +* Version : V1.0 +* Date : 2020/07/31 +* Description : +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + + +#ifndef __CH56x_GPIO_H__ +#define __CH56x_GPIO_H__ + +#ifdef __cplusplus + extern "C" { +#endif + + +#define GPIO_Pin_0 (0x00000001) /*!< Pin 0 selected */ +#define GPIO_Pin_1 (0x00000002) /*!< Pin 1 selected */ +#define GPIO_Pin_2 (0x00000004) /*!< Pin 2 selected */ +#define GPIO_Pin_3 (0x00000008) /*!< Pin 3 selected */ +#define GPIO_Pin_4 (0x00000010) /*!< Pin 4 selected */ +#define GPIO_Pin_5 (0x00000020) /*!< Pin 5 selected */ +#define GPIO_Pin_6 (0x00000040) /*!< Pin 6 selected */ +#define GPIO_Pin_7 (0x00000080) /*!< Pin 7 selected */ +#define GPIO_Pin_8 (0x00000100) /*!< Pin 8 selected */ +#define GPIO_Pin_9 (0x00000200) /*!< Pin 9 selected */ +#define GPIO_Pin_10 (0x00000400) /*!< Pin 10 selected */ +#define GPIO_Pin_11 (0x00000800) /*!< Pin 11 selected */ +#define GPIO_Pin_12 (0x00001000) /*!< Pin 12 selected */ +#define GPIO_Pin_13 (0x00002000) /*!< Pin 13 selected */ +#define GPIO_Pin_14 (0x00004000) /*!< Pin 14 selected */ +#define GPIO_Pin_15 (0x00008000) /*!< Pin 15 selected */ +#define GPIO_Pin_16 (0x00010000) /*!< Pin 16 selected */ +#define GPIO_Pin_17 (0x00020000) /*!< Pin 17 selected */ +#define GPIO_Pin_18 (0x00040000) /*!< Pin 18 selected */ +#define GPIO_Pin_19 (0x00080000) /*!< Pin 19 selected */ +#define GPIO_Pin_20 (0x00100000) /*!< Pin 20 selected */ +#define GPIO_Pin_21 (0x00200000) /*!< Pin 21 selected */ +#define GPIO_Pin_22 (0x00400000) /*!< Pin 22 selected */ +#define GPIO_Pin_23 (0x00800000) /*!< Pin 23 selected */ +#define GPIO_Pin_24 (0x01000000) /*!< PinB23 selected */ +#define GPIO_Pin_All (0xFFFFFFFF) /*!< All pins selected */ + + +/** + * @brief GPIO mode structure configuration + */ +typedef enum +{ + GPIO_ModeIN_Floating, //floating input + GPIO_ModeIN_PU_NSMT, + GPIO_ModeIN_PD_NSMT, + GPIO_ModeIN_PU_SMT, + GPIO_ModeIN_PD_SMT, + GPIO_Slowascent_PP_8mA, + GPIO_Slowascent_PP_16mA, + GPIO_Highspeed_PP_8mA, + GPIO_Highspeed_PP_16mA, + GPIO_ModeOut_OP_8mA, + GPIO_ModeOut_OP_16mA, +}GPIOModeTypeDef; + + +/** + * @brief GPIO interrupt structure configuration + */ +typedef enum +{ + GPIO_ITMode_LowLevel, //Low level trigger + GPIO_ITMode_HighLevel, //High level trigger + GPIO_ITMode_FallEdge, //Falling edge trigger + GPIO_ITMode_RiseEdge, //Rising edge trigger + +}GPIOITModeTpDef; + + +/** + * @brief GPIO MCO structure configuration + */ +typedef enum +{ + MCO_125 = 0, + MCO_25 = 4, + MCO_2d5 = 0xC, +}MCOMode; + +void GPIOA_ModeCfg( UINT32 pin, GPIOModeTypeDef mode ); /* GPIOA port pin mode configuration */ +void GPIOB_ModeCfg( UINT32 pin, GPIOModeTypeDef mode ); /* GPIOB port pin mode configuration */ +#define GPIOA_ResetBits( pin ) (R32_PA_CLR |= pin) /* GPIOA port pin output set low */ +#define GPIOA_SetBits( pin ) (R32_PA_OUT |= pin) /* GPIOA port pin output set high */ +#define GPIOB_ResetBits( pin ) (R32_PB_CLR |= pin) /* GPIOB port pin output set low */ +#define GPIOB_SetBits( pin ) (R32_PB_OUT |= pin) /* GPIOB port pin output set high */ +#define GPIOA_InverseBits( pin ) (R32_PA_OUT ^= pin) /* GPIOA port pin output level flip */ +#define GPIOB_InverseBits( pin ) (R32_PB_OUT ^= pin) /* GPIOB port pin output level flip */ +#define GPIOA_ReadPort() (R32_PA_PIN) /* The 32-bit data returned by the GPIOA port, the lower 16 bits are valid */ +#define GPIOB_ReadPort() (R32_PB_PIN) /* The 32-bit data returned by the GPIOB port, the lower 24 bits are valid */ +#define GPIOA_ReadPortPin( pin ) (R32_PA_PIN&pin) /* GPIOA port pin status, 0-pin low level, (!0)-pin high level */ +#define GPIOB_ReadPortPin( pin ) (R32_PB_PIN&pin) /* GPIOB port pin status, 0-pin low level, (!0)-pin high level */ + +void GPIOA_ITModeCfg( UINT32 pin, GPIOITModeTpDef mode ); /* GPIOA pin interrupt mode configuration */ +void GPIOB_ITModeCfg( UINT32 pin, GPIOITModeTpDef mode ); /* GPIOB pin interrupt mode configuration */ +#define GPIOA_ReadITFlagPort() (R8_GPIO_INT_FLAG) /* Read GPIOA port interrupt flag status */ +#define GPIOB_ReadITFlagPort() (R8_GPIO_INT_FLAG) /* Read GPIOB port interrupt flag status */ + +/*************************************Read Interrupt Bit Flag************************************/ +#define GPIOA_2_ReadITFlagBit( ) (R8_GPIO_INT_FLAG & 0x01) /* Read GPIOA port pin interrupt flag status */ +#define GPIOA_3_ReadITFlagBit( ) (R8_GPIO_INT_FLAG & 0x02) +#define GPIOA_4_ReadITFlagBit( ) (R8_GPIO_INT_FLAG & 0x04) + +#define GPIOB_3_ReadITFlagBit( ) (R8_GPIO_INT_FLAG & 0x08) /* Read GPIOB port pin interrupt flag status */ +#define GPIOB_4_ReadITFlagBit( ) (R8_GPIO_INT_FLAG & 0x10) +#define GPIOB_11_ReadITFlagBit( ) (R8_GPIO_INT_FLAG & 0x20) +#define GPIOB_12_ReadITFlagBit( ) (R8_GPIO_INT_FLAG & 0x40) +#define GPIOB_15_ReadITFlagBit( ) (R8_GPIO_INT_FLAG & 0x80) + + +/*************************************Clear Interrupt Bit Flag************************************/ +#define GPIOA_2_ClearITFlagBit( ) (R8_GPIO_INT_FLAG = 0x01) /* Clear the GPIOA port pin interrupt flag status */ +#define GPIOA_3_ClearITFlagBit( ) (R8_GPIO_INT_FLAG = 0x02) +#define GPIOA_4_ClearITFlagBit( ) (R8_GPIO_INT_FLAG = 0x04) + +#define GPIOB_3_ClearITFlagBit( ) (R8_GPIO_INT_FLAG = 0x08) /* Clear the GPIOB port pin interrupt flag status */ +#define GPIOB_4_ClearITFlagBit( ) (R8_GPIO_INT_FLAG = 0x10) +#define GPIOB_11_ClearITFlagBit( ) (R8_GPIO_INT_FLAG = 0x20) +#define GPIOB_12_ClearITFlagBit( ) (R8_GPIO_INT_FLAG = 0x40) +#define GPIOB_15_ClearITFlagBit( ) (R8_GPIO_INT_FLAG = 0x80) + + + +void GPIOPinRemap( UINT8 s, UINT16 perph ); /* Peripheral Function Pin Mapping */ +void GPIOMco( UINT8 s, UINT16 freq ); /* MCO function */ + + + +#ifdef __cplusplus +} +#endif + +#endif // __CH56x_GPIO_H__ diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_hspi.h b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_hspi.h new file mode 100644 index 000000000..d01c1285e --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_hspi.h @@ -0,0 +1,43 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : CH56x_hspi.h +* Author : WCH +* Version : V1.0 +* Date : 2020/07/31 +* Description : +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + + +#ifndef __CH56x_HSPI_H__ +#define __CH56x_HSPI_H__ + +#ifdef __cplusplus + extern "C" { +#endif + + +/** + * @brief HSPI Mode + */ +typedef enum +{ + DOWN_Mode = 0, + UP_Mode, +}HSPI_ModeTypeDef; + + + +void HSPI_Mode( UINT8 s, HSPI_ModeTypeDef i); +void HSPI_INTCfg( UINT8 s, UINT8 i ); + + + +#ifdef __cplusplus +} +#endif + +#endif // __CH56x_HSPI_H__ + diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_pwm.h b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_pwm.h new file mode 100644 index 000000000..c608439f7 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_pwm.h @@ -0,0 +1,70 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : CH56x_pwm.h +* Author : WCH +* Version : V1.0 +* Date : 2020/07/31 +* Description : +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + + +#ifndef __CH56x_PWM_H__ +#define __CH56x_PWM_H__ + +#ifdef __cplusplus + extern "C" { +#endif + + +/** + * @brief channel of PWM define + */ +#define CH_PWM0 0x01 // PWM0 channel +#define CH_PWM1 0x02 // PWM1 channel +#define CH_PWM2 0x04 // PWM2 channel +#define CH_PWM3 0x08 // PWM3 channel + + +/** + * @brief channel of PWM define + */ +typedef enum +{ + High_Level = 0, //Default low level, high level is active + Low_Level, //Default high level, low level active +}PWMX_PolarTypeDef; + + +/** + * @brief Configuration PWM0_3 Cycle size + */ +typedef enum +{ + PWMX_Cycle_256 = 0, //256 PWMX cycles + PWMX_Cycle_255, //255 PWMX cycles + +}PWMX_CycleTypeDef; + + +#define PWMX_CLKCfg( d ) (R8_PWM_CLOCK_DIV=d) //PWM Reference Clock Configuration +void PWMX_CycleCfg( PWMX_CycleTypeDef cyc ); //PWM output waveform period configuration + +#define PWM0_ActDataWidth( d ) (R8_PWM0_DATA = d) //PWM0 effective data pulse width +#define PWM1_ActDataWidth( d ) (R8_PWM1_DATA = d) //PWM1 effective data pulse width +#define PWM2_ActDataWidth( d ) (R8_PWM2_DATA = d) //PWM2 effective data pulse width +#define PWM3_ActDataWidth( d ) (R8_PWM3_DATA = d) //PWM3 effective data pulse width + +//Duty cycle = data valid width/waveform period +void PWMX_ACTOUT( UINT8 ch, UINT8 da, PWMX_PolarTypeDef pr, UINT8 s); //PWM0-3 output waveform configuration + + + +#ifdef __cplusplus +} +#endif + +#endif // __CH56x_PWM_H__ + diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_pwr.h b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_pwr.h new file mode 100644 index 000000000..6662b1fab --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_pwr.h @@ -0,0 +1,59 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : CH56x_pwr.h +* Author : WCH +* Version : V1.0 +* Date : 2020/07/31 +* Description : +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + + +#ifndef __CH56x_PWR_H__ +#define __CH56x_PWR_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/** + * @brief Peripher CLK control bit define + */ +#define BIT_SLP_CLK_TMR0 RB_SLP_CLK_TMR0 /*!< TMR0 peripher clk bit */ +#define BIT_SLP_CLK_TMR1 RB_SLP_CLK_TMR1 /*!< TMR1 peripher clk bit */ +#define BIT_SLP_CLK_TMR2 RB_SLP_CLK_TMR2 /*!< TMR2 peripher clk bit */ +#define BIT_SLP_CLK_PWMX RB_SLP_CLK_PWMX /*!< PWMX peripher clk bit */ +#define BIT_SLP_CLK_UART0 RB_SLP_CLK_UART0 /*!< UART0 peripher clk bit */ +#define BIT_SLP_CLK_UART1 RB_SLP_CLK_UART1 /*!< UART1 peripher clk bit */ +#define BIT_SLP_CLK_UART2 RB_SLP_CLK_UART2 /*!< UART2 peripher clk bit */ +#define BIT_SLP_CLK_UART3 RB_SLP_CLK_UART3 /*!< UART3 peripher clk bit */ +#define BIT_SLP_CLK_SPI0 RB_SLP_CLK_SPI0 /*!< SPI0 peripher clk bit */ +#define BIT_SLP_CLK_SPI1 RB_SLP_CLK_SPI1 /*!< SPI1 peripher clk bit */ +#define BIT_SLP_CLK_EMMC RB_SLP_CLK_EMMC /*!< EMMC peripher clk bit */ +#define BIT_SLP_CLK_HSPI RB_SLP_CLK_HSPI /*!< HSPI peripher clk bit */ +#define BIT_SLP_CLK_USBHS RB_SLP_CLK_USBHS /*!< USBHS peripher clk bit */ +#define BIT_SLP_CLK_USBSS RB_SLP_CLK_USBSS /*!< USBSS peripher clk bit */ +#define BIT_SLP_CLK_SERD RB_SLP_CLK_SERD /*!< SERD peripher clk bit */ +#define BIT_SLP_CLK_DVP RB_SLP_CLK_DVP /*!< DVP peripher clk bit */ +#define BIT_SLP_CLK_ETH RB_SLP_CLK_ETH /*!< ETH peripher clk bit */ +#define BIT_SLP_CLK_ECDC RB_SLP_CLK_ECDC /*!< ECDC peripher clk bit */ + + +void PWR_PeriphClkCfg( UINT8 s, UINT16 perph ); /* Peripheral Clock Control Bits */ +void PWR_PeriphWakeUpCfg( UINT8 s, UINT16 perph ); /* Sleep wakeup source configuration */ +void LowPower_Idle( void ); /* Low power consumption - IDLE mode Execute WFI*/ +void LowPower_Idle_WFE( void ); /* Low power consumption - IDLE mode Execute WFE*/ +void LowPower_Halt( void ); /* Low power consumption - Halt mode Execute WFI*/ +void LowPower_Halt_WFE( void ); /* Low power consumption - Halt mode Execute WFE*/ +void LowPower_Sleep( void ); /* Low power consumption - Sleep mode Execute WFI*/ +void LowPower_Sleep_WFE( void ); /* Low power consumption - Sleep mode Execute WFE*/ + + +#ifdef __cplusplus +} +#endif + +#endif // __CH56x_PWR_H__ + diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_spi.h b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_spi.h new file mode 100644 index 000000000..6bd0b090b --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_spi.h @@ -0,0 +1,118 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : CH56x_spi.h +* Author : WCH +* Version : V1.0 +* Date : 2020/07/31 +* Description : +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + + +#ifndef __CH56x_SPI_H__ +#define __CH56x_SPI_H__ + +#ifdef __cplusplus + extern "C" { +#endif + + +/** + * @brief SPI0 interrupt bit define + */ +#define SPI0_IT_FST_BYTE RB_SPI_IE_FST_BYTE +#define SPI0_IT_FIFO_OV RB_SPI_IE_FIFO_OV +#define SPI0_IT_DMA_END RB_SPI_IE_DMA_END +#define SPI0_IT_FIFO_HF RB_SPI_IE_FIFO_HF +#define SPI0_IT_BYTE_END RB_SPI_IE_BYTE_END +#define SPI0_IT_CNT_END RB_SPI_IE_CNT_END + + + +/** + * @brief Configuration data mode + */ +typedef enum +{ + Mode0_LowBitINFront = 0, + Mode0_HighBitINFront, + Mode3_LowBitINFront, + Mode3_HighBitINFront, +}ModeBitOrderTypeDef; + + +/** + * @brief Configuration SPI slave mode + */ +typedef enum +{ +Mode_DataStream = 0, +Mose_FirstCmd, +}Slave_ModeTypeDef; + + +/**************** SPI0 */ +void SPI0_MasterDefInit( void ); +void SPI0_DataMode( ModeBitOrderTypeDef m ); + +void SPI0_MasterSendByte( UINT8 d ); +UINT8 SPI0_MasterRecvByte( void ); + +void SPI0_MasterTrans( UINT8 *pbuf, UINT16 len ); +void SPI0_MasterRecv( UINT8 *pbuf, UINT16 len ); + +void SPI0_MasterDMATrans( PUINT8 pbuf, UINT16 len); +void SPI0_MasterDMARecv( PUINT8 pbuf, UINT16 len); + + +void SPI0_SlaveInit( void ); +#define SetFirst0Data(d) (R8_SPI0_SLAVE_PRE = d) +void SPI0_SlaveSendByte( UINT8 d ); +UINT8 SPI0_SlaveRecvByte( void ); + +void SPI0_SlaveTrans( UINT8 *pbuf, UINT16 len ); +void SPI0_SlaveRecv( PUINT8 pbuf, UINT16 len ); + +// refer to SPI0 interrupt bit define +#define SPI0_ITCfg(s,f) ((s)?(R8_SPI0_INTER_EN|=f):(R8_SPI0_INTER_EN&=~f)) +#define SPI0_GetITFlag(f) (R8_SPI0_INT_FLAG&f) +#define SPI0_ClearITFlag(f) (R8_SPI0_INT_FLAG = f) + + +/**************** SPI1 */ +void SPI1_MasterDefInit( void ); +void SPI1_DataMode( ModeBitOrderTypeDef m ); + +void SPI1_MasterSendByte( UINT8 d ); +UINT8 SPI1_MasterRecvByte( void ); + +void SPI1_MasterTrans( UINT8 *pbuf, UINT16 len ); +void SPI1_MasterRecv( UINT8 *pbuf, UINT16 len ); + +void SPI1_MasterDMATrans( PUINT8 pbuf, UINT16 len); +void SPI1_MasterDMARecv( PUINT8 pbuf, UINT16 len); + +void SPI1_SlaveInit( void ); +#define SetFirst1Data(d) (R8_SPI1_SLAVE_PRE = d) +void SPI1_SlaveSendByte( UINT8 d ); +UINT8 SPI1_SlaveRecvByte( void ); + +void SPI1_SlaveTrans( UINT8 *pbuf, UINT16 len ); +void SPI1_SlaveRecv( PUINT8 pbuf, UINT16 len ); + +// refer to SPI1 interrupt bit define +#define SPI1_ITCfg(s,f) ((s)?(R8_SPI1_INTER_EN|=f):(R8_SPI1_INTER_EN&=~f)) +#define SPI1_GetITFlag(f) (R8_SPI1_INT_FLAG&f) +#define SPI1_ClearITFlag(f) (R8_SPI1_INT_FLAG = f) + + + + +#ifdef __cplusplus +} +#endif + +#endif // __CH56x_SPI_H__ + diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_sys.h b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_sys.h new file mode 100644 index 000000000..5c93c3215 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_sys.h @@ -0,0 +1,64 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : CH56x_sys.h +* Author : WCH +* Version : V1.0 +* Date : 2020/07/31 +* Description : This file contains all the functions prototypes for +* SystemCoreClock, UART Printf , Delay functions . +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + + +#ifndef __CH56x_SYS_H__ +#define __CH56x_SYS_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "CH56xSFR.h" + + +/** + * @brief SYSTEM Information State + */ +typedef enum +{ + INFO_RESET_EN = 2, // RST# Whether the external manual reset input function is enabled + INFO_BOOT_EN, // Whether the system boot program BootLoader is enabled + INFO_DEBUG_EN, // Whether the system simulation debugging interface is enabled + INFO_LOADER, // Whether the current system is in the Bootloader area +}SYS_InfoStaTypeDef; + + +#define SYS_GetChipID() R8_CHIP_ID /* Get the chip ID class, generally a fixed value */ +#define SYS_GetAccessID() R8_SAFE_ACCESS_ID /* Get the security access ID, usually a fixed value */ +UINT8 SYS_GetInfoSta( SYS_InfoStaTypeDef i ); /* Get the current system information status */ + +void Delay_Init(uint32_t systemclck); +void mDelayuS(uint32_t n); +void mDelaymS(uint32_t n); + +//refer to SYS_ResetStaTypeDef +#define SYS_GetLastResetSta() (R8_RST_BOOT_STAT&RB_RESET_FLAG) /* Get the last reset status of the system */ +void SYS_ResetExecute( void ); /* Perform a system software reset */ +#define SYS_ResetKeepBuf( d ) (R8_GLOB_RESET_KEEP = d) /* Not affected by manual reset, software reset, watchdog reset or normal wake-up reset */ + +//WWDG +#define WWDG_SetCounter( c ) (R8_WDOG_COUNT = c) /* Load the initial value of the watchdog count, incremental */ +void WWDG_ITCfg( UINT8 s ); /* Watchdog overflow interrupt enable */ +void WWDG_ResetCfg( UINT8 s ); /* Watchdog time-out reset enable */ +#define WWDG_GetFlowFlag() (R8_RST_WDOG_CTRL&RB_WDOG_INT_FLAG) /* Get the current watchdog timer overflow flag */ +void WWDG_ClearFlag(void); /* Clear watchdog interrupt flag, reload count value can also be cleared */ + + + +#ifdef __cplusplus +} +#endif + +#endif // __CH56x_SYS_H__ + diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_timer.h b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_timer.h new file mode 100644 index 000000000..0f48b5746 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_timer.h @@ -0,0 +1,155 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : CH56x_timer.ch +* Author : WCH +* Version : V1.0 +* Date : 2020/07/31 +* Description : +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + + +#ifndef __CH56x_TIMER_H__ +#define __CH56x_TIMER_H__ + +#ifdef __cplusplus + extern "C" { +#endif + + +/** + * @brief Pulse Width Modulation Effective Output Words + */ +typedef enum +{ + PWM_Times_1 = 0, // PWM effective output repeats 1 times + PWM_Times_4 = 1, // PWM effective output repeats 4 times + PWM_Times_8 = 2, // PWM effective output repeats 8 times + PWM_Times_16 = 3, // PWM effective output repeats 16 times +}PWM_RepeatTsTypeDef; + + +/** + * @brief Input Capture Edge Mode + */ +typedef enum +{ + CAP_NULL = 0, // not capture + Edge_To_Edge = 1, // between any edge + FallEdge_To_FallEdge = 2, // falling edge to falling edge + RiseEdge_To_RiseEdge = 3, // rising edge to rising edge +}CapModeTypeDef; + + +/** + * @brief Direct access memory loop mode + */ +typedef enum +{ + Mode_Single = 0, // single mode + Mode_LOOP = 1, // cycle mode +}DMAModeTypeDef; + + +/** + * @brief PWM output polarity + */ +typedef enum +{ + high_on_low = 0, // Default low level, high level is active + low_on_high = 1, // Default high level, low level active +}PWM_PolarTypeDef; + + +/****************** TMR0 */ +// Timing and counting +void TMR0_TimerInit( UINT32 t ); /* Timing function initialization */ +void TMR0_EXTSignalCounterInit( UINT32 c ); /* External signal counting function initialization */ +#define TMR0_GetCurrentCount() R32_TMR0_COUNT /* Get the current count value, 67108864 */ + +// Pulse Width Modulation Function +#define TMR0_PWMCycleCfg( cyc ) (R32_TMR0_CNT_END=cyc) /* PWM0 channel output waveform period configuration, maximum 67108864 */ +void TMR0_PWMInit( PWM_PolarTypeDef pr, PWM_RepeatTsTypeDef ts ); /* PWM0 output initialization */ +#define TMR0_PWMActDataWidth( d ) (R32_TMR0_FIFO = d) /* PWM0 effective data pulse width, maximum 67108864 */ + +// Catch pulse width +#define TMR0_CAPTimeoutCfg( cyc ) (R32_TMR0_CNT_END=cyc) /* CAP0 capture level timeout configuration, maximum 33554432 */ +void TMR0_CapInit( CapModeTypeDef cap ); /* External signal capture function initialization */ +#define TMR0_CAPGetData() R32_TMR0_FIFO /* Get pulse data */ +#define TMR0_CAPDataCounter() R8_TMR0_FIFO_COUNT /* Get the number of currently captured data */ + +#define TMR0_Disable() (R8_TMR0_CTRL_MOD &= ~RB_TMR_COUNT_EN) /* Close TMR0 */ +// refer to TMR0 interrupt bit define +#define TMR0_ITCfg(s,f) ((s)?(R8_TMR0_INTER_EN|=f):(R8_TMR0_INTER_EN&=~f)) /* TMR0 corresponding interrupt bit on and off */ +// refer to TMR0 interrupt bit define +#define TMR0_ClearITFlag(f) (R8_TMR0_INT_FLAG = f) /* Clear interrupt flag */ +#define TMR0_GetITFlag(f) (R8_TMR0_INT_FLAG&f) /* Query interrupt flag status */ + + +/****************** TMR1 */ +// Timing and counting +void TMR1_TimerInit( UINT32 t ); /* Timing function initialization */ +void TMR1_EXTSignalCounterInit( UINT32 c ); /* External signal counting function initialization */ +#define TMR1_GetCurrentCount() R32_TMR1_COUNT /* Get the current count value, 67108864 */ + +// Pulse Width Modulation Function +#define TMR1_PWMCycleCfg( cyc ) (R32_TMR1_CNT_END=cyc) /* PWM1 channel output waveform period configuration, maximum 67108864 */ +void TMR1_PWMInit( PWM_PolarTypeDef pr, PWM_RepeatTsTypeDef ts ); /* PWM1 output initialization */ +#define TMR1_PWMActDataWidth( d ) (R32_TMR1_FIFO = d) /* PWM1 effective data pulse width, maximum 67108864 */ + +// Catch pulse width +#define TMR1_CAPTimeoutCfg( cyc ) (R32_TMR1_CNT_END=cyc) /* CAP1 capture level timeout configuration, maximum 33554432 */ +void TMR1_CapInit( CapModeTypeDef cap ); /* External signal capture function initialization */ +#define TMR1_CAPGetData() R32_TMR1_FIFO /* Get pulse data */ +#define TMR1_CAPDataCounter() R8_TMR1_FIFO_COUNT /* Get the number of currently captured data */ + +void TMR1_DMACfg( UINT8 s, UINT16 startAddr, UINT16 endAddr, DMAModeTypeDef m ); /* DMA configuration */ + +#define TMR1_Disable() (R8_TMR1_CTRL_MOD &= ~RB_TMR_COUNT_EN) /* Close TMR1 */ +// refer to TMR1 interrupt bit define +#define TMR1_ITCfg(s,f) ((s)?(R8_TMR1_INTER_EN|=f):(R8_TMR1_INTER_EN&=~f)) /* TMR1 corresponding interrupt bit on and off */ +// refer to TMR1 interrupt bit define +#define TMR1_ClearITFlag(f) (R8_TMR1_INT_FLAG = f) /* Clear interrupt flag */ +#define TMR1_GetITFlag(f) (R8_TMR1_INT_FLAG&f) /* Query interrupt flag status */ + + +/****************** TMR2 */ +// Timing and counting +void TMR2_TimerInit( UINT32 t ); /* Timing function initialization */ +void TMR2_EXTSignalCounterInit( UINT32 c ); /* External signal counting function initialization */ +#define TMR2_GetCurrentCount() R32_TMR2_COUNT /* Get the current count value, 67108864 */ + +// Pulse Width Modulation Function +#define TMR2_PWMCycleCfg( cyc ) (R32_TMR2_CNT_END=cyc) /* PWM2 channel output waveform period configuration, maximum 67108864 */ +void TMR2_PWMInit( PWM_PolarTypeDef pr, PWM_RepeatTsTypeDef ts ); /* PWM2 output initialization */ +#define TMR2_PWMActDataWidth( d ) (R32_TMR2_FIFO = d) /* PWM2 effective data pulse width, maximum 67108864 */ + +// Catch pulse width +#define TMR2_CAPTimeoutCfg( cyc ) (R32_TMR2_CNT_END=cyc) /* CAP2 capture level timeout configuration, maximum 33554432 */ +void TMR2_CapInit( CapModeTypeDef cap ); /* External signal capture function initialization */ +#define TMR2_CAPGetData() R32_TMR2_FIFO /* Get pulse data */ +#define TMR2_CAPDataCounter() R8_TMR2_FIFO_COUNT /* Get the number of currently captured data */ + +void TMR2_DMACfg( UINT8 s, UINT16 startAddr, UINT16 endAddr, DMAModeTypeDef m ); /* DMA configuration */ + +#define TMR2_Disable() (R8_TMR2_CTRL_MOD &= ~RB_TMR_COUNT_EN) /* Close TMR2 */ +// refer to TMR2 interrupt bit define +#define TMR2_ITCfg(s,f) ((s)?(R8_TMR2_INTER_EN|=f):(R8_TMR2_INTER_EN&=~f)) /* TMR2 corresponding interrupt bit on and off */ +// refer to TMR2 interrupt bit define +#define TMR2_ClearITFlag(f) (R8_TMR2_INT_FLAG = f) /* Clear interrupt flag */ +#define TMR2_GetITFlag(f) (R8_TMR2_INT_FLAG & f) /* Query interrupt flag status */ + + + +#ifdef __cplusplus + } +#endif + +#endif // __CH56x_TIMER_H__ + + + + + diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_uart.h b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_uart.h new file mode 100644 index 000000000..26e59e4fd --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/inc/CH56x_uart.h @@ -0,0 +1,136 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : CH56x_uart.h +* Author : WCH +* Version : V1.0 +* Date : 2020/07/31 +* Description : +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + + +#ifndef __CH56x_UART_H__ +#define __CH56x_UART_H__ + +#ifdef __cplusplus + extern "C" { +#endif + + +/** + * @brief Line Error Status Definition + */ +#define STA_ERR_BREAK RB_LSR_BREAK_ERR // Data Interval Error +#define STA_ERR_FRAME RB_LSR_FRAME_ERR // DataFrame error +#define STA_ERR_PAR RB_LSR_PAR_ERR // Parity bit error +#define STA_ERR_FIFOOV RB_LSR_OVER_ERR // Receive Data Overflow + +#define STA_TXFIFO_EMP RB_LSR_TX_FIFO_EMP // The current send FIFO is empty, you can continue to fill the send data +#define STA_TXALL_EMP RB_LSR_TX_ALL_EMP // All currently sent data has been sent +#define STA_RECV_DATA RB_LSR_DATA_RDY // Data is currently received + + +/** + * @brief Serial port byte trigger configuration + */ +typedef enum +{ + UART_1BYTE_TRIG = 0, // 1 byte trigger + UART_2BYTE_TRIG = 1, // 2 byte trigger + UART_4BYTE_TRIG = 2, // 4 byte trigger + UART_7BYTE_TRIG = 3 , // 7 byte trigger + +}UARTByteTRIGTypeDef; + + +/****************** UART0 */ +void UART0_DefInit( void ); /* Serial port default initialization configuration */ +void UART0_BaudRateCfg( UINT32 baudrate ); /* Serial port baud rate configuration */ +void UART0_ByteTrigCfg( UARTByteTRIGTypeDef b ); /* Serial byte trigger interrupt configuration */ +void UART0_INTCfg( UINT8 s, UINT8 i ); /* Serial port interrupt configuration */ +void UART0_Reset( void ); /* Serial port software reset */ + +#define UART0_CLR_RXFIFO() (R8_UART0_FCR |= RB_FCR_RX_FIFO_CLR) /* Clear the current receive FIFO */ +#define UART0_CLR_TXFIFO() (R8_UART0_FCR |= RB_FCR_TX_FIFO_CLR) /* Clear the current transmit FIFO */ + +#define UART0_GetITFlag() (R8_UART0_IIR & RB_IIR_INT_MASK) /* Get the current interrupt flag */ +// please refer to LINE error and status define +#define UART0_GetLinSTA() (R8_UART0_LSR) /* Get the current communication status */ +#define UART0_GetMSRSTA() (R8_UART0_MSR) /* Get the current flow control status, only applicable to UART0 */ + +#define UART0_SendByte(b) (R8_UART0_THR = b) /* Serial port single byte transmission */ +void UART0_SendString( PUINT8 buf, UINT16 l ); /* Serial multi-byte transmission */ +#define UART0_RecvByte() ( R8_UART0_RBR ) /* Serial port read single byte */ +UINT16 UART0_RecvString( PUINT8 buf ); /* Serial port read multibyte */ + + +/****************** UART1 */ +void UART1_DefInit( void ); /* Serial port default initialization configuration */ +void UART1_BaudRateCfg( UINT32 baudrate ); /* Serial port baud rate configuration */ +void UART1_ByteTrigCfg( UARTByteTRIGTypeDef b ); /* Serial byte trigger interrupt configuration */ +void UART1_INTCfg( UINT8 s, UINT8 i ); /* Serial port interrupt configuration */ +void UART1_Reset( void ); /* Serial port software reset */ + +#define UART1_CLR_RXFIFO() (R8_UART1_FCR |= RB_FCR_RX_FIFO_CLR) /* Clear the current receive FIFO */ +#define UART1_CLR_TXFIFO() (R8_UART1_FCR |= RB_FCR_TX_FIFO_CLR) /* Clear the current transmit FIFO */ + +#define UART1_GetITFlag() (R8_UART1_IIR&RB_IIR_INT_MASK) /* Get the current interrupt flag */ +// please refer to LINE error and status define +#define UART1_GetLinSTA() (R8_UART1_LSR) /* Get the current communication status */ + +#define UART1_SendByte(b) (R8_UART1_THR = b) /* Serial port single byte transmission */ +void UART1_SendString( PUINT8 buf, UINT16 l ); /* Serial multi-byte transmission */ +#define UART1_RecvByte() ( R8_UART1_RBR ) /* Serial port read single byte */ +UINT16 UART1_RecvString( PUINT8 buf ); /* Serial port read multibyte */ + + + +/****************** UART2 */ +void UART2_DefInit( void ); /* Serial port default initialization configuration */ +void UART2_BaudRateCfg( UINT32 baudrate ); /* Serial port baud rate configuration */ +void UART2_ByteTrigCfg( UARTByteTRIGTypeDef b ); /* Serial byte trigger interrupt configuration */ +void UART2_INTCfg( UINT8 s, UINT8 i ); /* Serial port interrupt configuration */ +void UART2_Reset( void ); /* Serial port software reset */ + +#define UART2_CLR_RXFIFO() (R8_UART2_FCR |= RB_FCR_RX_FIFO_CLR) /* Clear the current receive FIFO */ +#define UART2_CLR_TXFIFO() (R8_UART2_FCR |= RB_FCR_TX_FIFO_CLR) /* Clear the current transmit FIFO */ + +#define UART2_GetITFlag() (R8_UART2_IIR&RB_IIR_INT_MASK) /* Get the current interrupt flag */ +// please refer to LINE error and status define +#define UART2_GetLinSTA() (R8_UART2_LSR) /* Get the current communication status */ + +#define UART2_SendByte(b) (R8_UART2_THR = b) /* Serial port single byte transmission */ +void UART2_SendString( PUINT8 buf, UINT16 l ); /* Serial multi-byte transmission */ +#define UART2_RecvByte() ( R8_UART2_RBR ) /* Serial port read single byte */ +UINT16 UART2_RecvString( PUINT8 buf ); /* Serial port read multibyte */ + + +/****************** UART3 */ +void UART3_DefInit( void ); /* Serial port default initialization configuration */ +void UART3_BaudRateCfg( UINT32 baudrate ); /* Serial port baud rate configuration */ +void UART3_ByteTrigCfg( UARTByteTRIGTypeDef b ); /* Serial byte trigger interrupt configuration */ +void UART3_INTCfg( UINT8 s, UINT8 i ); /* Serial port interrupt configuration */ +void UART3_Reset( void ); /* Serial port software reset */ + +#define UART3_CLR_RXFIFO() (R8_UART3_FCR |= RB_FCR_RX_FIFO_CLR) /* Clear the current receive FIFO */ +#define UART3_CLR_TXFIFO() (R8_UART3_FCR |= RB_FCR_TX_FIFO_CLR) /* Clear the current transmit FIFO */ + +#define UART3_GetITFlag() (R8_UART3_IIR&RB_IIR_INT_MASK) /* Get the current interrupt flag */ +// please refer to LINE error and status define +#define UART3_GetLinSTA() (R8_UART3_LSR) /* Get the current communication status */ + +#define UART3_SendByte(b) (R8_UART3_THR = b) /* Serial port single byte transmission */ +void UART3_SendString( PUINT8 buf, UINT16 l ); /* Serial multi-byte transmission */ +#define UART3_RecvByte() ( R8_UART3_RBR ) /* Serial port read single byte */ +UINT16 UART3_RecvString( PUINT8 buf ); /* Serial port read multibyte */ + + + +#ifdef __cplusplus +} +#endif + +#endif // __CH56x_UART_H__ + diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_bus8.c b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_bus8.c new file mode 100644 index 000000000..940cf4f73 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_bus8.c @@ -0,0 +1,57 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : CH56x_bus8.c +* Author : WCH +* Version : V1.0 +* Date : 2020/07/31 +* Description : +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + +#include "CH56x_common.h" + + + +/******************************************************************************* + * @fn BUS8_GPIO_Init + * + * @brief BUS8 GPIO initialization + * + * @return None + */ +void BUS8_GPIO_Init(void) +{ + R32_PA_DIR = 0; + R32_PA_PU = 0xff; + R32_PA_SMT = 0xffffffff; + R32_PA_DIR |= bBUSRD | bBUSWR; //R/W signal GPIO + R32_PB_DIR |= 0x7fff; + R32_PB_SMT |= 0x7fff; + +} + +/******************************************************************************* + * @fn BUS8_Init + * + * @brief BUS8 initialization + * + * @param addroe:0x00-none;0x04-[5:0];0x08-[9:0];0x0c-[14:0]; + * width: 0x00-3;0x10-5;0x20-9;0x30-16; + * hold: 0x00-2;0x40-3; + * setup: 0x00-2;0x80-3; + * + * @return None + */ +void BUS8_Init(UINT8 addroe, UINT8 width, UINT8 hold, UINT8 setup) +{ + R8_XBUS_CONFIG = addroe | width | hold | setup; + R8_XBUS_CONFIG |= RB_XBUS_ENABLE; //Enable + BUS8_GPIO_Init(); +} + + + + + diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_clk.c b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_clk.c new file mode 100644 index 000000000..dbfb7213e --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_clk.c @@ -0,0 +1,115 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : CH56x_clk.c +* Author : WCH +* Version : V1.0 +* Date : 2020/07/31 +* Description : +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + +#include "CH56x_common.h" + + +/******************************************************************************* + * @fn SystemInit + * + * @brief System clock initialization + * + * @param systemclck: system clock Hz + * + * @return None + */ +void SystemInit(uint32_t systemclck) +{ + uint8_t sc; + + sc = systemclck/1000000; + + switch( sc ) + { + case CLK_SOURCE_PLL_15MHz: + R8_SAFE_ACCESS_SIG = 0x57; // enable safe access mode + R8_SAFE_ACCESS_SIG = 0xa8; + R8_CLK_PLL_DIV = 0x40 | 0x02; + R8_CLK_CFG_CTRL = 0x80 ; + + break; + case CLK_SOURCE_PLL_30MHz: + R8_SAFE_ACCESS_SIG = 0x57; // enable safe access mode + R8_SAFE_ACCESS_SIG = 0xa8; + R8_CLK_PLL_DIV = 0x40; + R8_CLK_CFG_CTRL = 0x80 | RB_CLK_SEL_PLL; + + break; + case CLK_SOURCE_PLL_60MHz: + R8_SAFE_ACCESS_SIG = 0x57; // enable safe access mode + R8_SAFE_ACCESS_SIG = 0xa8; + R8_CLK_PLL_DIV = 0x40 | 0x08; + R8_CLK_CFG_CTRL = 0x80 | RB_CLK_SEL_PLL; + + break; + case CLK_SOURCE_PLL_80MHz: + R8_SAFE_ACCESS_SIG = 0x57; // enable safe access mode + R8_SAFE_ACCESS_SIG = 0xa8; + R8_CLK_PLL_DIV = 0x40 | 0x06; + R8_CLK_CFG_CTRL = 0x80 | RB_CLK_SEL_PLL; + + break; + case CLK_SOURCE_PLL_96MHz: + R8_SAFE_ACCESS_SIG = 0x57; // enable safe access mode + R8_SAFE_ACCESS_SIG = 0xa8; + R8_CLK_PLL_DIV = 0x40 | 0x05; + R8_CLK_CFG_CTRL = 0x80 | RB_CLK_SEL_PLL; + + break; + case CLK_SOURCE_PLL_120MHz: + R8_SAFE_ACCESS_SIG = 0x57; // enable safe access mode + R8_SAFE_ACCESS_SIG = 0xa8; + R8_CLK_PLL_DIV = 0x40 | 0x04; + R8_CLK_CFG_CTRL = 0x80 | RB_CLK_SEL_PLL; + + break; + default : + break; + } + R8_SAFE_ACCESS_SIG = 0; +} + +/******************************************************************************* + * @fn GetSysClock + * + * @brief Get the current system clock + * + * @param None + * + * @return Hz + */ +UINT32 GetSysClock( void ) +{ + UINT8 rev; + + rev = R8_CLK_PLL_DIV & 0x0F; + + if(R8_CLK_CFG_CTRL & RB_CLK_SEL_PLL){ //The system clock source comes from the 480M provided by the USB PHY + if(rev == 0){ + return (30000000); + } + else{ + return (480000000/R8_CLK_PLL_DIV); + } + } + else{ //The system clock source comes from an external crystal oscillator 30M + if(rev == 0){ + return (2000000); + } + else{ + return (30000000/R8_CLK_PLL_DIV); + } + } +} + + + diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_dvp.c b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_dvp.c new file mode 100644 index 000000000..0177f4372 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_dvp.c @@ -0,0 +1,132 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : CH56x_dvp.c +* Author : WCH +* Version : V1.0 +* Date : 2020/07/31 +* Description : +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + +#include "CH56x_common.h" + + +/******************************************************************************* + * @fn DVP_INTCfg + * + * @brief DVP interrupt configuration + * + * @param s: interrupt control status + ENABLE - Enables the corresponding interrupt + DISABLE - disables the corresponding interrupt + i: interrupt type + RB_DVP_IE_STP_FRM - end of frame interrupt + RB_DVP_IE_FIFO_OV - Receive FIFO overflow interrupt + RB_DVP_IE_FRM_DONE - end of frame interrupt + RB_DVP_IE_ROW_DONE - end of line break + RB_DVP_IE_STR_FRM - start of frame interrupt + * + * @return None + **/ +void DVP_INTCfg( UINT8 s, UINT8 i ) +{ + if(s){ + R8_DVP_INT_EN |= i; + } + else{ + R8_DVP_INT_EN &= ~i; + } +} + +/******************************************************************************* + * @fn DVP_Mode + * + * @brief DVP mode + * + * @param s: data width + RB_DVP_D8_MOD - 8-bit mode + RB_DVP_D10_MOD - 10-bit mode + RB_DVP_D12_MOD - 12-bit mode + i: Compressed Data Mode + Video_Mode - enable video mode + JPEG_Mode - Enable JPEG mode + * + * @return None + */ +void DVP_Mode( UINT8 s, DVP_Data_ModeTypeDef i) +{ + R8_DVP_CR0 &= ~RB_DVP_MSK_DAT_MOD; //Restore default mode 8bit mode + + if(s){ + R8_DVP_CR0 |= s; + } + else{ + R8_DVP_CR0 &= ~(3<<4); + } + + if(i){ + R8_DVP_CR0 |= RB_DVP_JPEG; + } + else{ + R8_DVP_CR0 &= ~RB_DVP_JPEG; + } +} + +/******************************************************************************* + * @fn DVP_Cfg + * + * @brief DVP configuration + * + * @param s: DMA enable control + DVP_DMA_Enable - DMA enable + DVP_DMA_Disable - DMA disable + i: Flag and FIFO Clear Control + DVP_FLAG_FIFO_RESET_Enable - Reset flag and FIFO + DVP_FLAG_FIFO_RESET_Disable - cancel reset operation + j: Receive Logic Reset Control + DVP_RX_RESET_Enable - reset receiver logic + DVP_RX_RESET_Disable - cancel reset operation + * + * @return None + */ +void DVP_Cfg( DVP_DMATypeDef s, DVP_FLAG_FIFO_RESETTypeDef i, DVP_RX_RESETTypeDef j) +{ + switch( s ) + { + case DVP_DMA_Enable: + R8_DVP_CR1 |= RB_DVP_DMA_EN; + break; + case DVP_DMA_Disable: + R8_DVP_CR1 &= ~RB_DVP_DMA_EN; + break; + default: + break; + } + + switch( i ) + { + case DVP_RX_RESET_Enable: + R8_DVP_CR1 |= RB_DVP_ALL_CLR; + break; + case DVP_RX_RESET_Disable: + R8_DVP_CR1 &= ~RB_DVP_ALL_CLR; + break; + default: + break; + } + + switch( j ) + { + case DVP_RX_RESET_Enable: + R8_DVP_CR1 |= RB_DVP_RCV_CLR; + break; + case DVP_RX_RESET_Disable: + R8_DVP_CR1 &= ~RB_DVP_RCV_CLR; + break; + default: + break; + } + +} diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_ecdc.c b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_ecdc.c new file mode 100644 index 000000000..2b0160013 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_ecdc.c @@ -0,0 +1,182 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : CH56x_ecdc.c +* Author : WCH +* Version : V1.0 +* Date : 2020/07/31 +* Description : +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + +#include "CH56x_common.h" + + +/******************************************************************************* + * @fn ECDC_Init + * + * @brief initialization + * + * @param ecdcmode - 0-SM4&ECB 1-AES&ECB 2-SM4&CTR 3-AES&CTR + * clkmode - 1-closure 2-240M 3-160M + * keylen - 0-128bit 1-192bit 2-256bit + * pkey - key value pointer + * pcount - counter value pointer + * + * @return None + */ +void ECDC_Init( UINT8 ecdcmode, UINT8 clkmode, UINT8 keylen, PUINT32 pkey, PUINT32 pcount ) +{ + R8_ECDC_INT_FG |= 0xFF; + R16_ECEC_CTRL = 0; + + R16_ECEC_CTRL |= (ecdcmode&0x03)<<8; //Working mode selection + R16_ECEC_CTRL |= (keylen&0x03)<<10; //key length setting + R16_ECEC_CTRL |= (clkmode&0x03)<<4; //Encryption and decryption clock frequency division factor, aes encryption and decryption works at 240Mhz + ECDC_SetKey(pkey, keylen); + + if(R16_ECEC_CTRL & RB_ECDC_CIPHER_MOD) //Execute only in CTR mode, the only difference between CTR and ECB mode programming + ECDC_SetCount(pcount); + + R8_ECDC_INT_FG |= RB_ECDC_IF_EKDONE; + R16_ECEC_CTRL |= RB_ECDC_KEYEX_EN; + R16_ECEC_CTRL &= ~RB_ECDC_KEYEX_EN; + + while(!(R8_ECDC_INT_FG & RB_ECDC_IF_EKDONE)); + R8_ECDC_INT_FG |= RB_ECDC_IF_EKDONE; +} + +/******************************************************************************* + * @fn ECDC_SetKey + * + * @brief set key + * + * @param pkey - key value pointer + * keylen - 0-128bit 1-192bit 2-256bit + + * @return None + */ +void ECDC_SetKey( PUINT32 pkey, UINT8 keylen ) +{ + keylen = keylen&0x03; + + R32_ECDC_KEY_31T0 = *pkey++; + R32_ECDC_KEY_63T32 = *pkey++; + R32_ECDC_KEY_95T64 = *pkey++; + R32_ECDC_KEY_127T96 = *pkey++; + + if(keylen){ + R32_ECDC_KEY_159T128 = *pkey++; + R32_ECDC_KEY_191T160 = *pkey++; + } + if(keylen>1){ + R32_ECDC_KEY_223T192 = *pkey++; + R32_ECDC_KEY_255T224 = *pkey++; + } +} + +/******************************************************************************* + * @fn ECDC_SetCount + * + * @brief set counter + * + * @param pcount - counter value pointer + * + * @return None + */ +void ECDC_SetCount( PUINT32 pcount ) +{ + R32_ECDC_IV_31T0 = *pcount++; + R32_ECDC_IV_63T32 = *pcount++; + R32_ECDC_IV_95T64 = *pcount++; + R32_ECDC_IV_127T96 = *pcount++; +} + +/******************************************************************************* + * @fn ECDC_Excute + * + * @brief Set direction and mode + * + * @param excutemode - RAMX encryption -0x84 + * RAMX decryption -0x8c + * 128bits data single encryption -0x02 + * 128bits data single decryption -0x0a + * Peripheral to RAMX encryption -0x02 + * Peripheral to RAMX decryption -0x0a + * RAMX to Peripheral encryption -0x04 + * RAMX to Peripheral decryption -0x0c + * endianmode - big_endian-1 little_endian-0 + * + * @return None + */ +void ECDC_Excute( UINT8 excutemode, UINT8 endianmode ) +{ + R16_ECEC_CTRL &= 0xDF71; + R16_ECEC_CTRL |= excutemode; + if(endianmode) + R16_ECEC_CTRL |= RB_ECDC_DAT_MOD; + else + R16_ECEC_CTRL &= ~RB_ECDC_DAT_MOD; +} + +/******************************************************************************* + * @fn ECDC_SingleRegister + * + * @brief Single register encryption and decryption + * + * @param pWdatbuff - Write data first address + * pRdatbuff - Read data first address + * + * @return None + */ +void ECDC_SingleRegister( PUINT32 pWdatbuff, PUINT32 pRdatbuff ) +{ + R32_ECDC_SGSD_127T96 = pWdatbuff[3]; //low address + R32_ECDC_SGSD_95T64 = pWdatbuff[2]; + R32_ECDC_SGSD_63T32 = pWdatbuff[1]; + R32_ECDC_SGSD_31T0 = pWdatbuff[0]; //high address + + while(!(R8_ECDC_INT_FG & RB_ECDC_IF_SINGLE)); + R8_ECDC_INT_FG |= RB_ECDC_IF_SINGLE; + + pRdatbuff[3] = R32_ECDC_SGRT_127T96; + pRdatbuff[2] = R32_ECDC_SGRT_95T64; + pRdatbuff[1] = R32_ECDC_SGRT_63T32; + pRdatbuff[0] = R32_ECDC_SGRT_31T0; +} + +/******************************************************************************* + * @fn ECDC_RAMX + * + * @brief RAMX encryption and decryption + * + * @param ram_add - first address + * ram_len - length + * @return None + **/ +void ECDC_SelfDMA( UINT32 ram_addr, UINT32 ram_len ) +{ + R32_ECDC_SRAM_ADDR = ram_addr; + R32_ECDC_SRAM_LEN = ram_len; //start converting + + while(!(R8_ECDC_INT_FG & RB_ECDC_IF_WRSRAM)); //Completion flag + R8_ECDC_INT_FG |= RB_ECDC_IF_WRSRAM; +} + +/******************************************************************************* + * @fn ECDC_RloadCount + * + * @brief In CTR mode, every time a block is encrypted/decrypted, the counter value is reloaded + * + * @param pcount - counter value pointer + * + * @return None + */ +void ECDC_RloadCount( UINT8 excutemode, UINT8 endianmode, PUINT32 pcount ) +{ + R16_ECEC_CTRL &= 0xDFF9; //second position third position 0 + ECDC_SetCount(pcount); + ECDC_Excute(excutemode, endianmode); +} + diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_emmc.c b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_emmc.c new file mode 100644 index 000000000..0ee762800 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_emmc.c @@ -0,0 +1,870 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : CH56x_emmc.c +* Author : WCH +* Version : V1.0 +* Date : 2020/07/31 +* Description : +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "CH56x_common.h" + +/******************************************************************************* + * @fn EMMCIO0Init + * + * @brief EMMC Controller Initializtion + * + * @return OP_SUCCESS + */ +UINT8 EMMCIO0Init( void ) +{ +/* GPIO configuration */ + R32_PB_DRV |= bSDCMD; //Command Line + R32_PB_PU |= bSDCMD; + + R32_PB_DIR |= bSDCK; //CLK Line + R32_PB_DRV |= bSDCK; + + R32_PB_PU |= (0x1f<<17); //Data Line + R32_PA_PU |= (7<<0); + + R32_PA_DRV |= (7<<0); // Drive Capacity + R32_PB_DRV |= (0x1f<<17); // Drive Capacity + + +/* Controller Register */ + R8_EMMC_CONTROL = RB_EMMC_ALL_CLR | RB_EMMC_RST_LGC ; // reset all register + R8_EMMC_CONTROL = RB_EMMC_NEGSMP | RB_EMMC_DMAEN ; // Enable EMMCcard + R32_PB_DIR |= bSDCK; + R16_EMMC_CLK_DIV = RB_EMMC_CLKOE | LOWEMMCCLK|RB_EMMC_PHASEINV; + +/* Enable Interruption */ + R16_EMMC_INT_FG = 0xffff; + R16_EMMC_INT_EN = RB_EMMC_IE_FIFO_OV | //Enable error Interruption + RB_EMMC_IE_TRANERR | + RB_EMMC_IE_DATTMO | + RB_EMMC_IE_REIDX_ER | + RB_EMMC_IE_RECRC_WR | + RB_EMMC_IE_RE_TMOUT; + +/* Overtime */ + R8_EMMC_TIMEOUT = 35; // calculating overtime + return OP_SUCCESS; +} + +/******************************************************************************* + * @fn CheckCMDComp + * + * @brief Estimate the end of Command + * + * @param pEMMCPara + * + * @return CMD_NULL + **/ +UINT8 CheckCMDComp( PSD_PARAMETER pEMMCPara ) +{ + if(R16_EMMC_INT_FG & RB_EMMC_IF_CMDDONE) + { + R16_EMMC_INT_FG = RB_EMMC_IF_CMDDONE; + return CMD_SUCCESS; + } + if( pEMMCPara->EMMCOpErr ) return CMD_FAILED; + return CMD_NULL; +} + +/******************************************************************************* + * @fn EMMCResetIdle + * + * @brief when EMMC waiting status,do the OCR analysis + * + * @param pEMMCPara + * + * @return None + */ +void EMMCResetIdle( PSD_PARAMETER pEMMCPara ) +{ + UINT32 cmd_arg_val; + UINT16 cmd_set_val; + + cmd_arg_val = 0x0; + cmd_set_val = 0x0|EMMC_CMD0; + EMMCSendCmd(cmd_arg_val, cmd_set_val); + while( CheckCMDComp( pEMMCPara ) == CMD_NULL ); +} + + +/******************************************************************************* + * @fn EMMCReadOCR + * + * @brief when EMMC waiting status,do the OCR analysis + * + * @param pEMMCPara + * + * @return CMD_SUCCESS + */ +UINT8 EMMCReadOCR( PSD_PARAMETER pEMMCPara ) +{ + UINT8 i; + UINT32 cmd_arg_val; + UINT16 cmd_set_val; + UINT8 sta = 0; + UINT32 cmd_rsp_val; //command returned value + + for(i=0; i<100; i++) + { + cmd_arg_val = 0x40FF0080; //request switching voltage +// cmd_arg_val = 0x40000800; //request switching voltage + cmd_set_val = 0 | //ACK's index + 0 | //CRC + RESP_TYPE_48 | //ACK type + EMMC_CMD1; //command's index this moment + mDelaymS(10); + EMMCSendCmd(cmd_arg_val, cmd_set_val); + mDelayuS(2); + while(1) + { + sta = CheckCMDComp( pEMMCPara ); + if( sta!= CMD_NULL ) + { + break; + } + } + + if(sta == CMD_SUCCESS) + { + cmd_rsp_val = R32_EMMC_RESPONSE3; + if(cmd_rsp_val & (1<<31)) + { + break; + } + } + mDelaymS(50); + } + if(i == 100) return OP_FAILED; + + return sta; +} + + +/******************************************************************************* + * @fn EMMCReadCID + * + * @brief acquire 128bit CID parameter + * + * @param pEMMCPara + * + * @return OP_SUCCESS + **/ +UINT8 EMMCReadCID( PSD_PARAMETER pEMMCPara ) +{ + UINT32 cmd_arg_val; + UINT16 cmd_set_val; + UINT8 sta; + + cmd_arg_val = 0; + cmd_set_val = 0 | + 0 | + RESP_TYPE_136 | + EMMC_CMD2; + EMMCSendCmd( cmd_arg_val, cmd_set_val); + while(1) + { + sta = CheckCMDComp( pEMMCPara ); + if( sta != CMD_NULL ) break; + } + if(sta == CMD_SUCCESS) + { + pEMMCPara->EMMC_CID[0] = R32_EMMC_RESPONSE0; + pEMMCPara->EMMC_CID[1] = R32_EMMC_RESPONSE1; + pEMMCPara->EMMC_CID[2] = R32_EMMC_RESPONSE2; + pEMMCPara->EMMC_CID[3] = R32_EMMC_RESPONSE3; + } + + return sta; +} + +/******************************************************************************* + * @fn EMMCSetRCA + * + * @brief assign relative address to deviceARC 16bit + * + * @param pEMMCPara + * + * @return OP_SUCCESS + */ +UINT8 EMMCSetRCA( PSD_PARAMETER pEMMCPara ) +{ + UINT32 cmd_arg_val; + UINT16 cmd_set_val; + UINT8 sta; + + cmd_arg_val = 0xAAAA0000; + cmd_set_val = RB_EMMC_CKIDX | + RB_EMMC_CKCRC | + RESP_TYPE_48 | + EMMC_CMD3; + mDelaymS(10); + EMMCSendCmd(cmd_arg_val,cmd_set_val); + while(1) + { + sta = CheckCMDComp( pEMMCPara ); + if( sta != CMD_NULL ) break; + } + if(sta == CMD_SUCCESS) + { + pEMMCPara->EMMC_RCA = 0xAAAA; + } + + return sta; +} + +/******************************************************************************* + * @fn EMMCReadCSD + * + * @brief acquire 128bit CSD parameter and get it analyzed + * + * @param pEMMCPara + * + * @return OP_SUCCESS + */ +UINT8 EMMCReadCSD( PSD_PARAMETER pEMMCPara ) +{ + UINT32 cmd_arg_val; + UINT16 cmd_set_val; + UINT8 sta; + UINT32 disk_block_num = 0; + + cmd_arg_val = pEMMCPara->EMMC_RCA<<16; + cmd_set_val = 0 | + 0 | + RESP_TYPE_136 | + EMMC_CMD9; + EMMCSendCmd(cmd_arg_val, cmd_set_val); + while(1) + { + sta = CheckCMDComp( pEMMCPara ); + if( sta != CMD_NULL ) break; + } + + if(sta == CMD_SUCCESS) + { + pEMMCPara->EMMC_CSD[0] = R32_EMMC_RESPONSE0; + pEMMCPara->EMMC_CSD[1] = R32_EMMC_RESPONSE1; + pEMMCPara->EMMC_CSD[2] = R32_EMMC_RESPONSE2; + pEMMCPara->EMMC_CSD[3] = R32_EMMC_RESPONSE3; + + + disk_block_num = (((pEMMCPara->EMMC_CSD[2]&0x3ff)<<2) | ((pEMMCPara->EMMC_CSD[1])>>30)); + if(disk_block_num == 0xFFF) + { + pEMMCPara->EMMCSecNum = 0xFFF; + } + else + { + pEMMCPara->EMMCType = EMMCIO_CAPACITY_SD_CARD_V2_0; + /* memory capacity = BLOCKNR*BLOCK_LEN = (C_SIZE+1)<<(C_SIZE_MULT+2)<<(READ_BL_LEN) */ + disk_block_num = ( (((pEMMCPara->EMMC_CSD[2]&0x3ff)<<2) | (pEMMCPara->EMMC_CSD[1]>>30)) + 1 ); + disk_block_num = ( (disk_block_num) << (((pEMMCPara->EMMC_CSD[1]>>15)&0x07) + 2)); + } + } + + pEMMCPara->EMMCSecSize = 1<<((pEMMCPara->EMMC_CSD[2]>>16)&0x000f); + return sta; +} + +/******************************************************************************* + * @fn SelectEMMCCard + * + * @brief select card + * + * @param pEMMCPara + * + * @return OP_SUCCESS + */ +UINT8 SelectEMMCCard(PSD_PARAMETER pEMMCPara) +{ + UINT32 cmd_arg_val; + UINT16 cmd_set_val; + UINT8 sta; + + cmd_arg_val = pEMMCPara->EMMC_RCA<<16; + cmd_set_val = RB_EMMC_CKIDX | + RB_EMMC_CKCRC | + RESP_TYPE_48 | + EMMC_CMD7; + EMMCSendCmd(cmd_arg_val, cmd_set_val); + while(1) + { + sta = CheckCMDComp( pEMMCPara ); + if( sta != CMD_NULL ) break; + } + return sta; +} + +UINT8 ReadEMMCStatus(PSD_PARAMETER pEMMCPara) +{ + UINT32 cmd_arg_val; + UINT16 cmd_set_val; + UINT8 sta; + + cmd_arg_val = pEMMCPara->EMMC_RCA<<16; + cmd_set_val = RB_EMMC_CKIDX | + RB_EMMC_CKCRC | + RESP_TYPE_48 | + EMMC_CMD13; + EMMCSendCmd(cmd_arg_val, cmd_set_val); + while(1) + { + sta = CheckCMDComp( pEMMCPara ); + if( sta != CMD_NULL ) break; + } + return sta; +} + +/******************************************************************************* + * @fn SwitchEMMCIOBusType + * + * @brief set the IO bus_mode + * + * @param pEMMCPara - + * bus_mode - + * + * @return OP_SUCCESS + */ +UINT8 EMMCSetBusWidth(PSD_PARAMETER pEMMCPara, UINT8 bus_mode) +{ + UINT32 cmd_arg_val; + UINT16 cmd_set_val; + UINT8 sta; + + if(bus_mode == 0) cmd_arg_val = 0x03B70100; + else cmd_arg_val = 0x03B70200; + cmd_set_val = RB_EMMC_CKIDX | + RB_EMMC_CKCRC | + RESP_TYPE_48 | + EMMC_CMD6; + EMMCSendCmd(cmd_arg_val, cmd_set_val); + while(1) + { + sta = CheckCMDComp( pEMMCPara ); + if( sta != CMD_NULL ) break; + } + return sta; +} + +UINT8 EMMCSetHighSpeed(PSD_PARAMETER pEMMCPara) +{ + UINT32 cmd_arg_val; + UINT16 cmd_set_val; + UINT8 sta; + + cmd_arg_val = 0x03B90100; + cmd_set_val = RB_EMMC_CKIDX | + RB_EMMC_CKCRC | + RESP_TYPE_R1b | + EMMC_CMD6; + EMMCSendCmd(cmd_arg_val, cmd_set_val); + while(1) + { + sta = CheckCMDComp( pEMMCPara ); + if( sta != CMD_NULL ) break; + } + return sta; +} + +/******************************************************************************* + * @fn ConfigAllSD + * + * @brief EMMC Information + * + * @param pEMMCPara + * + * @return OP_SUCCESS + **/ +#define SD2CMD EMMCSendCmd +__attribute__ ((aligned(8))) UINT8 buf[512] __attribute__((section(".DMADATA"))); +UINT8 EMMCCardConfig( PSD_PARAMETER pEMMCPara ) +{ + UINT8 sta; + //cmd0 + EMMCResetIdle( pEMMCPara ); + mDelaymS(30); + sta = EMMCReadOCR( pEMMCPara ); + if(sta!=CMD_SUCCESS) return OP_FAILED; + //cmd2 + sta = EMMCReadCID( pEMMCPara ); + if(sta!=CMD_SUCCESS) return OP_FAILED; + //cmd3 + mDelaymS(30); + sta = EMMCSetRCA( pEMMCPara ); + if(sta!=CMD_SUCCESS) return OP_FAILED; + //cmd9 + sta = EMMCReadCSD( pEMMCPara ); + if(sta!=CMD_SUCCESS) return OP_FAILED; + //cmd7; + mDelaymS(30); + sta = SelectEMMCCard( pEMMCPara ); + if(sta!=CMD_SUCCESS) return OP_FAILED; + mDelaymS(30); + if(pEMMCPara->EMMCSecNum == 0xFFF) + { + sta = EMMCCardReadEXCSD( pEMMCPara, buf ); + if(sta!=OP_SUCCESS) return OP_FAILED; + pEMMCPara->EMMCSecNum = *((PUINT32)&buf[212]); // SEC_COUNT [215:212] MSB-LSB + } + //cmd6 + sta = EMMCSetBusWidth(pEMMCPara, 1); + if(sta!=CMD_SUCCESS) return OP_FAILED; + R8_EMMC_CONTROL = (R8_EMMC_CONTROL&~RB_EMMC_LW_MASK) | bLW_OP_DAT8; // 8line_mode + mDelaymS(30); + //configure high clock rate + EMMCSetHighSpeed(pEMMCPara); + //cmd13 + mDelaymS(30); + sta = ReadEMMCStatus( pEMMCPara ); + if(sta!=CMD_SUCCESS) return OP_FAILED; + mDelaymS(30); + // R8_EMMC_CONTROL |= RB_EMMC_NEGSMP; + R16_EMMC_CLK_DIV = RB_EMMC_CLKMode| + RB_EMMC_PHASEINV| + RB_EMMC_CLKOE | + 8; + return OP_SUCCESS; +} + +UINT8 EMMCCardConfig_N( PSD_PARAMETER pEMMCPara ) +{ + UINT8 sta; + + EMMCResetIdle( pEMMCPara ); + mDelaymS(30); + sta = EMMCReadOCR( pEMMCPara ); + if(sta!=CMD_SUCCESS) + { + return OP_FAILED; + } + sta = EMMCReadCID( pEMMCPara ); + if(sta!=CMD_SUCCESS) + { + return OP_FAILED; + } + mDelaymS(30); + sta = EMMCSetRCA( pEMMCPara ); + if(sta!=CMD_SUCCESS) + { + return OP_FAILED; + } + sta = EMMCReadCSD( pEMMCPara ); + if(sta!=CMD_SUCCESS) + { + return OP_FAILED; + } + mDelaymS(30); + sta = SelectEMMCCard( pEMMCPara ); + if(sta!=CMD_SUCCESS) + { + return OP_FAILED; + } + + R16_EMMC_CLK_DIV = RB_EMMC_CLKMode| + RB_EMMC_CLKOE | + LOWEMMCCLK; + sta = ReadEMMCStatus( pEMMCPara ); + if(sta!=CMD_SUCCESS) + { + return OP_FAILED; + } + if(pEMMCPara->EMMCSecNum == 0xFFF) + { + sta = EMMCCardReadEXCSD( pEMMCPara, buf ); + if(sta!=OP_SUCCESS) return OP_FAILED; + pEMMCPara->EMMCSecNum = *((PUINT32)&buf[212]); // SEC_COUNT [215:212] MSB-LSB + } + sta = EMMCSetBusWidth(pEMMCPara, 1); + if(sta!=CMD_SUCCESS) return OP_FAILED; + R8_EMMC_CONTROL = (R8_EMMC_CONTROL&~RB_EMMC_LW_MASK) | bLW_OP_DAT8; // 8line_mode + + //switching frequency + while(!(R32_EMMC_STATUS & (1<<17))); + sta = EMMCSetHighSpeed(pEMMCPara); + if(sta!=CMD_SUCCESS) return OP_FAILED; + while(!(R32_EMMC_STATUS & (1<<17))); + //configure higher clock rate + R16_EMMC_CLK_DIV = RB_EMMC_CLKMode| + RB_EMMC_CLKOE | + 4|RB_EMMC_PHASEINV; + return OP_SUCCESS; +} +/******************************************************************************* + * @fn EMMCIOTransErrorDeal + * + * @brief error processing + * + * @return OP_SUCCESS +*******************************************************************************/ +UINT8 EMMCIOTransErrorDeal( PSD_PARAMETER pEMMCPara ) +{ + pEMMCPara->EMMCOpErr = R16_EMMC_INT_FG; + R16_EMMC_INT_FG = 0xffff; + + return OP_SUCCESS; +} + +/******************************************************************************* + * @fn EMMCCardReadEXCSD + * + * @brief read single section + * + * @param pEMMCPara + * Lbaaddr - section first address + * + * @return OP_SUCCESS + **/ +UINT8 EMMCCardReadEXCSD( PSD_PARAMETER pEMMCPara, PUINT8 pRdatbuf ) +{ + UINT32 cmd_arg_val; + UINT16 cmd_set_val; + + R32_EMMC_DMA_BEG1 = (UINT32)pRdatbuf; + R32_EMMC_TRAN_MODE = 0; + R32_EMMC_BLOCK_CFG = 512<<16 | 1; + + cmd_arg_val = 0; + cmd_set_val = RB_EMMC_CKIDX | + RB_EMMC_CKCRC | + RESP_TYPE_48 | + EMMC_CMD8; + EMMCSendCmd(cmd_arg_val, cmd_set_val); + + while(1) + { + if(R16_EMMC_INT_FG & RB_EMMC_IF_TRANDONE) break; + if( pEMMCPara->EMMCOpErr ) return CMD_FAILED; + } + + R16_EMMC_INT_FG = 0xffff; + + return OP_SUCCESS; +} + + +/******************************************************************************* + * @fn EMMCCardReadOneSec + * + * @brief read single section + * + * @param pEMMCPara + * pRdatbuf -- read buffer address + * Lbaaddr + * + * @return OP_SUCCESS + **/ +UINT8 EMMCCardReadOneSec( PSD_PARAMETER pEMMCPara, PUINT8 pRdatbuf, UINT32 Lbaaddr ) +{ + UINT32 cmd_arg_val; + UINT16 cmd_set_val; + + if(Lbaaddr > (pEMMCPara->EMMCSecNum)) return OP_INVALID_ADD; + + R32_EMMC_DMA_BEG1 = (UINT32)pRdatbuf; + R32_EMMC_TRAN_MODE = 0; + R32_EMMC_BLOCK_CFG = (pEMMCPara->EMMCSecSize)<<16 | 1; + + cmd_arg_val = Lbaaddr; + cmd_set_val = RB_EMMC_CKIDX | + RB_EMMC_CKCRC | + RESP_TYPE_48 | + EMMC_CMD17; + EMMCSendCmd(cmd_arg_val, cmd_set_val); + + while(1) + { + if(R16_EMMC_INT_FG & RB_EMMC_IF_TRANDONE) break; + if( pEMMCPara->EMMCOpErr ) return CMD_FAILED; + } + + R16_EMMC_INT_FG = 0xffff; + + return OP_SUCCESS; +} + +/******************************************************************************* + * @fn EMMCCardReadMulSec + * + * @brief read continuous multiple sections + * + * @param pEMMCPara - + * pReqnum - request continuous sections address + * pRdatbuf - + * Lbaaddr - + * + * @return OP_SUCCESS + */ +UINT8 EMMCCardReadMulSec( PSD_PARAMETER pEMMCPara, PUINT16 pReqnum, PUINT8 pRdatbuf, UINT32 Lbaaddr ) +{ + UINT32 cmd_arg_val; + UINT16 cmd_set_val; + UINT8 sta; + + if(Lbaaddr > (pEMMCPara->EMMCSecNum)) return OP_INVALID_ADD; + + R32_EMMC_DMA_BEG1 = (UINT32)pRdatbuf; //data buffer address + R32_EMMC_TRAN_MODE = 0; //EMMC to controller + R32_EMMC_BLOCK_CFG = (pEMMCPara->EMMCSecSize)<<16 | (*pReqnum); + + //cmd18 + cmd_arg_val = Lbaaddr; + cmd_set_val = RB_EMMC_CKIDX | + RB_EMMC_CKCRC | + RESP_TYPE_48 | + EMMC_CMD18; + EMMCSendCmd(cmd_arg_val, cmd_set_val); + while(1) + { + if(R16_EMMC_INT_FG & RB_EMMC_IF_TRANDONE) + { + R16_EMMC_INT_FG = RB_EMMC_IF_CMDDONE; + //cmd12 + cmd_arg_val = 0; + cmd_set_val = RB_EMMC_CKIDX | + RB_EMMC_CKCRC | + RESP_TYPE_R1b | + EMMC_CMD12; + EMMCSendCmd(cmd_arg_val, cmd_set_val); + break; + } + if( pEMMCPara->EMMCOpErr ) return CMD_FAILED; + } + + while(1) + { + sta = CheckCMDComp( pEMMCPara ); + if( sta != CMD_NULL ) break; + } + + R16_EMMC_INT_FG = 0xffff; + *pReqnum = (UINT16)R32_EMMC_STATUS; // successfully transferred sections + + return sta; +} + +/******************************************************************************* + * @fn EMMCCardWriteMulSec + * @brief write continuous multiple sections + * @param pSDPara - + * pReqnum - + * pWdatbuf - + * Lbaaddr - + * @return OP_SUCCESS + **/ +UINT8 EMMCCardWriteMulSec( PSD_PARAMETER pEMMCPara, PUINT16 pReqnum, PUINT8 pWdatbuf, UINT32 Lbaaddr ) +{ + UINT32 cmd_arg_val; + UINT16 cmd_set_val; + UINT8 sta; + + if(Lbaaddr > (pEMMCPara->EMMCSecNum)) return OP_INVALID_ADD; + + //cmd25 + cmd_arg_val = Lbaaddr; + cmd_set_val = RB_EMMC_CKIDX | + RB_EMMC_CKCRC | + RESP_TYPE_48 | + EMMC_CMD25; + EMMCSendCmd(cmd_arg_val, cmd_set_val); + while(1) + { + sta = CheckCMDComp( pEMMCPara ); + if( sta != CMD_NULL ) break; + } + if( sta == CMD_FAILED ) return OP_FAILED; + + //DAT + + R32_EMMC_TRAN_MODE = RB_EMMC_DMA_DIR; + R32_EMMC_DMA_BEG1 = (UINT32)pWdatbuf; + R32_EMMC_BLOCK_CFG = (pEMMCPara->EMMCSecSize)<<16 | (*pReqnum); + + while(1) + { + if(R16_EMMC_INT_FG & RB_EMMC_IF_BKGAP) + { + R32_EMMC_RESPONSE3 = 0; + R16_EMMC_INT_FG = RB_EMMC_IF_BKGAP; + } + else if(R16_EMMC_INT_FG & RB_EMMC_IF_TRANDONE) + { + R16_EMMC_INT_FG = RB_EMMC_IF_CMDDONE; + //cmd12 + cmd_arg_val = 0; + cmd_set_val = RB_EMMC_CKIDX | + RB_EMMC_CKCRC | + RESP_TYPE_R1b | + EMMC_CMD12; + EMMCSendCmd(cmd_arg_val, cmd_set_val); + break; + } + if( pEMMCPara->EMMCOpErr ) return CMD_FAILED; + } + + while(1) + { + sta = CheckCMDComp( pEMMCPara ); + if( sta != CMD_NULL ) break; + } + + R16_EMMC_INT_FG = 0xffff; + *pReqnum = (UINT16)R32_EMMC_STATUS; + + return sta; +} + +/******************************************************************************* + * @fn AES_EMMCWriteMulSec + * + * @brief Write continuous multiple sections + * + * @param pEMMCPara - SD information structure pointer + * pReqnum - Request to the sector number variable address consecutively + * pWdatbuf - Write to the data cache address + * Lbaaddr - Write the sector head address continuously + * + * @return None + ***/ +UINT8 AES_EMMCWriteMulSec( PSD_PARAMETER pEMMCPara, PUINT32 pReqnum, PUINT32 pWdatbuf, UINT32 Lbaaddr, UINT8 excutemode, UINT8 endianmode, PUINT32 pcount) +{ + UINT32 cmd_arg_val; + UINT16 cmd_set_val; + UINT8 sta; + + if(Lbaaddr > (pEMMCPara->EMMCSecNum)) return OP_INVALID_ADD; + + //cmd25 + cmd_arg_val = Lbaaddr; + cmd_set_val = RB_EMMC_CKIDX | + RB_EMMC_CKCRC | + RESP_TYPE_48 | + EMMC_CMD25; + EMMCSendCmd(cmd_arg_val, cmd_set_val); + while(1) + { + sta = CheckCMDComp( pEMMCPara ); + if( sta != CMD_NULL ) break; + } + if( sta == CMD_FAILED ) return OP_FAILED; + + //DAT + + ECDC_Excute(excutemode, endianmode); + + R32_EMMC_TRAN_MODE |= RB_EMMC_DMA_DIR; + R32_EMMC_DMA_BEG1 = (UINT32)pWdatbuf; + R32_EMMC_BLOCK_CFG = (pEMMCPara->EMMCSecSize)<<16 | (*pReqnum); + + while(1) + { + if(R16_EMMC_INT_FG & RB_EMMC_IF_BKGAP) + { + ///////////////////////////////////////////////CTR mode + if(R16_ECEC_CTRL & RB_ECDC_CIPHER_MOD) + ECDC_RloadCount( excutemode, endianmode, pcount ); + + R32_EMMC_RESPONSE3 = 0; //start transform + R16_EMMC_INT_FG |= RB_EMMC_IF_BKGAP; + } + else if(R16_EMMC_INT_FG & RB_EMMC_IF_TRANDONE) + { + R16_EMMC_INT_FG = RB_EMMC_IF_CMDDONE; + //cmd12 + cmd_arg_val = 0; + cmd_set_val = RB_EMMC_CKIDX | + RB_EMMC_CKCRC | + RESP_TYPE_R1b | + EMMC_CMD12; + EMMCSendCmd(cmd_arg_val, cmd_set_val); + break; + } + if( pEMMCPara->EMMCOpErr ) return CMD_FAILED; + } + while(1) + { + sta = CheckCMDComp( pEMMCPara ); + if( sta != CMD_NULL ) break; + } + + R16_EMMC_INT_FG = 0xffff; + *pReqnum = (UINT16)R32_EMMC_STATUS; //the number of blocks transferred successfully + + return sta; +} + +/******************************************************************************* + * @fn AES_EMMCReadMulSec + * + * @brief Read continuous multiple sections + * + * @param pEMMCPara - SD information structure pointer + * pReqnum - Request to the sector number variable address consecutively + * pWdatbuf - Write to the data cache address + * Lbaaddr - Write the sector head address continuously + * + * @return OP_SUCCESS - suc + * other - err + **/ +UINT8 AES_EMMCReadMulSec( PSD_PARAMETER pEMMCPara, PUINT32 pReqnum, PUINT32 pRdatbuf, UINT32 Lbaaddr, UINT8 excutemode, UINT8 endianmode, PUINT32 pcount) +{ + UINT32 cmd_arg_val; + UINT16 cmd_set_val; + + if(Lbaaddr > (pEMMCPara->EMMCSecNum)) return OP_INVALID_ADD; + + //CTR mode.Once the transmission is completed ,turn off the clock. + if(R16_ECEC_CTRL & RB_ECDC_CIPHER_MOD) + { + R16_ECEC_CTRL &= 0xFFF9; //bit2 and bit3 set 0 + ECDC_SetCount(pcount); + R32_EMMC_TRAN_MODE |= RB_EMMC_AUTOGAPSTOP | RB_EMMC_GAP_STOP; + } + + ECDC_Excute(excutemode, endianmode); + + R32_EMMC_DMA_BEG1 = (UINT32)pRdatbuf; + R32_EMMC_TRAN_MODE &= ~RB_EMMC_DMA_DIR; + R32_EMMC_BLOCK_CFG = (pEMMCPara->EMMCSecSize)<<16 | (*pReqnum); + + //cmd18 + cmd_arg_val = Lbaaddr; + cmd_set_val = RB_EMMC_CKIDX | + RB_EMMC_CKCRC | + RESP_TYPE_48 | + EMMC_CMD18; + EMMCSendCmd(cmd_arg_val, cmd_set_val); + + while(1) + { + if(R16_ECEC_CTRL & RB_ECDC_CIPHER_MOD) + { + if(R16_EMMC_INT_FG & RB_EMMC_IF_BKGAP) + { + /* CTR mode */ + if(R16_ECEC_CTRL & RB_ECDC_CIPHER_MOD) + ECDC_RloadCount( excutemode, endianmode, pcount ); + + R32_EMMC_TRAN_MODE &= ~RB_EMMC_GAP_STOP; + R16_EMMC_INT_FG |= RB_EMMC_IF_BKGAP; + } + } + if(R16_EMMC_INT_FG & RB_EMMC_IF_TRANDONE) break; + if( pEMMCPara->EMMCOpErr ) return CMD_FAILED; + } + + + R16_EMMC_INT_FG = 0xffff; + *pReqnum = (UINT16)R32_EMMC_STATUS; //the number of blocks transferred successfully + + return OP_SUCCESS; +} + + diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_eth.c b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_eth.c new file mode 100644 index 000000000..9f2f7e173 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_eth.c @@ -0,0 +1,315 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : CH56x_eth.c +* Author : WCH +* Version : V1.0 +* Date : 2023/03/03 +* Description : This file provides all the ETH firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + +#include "CH56x_common.h" + +ETH_DMADESCTypeDef *DMATxDescToSet; +ETH_DMADESCTypeDef *DMARxDescToGet; + +/********************************************************************* + * @fn ETH_StructInit + * + * @brief Fills each ETH_InitStruct member with its default value. + * + * @param ETH_InitStruct - pointer to a ETH_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void ETH_StructInit(ETH_InitTypeDef *ETH_InitStruct) +{ + /*------------------------ MAC -----------------------------------*/ + ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable; + ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable; + ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable; + ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit; + ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable; + ETH_InitStruct->ETH_Speed = ETH_Speed_10M; + ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable; + ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable; + ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; + ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable; + ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable; + ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; + ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10; + ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable; + ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable; + ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable; + ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll; + ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; + ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal; + ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; + ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; + ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; + ETH_InitStruct->ETH_HashTableHigh = 0x0; + ETH_InitStruct->ETH_HashTableLow = 0x0; + ETH_InitStruct->ETH_PauseTime = 0x0; + ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable; + ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4; + ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable; + ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable; + ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable; + ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit; + ETH_InitStruct->ETH_VLANTagIdentifier = 0x0; + /*------------------------ DMA -----------------------------------*/ + ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; + ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; + ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Enable; + ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; + ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes; + ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; + ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes; + ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable; + ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; + ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable; + ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat; + ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat; + ETH_InitStruct->ETH_DescriptorSkipLength = 0x0; + ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1; +} + +/******************************************************************************* + * @fn ETH_SoftwareReset + * + * @brief ETH software reset + * + * @return None + */ +void ETH_SoftwareReset(void) +{ + /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ + /* After reset all the registers holds their respective reset values */ + ETH->DMABMR |= ETH_DMABMR_SR; +} + +/******************************************************************************* + * @fn RGMII_TXC_Delay + * + * @brief ETH send clock polarity and timing adjustment + * + * @param clock_polarity - send clock polarity + * delay_time - delay time(unit - half nanosecond) + * + * @return None + */ +void RGMII_TXC_Delay(uint8_t clock_polarity,uint8_t delay_time) +{ + if(clock_polarity) + ETH->MACCR |= (uint32_t)(1<<1); + else + ETH->MACCR &= ~(uint32_t)(1<<1); + + if(delay_time <= 7) + ETH->MACCR |= (uint32_t)(delay_time<<29); + else + printf("Error:delay_time is out of range!\n"); +} + +/******************************************************************************* + * @fn ETH_ReadPHYRegister + * + * @brief Read PHY register + * + * @param PHYAddress - PHY address + * PHYReg - PHY register address + * + * @return Value of PHY register + */ +uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg) +{ + uint32_t tmpreg = 0; + uint32_t timeout = 0; + + /* Get the ETHERNET MACMIIAR value */ + tmpreg = ETH->MACMIIAR; + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg &= ~MACMIIAR_CR_MASK; + /* Prepare the MII address register value */ + tmpreg |= (((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + tmpreg |= (((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */ + tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + /* Write the result value into the MII Address register */ + ETH->MACMIIAR = tmpreg; + /* Check for the Busy flag */ + do + { + timeout++; + tmpreg = ETH->MACMIIAR; + } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_READ_TO) + { + return (uint16_t)ETH_ERROR; + } + /* Return data register value */ + return (uint16_t)(ETH->MACMIIDR); +} + +/******************************************************************************* + * @fn ETH_WritePHYRegister + * + * @brief Write PHY register + * + * @param PHYAddress - PHY address + * PHYReg - PHY register address + * PHYValue - Value will be written of PHY register + * + * @return Execution status + */ +uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue) +{ + uint32_t tmpreg = 0; + uint32_t timeout = 0; + + /* Get the ETHERNET MACMIIAR value */ + tmpreg = ETH->MACMIIAR; + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg &= ~MACMIIAR_CR_MASK; + /* Prepare the MII register address value */ + tmpreg |= (((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + tmpreg |= (((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */ + tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + /* Give the value to the MII data register */ + ETH->MACMIIDR = PHYValue; + /* Write the result value into the MII Address register */ + ETH->MACMIIAR = tmpreg; + /* Check for the Busy flag */ + do + { + timeout++; + tmpreg = ETH->MACMIIAR; + } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_WRITE_TO) + { + return ETH_ERROR; + } + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/******************************************************************************* + * @fn ETH_DMAITConfig + * + * @brief Configuration DMA interrupt + * + * @param ETH_DMA_IT - Type of DMA interrupt + * NewState - Enable DMA interrupt or Disable DMA interrupt + * + * @return None + */ +void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET DMA interrupts */ + ETH->DMAIER |= ETH_DMA_IT; + } + else + { + /* Disable the selected ETHERNET DMA interrupts */ + ETH->DMAIER &= ~(uint32_t)ETH_DMA_IT; + } +} + +/******************************************************************************* + * @fn ETH_DMAClearITPendingBit + * + * @brief Clear DMA interrupt flag + * + * @param ETH_DMA_IT - Type of DMA interrupt + * + * @return None + */ +void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT) +{ + /* Clear the selected ETHERNET DMA IT */ + ETH->DMASR = (uint32_t) ETH_DMA_IT; +} + +/******************************************************************************* + * @fn ETH_DMATxDescChainInit + * + * @brief transmit descriptor initialization + * + * @param DMARxDescTab - pointer to the transmit descriptor table + * RxBuff - pointer to the transmit buffer (transmit queue) + * RxBuffCount - Number of transmit descriptor or transmit queue + * + * @return None + */ +void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount) +{ + uint8_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + DMATxDescToSet = DMATxDescTab; + + for(i = 0; i < TxBuffCount; i++) + { + DMATxDesc = DMATxDescTab + i; + DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_IC; + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i * ETH_MAX_PACKET_SIZE]); + + if(i < (TxBuffCount - 1)) + { + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab + i + 1); + } + else + { + DMATxDesc->Buffer2NextDescAddr = (uint32_t)DMATxDescTab; + } + } + + ETH->DMATDLAR = (uint32_t)DMATxDescTab; +} + +/******************************************************************************* + * @fn ETH_DMARxDescChainInit + * + * @brief Receive descriptor initialization + * + * @param DMARxDescTab - pointer to the receive descriptor table + * RxBuff - pointer to the receive buffer (receive queue) + * RxBuffCount - Number of receive descriptor or receive queue + * + * @return None + **/ +void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) +{ + uint8_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + DMARxDescToGet = DMARxDescTab; + + for(i = 0; i < RxBuffCount; i++) + { + DMARxDesc = DMARxDescTab + i; + DMARxDesc->Status = ETH_DMARxDesc_OWN; + DMARxDesc->ControlBufferSize = (uint32_t)ETH_MAX_PACKET_SIZE; + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i * ETH_MAX_PACKET_SIZE]); + + if(i < (RxBuffCount - 1)) + { + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab + i + 1); + } + else + { + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + } + } + + ETH->DMARDLAR = (uint32_t)DMARxDescTab; +} diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_gpio.c b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_gpio.c new file mode 100644 index 000000000..8e425c913 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_gpio.c @@ -0,0 +1,523 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : CH56x_gpio.c +* Author : WCH +* Version : V1.0 +* Date : 2020/07/31 +* Description : +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + +#include "CH56x_common.h" + + +/******************************************************************************* + * @fn GPIOA_ModeCfg + * + * @brief GPIOA port pin mode configuration + * + * @param pin - PA0-PA15 + * GPIO_Pin_0 - GPIO_Pin_15 + * mode - + * GPIO_ModeIN_Floating - Floating input/high impedance input + * GPIO_ModeIN_PU_NSMT - Input with pull-up resistor + * GPIO_ModeIN_PD_NSMT - Input with pull-down resistor + * GPIO_ModeIN_PU_SMT - Schmitt input with pull-up resistor + * GPIO_ModeIN_PD_SMT - Schmitt input with pull-down resistor + * GPIO_Slowascent_PP_8mA - Low slope push-pull output, drive capability 8mA level + * GPIO_Slowascent_PP_16mA - Low slope push-pull output, drive capability 16mA level + * GPIO_Highspeed_PP_8mA - Fast push-pull output, drive capability 8mA level + * GPIO_Highspeed_PP_16mA - Fast push-pull output, drive capability 16mA level + * GPIO_ModeOut_OP_8mA - Push-pull output up to 8mA + * GPIO_ModeOut_OP_16mA - Push-pull output up to 16mA + * + * @return None + */ +void GPIOA_ModeCfg( UINT32 pin, GPIOModeTypeDef mode ) +{ + switch(mode) + { + case GPIO_ModeIN_Floating: + R32_PA_PD &= ~pin; + R32_PA_PU &= ~pin; + R32_PA_DIR &= ~pin; + break; + + case GPIO_ModeIN_PU_NSMT: + R32_PA_SMT &=~ pin; + R32_PA_PD &= ~pin; + R32_PA_PU |= pin; + R32_PA_DIR &= ~pin; + break; + + case GPIO_ModeIN_PD_NSMT: + R32_PA_SMT &=~ pin; + R32_PA_PD |= pin; + R32_PA_PU &= ~pin; + R32_PA_DIR &= ~pin; + break; + + case GPIO_ModeIN_PU_SMT: + R32_PA_SMT |= pin; + R32_PA_PD &= ~pin; + R32_PA_PU |= pin; + R32_PA_DIR &= ~pin; + break; + + case GPIO_ModeIN_PD_SMT: + R32_PA_SMT |= pin; + R32_PA_PD |= pin; + R32_PA_PU &= ~pin; + R32_PA_DIR &= ~pin; + break; + + case GPIO_Slowascent_PP_8mA: + R32_PA_SMT |= pin; + R32_PA_DRV &= ~pin; + R32_PA_PD &= ~pin; + R32_PA_DIR |= pin; + break; + + case GPIO_Slowascent_PP_16mA: + R32_PA_SMT |= pin; + R32_PA_DRV |= pin; + R32_PA_PD &= ~pin; + R32_PA_DIR |= pin; + break; + + case GPIO_Highspeed_PP_8mA: + R32_PA_SMT &= ~pin; + R32_PA_DRV &= ~pin; + R32_PA_PD &= ~pin; + R32_PA_DIR |= pin; + break; + + case GPIO_Highspeed_PP_16mA: + R32_PA_SMT &= ~pin; + R32_PA_DRV |= pin; + R32_PA_PD &= ~pin; + R32_PA_DIR |= pin; + break; + + case GPIO_ModeOut_OP_8mA: + R32_PA_DRV &= ~pin; + R32_PA_PD |= pin; + R32_PA_DIR |= pin; + break; + + case GPIO_ModeOut_OP_16mA: + R32_PA_DRV |= pin; + R32_PA_PD |= pin; + R32_PA_DIR |= pin; + break; + + default: + break; + } +} + +/******************************************************************************* + * @fn GPIOB_ModeCfg + * + * @brief GPIOB port pin mode configuration + * + * @param pin - PB0-PB15 + * GPIO_Pin_0 - GPIO_Pin_15 + * mode - + * GPIO_ModeIN_Floating - Floating input/high impedance input + * GPIO_ModeIN_PU_NSMT - Input with pull-up resistor + * GPIO_ModeIN_PD_NSMT - Input with pull-down resistor + * GPIO_ModeIN_PU_SMT - Schmitt input with pull-up resistor + * GPIO_ModeIN_PD_SMT - Schmitt input with pull-down resistor + * GPIO_Slowascent_PP_8mA - Low slope push-pull output, drive capability 8mA level + * GPIO_Slowascent_PP_16mA - Low slope push-pull output, drive capability 16mA level + * GPIO_Highspeed_PP_8mA - Fast push-pull output, drive capability 8mA level + * GPIO_Highspeed_PP_16mA - Fast push-pull output, drive capability 16mA level + * GPIO_ModeOut_OP_8mA - Push-pull output up to 8mA + * GPIO_ModeOut_OP_16mA - Push-pull output up to 16mA + * + * @return None + */ + +void GPIOB_ModeCfg( UINT32 pin, GPIOModeTypeDef mode ) +{ + switch(mode) + { + case GPIO_ModeIN_Floating: + R32_PB_PD &= ~pin; + R32_PB_PU &= ~pin; + R32_PB_DIR &= ~pin; + break; + + case GPIO_ModeIN_PU_NSMT: + R32_PB_SMT &=~ pin; + R32_PB_PD &= ~pin; + R32_PB_PU |= pin; + R32_PB_DIR &= ~pin; + break; + + case GPIO_ModeIN_PD_NSMT: + R32_PB_SMT &=~ pin; + R32_PB_PD |= pin; + R32_PB_PU &= ~pin; + R32_PB_DIR &= ~pin; + break; + + case GPIO_ModeIN_PU_SMT: + R32_PB_SMT |= pin; + R32_PB_PD &= ~pin; + R32_PB_PU |= pin; + R32_PB_DIR &= ~pin; + break; + + case GPIO_ModeIN_PD_SMT: + R32_PB_SMT |= pin; + R32_PB_PD |= pin; + R32_PB_PU &= ~pin; + R32_PB_DIR &= ~pin; + break; + + case GPIO_Slowascent_PP_8mA: + R32_PB_SMT |= pin; + R32_PB_DRV &= ~pin; + R32_PB_PD &= ~pin; + R32_PB_DIR |= pin; + break; + + case GPIO_Slowascent_PP_16mA: + R32_PB_SMT |= pin; + R32_PB_DRV |= pin; + R32_PB_PD &= ~pin; + R32_PB_DIR |= pin; + break; + + case GPIO_Highspeed_PP_8mA: + R32_PB_SMT &= ~pin; + R32_PB_DRV &= ~pin; + R32_PB_PD &= ~pin; + R32_PB_DIR |= pin; + break; + + case GPIO_Highspeed_PP_16mA: + R32_PB_SMT &= ~pin; + R32_PB_DRV |= pin; + R32_PB_PD &= ~pin; + R32_PB_DIR |= pin; + break; + + case GPIO_ModeOut_OP_8mA: + R32_PB_DRV &= ~pin; + R32_PB_PD |= pin; + R32_PB_DIR |= pin; + break; + + case GPIO_ModeOut_OP_16mA: + R32_PB_DRV |= pin; + R32_PB_PD |= pin; + R32_PB_DIR |= pin; + break; + + default: + break; + } +} + +/******************************************************************************* + * @fn GPIOA_ITModeCfg + * + * @brief GPIOA pin interrupt mode configuration + * + * @param pin - PA2-PA4 + * mode - + * GPIO_ITMode_LowLevel - Low level trigger + * GPIO_ITMode_HighLevel - High level trigger + * GPIO_ITMode_FallEdge - Falling edge trigger + * GPIO_ITMode_RiseEdge - Rising edge trigger + * + * @return None + */ +void GPIOA_ITModeCfg( UINT32 pin, GPIOITModeTpDef mode ) +{ + switch( mode ) + { + case GPIO_ITMode_LowLevel: // Low level trigger + R32_PA_DIR &= ~pin; + R8_GPIO_INT_MODE &= ~(pin>>2); + R8_GPIO_INT_POLAR &= ~(pin>>2); + break; + + case GPIO_ITMode_HighLevel: // High level trigger + R32_PA_DIR &= ~pin; + R8_GPIO_INT_MODE &= ~(pin>>2); + R8_GPIO_INT_POLAR |= (pin>>2); + break; + + case GPIO_ITMode_FallEdge: // Falling edge trigger + R32_PA_DIR &= ~pin; + R8_GPIO_INT_MODE |= (pin>>2); + R8_GPIO_INT_POLAR &= ~(pin>>2); + break; + + case GPIO_ITMode_RiseEdge: // Rising edge trigger + R32_PA_DIR &= ~pin; + R8_GPIO_INT_MODE |= (pin>>2); + R8_GPIO_INT_POLAR |= (pin>>2); + break; + + default : + break; + } + R8_GPIO_INT_FLAG = (pin>>2); + R8_GPIO_INT_ENABLE |= (pin>>2); +} + +/******************************************************************************* + * @fn GPIOB_ITModeCfg + * + * @brief GPIOB pin interrupt mode configuration + * + * @param pin - PB3-PB4-PB11-PB12-PB15 + * mode - + * GPIO_ITMode_LowLevel - Low level trigger + * GPIO_ITMode_HighLevel - High level trigger + * GPIO_ITMode_FallEdge - Falling edge trigger + * GPIO_ITMode_RiseEdge - Rising edge trigger + * + * @return None + */ + +void GPIOB_ITModeCfg( UINT32 pin, GPIOITModeTpDef mode ) +{ + switch( mode ) + { + case GPIO_ITMode_LowLevel: // Low level trigger + if(pin==GPIO_Pin_3) + { + R32_PB_DIR &= ~(1<<3); + R8_GPIO_INT_MODE &= ~(1<<3); + R8_GPIO_INT_POLAR &= ~(1<<3); + R8_GPIO_INT_FLAG = (1<<3); + R8_GPIO_INT_ENABLE |= (1<<3); + } + else if(pin==GPIO_Pin_4) + { + R32_PB_DIR &= ~(1<<4); + R8_GPIO_INT_MODE &= ~(1<<4); + R8_GPIO_INT_POLAR &= ~(1<<4); + R8_GPIO_INT_FLAG = (1<<4); + R8_GPIO_INT_ENABLE |= (1<<4); + } + else if(pin==GPIO_Pin_11) + { + R32_PB_DIR &= ~(1<<11); + R8_GPIO_INT_MODE &= ~(1<<5); + R8_GPIO_INT_POLAR &= ~(1<<5); + R8_GPIO_INT_FLAG = (1<<5); + R8_GPIO_INT_ENABLE |= (1<<5); + } + else if(pin==GPIO_Pin_12) + { + R32_PB_DIR &= ~(1<<12); + R8_GPIO_INT_MODE &= ~(1<<6); + R8_GPIO_INT_POLAR &= ~(1<<6); + R8_GPIO_INT_FLAG = (1<<6); + R8_GPIO_INT_ENABLE |= (1<<6); + } + else if(pin==GPIO_Pin_15) + { + R32_PB_DIR &= ~(1<<15); + R8_GPIO_INT_MODE &= ~(1<<7); + R8_GPIO_INT_POLAR &= ~(1<<7); + R8_GPIO_INT_FLAG = (1<<7); + R8_GPIO_INT_ENABLE |= (1<<7); + } + break; + + case GPIO_ITMode_HighLevel: // High level trigger + if(pin==GPIO_Pin_3) + { + R32_PB_DIR &= ~(1<<3); + R8_GPIO_INT_MODE &= ~(1<<3); + R8_GPIO_INT_POLAR |= (1<<3); + R8_GPIO_INT_FLAG = (1<<3); + R8_GPIO_INT_ENABLE |= (1<<3); + } + else if(pin==GPIO_Pin_4) + { + R32_PB_DIR &= ~(1<<4); + R8_GPIO_INT_MODE &= ~(1<<4); + R8_GPIO_INT_POLAR |= (1<<4); + R8_GPIO_INT_FLAG = (1<<4); + R8_GPIO_INT_ENABLE |= (1<<4); + } + else if(pin==GPIO_Pin_11) + { + R32_PB_DIR &= ~(1<<11); + R8_GPIO_INT_MODE &= ~(1<<5); + R8_GPIO_INT_POLAR |= (1<<5); + R8_GPIO_INT_FLAG = (1<<5); + R8_GPIO_INT_ENABLE |= (1<<5); + } + else if(pin==GPIO_Pin_12) + { + R32_PB_DIR &= ~(1<<12); + R8_GPIO_INT_MODE &= ~(1<<6); + R8_GPIO_INT_POLAR |= (1<<6); + R8_GPIO_INT_FLAG = (1<<6); + R8_GPIO_INT_ENABLE |= (1<<6); + } + else if(pin==GPIO_Pin_15) + { + R32_PB_DIR &= ~(1<<15); + R8_GPIO_INT_MODE &= ~(1<<7); + R8_GPIO_INT_POLAR |= (1<<7); + R8_GPIO_INT_FLAG = (1<<7); + R8_GPIO_INT_ENABLE |= (1<<7); + } + break; + + case GPIO_ITMode_FallEdge: // Falling edge trigger + if(pin==GPIO_Pin_3) + { + R32_PB_DIR &= ~(1<<3); + R8_GPIO_INT_MODE |= (1<<3); + R8_GPIO_INT_POLAR &= ~(1<<3); + R8_GPIO_INT_FLAG = (1<<3); + R8_GPIO_INT_ENABLE |= (1<<3); + } + else if(pin==GPIO_Pin_4) + { + R32_PB_DIR &= ~(1<<4); + R8_GPIO_INT_MODE |= (1<<4); + R8_GPIO_INT_POLAR &= ~(1<<4); + R8_GPIO_INT_FLAG = (1<<4); + R8_GPIO_INT_ENABLE |= (1<<4); + } + else if(pin==GPIO_Pin_11) + { + R32_PB_DIR &= ~(1<<11); + R8_GPIO_INT_MODE |= (1<<5); + R8_GPIO_INT_POLAR &= ~(1<<5); + R8_GPIO_INT_FLAG = (1<<5); + R8_GPIO_INT_ENABLE |= (1<<5); + } + else if(pin==GPIO_Pin_12) + { + R32_PB_DIR &= ~(1<<12); + R8_GPIO_INT_MODE |= (1<<6); + R8_GPIO_INT_POLAR &= ~(1<<6); + R8_GPIO_INT_FLAG = (1<<6); + R8_GPIO_INT_ENABLE |= (1<<6); + } + else if(pin==GPIO_Pin_15) + { + R32_PB_DIR &= ~(1<<15); + R8_GPIO_INT_MODE |= (1<<7); + R8_GPIO_INT_POLAR &= ~(1<<7); + R8_GPIO_INT_FLAG = (1<<7); + R8_GPIO_INT_ENABLE |= (1<<7); + } + break; + + + case GPIO_ITMode_RiseEdge: // Rising edge trigger + if(pin==GPIO_Pin_3) + { + R32_PB_DIR &= ~(1<<3); + R8_GPIO_INT_MODE |= (1<<3); + R8_GPIO_INT_POLAR |= (1<<3); + R8_GPIO_INT_FLAG = (1<<3); + R8_GPIO_INT_ENABLE |= (1<<3); + } + else if(pin==GPIO_Pin_4) + { + R32_PB_DIR &= ~(1<<4); + R8_GPIO_INT_MODE |= (1<<4); + R8_GPIO_INT_POLAR |= (1<<4); + R8_GPIO_INT_FLAG = (1<<4); + R8_GPIO_INT_ENABLE |= (1<<4); + } + else if(pin==GPIO_Pin_11) + { + R32_PB_DIR &= ~(1<<11); + R8_GPIO_INT_MODE |= (1<<5); + R8_GPIO_INT_POLAR |= (1<<5); + R8_GPIO_INT_FLAG = (1<<5); + R8_GPIO_INT_ENABLE |= (1<<5); + } + else if(pin==GPIO_Pin_12) + { + R32_PB_DIR &= ~(1<<12); + R8_GPIO_INT_MODE |= (1<<6); + R8_GPIO_INT_POLAR |= (1<<6); + R8_GPIO_INT_FLAG = (1<<6); + R8_GPIO_INT_ENABLE |= (1<<6); + } + else if(pin==GPIO_Pin_15) + { + R32_PB_DIR &= ~(1<<15); + R8_GPIO_INT_MODE |= (1<<7); + R8_GPIO_INT_POLAR |= (1<<7); + R8_GPIO_INT_FLAG = (1<<7); + R8_GPIO_INT_ENABLE |= (1<<7); + } + break; + + default : + break; + } +} + +/******************************************************************************* + * @fn GPIOPinRemap + * + * @brief Peripheral Function Pin Mapping + * + * @param s - + * ENABLE - pin map + * DISABLE - default pin + * perph - + * RB_PIN_UART0 - RXD0 - PB5 -> PA5 + * - TXD0 - PB6 -> PA6 + * RB_PIN_TMR2 - TMR2/PWM6/CAP2 - PA4 -> PB3 + * RB_PIN_TMR1 - TMR1/PWM5/CAP1 - PB15 -> PB0 + * RB_PIN_MII - Ethernet - RMII -> RGMII + * @return None + */ +void GPIOPinRemap( UINT8 s, UINT16 perph ) +{ + if( s ) R8_PIN_ALTERNATE |= perph; + else R8_PIN_ALTERNATE &= ~perph; +} + +/******************************************************************************* + * @fn GPIOMco + * + * @brief GPIO MCO mode configuration + * + * @param s - ENABLE\DISABLE + * mode- + * MCO_125, + * MCO_25, + * MCO_2d5, + * @return None + */ +void GPIOMco( UINT8 s, UINT16 freq ) +{ + if(s) + { + R8_SAFE_ACCESS_SIG = 0x57; + R8_SAFE_ACCESS_SIG = 0xa8; + + R8_CLK_MOD_AUX = 0x10; + R8_CLK_MOD_AUX |=0x01; + R8_CLK_MOD_AUX |= freq; + } + else R8_CLK_MOD_AUX &= ~(1<<4); +} + + + + diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_hspi.c b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_hspi.c new file mode 100644 index 000000000..3cac44fa3 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_hspi.c @@ -0,0 +1,75 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : CH56x_hspi.c +* Author : WCH +* Version : V1.0 +* Date : 2020/07/31 +* Description : +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + +#include "CH56x_common.h" + + +/******************************************************************************* + * @fn HSPI_Mode + * + * @brief DVP mode + * + * @param s - data width + * RB_HPIF_DAT8_MOD - 8-bit mode + * RB_HPIF_DAT16_MOD - 16-bit mode + * RB_HPIF_DAT32_MOD - 32-bit mode + * i - Operating mode + * UP_Mode - Enable upper mode + * DOWN_Mode - Enable downside mode + * + * @return None + */ +void HSPI_Mode( UINT8 s, HSPI_ModeTypeDef i) +{ + R8_HSPI_CFG &= ~RB_HSPI_MSK_SIZE; //Restore default mode 8bit mode + + if(s){ + R8_HSPI_CFG |= s; + } + else{ + R8_HSPI_CFG &= ~RB_HSPI_MSK_SIZE; + } + + if(i){ + R8_HSPI_CFG |= RB_HSPI_MODE; + } + else{ + R8_HSPI_CFG &= ~RB_HSPI_MODE; + } +} + +/******************************************************************************* + * @fn HSPI_INTCfg + * + * @brief HSPI interrupt configuration + * + * @param s - interrupt control status + * ENABLE - Enable corresponding interrupt + * DISABLE - Disable the corresponding interrupt + * i - interrupt type + * RB_HSPI_IE_T_DONE - Burst Sequence Transmit Complete Interrupt + * RB_HSPI_IE_R_DONE - Receive FIFO overflow interrupt + * RB_HSPI_IE_FIFO_OV - Single packet receive complete interrupt + * RB_HSPI_IE_B_DONE - Guaranteed Send Complete Interrupt + * + * @return None + */ +void HSPI_INTCfg( UINT8 s, UINT8 i ) +{ + if(s){ + R8_HSPI_INT_EN |= i; + } + else{ + R8_HSPI_INT_EN &= ~i; + } +} + diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_pwm.c b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_pwm.c new file mode 100644 index 000000000..dfff9d065 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_pwm.c @@ -0,0 +1,76 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : CH56x_pwm.c +* Author : WCH +* Version : V1.0 +* Date : 2020/07/31 +* Description : +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + +#include "CH56x_common.h" + + +/******************************************************************************* + * @fn PWMX_CycleCfg + * + * @brief PWM0-PWM3 reference clock configuration + * + * @param cyc - + * + * @return None + */ +void PWMX_CycleCfg( PWMX_CycleTypeDef cyc ) +{ + switch( cyc ) + { + case PWMX_Cycle_256: + R8_PWM_CTRL_CFG &= ~RB_PWM_CYCLE_SEL; //PWM configuration control register, clock cycle selection + break; + + case PWMX_Cycle_255: + R8_PWM_CTRL_CFG |= RB_PWM_CYCLE_SEL; + break; + + default : + break; + } +} + +/******************************************************************************* + * @fn PWMX_ACTOUT + * + * @brief PWM0-PWM3 channel output waveform configuration + * + * @param ch - select channel of pwm + * refer to channel of PWM define + * da - effective pulse width + * pr - select wave polar + * refer to PWMX_PolarTypeDef + * s - control pwmx function + * ENABLE - Output PWM + * DISABLE - turn off PWM + * @return None + */ +void PWMX_ACTOUT( UINT8 ch, UINT8 da, PWMX_PolarTypeDef pr, UINT8 s) +{ + UINT8 i; + + if(s == DISABLE) R8_PWM_CTRL_MOD &= ~(ch); //Determine whether the PWM output is enabled + else + { + + (pr)?(R8_PWM_CTRL_MOD|=(ch<<4)):(R8_PWM_CTRL_MOD&=~(ch<<4)); //PWM output polarity control 1: Default high level, low active; 0: Default low level, high active + for(i=0; i<4; i++){ + if((ch>>i)&1) *((PUINT8V)((&R8_PWM0_DATA)+i)) = da; + } + R8_PWM_CTRL_MOD |= (ch); + } +} + + + + + diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_pwr.c b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_pwr.c new file mode 100644 index 000000000..a4074a137 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_pwr.c @@ -0,0 +1,173 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : CH56x_pwr.c +* Author : WCH +* Version : V1.0 +* Date : 2020/07/31 +* Description : +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + +#include "CH56x_common.h" + + +/******************************************************************************* + * @fn PWR_PeriphClkCfg + * + * @brief Peripheral Clock Control Bits + * @param s - + * ENABLE - Turn on the peripheral clock + * DISABLE - Turn off peripheral clock + * perph - + * please refer to Peripher CLK control bit define + + * @return None + */ +void PWR_PeriphClkCfg( UINT8 s, UINT16 perph ) +{ + if( s == DISABLE ) + { + R8_SAFE_ACCESS_SIG = 0x57; + R8_SAFE_ACCESS_SIG = 0xA8; + R32_SLEEP_CONTROL |= perph; + } + else + { + R8_SAFE_ACCESS_SIG = 0x57; + R8_SAFE_ACCESS_SIG = 0xA8; + R32_SLEEP_CONTROL &= ~perph; + } + R8_SAFE_ACCESS_SIG = 0; +} + +/******************************************************************************* + * @fn PWR_PeriphWakeUpCfg + * + * @brief Sleep wakeup source configuration + * + * @param s - + * ENABLE - Turn on this peripheral's wake-from-sleep feature + * DISABLE - Turn off this peripheral sleep wake function + * perph - + * RB_SLP_USBHS_WAKE - USB2.0 is the wake-up source + * RB_SLP_USBSS_WAKE - USB3.0 is the wake-up source + * RB_SLP_GPIO_WAKE - GPIO is the wake-up source + * RB_SLP_ETH_WAKE - ETH is the wakeup source + * ALL - all of above + * @return None + */ +void PWR_PeriphWakeUpCfg( UINT8 s, UINT16 perph ) +{ + if( s == DISABLE ) + { + R8_SAFE_ACCESS_SIG = 0x57; + R8_SAFE_ACCESS_SIG = 0xA8; + R8_SLP_WAKE_CTRL &= ~perph; + } + else + { + R8_SAFE_ACCESS_SIG = 0x57; + R8_SAFE_ACCESS_SIG = 0xA8; + R8_SLP_WAKE_CTRL |= perph; + } + R8_SAFE_ACCESS_SIG = 0; +} + +/******************************************************************************* + * @fn LowPower_Idle + * + * @brief Low power consumption - Enter Idle mode with WFI instruction + * + * @return None + */ +void LowPower_Idle( void ) +{ + PFIC->SCTLR &= ~1<<2; // Set the SleepDeep field of the core PFIC SCTLR register to 0 + __WFI(); // Execute __WFI() after setting the wake-up condition +} + +/******************************************************************************* + * @fn LowPower_Idle_WFE + * + * @brief Low power consumption - Enter Idle mode with WFE instruction + * + * @return None + */ +void LowPower_Idle_WFE( void ) +{ + PFIC->SCTLR &= ~1<<2; // Set the SleepDeep field of the core PFIC SCTLR register to 0 + __WFE(); // Execute __WFE() after setting the wake-up condition +} + +/******************************************************************************* + * @fn LowPower_Halt + * + * @brief Low power consumption - Enter Halt mode with WFI instruction + * + * @return None + */ +void LowPower_Halt( void ) +{ + R8_SAFE_ACCESS_SIG = 0x57; + R8_SAFE_ACCESS_SIG = 0xA8; + R8_SLP_POWER_CTRL |= RB_SLP_USBHS_PWRDN; // Set RB_SLP_USBHS_PWRDN to 1 + R8_SAFE_ACCESS_SIG = 0x00; + PFIC->SCTLR |= 1<<2; // Set the SleepDeep field of the core PFIC SCTLR register to 1 + __WFI(); // Execute __WFI() after setting the wake-up condition +} + +/******************************************************************************* + * @fn LowPower_Halt + * + * @brief Low power consumption - Enter Halt mode with WFE instruction + * + * @return None + */ +void LowPower_Halt_WFE( void ) +{ + R8_SAFE_ACCESS_SIG = 0x57; + R8_SAFE_ACCESS_SIG = 0xA8; + R8_SLP_POWER_CTRL |= RB_SLP_USBHS_PWRDN; // Set RB_SLP_USBHS_PWRDN to 1 + R8_SAFE_ACCESS_SIG = 0x00; + PFIC->SCTLR |= 1<<2; // Set the SleepDeep field of the core PFIC SCTLR register to 1 + __WFE(); // Execute __WFE() after setting the wake-up condition +} +/******************************************************************************* + * @fn LowPower_Sleep + * + * @brief Low power consumption - Enter Sleep mode with WFI instruction + * + * @return None + */ +void LowPower_Sleep( void ) +{ + R8_SAFE_ACCESS_SIG = 0x57; + R8_SAFE_ACCESS_SIG = 0xA8; + USBSS->LINK_CFG &= ~(0x1 << 12); // This bit should be set to 0 when USB3.0 enters low-power consumption + USBSS->LINK_CFG &= ~(0x1 << 3); // Cancel USB PHY RESET + R8_SLP_POWER_CTRL |= RB_SLP_USBHS_PWRDN; // Set RB_SLP_USBHS_PWRDN to 1 + R8_SAFE_ACCESS_SIG = 0x00; + PFIC->SCTLR |= 1<<2; // Set the SleepDeep field of the core PFIC SCTLR register to 1 + __WFI(); // Execute __WFI() after setting the wake-up condition +} + +/******************************************************************************* + * @fn LowPower_Sleep + * + * @brief Low power consumption - Enter Sleep mode with WFE instruction + * + * @return None + */ +void LowPower_Sleep_WFE( void ) +{ + R8_SAFE_ACCESS_SIG = 0x57; + R8_SAFE_ACCESS_SIG = 0xA8; + USBSS->LINK_CFG &= ~(0x1 << 12); // This bit should be set to 0 when USB3.0 enters low-power consumption + USBSS->LINK_CFG &= ~(0x1 << 3); // Cancel USB PHY RESET + R8_SLP_POWER_CTRL |= RB_SLP_USBHS_PWRDN; // Set RB_SLP_USBHS_PWRDN to 1 + R8_SAFE_ACCESS_SIG = 0x00; + PFIC->SCTLR |= 1<<2; // Set the SleepDeep field of the core PFIC SCTLR register to 1 + __WFE(); // Execute __WFE() after setting the wake-up condition +} diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_spi.c b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_spi.c new file mode 100644 index 000000000..570dc8075 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_spi.c @@ -0,0 +1,579 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : CH56x_spi.c +* Author : WCH +* Version : V1.0 +* Date : 2020/07/31 +* Description : +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + +#include "CH56x_common.h" + +/******************************************************************************* + * @fn SPI0_MasterDefInit + * + * @brief Host mode default initialization + * + * @return None + */ +void SPI0_MasterDefInit( void ) +{ + R8_SPI0_CLOCK_DIV = 4; //Main frequency clock divided by 4 + R8_SPI0_CTRL_MOD = RB_SPI_ALL_CLEAR; //FIFO/counter/interrupt flag register is cleared to 0, write 1 to force clear or clear + R8_SPI0_CTRL_MOD = RB_SPI_MOSI_OE | RB_SPI_SCK_OE ; //MOSI pin and SCK pin output enable + R8_SPI0_CTRL_CFG |= RB_SPI_AUTO_IF; //Enable access to BUFFER/FIFO to automatically clear the flag + R8_SPI0_CTRL_CFG &= ~RB_SPI_DMA_ENABLE; //Do not start DMA mode +} + +/******************************************************************************* + * @fn SPI0_DataMode + * + * @brief Set data flow mode + * + * @param m - data flow mode + * + * @return None + */ +void SPI0_DataMode( ModeBitOrderTypeDef m ) +{ + switch( m ) + { + case Mode0_LowBitINFront: //Mode 0, low order first + R8_SPI0_CTRL_MOD &= ~RB_SPI_MST_SCK_MOD; + R8_SPI0_CTRL_CFG |= RB_SPI_BIT_ORDER; + break; + case Mode0_HighBitINFront: //Mode 0, high bit first + R8_SPI0_CTRL_MOD &= ~RB_SPI_MST_SCK_MOD; + R8_SPI0_CTRL_CFG &= ~RB_SPI_BIT_ORDER; + break; + case Mode3_LowBitINFront: //Mode 3, low bit first + R8_SPI0_CTRL_MOD |= RB_SPI_MST_SCK_MOD; + R8_SPI0_CTRL_CFG |= RB_SPI_BIT_ORDER; + break; + case Mode3_HighBitINFront: //Mode 3, high bit first + R8_SPI0_CTRL_MOD |= RB_SPI_MST_SCK_MOD; + R8_SPI0_CTRL_CFG &= ~RB_SPI_BIT_ORDER; + break; + default: + break; + } +} + +/******************************************************************************* + * @fn SPI0_MasterSendByte + * + * @brief Send a single byte (buffer) + * + * @param d - send bytes + * + * @return None + */ +void SPI0_MasterSendByte( UINT8 d ) +{ + R8_SPI0_CTRL_MOD &= ~RB_SPI_FIFO_DIR; + R8_SPI0_BUFFER = d; + while( !(R8_SPI0_INT_FLAG & RB_SPI_FREE) ); +} + +/******************************************************************************* + * @fn SPI0_MasterRecvByte + * + * @brief Receive a single byte (buffer) + * + * @return bytes received + */ +UINT8 SPI0_MasterRecvByte( void ) +{ + R8_SPI0_CTRL_MOD &= ~RB_SPI_FIFO_DIR; + R8_SPI0_BUFFER = 0xFF; //start transfer + while( !(R8_SPI0_INT_FLAG & RB_SPI_FREE) ); + return ( R8_SPI0_BUFFER ); +} + +/******************************************************************************* + * @fn SPI0_MasterTrans + * + * @brief Continuously send multiple bytes using FIFO + * + * @param pbuf: The first address of the data content to be sent + * + * @return None + */ +void SPI0_MasterTrans( UINT8 *pbuf, UINT16 len ) +{ + UINT16 sendlen; + + sendlen = len; + R8_SPI0_CTRL_MOD &= ~RB_SPI_FIFO_DIR; //Set data direction to output + R16_SPI0_TOTAL_CNT = sendlen; //Set the length of the data to be sent + R8_SPI0_INT_FLAG = RB_SPI_IF_CNT_END; + while( sendlen ) + { + if( R8_SPI0_FIFO_COUNT < SPI_FIFO_SIZE ) + { + R8_SPI0_FIFO = *pbuf; + pbuf++; + sendlen--; + } + } + while( R8_SPI0_FIFO_COUNT != 0 ); //Wait for all the data in the FIFO to be sent +} + +/******************************************************************************* + * @fn SPI0_MasterRecv + * + * @brief Receive multiple bytes continuously using FIFO + * + * @param pbuf: The first address of the data content to be sent + * + * @return None + **/ +void SPI0_MasterRecv( UINT8 *pbuf, UINT16 len ) +{ + UINT16 readlen; + + readlen = len; + R8_SPI0_CTRL_MOD |= RB_SPI_FIFO_DIR; //Set data direction to input + R16_SPI0_TOTAL_CNT = len; //Set the length of the data to be received, the FIFO direction will start the transmission if the input length is not 0 + R8_SPI0_INT_FLAG = RB_SPI_IF_CNT_END; + while( readlen ) + { + if( R8_SPI0_FIFO_COUNT ) + { + *pbuf = R8_SPI0_FIFO; + pbuf++; + readlen--; + } + } +} + +/******************************************************************************* + * @fn SPI0_MasterDMATrans + * + * @brief Continuously send data in DMA mode + * + * @param pbuf: The starting address of the data to be sent + * + * @return None + */ +void SPI0_MasterDMATrans( PUINT8 pbuf, UINT16 len) +{ + R8_SPI0_CTRL_MOD &= ~RB_SPI_FIFO_DIR; + R32_SPI0_DMA_BEG = (UINT32)pbuf; + R32_SPI0_DMA_END = (UINT32)(pbuf + len); + R16_SPI0_TOTAL_CNT = len; + R8_SPI0_INT_FLAG = RB_SPI_IF_CNT_END|RB_SPI_IF_DMA_END; + R8_SPI0_CTRL_CFG |= RB_SPI_DMA_ENABLE; + while(!(R8_SPI0_INT_FLAG & RB_SPI_IF_CNT_END)); + R8_SPI0_CTRL_CFG &= ~RB_SPI_DMA_ENABLE; +} + +/******************************************************************************* + * @fn SPI0_MasterDMARecv + * + * @brief Receive data continuously in DMA mode + * + * @param pbuf: The starting address for storing the data to be received + * + * @return None + **/ +void SPI0_MasterDMARecv( PUINT8 pbuf, UINT16 len) +{ + R8_SPI0_CTRL_MOD |= RB_SPI_FIFO_DIR; + R32_SPI0_DMA_BEG = (UINT32)pbuf; + R32_SPI0_DMA_END = (UINT32)(pbuf + len); + R16_SPI0_TOTAL_CNT = len; + R8_SPI0_INT_FLAG = RB_SPI_IF_CNT_END|RB_SPI_IF_DMA_END; + R8_SPI0_CTRL_CFG |= RB_SPI_DMA_ENABLE; + while(!(R8_SPI0_INT_FLAG & RB_SPI_IF_CNT_END)); + R8_SPI0_CTRL_CFG &= ~RB_SPI_DMA_ENABLE; +} + +/******************************************************************************* + * @fn SPI0_SlaveInit + * + * @brief Device mode default initialization + * + * @return None + */ +void SPI0_SlaveInit( void ) +{ + R8_SPI0_CTRL_MOD = RB_SPI_ALL_CLEAR; //FIFO/counter/interrupt flag register is cleared to 0, write 1 to force clear or clear + R8_SPI0_CTRL_MOD = RB_SPI_MISO_OE | RB_SPI_MODE_SLAVE; + R8_SPI0_CTRL_CFG |= RB_SPI_AUTO_IF; //Enable access to BUFFER/FIFO to automatically clear the flag +} + +/******************************************************************************* + * @fn SPI0_SlaveRecvByte + * + * @brief Slave mode, receive one byte of data + * + * @return received data + */ +UINT8 SPI0_SlaveRecvByte( void ) +{ + R8_SPI0_CTRL_MOD |= RB_SPI_FIFO_DIR; //Set to input mode, receive data + while( R8_SPI0_FIFO_COUNT == 0 ); + return R8_SPI0_FIFO; +} + +/******************************************************************************* + * @fn SPI0_SlaveRecvByte + * + * @brief Slave mode, send one byte of data + * + * @return received data + **/ +void SPI0_SlaveSendByte( UINT8 d ) +{ + R8_SPI0_CTRL_MOD &= ~RB_SPI_FIFO_DIR; //Set data direction to output + R8_SPI0_FIFO = d; + while( R8_SPI0_FIFO_COUNT != 0 ); //Wait for the send to complete +} + +/******************************************************************************* + * @fn SPI0_SlaveRecv + * + * @brief Slave mode, receive multi-byte data + * + * @param pbuf: Receive data storage starting address + * + * @return None + **/ +void SPI0_SlaveRecv( PUINT8 pbuf, UINT16 len ) +{ + UINT16 revlen; + + revlen = len; + R8_SPI0_CTRL_MOD |= RB_SPI_FIFO_DIR; //Set to input mode, receive data + R16_SPI0_TOTAL_CNT = revlen; //Assign a value to the SPI send and receive data total length register + R8_SPI0_INT_FLAG = RB_SPI_IF_CNT_END; //SPI interrupt flag register All bytes transfer complete flag, write 1 to clear 0 + while( revlen ) + { + if( R8_SPI0_FIFO_COUNT ) //Byte count in the current FIFO + { + *pbuf = R8_SPI0_FIFO; + pbuf++; + revlen--; + } + } +} + +/******************************************************************************* + * @fn SPI0_SlaveTrans + * + * @brief Slave mode, send multi-byte data + * + * @param pbuf: The first address of the data content to be sent + * + * @return None + */ +void SPI0_SlaveTrans( UINT8 *pbuf, UINT16 len ) +{ + UINT16 sendlen; + + sendlen = len; + R8_SPI0_CTRL_MOD &= ~RB_SPI_FIFO_DIR; //Set data direction to output + R16_SPI0_TOTAL_CNT = sendlen; //Set the length of the data to be sent + R8_SPI0_INT_FLAG = RB_SPI_IF_CNT_END; //SPI interrupt flag register All bytes transfer complete flag, write 1 to clear 0 + while( sendlen ) + { + if( R8_SPI0_FIFO_COUNT < SPI_FIFO_SIZE ) //Compare the byte count size in the current FIFO + { + R8_SPI0_FIFO = *pbuf; + pbuf++; + sendlen--; + } + } + while( R8_SPI0_FIFO_COUNT != 0 ); //Wait for all the data in the FIFO to be sent +} + + +/******************************************************************************* + * @fn SPI1_MasterDefInit + * + * @brief Host mode default initialization + * + * @return None + */ +void SPI1_MasterDefInit( void ) +{ + R8_SPI1_CLOCK_DIV = 4; //Main frequency clock divided by 4 + R8_SPI1_CTRL_MOD = RB_SPI_ALL_CLEAR; + R8_SPI1_CTRL_MOD = RB_SPI_MOSI_OE | RB_SPI_SCK_OE ; + R8_SPI1_CTRL_CFG |= RB_SPI_AUTO_IF; + R8_SPI1_CTRL_CFG &= ~RB_SPI_DMA_ENABLE; //Do not start DMA mode + //R8_SPI1_CTRL_CFG |= RB_SPI_DMA_ENABLE; //Start DMA mode +} + +/******************************************************************************* + * @fn SPI1_DataMode + * + * @brief Set data flow mode + * + * @param m: data flow mode + * + * @return None + ***/ +void SPI1_DataMode( ModeBitOrderTypeDef m ) +{ + switch( m ) + { + case Mode0_LowBitINFront: + R8_SPI1_CTRL_MOD &= ~RB_SPI_MST_SCK_MOD; + R8_SPI1_CTRL_CFG |= RB_SPI_BIT_ORDER; + break; + case Mode0_HighBitINFront: + R8_SPI1_CTRL_MOD &= ~RB_SPI_MST_SCK_MOD; + R8_SPI1_CTRL_CFG &= ~RB_SPI_BIT_ORDER; + break; + case Mode3_LowBitINFront: + R8_SPI1_CTRL_MOD |= RB_SPI_MST_SCK_MOD; + R8_SPI1_CTRL_CFG |= RB_SPI_BIT_ORDER; + break; + case Mode3_HighBitINFront: + R8_SPI1_CTRL_MOD |= RB_SPI_MST_SCK_MOD; + R8_SPI1_CTRL_CFG &= ~RB_SPI_BIT_ORDER; + break; + default: + break; + } +} + +/******************************************************************************* + * @fn SPI1_MasterSendByte + * + * @brief Send a single byte (buffer) + * + * @param d - send bytes + * + * @return None + */ +void SPI1_MasterSendByte( UINT8 d ) +{ + R8_SPI1_CTRL_MOD &= ~RB_SPI_FIFO_DIR; + R8_SPI1_BUFFER = d; + while( !(R8_SPI1_INT_FLAG & RB_SPI_FREE) ); +} + +/******************************************************************************* + * @fn SPI1_MasterRecvByte + * + * @brief Receive a single byte (buffer) + * + * @return bytes received + */ +UINT8 SPI1_MasterRecvByte( void ) +{ + R8_SPI1_CTRL_MOD &= ~RB_SPI_FIFO_DIR; + R8_SPI1_BUFFER = 0xFF; //start transfer + while( !(R8_SPI1_INT_FLAG & RB_SPI_FREE) ); + return ( R8_SPI1_BUFFER ); +} + +/******************************************************************************* + * @fn SPI1_MasterTrans + * + * @brief Continuously send multiple bytes using FIFO + * + * @param pbuf - The first address of the data content to be sent + * len - The length of the data sent by the request, the maximum is 4095 + * @return None + */ +void SPI1_MasterTrans( UINT8 *pbuf, UINT16 len ) +{ + UINT16 sendlen; + + sendlen = len; + R8_SPI1_CTRL_MOD &= ~RB_SPI_FIFO_DIR; //Set data direction to output + R16_SPI1_TOTAL_CNT = sendlen; //Set the length of the data to be sent + R8_SPI1_INT_FLAG = RB_SPI_IF_CNT_END; + while( sendlen ) + { + if( R8_SPI1_FIFO_COUNT < SPI_FIFO_SIZE ) + { + R8_SPI1_FIFO = *pbuf; + pbuf++; + sendlen--; + } + } + while( R8_SPI1_FIFO_COUNT != 0 ); //Wait for all the data in the FIFO to be sent +} + +/******************************************************************************* + * @fn SPI1_MasterRecv + * + * @brief Receive multiple bytes continuously using FIFO + * + * @param pbuf - The first address of the data content to be sent + * len - The length of the data sent by the request, the maximum is 4095 + * @return None + **/ +void SPI1_MasterRecv( UINT8 *pbuf, UINT16 len ) +{ + UINT16 readlen; + + readlen = len; + R8_SPI1_CTRL_MOD |= RB_SPI_FIFO_DIR; //Set data direction to input + R16_SPI1_TOTAL_CNT = len; //Set the length of the data to be received, the FIFO direction will start the transmission if the input length is not 0 + R8_SPI1_INT_FLAG = RB_SPI_IF_CNT_END; + while( readlen ) + { + if( R8_SPI1_FIFO_COUNT ) + { + *pbuf = R8_SPI1_FIFO; + pbuf++; + readlen--; + } + } +} + +/******************************************************************************* + * @fn SPI1_MasterDMATrans + * + * @brief Continuously send data in DMA mode + * + * @param pbuf - The starting address of the data to be sent + * len - With send data length + * @return None + */ +void SPI1_MasterDMATrans( PUINT8 pbuf, UINT16 len) +{ + R8_SPI1_CTRL_MOD &= ~RB_SPI_FIFO_DIR; + R32_SPI1_DMA_BEG = (UINT32)pbuf; + R32_SPI1_DMA_END = (UINT32)(pbuf + len); + R16_SPI1_TOTAL_CNT = len; + R8_SPI1_INT_FLAG = RB_SPI_IF_CNT_END|RB_SPI_IF_DMA_END; + R8_SPI1_CTRL_CFG |= RB_SPI_DMA_ENABLE; + while(!(R8_SPI1_INT_FLAG & RB_SPI_IF_CNT_END)); + R8_SPI1_CTRL_CFG &= ~RB_SPI_DMA_ENABLE; +} + +/******************************************************************************* + * @fn SPI1_MasterDMARecv + * + * @brief Receive data continuously in DMA mode + * + * @param pbuf - The starting address for storing the data to be received + * len - Data length to be received + * + * @return None + */ +void SPI1_MasterDMARecv( PUINT8 pbuf, UINT16 len) +{ + R8_SPI1_CTRL_MOD |= RB_SPI_FIFO_DIR; + R32_SPI1_DMA_BEG = (UINT32)pbuf; + R32_SPI1_DMA_END = (UINT32)(pbuf + len); + R16_SPI1_TOTAL_CNT = len; + R8_SPI1_INT_FLAG = RB_SPI_IF_CNT_END|RB_SPI_IF_DMA_END; + R8_SPI1_CTRL_CFG |= RB_SPI_DMA_ENABLE; + while(!(R8_SPI0_INT_FLAG & RB_SPI_IF_CNT_END)); + R8_SPI1_CTRL_CFG &= ~RB_SPI_DMA_ENABLE; +} + +/******************************************************************************* + * @fn SPI1_SlaveInit + * + * @brief Device mode default initialization + * + * @return None + */ +void SPI1_SlaveInit( void ) +{ + R8_SPI1_CTRL_MOD = RB_SPI_ALL_CLEAR; + R8_SPI1_CTRL_MOD = RB_SPI_MISO_OE | RB_SPI_MODE_SLAVE; + R8_SPI1_CTRL_CFG |= RB_SPI_AUTO_IF; +} + +/******************************************************************************* + * @fn SPI1_SlaveRecvByte + * + * @brief Slave mode, receive one byte of data + * + * @return received data + */ +UINT8 SPI1_SlaveRecvByte( void ) +{ + R8_SPI1_CTRL_MOD |= RB_SPI_FIFO_DIR; + while( R8_SPI1_FIFO_COUNT == 0 ); + return R8_SPI1_FIFO; +} + +/******************************************************************************* + * @fn SPI1_SlaveRecvByte + * + * @brief Slave mode, receive one byte of data + * + * @return received data + */ +void SPI1_SlaveSendByte( UINT8 d ) +{ + R8_SPI1_CTRL_MOD &= ~RB_SPI_FIFO_DIR; + R8_SPI1_FIFO = d; + while( R8_SPI1_FIFO_COUNT != 0 ); //Wait for the send to complete +} + +/******************************************************************************* + * @fn SPI1_SlaveRecv + * @brief Slave mode, receive multi-byte data + * @param pbuf - Receive data storage starting address + * len - Request to receive data length + * @return None + */ +void SPI1_SlaveRecv( PUINT8 pbuf, UINT16 len ) +{ + UINT16 revlen; + + revlen = len; + R8_SPI1_CTRL_MOD |= RB_SPI_FIFO_DIR; + R16_SPI1_TOTAL_CNT = revlen; + R8_SPI1_INT_FLAG = RB_SPI_IF_CNT_END; + while( revlen ) + { + if( R8_SPI1_FIFO_COUNT ) + { + *pbuf = R8_SPI1_FIFO; + pbuf++; + revlen--; + } + } +} + +/******************************************************************************* + * @fn SPI1_SlaveTrans + * + * @brief Slave mode, send multi-byte data + * + * @param pbuf - The first address of the data content to be sent + * len - The length of the data sent by the request, the maximum is 4095 + * @return None + */ +void SPI1_SlaveTrans( UINT8 *pbuf, UINT16 len ) +{ + UINT16 sendlen; + + sendlen = len; + R8_SPI1_CTRL_MOD &= ~RB_SPI_FIFO_DIR; //Set data direction to output + R16_SPI1_TOTAL_CNT = sendlen; //Set the length of the data to be sent + R8_SPI1_INT_FLAG = RB_SPI_IF_CNT_END; + while( sendlen ) + { + if( R8_SPI1_FIFO_COUNT < SPI_FIFO_SIZE ) + { + R8_SPI1_FIFO = *pbuf; + pbuf++; + sendlen--; + } + } + while( R8_SPI1_FIFO_COUNT != 0 ); //Wait for all the data in the FIFO to be sent +} + + + + + + + diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_sys.c b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_sys.c new file mode 100644 index 000000000..a9528e902 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_sys.c @@ -0,0 +1,198 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH56x_sys.c + * Author : WCH + * Version : V1.0 + * Date : 2024/01/14 + * Description : This file contains all the functions prototypes for + * SystemCoreClock, UART Printf , Delay functions . + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#include "CH56x_common.h" + +static uint8_t p_us = 0; +static uint16_t p_ms = 0; + +/******************************************************************************* + * @fn Delay_Init + * + * @brief Initializes Delay Funcation. + * + * @param systemclck - system clock Hz + * + * @return None + **/ +void Delay_Init(uint32_t systemclck) +{ + p_us = systemclck / 8000000; + p_ms = (uint16_t)p_us * 1000; +} + +/******************************************************************************* + * @fn mDelayuS + * + * @brief Microsecond Delay Time. + * + * @param n - Microsecond number. + * + * @return None + **/ +void mDelayuS(uint32_t n) +{ + uint32_t i; + + SysTick->CNTFG &= ~(1 << 1); + + i = (uint32_t)n * p_us; + + SysTick->CMP = i; + SysTick->CTLR = (1 << 8) | (1 << 0); + + while ((SysTick->CNTFG & (1 << 1)) != (1 << 1)); + SysTick->CTLR = 0; +} + +/******************************************************************************* + * @fn mDelaymS + * + * @brief Millisecond Delay Time. + * + * @param n - Millisecond number. + * + * @return None + **/ +void mDelaymS(uint32_t n) +{ + uint32_t i; + + SysTick->CNTFG &= ~(1 << 1); + + i = (uint32_t)n * p_ms; + + SysTick->CMP = i; + SysTick->CTLR = (1 << 8) | (1 << 0); + + while ((SysTick->CNTFG & (1 << 1)) != (1 << 1)); + SysTick->CTLR = 0; +} + +/******************************************************************************* + * @fn SYS_GetInfoSta + * + * @brief Get the current system information status + * + * @param i - + * @return stat + **/ +UINT8 SYS_GetInfoSta(SYS_InfoStaTypeDef i) +{ + return (R8_RST_BOOT_STAT & (1 << i)); +} + +/******************************************************************************* + * @fn SYS_ResetExecute + * + * @brief Perform a system software reset + * + * @return None + **/ +void SYS_ResetExecute(void) +{ + R8_SAFE_ACCESS_SIG = 0x57; // enable safe access mode + R8_SAFE_ACCESS_SIG = 0xa8; + R8_RST_WDOG_CTRL |= RB_SOFTWARE_RESET | 0x40; + R8_SAFE_ACCESS_SIG = 0; +} + +/******************************************************************************* + * @fn WWDG_ITCfg + * + * @brief Watchdog timer overflow interrupt enable + * + * @param s - + * DISABLE - Overflow without interruption + * ENABLE - Overflow interrupt + * + * @return None + **/ +void WWDG_ITCfg(UINT8 s) +{ + R8_SAFE_ACCESS_SIG = 0x57; // enable safe access mode + R8_SAFE_ACCESS_SIG = 0xa8; + if (s == DISABLE) R8_RST_WDOG_CTRL = (R8_RST_WDOG_CTRL & (~RB_WDOG_INT_EN)) | 0x40; + else R8_RST_WDOG_CTRL |= RB_WDOG_INT_EN | 0x40; + R8_SAFE_ACCESS_SIG = 0; +} + +/******************************************************************************* + * @fn WWDG_ResetCfg + * + * @brief Watchdog timer reset function + * + * @param s - + * DISABLE - Overflow does not reset + * ENABLE - Overflow system reset + * + * @return None + **/ +void WWDG_ResetCfg(UINT8 s) +{ + R8_SAFE_ACCESS_SIG = 0x57; // enable safe access mode + R8_SAFE_ACCESS_SIG = 0xa8; + if (s == DISABLE) R8_RST_WDOG_CTRL = (R8_RST_WDOG_CTRL & (~RB_WDOG_RST_EN)) | 0x40; + else R8_RST_WDOG_CTRL |= RB_WDOG_RST_EN | 0x40; + R8_SAFE_ACCESS_SIG = 0; +} + +/******************************************************************************* + * @fn WWDG_ClearFlag + * @brief Clear watchdog interrupt flag, reload count value can also be cleared + * @param None + * @return None + **/ +void WWDG_ClearFlag(void) +{ + R8_SAFE_ACCESS_SIG = 0x57; // enable safe access mode + R8_SAFE_ACCESS_SIG = 0xa8; + R8_RST_WDOG_CTRL |= RB_WDOG_INT_FLAG | 0x40; + R8_SAFE_ACCESS_SIG = 0; +} + +#if (defined DEBUG) +/******************************************************************************* + * @fn _write + * + * @brief Support Printf Function + * + * @param *buf: UART send Data. + * size - Data length + * + * @return size - Data length + **/ +__attribute__((used)) int _write(int fd, char *buf, int size) +{ + int i; + + for (i = 0; i < size; i++) + { +#if DEBUG == Debug_UART0 + while (R8_UART0_TFC == UART_FIFO_SIZE); + R8_UART0_THR = *buf++; +#elif DEBUG == Debug_UART1 + while (R8_UART1_TFC == UART_FIFO_SIZE); + R8_UART1_THR = *buf++; +#elif DEBUG == Debug_UART2 + while (R8_UART2_TFC == UART_FIFO_SIZE); + R8_UART2_THR = *buf++; +#elif DEBUG == Debug_UART3 + while (R8_UART3_TFC == UART_FIFO_SIZE); + R8_UART3_THR = *buf++; +#endif + } + + return size; +} +#endif diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_timer.c b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_timer.c new file mode 100644 index 000000000..045e65336 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_timer.c @@ -0,0 +1,269 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : CH56x_timer.c +* Author : WCH +* Version : V1.0 +* Date : 2020/07/31 +* Description : +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + +#include "CH56x_common.h" + + +/******************************************************************************* + * @fn TMR0_TimerInit + * + * @brief Counting Function on TIM PeriPheral + * + * @param t - the Most End Value counting to + * + * @return None + */ +void TMR0_TimerInit( UINT32 t ) +{ + R32_TMR0_CNT_END = t; + R8_TMR0_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR0_CTRL_MOD = RB_TMR_COUNT_EN | RB_TMR_CAP_COUNT; +} + +/******************************************************************************* + * @fn TMR1_TimerInit + * + * @brief Counting Function on TIM PeriPheral + * + * @param t - the Most End Value counting to + * + * @return None + */ +void TMR1_TimerInit( UINT32 t ) +{ + R32_TMR1_CNT_END = t; + R8_TMR1_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR1_CTRL_MOD = RB_TMR_COUNT_EN | RB_TMR_CAP_COUNT; +} + +/******************************************************************************* + * @fn TMR2_TimerInit + * + * @brief Counting Function on TIM PeriPheral + * + * @param t - the Most End Value counting to + * + * @return None + */ +void TMR2_TimerInit( UINT32 t ) +{ + R32_TMR2_CNT_END = t; + R8_TMR2_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR2_CTRL_MOD = RB_TMR_COUNT_EN | RB_TMR_CAP_COUNT; +} + +/******************************************************************************* + * @fn TMR0_EXTSignalCounterInit + * + * @brief external signal count + * + * @param c + * + * @return None + */ +void TMR0_EXTSignalCounterInit( UINT32 c ) +{ + R32_TMR0_CNT_END = c; + R8_TMR0_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR0_CTRL_MOD = RB_TMR_CAP_COUNT|RB_TMR_MODE_IN|RB_TMR_COUNT_EN; +} + +/******************************************************************************* + * @fn TMR1_EXTSignalCounterInit + * + * @brief external signal count + * + * @param c + * + * @return None + */ +void TMR1_EXTSignalCounterInit( UINT32 c ) +{ + R32_TMR1_CNT_END = c; + R8_TMR1_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR1_CTRL_MOD = RB_TMR_CAP_COUNT|RB_TMR_MODE_IN|RB_TMR_COUNT_EN; +} + +/******************************************************************************* + * @fn TMR2_EXTSignalCounterInit + * + * @brief external signal count + * + * @param c + * + * @return None + */ +void TMR2_EXTSignalCounterInit( UINT32 c ) +{ + R32_TMR2_CNT_END = c; + R8_TMR2_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR2_CTRL_MOD = RB_TMR_CAP_COUNT|RB_TMR_MODE_IN|RB_TMR_COUNT_EN; +} + +/******************************************************************************* + * @fn TMR0_PWMInit + * + * @brief PWM Output Init + * + * @param pr- + * ts- + * + * @return None + */ +void TMR0_PWMInit( PWM_PolarTypeDef pr, PWM_RepeatTsTypeDef ts ) +{ + R8_TMR0_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR0_CTRL_MOD = RB_TMR_COUNT_EN + |RB_TMR_OUT_EN + |(pr<<4) + |(ts<<6); +} + +/******************************************************************************* + * @fn TMR1_PWMInit + * + * @brief PWM Output Init + * + * @param pr- + * ts- + * + * @return None + */ +void TMR1_PWMInit( PWM_PolarTypeDef pr, PWM_RepeatTsTypeDef ts ) +{ + R8_TMR1_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR1_CTRL_MOD = RB_TMR_COUNT_EN + |RB_TMR_OUT_EN + |(pr<<4) + |(ts<<6); +} + +/******************************************************************************* + * @fn TMR2_PWMInit + * + * @brief PWM Output Init + * + * @param pr- + * ts- + * + * @return None + */ +void TMR2_PWMInit( PWM_PolarTypeDef pr, PWM_RepeatTsTypeDef ts ) +{ + R8_TMR2_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR2_CTRL_MOD = RB_TMR_COUNT_EN + |RB_TMR_OUT_EN + |(pr<<4) + |(ts<<6); +} + +/******************************************************************************* + * @fn TMR0_CapInit + * + * @brief cap + * + * @param CapModeTypeDef + * + * @return None + */ +void TMR0_CapInit( CapModeTypeDef cap ) +{ + R8_TMR0_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR0_CTRL_MOD = RB_TMR_COUNT_EN \ + |RB_TMR_MODE_IN \ + |(cap<<6); +} + +/******************************************************************************* + * @fn TMR1_CapInit + * + * @brief cap + * + * @param CapModeTypeDef + * + * @return None + */ +void TMR1_CapInit( CapModeTypeDef cap ) +{ + R8_TMR1_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR1_CTRL_MOD = RB_TMR_COUNT_EN \ + |RB_TMR_MODE_IN \ + |(cap<<6); +} + +/******************************************************************************* + * @fn TMR2_CapInit + * + * @brief cap + * + * @param CapModeTypeDef + * + * @return None + */ +void TMR2_CapInit( CapModeTypeDef cap ) +{ + R8_TMR2_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR2_CTRL_MOD = RB_TMR_COUNT_EN \ + |RB_TMR_MODE_IN \ + |(cap<<6); +} + +/******************************************************************************* + * @fn TMR1_DMACfd + * + * @brief TMR DMA Configuration + * + * @param ENABLE/DISABLE + * startAddr + * endAddr + * DMAModeTypeDef + * @return None + **/ +void TMR1_DMACfg( UINT8 s, UINT16 startAddr, UINT16 endAddr, DMAModeTypeDef m ) +{ + if(s == DISABLE){ + R8_TMR1_CTRL_DMA = 0; + } + else{ + if(m) R8_TMR1_CTRL_DMA = RB_TMR_DMA_LOOP|RB_TMR_DMA_ENABLE; + else R8_TMR1_CTRL_DMA = RB_TMR_DMA_ENABLE; + R32_TMR1_DMA_BEG = startAddr; + R32_TMR1_DMA_END = endAddr; + } +} + +/******************************************************************************* + * @fn TMR2_DMACfd + * + * @brief TMR DMA Configuration + * + * @param ENABLE/DISABLE + * startAddr + * endAddr + * DMAModeTypeDef + * @return None + **/ + +void TMR2_DMACfg( UINT8 s, UINT16 startAddr, UINT16 endAddr, DMAModeTypeDef m ) +{ + if(s == DISABLE){ + R8_TMR2_CTRL_DMA = 0; + } + else{ + if(m) R8_TMR2_CTRL_DMA = RB_TMR_DMA_LOOP|RB_TMR_DMA_ENABLE; + else R8_TMR2_CTRL_DMA = RB_TMR_DMA_ENABLE; + R32_TMR2_DMA_BEG = startAddr; + R32_TMR2_DMA_END = endAddr; + } +} + + diff --git a/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_uart.c b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_uart.c new file mode 100644 index 000000000..3bc5dda47 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/ch569w/third_party_driver/Peripheral/src/CH56x_uart.c @@ -0,0 +1,548 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : CH56x_uart.c + * Author : WCH + * Version : V1.0 + * Date : 2020/07/31 + * Description : + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#include "CH56x_common.h" + +/****************************************************************************** + * @fn UART0_DefInit + * + * @brief Serial port default initialization configuration: FIFO enabled, trigger point byte count, serial port data + * length setting, baud rate and frequency division coefficient + * + * @return None + */ +void UART0_DefInit(void) +{ + R8_UART0_DIV = 1; + UART0_BaudRateCfg(115200); + R8_UART0_FCR = + (2 << 6) | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN; // FIFO open, trigger point 4 bytes + R8_UART0_LCR = RB_LCR_WORD_SZ; + R8_UART0_IER = RB_IER_TXD_EN; +} + +/******************************************************************************* + * @fn UART1_DefInit + * + * @brief Serial port default initialization configuration: FIFO enabled, trigger point byte count, serial port data + *length setting, baud rate and frequency division coefficient + * + * @return None + **/ +void UART1_DefInit(void) +{ + R8_UART1_DIV = 1; + UART1_BaudRateCfg(115200); + R8_UART1_FCR = + (2 << 6) | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN; // FIFO open, trigger point 4 bytes + R8_UART1_LCR = RB_LCR_WORD_SZ; + R8_UART1_IER = RB_IER_TXD_EN; +} + +/******************************************************************************* + * @fn UART2_DefInit + * + * @brief Serial port default initialization configuration: FIFO enabled, trigger point byte count, serial port data + * length setting, baud rate and frequency division coefficient + * + * @return None + */ +void UART2_DefInit(void) +{ + R8_UART2_DIV = 1; + UART2_BaudRateCfg(115200); + R8_UART2_FCR = + (2 << 6) | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN; // FIFO open, trigger point 4 bytes + R8_UART2_LCR = RB_LCR_WORD_SZ; + R8_UART2_IER = RB_IER_TXD_EN; +} + +/******************************************************************************* + * @fn UART3_DefInit + * + * @brief Serial port default initialization configuration: FIFO enabled, trigger point byte count, serial port data + * length setting, baud rate and frequency division coefficient + * + * @return None + */ +void UART3_DefInit(void) +{ + R8_UART3_DIV = 1; + UART3_BaudRateCfg(115200); + R8_UART3_FCR = + (2 << 6) | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN; // FIFO open, trigger point 4 bytes + R8_UART3_LCR = RB_LCR_WORD_SZ; + R8_UART3_IER = RB_IER_TXD_EN; +} + +/******************************************************************************* + * @fn UART0_BaudRateCfg + * + * @brief Serial port baud rate configuration + * + * @return None + */ +void UART0_BaudRateCfg(UINT32 baudrate) +{ + UINT32 x; + + x = 10 * (FREQ_SYS * 2 / R8_UART0_DIV) / 16 / baudrate; + x = (x + 5) / 10; + R16_UART0_DL = (UINT16)x; +} + +/******************************************************************************* + * @fn UART1_BaudRateCfg + * + * @brief Serial port baud rate configuration + * + * @return None + */ +void UART1_BaudRateCfg(UINT32 baudrate) +{ + UINT32 x; + + x = 10 * (FREQ_SYS * 2 / R8_UART1_DIV) / 16 / baudrate; + x = (x + 5) / 10; + R16_UART1_DL = (UINT16)x; +} + +/******************************************************************************* + * @fn UART2_BaudRateCfg + * + * @brief Serial port baud rate configuration + * + * @return None + */ +void UART2_BaudRateCfg(UINT32 baudrate) +{ + UINT32 x; + + x = 10 * (FREQ_SYS * 2 / R8_UART2_DIV) / 16 / baudrate; + x = (x + 5) / 10; + R16_UART2_DL = (UINT16)x; +} + +/******************************************************************************* + * @fn UART3_BaudRateCfg + * + * @brief Serial port baud rate configuration + * + * @return None + */ +void UART3_BaudRateCfg(UINT32 baudrate) +{ + UINT32 x; + + x = 10 * (FREQ_SYS * 2 / R8_UART3_DIV) / 16 / baudrate; + x = (x + 5) / 10; + R16_UART3_DL = (UINT16)x; +} + +/******************************************************************************* + * @fn UART0_ByteTrigCfg + * + * @brief Serial byte trigger interrupt configuration + * + * @param b - trigger bytes + * refer to UARTByteTRIGTypeDef + * @return None + */ +void UART0_ByteTrigCfg(UARTByteTRIGTypeDef b) +{ + R8_UART0_FCR = (R8_UART0_FCR & ~RB_FCR_FIFO_TRIG) | (b << 6); +} + +/******************************************************************************* + * @fn UART1_ByteTrigCfg + * + * @brief Serial byte trigger interrupt configuration + * + * @param b - trigger bytes + * refer to UARTByteTRIGTypeDef + * @return None + **/ +void UART1_ByteTrigCfg(UARTByteTRIGTypeDef b) +{ + R8_UART1_FCR = (R8_UART1_FCR & ~RB_FCR_FIFO_TRIG) | (b << 6); +} + +/******************************************************************************* + * @fn UART2_ByteTrigCfg + * + * @brief Serial byte trigger interrupt configuration + * + * @param b - trigger bytes + * refer to UARTByteTRIGTypeDef + * @return None + */ +void UART2_ByteTrigCfg(UARTByteTRIGTypeDef b) +{ + R8_UART2_FCR = (R8_UART2_FCR & ~RB_FCR_FIFO_TRIG) | (b << 6); +} + +/******************************************************************************* + * @fn UART3_ByteTrigCfg + * + * @brief Serial byte trigger interrupt configuration + * + * @param b - trigger bytes + * refer to UARTByteTRIGTypeDef + * @return None + ***/ +void UART3_ByteTrigCfg(UARTByteTRIGTypeDef b) +{ + R8_UART3_FCR = (R8_UART3_FCR & ~RB_FCR_FIFO_TRIG) | (b << 6); +} + +/******************************************************************************* + * @fn UART0_INTCfg + * + * @brief Serial port interrupt configuration + * + * @param s - interrupt control status + * ENABLE - Enable the corresponding interrupt + * DISABLE - Disable the corresponding interrupt + * i - interrupt type + * RB_IER_MODEM_CHG - Modem input status change interrupt enable bit (supported on UART0 only) + * RB_IER_LINE_STAT - Receive Line Status Interrupt + * RB_IER_THR_EMPTY - Send Holding Register Empty Interrupt + * RB_IER_RECV_RDY - receive data interrupt + * @return None + **/ +void UART0_INTCfg(UINT8 s, UINT8 i) +{ + if (s) + { + R8_UART0_IER |= i; + R8_UART0_MCR |= RB_MCR_INT_OE; + } + else + { + R8_UART0_IER &= ~i; + } +} + +/******************************************************************************* + * @fn UART1_INTCfg + * + * @brief Serial port interrupt configuration + * + * @param s - interrupt control status + * ENABLE - Enable the corresponding interrupt + * DISABLE - Disable the corresponding interrupt + * i - interrupt type + * RB_IER_MODEM_CHG - Modem input status change interrupt enable bit (supported on UART0 only) + * RB_IER_LINE_STAT - Receive Line Status Interrupt + * RB_IER_THR_EMPTY - Send Holding Register Empty Interrupt + * RB_IER_RECV_RDY - receive data interrupt + * @return None + **/ +void UART1_INTCfg(UINT8 s, UINT8 i) +{ + if (s) + { + R8_UART1_IER |= i; + R8_UART1_MCR |= RB_MCR_INT_OE; + } + else + { + R8_UART1_IER &= ~i; + } +} + +/******************************************************************************* + * @fn UART2_INTCfg + * + * @brief Serial port interrupt configuration + * + * @param s - interrupt control status + * ENABLE - Enable the corresponding interrupt + * DISABLE - Disable the corresponding interrupt + * i - interrupt type + * RB_IER_MODEM_CHG - Modem input status change interrupt enable bit (supported on UART0 only) + * RB_IER_LINE_STAT - Receive Line Status Interrupt + * RB_IER_THR_EMPTY - Send Holding Register Empty Interrupt + * RB_IER_RECV_RDY - receive data interrupt + * @return None + **/ +void UART2_INTCfg(UINT8 s, UINT8 i) +{ + if (s) + { + R8_UART2_IER |= i; + R8_UART2_MCR |= RB_MCR_INT_OE; + } + else + { + R8_UART2_IER &= ~i; + } +} + +/******************************************************************************* + * @fn UART3_INTCfg + * + * @brief Serial port interrupt configuration + * + * @param s - interrupt control status + * ENABLE - Enable the corresponding interrupt + * DISABLE - Disable the corresponding interrupt + * i - interrupt type + * RB_IER_MODEM_CHG - Modem input status change interrupt enable bit (supported on UART0 only) + * RB_IER_LINE_STAT - Receive Line Status Interrupt + * RB_IER_THR_EMPTY - Send Holding Register Empty Interrupt + * RB_IER_RECV_RDY - receive data interrupt + * @return None + **/ +void UART3_INTCfg(UINT8 s, UINT8 i) +{ + if (s) + { + R8_UART3_IER |= i; + R8_UART3_MCR |= RB_MCR_INT_OE; + } + else + { + R8_UART3_IER &= ~i; + } +} + +/******************************************************************************* + * @fn UART0_Reset + * + * @brief Serial port software reset + * + * @return None + **/ +void UART0_Reset(void) +{ + R8_UART0_IER = RB_IER_RESET; +} + +/******************************************************************************* + * @fn UART1_Reset + * + * @brief Serial port software reset + * + * @return None + **/ +void UART1_Reset(void) +{ + R8_UART1_IER = RB_IER_RESET; +} + +/******************************************************************************* + * @fn UART2_Reset + * + * @brief Serial port software reset + * + * @return None + **/ +void UART2_Reset(void) +{ + R8_UART2_IER = RB_IER_RESET; +} + +/******************************************************************************* + * @fn UART3_Reset + * + * @brief Serial port software reset + * + * @return None + **/ +void UART3_Reset(void) +{ + R8_UART3_IER = RB_IER_RESET; +} + +/******************************************************************************* + * @fn UART0_SendString + * + * @brief Serial multi-byte transmission + * + * @param buf - The first address of the data content to be sent + * l - length of data to be sent + * @return None + */ +void UART0_SendString(PUINT8 buf, UINT16 l) +{ + UINT16 len = l; + + while (len) + { + if (R8_UART0_TFC != UART_FIFO_SIZE) + { + R8_UART0_THR = *buf++; + len--; + } + } +} + +/******************************************************************************* + * @fn UART1_SendString + * + * @brief Serial multi-byte transmission + * + * @param buf - The first address of the data content to be sent + * l - length of data to be sent + * @return None + */ +void UART1_SendString(PUINT8 buf, UINT16 l) +{ + UINT16 len = l; + + while (len) + { + if (R8_UART1_TFC != UART_FIFO_SIZE) + { + R8_UART1_THR = *buf++; + len--; + } + } +} + +/******************************************************************************* + * @fn UART2_SendString + * + * @brief Serial multi-byte transmission + * + * @param buf - The first address of the data content to be sent + * l - length of data to be sent + * @return None + */ +void UART2_SendString(PUINT8 buf, UINT16 l) +{ + UINT16 len = l; + + while (len) + { + if (R8_UART2_TFC != UART_FIFO_SIZE) + { + R8_UART2_THR = *buf++; + len--; + } + } +} + +/******************************************************************************* + * @fn UART3_SendString + * + * @brief Serial multi-byte transmission + * + * @param buf - The first address of the data content to be sent + * l - length of data to be sent + * @return None + */ +void UART3_SendString(PUINT8 buf, UINT16 l) +{ + UINT16 len = l; + + while (len) + { + if (R8_UART3_TFC != UART_FIFO_SIZE) + { + R8_UART3_THR = *buf++; + len--; + } + } +} + +/******************************************************************************* + * @fn UART0_RecvString + * + * @brief Serial port read multibyte + * + * @param buf - The first address of the read data storage buffer + * + * @return read data length + */ +UINT16 UART0_RecvString(PUINT8 buf) +{ + UINT16 len = 0; + + while (R8_UART0_RFC) + { + *buf++ = R8_UART0_RBR; + len++; + } + + return (len); +} + +/******************************************************************************* + * @fn UART1_RecvString + * + * @brief Serial port read multibyte + * + * @param buf - The first address of the read data storage buffer + * + * @return read data length + */ + +UINT16 UART1_RecvString(PUINT8 buf) +{ + UINT16 len = 0; + + while (R8_UART1_RFC) + { + *buf++ = R8_UART1_RBR; + len++; + } + + return (len); +} + +/******************************************************************************* + * @fn UART2_RecvString + * + * @brief Serial port read multibyte + * + * @param buf - The first address of the read data storage buffer + * + * @return read data length + */ + +UINT16 UART2_RecvString(PUINT8 buf) +{ + UINT16 len = 0; + + while (R8_UART2_RFC) + { + *buf++ = R8_UART2_RBR; + len++; + } + + return (len); +} + +/******************************************************************************* + * @fn UART3_RecvString + * + * @brief Serial port read multibyte + * + * @param buf - The first address of the read data storage buffer + * + * @return read data length + */ + +UINT16 UART3_RecvString(PUINT8 buf) +{ + UINT16 len = 0; + + while (R8_UART3_RFC) + { + *buf++ = R8_UART3_RBR; + len++; + } + + return (len); +}