Support the M33 of the RZ/V2L development board

2024-01-08 14:01:53 +08:00
parent 9d546c8c02
commit 05aa2078c8
179 changed files with 157582 additions and 2 deletions
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BOARD_CFG_H_
+#define BOARD_CFG_H_
+#include "../../../rzv/board/rzv2l_smarc/board.h"
+#endif /* BOARD_CFG_H_ */
@@ -0,0 +1,29 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+#include "bsp_clock_cfg.h"
+#include "bsp_mcu_family_cfg.h"
+#include "board_cfg.h"
+#define FSP_NOT_DEFINED 0
+#ifndef BSP_CFG_RTOS
+#if (FSP_NOT_DEFINED) != (FSP_NOT_DEFINED)
+  #define BSP_CFG_RTOS (2)
+ #elif (FSP_NOT_DEFINED) != (FSP_NOT_DEFINED)
+  #define BSP_CFG_RTOS (1)
+ #else
+#define BSP_CFG_RTOS (0)
+#endif
+#endif
+#undef FSP_NOT_DEFINED
+#define BSP_CFG_MCU_VCC_MV (3300)
+#define BSP_CFG_S_STACK_MAIN_BYTES (0x200)
+#define BSP_CFG_STACK_MAIN_BYTES (0x5000)
+#define BSP_CFG_HEAP_BYTES (0xf000)
+#define BSP_CFG_PARAM_CHECKING_ENABLE (0)
+#define BSP_CFG_ASSERT (0)
+#define BSP_CFG_ERROR_LOG (0)
+
+#define BSP_CFG_PFS_PROTECT ((1))
+
+#define BSP_CFG_C_RUNTIME_INIT ((1))
+#endif /* BSP_CFG_H_ */
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_CFG_H_
+#define BSP_MCU_DEVICE_CFG_H_
+#define BSP_CFG_MCU_PART_SERIES (2)
+#endif /* BSP_MCU_DEVICE_CFG_H_ */
@@ -0,0 +1,9 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R9A07G054L23GBG_CM33
+#define BSP_ROM_SIZE_BYTES (0)
+#define BSP_RAM_SIZE_BYTES (131072)
+#define BSP_PACKAGE_LFBGA
+#define BSP_PACKAGE_PINS (456)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
@@ -0,0 +1,49 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+#include "bsp_mcu_device_pn_cfg.h"
+#include "bsp_mcu_device_cfg.h"
+#include "bsp_mcu_info.h"
+#include "bsp_clock_cfg.h"
+#define BSP_MCU_GROUP_RZV2L (1)
+#define BSP_CORTEX_VECTOR_TABLE_ENTRIES    (16U)
+#define BSP_VECTOR_TABLE_MAX_ENTRIES       (496U)
+
+#if defined(_RZV2L_TZ_SECURE)
+            #define BSP_TZ_SECURE_BUILD           (1)
+            #define BSP_TZ_NONSECURE_BUILD        (0)
+            #elif defined(_RZV2L_TZ_NONSECURE)
+            #define BSP_TZ_SECURE_BUILD           (0)
+            #define BSP_TZ_NONSECURE_BUILD        (1)
+            #else
+#define BSP_TZ_SECURE_BUILD           (0)
+#define BSP_TZ_NONSECURE_BUILD        (0)
+#endif
+
+/* TrustZone Settings */
+#define BSP_TZ_CFG_INIT_SECURE_ONLY       (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
+#define BSP_TZ_CFG_SKIP_INIT              (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
+
+#define SCB_SCR_SLEEPDEEPS_VAL            (0)
+#define SCB_SCR_SLEEPDEEP_VAL             (0)
+
+/* CMSIS TrustZone Settings */
+#define SCB_CSR_AIRCR_INIT                (1)
+#define SCB_AIRCR_BFHFNMINS_VAL           (1)
+#define SCB_AIRCR_SYSRESETREQS_VAL        (0)
+#define SCB_AIRCR_PRIS_VAL                (0)
+#define TZ_FPU_NS_USAGE                   (1)
+#ifndef SCB_NSACR_CP10_11_VAL
+#define SCB_NSACR_CP10_11_VAL             (3U)
+#endif
+#define SCB_SHCSR_SECUREFAULTENA_VAL	  (1)
+
+#ifndef FPU_FPCCR_TS_VAL
+#define FPU_FPCCR_TS_VAL                  (0U)
+#endif
+#define FPU_FPCCR_CLRONRETS_VAL           (0)
+
+#ifndef FPU_FPCCR_CLRONRET_VAL
+#define FPU_FPCCR_CLRONRET_VAL            (1)
+#endif
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
@@ -0,0 +1,9 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_PIN_CFG_H_
+#define BSP_PIN_CFG_H_
+#include "r_ioport.h"
+
+extern const ioport_cfg_t g_bsp_pin_cfg; /* RZV2L-SMARC.pincfg */
+
+void BSP_PinConfigSecurityInit();
+#endif /* BSP_PIN_CFG_H_ */
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef R_GTM_CFG_H_
+#define R_GTM_CFG_H_
+#define GTM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+#endif /* R_GTM_CFG_H_ */
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+#endif /* R_IOPORT_CFG_H_ */
@@ -0,0 +1,6 @@
+/* generated configuration header file - do not edit */
+#ifndef R_SCIF_UART_CFG_H_
+#define R_SCIF_UART_CFG_H_
+#define SCIF_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+#define SCIF_UART_CFG_FLOW_CONTROL_SUPPORT (0)
+#endif /* R_SCIF_UART_CFG_H_ */