forked from xuos/xiuos
fead support Ubiquitous/XiZi/board/xidatong bsp
This commit is contained in:
Liu_Weichao
parent
31697c14f2
commit
57c22182c2
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@ -6,7 +6,8 @@ MAKEFLAGS += --no-print-directory
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support :=kd233 stm32f407-st-discovery maix-go stm32f407zgt6 aiit-riscv64-board aiit-arm32-board hifive1-rev-B hifive1-emulator k210-emulator cortex-m3-emulator cortex-m4-emulator ok1052-c gapuino stm32f103-nano gd32vf103_rvstar cortex-m0-emulator rv32m1_vega nuvoton-m2354
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SRC_DIR:=
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support += xidatong
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SRC_DIR :=
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export BOARD ?=kd233
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# This is the environment variable for kconfig-mconf
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@ -0,0 +1,59 @@
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mainmenu "XiZi Project Configuration"
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config BSP_DIR
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string
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option env="BSP_ROOT"
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default "."
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config KERNEL_DIR
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string
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option env="KERNEL_ROOT"
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default "../.."
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config BOARD_CORTEX_M7_EVB
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bool
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select ARCH_ARM
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default y
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source "$KERNEL_DIR/arch/Kconfig"
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menu "xidatong feature"
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source "$BSP_DIR/third_party_driver/Kconfig"
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menu "config default board resources"
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menu "config board app name"
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config BOARD_APP_NAME
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string "config board app name"
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default "/XiUOS_xidatong_app.bin"
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endmenu
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menu "config board service table"
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config SERVICE_TABLE_ADDRESS
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hex "board service table address"
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default 0x2007F0000
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endmenu
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endmenu
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config __STACKSIZE__
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int "stack size for interrupt"
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default 4096
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menu "config board peripheral"
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config MOUNT_SDCARD
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bool "mount cd card"
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default n
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select BSP_USING_SDIO
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endmenu
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endmenu
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menu "Hardware feature"
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source "$KERNEL_DIR/resources/Kconfig"
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endmenu
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source "$KERNEL_DIR/Kconfig"
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@ -0,0 +1,5 @@
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SRC_DIR := third_party_driver
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SRC_FILES := board.c
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include $(KERNEL_ROOT)/compiler.mk
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@ -0,0 +1,163 @@
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# 从零开始构建矽璓工业物联操作系统：使用ARM架构的矽达通
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# xidatong
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[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓XiUOS是一款面向智慧车间的工业物联网操作系统，主要由一个极简的微型实时操作系统内核和其上的工业物联框架构成，通过高效管理工业物联网设备、支撑工业物联应用，在生产车间内实现智能化的“感知环境、联网传输、知悉识别、控制调整”，促进以工业设备和工业控制系统为核心的人、机、物深度互联，帮助提升生产线的数字化和智能化水平。
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## 1. 简介
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| 硬件 | 描述 |
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| -- | -- |
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|芯片型号| MIMXRT1052DVL6A |
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|架构| cortex-m7 |
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|主频| 600MHz |
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|片内SRAM| 512KB shared with TCM |
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|外设支持| UART |
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XiUOS板级当前支持使用UART。
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## 2. 开发环境搭建
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### 推荐使用：
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**操作系统：** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop)
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更新`ubuntu 18.04`源的方法:（根据自身情况而定，可以不更改）
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第一步:打开sources.list文件
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```c
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sudo vim /etc/apt/sources.list
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```
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第二步:将以下内容复制到sources.list文件
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```c
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deb http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse
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deb http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse
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deb http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse
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deb http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse
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deb http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse
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deb-src http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse
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deb-src http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse
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deb-src http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse
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deb-src http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse
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deb-src http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse
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```
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第三步:更新源和系统软件
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```c
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sudo apt-get update
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sudo apt-get upgrade
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```
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**开发工具推荐使用 VSCode ，VScode下载地址为：** VSCode [https://code.visualstudio.com/](https://code.visualstudio.com/)，推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb)
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### 依赖包安装：
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```
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$ sudo apt install build-essential pkg-config git
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$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev
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```
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**XiUOS操作系统源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos)
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新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下：
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```c
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mkdir test && cd test
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git clone https://gitlink.org.cn/xuos/xiuos.git
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```
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1、打开XiUOS源码文件包可以看到以下目录：
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| 名称 | 说明 |
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| -- | -- |
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| APP_Framework | 应用代码 |
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| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 |
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2、打开XiZi内核源码文件包可以看到以下目录：
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| 名称 | 说明 |
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| -- | -- |
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| arch | 架构代码 |
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| board | 板级支持包 |
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| fs | 文件系统 |
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| kernel | 内核源码 |
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| lib | 第三方库源码 |
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| resources | 驱动文件 |
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| tool | 系统工具 |
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使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示：
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<div align= "center">
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<img src = ./img/vscode.jpg width =1000>
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</div>
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### 裁减配置工具的下载
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裁减配置工具：
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**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)，下载与安装的具体命令如下：
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```c
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mkdir kfrontends && cd kfrontends
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git clone https://gitlink.org.cn/xuos/kconfig-frontends.git
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```
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下载源码后按以下步骤执行软件安装：
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```c
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cd kconfig-frontends
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./xs_build.sh
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```
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### 编译工具链：
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ARM： arm-none-eabi(`gcc version 6.3.1`)，默认安装到Ubuntu的/usr/bin/arm-none-eabi-，使用如下命令行下载和安装。
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```shell
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$ sudo apt install gcc-arm-none-eabi
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```
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## 编译说明
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### 编辑环境：`Ubuntu18.04`
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### 编译工具链：`arm-none-eabi-gcc`
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使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入linux系统命令终端即可打开目标项目
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编译步骤：
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1.在VScode命令终端中执行以下命令，生成配置文件
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```c
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cd ./Ubiquitous/XiZi
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make BOARD=xidatong distclean
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make BOARD=xidatong menuconfig
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```
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2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置）
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退出时选择`yes`保存上面所配置的内容，如下图所示：
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3.继续执行以下命令，进行编译
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```
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make BOARD=xidatong
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```
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4.如果编译正确无误，会产生XiZi_xidatong.elf、XiZi_xidatong.bin文件。
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## 3. 烧写及运行
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### 3.1 烧写
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### 3.2 运行结果
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@ -0,0 +1,683 @@
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/*
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* Copyright 2017 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/**
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* @file board.c
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* @brief relative configure for xidatong
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* @version 1.0
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* @author AIIT XUOS Lab
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* @date 2021.11.11
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*/
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/*************************************************
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File name: board.c
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Description: support imxrt1052-board init function
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Others: take SDK_2.6.1_MIMXRT1052xxxxB for references
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History:
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1. Date: 2022-01-25
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Author: AIIT XUOS Lab
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Modification:
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1. support imxrt1052-board MPU、clock、memory init
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2. support imxrt1052-board uart、semc、sdio driver init
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*************************************************/
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#include "fsl_common.h"
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#include "board.h"
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#include "pin_mux.h"
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#ifdef BSP_USING_SDIO
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extern int Imrt1052HwSdioInit(void);
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#endif
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#ifdef BSP_USING_SEMC
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extern status_t BOARD_InitSEMC(void);
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#ifdef BSP_USING_EXTSRAM
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extern int ExtSramInit(void);
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#endif
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#endif
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#if defined(FS_VFS) && defined(MOUNT_SDCARD)
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#include <iot-vfs.h>
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/**
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* @description: Mount SD card
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* @return 0
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*/
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int MountSDCard(void)
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{
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if (MountFilesystem(SDIO_BUS_NAME, SDIO_DEVICE_NAME, SDIO_DRIVER_NAME, FSTYPE_FATFS, "/") == 0)
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KPrintf("sd card mount to '/'");
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else
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KPrintf("sd card mount to '/' failed!");
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return 0;
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}
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#endif
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#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
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#include "fsl_lpi2c.h"
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#endif /* SDK_I2C_BASED_COMPONENT_USED */
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#include "fsl_iomuxc.h"
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#include "fsl_gpio.h"
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#include "fsl_lpuart.h"
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#ifdef BSP_USING_LPUART
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#include <connect_uart.h>
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#endif
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#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
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4 bits for subpriority */
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#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
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3 bits for subpriority */
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#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
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2 bits for subpriority */
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#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
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1 bits for subpriority */
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#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*******************************************************************************
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* Code
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******************************************************************************/
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#if 0
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/* Get debug console frequency. */
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uint32_t BOARD_DebugConsoleSrcFreq(void)
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{
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uint32_t freq;
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/* To make it simple, we assume default PLL and divider settings, and the only variable
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from application is use PLL3 source or OSC source */
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if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
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{
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freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
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}
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else
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{
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freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
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}
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return freq;
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}
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/* Initialize debug console. */
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void BOARD_InitDebugConsole(void)
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{
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uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
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DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
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}
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#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
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void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
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{
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lpi2c_master_config_t lpi2cConfig = {0};
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/*
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* lpi2cConfig.debugEnable = false;
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* lpi2cConfig.ignoreAck = false;
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* lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
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* lpi2cConfig.baudRate_Hz = 100000U;
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* lpi2cConfig.busIdleTimeout_ns = 0;
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* lpi2cConfig.pinLowTimeout_ns = 0;
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* lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
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* lpi2cConfig.sclGlitchFilterWidth_ns = 0;
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*/
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LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
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LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
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}
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status_t BOARD_LPI2C_Send(LPI2C_Type *base,
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uint8_t deviceAddress,
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uint32_t subAddress,
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uint8_t subAddressSize,
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uint8_t *txBuff,
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uint8_t txBuffSize)
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{
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status_t reVal;
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/* Send master blocking data to slave */
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reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write);
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if (kStatus_Success == reVal)
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{
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while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag)
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{
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}
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reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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reVal = LPI2C_MasterSend(base, txBuff, txBuffSize);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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reVal = LPI2C_MasterStop(base);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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}
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return reVal;
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}
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status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
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uint8_t deviceAddress,
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uint32_t subAddress,
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uint8_t subAddressSize,
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uint8_t *rxBuff,
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uint8_t rxBuffSize)
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{
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status_t reVal;
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reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write);
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if (kStatus_Success == reVal)
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{
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while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag)
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{
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}
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reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize);
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if (reVal != kStatus_Success)
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{
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return reVal;
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}
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reVal = LPI2C_MasterRepeatedStart(base, deviceAddress, kLPI2C_Read);
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if (reVal != kStatus_Success)
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{
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return reVal;
|
||||
}
|
||||
|
||||
reVal = LPI2C_MasterReceive(base, rxBuff, rxBuffSize);
|
||||
if (reVal != kStatus_Success)
|
||||
{
|
||||
return reVal;
|
||||
}
|
||||
|
||||
reVal = LPI2C_MasterStop(base);
|
||||
if (reVal != kStatus_Success)
|
||||
{
|
||||
return reVal;
|
||||
}
|
||||
}
|
||||
return reVal;
|
||||
}
|
||||
|
||||
status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subAddressSize,
|
||||
uint8_t *txBuff,
|
||||
uint8_t txBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Send(base, deviceAddress, subAddress, subAddressSize, txBuff, txBuffSize);
|
||||
}
|
||||
|
||||
status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subAddressSize,
|
||||
uint8_t *rxBuff,
|
||||
uint8_t rxBuffSize)
|
||||
{
|
||||
status_t reVal;
|
||||
|
||||
reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write);
|
||||
if (kStatus_Success == reVal)
|
||||
{
|
||||
while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag)
|
||||
{
|
||||
}
|
||||
|
||||
reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize);
|
||||
if (reVal != kStatus_Success)
|
||||
{
|
||||
return reVal;
|
||||
}
|
||||
|
||||
/* SCCB does not support LPI2C repeat start, must stop then start. */
|
||||
reVal = LPI2C_MasterStop(base);
|
||||
|
||||
if (reVal != kStatus_Success)
|
||||
{
|
||||
return reVal;
|
||||
}
|
||||
|
||||
reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Read);
|
||||
|
||||
if (reVal != kStatus_Success)
|
||||
{
|
||||
return reVal;
|
||||
}
|
||||
|
||||
reVal = LPI2C_MasterReceive(base, rxBuff, rxBuffSize);
|
||||
if (reVal != kStatus_Success)
|
||||
{
|
||||
return reVal;
|
||||
}
|
||||
|
||||
reVal = LPI2C_MasterStop(base);
|
||||
if (reVal != kStatus_Success)
|
||||
{
|
||||
return reVal;
|
||||
}
|
||||
}
|
||||
return reVal;
|
||||
}
|
||||
|
||||
void BOARD_Accel_I2C_Init(void)
|
||||
{
|
||||
BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
|
||||
}
|
||||
|
||||
status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
|
||||
{
|
||||
uint8_t data = (uint8_t)txBuff;
|
||||
|
||||
return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
|
||||
}
|
||||
|
||||
status_t BOARD_Accel_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
|
||||
}
|
||||
|
||||
void BOARD_Codec_I2C_Init(void)
|
||||
{
|
||||
BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
|
||||
}
|
||||
|
||||
status_t BOARD_Codec_I2C_Send(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
|
||||
txBuffSize);
|
||||
}
|
||||
|
||||
status_t BOARD_Codec_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
|
||||
}
|
||||
|
||||
void BOARD_Camera_I2C_Init(void)
|
||||
{
|
||||
CLOCK_SetMux(kCLOCK_Lpi2cMux, BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT);
|
||||
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER);
|
||||
BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ);
|
||||
}
|
||||
|
||||
status_t BOARD_Camera_I2C_Send(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
|
||||
txBuffSize);
|
||||
}
|
||||
|
||||
status_t BOARD_Camera_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
|
||||
rxBuffSize);
|
||||
}
|
||||
|
||||
status_t BOARD_Camera_I2C_SendSCCB(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
|
||||
txBuffSize);
|
||||
}
|
||||
|
||||
status_t BOARD_Camera_I2C_ReceiveSCCB(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
|
||||
{
|
||||
return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
|
||||
rxBuffSize);
|
||||
}
|
||||
#endif /* SDK_I2C_BASED_COMPONENT_USED */
|
||||
#endif
|
||||
|
||||
|
||||
void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength)
|
||||
{
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD,
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK,
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0,
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1,
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2,
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3,
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
||||
}
|
||||
|
||||
void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength)
|
||||
{
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_05_USDHC2_CMD,
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_04_USDHC2_CLK,
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0,
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1,
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2,
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3,
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4,
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5,
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6,
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7,
|
||||
IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
|
||||
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
|
||||
IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
|
||||
}
|
||||
|
||||
/* MPU configuration. */
|
||||
void BOARD_ConfigMPU(void)
|
||||
{
|
||||
/* Disable I cache and D cache */
|
||||
if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
|
||||
{
|
||||
SCB_DisableICache();
|
||||
}
|
||||
if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
|
||||
{
|
||||
SCB_DisableDCache();
|
||||
}
|
||||
|
||||
/* Disable MPU */
|
||||
ARM_MPU_Disable();
|
||||
|
||||
/* MPU configure:
|
||||
* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
|
||||
* SubRegionDisable, Size)
|
||||
* API in mpu_armv7.h.
|
||||
* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
|
||||
* disabled.
|
||||
* param AccessPermission Data access permissions, allows you to configure read/write access for User and
|
||||
* Privileged mode.
|
||||
* Use MACROS defined in mpu_armv7.h:
|
||||
* ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
|
||||
* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
|
||||
* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
|
||||
* 0 x 0 0 Strongly Ordered shareable
|
||||
* 0 x 0 1 Device shareable
|
||||
* 0 0 1 0 Normal not shareable Outer and inner write
|
||||
* through no write allocate
|
||||
* 0 0 1 1 Normal not shareable Outer and inner write
|
||||
* back no write allocate
|
||||
* 0 1 1 0 Normal shareable Outer and inner write
|
||||
* through no write allocate
|
||||
* 0 1 1 1 Normal shareable Outer and inner write
|
||||
* back no write allocate
|
||||
* 1 0 0 0 Normal not shareable outer and inner
|
||||
* noncache
|
||||
* 1 1 0 0 Normal shareable outer and inner
|
||||
* noncache
|
||||
* 1 0 1 1 Normal not shareable outer and inner write
|
||||
* back write/read acllocate
|
||||
* 1 1 1 1 Normal shareable outer and inner write
|
||||
* back write/read acllocate
|
||||
* 2 x 0 0 Device not shareable
|
||||
* Above are normal use settings, if your want to see more details or want to config different inner/outter cache
|
||||
* policy.
|
||||
* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
|
||||
* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
|
||||
* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
|
||||
* mpu_armv7.h.
|
||||
*/
|
||||
|
||||
/* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
|
||||
|
||||
/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
|
||||
|
||||
/* Region 2 setting */
|
||||
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
|
||||
/* Setting Memory with Normal type, not shareable, outer/inner write back. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
|
||||
#else
|
||||
/* Setting Memory with Device type, not shareable, non-cacheable. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_64MB);
|
||||
#endif
|
||||
|
||||
/* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
|
||||
|
||||
/* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||
MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
|
||||
|
||||
/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||
MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
|
||||
|
||||
/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||
MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
|
||||
|
||||
/* The define sets the cacheable memory to shareable,
|
||||
* this suggestion is referred from chapter 2.2.1 Memory regions,
|
||||
* types and attributes in Cortex-M7 Devices, Generic User Guide */
|
||||
#if defined(SDRAM_IS_SHAREABLE)
|
||||
/* Region 7 setting: Memory with Normal type, shareable, outer/inner write back */
|
||||
MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
|
||||
#else
|
||||
/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||
MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
|
||||
#endif
|
||||
|
||||
/* Region 8 setting, set last 2MB of SDRAM can't be accessed by cache, glocal variables which are not expected to be
|
||||
* accessed by cache can be put here */
|
||||
/* Memory with Normal type, not shareable, non-cacheable */
|
||||
MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
|
||||
|
||||
/* Enable MPU */
|
||||
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
|
||||
|
||||
/* Enable I cache and D cache */
|
||||
SCB_EnableDCache();
|
||||
SCB_EnableICache();
|
||||
}
|
||||
|
||||
|
||||
/* This is the timer interrupt service routine. */
|
||||
void SysTick_Handler(int irqn, void *arg)
|
||||
{
|
||||
TickAndTaskTimesliceUpdate();
|
||||
}
|
||||
DECLARE_HW_IRQ(SYSTICK_IRQN, SysTick_Handler, NONE);
|
||||
|
||||
#ifdef BSP_USING_LPUART
|
||||
void imxrt_uart_pins_init(void)
|
||||
{
|
||||
#ifdef BSP_USING_LPUART1
|
||||
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
|
||||
0x10B0u); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
|
||||
0x10B0u); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
#endif
|
||||
#ifdef BSP_USING_LPUART2
|
||||
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
|
||||
0U);
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
|
||||
0U);
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
|
||||
0x10B0u);
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
|
||||
0x10B0u);
|
||||
|
||||
#endif
|
||||
|
||||
}
|
||||
#endif /* BSP_USING_LPUART */
|
||||
|
||||
/**
|
||||
* This function will initial rt1050 board.
|
||||
*/
|
||||
void InitBoardHardware()
|
||||
{
|
||||
BOARD_ConfigMPU();
|
||||
BOARD_InitPins();
|
||||
BOARD_BootClockRUN();
|
||||
|
||||
#ifndef BSP_USING_LWIP
|
||||
NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
||||
SysTick_Config(SystemCoreClock / TICK_PER_SECOND);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_LPUART
|
||||
imxrt_uart_pins_init();
|
||||
#endif
|
||||
|
||||
InitBoardMemory((void *)HEAP_BEGIN, (void *)HEAP_END);
|
||||
#ifdef BSP_USING_SEMC
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd2, 29);
|
||||
/* Set semc clock to 163.86 MHz */
|
||||
CLOCK_SetMux(kCLOCK_SemcMux, 1);
|
||||
CLOCK_SetDiv(kCLOCK_SemcDiv, 1);
|
||||
|
||||
if (BOARD_InitSEMC() != kStatus_Success) {
|
||||
KPrintf("\r\n SEMC Init Failed\r\n");
|
||||
}
|
||||
#ifdef MEM_EXTERN_SRAM
|
||||
else {
|
||||
ExtSramInit();
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_LWIP
|
||||
ETH_BSP_Config();
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_LPUART
|
||||
Imrt1052HwUartInit();
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_ADC
|
||||
Imrt1052HwAdcInit();
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_SPI
|
||||
Imrt1052HwSpiInit();
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_RTC
|
||||
Imrt1052HwRtcInit();
|
||||
#endif
|
||||
|
||||
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
|
||||
|
||||
#ifdef BSP_USING_SDIO
|
||||
Imrt1052HwSdioInit();
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
|
||||
|
||||
export CFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb
|
||||
export AFLAGS := -c -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2
|
||||
|
||||
### if use USB function, use special lds file because USB uses ITCM
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_USB),y)
|
||||
export LFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi_xidatong.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link-usb.lds
|
||||
else
|
||||
export LFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi_xidatong.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
|
||||
endif
|
||||
|
||||
export CXXFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g
|
||||
|
||||
export APPLFLAGS := -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
|
||||
|
||||
|
||||
export DEFINES := -DHAVE_CCONFIG_H -DCPU_MIMXRT1052CVL5B -DSKIP_SYSCLK_INIT -DEVK_MCIMXRM -DFSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1 -DXIP_EXTERNAL_FLASH=1 -D__STARTUP_INITIALIZE_NONCACHEDATA -D__STARTUP_CLEAR_BSS
|
||||
|
||||
export ARCH = arm
|
||||
export MCU = cortex-m7
|
||||
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|
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|
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|
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|
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|
After Width: | Height: | Size: 18 KiB |
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|
After Width: | Height: | Size: 56 KiB |
|
|
@ -0,0 +1,309 @@
|
|||
/*
|
||||
* Copyright 2017-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file board.h
|
||||
* @brief define imxrt1052-board init configure and start-up function
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-05-28
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: board.h
|
||||
Description: define imxrt1052-board board init function and struct
|
||||
Others:
|
||||
History:
|
||||
1. Date: 2021-05-28
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. define imxrt-board InitBoardHardware
|
||||
2. define imxrt-board heap struct
|
||||
*************************************************/
|
||||
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_gpio.h"
|
||||
#include "fsl_clock.h"
|
||||
#include "fsl_enet.h"
|
||||
#include "clock_config.h"
|
||||
#include <xizi.h>
|
||||
#include <arch_interrupt.h>
|
||||
|
||||
extern int heap_start;
|
||||
extern int heap_end;
|
||||
#define HEAP_BEGIN (&heap_start)
|
||||
#define HEAP_END (&heap_end)
|
||||
|
||||
#define HEAP_SIZE ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN)
|
||||
|
||||
void InitBoardHardware(void);
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/*! @brief The board name */
|
||||
#define BOARD_NAME "IMXRT1050-EVKB"
|
||||
|
||||
/* The UART to use for debug messages. */
|
||||
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
|
||||
#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
|
||||
#define BOARD_DEBUG_UART_INSTANCE 1U
|
||||
|
||||
#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
|
||||
|
||||
#define BOARD_UART_IRQ LPUART1_IRQn
|
||||
#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
|
||||
|
||||
#ifndef BOARD_DEBUG_UART_BAUDRATE
|
||||
#define BOARD_DEBUG_UART_BAUDRATE (115200U)
|
||||
#endif /* BOARD_DEBUG_UART_BAUDRATE */
|
||||
|
||||
/*! @brief The USER_LED used for board */
|
||||
#define LOGIC_LED_ON (0U)
|
||||
#define LOGIC_LED_OFF (1U)
|
||||
#ifndef BOARD_USER_LED_GPIO
|
||||
#define BOARD_USER_LED_GPIO GPIO1
|
||||
#endif
|
||||
#ifndef BOARD_USER_LED_GPIO_PIN
|
||||
#define BOARD_USER_LED_GPIO_PIN (9U)
|
||||
#endif
|
||||
|
||||
#define USER_LED_INIT(output) \
|
||||
GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
|
||||
BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
|
||||
#define USER_LED_ON() \
|
||||
GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */
|
||||
#define USER_LED_OFF() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!<Turn on target USER_LED*/
|
||||
#define USER_LED_TOGGLE() \
|
||||
GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, \
|
||||
0x1 ^ GPIO_PinRead(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN)) /*!< Toggle target USER_LED */
|
||||
|
||||
/*! @brief Define the port interrupt number for the board switches */
|
||||
#ifndef BOARD_USER_BUTTON_GPIO
|
||||
#define BOARD_USER_BUTTON_GPIO GPIO5
|
||||
#endif
|
||||
#ifndef BOARD_USER_BUTTON_GPIO_PIN
|
||||
#define BOARD_USER_BUTTON_GPIO_PIN (0U)
|
||||
#endif
|
||||
#define BOARD_USER_BUTTON_IRQ GPIO5_Combined_0_15_IRQn
|
||||
#define BOARD_USER_BUTTON_IRQ_HANDLER GPIO5_Combined_0_15_IRQHandler
|
||||
#define BOARD_USER_BUTTON_NAME "SW8"
|
||||
|
||||
/*! @brief The hyper flash size */
|
||||
#define BOARD_FLASH_SIZE (0x4000000U)
|
||||
|
||||
/*! @brief The ENET PHY address. */
|
||||
#define BOARD_ENET0_PHY_ADDRESS (0x02U) /* Phy address of enet port 0. */
|
||||
|
||||
/* USB PHY condfiguration */
|
||||
#define BOARD_USB_PHY_D_CAL (0x0CU)
|
||||
#define BOARD_USB_PHY_TXCAL45DP (0x06U)
|
||||
#define BOARD_USB_PHY_TXCAL45DM (0x06U)
|
||||
|
||||
#define BOARD_ARDUINO_INT_IRQ (GPIO1_INT3_IRQn)
|
||||
#define BOARD_ARDUINO_I2C_IRQ (LPI2C1_IRQn)
|
||||
#define BOARD_ARDUINO_I2C_INDEX (1)
|
||||
#define BOARD_USDHC1_BASEADDR USDHC1
|
||||
#define BOARD_USDHC2_BASEADDR USDHC2
|
||||
#define BOARD_USDHC_CD_GPIO_BASE GPIO2
|
||||
#define BOARD_USDHC_CD_GPIO_PIN 28
|
||||
#define BOARD_USDHC_CD_PORT_IRQ GPIO2_Combined_16_31_IRQn
|
||||
#define BOARD_USDHC_CD_PORT_IRQ_HANDLER GPIO2_Combined_16_31_IRQHandler
|
||||
|
||||
#define BOARD_USDHC_CD_STATUS() (GPIO_PinRead(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN))
|
||||
|
||||
#define BOARD_USDHC_CD_INTERRUPT_STATUS() (GPIO_PortGetInterruptFlags(BOARD_USDHC_CD_GPIO_BASE))
|
||||
#define BOARD_USDHC_CD_CLEAR_INTERRUPT(flag) (GPIO_PortClearInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, flag))
|
||||
|
||||
#define BOARD_USDHC_CD_GPIO_INIT() \
|
||||
{ \
|
||||
gpio_pin_config_t sw_config = { \
|
||||
kGPIO_DigitalInput, \
|
||||
0, \
|
||||
kGPIO_IntRisingOrFallingEdge, \
|
||||
}; \
|
||||
GPIO_PinInit(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN, &sw_config); \
|
||||
GPIO_PortEnableInterrupts(BOARD_USDHC_CD_GPIO_BASE, 1U << BOARD_USDHC_CD_GPIO_PIN); \
|
||||
GPIO_PortClearInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, ~0); \
|
||||
}
|
||||
#define BOARD_HAS_SDCARD (1U)
|
||||
#define BOARD_SD_POWER_RESET_GPIO (GPIO1)
|
||||
#define BOARD_SD_POWER_RESET_GPIO_PIN (5U)
|
||||
|
||||
#define BOARD_USDHC_CARD_INSERT_CD_LEVEL (0U)
|
||||
|
||||
#define BOARD_USDHC_MMCCARD_POWER_CONTROL(state)
|
||||
|
||||
#define BOARD_USDHC_MMCCARD_POWER_CONTROL_INIT() \
|
||||
{ \
|
||||
gpio_pin_config_t sw_config = { \
|
||||
kGPIO_DigitalOutput, \
|
||||
0, \
|
||||
kGPIO_NoIntmode, \
|
||||
}; \
|
||||
GPIO_PinInit(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, &sw_config); \
|
||||
GPIO_PinWrite(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, true); \
|
||||
}
|
||||
|
||||
#define BOARD_USDHC_SDCARD_POWER_CONTROL_INIT() \
|
||||
{ \
|
||||
gpio_pin_config_t sw_config = { \
|
||||
kGPIO_DigitalOutput, \
|
||||
0, \
|
||||
kGPIO_NoIntmode, \
|
||||
}; \
|
||||
GPIO_PinInit(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, &sw_config); \
|
||||
}
|
||||
|
||||
#define BOARD_USDHC_SDCARD_POWER_CONTROL(state) \
|
||||
(GPIO_PinWrite(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, state))
|
||||
|
||||
#define BOARD_USDHC1_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) / (CLOCK_GetDiv(kCLOCK_Usdhc1Div) + 1U))
|
||||
#define BOARD_USDHC2_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) / (CLOCK_GetDiv(kCLOCK_Usdhc2Div) + 1U))
|
||||
|
||||
#define BOARD_SD_HOST_BASEADDR BOARD_USDHC1_BASEADDR
|
||||
#define BOARD_SD_HOST_CLK_FREQ BOARD_USDHC1_CLK_FREQ
|
||||
#define BOARD_SD_HOST_IRQ USDHC1_IRQn
|
||||
|
||||
#define BOARD_MMC_HOST_BASEADDR BOARD_USDHC2_BASEADDR
|
||||
#define BOARD_MMC_HOST_CLK_FREQ BOARD_USDHC2_CLK_FREQ
|
||||
#define BOARD_MMC_HOST_IRQ USDHC2_IRQn
|
||||
#define BOARD_MMC_VCCQ_SUPPLY kMMC_VoltageWindow170to195
|
||||
#define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360
|
||||
/* we are using the BB SD socket to DEMO the MMC example,but the
|
||||
* SD socket provide 4bit bus only, so we define this macro to avoid
|
||||
* 8bit data bus test
|
||||
*/
|
||||
#define BOARD_MMC_SUPPORT_8BIT_BUS (1U)
|
||||
|
||||
#define BOARD_SD_HOST_SUPPORT_SDR104_FREQ (200000000U)
|
||||
#define BOARD_SD_HOST_SUPPORT_HS200_FREQ (180000000U)
|
||||
|
||||
/*! @brief The WIFI-QCA shield pin. */
|
||||
#define BOARD_INITGT202SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
|
||||
#define BOARD_INITGT202SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
|
||||
#define BOARD_INITGT202SHIELD_PWRON_GPIO_PIN 3U /*!< PIO4 pin index: 3 */
|
||||
#define BOARD_INITGT202SHIELD_PWRON_PIN_NAME GPIO1_3 /*!< Pin name */
|
||||
#define BOARD_INITGT202SHIELD_PWRON_LABEL "PWRON" /*!< Label */
|
||||
#define BOARD_INITGT202SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
|
||||
#define BOARD_INITGT202SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
|
||||
|
||||
#define BOARD_INITGT202SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
|
||||
#define BOARD_INITGT202SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
|
||||
#define BOARD_INITGT202SHIELD_IRQ_GPIO_PIN 19U /*!< PIO1 pin index: 19 */
|
||||
#define BOARD_INITGT202SHIELD_IRQ_PIN_NAME GPIO1_19 /*!< Pin name */
|
||||
#define BOARD_INITGT202SHIELD_IRQ_LABEL "IRQ" /*!< Label */
|
||||
#define BOARD_INITGT202SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
|
||||
#define BOARD_INITGT202SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
|
||||
|
||||
/*! @brief The WIFI-QCA Silex 2401 shield pin. */
|
||||
#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
|
||||
#define BOARD_INITSILEX2401SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
|
||||
#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO_PIN 9U /*!< PIO4 pin index: 9 */
|
||||
#define BOARD_INITSILEX2401SHIELD_PWRON_PIN_NAME GPIO1_9 /*!< Pin name */
|
||||
#define BOARD_INITSILEX2401SHIELD_PWRON_LABEL "PWRON" /*!< Label */
|
||||
#define BOARD_INITSILEX2401SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
|
||||
#define BOARD_INITSILEX2401SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
|
||||
|
||||
#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
|
||||
#define BOARD_INITSILEX2401SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
|
||||
#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO_PIN 11U /*!< PIO1 pin index: 11 */
|
||||
#define BOARD_INITSILEX2401SHIELD_IRQ_PIN_NAME GPIO1_11 /*!< Pin name */
|
||||
#define BOARD_INITSILEX2401SHIELD_IRQ_LABEL "IRQ" /*!< Label */
|
||||
#define BOARD_INITSILEX2401SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
|
||||
#define BOARD_INITSILEX2401SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
|
||||
|
||||
/* @Brief Board accelerator sensor configuration */
|
||||
#define BOARD_ACCEL_I2C_BASEADDR LPI2C1
|
||||
/* Select USB1 PLL (480 MHz) as LPI2C's clock source */
|
||||
#define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U)
|
||||
/* Clock divider for LPI2C clock source */
|
||||
#define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U)
|
||||
#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U))
|
||||
|
||||
#define BOARD_CODEC_I2C_BASEADDR LPI2C1
|
||||
#define BOARD_CODEC_I2C_INSTANCE 1U
|
||||
#define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U)
|
||||
#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U)
|
||||
#define BOARD_CODEC_I2C_CLOCK_FREQ (10000000U)
|
||||
|
||||
/* @Brief Board CAMERA configuration */
|
||||
#define BOARD_CAMERA_I2C_BASEADDR LPI2C1
|
||||
#define BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER (5U)
|
||||
#define BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT (0U) /* Select USB1 PLL (480 MHz) as LPI2C's clock source */
|
||||
#define BOARD_CAMERA_I2C_CLOCK_FREQ \
|
||||
(CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER + 1U))
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
uint32_t BOARD_DebugConsoleSrcFreq(void);
|
||||
|
||||
void BOARD_InitDebugConsole(void);
|
||||
|
||||
void BOARD_ConfigMPU(void);
|
||||
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
|
||||
void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
|
||||
status_t BOARD_LPI2C_Send(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *txBuff,
|
||||
uint8_t txBuffSize);
|
||||
status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *rxBuff,
|
||||
uint8_t rxBuffSize);
|
||||
status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *txBuff,
|
||||
uint8_t txBuffSize);
|
||||
status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
|
||||
uint8_t deviceAddress,
|
||||
uint32_t subAddress,
|
||||
uint8_t subaddressSize,
|
||||
uint8_t *rxBuff,
|
||||
uint8_t rxBuffSize);
|
||||
void BOARD_Accel_I2C_Init(void);
|
||||
status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
|
||||
status_t BOARD_Accel_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||
void BOARD_Codec_I2C_Init(void);
|
||||
status_t BOARD_Codec_I2C_Send(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
|
||||
status_t BOARD_Codec_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||
void BOARD_Camera_I2C_Init(void);
|
||||
status_t BOARD_Camera_I2C_Send(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
|
||||
status_t BOARD_Camera_I2C_Receive(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||
|
||||
status_t BOARD_Camera_I2C_SendSCCB(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
|
||||
status_t BOARD_Camera_I2C_ReceiveSCCB(
|
||||
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
|
||||
#endif /* SDK_I2C_BASED_COMPONENT_USED */
|
||||
void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength);
|
||||
void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* _BOARD_H_ */
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
/*
|
||||
* Copyright 2017-2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file clock_config.h
|
||||
* @brief define imxrt1052-board clock configure
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-05-29
|
||||
*/
|
||||
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
|
||||
|
||||
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes default configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootClocks(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
|
||||
|
||||
/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
|
||||
/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
|
||||
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
/*
|
||||
* Copyright 2017-2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file pin_mux.h
|
||||
* @brief define imxrt1052-board pin configure
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-05-29
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _PIN_MUX_H_
|
||||
#define _PIN_MUX_H_
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*! @brief Direction type */
|
||||
typedef enum _pin_mux_direction
|
||||
{
|
||||
kPIN_MUX_DirectionInput = 0U, /* Input direction */
|
||||
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
|
||||
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
|
||||
} pin_mux_direction_t;
|
||||
|
||||
/*!
|
||||
* @addtogroup pin_mux
|
||||
* @{
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* API
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Calls initialization functions.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootPins(void);
|
||||
|
||||
/* GPIO_AD_B0_13 (coord L14), UART1_RXD */
|
||||
#define BOARD_INITPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Device name: LPUART1 */
|
||||
#define BOARD_INITPINS_UART1_RXD_SIGNAL RX /*!< LPUART1 signal: RX */
|
||||
|
||||
/* GPIO_AD_B0_12 (coord K14), UART1_TXD */
|
||||
#define BOARD_INITPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Device name: LPUART1 */
|
||||
#define BOARD_INITPINS_UART1_TXD_SIGNAL TX /*!< LPUART1 signal: TX */
|
||||
|
||||
/* GPIO_AD_B0_09 (coord F14), BSP_LED */
|
||||
#define BOARD_INITPINS_BSP_LED_GPIO GPIO1 /*!< GPIO device name: GPIO1 */
|
||||
#define BOARD_INITPINS_BSP_LED_PORT GPIO1 /*!< PORT device name: GPIO1 */
|
||||
#define BOARD_INITPINS_BSP_LED_PIN 9U /*!< GPIO1 pin index: 9 */
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitPins(void);
|
||||
void BOARD_InitI2C1Pins(void);
|
||||
void BOARD_InitSPIPins(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/
|
||||
#endif /* _PIN_MUX_H_ */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
|
|
@ -0,0 +1,250 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1052CVJ5B
|
||||
** MIMXRT1052CVL5B
|
||||
** MIMXRT1052DVJ6B
|
||||
** MIMXRT1052DVL6B
|
||||
**
|
||||
** Compiler: GNU C Compiler
|
||||
** Reference manual: IMXRT1050RM Rev.1, 03/2018
|
||||
** Version: rev. 1.0, 2018-09-21
|
||||
** Build: b180921
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the GNU C Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2018 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @file link.lds
|
||||
* @brief xidatong Linker script
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-05-28
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: link.lds
|
||||
Description: xidatong Linker script
|
||||
Others: take MIMXRT1052xxxxx_flexspi_nor.ld for references
|
||||
History:
|
||||
1. Date: 2021-05-28
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. add shell cmd table and g_service_table
|
||||
*************************************************/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
|
||||
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400
|
||||
m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00
|
||||
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
|
||||
m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00060000
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
/* The startup code goes first into internal RAM */
|
||||
.interrupts :
|
||||
{
|
||||
__VECTOR_TABLE = .;
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} > m_interrupts
|
||||
|
||||
__VECTOR_RAM = __VECTOR_TABLE;
|
||||
__RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;
|
||||
|
||||
/* The program code and other data goes into internal RAM */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(4);
|
||||
|
||||
|
||||
/* section information for shell */
|
||||
. = ALIGN(4);
|
||||
_shell_command_start = .;
|
||||
KEEP (*(shellCommand))
|
||||
_shell_command_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
__isrtbl_idx_start = .;
|
||||
KEEP(*(.isrtbl.idx))
|
||||
__isrtbl_start = .;
|
||||
KEEP(*(.isrtbl))
|
||||
__isrtbl_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
PROVIDE(g_service_table_start = ABSOLUTE(.));
|
||||
KEEP(*(.g_service_table))
|
||||
PROVIDE(g_service_table_end = ABSOLUTE(.));
|
||||
} > m_text
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > m_text
|
||||
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} > m_text
|
||||
|
||||
.ctors :
|
||||
{
|
||||
__CTOR_LIST__ = .;
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
from the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
__CTOR_END__ = .;
|
||||
} > m_text
|
||||
|
||||
.dtors :
|
||||
{
|
||||
__DTOR_LIST__ = .;
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
__DTOR_END__ = .;
|
||||
} > m_text
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} > m_text
|
||||
|
||||
__etext = .; /* define a global symbol at end of code */
|
||||
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
|
||||
|
||||
.data : AT(__DATA_ROM)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__DATA_RAM = .;
|
||||
__data_start__ = .; /* create a global symbol at data start */
|
||||
*(m_usb_dma_init_data)
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
__data_end__ = .; /* define a global symbol at data end */
|
||||
} > m_data
|
||||
|
||||
__NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);
|
||||
.ncache.init : AT(__NDATA_ROM)
|
||||
{
|
||||
__noncachedata_start__ = .; /* create a global symbol at ncache data start */
|
||||
*(NonCacheable.init)
|
||||
. = ALIGN(4);
|
||||
__noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
|
||||
} > m_data
|
||||
. = __noncachedata_init_end__;
|
||||
.ncache :
|
||||
{
|
||||
*(NonCacheable)
|
||||
. = ALIGN(4);
|
||||
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
|
||||
} > m_data
|
||||
|
||||
__DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
|
||||
text_end = ORIGIN(m_text) + LENGTH(m_text);
|
||||
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
|
||||
|
||||
/* Uninitialized data section */
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
. = ALIGN(4);
|
||||
__START_BSS = .;
|
||||
__bss_start__ = .;
|
||||
*(m_usb_dma_noninit_data)
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
__END_BSS = .;
|
||||
} > m_data
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
stack_start = .;
|
||||
. += STACK_SIZE;
|
||||
stack_end = .;
|
||||
__StackTop = .;
|
||||
heap_start = .;
|
||||
} > m_data
|
||||
|
||||
PROVIDE(heap_end = ORIGIN(m_data) + LENGTH(m_data));
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,250 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1052CVJ5B
|
||||
** MIMXRT1052CVL5B
|
||||
** MIMXRT1052DVJ6B
|
||||
** MIMXRT1052DVL6B
|
||||
**
|
||||
** Compiler: GNU C Compiler
|
||||
** Reference manual: IMXRT1050RM Rev.1, 03/2018
|
||||
** Version: rev. 1.0, 2018-09-21
|
||||
** Build: b180921
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the GNU C Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2018 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @file link.lds
|
||||
* @brief xidatong Linker script
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-05-28
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: link.lds
|
||||
Description: xidatong Linker script
|
||||
Others: take MIMXRT1052xxxxx_flexspi_nor.ld for references
|
||||
History:
|
||||
1. Date: 2021-05-28
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. add shell cmd table and g_service_table
|
||||
*************************************************/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
|
||||
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400
|
||||
m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00
|
||||
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
|
||||
m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00060000
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
/* The startup code goes first into internal RAM */
|
||||
.interrupts :
|
||||
{
|
||||
__VECTOR_TABLE = .;
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} > m_interrupts
|
||||
|
||||
__VECTOR_RAM = __VECTOR_TABLE;
|
||||
__RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;
|
||||
|
||||
/* The program code and other data goes into internal RAM */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(4);
|
||||
|
||||
|
||||
/* section information for shell */
|
||||
. = ALIGN(4);
|
||||
_shell_command_start = .;
|
||||
KEEP (*(shellCommand))
|
||||
_shell_command_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
__isrtbl_idx_start = .;
|
||||
KEEP(*(.isrtbl.idx))
|
||||
__isrtbl_start = .;
|
||||
KEEP(*(.isrtbl))
|
||||
__isrtbl_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
PROVIDE(g_service_table_start = ABSOLUTE(.));
|
||||
KEEP(*(.g_service_table))
|
||||
PROVIDE(g_service_table_end = ABSOLUTE(.));
|
||||
} > m_text
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > m_text
|
||||
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} > m_text
|
||||
|
||||
.ctors :
|
||||
{
|
||||
__CTOR_LIST__ = .;
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
from the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
__CTOR_END__ = .;
|
||||
} > m_text
|
||||
|
||||
.dtors :
|
||||
{
|
||||
__DTOR_LIST__ = .;
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
__DTOR_END__ = .;
|
||||
} > m_text
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} > m_text
|
||||
|
||||
__etext = .; /* define a global symbol at end of code */
|
||||
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
|
||||
|
||||
.data : AT(__DATA_ROM)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__DATA_RAM = .;
|
||||
__data_start__ = .; /* create a global symbol at data start */
|
||||
*(m_usb_dma_init_data)
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
__data_end__ = .; /* define a global symbol at data end */
|
||||
} > m_data
|
||||
|
||||
__NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);
|
||||
.ncache.init : AT(__NDATA_ROM)
|
||||
{
|
||||
__noncachedata_start__ = .; /* create a global symbol at ncache data start */
|
||||
*(NonCacheable.init)
|
||||
. = ALIGN(4);
|
||||
__noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
|
||||
} > m_data
|
||||
. = __noncachedata_init_end__;
|
||||
.ncache :
|
||||
{
|
||||
*(NonCacheable)
|
||||
. = ALIGN(4);
|
||||
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
|
||||
} > m_data
|
||||
|
||||
__DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
|
||||
text_end = ORIGIN(m_text) + LENGTH(m_text);
|
||||
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
|
||||
|
||||
/* Uninitialized data section */
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
. = ALIGN(4);
|
||||
__START_BSS = .;
|
||||
__bss_start__ = .;
|
||||
*(m_usb_dma_noninit_data)
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
__END_BSS = .;
|
||||
} > m_data
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
stack_start = .;
|
||||
. += STACK_SIZE;
|
||||
stack_end = .;
|
||||
__StackTop = .;
|
||||
heap_start = .;
|
||||
} > m_data2
|
||||
|
||||
PROVIDE(heap_end = ORIGIN(m_data2) + LENGTH(m_data2));
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,266 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iccarm.h>
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,39 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.2
|
||||
* @date 19. April 2017
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,197 @@
|
|||
/******************************************************************************
|
||||
* @file mpu_armv7.h
|
||||
* @brief CMSIS MPU API for Armv7-M MPU
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
|
||||
|
||||
#define ARM_MPU_AP_NONE 0U
|
||||
#define ARM_MPU_AP_PRIV 1U
|
||||
#define ARM_MPU_AP_URO 2U
|
||||
#define ARM_MPU_AP_FULL 3U
|
||||
#define ARM_MPU_AP_PRO 5U
|
||||
#define ARM_MPU_AP_RO 6U
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
*
|
||||
* \param Region The region to be configured, number 0 to 15.
|
||||
* \param BaseAddress The base address for the region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||
(MPU_RBAR_VALID_Msk))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
(((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \
|
||||
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
||||
(((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
||||
(MPU_RASR_ENABLE_Msk))
|
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RASR = 0U;
|
||||
}
|
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
while (cnt > MPU_TYPE_RALIASES) {
|
||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||
table += MPU_TYPE_RALIASES;
|
||||
cnt -= MPU_TYPE_RALIASES;
|
||||
}
|
||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,201 @@
|
|||
Apache License
|
||||
Version 2.0, January 2004
|
||||
http://www.apache.org/licenses/
|
||||
|
||||
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
|
||||
|
||||
1. Definitions.
|
||||
|
||||
"License" shall mean the terms and conditions for use, reproduction,
|
||||
and distribution as defined by Sections 1 through 9 of this document.
|
||||
|
||||
"Licensor" shall mean the copyright owner or entity authorized by
|
||||
the copyright owner that is granting the License.
|
||||
|
||||
"Legal Entity" shall mean the union of the acting entity and all
|
||||
other entities that control, are controlled by, or are under common
|
||||
control with that entity. For the purposes of this definition,
|
||||
"control" means (i) the power, direct or indirect, to cause the
|
||||
direction or management of such entity, whether by contract or
|
||||
otherwise, or (ii) ownership of fifty percent (50%) or more of the
|
||||
outstanding shares, or (iii) beneficial ownership of such entity.
|
||||
|
||||
"You" (or "Your") shall mean an individual or Legal Entity
|
||||
exercising permissions granted by this License.
|
||||
|
||||
"Source" form shall mean the preferred form for making modifications,
|
||||
including but not limited to software source code, documentation
|
||||
source, and configuration files.
|
||||
|
||||
"Object" form shall mean any form resulting from mechanical
|
||||
transformation or translation of a Source form, including but
|
||||
not limited to compiled object code, generated documentation,
|
||||
and conversions to other media types.
|
||||
|
||||
"Work" shall mean the work of authorship, whether in Source or
|
||||
Object form, made available under the License, as indicated by a
|
||||
copyright notice that is included in or attached to the work
|
||||
(an example is provided in the Appendix below).
|
||||
|
||||
"Derivative Works" shall mean any work, whether in Source or Object
|
||||
form, that is based on (or derived from) the Work and for which the
|
||||
editorial revisions, annotations, elaborations, or other modifications
|
||||
represent, as a whole, an original work of authorship. For the purposes
|
||||
of this License, Derivative Works shall not include works that remain
|
||||
separable from, or merely link (or bind by name) to the interfaces of,
|
||||
the Work and Derivative Works thereof.
|
||||
|
||||
"Contribution" shall mean any work of authorship, including
|
||||
the original version of the Work and any modifications or additions
|
||||
to that Work or Derivative Works thereof, that is intentionally
|
||||
submitted to Licensor for inclusion in the Work by the copyright owner
|
||||
or by an individual or Legal Entity authorized to submit on behalf of
|
||||
the copyright owner. For the purposes of this definition, "submitted"
|
||||
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END OF TERMS AND CONDITIONS
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APPENDIX: How to apply the Apache License to your work.
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To apply the Apache License to your work, attach the following
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|
|
@ -0,0 +1,32 @@
|
|||
menuconfig BSP_USING_LPUART
|
||||
bool "Using UART device"
|
||||
default y
|
||||
select RESOURCES_SERIAL
|
||||
if BSP_USING_LPUART
|
||||
source "$BSP_DIR/third_party_driver/uart/Kconfig"
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_GPIO
|
||||
bool "Using GPIO device "
|
||||
default y
|
||||
select RESOURCES_PIN
|
||||
|
||||
if BSP_USING_GPIO
|
||||
source "$BSP_DIR/third_party_driver/gpio/Kconfig"
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_SDIO
|
||||
bool "Using SD card device"
|
||||
default n
|
||||
select RESOURCES_SDIO
|
||||
if BSP_USING_SDIO
|
||||
source "$BSP_DIR/third_party_driver/sdio/Kconfig"
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_USB
|
||||
bool "Using USB device"
|
||||
default n
|
||||
select RESOURCES_USB
|
||||
if BSP_USING_USB
|
||||
source "$BSP_DIR/third_party_driver/usb/Kconfig"
|
||||
endif
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
SRC_DIR := common gpio
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_LPUART),y)
|
||||
SRC_DIR += uart
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_SDIO),y)
|
||||
SRC_DIR += sdio
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_USB),y)
|
||||
SRC_DIR += usb
|
||||
endif
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
SRC_FILES := system_MIMXRT1052.c fsl_cache.c fsl_clock.c fsl_common.c pin_mux.c clock_config.c
|
||||
|
||||
ifeq ($(CONFIG_BSP_USING_SDIO),y)
|
||||
SRC_FILES += fsl_usdhc.c
|
||||
endif
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,479 @@
|
|||
/*
|
||||
* Copyright 2017-2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file clock_config.c
|
||||
* @brief support imxrt1052-board clock configure
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-05-29
|
||||
*/
|
||||
|
||||
/*
|
||||
* How to setup clock using clock driver functions:
|
||||
*
|
||||
* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
|
||||
*
|
||||
* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
|
||||
*
|
||||
* 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
|
||||
*
|
||||
* 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
|
||||
*
|
||||
* 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
|
||||
*
|
||||
*/
|
||||
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Clocks v5.0
|
||||
processor: MIMXRT1052xxxxB
|
||||
package_id: MIMXRT1052DVL6B
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 5.0.2
|
||||
board: IMXRT1050-EVKB
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
|
||||
#include "clock_config.h"
|
||||
#include "fsl_iomuxc.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/* System clock frequency. */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
void BOARD_InitBootClocks(void)
|
||||
{
|
||||
BOARD_BootClockRUN();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockRUN
|
||||
called_from_default_init: true
|
||||
outputs:
|
||||
- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
|
||||
- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
|
||||
- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
|
||||
- {id: CLK_1M.outFreq, value: 1 MHz}
|
||||
- {id: CLK_24M.outFreq, value: 24 MHz}
|
||||
- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
|
||||
- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
|
||||
- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
|
||||
- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
|
||||
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
|
||||
- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
|
||||
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 2880/11 MHz}
|
||||
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
|
||||
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
|
||||
- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
|
||||
- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5/7 MHz}
|
||||
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
|
||||
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
|
||||
- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
|
||||
- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
|
||||
- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
|
||||
- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
|
||||
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
|
||||
- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
|
||||
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
|
||||
- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
|
||||
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
|
||||
- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
|
||||
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
|
||||
- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
|
||||
- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
|
||||
settings:
|
||||
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
|
||||
- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
|
||||
- {id: CCM.FLEXSPI_PODF.scale, value: '1', locked: true}
|
||||
- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
|
||||
- {id: CCM.LCDIF_PODF.scale, value: '8', locked: true}
|
||||
- {id: CCM.LCDIF_PRED.scale, value: '7', locked: true}
|
||||
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
|
||||
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
|
||||
- {id: CCM.SEMC_PODF.scale, value: '8'}
|
||||
- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
|
||||
- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
|
||||
- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
|
||||
- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
|
||||
- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
|
||||
- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
|
||||
- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
|
||||
- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
|
||||
- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
|
||||
- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
|
||||
- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
|
||||
- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
|
||||
- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
|
||||
- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
|
||||
- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
|
||||
- {id: CCM_ANALOG.PLL4.denom, value: '50'}
|
||||
- {id: CCM_ANALOG.PLL4.div, value: '47'}
|
||||
- {id: CCM_ANALOG.PLL5.denom, value: '1'}
|
||||
- {id: CCM_ANALOG.PLL5.div, value: '40'}
|
||||
- {id: CCM_ANALOG.PLL5.num, value: '0'}
|
||||
- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
|
||||
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
|
||||
sources:
|
||||
- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
|
||||
- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
};
|
||||
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
|
||||
.numerator = 0, /* 30 bit numerator of fractional loop divider */
|
||||
.denominator = 1, /* 30 bit denominator of fractional loop divider */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
};
|
||||
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
};
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockRUN(void)
|
||||
{
|
||||
/* Init RTC OSC clock frequency. */
|
||||
CLOCK_SetRtcXtalFreq(32768U);
|
||||
/* Enable 1MHz clock output. */
|
||||
XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
|
||||
/* Use free 1MHz clock output. */
|
||||
XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
|
||||
/* Set XTAL 24MHz clock frequency. */
|
||||
CLOCK_SetXtalFreq(24000000U);
|
||||
/* Enable XTAL 24MHz clock source. */
|
||||
CLOCK_InitExternalClk(0);
|
||||
/* Enable internal RC. */
|
||||
CLOCK_InitRcOsc24M();
|
||||
/* Switch clock source to external OSC. */
|
||||
CLOCK_SwitchOsc(kCLOCK_XtalOsc);
|
||||
/* Set Oscillator ready counter value. */
|
||||
CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
|
||||
/* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
|
||||
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
|
||||
CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
|
||||
/* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
|
||||
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
|
||||
/* Waiting for DCDC_STS_DC_OK bit is asserted */
|
||||
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
|
||||
{
|
||||
}
|
||||
/* Set AHB_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
|
||||
/* Disable IPG clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Adc1);
|
||||
CLOCK_DisableClock(kCLOCK_Adc2);
|
||||
CLOCK_DisableClock(kCLOCK_Xbar1);
|
||||
CLOCK_DisableClock(kCLOCK_Xbar2);
|
||||
CLOCK_DisableClock(kCLOCK_Xbar3);
|
||||
/* Set IPG_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
|
||||
/* Set ARM_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
|
||||
/* Set PERIPH_CLK2_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
|
||||
/* Disable PERCLK clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Gpt1);
|
||||
CLOCK_DisableClock(kCLOCK_Gpt1S);
|
||||
CLOCK_DisableClock(kCLOCK_Gpt2);
|
||||
CLOCK_DisableClock(kCLOCK_Gpt2S);
|
||||
CLOCK_DisableClock(kCLOCK_Pit);
|
||||
/* Set PERCLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
|
||||
/* Disable USDHC1 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Usdhc1);
|
||||
/* Set USDHC1_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
|
||||
/* Set Usdhc1 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
|
||||
/* Disable USDHC2 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Usdhc2);
|
||||
/* Set USDHC2_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
|
||||
/* Set Usdhc2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
|
||||
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
|
||||
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
|
||||
#ifndef SKIP_SYSCLK_INIT
|
||||
/* Disable Semc clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Semc);
|
||||
/* Set SEMC_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
|
||||
/* Set Semc alt clock source. */
|
||||
CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
|
||||
/* Set Semc clock source. */
|
||||
CLOCK_SetMux(kCLOCK_SemcMux, 0);
|
||||
#endif
|
||||
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
|
||||
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
|
||||
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
|
||||
/* Disable Flexspi clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_FlexSpi);
|
||||
/* Set FLEXSPI_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0);
|
||||
/* Set Flexspi clock source. */
|
||||
CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
|
||||
#endif
|
||||
/* Disable CSI clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Csi);
|
||||
/* Set CSI_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
|
||||
/* Set Csi clock source. */
|
||||
CLOCK_SetMux(kCLOCK_CsiMux, 0);
|
||||
/* Disable LPSPI clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Lpspi1);
|
||||
CLOCK_DisableClock(kCLOCK_Lpspi2);
|
||||
CLOCK_DisableClock(kCLOCK_Lpspi3);
|
||||
CLOCK_DisableClock(kCLOCK_Lpspi4);
|
||||
/* Set LPSPI_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
|
||||
/* Set Lpspi clock source. */
|
||||
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
|
||||
/* Disable TRACE clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Trace);
|
||||
/* Set TRACE_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
|
||||
/* Set Trace clock source. */
|
||||
CLOCK_SetMux(kCLOCK_TraceMux, 2);
|
||||
/* Disable SAI1 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Sai1);
|
||||
/* Set SAI1_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
|
||||
/* Set SAI1_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
|
||||
/* Set Sai1 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
|
||||
/* Disable SAI2 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Sai2);
|
||||
/* Set SAI2_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
|
||||
/* Set SAI2_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
|
||||
/* Set Sai2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
|
||||
/* Disable SAI3 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Sai3);
|
||||
/* Set SAI3_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
|
||||
/* Set SAI3_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
|
||||
/* Set Sai3 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
|
||||
/* Disable Lpi2c clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Lpi2c1);
|
||||
CLOCK_DisableClock(kCLOCK_Lpi2c2);
|
||||
CLOCK_DisableClock(kCLOCK_Lpi2c3);
|
||||
/* Set LPI2C_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
|
||||
/* Set Lpi2c clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
|
||||
/* Disable CAN clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Can1);
|
||||
CLOCK_DisableClock(kCLOCK_Can2);
|
||||
CLOCK_DisableClock(kCLOCK_Can1S);
|
||||
CLOCK_DisableClock(kCLOCK_Can2S);
|
||||
/* Set CAN_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_CanDiv, 1);
|
||||
/* Set Can clock source. */
|
||||
CLOCK_SetMux(kCLOCK_CanMux, 2);
|
||||
/* Disable UART clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart1);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart2);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart3);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart4);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart5);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart6);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart7);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart8);
|
||||
/* Set UART_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
|
||||
/* Set Uart clock source. */
|
||||
CLOCK_SetMux(kCLOCK_UartMux, 0);
|
||||
/* Disable LCDIF clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_LcdPixel);
|
||||
/* Set LCDIF_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 6);
|
||||
/* Set LCDIF_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_LcdifDiv, 7);
|
||||
/* Set Lcdif pre clock source. */
|
||||
CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
|
||||
/* Disable SPDIF clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Spdif);
|
||||
/* Set SPDIF0_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
|
||||
/* Set SPDIF0_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
|
||||
/* Set Spdif clock source. */
|
||||
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
|
||||
/* Disable Flexio1 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Flexio1);
|
||||
/* Set FLEXIO1_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
|
||||
/* Set FLEXIO1_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
|
||||
/* Set Flexio1 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
|
||||
/* Disable Flexio2 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Flexio2);
|
||||
/* Set FLEXIO2_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
|
||||
/* Set FLEXIO2_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
|
||||
/* Set Flexio2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
|
||||
/* Set Pll3 sw clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
|
||||
/* Init ARM PLL. */
|
||||
CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
|
||||
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
|
||||
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
|
||||
#ifndef SKIP_SYSCLK_INIT
|
||||
/* Init System PLL. */
|
||||
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
|
||||
/* Init System pfd0. */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
|
||||
/* Init System pfd1. */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
|
||||
/* Init System pfd2. */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
|
||||
/* Init System pfd3. */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
|
||||
/* Disable pfd offset. */
|
||||
CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK;
|
||||
#endif
|
||||
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
|
||||
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
|
||||
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
|
||||
/* Init Usb1 PLL. */
|
||||
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
|
||||
/* Init Usb1 pfd0. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
|
||||
/* Init Usb1 pfd1. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
|
||||
/* Init Usb1 pfd2. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
|
||||
/* Init Usb1 pfd3. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
|
||||
/* Disable Usb1 PLL output for USBPHY1. */
|
||||
CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
|
||||
#endif
|
||||
/* DeInit Audio PLL. */
|
||||
CLOCK_DeinitAudioPll();
|
||||
/* Bypass Audio PLL. */
|
||||
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
|
||||
/* Set divider for Audio PLL. */
|
||||
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
|
||||
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
|
||||
/* Enable Audio PLL output. */
|
||||
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
|
||||
/* DeInit Video PLL. */
|
||||
CLOCK_DeinitVideoPll();
|
||||
/* Bypass Video PLL. */
|
||||
CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
|
||||
/* Set divider for Video PLL. */
|
||||
CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0);
|
||||
/* Enable Video PLL output. */
|
||||
CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
|
||||
/* DeInit Enet PLL. */
|
||||
CLOCK_DeinitEnetPll();
|
||||
/* Bypass Enet PLL. */
|
||||
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
|
||||
/* Set Enet output divider. */
|
||||
CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
|
||||
/* Enable Enet output. */
|
||||
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
|
||||
/* Enable Enet25M output. */
|
||||
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
|
||||
/* DeInit Usb2 PLL. */
|
||||
CLOCK_DeinitUsb2Pll();
|
||||
/* Bypass Usb2 PLL. */
|
||||
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
|
||||
/* Enable Usb2 PLL output. */
|
||||
CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
|
||||
/* Set preperiph clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
|
||||
/* Set periph clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
|
||||
/* Set periph clock2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
|
||||
/* Set per clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
|
||||
/* Set lvds1 clock source. */
|
||||
CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
|
||||
/* Set clock out1 divider. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
|
||||
/* Set clock out1 source. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
|
||||
/* Set clock out2 divider. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
|
||||
/* Set clock out2 source. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
|
||||
/* Set clock out1 drives clock out1. */
|
||||
CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
|
||||
/* Disable clock out1. */
|
||||
CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
|
||||
/* Disable clock out2. */
|
||||
CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
|
||||
/* Set SAI1 MCLK1 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
|
||||
/* Set SAI1 MCLK2 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
|
||||
/* Set SAI1 MCLK3 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
|
||||
/* Set SAI2 MCLK3 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
|
||||
/* Set SAI3 MCLK3 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
|
||||
/* Set MQS configuration. */
|
||||
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
|
||||
/* Set ENET Tx clock source. */
|
||||
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
|
||||
/* Set GPT1 High frequency reference clock source. */
|
||||
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
|
||||
/* Set GPT2 High frequency reference clock source. */
|
||||
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,611 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file fsl_cache.c
|
||||
* @brief cache drivers
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021.11.11
|
||||
*/
|
||||
|
||||
#include "fsl_cache.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.cache_armv7_m7"
|
||||
#endif
|
||||
|
||||
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
|
||||
#define L2CACHE_OPERATION_TIMEOUT 0xFFFFFU
|
||||
#define L2CACHE_8WAYS_MASK 0xFFU
|
||||
#define L2CACHE_16WAYS_MASK 0xFFFFU
|
||||
#define L2CACHE_SMALLWAYS_NUM 8U
|
||||
#define L2CACHE_1KBCOVERTOB 1024U
|
||||
#define L2CACHE_SAMLLWAYS_SIZE 16U
|
||||
#define L2CACHE_LOCKDOWN_REGNUM 8 /*!< Lock down register numbers.*/
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief Set for all ways and waiting for the operation finished.
|
||||
* This is provided for all the background operations.
|
||||
*
|
||||
* @param auxCtlReg The auxiliary control register.
|
||||
* @param regAddr The register address to be operated.
|
||||
*/
|
||||
static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t regAddr);
|
||||
|
||||
/*!
|
||||
* @brief Invalidates the Level 2 cache line by physical address.
|
||||
* This function invalidates a cache line by physcial address.
|
||||
*
|
||||
* @param address The physical addderss of the cache.
|
||||
* The format of the address shall be :
|
||||
* bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0
|
||||
* Tag | index | 0
|
||||
* Note: the physical address shall be aligned to the line size - 32B (256 bit).
|
||||
* so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero.
|
||||
* If the input address is not aligned, it will be changed to 32-byte aligned address.
|
||||
* The n is varies according to the index width.
|
||||
* @return The actual 32-byte aligned physical address be operated.
|
||||
*/
|
||||
static uint32_t L2CACHE_InvalidateLineByAddr(uint32_t address);
|
||||
|
||||
/*!
|
||||
* @brief Cleans the Level 2 cache line based on the physical address.
|
||||
* This function cleans a cache line based on a physcial address.
|
||||
*
|
||||
* @param address The physical addderss of the cache.
|
||||
* The format of the address shall be :
|
||||
* bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0
|
||||
* Tag | index | 0
|
||||
* Note: the physical address shall be aligned to the line size - 32B (256 bit).
|
||||
* so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero.
|
||||
* If the input address is not aligned, it will be changed to 32-byte aligned address.
|
||||
* The n is varies according to the index width.
|
||||
* @return The actual 32-byte aligned physical address be operated.
|
||||
*/
|
||||
static uint32_t L2CACHE_CleanLineByAddr(uint32_t address);
|
||||
|
||||
/*!
|
||||
* @brief Cleans and invalidates the Level 2 cache line based on the physical address.
|
||||
* This function cleans and invalidates a cache line based on a physcial address.
|
||||
*
|
||||
* @param address The physical addderss of the cache.
|
||||
* The format of the address shall be :
|
||||
* bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0
|
||||
* Tag | index | 0
|
||||
* Note: the physical address shall be aligned to the line size - 32B (256 bit).
|
||||
* so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero.
|
||||
* If the input address is not aligned, it will be changed to 32-byte aligned address.
|
||||
* The n is varies according to the index width.
|
||||
* @return The actual 32-byte aligned physical address be operated.
|
||||
*/
|
||||
static uint32_t L2CACHE_CleanInvalidateLineByAddr(uint32_t address);
|
||||
|
||||
/*!
|
||||
* @brief Gets the number of the Level 2 cache and the way size.
|
||||
* This function cleans and invalidates a cache line based on a physcial address.
|
||||
*
|
||||
* @param num_ways The number of the cache way.
|
||||
* @param size_way The way size.
|
||||
*/
|
||||
static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way);
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t regAddr)
|
||||
{
|
||||
uint16_t mask = L2CACHE_8WAYS_MASK;
|
||||
uint32_t timeout = L2CACHE_OPERATION_TIMEOUT;
|
||||
|
||||
/* Check the ways used at first. */
|
||||
if (auxCtlReg & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK)
|
||||
{
|
||||
mask = L2CACHE_16WAYS_MASK;
|
||||
}
|
||||
|
||||
/* Set the opeartion for all ways/entries of the cache. */
|
||||
*(uint32_t *)regAddr = mask;
|
||||
/* Waiting for until the operation is complete. */
|
||||
while ((*(volatile uint32_t *)regAddr & mask) && timeout)
|
||||
{
|
||||
__ASM("nop");
|
||||
timeout--;
|
||||
}
|
||||
}
|
||||
|
||||
static uint32_t L2CACHE_InvalidateLineByAddr(uint32_t address)
|
||||
{
|
||||
/* Align the address first. */
|
||||
address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1);
|
||||
/* Invalidate the cache line by physical address. */
|
||||
L2CACHEC->REG7_INV_PA = address;
|
||||
|
||||
return address;
|
||||
}
|
||||
|
||||
static uint32_t L2CACHE_CleanLineByAddr(uint32_t address)
|
||||
{
|
||||
/* Align the address first. */
|
||||
address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1);
|
||||
/* Invalidate the cache line by physical address. */
|
||||
L2CACHEC->REG7_CLEAN_PA = address;
|
||||
|
||||
return address;
|
||||
}
|
||||
|
||||
static uint32_t L2CACHE_CleanInvalidateLineByAddr(uint32_t address)
|
||||
{
|
||||
/* Align the address first. */
|
||||
address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1);
|
||||
/* Clean and invalidate the cache line by physical address. */
|
||||
L2CACHEC->REG7_CLEAN_INV_PA = address;
|
||||
|
||||
return address;
|
||||
}
|
||||
|
||||
static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way)
|
||||
{
|
||||
assert(num_ways);
|
||||
assert(size_way);
|
||||
|
||||
uint32_t number = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
|
||||
L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT;
|
||||
uint32_t size = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_MASK) >>
|
||||
L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_SHIFT;
|
||||
|
||||
*num_ways = (number + 1) * L2CACHE_SMALLWAYS_NUM;
|
||||
if (!size)
|
||||
{
|
||||
/* 0 internally mapped to the same size as 1 - 16KB.*/
|
||||
size += 1;
|
||||
}
|
||||
*size_way = (1 << (size - 1)) * L2CACHE_SAMLLWAYS_SIZE * L2CACHE_1KBCOVERTOB;
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Initializes the level 2 cache controller module.
|
||||
*
|
||||
* param config Pointer to configuration structure. See "l2cache_config_t".
|
||||
*/
|
||||
void L2CACHE_Init(l2cache_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
|
||||
uint16_t waysNum = 0xFFU; /* Default use the 8-way mask. */
|
||||
uint8_t count;
|
||||
uint32_t auxReg = 0;
|
||||
|
||||
/*The aux register must be configured when the cachec is disabled
|
||||
* So disable first if the cache controller is enabled.
|
||||
*/
|
||||
if (L2CACHEC->REG1_CONTROL & L2CACHEC_REG1_CONTROL_CE_MASK)
|
||||
{
|
||||
L2CACHE_Disable();
|
||||
}
|
||||
|
||||
/* Unlock all entries. */
|
||||
if (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK)
|
||||
{
|
||||
waysNum = 0xFFFFU;
|
||||
}
|
||||
|
||||
for (count = 0; count < L2CACHE_LOCKDOWN_REGNUM; count++)
|
||||
{
|
||||
L2CACHE_LockdownByWayEnable(count, waysNum, false);
|
||||
}
|
||||
|
||||
/* Set the ways and way-size etc. */
|
||||
auxReg = L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY(config->wayNum) |
|
||||
L2CACHEC_REG1_AUX_CONTROL_WAYSIZE(config->waySize) | L2CACHEC_REG1_AUX_CONTROL_CRP(config->repacePolicy) |
|
||||
L2CACHEC_REG1_AUX_CONTROL_IPE(config->istrPrefetchEnable) |
|
||||
L2CACHEC_REG1_AUX_CONTROL_DPE(config->dataPrefetchEnable) |
|
||||
L2CACHEC_REG1_AUX_CONTROL_NLE(config->nsLockdownEnable) |
|
||||
L2CACHEC_REG1_AUX_CONTROL_FWA(config->writeAlloc) | L2CACHEC_REG1_AUX_CONTROL_HPSDRE(config->writeAlloc);
|
||||
L2CACHEC->REG1_AUX_CONTROL = auxReg;
|
||||
|
||||
/* Set the tag/data ram latency. */
|
||||
if (config->lateConfig)
|
||||
{
|
||||
uint32_t data = 0;
|
||||
/* Tag latency. */
|
||||
data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) |
|
||||
L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) |
|
||||
L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate) |
|
||||
L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
|
||||
L2CACHEC->REG1_TAG_RAM_CONTROL = data;
|
||||
/* Data latency. */
|
||||
data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) |
|
||||
L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) |
|
||||
L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate) |
|
||||
L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
|
||||
L2CACHEC->REG1_DATA_RAM_CONTROL = data;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Gets an available default settings for the cache controller.
|
||||
*
|
||||
* This function initializes the cache controller configuration structure with default settings.
|
||||
* The default values are:
|
||||
* code
|
||||
* config->waysNum = kL2CACHE_8ways;
|
||||
* config->waySize = kL2CACHE_32KbSize;
|
||||
* config->repacePolicy = kL2CACHE_Roundrobin;
|
||||
* config->lateConfig = NULL;
|
||||
* config->istrPrefetchEnable = false;
|
||||
* config->dataPrefetchEnable = false;
|
||||
* config->nsLockdownEnable = false;
|
||||
* config->writeAlloc = kL2CACHE_UseAwcache;
|
||||
* endcode
|
||||
* param config Pointer to the configuration structure.
|
||||
*/
|
||||
void L2CACHE_GetDefaultConfig(l2cache_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
|
||||
/* Initializes the configure structure to zero. */
|
||||
memset(config, 0, sizeof(*config));
|
||||
|
||||
uint32_t number = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
|
||||
L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT;
|
||||
uint32_t size = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_MASK) >>
|
||||
L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_SHIFT;
|
||||
|
||||
/* Get the default value */
|
||||
config->wayNum = (l2cache_way_num_t)number;
|
||||
config->waySize = (l2cache_way_size)size;
|
||||
config->repacePolicy = kL2CACHE_Roundrobin;
|
||||
config->lateConfig = NULL;
|
||||
config->istrPrefetchEnable = false;
|
||||
config->dataPrefetchEnable = false;
|
||||
config->nsLockdownEnable = false;
|
||||
config->writeAlloc = kL2CACHE_UseAwcache;
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Enables the level 2 cache controller.
|
||||
* This function enables the cache controller. Must be written using a secure access.
|
||||
* If write with a Non-secure access will cause a DECERR response.
|
||||
*
|
||||
*/
|
||||
void L2CACHE_Enable(void)
|
||||
{
|
||||
/* Invalidate first. */
|
||||
L2CACHE_Invalidate();
|
||||
/* Enable the level 2 cache controller. */
|
||||
L2CACHEC->REG1_CONTROL = L2CACHEC_REG1_CONTROL_CE_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Disables the level 2 cache controller.
|
||||
* This function disables the cache controller. Must be written using a secure access.
|
||||
* If write with a Non-secure access will cause a DECERR response.
|
||||
*
|
||||
*/
|
||||
void L2CACHE_Disable(void)
|
||||
{
|
||||
/* First CleanInvalidate all enties in the cache. */
|
||||
L2CACHE_CleanInvalidate();
|
||||
/* Disable the level 2 cache controller. */
|
||||
L2CACHEC->REG1_CONTROL &= ~L2CACHEC_REG1_CONTROL_CE_MASK;
|
||||
/* DSB - data sync barrier.*/
|
||||
__DSB();
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Invalidates the Level 2 cache.
|
||||
* This function invalidates all entries in cache.
|
||||
*
|
||||
*/
|
||||
void L2CACHE_Invalidate(void)
|
||||
{
|
||||
/* Invalidate all entries in cache. */
|
||||
L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_INV_WAY);
|
||||
/* Cache sync. */
|
||||
L2CACHEC->REG7_CACHE_SYNC = 0;
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Cleans the level 2 cache controller.
|
||||
* This function cleans all entries in the level 2 cache controller.
|
||||
*
|
||||
*/
|
||||
void L2CACHE_Clean(void)
|
||||
{
|
||||
/* Clean all entries of the cache. */
|
||||
L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_CLEAN_WAY);
|
||||
/* Cache sync. */
|
||||
L2CACHEC->REG7_CACHE_SYNC = 0;
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Cleans and invalidates the level 2 cache controller.
|
||||
* This function cleans and invalidates all entries in the level 2 cache controller.
|
||||
*
|
||||
*/
|
||||
void L2CACHE_CleanInvalidate(void)
|
||||
{
|
||||
/* Clean all entries of the cache. */
|
||||
L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_CLEAN_INV_WAY);
|
||||
/* Cache sync. */
|
||||
L2CACHEC->REG7_CACHE_SYNC = 0;
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Invalidates the Level 2 cache lines in the range of two physical addresses.
|
||||
* This function invalidates all cache lines between two physical addresses.
|
||||
*
|
||||
* param address The start address of the memory to be invalidated.
|
||||
* param size_byte The memory size.
|
||||
* note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
|
||||
* The startAddr here will be forced to align to L2 line size if startAddr
|
||||
* is not aligned. For the size_byte, application should make sure the
|
||||
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
|
||||
{
|
||||
uint32_t endAddr = address + size_byte;
|
||||
|
||||
/* Invalidate addresses in the range. */
|
||||
while (address < endAddr)
|
||||
{
|
||||
address = L2CACHE_InvalidateLineByAddr(address);
|
||||
/* Update the size. */
|
||||
address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE;
|
||||
}
|
||||
|
||||
/* Cache sync. */
|
||||
L2CACHEC->REG7_CACHE_SYNC = 0;
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Cleans the Level 2 cache lines in the range of two physical addresses.
|
||||
* This function cleans all cache lines between two physical addresses.
|
||||
*
|
||||
* param address The start address of the memory to be cleaned.
|
||||
* param size_byte The memory size.
|
||||
* note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
|
||||
* The startAddr here will be forced to align to L2 line size if startAddr
|
||||
* is not aligned. For the size_byte, application should make sure the
|
||||
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte)
|
||||
{
|
||||
uint32_t num_ways = 0;
|
||||
uint32_t size_way = 0;
|
||||
uint32_t endAddr = address + size_byte;
|
||||
|
||||
/* Get the number and size of the cache way. */
|
||||
L2CACHE_GetWayNumSize(&num_ways, &size_way);
|
||||
|
||||
/* Check if the clean size is over the cache size. */
|
||||
if ((endAddr - address) > num_ways * size_way)
|
||||
{
|
||||
L2CACHE_Clean();
|
||||
return;
|
||||
}
|
||||
|
||||
/* Clean addresses in the range. */
|
||||
while ((address & ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1)) < endAddr)
|
||||
{
|
||||
/* Clean the address in the range. */
|
||||
address = L2CACHE_CleanLineByAddr(address);
|
||||
address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE;
|
||||
}
|
||||
|
||||
L2CACHEC->REG7_CACHE_SYNC = 0;
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Cleans and invalidates the Level 2 cache lines in the range of two physical addresses.
|
||||
* This function cleans and invalidates all cache lines between two physical addresses.
|
||||
*
|
||||
* param address The start address of the memory to be cleaned and invalidated.
|
||||
* param size_byte The memory size.
|
||||
* note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
|
||||
* The startAddr here will be forced to align to L2 line size if startAddr
|
||||
* is not aligned. For the size_byte, application should make sure the
|
||||
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
|
||||
{
|
||||
uint32_t num_ways = 0;
|
||||
uint32_t size_way = 0;
|
||||
uint32_t endAddr = address + size_byte;
|
||||
|
||||
/* Get the number and size of the cache way. */
|
||||
L2CACHE_GetWayNumSize(&num_ways, &size_way);
|
||||
|
||||
/* Check if the clean size is over the cache size. */
|
||||
if ((endAddr - address) > num_ways * size_way)
|
||||
{
|
||||
L2CACHE_CleanInvalidate();
|
||||
return;
|
||||
}
|
||||
|
||||
/* Clean addresses in the range. */
|
||||
while ((address & ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1)) < endAddr)
|
||||
{
|
||||
/* Clean the address in the range. */
|
||||
address = L2CACHE_CleanInvalidateLineByAddr(address);
|
||||
address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE;
|
||||
}
|
||||
|
||||
L2CACHEC->REG7_CACHE_SYNC = 0;
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Enables or disables to lock down the data and instruction by way.
|
||||
* This function locks down the cached instruction/data by way and prevent the adresses from
|
||||
* being allocated and prevent dara from being evicted out of the level 2 cache.
|
||||
* But the normal cache maintenance operations that invalidate, clean or clean
|
||||
* and validate cache contents affect the locked-down cache lines as normal.
|
||||
*
|
||||
* param masterId The master id, range from 0 ~ 7.
|
||||
* param mask The ways to be enabled or disabled to lockdown.
|
||||
* each bit in value is related to each way of the cache. for example:
|
||||
* value: bit 0 ------ way 0.
|
||||
* value: bit 1 ------ way 1.
|
||||
* --------------------------
|
||||
* value: bit 15 ------ way 15.
|
||||
* Note: please make sure the value setting is align with your supported ways.
|
||||
* param enable True enable the lockdown, false to disable the lockdown.
|
||||
*/
|
||||
void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable)
|
||||
{
|
||||
uint8_t num_ways = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
|
||||
L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT;
|
||||
num_ways = (num_ways + 1) * L2CACHE_SMALLWAYS_NUM;
|
||||
|
||||
assert(mask < (1U << num_ways));
|
||||
assert(masterId < L2CACHE_LOCKDOWN_REGNUM);
|
||||
|
||||
uint32_t dataReg = L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN;
|
||||
uint32_t istrReg = L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN;
|
||||
|
||||
if (enable)
|
||||
{
|
||||
/* Data lockdown. */
|
||||
L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg | mask;
|
||||
/* Instruction lockdown. */
|
||||
L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg | mask;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Data lockdown. */
|
||||
L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg & ~mask;
|
||||
/* Instruction lockdown. */
|
||||
L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask;
|
||||
}
|
||||
}
|
||||
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
|
||||
|
||||
/*!
|
||||
* brief Invalidate cortex-m7 L1 instruction cache by range.
|
||||
*
|
||||
* param address The start address of the memory to be invalidated.
|
||||
* param size_byte The memory size.
|
||||
* note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.
|
||||
* The startAddr here will be forced to align to L1 I-cache line size if
|
||||
* startAddr is not aligned. For the size_byte, application should make sure the
|
||||
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
|
||||
{
|
||||
#if (__DCACHE_PRESENT == 1U)
|
||||
uint32_t addr = address & (uint32_t) ~(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE - 1);
|
||||
int32_t size = size_byte + address - addr;
|
||||
uint32_t linesize = 32U;
|
||||
|
||||
__DSB();
|
||||
while (size > 0)
|
||||
{
|
||||
SCB->ICIMVAU = addr;
|
||||
addr += linesize;
|
||||
size -= linesize;
|
||||
}
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Invalidates all instruction caches by range.
|
||||
*
|
||||
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
||||
*
|
||||
* param address The physical address.
|
||||
* param size_byte size of the memory to be invalidated.
|
||||
* note address and size should be aligned to cache line size
|
||||
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
||||
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
||||
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
|
||||
{
|
||||
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
|
||||
#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
|
||||
L2CACHE_InvalidateByRange(address, size_byte);
|
||||
#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
|
||||
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
|
||||
|
||||
L1CACHE_InvalidateICacheByRange(address, size_byte);
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Invalidates all data caches by range.
|
||||
*
|
||||
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
||||
*
|
||||
* param address The physical address.
|
||||
* param size_byte size of the memory to be invalidated.
|
||||
* note address and size should be aligned to cache line size
|
||||
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
||||
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
||||
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
|
||||
{
|
||||
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
|
||||
#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
|
||||
L2CACHE_InvalidateByRange(address, size_byte);
|
||||
#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
|
||||
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
|
||||
L1CACHE_InvalidateDCacheByRange(address, size_byte);
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Cleans all data caches by range.
|
||||
*
|
||||
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
||||
*
|
||||
* param address The physical address.
|
||||
* param size_byte size of the memory to be cleaned.
|
||||
* note address and size should be aligned to cache line size
|
||||
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
||||
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
||||
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
|
||||
{
|
||||
L1CACHE_CleanDCacheByRange(address, size_byte);
|
||||
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
|
||||
#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
|
||||
L2CACHE_CleanByRange(address, size_byte);
|
||||
#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
|
||||
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Cleans and Invalidates all data caches by range.
|
||||
*
|
||||
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
||||
*
|
||||
* param address The physical address.
|
||||
* param size_byte size of the memory to be cleaned and invalidated.
|
||||
* note address and size should be aligned to cache line size
|
||||
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
||||
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
||||
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
|
||||
{
|
||||
L1CACHE_CleanInvalidateDCacheByRange(address, size_byte);
|
||||
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
|
||||
#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
|
||||
L2CACHE_CleanInvalidateByRange(address, size_byte);
|
||||
#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
|
||||
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,155 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file fsl_common.c
|
||||
* @brief common drivers
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021.11.11
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
#define SDK_MEM_MAGIC_NUMBER 12345U
|
||||
|
||||
typedef struct _mem_align_control_block
|
||||
{
|
||||
uint16_t identifier; /*!< Identifier for the memory control block. */
|
||||
uint16_t offset; /*!< offset from aligned address to real address */
|
||||
} mem_align_cb_t;
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.common"
|
||||
#endif
|
||||
|
||||
#ifndef __GIC_PRIO_BITS
|
||||
#if defined(ENABLE_RAM_VECTOR_TABLE)
|
||||
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
|
||||
{
|
||||
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
|
||||
extern uint32_t Image$$VECTOR_ROM$$Base[];
|
||||
extern uint32_t Image$$VECTOR_RAM$$Base[];
|
||||
extern uint32_t Image$$RW_m_data$$Base[];
|
||||
|
||||
#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
|
||||
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
|
||||
#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
|
||||
#elif defined(__ICCARM__)
|
||||
extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
|
||||
extern uint32_t __VECTOR_TABLE[];
|
||||
extern uint32_t __VECTOR_RAM[];
|
||||
#elif defined(__GNUC__)
|
||||
extern uint32_t __VECTOR_TABLE[];
|
||||
extern uint32_t __VECTOR_RAM[];
|
||||
extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
|
||||
uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
|
||||
#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */
|
||||
uint32_t n;
|
||||
uint32_t ret;
|
||||
uint32_t irqMaskValue;
|
||||
|
||||
irqMaskValue = DisableGlobalIRQ();
|
||||
if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
|
||||
{
|
||||
/* Copy the vector table from ROM to RAM */
|
||||
for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
|
||||
{
|
||||
__VECTOR_RAM[n] = __VECTOR_TABLE[n];
|
||||
}
|
||||
/* Point the VTOR to the position of vector table */
|
||||
SCB->VTOR = (uint32_t)__VECTOR_RAM;
|
||||
}
|
||||
|
||||
ret = __VECTOR_RAM[irq + 16];
|
||||
/* make sure the __VECTOR_RAM is noncachable */
|
||||
__VECTOR_RAM[irq + 16] = irqHandler;
|
||||
|
||||
EnableGlobalIRQ(irqMaskValue);
|
||||
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif /* ENABLE_RAM_VECTOR_TABLE. */
|
||||
#endif /* __GIC_PRIO_BITS. */
|
||||
|
||||
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
|
||||
#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)
|
||||
|
||||
void EnableDeepSleepIRQ(IRQn_Type interrupt)
|
||||
{
|
||||
uint32_t intNumber = (uint32_t)interrupt;
|
||||
|
||||
uint32_t index = 0;
|
||||
|
||||
while (intNumber >= 32u)
|
||||
{
|
||||
index++;
|
||||
intNumber -= 32u;
|
||||
}
|
||||
|
||||
SYSCON->STARTERSET[index] = 1u << intNumber;
|
||||
EnableIRQ(interrupt); /* also enable interrupt at NVIC */
|
||||
}
|
||||
|
||||
void DisableDeepSleepIRQ(IRQn_Type interrupt)
|
||||
{
|
||||
uint32_t intNumber = (uint32_t)interrupt;
|
||||
|
||||
DisableIRQ(interrupt); /* also disable interrupt at NVIC */
|
||||
uint32_t index = 0;
|
||||
|
||||
while (intNumber >= 32u)
|
||||
{
|
||||
index++;
|
||||
intNumber -= 32u;
|
||||
}
|
||||
|
||||
SYSCON->STARTERCLR[index] = 1u << intNumber;
|
||||
}
|
||||
#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */
|
||||
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
|
||||
|
||||
void *SDK_Malloc(size_t size, size_t alignbytes)
|
||||
{
|
||||
mem_align_cb_t *p_cb = NULL;
|
||||
uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t);
|
||||
void *p_align_addr, *p_addr = malloc(alignedsize);
|
||||
|
||||
if (!p_addr)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
p_align_addr = (void *)SDK_SIZEALIGN((uint32_t)p_addr + sizeof(mem_align_cb_t), alignbytes);
|
||||
|
||||
p_cb = (mem_align_cb_t *)((uint32_t)p_align_addr - 4);
|
||||
p_cb->identifier = SDK_MEM_MAGIC_NUMBER;
|
||||
p_cb->offset = (uint32_t)p_align_addr - (uint32_t)p_addr;
|
||||
|
||||
return (void *)p_align_addr;
|
||||
}
|
||||
|
||||
void SDK_Free(void *ptr)
|
||||
{
|
||||
mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4);
|
||||
|
||||
if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
free((void *)((uint32_t)ptr - p_cb->offset));
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,236 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1052CVJ5B
|
||||
** MIMXRT1052CVL5B
|
||||
** MIMXRT1052DVJ6B
|
||||
** MIMXRT1052DVL6B
|
||||
**
|
||||
** Compilers: Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
** Keil ARM C/C++ Compiler
|
||||
** MCUXpresso Compiler
|
||||
**
|
||||
** Reference manual: IMXRT1050RM Rev.2.1, 12/2018
|
||||
** Version: rev. 1.2, 2018-11-27
|
||||
** Build: b181205
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that
|
||||
** contains the system frequency. It configures the device and initializes
|
||||
** the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2018 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 0.1 (2017-01-10)
|
||||
** Initial version.
|
||||
** - rev. 1.0 (2018-09-21)
|
||||
** Update interrupt vector table and dma request source.
|
||||
** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
|
||||
** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
|
||||
** - rev. 1.1 (2018-11-16)
|
||||
** Update header files to align with IMXRT1050RM Rev.1.
|
||||
** - rev. 1.2 (2018-11-27)
|
||||
** Update header files to align with IMXRT1050RM Rev.2.1.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file MIMXRT1052
|
||||
* @version 1.2
|
||||
* @date 2018-11-27
|
||||
* @brief Device specific configuration file for MIMXRT1052 (implementation file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "fsl_device_registers.h"
|
||||
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- Core clock
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemInit()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
void SystemInit (void) {
|
||||
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
|
||||
SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
|
||||
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
|
||||
|
||||
#if defined(__MCUXPRESSO)
|
||||
extern uint32_t g_pfnVectors[]; // Vector table defined in startup code
|
||||
SCB->VTOR = (uint32_t)g_pfnVectors;
|
||||
#endif
|
||||
|
||||
/* Disable Watchdog Power Down Counter */
|
||||
WDOG1->WMCR &= ~WDOG_WMCR_PDE_MASK;
|
||||
WDOG2->WMCR &= ~WDOG_WMCR_PDE_MASK;
|
||||
|
||||
/* Watchdog disable */
|
||||
|
||||
#if (DISABLE_WDOG)
|
||||
if (WDOG1->WCR & WDOG_WCR_WDE_MASK)
|
||||
{
|
||||
WDOG1->WCR &= ~WDOG_WCR_WDE_MASK;
|
||||
}
|
||||
if (WDOG2->WCR & WDOG_WCR_WDE_MASK)
|
||||
{
|
||||
WDOG2->WCR &= ~WDOG_WCR_WDE_MASK;
|
||||
}
|
||||
RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
|
||||
RTWDOG->TOVAL = 0xFFFF;
|
||||
RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
|
||||
#endif /* (DISABLE_WDOG) */
|
||||
|
||||
/* Disable Systick which might be enabled by bootrom */
|
||||
if (SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)
|
||||
{
|
||||
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/* Enable instruction and data caches */
|
||||
#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
|
||||
if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) {
|
||||
SCB_EnableICache();
|
||||
}
|
||||
#endif
|
||||
#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
|
||||
if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) {
|
||||
SCB_EnableDCache();
|
||||
}
|
||||
#endif
|
||||
|
||||
SystemInitHook();
|
||||
}
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemCoreClockUpdate()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
void SystemCoreClockUpdate (void) {
|
||||
|
||||
uint32_t freq;
|
||||
uint32_t PLL1MainClock;
|
||||
uint32_t PLL2MainClock;
|
||||
|
||||
/* Periph_clk2_clk ---> Periph_clk */
|
||||
if (CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK)
|
||||
{
|
||||
switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
|
||||
{
|
||||
/* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */
|
||||
case CCM_CBCMR_PERIPH_CLK2_SEL(0U):
|
||||
if(CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK)
|
||||
{
|
||||
freq = (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) == 0U) ?
|
||||
CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
|
||||
}
|
||||
else
|
||||
{
|
||||
freq = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U));
|
||||
}
|
||||
break;
|
||||
|
||||
/* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */
|
||||
case CCM_CBCMR_PERIPH_CLK2_SEL(1U):
|
||||
freq = CPU_XTAL_CLK_HZ;
|
||||
break;
|
||||
|
||||
case CCM_CBCMR_PERIPH_CLK2_SEL(2U):
|
||||
freq = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ?
|
||||
CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
|
||||
break;
|
||||
|
||||
case CCM_CBCMR_PERIPH_CLK2_SEL(3U):
|
||||
default:
|
||||
freq = 0U;
|
||||
break;
|
||||
}
|
||||
|
||||
freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U);
|
||||
}
|
||||
/* Pre_Periph_clk ---> Periph_clk */
|
||||
else
|
||||
{
|
||||
/* check if pll is bypassed */
|
||||
if(CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
|
||||
{
|
||||
PLL1MainClock = (((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) == 0U) ?
|
||||
CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
|
||||
}
|
||||
else
|
||||
{
|
||||
PLL1MainClock = ((CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
|
||||
CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U);
|
||||
}
|
||||
|
||||
/* check if pll is bypassed */
|
||||
if(CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK)
|
||||
{
|
||||
PLL2MainClock = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ?
|
||||
CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
|
||||
}
|
||||
else
|
||||
{
|
||||
PLL2MainClock = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) ? 22U : 20U));
|
||||
}
|
||||
PLL2MainClock += ((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM));
|
||||
|
||||
|
||||
switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
|
||||
{
|
||||
/* PLL2 ---> Pre_Periph_clk ---> Periph_clk */
|
||||
case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U):
|
||||
freq = PLL2MainClock;
|
||||
break;
|
||||
|
||||
/* PLL2 PFD2 ---> Pre_Periph_clk ---> Periph_clk */
|
||||
case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U):
|
||||
freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT) * 18U;
|
||||
break;
|
||||
|
||||
/* PLL2 PFD0 ---> Pre_Periph_clk ---> Periph_clk */
|
||||
case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U):
|
||||
freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) * 18U;
|
||||
break;
|
||||
|
||||
/* PLL1 divided(/2) ---> Pre_Periph_clk ---> Periph_clk */
|
||||
case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U):
|
||||
freq = PLL1MainClock / (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U);
|
||||
break;
|
||||
|
||||
default:
|
||||
freq = 0U;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U));
|
||||
|
||||
}
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemInitHook()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
__attribute__ ((weak)) void SystemInitHook (void) {
|
||||
/* Void implementation of the weak function. */
|
||||
}
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
|
||||
config PIN_BUS_NAME
|
||||
string "pin bus name"
|
||||
default "pin"
|
||||
|
||||
config PIN_DRIVER_NAME
|
||||
string "pin driver name"
|
||||
default "pin_drv"
|
||||
|
||||
config PIN_DEVICE_NAME
|
||||
string "pin device name"
|
||||
default "pin_dev"
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
SRC_FILES := connect_gpio.c fsl_gpio.c
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,544 @@
|
|||
/*
|
||||
* Copyright (c) 2020 RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-06 balanceTWK first version
|
||||
* 2019-04-23 WillianChan Fix GPIO serial number disorder
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file connect_gpio.c
|
||||
* @brief support gpio function using bus driver framework
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-04-25
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: connect_gpio.c
|
||||
Description: support gpio configure and register to bus framework
|
||||
Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_gpio.c for references
|
||||
https://github.com/RT-Thread/rt-thread/tree/v4.0.2
|
||||
History:
|
||||
1. Date: 2021-04-25
|
||||
Author: AIIT XUOS Lab
|
||||
Modification: add bus driver framework support for gpio
|
||||
*************************************************/
|
||||
|
||||
#include <device.h>
|
||||
#include <board.h>
|
||||
|
||||
#define STM32_PIN_NUMBERS 100 // [48, 64, 100, 144]
|
||||
|
||||
#define ITEM_NUM(items) sizeof(items)/sizeof(items[0])
|
||||
|
||||
struct PinIndex
|
||||
{
|
||||
int index;
|
||||
GPIO_Type *gpio;
|
||||
uint32_t pin;
|
||||
};
|
||||
|
||||
struct PinIrq
|
||||
{
|
||||
uint8 port_source;
|
||||
uint8 pin_source;
|
||||
enum IRQn irq_exti_channel;
|
||||
uint32 exti_line;
|
||||
};
|
||||
|
||||
static const struct PinIndex pins[] = {
|
||||
{0, GPIO1, 0},
|
||||
{1, GPIO1, 1},
|
||||
{2, GPIO1, 2},
|
||||
{3, GPIO1, 3},
|
||||
{4, GPIO1, 4},
|
||||
{5, GPIO1, 5},
|
||||
{6, GPIO1, 6},
|
||||
{7, GPIO1, 7},
|
||||
{8, GPIO1, 8},
|
||||
{9, GPIO1, 9},
|
||||
{10, GPIO1, 10},
|
||||
{11, GPIO1, 11},
|
||||
{12, GPIO1, 12},
|
||||
{13, GPIO1, 13},
|
||||
{14, GPIO1, 14},
|
||||
{15, GPIO1, 15},
|
||||
{16, GPIO2, 0},
|
||||
{17, GPIO2, 1},
|
||||
{18, GPIO2, 2},
|
||||
{19, GPIO2, 3},
|
||||
{20, GPIO2, 4},
|
||||
{21, GPIO2, 5},
|
||||
{22, GPIO2, 6},
|
||||
{23, GPIO2, 7},
|
||||
{24, GPIO2, 8},
|
||||
{25, GPIO2, 9},
|
||||
{26, GPIO2, 10},
|
||||
{27, GPIO2, 11},
|
||||
{28, GPIO2, 12},
|
||||
{29, GPIO2, 13},
|
||||
{30, GPIO2, 14},
|
||||
{31, GPIO2, 15},
|
||||
{32, GPIO3, 0},
|
||||
{33, GPIO3, 1},
|
||||
{34, GPIO3, 2},
|
||||
{35, GPIO3, 3},
|
||||
{36, GPIO3, 4},
|
||||
{37, GPIO3, 5},
|
||||
{38, GPIO3, 6},
|
||||
{39, GPIO3, 7},
|
||||
{40, GPIO3, 8},
|
||||
{41, GPIO3, 9},
|
||||
{42, GPIO3, 10},
|
||||
{43, GPIO3, 11},
|
||||
{44, GPIO3, 12},
|
||||
{45, GPIO3, 13},
|
||||
{46, GPIO3, 14},
|
||||
{47, GPIO3, 15},
|
||||
{-1, 0u, -1}
|
||||
};
|
||||
|
||||
struct PinIrqHdr pin_irq_hdr_tab[] = {};
|
||||
|
||||
const struct PinIndex *GetPin(uint8_t pin)
|
||||
{
|
||||
const struct PinIndex *index;
|
||||
|
||||
if (pin < ITEM_NUM(pins)){
|
||||
index = &pins[pin];
|
||||
if (index->index == -1)
|
||||
index = NONE;
|
||||
}
|
||||
else{
|
||||
index = NONE;
|
||||
}
|
||||
|
||||
return index;
|
||||
}
|
||||
|
||||
static int32 GpioConfigMode(int mode, const struct PinIndex* index)
|
||||
{
|
||||
gpio_pin_config_t gpio_config;
|
||||
NULL_PARAM_CHECK(index);
|
||||
|
||||
switch (mode)
|
||||
{
|
||||
case GPIO_CFG_OUTPUT:
|
||||
gpio_config.direction = kGPIO_DigitalOutput;
|
||||
gpio_config.interruptMode = kGPIO_NoIntmode;
|
||||
break;
|
||||
case GPIO_CFG_INPUT:
|
||||
gpio_config.direction = kGPIO_DigitalInput;
|
||||
gpio_config.interruptMode = kGPIO_NoIntmode;
|
||||
break;
|
||||
case GPIO_CFG_INPUT_PULLUP:
|
||||
gpio_config.direction = kGPIO_DigitalInput;
|
||||
gpio_config.interruptMode = kGPIO_IntRisingEdge;
|
||||
break;
|
||||
case GPIO_CFG_INPUT_PULLDOWN:
|
||||
gpio_config.direction = kGPIO_DigitalInput;
|
||||
gpio_config.interruptMode = kGPIO_IntFallingEdge;
|
||||
break;
|
||||
case GPIO_CFG_OUTPUT_OD:
|
||||
gpio_config.direction = kGPIO_DigitalOutput;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
GPIO_PinInit(index->gpio, index->pin, &gpio_config);
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static __inline int32 Bit2Bitnum(uint32 bit)
|
||||
{
|
||||
for (int i = 0; i < 32; i++){
|
||||
if ((1UL << i) == bit){
|
||||
return i;
|
||||
}
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
static __inline int32 Bitno2Bit(uint32 bitno)
|
||||
{
|
||||
if (bitno <= 32) {
|
||||
return 1UL << bitno;
|
||||
}
|
||||
else {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
static const struct PinIrq *GetPinIrq(uint16_t pin)
|
||||
{
|
||||
static struct PinIrq irq;
|
||||
const struct PinIndex* index = GetPin(pin);
|
||||
|
||||
if (index == NONE) {
|
||||
return NONE;
|
||||
}
|
||||
|
||||
irq.exti_line = index->pin;
|
||||
irq.pin_source = Bit2Bitnum(index->pin);
|
||||
irq.port_source = ((uint32_t)index->gpio - GPIO1_BASE) / (GPIO2_BASE - GPIO1_BASE);
|
||||
switch (irq.pin_source)
|
||||
{
|
||||
case 0 :
|
||||
irq.irq_exti_channel = GPIO1_INT0_IRQn;
|
||||
break;
|
||||
case 1 :
|
||||
irq.irq_exti_channel = GPIO1_INT1_IRQn;
|
||||
break;
|
||||
case 2 :
|
||||
irq.irq_exti_channel = GPIO1_INT2_IRQn;
|
||||
break;
|
||||
case 3 :
|
||||
irq.irq_exti_channel = GPIO1_INT3_IRQn;
|
||||
break;
|
||||
case 4 :
|
||||
irq.irq_exti_channel = GPIO1_INT4_IRQn;
|
||||
break;
|
||||
case 5 :
|
||||
irq.irq_exti_channel = GPIO1_INT5_IRQn;
|
||||
break;
|
||||
case 6 :
|
||||
irq.irq_exti_channel = GPIO1_INT6_IRQn;
|
||||
break;
|
||||
case 7 :
|
||||
irq.irq_exti_channel = GPIO1_INT7_IRQn;
|
||||
break;
|
||||
default :
|
||||
return NONE;
|
||||
}
|
||||
|
||||
return &irq;
|
||||
};
|
||||
static int32 GpioIrqRegister(int32 pin, int32 mode, void (*hdr)(void *args), void *args)
|
||||
{
|
||||
const struct PinIndex* index = GetPin(pin);
|
||||
int32 irqindex = -1;
|
||||
|
||||
irqindex = Bit2Bitnum(index->pin);
|
||||
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)) {
|
||||
return -ENONESYS;
|
||||
}
|
||||
|
||||
x_base level = CriticalAreaLock();
|
||||
if (pin_irq_hdr_tab[irqindex].pin == pin &&
|
||||
pin_irq_hdr_tab[irqindex].hdr == hdr &&
|
||||
pin_irq_hdr_tab[irqindex].mode == mode &&
|
||||
pin_irq_hdr_tab[irqindex].args == args
|
||||
)
|
||||
{
|
||||
CriticalAreaUnLock(level);
|
||||
return EOK;
|
||||
}
|
||||
if (pin_irq_hdr_tab[irqindex].pin != -1) {
|
||||
CriticalAreaUnLock(level);
|
||||
return -EDEV_BUSY;
|
||||
}
|
||||
pin_irq_hdr_tab[irqindex].pin = pin;
|
||||
pin_irq_hdr_tab[irqindex].hdr = hdr;
|
||||
pin_irq_hdr_tab[irqindex].mode = mode;
|
||||
pin_irq_hdr_tab[irqindex].args = args;
|
||||
CriticalAreaUnLock(level);
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static uint32 GpioIrqFree(int32 pin)
|
||||
{
|
||||
const struct PinIndex* index = GetPin(pin);
|
||||
int32 irqindex = -1;
|
||||
|
||||
irqindex = Bit2Bitnum(index->pin);
|
||||
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)) {
|
||||
return -ENONESYS;
|
||||
}
|
||||
|
||||
x_base level = CriticalAreaLock();
|
||||
if (pin_irq_hdr_tab[irqindex].pin == -1){
|
||||
CriticalAreaUnLock(level);
|
||||
return EOK;
|
||||
}
|
||||
pin_irq_hdr_tab[irqindex].pin = -1;
|
||||
pin_irq_hdr_tab[irqindex].hdr = NONE;
|
||||
pin_irq_hdr_tab[irqindex].mode = 0;
|
||||
pin_irq_hdr_tab[irqindex].args = NONE;
|
||||
CriticalAreaUnLock(level);
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static int32 GpioIrqEnable(x_base pin)
|
||||
{
|
||||
const struct PinIndex* index = GetPin(pin);
|
||||
int32 irqindex = -1;
|
||||
const struct PinIrq *irq;
|
||||
gpio_pin_config_t gpio_config;
|
||||
|
||||
irqindex = Bit2Bitnum(index->pin);
|
||||
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)){
|
||||
return -ENONESYS;
|
||||
}
|
||||
x_base level = CriticalAreaLock();
|
||||
if (pin_irq_hdr_tab[irqindex].pin == -1) {
|
||||
CriticalAreaUnLock(level);
|
||||
return -ENONESYS;
|
||||
}
|
||||
|
||||
irq = GetPinIrq(pin);
|
||||
if (irq == NONE){
|
||||
CriticalAreaUnLock(level);
|
||||
return -ENONESYS;
|
||||
}
|
||||
|
||||
switch (pin_irq_hdr_tab[irqindex].mode)
|
||||
{
|
||||
case GPIO_IRQ_EDGE_RISING:
|
||||
gpio_config.direction = kGPIO_DigitalInput;
|
||||
gpio_config.interruptMode = kGPIO_IntRisingEdge;
|
||||
break;
|
||||
case GPIO_IRQ_EDGE_FALLING:
|
||||
gpio_config.direction = kGPIO_DigitalInput;
|
||||
gpio_config.interruptMode = kGPIO_IntFallingEdge;
|
||||
break;
|
||||
case GPIO_IRQ_EDGE_BOTH:
|
||||
gpio_config.direction = kGPIO_DigitalInput;
|
||||
gpio_config.interruptMode = kGPIO_IntRisingOrFallingEdge;
|
||||
break;
|
||||
}
|
||||
|
||||
GPIO_PinInit(index->gpio, index->pin, &gpio_config);
|
||||
GPIO_PortEnableInterrupts(index->gpio, index->pin);
|
||||
CriticalAreaUnLock(level);
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static int32 GpioIrqDisable(x_base pin)
|
||||
{
|
||||
const struct PinIndex* index = GetPin(pin);
|
||||
const struct PinIrq *irq;
|
||||
|
||||
irq = GetPinIrq(index->pin);
|
||||
NULL_PARAM_CHECK(irq);
|
||||
|
||||
GPIO_PortDisableInterrupts(index->gpio, index->pin);
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static uint32 Stm32PinConfigure(struct PinParam *param)
|
||||
{
|
||||
NULL_PARAM_CHECK(param);
|
||||
int ret = EOK;
|
||||
|
||||
const struct PinIndex *index = GetPin(param->pin);
|
||||
switch(param->cmd)
|
||||
{
|
||||
case GPIO_CONFIG_MODE:
|
||||
GpioConfigMode(param->mode, index);
|
||||
break;
|
||||
case GPIO_IRQ_REGISTER:
|
||||
ret = GpioIrqRegister(param->pin,param->irq_set.irq_mode,param->irq_set.hdr,param->irq_set.args);
|
||||
break;
|
||||
case GPIO_IRQ_FREE:
|
||||
ret = GpioIrqFree(param->pin);
|
||||
break;
|
||||
case GPIO_IRQ_ENABLE:
|
||||
ret = GpioIrqEnable(param->pin);
|
||||
break;
|
||||
case GPIO_IRQ_DISABLE:
|
||||
ret = GpioIrqDisable(param->pin);
|
||||
break;
|
||||
default:
|
||||
ret = -EINVALED;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static uint32 Stm32PinInit(void)
|
||||
{
|
||||
static x_bool pin_init_flag = RET_FALSE;
|
||||
|
||||
if (!pin_init_flag) {
|
||||
pin_init_flag = RET_TRUE;
|
||||
}
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static uint32 Stm32GpioDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
|
||||
{
|
||||
NULL_PARAM_CHECK(drv);
|
||||
NULL_PARAM_CHECK(configure_info);
|
||||
|
||||
x_err_t ret = EOK;
|
||||
struct PinParam *param;
|
||||
|
||||
switch (configure_info->configure_cmd)
|
||||
{
|
||||
case OPE_INT:
|
||||
ret = Stm32PinInit();
|
||||
break;
|
||||
case OPE_CFG:
|
||||
param = (struct PinParam *)configure_info->private_data;
|
||||
ret = Stm32PinConfigure(param);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
uint32 Stm32PinWrite(void *dev, struct BusBlockWriteParam *write_param)
|
||||
{
|
||||
NULL_PARAM_CHECK(dev);
|
||||
NULL_PARAM_CHECK(write_param);
|
||||
struct PinStat *pinstat = (struct PinStat *)write_param->buffer;
|
||||
const struct PinIndex* index = GetPin(pinstat->pin);
|
||||
NULL_PARAM_CHECK(index);
|
||||
|
||||
if (GPIO_LOW == pinstat->val) {
|
||||
GPIO_PinWrite(index->gpio, index->pin, 0);
|
||||
} else {
|
||||
GPIO_PinWrite(index->gpio, index->pin, 1);
|
||||
}
|
||||
return EOK;
|
||||
}
|
||||
|
||||
uint32 Stm32PinRead(void *dev, struct BusBlockReadParam *read_param)
|
||||
{
|
||||
NULL_PARAM_CHECK(dev);
|
||||
NULL_PARAM_CHECK(read_param);
|
||||
struct PinStat *pinstat = (struct PinStat *)read_param->buffer;
|
||||
const struct PinIndex* index = GetPin(pinstat->pin);
|
||||
NULL_PARAM_CHECK(index);
|
||||
|
||||
if(GPIO_PinRead(index->gpio, index->pin) == GPIO_LOW) {
|
||||
pinstat->val = GPIO_LOW;
|
||||
} else {
|
||||
pinstat->val = GPIO_HIGH;
|
||||
}
|
||||
return pinstat->val;
|
||||
}
|
||||
|
||||
static const struct PinDevDone dev_done =
|
||||
{
|
||||
.open = NONE,
|
||||
.close = NONE,
|
||||
.write = Stm32PinWrite,
|
||||
.read = Stm32PinRead,
|
||||
};
|
||||
|
||||
int Stm32HwGpioInit(void)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
|
||||
static struct PinBus pin;
|
||||
|
||||
ret = PinBusInit(&pin, PIN_BUS_NAME);
|
||||
if (ret != EOK) {
|
||||
KPrintf("gpio bus init error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
static struct PinDriver drv;
|
||||
drv.configure = &Stm32GpioDrvConfigure;
|
||||
|
||||
ret = PinDriverInit(&drv, PIN_DRIVER_NAME, NONE);
|
||||
if (ret != EOK) {
|
||||
KPrintf("pin driver init error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
ret = PinDriverAttachToBus(PIN_DRIVER_NAME, PIN_BUS_NAME);
|
||||
if (ret != EOK) {
|
||||
KPrintf("pin driver attach error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
static struct PinHardwareDevice dev;
|
||||
dev.dev_done = &dev_done;
|
||||
|
||||
ret = PinDeviceRegister(&dev, NONE, PIN_DEVICE_NAME);
|
||||
if (ret != EOK) {
|
||||
KPrintf("pin device register error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
ret = PinDeviceAttachToBus(PIN_DEVICE_NAME, PIN_BUS_NAME);
|
||||
if (ret != EOK) {
|
||||
KPrintf("pin device register error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static __inline void PinIrqHdr(int irqno)
|
||||
{
|
||||
const struct PinIndex* index = GetPin(irqno);
|
||||
const struct PinIrq *irq;
|
||||
|
||||
irq = GetPinIrq(index->pin);
|
||||
NULL_PARAM_CHECK(irq);
|
||||
|
||||
GPIO_ClearPinsInterruptFlags(index->gpio, index->pin);
|
||||
|
||||
if (pin_irq_hdr_tab[irqno].hdr){
|
||||
pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
|
||||
}
|
||||
}
|
||||
|
||||
void EXTI0_IRQHandler(int irq_num, void *arg)
|
||||
{
|
||||
PinIrqHdr(0);
|
||||
}
|
||||
DECLARE_HW_IRQ(GPIO1_INT0_IRQn, EXTI0_IRQHandler, NONE);
|
||||
|
||||
void EXTI1_IRQHandler(int irq_num, void *arg)
|
||||
{
|
||||
PinIrqHdr(1);
|
||||
}
|
||||
DECLARE_HW_IRQ(GPIO1_INT1_IRQn, EXTI1_IRQHandler, NONE);
|
||||
|
||||
void EXTI2_IRQHandler(int irq_num, void *arg)
|
||||
{
|
||||
PinIrqHdr(2);
|
||||
}
|
||||
DECLARE_HW_IRQ(GPIO1_INT2_IRQn, EXTI2_IRQHandler, NONE);
|
||||
|
||||
void EXTI3_IRQHandler(int irq_num, void *arg)
|
||||
{
|
||||
PinIrqHdr(3);
|
||||
}
|
||||
DECLARE_HW_IRQ(GPIO1_INT3_IRQn, EXTI3_IRQHandler, NONE);
|
||||
|
||||
void EXTI4_IRQHandler(int irq_num, void *arg)
|
||||
{
|
||||
PinIrqHdr(4);
|
||||
}
|
||||
DECLARE_HW_IRQ(GPIO1_INT4_IRQn, EXTI4_IRQHandler, NONE);
|
||||
|
||||
void EXTI5_IRQHandler(int irq_num, void *arg)
|
||||
{
|
||||
PinIrqHdr(5);
|
||||
}
|
||||
DECLARE_HW_IRQ(GPIO1_INT5_IRQn, EXTI5_IRQHandler, NONE);
|
||||
|
||||
void EXTI6_IRQHandler(int irq_num, void *arg)
|
||||
{
|
||||
PinIrqHdr(6);
|
||||
}
|
||||
DECLARE_HW_IRQ(GPIO1_INT6_IRQn, EXTI6_IRQHandler, NONE);
|
||||
|
||||
void EXTI7_IRQHandler(int irq_num, void *arg)
|
||||
{
|
||||
PinIrqHdr(7);
|
||||
}
|
||||
DECLARE_HW_IRQ(GPIO1_INT7_IRQn, EXTI7_IRQHandler, NONE);
|
||||
|
||||
|
|
@ -0,0 +1,171 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "fsl_gpio.h"
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.igpio"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
/* Array of GPIO peripheral base address. */
|
||||
static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Array of GPIO clock name. */
|
||||
static const clock_ip_name_t s_gpioClock[] = GPIO_CLOCKS;
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief Gets the GPIO instance according to the GPIO base
|
||||
*
|
||||
* @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.)
|
||||
* @retval GPIO instance
|
||||
*/
|
||||
static uint32_t GPIO_GetInstance(GPIO_Type *base);
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
static uint32_t GPIO_GetInstance(GPIO_Type *base)
|
||||
{
|
||||
uint32_t instance;
|
||||
|
||||
/* Find the instance index from base address mappings. */
|
||||
for (instance = 0; instance < ARRAY_SIZE(s_gpioBases); instance++)
|
||||
{
|
||||
if (s_gpioBases[instance] == base)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
assert(instance < ARRAY_SIZE(s_gpioBases));
|
||||
|
||||
return instance;
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Initializes the GPIO peripheral according to the specified
|
||||
* parameters in the initConfig.
|
||||
*
|
||||
* param base GPIO base pointer.
|
||||
* param pin Specifies the pin number
|
||||
* param initConfig pointer to a ref gpio_pin_config_t structure that
|
||||
* contains the configuration information.
|
||||
*/
|
||||
void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config)
|
||||
{
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Enable GPIO clock. */
|
||||
uint32_t instance = GPIO_GetInstance(base);
|
||||
|
||||
/* If The clock IP is valid, enable the clock gate. */
|
||||
if ((instance < ARRAY_SIZE(s_gpioClock)) && (kCLOCK_IpInvalid != s_gpioClock[instance]))
|
||||
{
|
||||
CLOCK_EnableClock(s_gpioClock[instance]);
|
||||
}
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/* Register reset to default value */
|
||||
base->IMR &= ~(1U << pin);
|
||||
|
||||
/* Configure GPIO pin direction */
|
||||
if (Config->direction == kGPIO_DigitalInput)
|
||||
{
|
||||
base->GDIR &= ~(1U << pin);
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIO_PinWrite(base, pin, Config->outputLogic);
|
||||
base->GDIR |= (1U << pin);
|
||||
}
|
||||
|
||||
/* Configure GPIO pin interrupt mode */
|
||||
GPIO_SetPinInterruptConfig(base, pin, Config->interruptMode);
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Sets the output level of the individual GPIO pin to logic 1 or 0.
|
||||
*
|
||||
* param base GPIO base pointer.
|
||||
* param pin GPIO port pin number.
|
||||
* param output GPIOpin output logic level.
|
||||
* - 0: corresponding pin output low-logic level.
|
||||
* - 1: corresponding pin output high-logic level.
|
||||
*/
|
||||
void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output)
|
||||
{
|
||||
assert(pin < 32);
|
||||
if (output == 0U)
|
||||
{
|
||||
base->DR &= ~(1U << pin); /* Set pin output to low level.*/
|
||||
}
|
||||
else
|
||||
{
|
||||
base->DR |= (1U << pin); /* Set pin output to high level.*/
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* brief Sets the current pin interrupt mode.
|
||||
*
|
||||
* param base GPIO base pointer.
|
||||
* param pin GPIO port pin number.
|
||||
* param pininterruptMode pointer to a ref gpio_interrupt_mode_t structure
|
||||
* that contains the interrupt mode information.
|
||||
*/
|
||||
void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode)
|
||||
{
|
||||
volatile uint32_t *icr;
|
||||
uint32_t icrShift;
|
||||
|
||||
icrShift = pin;
|
||||
|
||||
/* Register reset to default value */
|
||||
base->EDGE_SEL &= ~(1U << pin);
|
||||
|
||||
if (pin < 16)
|
||||
{
|
||||
icr = &(base->ICR1);
|
||||
}
|
||||
else
|
||||
{
|
||||
icr = &(base->ICR2);
|
||||
icrShift -= 16;
|
||||
}
|
||||
switch (pinInterruptMode)
|
||||
{
|
||||
case (kGPIO_IntLowLevel):
|
||||
*icr &= ~(3U << (2 * icrShift));
|
||||
break;
|
||||
case (kGPIO_IntHighLevel):
|
||||
*icr = (*icr & (~(3U << (2 * icrShift)))) | (1U << (2 * icrShift));
|
||||
break;
|
||||
case (kGPIO_IntRisingEdge):
|
||||
*icr = (*icr & (~(3U << (2 * icrShift)))) | (2U << (2 * icrShift));
|
||||
break;
|
||||
case (kGPIO_IntFallingEdge):
|
||||
*icr |= (3U << (2 * icrShift));
|
||||
break;
|
||||
case (kGPIO_IntRisingOrFallingEdge):
|
||||
base->EDGE_SEL |= (1U << pin);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,627 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Version: rev. 1.1, 2018-11-16
|
||||
** Build: b181120
|
||||
**
|
||||
** Abstract:
|
||||
** Chip specific module features.
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2018 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 0.1 (2017-01-10)
|
||||
** Initial version.
|
||||
** - rev. 1.0 (2018-09-21)
|
||||
** Update interrupt vector table and dma request source.
|
||||
** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
|
||||
** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
|
||||
** - rev. 1.1 (2018-11-16)
|
||||
** Update feature files to align with IMXRT1050RM Rev.1.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#ifndef _MIMXRT1052_FEATURES_H_
|
||||
#define _MIMXRT1052_FEATURES_H_
|
||||
|
||||
/* SOC module features */
|
||||
|
||||
/* @brief ADC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ADC_COUNT (2)
|
||||
/* @brief AIPSTZ availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_AIPSTZ_COUNT (4)
|
||||
/* @brief AOI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_AOI_COUNT (2)
|
||||
/* @brief CCM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CCM_COUNT (1)
|
||||
/* @brief CCM_ANALOG availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)
|
||||
/* @brief CMP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CMP_COUNT (4)
|
||||
/* @brief CSI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CSI_COUNT (1)
|
||||
/* @brief DCDC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DCDC_COUNT (1)
|
||||
/* @brief DCP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DCP_COUNT (1)
|
||||
/* @brief DMAMUX availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
|
||||
/* @brief EDMA availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_EDMA_COUNT (1)
|
||||
/* @brief ENC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ENC_COUNT (4)
|
||||
/* @brief ENET availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ENET_COUNT (1)
|
||||
/* @brief EWM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_EWM_COUNT (1)
|
||||
/* @brief FLEXCAN availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FLEXCAN_COUNT (2)
|
||||
/* @brief FLEXIO availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FLEXIO_COUNT (2)
|
||||
/* @brief FLEXRAM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FLEXRAM_COUNT (1)
|
||||
/* @brief FLEXSPI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1)
|
||||
/* @brief GPC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_GPC_COUNT (1)
|
||||
/* @brief GPT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_GPT_COUNT (2)
|
||||
/* @brief I2S availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_I2S_COUNT (3)
|
||||
/* @brief IGPIO availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IGPIO_COUNT (5)
|
||||
/* @brief IOMUXC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IOMUXC_COUNT (1)
|
||||
/* @brief IOMUXC_GPR availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1)
|
||||
/* @brief IOMUXC_SNVS availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (1)
|
||||
/* @brief KPP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_KPP_COUNT (1)
|
||||
/* @brief LCDIF availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LCDIF_COUNT (1)
|
||||
/* @brief LPI2C availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPI2C_COUNT (4)
|
||||
/* @brief LPSPI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPSPI_COUNT (4)
|
||||
/* @brief LPUART availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPUART_COUNT (8)
|
||||
/* @brief OCOTP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_OCOTP_COUNT (1)
|
||||
/* @brief PIT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PIT_COUNT (1)
|
||||
/* @brief PMU availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PMU_COUNT (1)
|
||||
/* @brief PWM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PWM_COUNT (4)
|
||||
/* @brief PXP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PXP_COUNT (1)
|
||||
/* @brief ROMC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ROMC_COUNT (1)
|
||||
/* @brief SEMC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SEMC_COUNT (1)
|
||||
/* @brief SNVS availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SNVS_COUNT (1)
|
||||
/* @brief SPDIF availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SPDIF_COUNT (1)
|
||||
/* @brief SRC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SRC_COUNT (1)
|
||||
/* @brief TEMPMON availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_TEMPMON_COUNT (1)
|
||||
/* @brief TMR availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_TMR_COUNT (4)
|
||||
/* @brief TRNG availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_TRNG_COUNT (1)
|
||||
/* @brief TSC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_TSC_COUNT (1)
|
||||
/* @brief USBHS availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USBHS_COUNT (2)
|
||||
/* @brief USBNC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USBNC_COUNT (2)
|
||||
/* @brief USBPHY availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USBPHY_COUNT (2)
|
||||
/* @brief USDHC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USDHC_COUNT (2)
|
||||
/* @brief WDOG availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_WDOG_COUNT (2)
|
||||
/* @brief XBARA availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_XBARA_COUNT (1)
|
||||
/* @brief XBARB availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_XBARB_COUNT (2)
|
||||
/* @brief XTALOSC24M availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_XTALOSC24M_COUNT (1)
|
||||
|
||||
/* ADC module features */
|
||||
|
||||
/* @brief Remove Hardware Trigger feature. */
|
||||
#define FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE (0)
|
||||
/* @brief Remove ALT Clock selection feature. */
|
||||
#define FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE (1)
|
||||
/* @brief Conversion control count (related to number of registers HCn and Rn). */
|
||||
#define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (8)
|
||||
|
||||
/* ADC_ETC module features */
|
||||
|
||||
/* @brief Has DMA model control(bit field CTRL[DMA_MODE_SEL]). */
|
||||
#define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1)
|
||||
|
||||
/* AOI module features */
|
||||
|
||||
/* @brief Maximum value of input mux. */
|
||||
#define FSL_FEATURE_AOI_MODULE_INPUTS (4)
|
||||
/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */
|
||||
#define FSL_FEATURE_AOI_EVENT_COUNT (4)
|
||||
|
||||
/* FLEXCAN module features */
|
||||
|
||||
/* @brief Message buffer size */
|
||||
#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (64)
|
||||
/* @brief Has doze mode support (register bit field MCR[DOZE]). */
|
||||
#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
|
||||
/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */
|
||||
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0)
|
||||
/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
|
||||
#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
|
||||
/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
|
||||
#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1)
|
||||
/* @brief Instance has extended bit timing register (register CBT). */
|
||||
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (0)
|
||||
/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
|
||||
#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0)
|
||||
/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */
|
||||
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (0)
|
||||
/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */
|
||||
#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1)
|
||||
/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */
|
||||
#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1)
|
||||
/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
|
||||
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
|
||||
/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */
|
||||
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (1)
|
||||
/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */
|
||||
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (1)
|
||||
/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */
|
||||
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (1)
|
||||
/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */
|
||||
#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (0)
|
||||
/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */
|
||||
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (0)
|
||||
/* @brief Has extra MB interrupt or common one. */
|
||||
#define FSL_FEATURE_FLEXCAN_HAS_EXTRA_MB_INT (1)
|
||||
|
||||
/* CMP module features */
|
||||
|
||||
/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
|
||||
#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0)
|
||||
/* @brief Has Window mode in CMP (register bit field CR1[WE]). */
|
||||
#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1)
|
||||
/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
|
||||
#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1)
|
||||
/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
|
||||
#define FSL_FEATURE_CMP_HAS_DMA (1)
|
||||
/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
|
||||
#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0)
|
||||
/* @brief Has DAC Test function in CMP (register DACTEST). */
|
||||
#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
|
||||
|
||||
/* EDMA module features */
|
||||
|
||||
/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
|
||||
#define FSL_FEATURE_EDMA_MODULE_CHANNEL (32)
|
||||
/* @brief Total number of DMA channels on all modules. */
|
||||
#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (32)
|
||||
/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
|
||||
#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
|
||||
/* @brief Has DMA_Error interrupt vector. */
|
||||
#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
|
||||
/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
|
||||
#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32)
|
||||
|
||||
/* DMAMUX module features */
|
||||
|
||||
/* @brief Number of DMA channels (related to number of register CHCFGn). */
|
||||
#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32)
|
||||
/* @brief Total number of DMA channels on all modules. */
|
||||
#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 32)
|
||||
/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
|
||||
#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
|
||||
/* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */
|
||||
#define FSL_FEATURE_DMAMUX_HAS_A_ON (1)
|
||||
|
||||
/* ENET module features */
|
||||
|
||||
/* @brief Support Interrupt Coalesce */
|
||||
#define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (1)
|
||||
/* @brief Queue Size. */
|
||||
#define FSL_FEATURE_ENET_QUEUE (1)
|
||||
/* @brief Has AVB Support. */
|
||||
#define FSL_FEATURE_ENET_HAS_AVB (0)
|
||||
/* @brief Has Timer Pulse Width control. */
|
||||
#define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (1)
|
||||
/* @brief Has Extend MDIO Support. */
|
||||
#define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1)
|
||||
/* @brief Has Additional 1588 Timer Channel Interrupt. */
|
||||
#define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0)
|
||||
|
||||
/* EWM module features */
|
||||
|
||||
/* @brief Has clock select (register CLKCTRL). */
|
||||
#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1)
|
||||
/* @brief Has clock prescaler (register CLKPRESCALER). */
|
||||
#define FSL_FEATURE_EWM_HAS_PRESCALER (1)
|
||||
|
||||
/* FLEXIO module features */
|
||||
|
||||
/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */
|
||||
#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1)
|
||||
/* @brief Has Pin Data Input Register (FLEXIO_PIN) */
|
||||
#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1)
|
||||
/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */
|
||||
#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1)
|
||||
/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */
|
||||
#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1)
|
||||
/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */
|
||||
#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1)
|
||||
/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */
|
||||
#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1)
|
||||
/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */
|
||||
#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1)
|
||||
/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */
|
||||
#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1)
|
||||
/* @brief Reset value of the FLEXIO_VERID register */
|
||||
#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001)
|
||||
/* @brief Reset value of the FLEXIO_PARAM register */
|
||||
#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x2200404)
|
||||
|
||||
/* FLEXRAM module features */
|
||||
|
||||
/* @brief Bank size */
|
||||
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32768)
|
||||
/* @brief Total Bank numbers */
|
||||
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16)
|
||||
|
||||
/* FLEXSPI module features */
|
||||
|
||||
/* @brief FlexSPI AHB buffer count */
|
||||
#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (4)
|
||||
/* @brief FlexSPI has no data learn. */
|
||||
#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (1)
|
||||
|
||||
/* GPC module features */
|
||||
|
||||
/* @brief Has DVFS0 Change Request. */
|
||||
#define FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR (0)
|
||||
/* @brief Has GPC interrupt/event masking. */
|
||||
#define FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM (0)
|
||||
/* @brief Has L2 cache power control. */
|
||||
#define FSL_FEATURE_GPC_HAS_CNTR_L2PGE (0)
|
||||
/* @brief Has FLEXRAM PDRAM0(bank1-7) power control. */
|
||||
#define FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE (1)
|
||||
/* @brief Has VADC power control. */
|
||||
#define FSL_FEATURE_GPC_HAS_CNTR_VADC (0)
|
||||
/* @brief Has Display power control. */
|
||||
#define FSL_FEATURE_GPC_HAS_CNTR_DISPLAY (0)
|
||||
/* @brief Supports IRQ 0-31. */
|
||||
#define FSL_FEATURE_GPC_HAS_IRQ_0_31 (1)
|
||||
|
||||
/* IGPIO module features */
|
||||
|
||||
/* @brief Has data register set DR_SET. */
|
||||
#define FSL_FEATURE_IGPIO_HAS_DR_SET (1)
|
||||
/* @brief Has data register clear DR_CLEAR. */
|
||||
#define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (1)
|
||||
/* @brief Has data register toggle DR_TOGGLE. */
|
||||
#define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (1)
|
||||
|
||||
/* LCDIF module features */
|
||||
|
||||
/* @brief LCDIF does not support alpha support. */
|
||||
#define FSL_FEATURE_LCDIF_HAS_NO_AS (1)
|
||||
/* @brief LCDIF does not support output reset pin to LCD panel. */
|
||||
#define FSL_FEATURE_LCDIF_HAS_NO_RESET_PIN (1)
|
||||
/* @brief LCDIF supports LUT. */
|
||||
#define FSL_FEATURE_LCDIF_HAS_LUT (1)
|
||||
|
||||
/* LPI2C module features */
|
||||
|
||||
/* @brief Has separate DMA RX and TX requests. */
|
||||
#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0)
|
||||
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||
#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4)
|
||||
|
||||
/* LPSPI module features */
|
||||
|
||||
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||
#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (16)
|
||||
/* @brief Has separate DMA RX and TX requests. */
|
||||
#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
|
||||
|
||||
/* LPUART module features */
|
||||
|
||||
/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
|
||||
#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
|
||||
/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
|
||||
/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
|
||||
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||
#define FSL_FEATURE_LPUART_HAS_FIFO (1)
|
||||
/* @brief Has 32-bit register MODIR */
|
||||
#define FSL_FEATURE_LPUART_HAS_MODIR (1)
|
||||
/* @brief Hardware flow control (RTS, CTS) is supported. */
|
||||
#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
|
||||
/* @brief Infrared (modulation) is supported. */
|
||||
#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
|
||||
/* @brief 2 bits long stop bit is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
|
||||
/* @brief If 10-bit mode is supported. */
|
||||
#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
|
||||
/* @brief If 7-bit mode is supported. */
|
||||
#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1)
|
||||
/* @brief Baud rate fine adjustment is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
|
||||
/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
|
||||
/* @brief Baud rate oversampling is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
|
||||
/* @brief Baud rate oversampling is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
|
||||
/* @brief Peripheral type. */
|
||||
#define FSL_FEATURE_LPUART_IS_SCI (1)
|
||||
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||
#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4)
|
||||
/* @brief Maximal data width without parity bit. */
|
||||
#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
|
||||
/* @brief Maximal data width with parity bit. */
|
||||
#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9)
|
||||
/* @brief Supports two match addresses to filter incoming frames. */
|
||||
#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
|
||||
/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
|
||||
/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
|
||||
#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
|
||||
/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
|
||||
/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
|
||||
#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
|
||||
/* @brief Has improved smart card (ISO7816 protocol) support. */
|
||||
#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
|
||||
/* @brief Has local operation network (CEA709.1-B protocol) support. */
|
||||
#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
|
||||
/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
|
||||
#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
|
||||
/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
|
||||
#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
|
||||
/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
|
||||
#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
|
||||
/* @brief Has separate DMA RX and TX requests. */
|
||||
#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
|
||||
/* @brief Has separate RX and TX interrupts. */
|
||||
#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
|
||||
/* @brief Has LPAURT_PARAM. */
|
||||
#define FSL_FEATURE_LPUART_HAS_PARAM (1)
|
||||
/* @brief Has LPUART_VERID. */
|
||||
#define FSL_FEATURE_LPUART_HAS_VERID (1)
|
||||
/* @brief Has LPUART_GLOBAL. */
|
||||
#define FSL_FEATURE_LPUART_HAS_GLOBAL (1)
|
||||
/* @brief Has LPUART_PINCFG. */
|
||||
#define FSL_FEATURE_LPUART_HAS_PINCFG (1)
|
||||
|
||||
/* interrupt module features */
|
||||
|
||||
/* @brief Lowest interrupt request number. */
|
||||
#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
|
||||
/* @brief Highest interrupt request number. */
|
||||
#define FSL_FEATURE_INTERRUPT_IRQ_MAX (151)
|
||||
|
||||
/* OCOTP module features */
|
||||
|
||||
/* No feature definitions */
|
||||
|
||||
/* PIT module features */
|
||||
|
||||
/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
|
||||
#define FSL_FEATURE_PIT_TIMER_COUNT (4)
|
||||
/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
|
||||
#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
|
||||
/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
|
||||
#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
|
||||
/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
|
||||
#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1)
|
||||
/* @brief Has timer enable control. */
|
||||
#define FSL_FEATURE_PIT_HAS_MDIS (1)
|
||||
|
||||
/* PMU module features */
|
||||
|
||||
/* @brief PMU supports lower power control. */
|
||||
#define FSL_FEATURE_PMU_HAS_LOWPWR_CTRL (0)
|
||||
|
||||
/* PWM module features */
|
||||
|
||||
/* @brief Number of each EflexPWM module channels (outputs). */
|
||||
#define FSL_FEATURE_PWM_CHANNEL_COUNT (12U)
|
||||
/* @brief Number of EflexPWM module A channels (outputs). */
|
||||
#define FSL_FEATURE_PWM_CHANNELA_COUNT (4U)
|
||||
/* @brief Number of EflexPWM module B channels (outputs). */
|
||||
#define FSL_FEATURE_PWM_CHANNELB_COUNT (4U)
|
||||
/* @brief Number of EflexPWM module X channels (outputs). */
|
||||
#define FSL_FEATURE_PWM_CHANNELX_COUNT (4U)
|
||||
/* @brief Number of each EflexPWM module compare channels interrupts. */
|
||||
#define FSL_FEATURE_PWM_CMP_INT_HANDLER_COUNT (4U)
|
||||
/* @brief Number of each EflexPWM module reload channels interrupts. */
|
||||
#define FSL_FEATURE_PWM_RELOAD_INT_HANDLER_COUNT (4U)
|
||||
/* @brief Number of each EflexPWM module capture channels interrupts. */
|
||||
#define FSL_FEATURE_PWM_CAP_INT_HANDLER_COUNT (1U)
|
||||
/* @brief Number of each EflexPWM module reload error channels interrupts. */
|
||||
#define FSL_FEATURE_PWM_RERR_INT_HANDLER_COUNT (1U)
|
||||
/* @brief Number of each EflexPWM module fault channels interrupts. */
|
||||
#define FSL_FEATURE_PWM_FAULT_INT_HANDLER_COUNT (1U)
|
||||
/* @brief Number of submodules in each EflexPWM module. */
|
||||
#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U)
|
||||
|
||||
/* PXP module features */
|
||||
|
||||
/* @brief PXP module has dither engine. */
|
||||
#define FSL_FEATURE_PXP_HAS_DITHER (0)
|
||||
/* @brief PXP module supports repeat run */
|
||||
#define FSL_FEATURE_PXP_HAS_EN_REPEAT (1)
|
||||
/* @brief PXP doesn't have CSC */
|
||||
#define FSL_FEATURE_PXP_HAS_NO_CSC2 (1)
|
||||
/* @brief PXP doesn't have LUT */
|
||||
#define FSL_FEATURE_PXP_HAS_NO_LUT (1)
|
||||
|
||||
/* RTWDOG module features */
|
||||
|
||||
/* @brief Watchdog is available. */
|
||||
#define FSL_FEATURE_RTWDOG_HAS_WATCHDOG (1)
|
||||
/* @brief RTWDOG_CNT can be 32-bit written. */
|
||||
#define FSL_FEATURE_RTWDOG_HAS_32BIT_ACCESS (1)
|
||||
|
||||
/* SAI module features */
|
||||
|
||||
/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
|
||||
#define FSL_FEATURE_SAI_FIFO_COUNT (32)
|
||||
/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
|
||||
#define FSL_FEATURE_SAI_CHANNEL_COUNT (4)
|
||||
/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
|
||||
#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
|
||||
/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
|
||||
#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1)
|
||||
/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
|
||||
#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1)
|
||||
/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
|
||||
#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1)
|
||||
/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
|
||||
#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1)
|
||||
/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
|
||||
#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
|
||||
/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
|
||||
#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0)
|
||||
/* @brief Interrupt source number */
|
||||
#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2)
|
||||
/* @brief Has register of MCR. */
|
||||
#define FSL_FEATURE_SAI_HAS_MCR (0)
|
||||
/* @brief Has bit field MICS of the MCR register. */
|
||||
#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1)
|
||||
/* @brief Has register of MDR */
|
||||
#define FSL_FEATURE_SAI_HAS_MDR (0)
|
||||
/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */
|
||||
#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0)
|
||||
|
||||
/* SEMC module features */
|
||||
|
||||
/* @brief Has WDH time in NOR controller (register bit field NORCR2[WDH]). */
|
||||
#define FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME (1)
|
||||
/* @brief Has WDS time in NOR controller (register bit field NORCR2[WDS]).) */
|
||||
#define FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME (1)
|
||||
|
||||
/* SNVS module features */
|
||||
|
||||
/* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */
|
||||
#define FSL_FEATURE_SNVS_HAS_SRTC (1)
|
||||
|
||||
/* SRC module features */
|
||||
|
||||
/* @brief There is MASK_WDOG3_RST bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST (1)
|
||||
/* @brief There is MIX_RST_STRCH bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH (0)
|
||||
/* @brief There is DBG_RST_MSK_PG bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG (1)
|
||||
/* @brief There is WDOG3_RST_OPTN bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN (0)
|
||||
/* @brief There is CORES_DBG_RST bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST (0)
|
||||
/* @brief There is MTSR bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_MTSR (0)
|
||||
/* @brief There is CORE0_DBG_RST bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_CORE0_DBG_RST (1)
|
||||
/* @brief There is CORE0_RST bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_CORE0_RST (1)
|
||||
/* @brief There is LOCKUP_RST bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST (0)
|
||||
/* @brief There is SWRC bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_SWRC (0)
|
||||
/* @brief There is EIM_RST bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_EIM_RST (0)
|
||||
/* @brief There is LUEN bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_LUEN (0)
|
||||
/* @brief There is no WRBC bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_NO_SCR_WRBC (1)
|
||||
/* @brief There is no WRE bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_NO_SCR_WRE (1)
|
||||
/* @brief There is SISR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SISR (0)
|
||||
/* @brief There is RESET_OUT bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT (0)
|
||||
/* @brief There is WDOG3_RST_B bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B (1)
|
||||
/* @brief There is SW bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_SW (0)
|
||||
/* @brief There is IPP_USER_RESET_B bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B (1)
|
||||
/* @brief There is SNVS bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_SNVS (0)
|
||||
/* @brief There is CSU_RESET_B bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B (1)
|
||||
/* @brief There is LOCKUP bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP (0)
|
||||
/* @brief There is LOCKUP_SYSRESETREQ bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ (1)
|
||||
/* @brief There is POR bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_POR (0)
|
||||
/* @brief There is IPP_RESET_B bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B (1)
|
||||
/* @brief There is no WBI bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_NO_SRSR_WBI (1)
|
||||
|
||||
/* SCB module features */
|
||||
|
||||
/* @brief L1 ICACHE line size in byte. */
|
||||
#define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32)
|
||||
/* @brief L1 DCACHE line size in byte. */
|
||||
#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32)
|
||||
|
||||
/* TRNG module features */
|
||||
|
||||
/* @brief TRNG has no TRNG_ACC bitfield. */
|
||||
#define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1)
|
||||
|
||||
/* USBHS module features */
|
||||
|
||||
/* @brief EHCI module instance count */
|
||||
#define FSL_FEATURE_USBHS_EHCI_COUNT (2)
|
||||
/* @brief Number of endpoints supported */
|
||||
#define FSL_FEATURE_USBHS_ENDPT_COUNT (8)
|
||||
|
||||
/* USDHC module features */
|
||||
|
||||
/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */
|
||||
#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0)
|
||||
/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */
|
||||
#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0)
|
||||
/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */
|
||||
#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1)
|
||||
/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */
|
||||
#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1)
|
||||
|
||||
/* XBARA module features */
|
||||
|
||||
/* @brief DMA_CH_MUX_REQ_30. */
|
||||
#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30 (1)
|
||||
/* @brief DMA_CH_MUX_REQ_31. */
|
||||
#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31 (1)
|
||||
/* @brief DMA_CH_MUX_REQ_94. */
|
||||
#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94 (1)
|
||||
/* @brief DMA_CH_MUX_REQ_95. */
|
||||
#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95 (1)
|
||||
|
||||
#endif /* _MIMXRT1052_FEATURES_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* Copyright (c) 2022 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file connect_gpio.h
|
||||
* @brief define imxrt1052-board gpio function and struct
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2022-03-01
|
||||
*/
|
||||
|
||||
#ifndef __CONNECT_GPIO_H_
|
||||
#define __CONNECT_GPIO_H_
|
||||
|
||||
#include <device.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
int Stm32HwGpioInit(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file connect_sdio.h
|
||||
* @brief define imxrt1052-board sdio function and struct
|
||||
* @version 2.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2022-01-24
|
||||
*/
|
||||
|
||||
#ifndef CONNECT_SDIO_H
|
||||
#define CONNECT_SDIO_H
|
||||
|
||||
#include <device.h>
|
||||
#include <fsl_sd.h>
|
||||
#include <pin_mux.h>
|
||||
#include <clock_config.h>
|
||||
#include <fsl_gpio.h>
|
||||
#include <fsl_common.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
int Imrt1052HwSdioInit(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file connect_uart.h
|
||||
* @brief define imxrt1052-board usart function and struct
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-05-28
|
||||
*/
|
||||
|
||||
#ifndef CONNECT_UART_H
|
||||
#define CONNECT_UART_H
|
||||
|
||||
#include <device.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#define KERNEL_CONSOLE_BUS_NAME SERIAL_BUS_NAME_1
|
||||
#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_1
|
||||
#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_1_DEVICE_NAME_0
|
||||
|
||||
int Imrt1052HwUartInit(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* Copyright (c) 2020 AIIT XUOS Lab
|
||||
* XiUOS is licensed under Mulan PSL v2.
|
||||
* You can use this software according to the terms and conditions of the Mulan PSL v2.
|
||||
* You may obtain a copy of Mulan PSL v2 at:
|
||||
* http://license.coscl.org.cn/MulanPSL2
|
||||
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
||||
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
||||
* See the Mulan PSL v2 for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file connect_usb.h
|
||||
* @brief define imxrt1052-board usb function and struct
|
||||
* @version 2.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2022-02-09
|
||||
*/
|
||||
|
||||
#ifndef CONNECT_USB_H
|
||||
#define CONNECT_USB_H
|
||||
|
||||
#include <device.h>
|
||||
#include <fsl_common.h>
|
||||
#include <usb_host_config.h>
|
||||
#include <usb_host.h>
|
||||
#include <usb_host_msd.h>
|
||||
#include <host_msd_command.h>
|
||||
#include <usb_phy.h>
|
||||
|
||||
#if defined(FS_VFS)
|
||||
#include <iot-vfs.h>
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define CONTROLLER_ID kUSB_ControllerEhci1
|
||||
#define USB_HOST_INTERRUPT_PRIORITY (3U)
|
||||
|
||||
#define USB_HOST_STACK_SIZE 4096
|
||||
|
||||
#define USB_SINGLE_BLOCK_SIZE 512
|
||||
|
||||
int Imrt1052HwUsbHostInit(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,476 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file fsl_cache.h
|
||||
* @brief cache drivers
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021.11.11
|
||||
*/
|
||||
|
||||
#ifndef _FSL_CACHE_H_
|
||||
#define _FSL_CACHE_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup cache
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief cache driver version 2.0.1. */
|
||||
#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
|
||||
/*@}*/
|
||||
|
||||
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
|
||||
#ifndef FSL_SDK_DISBLE_L2CACHE_PRESENT
|
||||
#define FSL_SDK_DISBLE_L2CACHE_PRESENT 0
|
||||
#endif
|
||||
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
|
||||
|
||||
/*! @brief Number of level 2 cache controller ways. */
|
||||
typedef enum _l2cache_way_num
|
||||
{
|
||||
kL2CACHE_8ways = 0, /*!< 8 ways. */
|
||||
#if defined(FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY) && FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY
|
||||
kL2CACHE_16ways /*!< 16 ways. */
|
||||
#endif /* FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY */
|
||||
} l2cache_way_num_t;
|
||||
|
||||
/*! @brief Level 2 cache controller way size. */
|
||||
typedef enum _l2cache_way_size
|
||||
{
|
||||
kL2CACHE_16KBSize = 1, /*!< 16 KB way size. */
|
||||
kL2CACHE_32KBSize = 2, /*!< 32 KB way size. */
|
||||
kL2CACHE_64KBSize = 3, /*!< 64 KB way size. */
|
||||
kL2CACHE_128KBSize = 4, /*!< 128 KB way size. */
|
||||
kL2CACHE_256KBSize = 5, /*!< 256 KB way size. */
|
||||
kL2CACHE_512KBSize = 6 /*!< 512 KB way size. */
|
||||
} l2cache_way_size;
|
||||
|
||||
/*! @brief Level 2 cache controller replacement policy. */
|
||||
typedef enum _l2cache_replacement
|
||||
{
|
||||
kL2CACHE_Pseudorandom = 0U, /*!< Peseudo-random replacement policy using an lfsr. */
|
||||
kL2CACHE_Roundrobin /*!< Round-robin replacemnt policy. */
|
||||
} l2cache_replacement_t;
|
||||
|
||||
/*! @brief Level 2 cache controller force write allocate options. */
|
||||
typedef enum _l2cache_writealloc
|
||||
{
|
||||
kL2CACHE_UseAwcache = 0, /*!< Use AWCAHE attribute for the write allocate. */
|
||||
kL2CACHE_NoWriteallocate, /*!< Force no write allocate. */
|
||||
kL2CACHE_forceWriteallocate /*!< Force write allocate when write misses. */
|
||||
} l2cache_writealloc_t;
|
||||
|
||||
/*! @brief Level 2 cache controller tag/data ram latency. */
|
||||
typedef enum _l2cache_latency
|
||||
{
|
||||
kL2CACHE_1CycleLate = 0, /*!< 1 cycle of latency. */
|
||||
kL2CACHE_2CycleLate, /*!< 2 cycle of latency. */
|
||||
kL2CACHE_3CycleLate, /*!< 3 cycle of latency. */
|
||||
kL2CACHE_4CycleLate, /*!< 4 cycle of latency. */
|
||||
kL2CACHE_5CycleLate, /*!< 5 cycle of latency. */
|
||||
kL2CACHE_6CycleLate, /*!< 6 cycle of latency. */
|
||||
kL2CACHE_7CycleLate, /*!< 7 cycle of latency. */
|
||||
kL2CACHE_8CycleLate /*!< 8 cycle of latency. */
|
||||
} l2cache_latency_t;
|
||||
|
||||
/*! @brief Level 2 cache controller tag/data ram latency configure structure. */
|
||||
typedef struct _l2cache_latency_config
|
||||
{
|
||||
l2cache_latency_t tagWriteLate; /*!< Tag write latency. */
|
||||
l2cache_latency_t tagReadLate; /*!< Tag Read latency. */
|
||||
l2cache_latency_t tagSetupLate; /*!< Tag setup latency. */
|
||||
l2cache_latency_t dataWriteLate; /*!< Data write latency. */
|
||||
l2cache_latency_t dataReadLate; /*!< Data Read latency. */
|
||||
l2cache_latency_t dataSetupLate; /*!< Data setup latency. */
|
||||
} L2cache_latency_config_t;
|
||||
|
||||
/*! @brief Level 2 cache controller configure structure. */
|
||||
typedef struct _l2cache_config
|
||||
{
|
||||
/* ------------------------ l2 cachec basic settings ---------------------------- */
|
||||
l2cache_way_num_t wayNum; /*!< The number of ways. */
|
||||
l2cache_way_size waySize; /*!< The way size = Cache Ram size / wayNum. */
|
||||
l2cache_replacement_t repacePolicy; /*!< Replacemnet policy. */
|
||||
/* ------------------------ tag/data ram latency settings ----------------------- */
|
||||
L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */
|
||||
/* ------------------------ Prefetch enable settings ---------------------------- */
|
||||
bool istrPrefetchEnable; /*!< Instruction prefetch enable. */
|
||||
bool dataPrefetchEnable; /*!< Data prefetch enable. */
|
||||
/* ------------------------ Non-secure access settings -------------------------- */
|
||||
bool nsLockdownEnable; /*!< None-secure lockdown enable. */
|
||||
/* ------------------------ other settings -------------------------------------- */
|
||||
l2cache_writealloc_t writeAlloc; /*!< Write allcoate force option. */
|
||||
} l2cache_config_t;
|
||||
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Control for cortex-m7 L1 cache
|
||||
*@{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enables cortex-m7 L1 instruction cache.
|
||||
*
|
||||
*/
|
||||
static inline void L1CACHE_EnableICache(void)
|
||||
{
|
||||
SCB_EnableICache();
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disables cortex-m7 L1 instruction cache.
|
||||
*
|
||||
*/
|
||||
static inline void L1CACHE_DisableICache(void)
|
||||
{
|
||||
SCB_DisableICache();
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Invalidate cortex-m7 L1 instruction cache.
|
||||
*
|
||||
*/
|
||||
static inline void L1CACHE_InvalidateICache(void)
|
||||
{
|
||||
SCB_InvalidateICache();
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Invalidate cortex-m7 L1 instruction cache by range.
|
||||
*
|
||||
* @param address The start address of the memory to be invalidated.
|
||||
* @param size_byte The memory size.
|
||||
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.
|
||||
* The startAddr here will be forced to align to L1 I-cache line size if
|
||||
* startAddr is not aligned. For the size_byte, application should make sure the
|
||||
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte);
|
||||
|
||||
/*!
|
||||
* @brief Enables cortex-m7 L1 data cache.
|
||||
*
|
||||
*/
|
||||
static inline void L1CACHE_EnableDCache(void)
|
||||
{
|
||||
SCB_EnableDCache();
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disables cortex-m7 L1 data cache.
|
||||
*
|
||||
*/
|
||||
static inline void L1CACHE_DisableDCache(void)
|
||||
{
|
||||
SCB_DisableDCache();
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Invalidates cortex-m7 L1 data cache.
|
||||
*
|
||||
*/
|
||||
static inline void L1CACHE_InvalidateDCache(void)
|
||||
{
|
||||
SCB_InvalidateDCache();
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Cleans cortex-m7 L1 data cache.
|
||||
*
|
||||
*/
|
||||
static inline void L1CACHE_CleanDCache(void)
|
||||
{
|
||||
SCB_CleanDCache();
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Cleans and Invalidates cortex-m7 L1 data cache.
|
||||
*
|
||||
*/
|
||||
static inline void L1CACHE_CleanInvalidateDCache(void)
|
||||
{
|
||||
SCB_CleanInvalidateDCache();
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Invalidates cortex-m7 L1 data cache by range.
|
||||
*
|
||||
* @param address The start address of the memory to be invalidated.
|
||||
* @param size_byte The memory size.
|
||||
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
|
||||
* The startAddr here will be forced to align to L1 D-cache line size if
|
||||
* startAddr is not aligned. For the size_byte, application should make sure the
|
||||
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
|
||||
{
|
||||
uint32_t startAddr = address & (uint32_t) ~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1);
|
||||
uint32_t size = size_byte + address - startAddr;
|
||||
|
||||
SCB_InvalidateDCache_by_Addr((uint32_t *)startAddr, size);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Cleans cortex-m7 L1 data cache by range.
|
||||
*
|
||||
* @param address The start address of the memory to be cleaned.
|
||||
* @param size_byte The memory size.
|
||||
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
|
||||
* The startAddr here will be forced to align to L1 D-cache line size if
|
||||
* startAddr is not aligned. For the size_byte, application should make sure the
|
||||
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
static inline void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte)
|
||||
{
|
||||
uint32_t startAddr = address & (uint32_t) ~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1);
|
||||
uint32_t size = size_byte + address - startAddr;
|
||||
|
||||
SCB_CleanDCache_by_Addr((uint32_t *)startAddr, size);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Cleans and Invalidates cortex-m7 L1 data cache by range.
|
||||
*
|
||||
* @param address The start address of the memory to be clean and invalidated.
|
||||
* @param size_byte The memory size.
|
||||
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
|
||||
* The startAddr here will be forced to align to L1 D-cache line size if
|
||||
* startAddr is not aligned. For the size_byte, application should make sure the
|
||||
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
|
||||
{
|
||||
uint32_t startAddr = address & (uint32_t) ~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1);
|
||||
uint32_t size = size_byte + address - startAddr;
|
||||
|
||||
SCB_CleanInvalidateDCache_by_Addr((uint32_t *)startAddr, size);
|
||||
}
|
||||
/*@}*/
|
||||
|
||||
#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
|
||||
/*!
|
||||
* @name Control for L2 pl310 cache
|
||||
*@{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes the level 2 cache controller module.
|
||||
*
|
||||
* @param config Pointer to configuration structure. See "l2cache_config_t".
|
||||
*/
|
||||
void L2CACHE_Init(l2cache_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Gets an available default settings for the cache controller.
|
||||
*
|
||||
* This function initializes the cache controller configuration structure with default settings.
|
||||
* The default values are:
|
||||
* @code
|
||||
* config->waysNum = kL2CACHE_8ways;
|
||||
* config->waySize = kL2CACHE_32KbSize;
|
||||
* config->repacePolicy = kL2CACHE_Roundrobin;
|
||||
* config->lateConfig = NULL;
|
||||
* config->istrPrefetchEnable = false;
|
||||
* config->dataPrefetchEnable = false;
|
||||
* config->nsLockdownEnable = false;
|
||||
* config->writeAlloc = kL2CACHE_UseAwcache;
|
||||
* @endcode
|
||||
* @param config Pointer to the configuration structure.
|
||||
*/
|
||||
void L2CACHE_GetDefaultConfig(l2cache_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Enables the level 2 cache controller.
|
||||
* This function enables the cache controller. Must be written using a secure access.
|
||||
* If write with a Non-secure access will cause a DECERR response.
|
||||
*
|
||||
*/
|
||||
void L2CACHE_Enable(void);
|
||||
|
||||
/*!
|
||||
* @brief Disables the level 2 cache controller.
|
||||
* This function disables the cache controller. Must be written using a secure access.
|
||||
* If write with a Non-secure access will cause a DECERR response.
|
||||
*
|
||||
*/
|
||||
void L2CACHE_Disable(void);
|
||||
|
||||
/*!
|
||||
* @brief Invalidates the Level 2 cache.
|
||||
* This function invalidates all entries in cache.
|
||||
*
|
||||
*/
|
||||
void L2CACHE_Invalidate(void);
|
||||
|
||||
/*!
|
||||
* @brief Invalidates the Level 2 cache lines in the range of two physical addresses.
|
||||
* This function invalidates all cache lines between two physical addresses.
|
||||
*
|
||||
* @param address The start address of the memory to be invalidated.
|
||||
* @param size_byte The memory size.
|
||||
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
|
||||
* The startAddr here will be forced to align to L2 line size if startAddr
|
||||
* is not aligned. For the size_byte, application should make sure the
|
||||
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte);
|
||||
|
||||
/*!
|
||||
* @brief Cleans the level 2 cache controller.
|
||||
* This function cleans all entries in the level 2 cache controller.
|
||||
*
|
||||
*/
|
||||
void L2CACHE_Clean(void);
|
||||
|
||||
/*!
|
||||
* @brief Cleans the Level 2 cache lines in the range of two physical addresses.
|
||||
* This function cleans all cache lines between two physical addresses.
|
||||
*
|
||||
* @param address The start address of the memory to be cleaned.
|
||||
* @param size_byte The memory size.
|
||||
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
|
||||
* The startAddr here will be forced to align to L2 line size if startAddr
|
||||
* is not aligned. For the size_byte, application should make sure the
|
||||
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte);
|
||||
|
||||
/*!
|
||||
* @brief Cleans and invalidates the level 2 cache controller.
|
||||
* This function cleans and invalidates all entries in the level 2 cache controller.
|
||||
*
|
||||
*/
|
||||
void L2CACHE_CleanInvalidate(void);
|
||||
|
||||
/*!
|
||||
* @brief Cleans and invalidates the Level 2 cache lines in the range of two physical addresses.
|
||||
* This function cleans and invalidates all cache lines between two physical addresses.
|
||||
*
|
||||
* @param address The start address of the memory to be cleaned and invalidated.
|
||||
* @param size_byte The memory size.
|
||||
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
|
||||
* The startAddr here will be forced to align to L2 line size if startAddr
|
||||
* is not aligned. For the size_byte, application should make sure the
|
||||
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte);
|
||||
|
||||
/*!
|
||||
* @brief Enables or disables to lock down the data and instruction by way.
|
||||
* This function locks down the cached instruction/data by way and prevent the adresses from
|
||||
* being allocated and prevent dara from being evicted out of the level 2 cache.
|
||||
* But the normal cache maintenance operations that invalidate, clean or clean
|
||||
* and validate cache contents affect the locked-down cache lines as normal.
|
||||
*
|
||||
* @param masterId The master id, range from 0 ~ 7.
|
||||
* @param mask The ways to be enabled or disabled to lockdown.
|
||||
* each bit in value is related to each way of the cache. for example:
|
||||
* value: bit 0 ------ way 0.
|
||||
* value: bit 1 ------ way 1.
|
||||
* --------------------------
|
||||
* value: bit 15 ------ way 15.
|
||||
* Note: please make sure the value setting is align with your supported ways.
|
||||
* @param enable True enable the lockdown, false to disable the lockdown.
|
||||
*/
|
||||
void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable);
|
||||
|
||||
/*@}*/
|
||||
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
|
||||
|
||||
/*!
|
||||
* @name Unified Cache Control for all caches (cortex-m7 L1 cache + l2 pl310)
|
||||
* Mainly used for many drivers for easy cache operation.
|
||||
*@{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Invalidates all instruction caches by range.
|
||||
*
|
||||
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
||||
*
|
||||
* @param address The physical address.
|
||||
* @param size_byte size of the memory to be invalidated.
|
||||
* @note address and size should be aligned to cache line size
|
||||
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
||||
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
||||
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte);
|
||||
|
||||
/*!
|
||||
* @brief Invalidates all data caches by range.
|
||||
*
|
||||
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
||||
*
|
||||
* @param address The physical address.
|
||||
* @param size_byte size of the memory to be invalidated.
|
||||
* @note address and size should be aligned to cache line size
|
||||
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
||||
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
||||
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte);
|
||||
|
||||
/*!
|
||||
* @brief Cleans all data caches by range.
|
||||
*
|
||||
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
||||
*
|
||||
* @param address The physical address.
|
||||
* @param size_byte size of the memory to be cleaned.
|
||||
* @note address and size should be aligned to cache line size
|
||||
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
||||
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
||||
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte);
|
||||
|
||||
/*!
|
||||
* @brief Cleans and Invalidates all data caches by range.
|
||||
*
|
||||
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
||||
*
|
||||
* @param address The physical address.
|
||||
* @param size_byte size of the memory to be cleaned and invalidated.
|
||||
* @note address and size should be aligned to cache line size
|
||||
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
||||
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
||||
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte);
|
||||
|
||||
/*@}*/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_CACHE_H_*/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,593 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file fsl_common.h
|
||||
* @brief common drivers header
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021.11.11
|
||||
*/
|
||||
|
||||
#ifndef _FSL_COMMON_H_
|
||||
#define _FSL_COMMON_H_
|
||||
|
||||
#include <assert.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#include <stddef.h>
|
||||
#endif
|
||||
|
||||
#include "fsl_device_registers.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup ksdk_common
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief Construct a status code value from a group and code number. */
|
||||
#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
|
||||
|
||||
/*! @brief Construct the version number for drivers. */
|
||||
#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief common driver version 2.0.1. */
|
||||
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
|
||||
/*@}*/
|
||||
|
||||
/* Debug console type definition. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */
|
||||
|
||||
/*! @brief Status group numbers. */
|
||||
enum _status_groups
|
||||
{
|
||||
kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */
|
||||
kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */
|
||||
kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */
|
||||
kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */
|
||||
kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */
|
||||
kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */
|
||||
kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */
|
||||
kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */
|
||||
kStatusGroup_UART = 10, /*!< Group number for UART status codes. */
|
||||
kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */
|
||||
kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */
|
||||
kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */
|
||||
kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/
|
||||
kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/
|
||||
kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/
|
||||
kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */
|
||||
kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */
|
||||
kStatusGroup_SAI = 19, /*!< Group number for SAI status code */
|
||||
kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */
|
||||
kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */
|
||||
kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */
|
||||
kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */
|
||||
kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */
|
||||
kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */
|
||||
kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */
|
||||
kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */
|
||||
kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */
|
||||
kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */
|
||||
kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */
|
||||
kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */
|
||||
kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */
|
||||
kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */
|
||||
kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */
|
||||
kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */
|
||||
kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */
|
||||
kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */
|
||||
kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */
|
||||
kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */
|
||||
kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */
|
||||
kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */
|
||||
kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */
|
||||
kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */
|
||||
kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */
|
||||
kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */
|
||||
kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */
|
||||
kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */
|
||||
kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/
|
||||
kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */
|
||||
kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */
|
||||
kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */
|
||||
kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */
|
||||
kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */
|
||||
kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/
|
||||
kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/
|
||||
kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/
|
||||
kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/
|
||||
kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */
|
||||
kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */
|
||||
kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */
|
||||
kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */
|
||||
kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */
|
||||
kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */
|
||||
kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */
|
||||
kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */
|
||||
kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */
|
||||
kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */
|
||||
kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */
|
||||
kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */
|
||||
kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */
|
||||
kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */
|
||||
kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
|
||||
kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */
|
||||
|
||||
kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */
|
||||
kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */
|
||||
kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */
|
||||
kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */
|
||||
kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */
|
||||
kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */
|
||||
kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */
|
||||
kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */
|
||||
kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */
|
||||
kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */
|
||||
kStatusGroup_LED = 137, /*!< Group number for LED status codes. */
|
||||
kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */
|
||||
kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */
|
||||
kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */
|
||||
kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */
|
||||
kStatusGroup_LIST = 142, /*!< Group number for List status codes. */
|
||||
kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */
|
||||
kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */
|
||||
kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */
|
||||
};
|
||||
|
||||
/*! @brief Generic status return codes. */
|
||||
enum _generic_status
|
||||
{
|
||||
kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
|
||||
kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
|
||||
kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
|
||||
kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
|
||||
kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
|
||||
kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
|
||||
kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
|
||||
};
|
||||
|
||||
/*! @brief Type used for all status and error return values. */
|
||||
typedef int32_t status_t;
|
||||
|
||||
/*
|
||||
* The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
|
||||
* defined in previous of this file.
|
||||
*/
|
||||
#include "fsl_clock.h"
|
||||
|
||||
/*
|
||||
* Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
|
||||
*/
|
||||
#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
|
||||
(defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
|
||||
#include "fsl_reset.h"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Macro guard for whether to use default weak IRQ implementation in drivers
|
||||
*/
|
||||
#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
|
||||
#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1
|
||||
#endif
|
||||
|
||||
/*! @name Min/max macros */
|
||||
/* @{ */
|
||||
#if !defined(MIN)
|
||||
#define MIN(a, b) ((a) < (b) ? (a) : (b))
|
||||
#endif
|
||||
|
||||
#if !defined(MAX)
|
||||
#define MAX(a, b) ((a) > (b) ? (a) : (b))
|
||||
#endif
|
||||
/* @} */
|
||||
|
||||
/*! @brief Computes the number of elements in an array. */
|
||||
#if !defined(ARRAY_SIZE)
|
||||
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
|
||||
#endif
|
||||
|
||||
/*! @name UINT16_MAX/UINT32_MAX value */
|
||||
/* @{ */
|
||||
#if !defined(UINT16_MAX)
|
||||
#define UINT16_MAX ((uint16_t)-1)
|
||||
#endif
|
||||
|
||||
#if !defined(UINT32_MAX)
|
||||
#define UINT32_MAX ((uint32_t)-1)
|
||||
#endif
|
||||
/* @} */
|
||||
|
||||
/*! @name Timer utilities */
|
||||
/* @{ */
|
||||
/*! Macro to convert a microsecond period to raw count value */
|
||||
#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)
|
||||
/*! Macro to convert a raw count value to microsecond */
|
||||
#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
|
||||
|
||||
/*! Macro to convert a millisecond period to raw count value */
|
||||
#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
|
||||
/*! Macro to convert a raw count value to millisecond */
|
||||
#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
|
||||
/* @} */
|
||||
|
||||
/*! @name Alignment variable definition macros */
|
||||
/* @{ */
|
||||
#if (defined(__ICCARM__))
|
||||
/**
|
||||
* Workaround to disable MISRA C message suppress warnings for IAR compiler.
|
||||
* http://supp.iar.com/Support/?note=24725
|
||||
*/
|
||||
_Pragma("diag_suppress=Pm120")
|
||||
#define SDK_PRAGMA(x) _Pragma(#x)
|
||||
_Pragma("diag_error=Pm120")
|
||||
/*! Macro to define a variable with alignbytes alignment */
|
||||
#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
|
||||
/*! Macro to define a variable with L1 d-cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||
#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
|
||||
#endif
|
||||
/*! Macro to define a variable with L2 cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
||||
#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
|
||||
#endif
|
||||
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
|
||||
/*! Macro to define a variable with alignbytes alignment */
|
||||
#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
|
||||
/*! Macro to define a variable with L1 d-cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||
#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var
|
||||
#endif
|
||||
/*! Macro to define a variable with L2 cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
||||
#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var
|
||||
#endif
|
||||
#elif defined(__GNUC__)
|
||||
/*! Macro to define a variable with alignbytes alignment */
|
||||
#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
|
||||
/*! Macro to define a variable with L1 d-cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||
#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))
|
||||
#endif
|
||||
/*! Macro to define a variable with L2 cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
||||
#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)))
|
||||
#endif
|
||||
#else
|
||||
#error Toolchain not supported
|
||||
#define SDK_ALIGN(var, alignbytes) var
|
||||
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||
#define SDK_L1DCACHE_ALIGN(var) var
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
||||
#define SDK_L2CACHE_ALIGN(var) var
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*! Macro to change a value to a given size aligned value */
|
||||
#define SDK_SIZEALIGN(var, alignbytes) \
|
||||
((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))
|
||||
/* @} */
|
||||
|
||||
/*! @name Non-cacheable region definition macros */
|
||||
/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
|
||||
* "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables,
|
||||
* please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables
|
||||
* will be initialized to zero in system startup.
|
||||
*/
|
||||
/* @{ */
|
||||
#if (defined(__ICCARM__))
|
||||
#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
|
||||
#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"
|
||||
#else
|
||||
#define AT_NONCACHEABLE_SECTION(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
|
||||
#endif
|
||||
#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
|
||||
#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
|
||||
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
|
||||
__attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
|
||||
__attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var
|
||||
#else
|
||||
#define AT_NONCACHEABLE_SECTION(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var
|
||||
#endif
|
||||
#elif(defined(__GNUC__))
|
||||
/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
|
||||
* in your projects to make sure the non-cacheable section variables will be initialized in system startup.
|
||||
*/
|
||||
#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
|
||||
__attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
|
||||
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
|
||||
__attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))
|
||||
#else
|
||||
#define AT_NONCACHEABLE_SECTION(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes)))
|
||||
#endif
|
||||
#else
|
||||
#error Toolchain not supported.
|
||||
#define AT_NONCACHEABLE_SECTION(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var
|
||||
#endif
|
||||
/* @} */
|
||||
|
||||
/*! @name Time sensitive region */
|
||||
/* @{ */
|
||||
#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE
|
||||
#if (defined(__ICCARM__))
|
||||
#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
|
||||
#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess"
|
||||
#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
|
||||
#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
|
||||
#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
|
||||
#elif(defined(__GNUC__))
|
||||
#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
|
||||
#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
|
||||
#else
|
||||
#error Toolchain not supported.
|
||||
#endif /* defined(__ICCARM__) */
|
||||
#else
|
||||
#if (defined(__ICCARM__))
|
||||
#define AT_QUICKACCESS_SECTION_CODE(func) func
|
||||
#define AT_QUICKACCESS_SECTION_DATA(func) func
|
||||
#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
|
||||
#define AT_QUICKACCESS_SECTION_CODE(func) func
|
||||
#define AT_QUICKACCESS_SECTION_DATA(func) func
|
||||
#elif(defined(__GNUC__))
|
||||
#define AT_QUICKACCESS_SECTION_CODE(func) func
|
||||
#define AT_QUICKACCESS_SECTION_DATA(func) func
|
||||
#else
|
||||
#error Toolchain not supported.
|
||||
#endif
|
||||
#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
|
||||
/* @} */
|
||||
|
||||
/*! @name Ram Function */
|
||||
#if (defined(__ICCARM__))
|
||||
#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"
|
||||
#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
|
||||
#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
|
||||
#elif(defined(__GNUC__))
|
||||
#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
|
||||
#else
|
||||
#error Toolchain not supported.
|
||||
#endif /* defined(__ICCARM__) */
|
||||
/* @} */
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Enable specific interrupt.
|
||||
*
|
||||
* Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
|
||||
* levels. For example, there are NVIC and intmux. Here the interrupts connected
|
||||
* to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
|
||||
* The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
|
||||
* to NVIC first then routed to core.
|
||||
*
|
||||
* This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
|
||||
* is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
|
||||
*
|
||||
* @param interrupt The IRQ number.
|
||||
* @retval kStatus_Success Interrupt enabled successfully
|
||||
* @retval kStatus_Fail Failed to enable the interrupt
|
||||
*/
|
||||
static inline status_t EnableIRQ(IRQn_Type interrupt)
|
||||
{
|
||||
if (NotAvail_IRQn == interrupt)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
|
||||
if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(__GIC_PRIO_BITS)
|
||||
GIC_EnableIRQ(interrupt);
|
||||
#else
|
||||
NVIC_EnableIRQ(interrupt);
|
||||
#endif
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable specific interrupt.
|
||||
*
|
||||
* Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
|
||||
* levels. For example, there are NVIC and intmux. Here the interrupts connected
|
||||
* to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
|
||||
* The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
|
||||
* to NVIC first then routed to core.
|
||||
*
|
||||
* This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
|
||||
* is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
|
||||
*
|
||||
* @param interrupt The IRQ number.
|
||||
* @retval kStatus_Success Interrupt disabled successfully
|
||||
* @retval kStatus_Fail Failed to disable the interrupt
|
||||
*/
|
||||
static inline status_t DisableIRQ(IRQn_Type interrupt)
|
||||
{
|
||||
if (NotAvail_IRQn == interrupt)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
|
||||
if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(__GIC_PRIO_BITS)
|
||||
GIC_DisableIRQ(interrupt);
|
||||
#else
|
||||
NVIC_DisableIRQ(interrupt);
|
||||
#endif
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the global IRQ
|
||||
*
|
||||
* Disable the global interrupt and return the current primask register. User is required to provided the primask
|
||||
* register for the EnableGlobalIRQ().
|
||||
*
|
||||
* @return Current primask value.
|
||||
*/
|
||||
static inline uint32_t DisableGlobalIRQ(void)
|
||||
{
|
||||
#if defined(CPSR_I_Msk)
|
||||
uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
|
||||
|
||||
__disable_irq();
|
||||
|
||||
return cpsr;
|
||||
#else
|
||||
uint32_t regPrimask = __get_PRIMASK();
|
||||
|
||||
__disable_irq();
|
||||
|
||||
return regPrimask;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the global IRQ
|
||||
*
|
||||
* Set the primask register with the provided primask value but not just enable the primask. The idea is for the
|
||||
* convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
|
||||
* use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
|
||||
*
|
||||
* @param primask value of primask register to be restored. The primask value is supposed to be provided by the
|
||||
* DisableGlobalIRQ().
|
||||
*/
|
||||
static inline void EnableGlobalIRQ(uint32_t primask)
|
||||
{
|
||||
#if defined(CPSR_I_Msk)
|
||||
__set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
|
||||
#else
|
||||
__set_PRIMASK(primask);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if defined(ENABLE_RAM_VECTOR_TABLE)
|
||||
/*!
|
||||
* @brief install IRQ handler
|
||||
*
|
||||
* @param irq IRQ number
|
||||
* @param irqHandler IRQ handler address
|
||||
* @return The old IRQ handler address
|
||||
*/
|
||||
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
|
||||
#endif /* ENABLE_RAM_VECTOR_TABLE. */
|
||||
|
||||
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
|
||||
/*!
|
||||
* @brief Enable specific interrupt for wake-up from deep-sleep mode.
|
||||
*
|
||||
* Enable the interrupt for wake-up from deep sleep mode.
|
||||
* Some interrupts are typically used in sleep mode only and will not occur during
|
||||
* deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
|
||||
* those clocks (significantly increasing power consumption in the reduced power mode),
|
||||
* making these wake-ups possible.
|
||||
*
|
||||
* @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly).
|
||||
*
|
||||
* @param interrupt The IRQ number.
|
||||
*/
|
||||
void EnableDeepSleepIRQ(IRQn_Type interrupt);
|
||||
|
||||
/*!
|
||||
* @brief Disable specific interrupt for wake-up from deep-sleep mode.
|
||||
*
|
||||
* Disable the interrupt for wake-up from deep sleep mode.
|
||||
* Some interrupts are typically used in sleep mode only and will not occur during
|
||||
* deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
|
||||
* those clocks (significantly increasing power consumption in the reduced power mode),
|
||||
* making these wake-ups possible.
|
||||
*
|
||||
* @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly).
|
||||
*
|
||||
* @param interrupt The IRQ number.
|
||||
*/
|
||||
void DisableDeepSleepIRQ(IRQn_Type interrupt);
|
||||
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
|
||||
|
||||
/*!
|
||||
* @brief Allocate memory with given alignment and aligned size.
|
||||
*
|
||||
* This is provided to support the dynamically allocated memory
|
||||
* used in cache-able region.
|
||||
* @param size The length required to malloc.
|
||||
* @param alignbytes The alignment size.
|
||||
* @retval The allocated memory.
|
||||
*/
|
||||
void *SDK_Malloc(size_t size, size_t alignbytes);
|
||||
|
||||
/*!
|
||||
* @brief Free memory.
|
||||
*
|
||||
* @param ptr The memory to be release.
|
||||
*/
|
||||
void SDK_Free(void *ptr);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @} */
|
||||
|
||||
#endif /* _FSL_COMMON_H_ */
|
||||
|
|
@ -0,0 +1,213 @@
|
|||
/*
|
||||
* Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Debug console shall provide input and output functions to scan and print formatted data.
|
||||
* o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier"
|
||||
* - [flags] :'-', '+', '#', ' ', '0'
|
||||
* - [width]: number (0,1...)
|
||||
* - [.precision]: number (0,1...)
|
||||
* - [length]: do not support
|
||||
* - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n'
|
||||
* o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier"
|
||||
* - [*]: is supported.
|
||||
* - [width]: number (0,1...)
|
||||
* - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t')
|
||||
* - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's'
|
||||
*/
|
||||
|
||||
#ifndef _FSL_DEBUGCONSOLE_H_
|
||||
#define _FSL_DEBUGCONSOLE_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "serial_manager.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup debugconsole
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
extern serial_handle_t g_serialHandle; /*!< serial manager handle */
|
||||
|
||||
/*! @brief Definition select redirect toolchain printf, scanf to uart or not. */
|
||||
#define DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN 0U /*!< Select toolchain printf and scanf. */
|
||||
#define DEBUGCONSOLE_REDIRECT_TO_SDK 1U /*!< Select SDK version printf, scanf. */
|
||||
#define DEBUGCONSOLE_DISABLE 2U /*!< Disable debugconsole function. */
|
||||
|
||||
/*! @brief Definition to select sdk or toolchain printf, scanf. The macro only support
|
||||
* to be redefined in project setting.
|
||||
*/
|
||||
#ifndef SDK_DEBUGCONSOLE
|
||||
#define SDK_DEBUGCONSOLE 1U
|
||||
#endif
|
||||
|
||||
/*! @brief Definition to select redirect toolchain printf, scanf to uart or not. */
|
||||
#ifndef SDK_DEBUGCONSOLE_UART
|
||||
/* mcux will handle this macro, not define it here */
|
||||
#if (!defined(__MCUXPRESSO))
|
||||
#define SDK_DEBUGCONSOLE_UART
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE)
|
||||
#include <stdio.h>
|
||||
#endif
|
||||
|
||||
/*! @brief Definition to select redirect toolchain printf, scanf to uart or not.
|
||||
*
|
||||
* if SDK_DEBUGCONSOLE defined to 0,it represents select toolchain printf, scanf.
|
||||
* if SDK_DEBUGCONSOLE defined to 1,it represents select SDK version printf, scanf.
|
||||
* if SDK_DEBUGCONSOLE defined to 2,it represents disable debugconsole function.
|
||||
*/
|
||||
#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE /* Disable debug console */
|
||||
#define PRINTF
|
||||
#define SCANF
|
||||
#define PUTCHAR
|
||||
#define GETCHAR
|
||||
#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK /* Select printf, scanf, putchar, getchar of SDK version. */
|
||||
#define PRINTF DbgConsole_Printf
|
||||
#define SCANF DbgConsole_Scanf
|
||||
#define PUTCHAR DbgConsole_Putchar
|
||||
#define GETCHAR DbgConsole_Getchar
|
||||
#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN /* Select printf, scanf, putchar, getchar of toolchain. \ \
|
||||
*/
|
||||
#define PRINTF printf
|
||||
#define SCANF scanf
|
||||
#define PUTCHAR putchar
|
||||
#define GETCHAR getchar
|
||||
#endif /* SDK_DEBUGCONSOLE */
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*! @name Initialization*/
|
||||
/* @{ */
|
||||
|
||||
/*!
|
||||
* @brief Initializes the peripheral used for debug messages.
|
||||
*
|
||||
* Call this function to enable debug log messages to be output via the specified peripheral
|
||||
* initialized by the serial manager module.
|
||||
* After this function has returned, stdout and stdin are connected to the selected peripheral.
|
||||
*
|
||||
* @param instance The instance of the module.
|
||||
* @param baudRate The desired baud rate in bits per second.
|
||||
* @param device Low level device type for the debug console, can be one of the following.
|
||||
* @arg kSerialPort_Uart,
|
||||
* @arg kSerialPort_UsbCdc
|
||||
* @arg kSerialPort_UsbCdcVirtual.
|
||||
* @param clkSrcFreq Frequency of peripheral source clock.
|
||||
*
|
||||
* @return Indicates whether initialization was successful or not.
|
||||
* @retval kStatus_Success Execution successfully
|
||||
*/
|
||||
status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq);
|
||||
|
||||
/*!
|
||||
* @brief De-initializes the peripheral used for debug messages.
|
||||
*
|
||||
* Call this function to disable debug log messages to be output via the specified peripheral
|
||||
* initialized by the serial manager module.
|
||||
*
|
||||
* @return Indicates whether de-initialization was successful or not.
|
||||
*/
|
||||
status_t DbgConsole_Deinit(void);
|
||||
|
||||
#if SDK_DEBUGCONSOLE
|
||||
/*!
|
||||
* @brief Writes formatted output to the standard output stream.
|
||||
*
|
||||
* Call this function to write a formatted output to the standard output stream.
|
||||
*
|
||||
* @param formatString Format control string.
|
||||
* @return Returns the number of characters printed or a negative value if an error occurs.
|
||||
*/
|
||||
int DbgConsole_Printf(const char *formatString, ...);
|
||||
|
||||
/*!
|
||||
* @brief Writes a character to stdout.
|
||||
*
|
||||
* Call this function to write a character to stdout.
|
||||
*
|
||||
* @param ch Character to be written.
|
||||
* @return Returns the character written.
|
||||
*/
|
||||
int DbgConsole_Putchar(int ch);
|
||||
|
||||
/*!
|
||||
* @brief Reads formatted data from the standard input stream.
|
||||
*
|
||||
* Call this function to read formatted data from the standard input stream.
|
||||
*
|
||||
* @note Due the limitation in the BM OSA environment (CPU is blocked in the function,
|
||||
* other tasks will not be scheduled), the function cannot be used when the
|
||||
* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment.
|
||||
* And an error is returned when the function called in this case. The suggestion
|
||||
* is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.
|
||||
*
|
||||
* @param formatString Format control string.
|
||||
* @return Returns the number of fields successfully converted and assigned.
|
||||
*/
|
||||
int DbgConsole_Scanf(char *formatString, ...);
|
||||
|
||||
/*!
|
||||
* @brief Reads a character from standard input.
|
||||
*
|
||||
* Call this function to read a character from standard input.
|
||||
*
|
||||
* @note Due the limitation in the BM OSA environment (CPU is blocked in the function,
|
||||
* other tasks will not be scheduled), the function cannot be used when the
|
||||
* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment.
|
||||
* And an error is returned when the function called in this case. The suggestion
|
||||
* is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.
|
||||
*
|
||||
* @return Returns the character read.
|
||||
*/
|
||||
int DbgConsole_Getchar(void);
|
||||
|
||||
/*!
|
||||
* @brief Debug console flush.
|
||||
*
|
||||
* Call this function to wait the tx buffer empty.
|
||||
* If interrupt transfer is using, make sure the global IRQ is enable before call this function
|
||||
* This function should be called when
|
||||
* 1, before enter power down mode
|
||||
* 2, log is required to print to terminal immediately
|
||||
* @return Indicates whether wait idle was successful or not.
|
||||
*/
|
||||
status_t DbgConsole_Flush(void);
|
||||
|
||||
#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
|
||||
/*!
|
||||
* @brief Debug console try to get char
|
||||
* This function provides a API which will not block current task, if character is
|
||||
* available return it, otherwise return fail.
|
||||
* @param ch the address of char to receive
|
||||
* @return Indicates get char was successful or not.
|
||||
*/
|
||||
status_t DbgConsole_TryGetchar(char *ch);
|
||||
#endif
|
||||
|
||||
#endif /* SDK_DEBUGCONSOLE */
|
||||
|
||||
/*! @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*! @} */
|
||||
|
||||
#endif /* _FSL_DEBUGCONSOLE_H_ */
|
||||
|
|
@ -0,0 +1,158 @@
|
|||
/*
|
||||
* Copyright 2017 - 2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _FSL_DEBUG_CONSOLE_CONF_H_
|
||||
#define _FSL_DEBUG_CONSOLE_CONF_H_
|
||||
|
||||
/****************Debug console configuration********************/
|
||||
|
||||
/*! @brief If Non-blocking mode is needed, please define it at project setting,
|
||||
* otherwise blocking mode is the default transfer mode.
|
||||
* Warning: If you want to use non-blocking transfer,please make sure the corresponding
|
||||
* IO interrupt is enable, otherwise there is no output.
|
||||
* And non-blocking is combine with buffer, no matter bare-metal or rtos.
|
||||
* Below shows how to configure in your project if you want to use non-blocking mode.
|
||||
* For IAR, right click project and select "Options", define it in "C/C++ Compiler->Preprocessor->Defined symbols".
|
||||
* For KEIL, click "Options for Target…", define it in "C/C++->Preprocessor Symbols->Define".
|
||||
* For ARMGCC, open CmakeLists.txt and add the following lines,
|
||||
* "SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for debug target.
|
||||
* "SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for release target.
|
||||
* For MCUxpresso, right click project and select "Properties", define it in "C/C++ Build->Settings->MCU C
|
||||
* Complier->Preprocessor".
|
||||
*
|
||||
*/
|
||||
#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
|
||||
/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically
|
||||
* when
|
||||
* non-blocking transfer is using,
|
||||
* This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
|
||||
* If it is configured too small, log maybe missed , because the log will not be
|
||||
* buffered if the buffer is full, and the print will return immediately with -1.
|
||||
* And this value should be multiple of 4 to meet memory alignment.
|
||||
*
|
||||
*/
|
||||
#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN
|
||||
#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U)
|
||||
#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */
|
||||
|
||||
/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when
|
||||
* non-blocking transfer is using,
|
||||
* This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
|
||||
* If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small.
|
||||
* And this value should be multiple of 4 to meet memory alignment.
|
||||
*
|
||||
*/
|
||||
#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN
|
||||
#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (1024U)
|
||||
#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */
|
||||
|
||||
/*!@ brief Whether enable the reliable TX function
|
||||
* If the macro is zero, the reliable TX function of the debug console is disabled.
|
||||
* When the macro is zero, the string of PRINTF will be thrown away after the transmit buffer is full.
|
||||
*/
|
||||
#ifndef DEBUG_CONSOLE_TX_RELIABLE_ENABLE
|
||||
#define DEBUG_CONSOLE_TX_RELIABLE_ENABLE (1U)
|
||||
#endif /* DEBUG_CONSOLE_RX_ENABLE */
|
||||
|
||||
#else
|
||||
#define DEBUG_CONSOLE_TRANSFER_BLOCKING
|
||||
#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
|
||||
|
||||
/*!@ brief Whether enable the RX function
|
||||
* If the macro is zero, the receive function of the debug console is disabled.
|
||||
*/
|
||||
#ifndef DEBUG_CONSOLE_RX_ENABLE
|
||||
#define DEBUG_CONSOLE_RX_ENABLE (1U)
|
||||
#endif /* DEBUG_CONSOLE_RX_ENABLE */
|
||||
|
||||
/*!@ brief define the MAX log length debug console support , that is when you call printf("log", x);, the log
|
||||
* length can not bigger than this value.
|
||||
* This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if
|
||||
* the buffer is too big and current task stack size not big enough.
|
||||
*/
|
||||
#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN
|
||||
#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U)
|
||||
#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */
|
||||
|
||||
/*!@ brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log
|
||||
* length can not bigger than this value.
|
||||
* As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN.
|
||||
*/
|
||||
#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN
|
||||
#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U)
|
||||
#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */
|
||||
|
||||
/*! @brief Debug console synchronization
|
||||
* User should not change these macro for synchronization mode, but add the
|
||||
* corresponding synchronization mechanism per different software environment.
|
||||
* Such as, if another RTOS is used,
|
||||
* add:
|
||||
* #define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3
|
||||
* in this configuration file and implement the synchronization in fsl.log.c.
|
||||
*/
|
||||
/*! @brief synchronization for baremetal software */
|
||||
#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0
|
||||
/*! @brief synchronization for freertos software */
|
||||
#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1
|
||||
|
||||
/*! @brief RTOS synchronization mechanism disable
|
||||
* If not defined, default is enable, to avoid multitask log print mess.
|
||||
* If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c
|
||||
* If synchronization is disabled, log maybe messed on terminal.
|
||||
*/
|
||||
#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION
|
||||
#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
|
||||
#ifdef FSL_RTOS_FREE_RTOS
|
||||
#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS
|
||||
#else
|
||||
#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM
|
||||
#endif /* FSL_RTOS_FREE_RTOS */
|
||||
#else
|
||||
#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM
|
||||
#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
|
||||
#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */
|
||||
|
||||
/*! @brief echo function support
|
||||
* If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO
|
||||
* at your project setting.
|
||||
*/
|
||||
#ifndef DEBUG_CONSOLE_ENABLE_ECHO
|
||||
#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0
|
||||
#else
|
||||
#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1
|
||||
#endif /* DEBUG_CONSOLE_ENABLE_ECHO */
|
||||
|
||||
/*********************************************************************/
|
||||
|
||||
/***************Debug console other configuration*********************/
|
||||
/*! @brief Definition to printf the float number. */
|
||||
#ifndef PRINTF_FLOAT_ENABLE
|
||||
#define PRINTF_FLOAT_ENABLE 0U
|
||||
#endif /* PRINTF_FLOAT_ENABLE */
|
||||
|
||||
/*! @brief Definition to scanf the float number. */
|
||||
#ifndef SCANF_FLOAT_ENABLE
|
||||
#define SCANF_FLOAT_ENABLE 0U
|
||||
#endif /* SCANF_FLOAT_ENABLE */
|
||||
|
||||
/*! @brief Definition to support advanced format specifier for printf. */
|
||||
#ifndef PRINTF_ADVANCED_ENABLE
|
||||
#define PRINTF_ADVANCED_ENABLE 0U
|
||||
#endif /* PRINTF_ADVANCED_ENABLE */
|
||||
|
||||
/*! @brief Definition to support advanced format specifier for scanf. */
|
||||
#ifndef SCANF_ADVANCED_ENABLE
|
||||
#define SCANF_ADVANCED_ENABLE 0U
|
||||
#endif /* SCANF_ADVANCED_ENABLE */
|
||||
|
||||
/*! @brief Definition to select virtual com(USB CDC) as the debug console. */
|
||||
#ifndef BOARD_USE_VIRTUALCOM
|
||||
#define BOARD_USE_VIRTUALCOM 0U
|
||||
#endif
|
||||
/*******************************************************************/
|
||||
|
||||
#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* Copyright 2014-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __FSL_DEVICE_REGISTERS_H__
|
||||
#define __FSL_DEVICE_REGISTERS_H__
|
||||
|
||||
/*
|
||||
* Include the cpu specific register header files.
|
||||
*
|
||||
* The CPU macro should be declared in the project or makefile.
|
||||
*/
|
||||
#if (defined(CPU_MIMXRT1052CVJ5B) || defined(CPU_MIMXRT1052CVL5B) || defined(CPU_MIMXRT1052DVJ6B) || \
|
||||
defined(CPU_MIMXRT1052DVL6B))
|
||||
|
||||
#define MIMXRT1052_SERIES
|
||||
|
||||
/* CMSIS-style register definitions */
|
||||
#include "MIMXRT1052.h"
|
||||
/* CPU specific feature definitions */
|
||||
#include "MIMXRT1052_features.h"
|
||||
|
||||
#else
|
||||
#error "No valid CPU defined!"
|
||||
#endif
|
||||
|
||||
#endif /* __FSL_DEVICE_REGISTERS_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,342 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _FSL_GPIO_H_
|
||||
#define _FSL_GPIO_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup gpio_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief GPIO driver version 2.0.1. */
|
||||
#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
|
||||
/*@}*/
|
||||
|
||||
/*! @brief GPIO direction definition. */
|
||||
typedef enum _gpio_pin_direction
|
||||
{
|
||||
kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input.*/
|
||||
kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output.*/
|
||||
} gpio_pin_direction_t;
|
||||
|
||||
/*! @brief GPIO interrupt mode definition. */
|
||||
typedef enum _gpio_interrupt_mode
|
||||
{
|
||||
kGPIO_NoIntmode = 0U, /*!< Set current pin general IO functionality.*/
|
||||
kGPIO_IntLowLevel = 1U, /*!< Set current pin interrupt is low-level sensitive.*/
|
||||
kGPIO_IntHighLevel = 2U, /*!< Set current pin interrupt is high-level sensitive.*/
|
||||
kGPIO_IntRisingEdge = 3U, /*!< Set current pin interrupt is rising-edge sensitive.*/
|
||||
kGPIO_IntFallingEdge = 4U, /*!< Set current pin interrupt is falling-edge sensitive.*/
|
||||
kGPIO_IntRisingOrFallingEdge = 5U, /*!< Enable the edge select bit to override the ICR register's configuration.*/
|
||||
} gpio_interrupt_mode_t;
|
||||
|
||||
/*! @brief GPIO Init structure definition. */
|
||||
typedef struct _gpio_pin_config
|
||||
{
|
||||
gpio_pin_direction_t direction; /*!< Specifies the pin direction. */
|
||||
uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */
|
||||
gpio_interrupt_mode_t
|
||||
interruptMode; /*!< Specifies the pin interrupt mode, a value of @ref gpio_interrupt_mode_t. */
|
||||
} gpio_pin_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name GPIO Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes the GPIO peripheral according to the specified
|
||||
* parameters in the initConfig.
|
||||
*
|
||||
* @param base GPIO base pointer.
|
||||
* @param pin Specifies the pin number
|
||||
* @param initConfig pointer to a @ref gpio_pin_config_t structure that
|
||||
* contains the configuration information.
|
||||
*/
|
||||
void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config);
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name GPIO Reads and Write Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Sets the output level of the individual GPIO pin to logic 1 or 0.
|
||||
*
|
||||
* @param base GPIO base pointer.
|
||||
* @param pin GPIO port pin number.
|
||||
* @param output GPIOpin output logic level.
|
||||
* - 0: corresponding pin output low-logic level.
|
||||
* - 1: corresponding pin output high-logic level.
|
||||
*/
|
||||
void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output);
|
||||
|
||||
/*!
|
||||
* @brief Sets the output level of the individual GPIO pin to logic 1 or 0.
|
||||
* @deprecated Do not use this function. It has been superceded by @ref GPIO_PinWrite.
|
||||
*/
|
||||
static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output)
|
||||
{
|
||||
GPIO_PinWrite(base, pin, output);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the output level of the multiple GPIO pins to the logic 1.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.)
|
||||
* @param mask GPIO pin number macro
|
||||
*/
|
||||
static inline void GPIO_PortSet(GPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
#if (defined(FSL_FEATURE_IGPIO_HAS_DR_SET) && (FSL_FEATURE_IGPIO_HAS_DR_SET == 1))
|
||||
base->DR_SET = mask;
|
||||
#else
|
||||
base->DR |= mask;
|
||||
#endif /* FSL_FEATURE_IGPIO_HAS_DR_SET */
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the output level of the multiple GPIO pins to the logic 1.
|
||||
* @deprecated Do not use this function. It has been superceded by @ref GPIO_PortSet.
|
||||
*/
|
||||
static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
GPIO_PortSet(base, mask);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the output level of the multiple GPIO pins to the logic 0.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.)
|
||||
* @param mask GPIO pin number macro
|
||||
*/
|
||||
static inline void GPIO_PortClear(GPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
#if (defined(FSL_FEATURE_IGPIO_HAS_DR_CLEAR) && (FSL_FEATURE_IGPIO_HAS_DR_CLEAR == 1))
|
||||
base->DR_CLEAR = mask;
|
||||
#else
|
||||
base->DR &= ~mask;
|
||||
#endif /* FSL_FEATURE_IGPIO_HAS_DR_CLEAR */
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the output level of the multiple GPIO pins to the logic 0.
|
||||
* @deprecated Do not use this function. It has been superceded by @ref GPIO_PortClear.
|
||||
*/
|
||||
static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
GPIO_PortClear(base, mask);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Reverses the current output logic of the multiple GPIO pins.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.)
|
||||
* @param mask GPIO pin number macro
|
||||
*/
|
||||
static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
#if (defined(FSL_FEATURE_IGPIO_HAS_DR_TOGGLE) && (FSL_FEATURE_IGPIO_HAS_DR_TOGGLE == 1))
|
||||
base->DR_TOGGLE = mask;
|
||||
#endif /* FSL_FEATURE_IGPIO_HAS_DR_TOGGLE */
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Reads the current input value of the GPIO port.
|
||||
*
|
||||
* @param base GPIO base pointer.
|
||||
* @param pin GPIO port pin number.
|
||||
* @retval GPIO port input value.
|
||||
*/
|
||||
static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin)
|
||||
{
|
||||
assert(pin < 32);
|
||||
|
||||
return (((base->DR) >> pin) & 0x1U);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Reads the current input value of the GPIO port.
|
||||
* @deprecated Do not use this function. It has been superceded by @ref GPIO_PinRead.
|
||||
*/
|
||||
static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin)
|
||||
{
|
||||
return GPIO_PinRead(base, pin);
|
||||
}
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name GPIO Reads Pad Status Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Reads the current GPIO pin pad status.
|
||||
*
|
||||
* @param base GPIO base pointer.
|
||||
* @param pin GPIO port pin number.
|
||||
* @retval GPIO pin pad status value.
|
||||
*/
|
||||
static inline uint8_t GPIO_PinReadPadStatus(GPIO_Type *base, uint32_t pin)
|
||||
{
|
||||
assert(pin < 32);
|
||||
|
||||
return (uint8_t)(((base->PSR) >> pin) & 0x1U);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Reads the current GPIO pin pad status.
|
||||
* @deprecated Do not use this function. It has been superceded by @ref GPIO_PinReadPadStatus.
|
||||
*/
|
||||
static inline uint8_t GPIO_ReadPadStatus(GPIO_Type *base, uint32_t pin)
|
||||
{
|
||||
return GPIO_PinReadPadStatus(base, pin);
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Interrupts and flags management functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Sets the current pin interrupt mode.
|
||||
*
|
||||
* @param base GPIO base pointer.
|
||||
* @param pin GPIO port pin number.
|
||||
* @param pininterruptMode pointer to a @ref gpio_interrupt_mode_t structure
|
||||
* that contains the interrupt mode information.
|
||||
*/
|
||||
void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode);
|
||||
|
||||
/*!
|
||||
* @brief Sets the current pin interrupt mode.
|
||||
* @deprecated Do not use this function. It has been superceded by @ref GPIO_PinSetInterruptConfig.
|
||||
*/
|
||||
static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode)
|
||||
{
|
||||
GPIO_PinSetInterruptConfig(base, pin, pinInterruptMode);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enables the specific pin interrupt.
|
||||
*
|
||||
* @param base GPIO base pointer.
|
||||
* @param mask GPIO pin number macro.
|
||||
*/
|
||||
static inline void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
base->IMR |= mask;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enables the specific pin interrupt.
|
||||
*
|
||||
* @param base GPIO base pointer.
|
||||
* @param mask GPIO pin number macro.
|
||||
*/
|
||||
static inline void GPIO_EnableInterrupts(GPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
GPIO_PortEnableInterrupts(base, mask);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disables the specific pin interrupt.
|
||||
*
|
||||
* @param base GPIO base pointer.
|
||||
* @param mask GPIO pin number macro.
|
||||
*/
|
||||
static inline void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
base->IMR &= ~mask;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disables the specific pin interrupt.
|
||||
* @deprecated Do not use this function. It has been superceded by @ref GPIO_PortDisableInterrupts.
|
||||
*/
|
||||
static inline void GPIO_DisableInterrupts(GPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
GPIO_PortDisableInterrupts(base, mask);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Reads individual pin interrupt status.
|
||||
*
|
||||
* @param base GPIO base pointer.
|
||||
* @retval current pin interrupt status flag.
|
||||
*/
|
||||
static inline uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base)
|
||||
{
|
||||
return base->ISR;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Reads individual pin interrupt status.
|
||||
*
|
||||
* @param base GPIO base pointer.
|
||||
* @retval current pin interrupt status flag.
|
||||
*/
|
||||
static inline uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base)
|
||||
{
|
||||
return GPIO_PortGetInterruptFlags(base);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clears pin interrupt flag. Status flags are cleared by
|
||||
* writing a 1 to the corresponding bit position.
|
||||
*
|
||||
* @param base GPIO base pointer.
|
||||
* @param mask GPIO pin number macro.
|
||||
*/
|
||||
static inline void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
base->ISR = mask;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clears pin interrupt flag. Status flags are cleared by
|
||||
* writing a 1 to the corresponding bit position.
|
||||
*
|
||||
* @param base GPIO base pointer.
|
||||
* @param mask GPIO pin number macro.
|
||||
*/
|
||||
static inline void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask)
|
||||
{
|
||||
GPIO_PortClearInterruptFlags(base, mask);
|
||||
}
|
||||
/*@}*/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* _FSL_GPIO_H_*/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,864 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file fsl_lpuart.h
|
||||
* @brief fsl uart drivers
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021.11.11
|
||||
*/
|
||||
|
||||
#ifndef _FSL_LPUART_H_
|
||||
#define _FSL_LPUART_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup lpuart_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief LPUART driver version 2.2.6. */
|
||||
#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 2, 6))
|
||||
/*@}*/
|
||||
|
||||
/*! @brief Error codes for the LPUART driver. */
|
||||
enum _lpuart_status
|
||||
{
|
||||
kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0), /*!< TX busy */
|
||||
kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1), /*!< RX busy */
|
||||
kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2), /*!< LPUART transmitter is idle. */
|
||||
kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3), /*!< LPUART receiver is idle. */
|
||||
kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4), /*!< TX FIFO watermark too large */
|
||||
kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5), /*!< RX FIFO watermark too large */
|
||||
kStatus_LPUART_FlagCannotClearManually = MAKE_STATUS(kStatusGroup_LPUART, 6), /*!< Some flag can't manually clear */
|
||||
kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7), /*!< Error happens on LPUART. */
|
||||
kStatus_LPUART_RxRingBufferOverrun =
|
||||
MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */
|
||||
kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */
|
||||
kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10), /*!< LPUART noise error. */
|
||||
kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11), /*!< LPUART framing error. */
|
||||
kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12), /*!< LPUART parity error. */
|
||||
kStatus_LPUART_BaudrateNotSupport =
|
||||
MAKE_STATUS(kStatusGroup_LPUART, 13), /*!< Baudrate is not support in current clock source */
|
||||
kStatus_LPUART_IdleLineDetected = MAKE_STATUS(kStatusGroup_LPUART, 14), /*!< IDLE flag. */
|
||||
};
|
||||
|
||||
/*! @brief LPUART parity mode. */
|
||||
typedef enum _lpuart_parity_mode
|
||||
{
|
||||
kLPUART_ParityDisabled = 0x0U, /*!< Parity disabled */
|
||||
kLPUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */
|
||||
kLPUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */
|
||||
} lpuart_parity_mode_t;
|
||||
|
||||
/*! @brief LPUART data bits count. */
|
||||
typedef enum _lpuart_data_bits
|
||||
{
|
||||
kLPUART_EightDataBits = 0x0U, /*!< Eight data bit */
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
|
||||
kLPUART_SevenDataBits = 0x1U, /*!< Seven data bit */
|
||||
#endif
|
||||
} lpuart_data_bits_t;
|
||||
|
||||
/*! @brief LPUART stop bit count. */
|
||||
typedef enum _lpuart_stop_bit_count
|
||||
{
|
||||
kLPUART_OneStopBit = 0U, /*!< One stop bit */
|
||||
kLPUART_TwoStopBit = 1U, /*!< Two stop bits */
|
||||
} lpuart_stop_bit_count_t;
|
||||
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
|
||||
/*! @brief LPUART transmit CTS source. */
|
||||
typedef enum _lpuart_transmit_cts_source
|
||||
{
|
||||
kLPUART_CtsSourcePin = 0U, /*!< CTS resource is the LPUART_CTS pin. */
|
||||
kLPUART_CtsSourceMatchResult = 1U, /*!< CTS resource is the match result. */
|
||||
} lpuart_transmit_cts_source_t;
|
||||
|
||||
/*! @brief LPUART transmit CTS configure. */
|
||||
typedef enum _lpuart_transmit_cts_config
|
||||
{
|
||||
kLPUART_CtsSampleAtStart = 0U, /*!< CTS input is sampled at the start of each character. */
|
||||
kLPUART_CtsSampleAtIdle = 1U, /*!< CTS input is sampled when the transmitter is idle */
|
||||
} lpuart_transmit_cts_config_t;
|
||||
#endif
|
||||
|
||||
/*! @brief LPUART idle flag type defines when the receiver starts counting. */
|
||||
typedef enum _lpuart_idle_type_select
|
||||
{
|
||||
kLPUART_IdleTypeStartBit = 0U, /*!< Start counting after a valid start bit. */
|
||||
kLPUART_IdleTypeStopBit = 1U, /*!< Start counting after a stop bit. */
|
||||
} lpuart_idle_type_select_t;
|
||||
|
||||
/*! @brief LPUART idle detected configuration.
|
||||
* This structure defines the number of idle characters that must be received before
|
||||
* the IDLE flag is set.
|
||||
*/
|
||||
typedef enum _lpuart_idle_config
|
||||
{
|
||||
kLPUART_IdleCharacter1 = 0U, /*!< the number of idle characters. */
|
||||
kLPUART_IdleCharacter2 = 1U, /*!< the number of idle characters. */
|
||||
kLPUART_IdleCharacter4 = 2U, /*!< the number of idle characters. */
|
||||
kLPUART_IdleCharacter8 = 3U, /*!< the number of idle characters. */
|
||||
kLPUART_IdleCharacter16 = 4U, /*!< the number of idle characters. */
|
||||
kLPUART_IdleCharacter32 = 5U, /*!< the number of idle characters. */
|
||||
kLPUART_IdleCharacter64 = 6U, /*!< the number of idle characters. */
|
||||
kLPUART_IdleCharacter128 = 7U, /*!< the number of idle characters. */
|
||||
} lpuart_idle_config_t;
|
||||
|
||||
/*!
|
||||
* @brief LPUART interrupt configuration structure, default settings all disabled.
|
||||
*
|
||||
* This structure contains the settings for all LPUART interrupt configurations.
|
||||
*/
|
||||
enum _lpuart_interrupt_enable
|
||||
{
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
|
||||
kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8), /*!< LIN break detect. */
|
||||
#endif
|
||||
kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8), /*!< Receive Active Edge. */
|
||||
kLPUART_TxDataRegEmptyInterruptEnable = (LPUART_CTRL_TIE_MASK), /*!< Transmit data register empty. */
|
||||
kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK), /*!< Transmission complete. */
|
||||
kLPUART_RxDataRegFullInterruptEnable = (LPUART_CTRL_RIE_MASK), /*!< Receiver data register full. */
|
||||
kLPUART_IdleLineInterruptEnable = (LPUART_CTRL_ILIE_MASK), /*!< Idle line. */
|
||||
kLPUART_RxOverrunInterruptEnable = (LPUART_CTRL_ORIE_MASK), /*!< Receiver Overrun. */
|
||||
kLPUART_NoiseErrorInterruptEnable = (LPUART_CTRL_NEIE_MASK), /*!< Noise error flag. */
|
||||
kLPUART_FramingErrorInterruptEnable = (LPUART_CTRL_FEIE_MASK), /*!< Framing error flag. */
|
||||
kLPUART_ParityErrorInterruptEnable = (LPUART_CTRL_PEIE_MASK), /*!< Parity error flag. */
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
|
||||
kLPUART_TxFifoOverflowInterruptEnable = (LPUART_FIFO_TXOFE_MASK >> 8), /*!< Transmit FIFO Overflow. */
|
||||
kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK >> 8), /*!< Receive FIFO Underflow. */
|
||||
#endif
|
||||
};
|
||||
|
||||
/*!
|
||||
* @brief LPUART status flags.
|
||||
*
|
||||
* This provides constants for the LPUART status flags for use in the LPUART functions.
|
||||
*/
|
||||
enum _lpuart_flags
|
||||
{
|
||||
kLPUART_TxDataRegEmptyFlag =
|
||||
(LPUART_STAT_TDRE_MASK), /*!< Transmit data register empty flag, sets when transmit buffer is empty */
|
||||
kLPUART_TransmissionCompleteFlag =
|
||||
(LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete */
|
||||
kLPUART_RxDataRegFullFlag =
|
||||
(LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the receive data buffer is full */
|
||||
kLPUART_IdleLineFlag = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected */
|
||||
kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK), /*!< Receive Overrun, sets when new data is received before data is
|
||||
read from receive register */
|
||||
kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK), /*!< Receive takes 3 samples of each received bit. If any of these
|
||||
samples differ, noise flag sets */
|
||||
kLPUART_FramingErrorFlag =
|
||||
(LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */
|
||||
kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection */
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
|
||||
kLPUART_LinBreakFlag =
|
||||
(int)(LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break char
|
||||
detected and LIN circuit enabled */
|
||||
#endif
|
||||
kLPUART_RxActiveEdgeFlag =
|
||||
(LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active edge detected */
|
||||
kLPUART_RxActiveFlag =
|
||||
(LPUART_STAT_RAF_MASK), /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
|
||||
kLPUART_DataMatch1Flag = LPUART_STAT_MA1F_MASK, /*!< The next character to be read from LPUART_DATA matches MA1*/
|
||||
kLPUART_DataMatch2Flag = LPUART_STAT_MA2F_MASK, /*!< The next character to be read from LPUART_DATA matches MA2*/
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS
|
||||
kLPUART_NoiseErrorInRxDataRegFlag =
|
||||
(LPUART_DATA_NOISY_MASK >> 10), /*!< NOISY bit, sets if noise detected in current data word */
|
||||
kLPUART_ParityErrorInRxDataRegFlag =
|
||||
(LPUART_DATA_PARITYE_MASK >> 10), /*!< PARITYE bit, sets if noise detected in current data word */
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
|
||||
kLPUART_TxFifoEmptyFlag = (LPUART_FIFO_TXEMPT_MASK >> 16), /*!< TXEMPT bit, sets if transmit buffer is empty */
|
||||
kLPUART_RxFifoEmptyFlag = (LPUART_FIFO_RXEMPT_MASK >> 16), /*!< RXEMPT bit, sets if receive buffer is empty */
|
||||
kLPUART_TxFifoOverflowFlag =
|
||||
(LPUART_FIFO_TXOF_MASK >> 16), /*!< TXOF bit, sets if transmit buffer overflow occurred */
|
||||
kLPUART_RxFifoUnderflowFlag =
|
||||
(LPUART_FIFO_RXUF_MASK >> 16), /*!< RXUF bit, sets if receive buffer underflow occurred */
|
||||
#endif
|
||||
};
|
||||
|
||||
/*! @brief LPUART configuration structure. */
|
||||
typedef struct _lpuart_config
|
||||
{
|
||||
uint32_t baudRate_Bps; /*!< LPUART baud rate */
|
||||
lpuart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
|
||||
lpuart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */
|
||||
bool isMsb; /*!< Data bits order, LSB (default), MSB */
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
|
||||
lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
|
||||
uint8_t txFifoWatermark; /*!< TX FIFO watermark */
|
||||
uint8_t rxFifoWatermark; /*!< RX FIFO watermark */
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
|
||||
bool enableRxRTS; /*!< RX RTS enable */
|
||||
bool enableTxCTS; /*!< TX CTS enable */
|
||||
lpuart_transmit_cts_source_t txCtsSource; /*!< TX CTS source */
|
||||
lpuart_transmit_cts_config_t txCtsConfig; /*!< TX CTS configure */
|
||||
#endif
|
||||
lpuart_idle_type_select_t rxIdleType; /*!< RX IDLE type. */
|
||||
lpuart_idle_config_t rxIdleConfig; /*!< RX IDLE configuration. */
|
||||
bool enableTx; /*!< Enable TX */
|
||||
bool enableRx; /*!< Enable RX */
|
||||
} lpuart_config_t;
|
||||
|
||||
/*! @brief LPUART transfer structure. */
|
||||
typedef struct _lpuart_transfer
|
||||
{
|
||||
uint8_t *data; /*!< The buffer of data to be transfer.*/
|
||||
size_t dataSize; /*!< The byte count to be transfer. */
|
||||
} lpuart_transfer_t;
|
||||
|
||||
/* Forward declaration of the handle typedef. */
|
||||
typedef struct _lpuart_handle lpuart_handle_t;
|
||||
|
||||
/*! @brief LPUART transfer callback function. */
|
||||
typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData);
|
||||
|
||||
/*! @brief LPUART handle structure. */
|
||||
struct _lpuart_handle
|
||||
{
|
||||
uint8_t *volatile txData; /*!< Address of remaining data to send. */
|
||||
volatile size_t txDataSize; /*!< Size of the remaining data to send. */
|
||||
size_t txDataSizeAll; /*!< Size of the data to send out. */
|
||||
uint8_t *volatile rxData; /*!< Address of remaining data to receive. */
|
||||
volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */
|
||||
size_t rxDataSizeAll; /*!< Size of the data to receive. */
|
||||
|
||||
uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */
|
||||
size_t rxRingBufferSize; /*!< Size of the ring buffer. */
|
||||
volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */
|
||||
volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */
|
||||
|
||||
lpuart_transfer_callback_t callback; /*!< Callback function. */
|
||||
void *userData; /*!< LPUART callback function parameter.*/
|
||||
|
||||
volatile uint8_t txState; /*!< TX transfer state. */
|
||||
volatile uint8_t rxState; /*!< RX transfer state. */
|
||||
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
|
||||
bool isSevenDataBits; /*!< Seven data bits flag. */
|
||||
#endif
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* _cplusplus */
|
||||
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL
|
||||
|
||||
/*!
|
||||
* @name Software Reset
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Resets the LPUART using software.
|
||||
*
|
||||
* This function resets all internal logic and registers except the Global Register.
|
||||
* Remains set until cleared by software.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
*/
|
||||
static inline void LPUART_SoftwareReset(LPUART_Type *base)
|
||||
{
|
||||
base->GLOBAL |= LPUART_GLOBAL_RST_MASK;
|
||||
base->GLOBAL &= ~LPUART_GLOBAL_RST_MASK;
|
||||
}
|
||||
/* @} */
|
||||
#endif /*FSL_FEATURE_LPUART_HAS_GLOBAL*/
|
||||
|
||||
/*!
|
||||
* @name Initialization and deinitialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock.
|
||||
*
|
||||
* This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function
|
||||
* to configure the configuration structure and get the default configuration.
|
||||
* The example below shows how to use this API to configure the LPUART.
|
||||
* @code
|
||||
* lpuart_config_t lpuartConfig;
|
||||
* lpuartConfig.baudRate_Bps = 115200U;
|
||||
* lpuartConfig.parityMode = kLPUART_ParityDisabled;
|
||||
* lpuartConfig.dataBitsCount = kLPUART_EightDataBits;
|
||||
* lpuartConfig.isMsb = false;
|
||||
* lpuartConfig.stopBitCount = kLPUART_OneStopBit;
|
||||
* lpuartConfig.txFifoWatermark = 0;
|
||||
* lpuartConfig.rxFifoWatermark = 1;
|
||||
* LPUART_Init(LPUART1, &lpuartConfig, 20000000U);
|
||||
* @endcode
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param config Pointer to a user-defined configuration structure.
|
||||
* @param srcClock_Hz LPUART clock source frequency in HZ.
|
||||
* @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source.
|
||||
* @retval kStatus_Success LPUART initialize succeed
|
||||
*/
|
||||
status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes a LPUART instance.
|
||||
*
|
||||
* This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
*/
|
||||
void LPUART_Deinit(LPUART_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Gets the default configuration structure.
|
||||
*
|
||||
* This function initializes the LPUART configuration structure to a default value. The default
|
||||
* values are:
|
||||
* lpuartConfig->baudRate_Bps = 115200U;
|
||||
* lpuartConfig->parityMode = kLPUART_ParityDisabled;
|
||||
* lpuartConfig->dataBitsCount = kLPUART_EightDataBits;
|
||||
* lpuartConfig->isMsb = false;
|
||||
* lpuartConfig->stopBitCount = kLPUART_OneStopBit;
|
||||
* lpuartConfig->txFifoWatermark = 0;
|
||||
* lpuartConfig->rxFifoWatermark = 1;
|
||||
* lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit;
|
||||
* lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1;
|
||||
* lpuartConfig->enableTx = false;
|
||||
* lpuartConfig->enableRx = false;
|
||||
*
|
||||
* @param config Pointer to a configuration structure.
|
||||
*/
|
||||
void LPUART_GetDefaultConfig(lpuart_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Sets the LPUART instance baudrate.
|
||||
*
|
||||
* This function configures the LPUART module baudrate. This function is used to update
|
||||
* the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init.
|
||||
* @code
|
||||
* LPUART_SetBaudRate(LPUART1, 115200U, 20000000U);
|
||||
* @endcode
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param baudRate_Bps LPUART baudrate to be set.
|
||||
* @param srcClock_Hz LPUART clock source frequency in HZ.
|
||||
* @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source.
|
||||
* @retval kStatus_Success Set baudrate succeeded.
|
||||
*/
|
||||
status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Status
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Gets LPUART status flags.
|
||||
*
|
||||
* This function gets all LPUART status flags. The flags are returned as the logical
|
||||
* OR value of the enumerators @ref _lpuart_flags. To check for a specific status,
|
||||
* compare the return value with enumerators in the @ref _lpuart_flags.
|
||||
* For example, to check whether the TX is empty:
|
||||
* @code
|
||||
* if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1))
|
||||
* {
|
||||
* ...
|
||||
* }
|
||||
* @endcode
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @return LPUART status flags which are ORed by the enumerators in the _lpuart_flags.
|
||||
*/
|
||||
uint32_t LPUART_GetStatusFlags(LPUART_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Clears status flags with a provided mask.
|
||||
*
|
||||
* This function clears LPUART status flags with a provided mask. Automatically cleared flags
|
||||
* can't be cleared by this function.
|
||||
* Flags that can only cleared or set by hardware are:
|
||||
* kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag,
|
||||
* kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag,
|
||||
* kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag
|
||||
* Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param mask the status flags to be cleared. The user can use the enumerators in the
|
||||
* _lpuart_status_flag_t to do the OR operation and get the mask.
|
||||
* @return 0 succeed, others failed.
|
||||
* @retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but
|
||||
* it is cleared automatically by hardware.
|
||||
* @retval kStatus_Success Status in the mask are cleared.
|
||||
*/
|
||||
status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enables LPUART interrupts according to a provided mask.
|
||||
*
|
||||
* This function enables the LPUART interrupts according to a provided mask. The mask
|
||||
* is a logical OR of enumeration members. See the @ref _lpuart_interrupt_enable.
|
||||
* This examples shows how to enable TX empty interrupt and RX full interrupt:
|
||||
* @code
|
||||
* LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);
|
||||
* @endcode
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable.
|
||||
*/
|
||||
void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask);
|
||||
|
||||
/*!
|
||||
* @brief Disables LPUART interrupts according to a provided mask.
|
||||
*
|
||||
* This function disables the LPUART interrupts according to a provided mask. The mask
|
||||
* is a logical OR of enumeration members. See @ref _lpuart_interrupt_enable.
|
||||
* This example shows how to disable the TX empty interrupt and RX full interrupt:
|
||||
* @code
|
||||
* LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);
|
||||
* @endcode
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param mask The interrupts to disable. Logical OR of @ref _lpuart_interrupt_enable.
|
||||
*/
|
||||
void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask);
|
||||
|
||||
/*!
|
||||
* @brief Gets enabled LPUART interrupts.
|
||||
*
|
||||
* This function gets the enabled LPUART interrupts. The enabled interrupts are returned
|
||||
* as the logical OR value of the enumerators @ref _lpuart_interrupt_enable. To check
|
||||
* a specific interrupt enable status, compare the return value with enumerators
|
||||
* in @ref _lpuart_interrupt_enable.
|
||||
* For example, to check whether the TX empty interrupt is enabled:
|
||||
* @code
|
||||
* uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1);
|
||||
*
|
||||
* if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)
|
||||
* {
|
||||
* ...
|
||||
* }
|
||||
* @endcode
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @return LPUART interrupt flags which are logical OR of the enumerators in @ref _lpuart_interrupt_enable.
|
||||
*/
|
||||
uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base);
|
||||
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_DMA_ENABLE) && FSL_FEATURE_LPUART_HAS_DMA_ENABLE
|
||||
/*!
|
||||
* @brief Gets the LPUART data register address.
|
||||
*
|
||||
* This function returns the LPUART data register address, which is mainly used by the DMA/eDMA.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @return LPUART data register addresses which are used both by the transmitter and receiver.
|
||||
*/
|
||||
static inline uint32_t LPUART_GetDataRegisterAddress(LPUART_Type *base)
|
||||
{
|
||||
return (uint32_t) & (base->DATA);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enables or disables the LPUART transmitter DMA request.
|
||||
*
|
||||
* This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param enable True to enable, false to disable.
|
||||
*/
|
||||
static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->BAUD |= LPUART_BAUD_TDMAE_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->BAUD &= ~LPUART_BAUD_TDMAE_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enables or disables the LPUART receiver DMA.
|
||||
*
|
||||
* This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param enable True to enable, false to disable.
|
||||
*/
|
||||
static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->BAUD |= LPUART_BAUD_RDMAE_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->BAUD &= ~LPUART_BAUD_RDMAE_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/* @} */
|
||||
#endif /* FSL_FEATURE_LPUART_HAS_DMA_ENABLE */
|
||||
|
||||
/*!
|
||||
* @name Bus Operations
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Get the LPUART instance from peripheral base address.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @return LPUART instance.
|
||||
*/
|
||||
uint32_t LPUART_GetInstance(LPUART_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Enables or disables the LPUART transmitter.
|
||||
*
|
||||
* This function enables or disables the LPUART transmitter.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param enable True to enable, false to disable.
|
||||
*/
|
||||
static inline void LPUART_EnableTx(LPUART_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->CTRL |= LPUART_CTRL_TE_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->CTRL &= ~LPUART_CTRL_TE_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enables or disables the LPUART receiver.
|
||||
*
|
||||
* This function enables or disables the LPUART receiver.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param enable True to enable, false to disable.
|
||||
*/
|
||||
static inline void LPUART_EnableRx(LPUART_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->CTRL |= LPUART_CTRL_RE_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->CTRL &= ~LPUART_CTRL_RE_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Writes to the transmitter register.
|
||||
*
|
||||
* This function writes data to the transmitter register directly. The upper layer must
|
||||
* ensure that the TX register is empty or that the TX FIFO has room before calling this function.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param data Data write to the TX register.
|
||||
*/
|
||||
static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data)
|
||||
{
|
||||
base->DATA = data;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Reads the receiver register.
|
||||
*
|
||||
* This function reads data from the receiver register directly. The upper layer must
|
||||
* ensure that the receiver register is full or that the RX FIFO has data before calling this function.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @return Data read from data register.
|
||||
*/
|
||||
static inline uint8_t LPUART_ReadByte(LPUART_Type *base)
|
||||
{
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
|
||||
uint32_t ctrl = base->CTRL;
|
||||
bool isSevenDataBits =
|
||||
((ctrl & LPUART_CTRL_M7_MASK) ||
|
||||
((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
|
||||
|
||||
if (isSevenDataBits)
|
||||
{
|
||||
return (base->DATA & 0x7F);
|
||||
}
|
||||
else
|
||||
{
|
||||
return base->DATA;
|
||||
}
|
||||
#else
|
||||
return base->DATA;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Writes to the transmitter register using a blocking method.
|
||||
*
|
||||
* This function polls the transmitter register, waits for the register to be empty or for TX FIFO to have
|
||||
* room, and writes data to the transmitter buffer.
|
||||
*
|
||||
* @note This function does not check whether all data has been sent out to the bus.
|
||||
* Before disabling the transmitter, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is
|
||||
* finished.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param data Start address of the data to write.
|
||||
* @param length Size of the data to write.
|
||||
*/
|
||||
void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length);
|
||||
|
||||
/*!
|
||||
* @brief Reads the receiver data register using a blocking method.
|
||||
*
|
||||
* This function polls the receiver register, waits for the receiver register full or receiver FIFO
|
||||
* has data, and reads data from the TX register.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param data Start address of the buffer to store the received data.
|
||||
* @param length Size of the buffer.
|
||||
* @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data.
|
||||
* @retval kStatus_LPUART_NoiseError Noise error happened while receiving data.
|
||||
* @retval kStatus_LPUART_FramingError Framing error happened while receiving data.
|
||||
* @retval kStatus_LPUART_ParityError Parity error happened while receiving data.
|
||||
* @retval kStatus_Success Successfully received all data.
|
||||
*/
|
||||
status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Transactional
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes the LPUART handle.
|
||||
*
|
||||
* This function initializes the LPUART handle, which can be used for other LPUART
|
||||
* transactional APIs. Usually, for a specified LPUART instance,
|
||||
* call this API once to get the initialized handle.
|
||||
*
|
||||
* The LPUART driver supports the "background" receiving, which means that user can set up
|
||||
* an RX ring buffer optionally. Data received is stored into the ring buffer even when the
|
||||
* user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received
|
||||
* in the ring buffer, the user can get the received data from the ring buffer directly.
|
||||
* The ring buffer is disabled if passing NULL as @p ringBuffer.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param handle LPUART handle pointer.
|
||||
* @param callback Callback function.
|
||||
* @param userData User data.
|
||||
*/
|
||||
void LPUART_TransferCreateHandle(LPUART_Type *base,
|
||||
lpuart_handle_t *handle,
|
||||
lpuart_transfer_callback_t callback,
|
||||
void *userData);
|
||||
/*!
|
||||
* @brief Transmits a buffer of data using the interrupt method.
|
||||
*
|
||||
* This function send data using an interrupt method. This is a non-blocking function, which
|
||||
* returns directly without waiting for all data written to the transmitter register. When
|
||||
* all data is written to the TX register in the ISR, the LPUART driver calls the callback
|
||||
* function and passes the @ref kStatus_LPUART_TxIdle as status parameter.
|
||||
*
|
||||
* @note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written
|
||||
* to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX,
|
||||
* check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param handle LPUART handle pointer.
|
||||
* @param xfer LPUART transfer structure, see #lpuart_transfer_t.
|
||||
* @retval kStatus_Success Successfully start the data transmission.
|
||||
* @retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register.
|
||||
* @retval kStatus_InvalidArgument Invalid argument.
|
||||
*/
|
||||
status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer);
|
||||
|
||||
/*!
|
||||
* @brief Sets up the RX ring buffer.
|
||||
*
|
||||
* This function sets up the RX ring buffer to a specific UART handle.
|
||||
*
|
||||
* When the RX ring buffer is used, data received is stored into the ring buffer even when
|
||||
* the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received
|
||||
* in the ring buffer, the user can get the received data from the ring buffer directly.
|
||||
*
|
||||
* @note When using RX ring buffer, one byte is reserved for internal use. In other
|
||||
* words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param handle LPUART handle pointer.
|
||||
* @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
|
||||
* @param ringBufferSize size of the ring buffer.
|
||||
*/
|
||||
void LPUART_TransferStartRingBuffer(LPUART_Type *base,
|
||||
lpuart_handle_t *handle,
|
||||
uint8_t *ringBuffer,
|
||||
size_t ringBufferSize);
|
||||
|
||||
/*!
|
||||
* @brief Aborts the background transfer and uninstalls the ring buffer.
|
||||
*
|
||||
* This function aborts the background transfer and uninstalls the ring buffer.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param handle LPUART handle pointer.
|
||||
*/
|
||||
void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle);
|
||||
|
||||
/*!
|
||||
* @brief Get the length of received data in RX ring buffer.
|
||||
*
|
||||
* @param handle LPUART handle pointer.
|
||||
* @return Length of received data in RX ring buffer.
|
||||
*/
|
||||
size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle);
|
||||
|
||||
/*!
|
||||
* @brief Aborts the interrupt-driven data transmit.
|
||||
*
|
||||
* This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
|
||||
* how many bytes are not sent out.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param handle LPUART handle pointer.
|
||||
*/
|
||||
void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle);
|
||||
|
||||
/*!
|
||||
* @brief Gets the number of bytes that have been written to the LPUART transmitter register.
|
||||
*
|
||||
* This function gets the number of bytes that have been written to LPUART TX
|
||||
* register by an interrupt method.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param handle LPUART handle pointer.
|
||||
* @param count Send bytes count.
|
||||
* @retval kStatus_NoTransferInProgress No send in progress.
|
||||
* @retval kStatus_InvalidArgument Parameter is invalid.
|
||||
* @retval kStatus_Success Get successfully through the parameter \p count;
|
||||
*/
|
||||
status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count);
|
||||
|
||||
/*!
|
||||
* @brief Receives a buffer of data using the interrupt method.
|
||||
*
|
||||
* This function receives data using an interrupt method. This is a non-blocking function
|
||||
* which returns without waiting to ensure that all data are received.
|
||||
* If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
|
||||
* the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.
|
||||
* After copying, if the data in the ring buffer is not enough for read, the receive
|
||||
* request is saved by the LPUART driver. When the new data arrives, the receive request
|
||||
* is serviced first. When all data is received, the LPUART driver notifies the upper layer
|
||||
* through a callback function and passes a status parameter @ref kStatus_UART_RxIdle.
|
||||
* For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer.
|
||||
* The 5 bytes are copied to xfer->data, which returns with the
|
||||
* parameter @p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is
|
||||
* saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer.
|
||||
* If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
|
||||
* to receive data to xfer->data. When all data is received, the upper layer is notified.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param handle LPUART handle pointer.
|
||||
* @param xfer LPUART transfer structure, see #uart_transfer_t.
|
||||
* @param receivedBytes Bytes received from the ring buffer directly.
|
||||
* @retval kStatus_Success Successfully queue the transfer into the transmit queue.
|
||||
* @retval kStatus_LPUART_RxBusy Previous receive request is not finished.
|
||||
* @retval kStatus_InvalidArgument Invalid argument.
|
||||
*/
|
||||
status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
|
||||
lpuart_handle_t *handle,
|
||||
lpuart_transfer_t *xfer,
|
||||
size_t *receivedBytes);
|
||||
|
||||
/*!
|
||||
* @brief Aborts the interrupt-driven data receiving.
|
||||
*
|
||||
* This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
|
||||
* how many bytes not received yet.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param handle LPUART handle pointer.
|
||||
*/
|
||||
void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle);
|
||||
|
||||
/*!
|
||||
* @brief Gets the number of bytes that have been received.
|
||||
*
|
||||
* This function gets the number of bytes that have been received.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param handle LPUART handle pointer.
|
||||
* @param count Receive bytes count.
|
||||
* @retval kStatus_NoTransferInProgress No receive in progress.
|
||||
* @retval kStatus_InvalidArgument Parameter is invalid.
|
||||
* @retval kStatus_Success Get successfully through the parameter \p count;
|
||||
*/
|
||||
status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count);
|
||||
|
||||
/*!
|
||||
* @brief LPUART IRQ handle function.
|
||||
*
|
||||
* This function handles the LPUART transmit and receive IRQ request.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param handle LPUART handle pointer.
|
||||
*/
|
||||
void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle);
|
||||
|
||||
/*!
|
||||
* @brief LPUART Error IRQ handle function.
|
||||
*
|
||||
* This function handles the LPUART error IRQ request.
|
||||
*
|
||||
* @param base LPUART peripheral base address.
|
||||
* @param handle LPUART handle pointer.
|
||||
*/
|
||||
void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle);
|
||||
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_LPUART_H_ */
|
||||
|
|
@ -0,0 +1,830 @@
|
|||
/*
|
||||
* Copyright 2017-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _FSL_SEMC_H_
|
||||
#define _FSL_SEMC_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup semc
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief SEMC driver version 2.0.4. */
|
||||
#define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
|
||||
/*@}*/
|
||||
|
||||
/*! @brief SEMC status. */
|
||||
enum _semc_status
|
||||
{
|
||||
kStatus_SEMC_InvalidDeviceType = MAKE_STATUS(kStatusGroup_SEMC, 0),
|
||||
kStatus_SEMC_IpCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 1),
|
||||
kStatus_SEMC_AxiCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 2),
|
||||
kStatus_SEMC_InvalidMemorySize = MAKE_STATUS(kStatusGroup_SEMC, 3),
|
||||
kStatus_SEMC_InvalidIpcmdDataSize = MAKE_STATUS(kStatusGroup_SEMC, 4),
|
||||
kStatus_SEMC_InvalidAddressPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 5),
|
||||
kStatus_SEMC_InvalidDataPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 6),
|
||||
kStatus_SEMC_InvalidSwPinmuxSelection = MAKE_STATUS(kStatusGroup_SEMC, 7),
|
||||
kStatus_SEMC_InvalidBurstLength = MAKE_STATUS(kStatusGroup_SEMC, 8),
|
||||
kStatus_SEMC_InvalidColumnAddressBitWidth = MAKE_STATUS(kStatusGroup_SEMC, 9),
|
||||
kStatus_SEMC_InvalidBaseAddress = MAKE_STATUS(kStatusGroup_SEMC, 10),
|
||||
kStatus_SEMC_InvalidTimerSetting = MAKE_STATUS(kStatusGroup_SEMC, 11),
|
||||
};
|
||||
|
||||
/*! @brief SEMC memory device type. */
|
||||
typedef enum _semc_mem_type
|
||||
{
|
||||
kSEMC_MemType_SDRAM = 0, /*!< SDRAM */
|
||||
kSEMC_MemType_SRAM, /*!< SRAM */
|
||||
kSEMC_MemType_NOR, /*!< NOR */
|
||||
kSEMC_MemType_NAND, /*!< NAND */
|
||||
kSEMC_MemType_8080 /*!< 8080. */
|
||||
} semc_mem_type_t;
|
||||
|
||||
/*! @brief SEMC WAIT/RDY polarity. */
|
||||
typedef enum _semc_waitready_polarity
|
||||
{
|
||||
kSEMC_LowActive = 0, /*!< Low active. */
|
||||
kSEMC_HighActive, /*!< High active. */
|
||||
} semc_waitready_polarity_t;
|
||||
|
||||
/*! @brief SEMC SDRAM Chip selection . */
|
||||
typedef enum _semc_sdram_cs
|
||||
{
|
||||
kSEMC_SDRAM_CS0 = 0, /*!< SEMC SDRAM CS0. */
|
||||
kSEMC_SDRAM_CS1, /*!< SEMC SDRAM CS1. */
|
||||
kSEMC_SDRAM_CS2, /*!< SEMC SDRAM CS2. */
|
||||
kSEMC_SDRAM_CS3 /*!< SEMC SDRAM CS3. */
|
||||
} semc_sdram_cs_t;
|
||||
|
||||
/*! @brief SEMC NAND device type. */
|
||||
typedef enum _semc_nand_access_type
|
||||
{
|
||||
kSEMC_NAND_ACCESS_BY_AXI = 0,
|
||||
kSEMC_NAND_ACCESS_BY_IPCMD,
|
||||
} semc_nand_access_type_t;
|
||||
|
||||
/*! @brief SEMC interrupts . */
|
||||
typedef enum _semc_interrupt_enable
|
||||
{
|
||||
kSEMC_IPCmdDoneInterrupt = SEMC_INTEN_IPCMDDONEEN_MASK, /*!< Ip command done interrupt. */
|
||||
kSEMC_IPCmdErrInterrupt = SEMC_INTEN_IPCMDERREN_MASK, /*!< Ip command error interrupt. */
|
||||
kSEMC_AXICmdErrInterrupt = SEMC_INTEN_AXICMDERREN_MASK, /*!< AXI command error interrupt. */
|
||||
kSEMC_AXIBusErrInterrupt = SEMC_INTEN_AXIBUSERREN_MASK /*!< AXI bus error interrupt. */
|
||||
} semc_interrupt_enable_t;
|
||||
|
||||
/*! @brief SEMC IP command data size in bytes. */
|
||||
typedef enum _semc_ipcmd_datasize
|
||||
{
|
||||
kSEMC_IPcmdDataSize_1bytes = 1, /*!< The IP command data size 1 byte. */
|
||||
kSEMC_IPcmdDataSize_2bytes, /*!< The IP command data size 2 byte. */
|
||||
kSEMC_IPcmdDataSize_3bytes, /*!< The IP command data size 3 byte. */
|
||||
kSEMC_IPcmdDataSize_4bytes /*!< The IP command data size 4 byte. */
|
||||
} semc_ipcmd_datasize_t;
|
||||
|
||||
/*! @brief SEMC auto-refresh timing. */
|
||||
typedef enum _semc_refresh_time
|
||||
{
|
||||
kSEMC_RefreshThreeClocks = 0x0U, /*!< The refresh timing with three bus clocks. */
|
||||
kSEMC_RefreshSixClocks, /*!< The refresh timing with six bus clocks. */
|
||||
kSEMC_RefreshNineClocks /*!< The refresh timing with nine bus clocks. */
|
||||
} semc_refresh_time_t;
|
||||
|
||||
/*! @brief CAS latency */
|
||||
typedef enum _semc_caslatency
|
||||
{
|
||||
kSEMC_LatencyOne = 1, /*!< Latency 1. */
|
||||
kSEMC_LatencyTwo, /*!< Latency 2. */
|
||||
kSEMC_LatencyThree, /*!< Latency 3. */
|
||||
} semc_caslatency_t;
|
||||
|
||||
/*! @brief SEMC sdram column address bit number. */
|
||||
typedef enum _semc_sdram_column_bit_num
|
||||
{
|
||||
kSEMC_SdramColunm_12bit = 0x0U, /*!< 12 bit. */
|
||||
kSEMC_SdramColunm_11bit, /*!< 11 bit. */
|
||||
kSEMC_SdramColunm_10bit, /*!< 10 bit. */
|
||||
kSEMC_SdramColunm_9bit, /*!< 9 bit. */
|
||||
} semc_sdram_column_bit_num_t;
|
||||
|
||||
/*! @brief SEMC sdram burst length. */
|
||||
typedef enum _semc_sdram_burst_len
|
||||
{
|
||||
kSEMC_Sdram_BurstLen1 = 0, /*!< Burst length 1*/
|
||||
kSEMC_Sdram_BurstLen2, /*!< Burst length 2*/
|
||||
kSEMC_Sdram_BurstLen4, /*!< Burst length 4*/
|
||||
kSEMC_Sdram_BurstLen8 /*!< Burst length 8*/
|
||||
} sem_sdram_burst_len_t;
|
||||
|
||||
/*! @brief SEMC nand column address bit number. */
|
||||
typedef enum _semc_nand_column_bit_num
|
||||
{
|
||||
kSEMC_NandColum_16bit = 0x0U, /*!< 16 bit. */
|
||||
kSEMC_NandColum_15bit, /*!< 15 bit. */
|
||||
kSEMC_NandColum_14bit, /*!< 14 bit. */
|
||||
kSEMC_NandColum_13bit, /*!< 13 bit. */
|
||||
kSEMC_NandColum_12bit, /*!< 12 bit. */
|
||||
kSEMC_NandColum_11bit, /*!< 11 bit. */
|
||||
kSEMC_NandColum_10bit, /*!< 10 bit. */
|
||||
kSEMC_NandColum_9bit, /*!< 9 bit. */
|
||||
} semc_nand_column_bit_num_t;
|
||||
|
||||
/*! @brief SEMC nand burst length. */
|
||||
typedef enum _semc_nand_burst_len
|
||||
{
|
||||
kSEMC_Nand_BurstLen1 = 0, /*!< Burst length 1*/
|
||||
kSEMC_Nand_BurstLen2, /*!< Burst length 2*/
|
||||
kSEMC_Nand_BurstLen4, /*!< Burst length 4*/
|
||||
kSEMC_Nand_BurstLen8, /*!< Burst length 8*/
|
||||
kSEMC_Nand_BurstLen16, /*!< Burst length 16*/
|
||||
kSEMC_Nand_BurstLen32, /*!< Burst length 32*/
|
||||
kSEMC_Nand_BurstLen64 /*!< Burst length 64*/
|
||||
} sem_nand_burst_len_t;
|
||||
|
||||
/*! @brief SEMC nor/sram column address bit number. */
|
||||
typedef enum _semc_norsram_column_bit_num
|
||||
{
|
||||
kSEMC_NorColum_12bit = 0x0U, /*!< 12 bit. */
|
||||
kSEMC_NorColum_11bit, /*!< 11 bit. */
|
||||
kSEMC_NorColum_10bit, /*!< 10 bit. */
|
||||
kSEMC_NorColum_9bit, /*!< 9 bit. */
|
||||
kSEMC_NorColum_8bit, /*!< 8 bit. */
|
||||
kSEMC_NorColum_7bit, /*!< 7 bit. */
|
||||
kSEMC_NorColum_6bit, /*!< 6 bit. */
|
||||
kSEMC_NorColum_5bit, /*!< 5 bit. */
|
||||
kSEMC_NorColum_4bit, /*!< 4 bit. */
|
||||
kSEMC_NorColum_3bit, /*!< 3 bit. */
|
||||
kSEMC_NorColum_2bit /*!< 2 bit. */
|
||||
} semc_norsram_column_bit_num_t;
|
||||
|
||||
/*! @brief SEMC nor/sram burst length. */
|
||||
typedef enum _semc_norsram_burst_len
|
||||
{
|
||||
kSEMC_Nor_BurstLen1 = 0, /*!< Burst length 1*/
|
||||
kSEMC_Nor_BurstLen2, /*!< Burst length 2*/
|
||||
kSEMC_Nor_BurstLen4, /*!< Burst length 4*/
|
||||
kSEMC_Nor_BurstLen8, /*!< Burst length 8*/
|
||||
kSEMC_Nor_BurstLen16, /*!< Burst length 16*/
|
||||
kSEMC_Nor_BurstLen32, /*!< Burst length 32*/
|
||||
kSEMC_Nor_BurstLen64 /*!< Burst length 64*/
|
||||
} sem_norsram_burst_len_t;
|
||||
|
||||
/*! @brief SEMC dbi column address bit number. */
|
||||
typedef enum _semc_dbi_column_bit_num
|
||||
{
|
||||
kSEMC_Dbi_Colum_12bit = 0x0U, /*!< 12 bit. */
|
||||
kSEMC_Dbi_Colum_11bit, /*!< 11 bit. */
|
||||
kSEMC_Dbi_Colum_10bit, /*!< 10 bit. */
|
||||
kSEMC_Dbi_Colum_9bit, /*!< 9 bit. */
|
||||
kSEMC_Dbi_Colum_8bit, /*!< 8 bit. */
|
||||
kSEMC_Dbi_Colum_7bit, /*!< 7 bit. */
|
||||
kSEMC_Dbi_Colum_6bit, /*!< 6 bit. */
|
||||
kSEMC_Dbi_Colum_5bit, /*!< 5 bit. */
|
||||
kSEMC_Dbi_Colum_4bit, /*!< 4 bit. */
|
||||
kSEMC_Dbi_Colum_3bit, /*!< 3 bit. */
|
||||
kSEMC_Dbi_Colum_2bit /*!< 2 bit. */
|
||||
} semc_dbi_column_bit_num_t;
|
||||
|
||||
/*! @brief SEMC dbi burst length. */
|
||||
typedef enum _semc_dbi_burst_len
|
||||
{
|
||||
kSEMC_Dbi_BurstLen1 = 0, /*!< Burst length 1*/
|
||||
kSEMC_Dbi_BurstLen2, /*!< Burst length 2*/
|
||||
kSEMC_Dbi_Dbi_BurstLen4, /*!< Burst length 4*/
|
||||
kSEMC_Dbi_BurstLen8, /*!< Burst length 8*/
|
||||
kSEMC_Dbi_BurstLen16, /*!< Burst length 16*/
|
||||
kSEMC_Dbi_BurstLen32, /*!< Burst length 32*/
|
||||
kSEMC_Dbi_BurstLen64 /*!< Burst length 64*/
|
||||
} sem_dbi_burst_len_t;
|
||||
|
||||
/*! @brief SEMC IOMUXC. */
|
||||
typedef enum _semc_iomux_pin
|
||||
{
|
||||
kSEMC_MUXA8 = SEMC_IOCR_MUX_A8_SHIFT, /*!< MUX A8 pin. */
|
||||
kSEMC_MUXCSX0 = SEMC_IOCR_MUX_CSX0_SHIFT, /*!< MUX CSX0 pin */
|
||||
kSEMC_MUXCSX1 = SEMC_IOCR_MUX_CSX1_SHIFT, /*!< MUX CSX1 Pin.*/
|
||||
kSEMC_MUXCSX2 = SEMC_IOCR_MUX_CSX2_SHIFT, /*!< MUX CSX2 Pin. */
|
||||
kSEMC_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */
|
||||
kSEMC_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */
|
||||
} semc_iomux_pin;
|
||||
|
||||
/*! @brief SEMC NOR/PSRAM Address bit 27 A27. */
|
||||
typedef enum _semc_iomux_nora27_pin
|
||||
{
|
||||
kSEMC_MORA27_NONE = 0, /*!< No NOR/SRAM A27 pin. */
|
||||
kSEMC_NORA27_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */
|
||||
kSEMC_NORA27_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */
|
||||
} semc_iomux_nora27_pin;
|
||||
|
||||
/*! @brief SEMC port size. */
|
||||
typedef enum _semc_port_size
|
||||
{
|
||||
kSEMC_PortSize8Bit = 0, /*!< 8-Bit port size. */
|
||||
kSEMC_PortSize16Bit /*!< 16-Bit port size. */
|
||||
} smec_port_size_t;
|
||||
|
||||
/*! @brief SEMC address mode. */
|
||||
typedef enum _semc_addr_mode
|
||||
{
|
||||
kSEMC_AddrDataMux = 0, /*!< SEMC address/data mux mode. */
|
||||
kSEMC_AdvAddrdataMux, /*!< Advanced address/data mux mode. */
|
||||
kSEMC_AddrDataNonMux /*!< Address/data non-mux mode. */
|
||||
} semc_addr_mode_t;
|
||||
|
||||
/*! @brief SEMC DQS read strobe mode. */
|
||||
typedef enum _semc_dqs_mode
|
||||
{
|
||||
kSEMC_Loopbackinternal = 0, /*!< Dummy read strobe loopbacked internally. */
|
||||
kSEMC_Loopbackdqspad, /*!< Dummy read strobe loopbacked from DQS pad. */
|
||||
} semc_dqs_mode_t;
|
||||
|
||||
/*! @brief SEMC ADV signal active polarity. */
|
||||
typedef enum _semc_adv_polarity
|
||||
{
|
||||
kSEMC_AdvActiveLow = 0, /*!< Adv active low. */
|
||||
kSEMC_AdvActivehigh, /*!< Adv active low. */
|
||||
} semc_adv_polarity_t;
|
||||
|
||||
/*! @brief SEMC RDY signal active polarity. */
|
||||
typedef enum _semc_rdy_polarity
|
||||
{
|
||||
kSEMC_RdyActiveLow = 0, /*!< Adv active low. */
|
||||
kSEMC_RdyActivehigh, /*!< Adv active low. */
|
||||
} semc_rdy_polarity_t;
|
||||
|
||||
/*! @brief SEMC IP command for NAND: address mode. */
|
||||
typedef enum _semc_ipcmd_nand_addrmode
|
||||
{
|
||||
kSEMC_NANDAM_ColumnRow = 0x0U, /*!< Address mode: column and row address(5Byte-CA0/CA1/RA0/RA1/RA2). */
|
||||
kSEMC_NANDAM_ColumnCA0, /*!< Address mode: column address only(1 Byte-CA0). */
|
||||
kSEMC_NANDAM_ColumnCA0CA1, /*!< Address mode: column address only(2 Byte-CA0/CA1). */
|
||||
kSEMC_NANDAM_RawRA0, /*!< Address mode: row address only(1 Byte-RA0). */
|
||||
kSEMC_NANDAM_RawRA0RA1, /*!< Address mode: row address only(2 Byte-RA0/RA1). */
|
||||
kSEMC_NANDAM_RawRA0RA1RA2 /*!< Address mode: row address only(3 Byte-RA0). */
|
||||
} semc_ipcmd_nand_addrmode_t;
|
||||
|
||||
/*! @brief SEMC IP command for NAND： command mode. */
|
||||
typedef enum _semc_ipcmd_nand_cmdmode
|
||||
{
|
||||
kSEMC_NANDCM_Command = 0x2U, /*!< command. */
|
||||
kSEMC_NANDCM_CommandHold, /*!< Command hold. */
|
||||
kSEMC_NANDCM_CommandAddress, /*!< Command address. */
|
||||
kSEMC_NANDCM_CommandAddressHold, /*!< Command address hold. */
|
||||
kSEMC_NANDCM_CommandAddressRead, /*!< Command address read. */
|
||||
kSEMC_NANDCM_CommandAddressWrite, /*!< Command address write. */
|
||||
kSEMC_NANDCM_CommandRead, /*!< Command read. */
|
||||
kSEMC_NANDCM_CommandWrite, /*!< Command write. */
|
||||
kSEMC_NANDCM_Read, /*!< Read. */
|
||||
kSEMC_NANDCM_Write /*!< Write. */
|
||||
} semc_ipcmd_nand_cmdmode_t;
|
||||
|
||||
/*! @brief SEMC NAND address option. */
|
||||
typedef enum _semc_nand_address_option
|
||||
{
|
||||
kSEMC_NandAddrOption_5byte_CA2RA3 = 0U, /*!< CA0+CA1+RA0+RA1+RA2 */
|
||||
kSEMC_NandAddrOption_4byte_CA2RA2 = 2U, /*!< CA0+CA1+RA0+RA1 */
|
||||
kSEMC_NandAddrOption_3byte_CA2RA1 = 4U, /*!< CA0+CA1+RA0 */
|
||||
kSEMC_NandAddrOption_4byte_CA1RA3 = 1U, /*!< CA0+RA0+RA1+RA2 */
|
||||
kSEMC_NandAddrOption_3byte_CA1RA2 = 3U, /*!< CA0+RA0+RA1 */
|
||||
kSEMC_NandAddrOption_2byte_CA1RA1 = 7U, /*!< CA0+RA0 */
|
||||
} semc_nand_address_option_t;
|
||||
|
||||
/*! @brief SEMC IP command for NOR. */
|
||||
typedef enum _semc_ipcmd_nor_dbi
|
||||
{
|
||||
kSEMC_NORDBICM_Read = 0x2U, /*!< NOR read. */
|
||||
kSEMC_NORDBICM_Write /*!< NOR write. */
|
||||
} semc_ipcmd_nor_dbi_t;
|
||||
|
||||
/*! @brief SEMC IP command for SRAM. */
|
||||
typedef enum _semc_ipcmd_sram
|
||||
{
|
||||
kSEMC_SRAMCM_ArrayRead = 0x2U, /*!< SRAM memory array read. */
|
||||
kSEMC_SRAMCM_ArrayWrite, /*!< SRAM memory array write. */
|
||||
kSEMC_SRAMCM_RegRead, /*!< SRAM memory register read. */
|
||||
kSEMC_SRAMCM_RegWrite /*!< SRAM memory register write. */
|
||||
} semc_ipcmd_sram_t;
|
||||
|
||||
/*! @brief SEMC IP command for SDARM. */
|
||||
typedef enum _semc_ipcmd_sdram
|
||||
{
|
||||
kSEMC_SDRAMCM_Read = 0x8U, /*!< SDRAM memory read. */
|
||||
kSEMC_SDRAMCM_Write, /*!< SDRAM memory write. */
|
||||
kSEMC_SDRAMCM_Modeset, /*!< SDRAM MODE SET. */
|
||||
kSEMC_SDRAMCM_Active, /*!< SDRAM active. */
|
||||
kSEMC_SDRAMCM_AutoRefresh, /*!< SDRAM auto-refresh. */
|
||||
kSEMC_SDRAMCM_SelfRefresh, /*!< SDRAM self-refresh. */
|
||||
kSEMC_SDRAMCM_Precharge, /*!< SDRAM precharge. */
|
||||
kSEMC_SDRAMCM_Prechargeall /*!< SDRAM precharge all. */
|
||||
} semc_ipcmd_sdram_t;
|
||||
|
||||
/*! @brief SEMC SDRAM configuration structure.
|
||||
*
|
||||
* 1. The memory size in the configuration is in the unit of KB. So memsize_kbytes
|
||||
* should be set as 2^2, 2^3, 2^4 .etc which is base 2KB exponential function.
|
||||
* Take refer to BR0~BR3 register in RM for details.
|
||||
* 2. The prescalePeriod_N16Cycle is in unit of 16 clock cycle. It is a exception for prescaleTimer_n16cycle = 0,
|
||||
* it means the prescaler timer period is 256 * 16 clock cycles. For precalerIf precalerTimer_n16cycle not equal to 0,
|
||||
* The prescaler timer period is prescalePeriod_N16Cycle * 16 clock cycles.
|
||||
* idleTimeout_NprescalePeriod, refreshUrgThreshold_NprescalePeriod, refreshPeriod_NprescalePeriod are
|
||||
* similar to prescalePeriod_N16Cycle.
|
||||
*
|
||||
*/
|
||||
typedef struct _semc_sdram_config
|
||||
{
|
||||
semc_iomux_pin csxPinMux; /*!< CS pin mux. The kSEMC_MUXA8 is not valid in sdram pin mux setting. */
|
||||
uint32_t address; /*!< The base address. */
|
||||
uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */
|
||||
smec_port_size_t portSize; /*!< Port size. */
|
||||
sem_sdram_burst_len_t burstLen; /*!< Burst length. */
|
||||
semc_sdram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
|
||||
semc_caslatency_t casLatency; /*!< CAS latency. */
|
||||
uint8_t tPrecharge2Act_Ns; /*!< Precharge to active wait time in unit of nanosecond. */
|
||||
uint8_t tAct2ReadWrite_Ns; /*!< Act to read/write wait time in unit of nanosecond. */
|
||||
uint8_t tRefreshRecovery_Ns; /*!< Refresh recovery time in unit of nanosecond. */
|
||||
uint8_t tWriteRecovery_Ns; /*!< write recovery time in unit of nanosecond. */
|
||||
uint8_t tCkeOff_Ns; /*!< CKE off minimum time in unit of nanosecond. */
|
||||
uint8_t tAct2Prechage_Ns; /*!< Active to precharge in unit of nanosecond. */
|
||||
uint8_t tSelfRefRecovery_Ns; /*!< Self refresh recovery time in unit of nanosecond. */
|
||||
uint8_t tRefresh2Refresh_Ns; /*!< Refresh to refresh wait time in unit of nanosecond. */
|
||||
uint8_t tAct2Act_Ns; /*!< Active to active wait time in unit of nanosecond. */
|
||||
uint32_t tPrescalePeriod_Ns; /*!< Prescaler timer period should not be larger than 256 * 16 * clock cycle. */
|
||||
uint32_t tIdleTimeout_Ns; /*!< Idle timeout in unit of prescale time period. */
|
||||
uint32_t refreshPeriod_nsPerRow; /*!< Refresh timer period like 64ms * 1000000/8192 . */
|
||||
uint32_t refreshUrgThreshold; /*!< Refresh urgent threshold. */
|
||||
uint8_t refreshBurstLen; /*!< Refresh burst length. */
|
||||
} semc_sdram_config_t;
|
||||
|
||||
/*! @brief SEMC NAND device timing configuration structure. */
|
||||
typedef struct _semc_nand_timing_config
|
||||
{
|
||||
uint8_t tCeSetup_Ns; /*!< CE setup time: tCS. */
|
||||
uint8_t tCeHold_Ns; /*!< CE hold time: tCH. */
|
||||
uint8_t tCeInterval_Ns; /*!< CE interval time:tCEITV. */
|
||||
uint8_t tWeLow_Ns; /*!< WE low time: tWP. */
|
||||
uint8_t tWeHigh_Ns; /*!< WE high time: tWH. */
|
||||
uint8_t tReLow_Ns; /*!< RE low time: tRP. */
|
||||
uint8_t tReHigh_Ns; /*!< RE high time: tREH. */
|
||||
uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode: tTA. */
|
||||
uint8_t tWehigh2Relow_Ns; /*!< WE# high to RE# wait time: tWHR. */
|
||||
uint8_t tRehigh2Welow_Ns; /*!< RE# high to WE# low wait time: tRHW. */
|
||||
uint8_t tAle2WriteStart_Ns; /*!< ALE to write start wait time: tADL. */
|
||||
uint8_t tReady2Relow_Ns; /*!< Ready to RE# low min wait time: tRR. */
|
||||
uint8_t tWehigh2Busy_Ns; /*!< WE# high to busy wait time: tWB. */
|
||||
} semc_nand_timing_config_t;
|
||||
|
||||
/*! @brief SEMC NAND configuration structure. */
|
||||
typedef struct _semc_nand_config
|
||||
{
|
||||
semc_iomux_pin cePinMux; /*!< The CE pin mux setting. The kSEMC_MUXRDY is not valid for CE pin setting. */
|
||||
uint32_t axiAddress; /*!< The base address for AXI nand. */
|
||||
uint32_t axiMemsize_kbytes; /*!< The memory size in unit of kbytes for AXI nand. */
|
||||
uint32_t ipgAddress; /*!< The base address for IPG nand . */
|
||||
uint32_t ipgMemsize_kbytes; /*!< The memory size in unit of kbytes for IPG nand. */
|
||||
semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */
|
||||
bool edoModeEnabled; /*!< EDO mode enabled. */
|
||||
semc_nand_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
|
||||
semc_nand_address_option_t arrayAddrOption; /*!< Address option. */
|
||||
sem_nand_burst_len_t burstLen; /*!< Burst length. */
|
||||
smec_port_size_t portSize; /*!< Port size. */
|
||||
semc_nand_timing_config_t *timingConfig; /*!< SEMC nand timing configuration. */
|
||||
} semc_nand_config_t;
|
||||
|
||||
/*! @brief SEMC NOR configuration structure. */
|
||||
typedef struct _semc_nor_config
|
||||
{
|
||||
semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */
|
||||
semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */
|
||||
uint32_t address; /*!< The base address. */
|
||||
uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */
|
||||
uint8_t addrPortWidth; /*!< The address port width. */
|
||||
semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */
|
||||
semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity. */
|
||||
semc_norsram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
|
||||
semc_addr_mode_t addrMode; /*!< Address mode. */
|
||||
sem_norsram_burst_len_t burstLen; /*!< Burst length. */
|
||||
smec_port_size_t portSize; /*!< Port size. */
|
||||
uint8_t tCeSetup_Ns; /*!< The CE setup time. */
|
||||
uint8_t tCeHold_Ns; /*!< The CE hold time. */
|
||||
uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */
|
||||
uint8_t tAddrSetup_Ns; /*!< The address setup time. */
|
||||
uint8_t tAddrHold_Ns; /*!< The address hold time. */
|
||||
uint8_t tWeLow_Ns; /*!< WE low time for async mode. */
|
||||
uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */
|
||||
uint8_t tReLow_Ns; /*!< RE low time for async mode. */
|
||||
uint8_t tReHigh_Ns; /*!< RE high time for async mode. */
|
||||
uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */
|
||||
uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */
|
||||
#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME)
|
||||
uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME)
|
||||
uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */
|
||||
#endif
|
||||
uint8_t latencyCount; /*!< Latency count for sync mode. */
|
||||
uint8_t readCycle; /*!< Read cycle time for sync mode. */
|
||||
} semc_nor_config_t;
|
||||
|
||||
/*! @brief SEMC SRAM configuration structure. */
|
||||
typedef struct _semc_sram_config
|
||||
{
|
||||
semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */
|
||||
semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */
|
||||
uint32_t address; /*!< The base address. */
|
||||
uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */
|
||||
uint8_t addrPortWidth; /*!< The address port width. */
|
||||
semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity 1: active high, 0: active low. */
|
||||
semc_addr_mode_t addrMode; /*!< Address mode. */
|
||||
sem_norsram_burst_len_t burstLen; /*!< Burst length. */
|
||||
smec_port_size_t portSize; /*!< Port size. */
|
||||
uint8_t tCeSetup_Ns; /*!< The CE setup time. */
|
||||
uint8_t tCeHold_Ns; /*!< The CE hold time. */
|
||||
uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */
|
||||
uint8_t tAddrSetup_Ns; /*!< The address setup time. */
|
||||
uint8_t tAddrHold_Ns; /*!< The address hold time. */
|
||||
uint8_t tWeLow_Ns; /*!< WE low time for async mode. */
|
||||
uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */
|
||||
uint8_t tReLow_Ns; /*!< RE low time for async mode. */
|
||||
uint8_t tReHigh_Ns; /*!< RE high time for async mode. */
|
||||
uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */
|
||||
uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */
|
||||
uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/
|
||||
uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */
|
||||
uint8_t latencyCount; /*!< Latency count for sync mode. */
|
||||
uint8_t readCycle; /*!< Read cycle time for sync mode. */
|
||||
} semc_sram_config_t;
|
||||
|
||||
/*! @brief SEMC DBI configuration structure. */
|
||||
typedef struct _semc_dbi_config
|
||||
{
|
||||
semc_iomux_pin csxPinMux; /*!< The CE# pin mux. */
|
||||
uint32_t address; /*!< The base address. */
|
||||
uint32_t memsize_kbytes; /*!< The memory size in unit of 4kbytes. */
|
||||
semc_dbi_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
|
||||
sem_dbi_burst_len_t burstLen; /*!< Burst length. */
|
||||
smec_port_size_t portSize; /*!< Port size. */
|
||||
uint8_t tCsxSetup_Ns; /*!< The CSX setup time. */
|
||||
uint8_t tCsxHold_Ns; /*!< The CSX hold time. */
|
||||
uint8_t tWexLow_Ns; /*!< WEX low time. */
|
||||
uint8_t tWexHigh_Ns; /*!< WEX high time. */
|
||||
uint8_t tRdxLow_Ns; /*!< RDX low time. */
|
||||
uint8_t tRdxHigh_Ns; /*!< RDX high time. */
|
||||
uint8_t tCsxInterval_Ns; /*!< Write data setup time.*/
|
||||
} semc_dbi_config_t;
|
||||
|
||||
/*! @brief SEMC AXI queue a weight setting structure. */
|
||||
typedef struct _semc_queuea_weight_struct
|
||||
{
|
||||
uint32_t qos : 4; /*!< weight of qos for queue 0 . */
|
||||
uint32_t aging : 4; /*!< weight of aging for queue 0.*/
|
||||
uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 0.*/
|
||||
uint32_t slaveHitNoswitch : 8; /*!< weight of read/write no switch for queue 0 .*/
|
||||
} semc_queuea_weight_struct_t;
|
||||
|
||||
/*! @brief SEMC AXI queue a weight setting union. */
|
||||
typedef union _semc_queuea_weight
|
||||
{
|
||||
semc_queuea_weight_struct_t queueaConfig; /*!< Structure configuration for queueA. */
|
||||
uint32_t queueaValue; /*!< Configuration value for queueA which could directly write to the reg. */
|
||||
} semc_queuea_weight_t;
|
||||
|
||||
/*! @brief SEMC AXI queue b weight setting structure. */
|
||||
typedef struct _semc_queueb_weight_struct
|
||||
{
|
||||
uint32_t qos : 4; /*!< weight of qos for queue 1. */
|
||||
uint32_t aging : 4; /*!< weight of aging for queue 1.*/
|
||||
uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 1.*/
|
||||
uint32_t weightPagehit : 8; /*!< weight of page hit for queue 1 only .*/
|
||||
uint32_t bankRotation : 8; /*!< weight of bank rotation for queue 1 only .*/
|
||||
} semc_queueb_weight_struct_t;
|
||||
|
||||
/*! @brief SEMC AXI queue b weight setting union. */
|
||||
typedef union _semc_queueb_weight
|
||||
{
|
||||
semc_queueb_weight_struct_t queuebConfig; /*!< Structure configuration for queueB. */
|
||||
uint32_t queuebValue; /*!< Configuration value for queueB which could directly write to the reg. */
|
||||
} semc_queueb_weight_t;
|
||||
|
||||
/*! @brief SEMC AXI queue weight setting. */
|
||||
typedef struct _semc_axi_queueweight
|
||||
{
|
||||
semc_queuea_weight_t queueaWeight; /*!< Weight settings for queue a. */
|
||||
semc_queueb_weight_t queuebWeight; /*!< Weight settings for queue b. */
|
||||
} semc_axi_queueweight_t;
|
||||
|
||||
/*!
|
||||
* @brief SEMC configuration structure.
|
||||
*
|
||||
* busTimeoutCycles: when busTimeoutCycles is zero, the bus timeout cycle is
|
||||
* 255*1024. otherwise the bus timeout cycles is busTimeoutCycles*1024.
|
||||
* cmdTimeoutCycles: is used for command execution timeout cycles. it's
|
||||
* similar to the busTimeoutCycles.
|
||||
*/
|
||||
typedef struct _semc_config_t
|
||||
{
|
||||
semc_dqs_mode_t dqsMode; /*!< Dummy read strobe mode: use enum in "semc_dqs_mode_t". */
|
||||
uint8_t cmdTimeoutCycles; /*!< Command execution timeout cycles. */
|
||||
uint8_t busTimeoutCycles; /*!< Bus timeout cycles. */
|
||||
semc_axi_queueweight_t queueWeight; /*!< AXI queue weight. */
|
||||
} semc_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name SEMC Initialization and De-initialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Gets the SEMC default basic configuration structure.
|
||||
*
|
||||
* The purpose of this API is to get the default SEMC
|
||||
* configure structure for SEMC_Init(). User may use the initialized
|
||||
* structure unchanged in SEMC_Init(), or modify some fields of the
|
||||
* structure before calling SEMC_Init().
|
||||
* Example:
|
||||
@code
|
||||
semc_config_t config;
|
||||
SEMC_GetDefaultConfig(&config);
|
||||
@endcode
|
||||
* @param config The SEMC configuration structure pointer.
|
||||
*/
|
||||
void SEMC_GetDefaultConfig(semc_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Initializes SEMC.
|
||||
* This function ungates the SEMC clock and initializes SEMC.
|
||||
* This function must be called before calling any other SEMC driver functions.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param configure The SEMC configuration structure pointer.
|
||||
*/
|
||||
void SEMC_Init(SEMC_Type *base, semc_config_t *configure);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes the SEMC module and gates the clock.
|
||||
*
|
||||
* This function gates the SEMC clock. As a result, the SEMC module doesn't work after
|
||||
* calling this function, for some IDE, calling this API may cause the next downloading
|
||||
* operation failed. so, please call this API cautiously. Additional, users can
|
||||
* using "#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL (1)" to disable the clock control
|
||||
* operation in drivers.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
*/
|
||||
void SEMC_Deinit(SEMC_Type *base);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name SEMC Configuration Operation For Each Memory Type
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Configures SDRAM controller in SEMC.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param cs The chip selection.
|
||||
* @param config The sdram configuration.
|
||||
* @param clkSrc_Hz The SEMC clock frequency.
|
||||
*/
|
||||
status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz);
|
||||
|
||||
/*!
|
||||
* @brief Configures NAND controller in SEMC.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param config The nand configuration.
|
||||
* @param clkSrc_Hz The SEMC clock frequency.
|
||||
*/
|
||||
status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz);
|
||||
|
||||
/*!
|
||||
* @brief Configures NOR controller in SEMC.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param config The nor configuration.
|
||||
* @param clkSrc_Hz The SEMC clock frequency.
|
||||
*/
|
||||
status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz);
|
||||
|
||||
/*!
|
||||
* @brief Configures SRAM controller in SEMC.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param config The sram configuration.
|
||||
* @param clkSrc_Hz The SEMC clock frequency.
|
||||
*/
|
||||
status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz);
|
||||
|
||||
/*!
|
||||
* @brief Configures DBI controller in SEMC.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param config The dbi configuration.
|
||||
* @param clkSrc_Hz The SEMC clock frequency.
|
||||
*/
|
||||
status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name SEMC Interrupt Operation
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enables the SEMC interrupt.
|
||||
*
|
||||
* This function enables the SEMC interrupts according to the provided mask. The mask
|
||||
* is a logical OR of enumeration members. See @ref semc_interrupt_enable_t.
|
||||
* For example, to enable the IP command done and error interrupt, do the following.
|
||||
* @code
|
||||
* SEMC_EnableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt);
|
||||
* @endcode
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param mask SEMC interrupts to enable. This is a logical OR of the
|
||||
* enumeration :: semc_interrupt_enable_t.
|
||||
*/
|
||||
static inline void SEMC_EnableInterrupts(SEMC_Type *base, uint32_t mask)
|
||||
{
|
||||
base->INTEN |= mask;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disables the SEMC interrupt.
|
||||
*
|
||||
* This function disables the SEMC interrupts according to the provided mask. The mask
|
||||
* is a logical OR of enumeration members. See @ref semc_interrupt_enable_t.
|
||||
* For example, to disable the IP command done and error interrupt, do the following.
|
||||
* @code
|
||||
* SEMC_DisableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt);
|
||||
* @endcode
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param mask SEMC interrupts to disable. This is a logical OR of the
|
||||
* enumeration :: semc_interrupt_enable_t.
|
||||
*/
|
||||
static inline void SEMC_DisableInterrupts(SEMC_Type *base, uint32_t mask)
|
||||
{
|
||||
base->INTEN &= ~mask;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Gets the SEMC status.
|
||||
*
|
||||
* This function gets the SEMC interrupts event status.
|
||||
* User can use the a logical OR of enumeration member as a mask.
|
||||
* See @ref semc_interrupt_enable_t.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @return status flag, use status flag in semc_interrupt_enable_t to get the related status.
|
||||
*/
|
||||
static inline bool SEMC_GetStatusFlag(SEMC_Type *base)
|
||||
{
|
||||
return base->INTR;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clears the SEMC status flag state.
|
||||
*
|
||||
* The following status register flags can be cleared SEMC interrupt status.
|
||||
*
|
||||
* @param base SEMC base pointer
|
||||
* @param mask The status flag mask, a logical OR of enumeration member @ref semc_interrupt_enable_t.
|
||||
*/
|
||||
static inline void SEMC_ClearStatusFlags(SEMC_Type *base, uint32_t mask)
|
||||
{
|
||||
base->INTR |= mask;
|
||||
}
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name SEMC Memory Access Operation
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Check if SEMC is in idle.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @return True SEMC is in idle, false is not in idle.
|
||||
*/
|
||||
static inline bool SEMC_IsInIdle(SEMC_Type *base)
|
||||
{
|
||||
return (base->STS0 & SEMC_STS0_IDLE_MASK) ? true : false;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief SEMC IP command access.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param type SEMC memory type. refer to "semc_mem_type_t"
|
||||
* @param address SEMC device address.
|
||||
* @param command SEMC IP command.
|
||||
* For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command.
|
||||
* For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t".
|
||||
* For SRAM device, take refer to "semc_ipcmd_sram_t".
|
||||
* For SDRAM device, take refer to "semc_ipcmd_sdram_t".
|
||||
* @param write Data for write access.
|
||||
* @param read Data pointer for read data out.
|
||||
*/
|
||||
status_t SEMC_SendIPCommand(
|
||||
SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint16_t command, uint32_t write, uint32_t *read);
|
||||
|
||||
/*!
|
||||
* @brief Build SEMC IP command for NAND.
|
||||
*
|
||||
* This function build SEMC NAND IP command. The command is build of user command code,
|
||||
* SEMC address mode and SEMC command mode.
|
||||
*
|
||||
* @param userCommand NAND device normal command.
|
||||
* @param addrMode NAND address mode. Refer to "semc_ipcmd_nand_addrmode_t".
|
||||
* @param cmdMode NAND command mode. Refer to "semc_ipcmd_nand_cmdmode_t".
|
||||
*/
|
||||
static inline uint16_t SEMC_BuildNandIPCommand(uint8_t userCommand,
|
||||
semc_ipcmd_nand_addrmode_t addrMode,
|
||||
semc_ipcmd_nand_cmdmode_t cmdMode)
|
||||
{
|
||||
return (uint16_t)((uint16_t)userCommand << 8) | (uint16_t)(addrMode << 4) | ((uint8_t)cmdMode & 0x0Fu);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Check if the NAND device is ready.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @return True NAND is ready, false NAND is not ready.
|
||||
*/
|
||||
static inline bool SEMC_IsNandReady(SEMC_Type *base)
|
||||
{
|
||||
return (base->STS0 & SEMC_STS0_NARDY_MASK) ? true : false;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief SEMC NAND device memory write through IP command.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param address SEMC NAND device address.
|
||||
* @param data Data for write access.
|
||||
* @param size_bytes Data length.
|
||||
*/
|
||||
status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
|
||||
|
||||
/*!
|
||||
* @brief SEMC NAND device memory read through IP command.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param address SEMC NAND device address.
|
||||
* @param data Data pointer for data read out.
|
||||
* @param size_bytes Data length.
|
||||
*/
|
||||
status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
|
||||
|
||||
/*!
|
||||
* @brief SEMC NOR device memory write through IP command.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param address SEMC NOR device address.
|
||||
* @param data Data for write access.
|
||||
* @param size_bytes Data length.
|
||||
*/
|
||||
status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
|
||||
|
||||
/*!
|
||||
* @brief SEMC NOR device memory read through IP command.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param address SEMC NOR device address.
|
||||
* @param data Data pointer for data read out.
|
||||
* @param size_bytes Data length.
|
||||
*/
|
||||
status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
|
||||
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_SEMC_H_*/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,127 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1052CVJ5B
|
||||
** MIMXRT1052CVL5B
|
||||
** MIMXRT1052DVJ6B
|
||||
** MIMXRT1052DVL6B
|
||||
**
|
||||
** Compilers: Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
** Keil ARM C/C++ Compiler
|
||||
** MCUXpresso Compiler
|
||||
**
|
||||
** Reference manual: IMXRT1050RM Rev.2.1, 12/2018
|
||||
** Version: rev. 1.2, 2018-11-27
|
||||
** Build: b181205
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that
|
||||
** contains the system frequency. It configures the device and initializes
|
||||
** the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2018 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 0.1 (2017-01-10)
|
||||
** Initial version.
|
||||
** - rev. 1.0 (2018-09-21)
|
||||
** Update interrupt vector table and dma request source.
|
||||
** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
|
||||
** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
|
||||
** - rev. 1.1 (2018-11-16)
|
||||
** Update header files to align with IMXRT1050RM Rev.1.
|
||||
** - rev. 1.2 (2018-11-27)
|
||||
** Update header files to align with IMXRT1050RM Rev.2.1.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file MIMXRT1052
|
||||
* @version 1.2
|
||||
* @date 2018-11-27
|
||||
* @brief Device specific configuration file for MIMXRT1052 (header file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
|
||||
#ifndef _SYSTEM_MIMXRT1052_H_
|
||||
#define _SYSTEM_MIMXRT1052_H_ /**< Symbol preventing repeated inclusion */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
#ifndef DISABLE_WDOG
|
||||
#define DISABLE_WDOG 1
|
||||
#endif
|
||||
|
||||
/* Define clock source values */
|
||||
|
||||
#define CPU_XTAL_CLK_HZ 24000000UL /* Value of the external crystal or oscillator clock frequency in Hz */
|
||||
|
||||
#define CPU_CLK1_HZ 0UL /* Value of the CLK1 (select the CLK1_N/CLK1_P as source) frequency in Hz */
|
||||
/* If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 will be returned. */
|
||||
|
||||
#define DEFAULT_SYSTEM_CLOCK 528000000UL /* Default System clock value */
|
||||
|
||||
|
||||
/**
|
||||
* @brief System clock frequency (core clock)
|
||||
*
|
||||
* The system clock frequency supplied to the SysTick timer and the processor
|
||||
* core clock. This variable can be used by the user application to setup the
|
||||
* SysTick timer or configure other parameters. It may also be used by debugger to
|
||||
* query the frequency of the debug timer or configure the trace clock speed
|
||||
* SystemCoreClock is initialized with a correct predefined value.
|
||||
*/
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
*
|
||||
* Typically this function configures the oscillator (PLL) that is part of the
|
||||
* microcontroller device. For systems with variable clock speed it also updates
|
||||
* the variable SystemCoreClock. SystemInit is called from startup_device file.
|
||||
*/
|
||||
void SystemInit (void);
|
||||
|
||||
/**
|
||||
* @brief Updates the SystemCoreClock variable.
|
||||
*
|
||||
* It must be called whenever the core clock is changed during program
|
||||
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
|
||||
* the current core clock.
|
||||
*/
|
||||
void SystemCoreClockUpdate (void);
|
||||
|
||||
/**
|
||||
* @brief SystemInit function hook.
|
||||
*
|
||||
* This weak function allows to call specific initialization code during the
|
||||
* SystemInit() execution.This can be used when an application specific code needs
|
||||
* to be called as close to the reset entry as possible (for example the Multicore
|
||||
* Manager MCMGR_EarlyInit() function call).
|
||||
* NOTE: No global r/w variables can be used in this hook function because the
|
||||
* initialization of these variables happens after this function.
|
||||
*/
|
||||
void SystemInitHook (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SYSTEM_MIMXRT1052_H_ */
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
if BSP_USING_SDIO
|
||||
config SDIO_BUS_NAME
|
||||
string "sdio bus name"
|
||||
default "sdio"
|
||||
|
||||
config SDIO_DRIVER_NAME
|
||||
string "sdio driver name"
|
||||
default "sdio_drv"
|
||||
|
||||
config SDIO_DEVICE_NAME
|
||||
string "sdio device name"
|
||||
default "sdio_dev"
|
||||
endif
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
SRC_DIR := sdmmc
|
||||
|
||||
SRC_FILES := connect_sdio.c
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,367 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file connect_sdio.c
|
||||
* @brief support sdio function using bus driver framework on OK1052 board
|
||||
* @version 2.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2022-01-24
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: connect_sdio.c
|
||||
Description: support imxrt1052-board sd card configure and sdio bus register function
|
||||
Others: take SDK_2.6.1_MIMXRT1052xxxxB/boards/evkbimxrt1050/driver_examples/sdcard/polling/sdcard_polling.c for references
|
||||
History:
|
||||
1. Date: 2022-01-24
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. support imxrt1052-board sdio configure, write and read
|
||||
2. support imxrt1052-board sdio bus device and driver register
|
||||
*************************************************/
|
||||
|
||||
#include <connect_sdio.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
#define SDCARD_POWER_CTRL_FUNCTION_EXIST
|
||||
|
||||
/*! @brief Data block count accessed in card */
|
||||
#define DATA_BLOCK_COUNT (5U)
|
||||
/*! @brief Start data block number accessed in card */
|
||||
#define DATA_BLOCK_START (2U)
|
||||
/*! @brief Data buffer size. */
|
||||
#define DATA_BUFFER_SIZE (FSL_SDMMC_DEFAULT_BLOCK_SIZE * DATA_BLOCK_COUNT)
|
||||
|
||||
#define BOARD_USDHC_SDCARD_POWER_CONTROL(state) \
|
||||
(GPIO_PinWrite(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, state))
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
static void BoardPowerOffSdCard(void);
|
||||
static void BoardPowerOnSdCard(void);
|
||||
|
||||
/*!
|
||||
* @brief printf the card information log.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
*/
|
||||
static void CardInformationLog(sd_card_t *card);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
/* @brief decription about the read/write buffer
|
||||
* The size of the read/write buffer should be a multiple of 512, since SDHC/SDXC card uses 512-byte fixed
|
||||
* block length and this driver example is enabled with a SDHC/SDXC card.If you are using a SDSC card, you
|
||||
* can define the block length by yourself if the card supports partial access.
|
||||
* The address of the read/write buffer should align to the specific DMA data buffer address align value if
|
||||
* DMA transfer is used, otherwise the buffer address is not important.
|
||||
* At the same time buffer address/size should be aligned to the cache line size if cache is supported.
|
||||
*/
|
||||
/*! @brief Data written to the card */
|
||||
SDK_ALIGN(uint8_t g_data_write[SDK_SIZEALIGN(DATA_BUFFER_SIZE, SDMMC_DATA_BUFFER_ALIGN_CACHE)],
|
||||
MAX(SDMMC_DATA_BUFFER_ALIGN_CACHE, SDMMCHOST_DMA_BUFFER_ADDR_ALIGN));
|
||||
/*! @brief Data read from the card */
|
||||
SDK_ALIGN(uint8_t g_data_read[SDK_SIZEALIGN(DATA_BUFFER_SIZE, SDMMC_DATA_BUFFER_ALIGN_CACHE)],
|
||||
MAX(SDMMC_DATA_BUFFER_ALIGN_CACHE, SDMMCHOST_DMA_BUFFER_ADDR_ALIGN));
|
||||
|
||||
/*! @brief SDMMC host detect card configuration */
|
||||
static const sdmmchost_detect_card_t s_sdcard_detect = {
|
||||
#ifndef BOARD_SD_DETECT_TYPE
|
||||
.cdType = kSDMMCHOST_DetectCardByGpioCD,
|
||||
#else
|
||||
.cdType = BOARD_SD_DETECT_TYPE,
|
||||
#endif
|
||||
.cdTimeOut_ms = (~0U),
|
||||
};
|
||||
|
||||
/*! @brief SDMMC card power control configuration */
|
||||
#if defined SDCARD_POWER_CTRL_FUNCTION_EXIST
|
||||
static const sdmmchost_pwr_card_t s_sdcard_pwr_ctrl = {
|
||||
.powerOn = BoardPowerOnSdCard,
|
||||
.powerOnDelay_ms = 0U,
|
||||
.powerOff = BoardPowerOffSdCard,
|
||||
.powerOffDelay_ms = 0U,
|
||||
};
|
||||
#endif
|
||||
|
||||
/*! @brief SDMMC card power control configuration */
|
||||
#if defined SDCARD_SWITCH_VOLTAGE_FUNCTION_EXIST
|
||||
static const sdmmchost_card_switch_voltage_func_t s_sdcard_voltage_switch = {
|
||||
.cardSignalLine1V8 = BOARD_USDHC_Switch_VoltageTo1V8,
|
||||
.cardSignalLine3V3 = BOARD_USDHC_Switch_VoltageTo3V3,
|
||||
};
|
||||
#endif
|
||||
|
||||
/*! @brief SD card detect flag */
|
||||
static volatile bool s_card_inserted = false;
|
||||
|
||||
/*! @brief Card descriptor. */
|
||||
static sd_card_t g_sd;
|
||||
static int sd_lock = -1;
|
||||
|
||||
static void BoardUSDHCClockConfiguration(void)
|
||||
{
|
||||
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
|
||||
/*configure system pll PFD0 fractional divider to 24, output clock is 528MHZ * 18 / 24 = 396 MHZ*/
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd0, 24U);
|
||||
/* Configure USDHC clock source and divider */
|
||||
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 0U);
|
||||
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 1U);
|
||||
}
|
||||
|
||||
static void BoardPowerOffSdCard(void)
|
||||
{
|
||||
/*
|
||||
Do nothing here.
|
||||
|
||||
SD card will not be detected correctly if the card VDD is power off,
|
||||
the reason is caused by card VDD supply to the card detect circuit, this issue is exist on EVK board rev A1 and
|
||||
A2.
|
||||
|
||||
If power off function is not implemented after soft reset and prior to SD Host initialization without
|
||||
remove/insert card,
|
||||
a UHS-I card may not reach its highest speed mode during the second card initialization.
|
||||
Application can avoid this issue by toggling the SD_VDD (GPIO) before the SD host initialization.
|
||||
*/
|
||||
}
|
||||
|
||||
static void BoardPowerOnSdCard(void)
|
||||
{
|
||||
BOARD_USDHC_SDCARD_POWER_CONTROL(1);
|
||||
}
|
||||
|
||||
static void SdcardDetectCallBack(bool is_inserted, void *user_data)
|
||||
{
|
||||
s_card_inserted = is_inserted;
|
||||
}
|
||||
|
||||
static void CardInformationLog(sd_card_t *card)
|
||||
{
|
||||
NULL_PARAM_CHECK(card);
|
||||
|
||||
KPrintf("\r\nCard size %d * %d bytes\r\n", card->blockCount, card->blockSize);
|
||||
KPrintf("\r\nWorking condition:\r\n");
|
||||
if (card->operationVoltage == kCARD_OperationVoltage330V) {
|
||||
KPrintf("\r\n Voltage : 3.3V\r\n");
|
||||
} else if (card->operationVoltage == kCARD_OperationVoltage180V) {
|
||||
KPrintf("\r\n Voltage : 1.8V\r\n");
|
||||
}
|
||||
|
||||
if (card->currentTiming == kSD_TimingSDR12DefaultMode) {
|
||||
if (card->operationVoltage == kCARD_OperationVoltage330V) {
|
||||
KPrintf("\r\n Timing mode: Default mode\r\n");
|
||||
} else if (card->operationVoltage == kCARD_OperationVoltage180V) {
|
||||
KPrintf("\r\n Timing mode: SDR12 mode\r\n");
|
||||
}
|
||||
} else if (card->currentTiming == kSD_TimingSDR25HighSpeedMode) {
|
||||
if (card->operationVoltage == kCARD_OperationVoltage180V) {
|
||||
KPrintf("\r\n Timing mode: SDR25\r\n");
|
||||
} else {
|
||||
KPrintf("\r\n Timing mode: High Speed\r\n");
|
||||
}
|
||||
} else if (card->currentTiming == kSD_TimingSDR50Mode) {
|
||||
KPrintf("\r\n Timing mode: SDR50\r\n");
|
||||
} else if (card->currentTiming == kSD_TimingSDR104Mode) {
|
||||
KPrintf("\r\n Timing mode: SDR104\r\n");
|
||||
} else if (card->currentTiming == kSD_TimingDDR50Mode) {
|
||||
KPrintf("\r\n Timing mode: DDR50\r\n");
|
||||
}
|
||||
|
||||
KPrintf("\r\n Freq : %d HZ\r\n", card->busClock_Hz);
|
||||
}
|
||||
|
||||
static uint32 SdioConfigure(void *drv, struct BusConfigureInfo *configure_info)
|
||||
{
|
||||
NULL_PARAM_CHECK(drv);
|
||||
NULL_PARAM_CHECK(configure_info);
|
||||
|
||||
if (configure_info->configure_cmd == OPER_BLK_GETGEOME) {
|
||||
NULL_PARAM_CHECK(configure_info->private_data);
|
||||
struct DeviceBlockArrange *args = (struct DeviceBlockArrange *)configure_info->private_data;
|
||||
|
||||
args->size_perbank = g_sd.blockSize;
|
||||
args->block_size = g_sd.blockSize;
|
||||
args->bank_num = g_sd.blockCount;
|
||||
}
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static uint32 SdioOpen(void *dev)
|
||||
{
|
||||
NULL_PARAM_CHECK(dev);
|
||||
|
||||
if(sd_lock >= 0) {
|
||||
KSemaphoreDelete(sd_lock);
|
||||
}
|
||||
sd_lock = KSemaphoreCreate(1);
|
||||
if (sd_lock < 0){
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static uint32 SdioClose(void *dev)
|
||||
{
|
||||
NULL_PARAM_CHECK(dev);
|
||||
|
||||
KSemaphoreDelete(sd_lock);
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static uint32 SdioRead(void *dev, struct BusBlockReadParam *read_param)
|
||||
{
|
||||
uint8 ret = EOK;
|
||||
uint32 sector = read_param->pos;
|
||||
uint32 block_num = read_param->size;
|
||||
uint8 *read_buffer = (uint8 *)read_param->buffer;
|
||||
|
||||
KSemaphoreObtain(sd_lock, WAITING_FOREVER);
|
||||
|
||||
if (kStatus_Success != SD_ReadBlocks(&g_sd, read_buffer, sector, block_num)) {
|
||||
KPrintf("Read multiple data blocks failed.\r\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
KSemaphoreAbandon(sd_lock);
|
||||
|
||||
return read_param->size;
|
||||
}
|
||||
|
||||
static uint32 SdioWrite(void *dev, struct BusBlockWriteParam *write_param)
|
||||
{
|
||||
uint8 ret = EOK;
|
||||
uint32 sector = write_param->pos;
|
||||
uint32 block_num = write_param->size;
|
||||
const uint8 *write_buffer = (uint8 *)write_param->buffer;
|
||||
|
||||
KSemaphoreObtain(sd_lock, WAITING_FOREVER);
|
||||
|
||||
if (kStatus_Success != SD_WriteBlocks(&g_sd, write_buffer, sector, block_num)) {
|
||||
KPrintf("Write multiple data blocks failed.\r\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
KSemaphoreAbandon(sd_lock);
|
||||
|
||||
return write_param->size;
|
||||
}
|
||||
|
||||
static struct SdioDevDone dev_done =
|
||||
{
|
||||
SdioOpen,
|
||||
SdioClose,
|
||||
SdioWrite,
|
||||
SdioRead,
|
||||
};
|
||||
|
||||
int Imrt1052HwSdioInit(void)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
bool is_read_only;
|
||||
|
||||
static struct SdioBus sdio_bus;
|
||||
static struct SdioDriver sdio_drv;
|
||||
static struct SdioHardwareDevice sdio_dev;
|
||||
static sd_card_t *card = &g_sd;
|
||||
|
||||
memset(&sdio_bus, 0, sizeof(struct SdioBus));
|
||||
memset(&sdio_drv, 0, sizeof(struct SdioDriver));
|
||||
memset(&sdio_dev, 0, sizeof(struct SdioHardwareDevice));
|
||||
|
||||
BoardUSDHCClockConfiguration();
|
||||
|
||||
card->host.base = SD_HOST_BASEADDR;
|
||||
card->host.sourceClock_Hz = SD_HOST_CLK_FREQ;
|
||||
|
||||
/* card detect type */
|
||||
card->usrParam.cd = &s_sdcard_detect;
|
||||
|
||||
#if defined SDCARD_POWER_CTRL_FUNCTION_EXIST
|
||||
card->usrParam.pwr = &s_sdcard_pwr_ctrl;
|
||||
#endif
|
||||
|
||||
#if defined DEMO_SDCARD_SWITCH_VOLTAGE_FUNCTION_EXIST
|
||||
card->usrParam.cardVoltage = &s_sdcard_voltage_switch;
|
||||
#endif
|
||||
|
||||
/* SD host init function */
|
||||
if (SD_HostInit(card) != kStatus_Success) {
|
||||
KPrintf("\r\nSD host init fail\r\n");
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
KPrintf("\r\nPlease insert a card into board.\r\n");
|
||||
|
||||
/* power off card */
|
||||
SD_PowerOffCard(card->host.base, card->usrParam.pwr);
|
||||
|
||||
if (SD_WaitCardDetectStatus(SD_HOST_BASEADDR, &s_sdcard_detect, true) == kStatus_Success) {
|
||||
KPrintf("\r\nCard inserted.\r\n");
|
||||
/* reset host once card re-plug in */
|
||||
SD_HostReset(&(card->host));
|
||||
/* power on the card */
|
||||
SD_PowerOnCard(card->host.base, card->usrParam.pwr);
|
||||
KPrintf("power on done\n");
|
||||
} else {
|
||||
KPrintf("\r\nCard detect fail.\r\n");
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/* Init card. */
|
||||
if (SD_CardInit(card)) {
|
||||
KPrintf("\r\nSD card init failed.\r\n");
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/* card information log */
|
||||
CardInformationLog(card);
|
||||
|
||||
/* Check if card is readonly. */
|
||||
is_read_only = SD_CheckReadOnly(card);
|
||||
|
||||
ret = SdioBusInit(&sdio_bus, SDIO_BUS_NAME);
|
||||
if (ret != EOK) {
|
||||
KPrintf("Sdio bus init error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = SdioDriverInit(&sdio_drv, SDIO_DRIVER_NAME);
|
||||
if (ret != EOK) {
|
||||
KPrintf("Sdio driver init error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
ret = SdioDriverAttachToBus(SDIO_DRIVER_NAME, SDIO_BUS_NAME);
|
||||
if (ret != EOK) {
|
||||
KPrintf("Sdio driver attach error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
sdio_dev.dev_done = &dev_done;
|
||||
ret = SdioDeviceRegister(&sdio_dev, SDIO_DEVICE_NAME);
|
||||
if (ret != EOK) {
|
||||
KPrintf("Sdio device register error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
ret = SdioDeviceAttachToBus(SDIO_DEVICE_NAME, SDIO_BUS_NAME);
|
||||
if (ret != EOK) {
|
||||
KPrintf("Sdio device register error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
SRC_DIR += port src
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,321 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _FSL_MMC_H_
|
||||
#define _FSL_MMC_H_
|
||||
|
||||
#include "fsl_sdmmc_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup MMCCARD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/*! @brief MMC card flags */
|
||||
enum _mmc_card_flag
|
||||
{
|
||||
kMMC_SupportHighSpeed26MHZFlag = (1U << 0U), /*!< Support high speed 26MHZ */
|
||||
kMMC_SupportHighSpeed52MHZFlag = (1U << 1U), /*!< Support high speed 52MHZ */
|
||||
kMMC_SupportHighSpeedDDR52MHZ180V300VFlag = (1 << 2U), /*!< ddr 52MHZ 1.8V or 3.0V */
|
||||
kMMC_SupportHighSpeedDDR52MHZ120VFlag = (1 << 3U), /*!< DDR 52MHZ 1.2V */
|
||||
kMMC_SupportHS200200MHZ180VFlag = (1 << 4U), /*!< HS200 ,200MHZ,1.8V */
|
||||
kMMC_SupportHS200200MHZ120VFlag = (1 << 5U), /*!< HS200, 200MHZ, 1.2V */
|
||||
kMMC_SupportHS400DDR200MHZ180VFlag = (1 << 6U), /*!< HS400, DDR, 200MHZ,1.8V */
|
||||
kMMC_SupportHS400DDR200MHZ120VFlag = (1 << 7U), /*!< HS400, DDR, 200MHZ,1.2V */
|
||||
kMMC_SupportHighCapacityFlag = (1U << 8U), /*!< Support high capacity */
|
||||
kMMC_SupportAlternateBootFlag = (1U << 9U), /*!< Support alternate boot */
|
||||
kMMC_SupportDDRBootFlag = (1U << 10U), /*!< support DDR boot flag*/
|
||||
kMMC_SupportHighSpeedBootFlag = (1U << 11U), /*!< support high speed boot flag*/
|
||||
};
|
||||
|
||||
/*!
|
||||
* @brief mmc card state
|
||||
*
|
||||
* Define the card structure including the necessary fields to identify and describe the card.
|
||||
*/
|
||||
typedef struct _mmc_card
|
||||
{
|
||||
SDMMCHOST_CONFIG host; /*!< Host information */
|
||||
mmccard_usr_param_t usrParam; /*!< user parameter */
|
||||
|
||||
bool isHostReady; /*!< Use this flag to indicate if need host re-init or not*/
|
||||
bool noInteralAlign; /*!< use this flag to disable sdmmc align. If disable, sdmmc will not make sure the
|
||||
data buffer address is word align, otherwise all the transfer are align to low level driver */
|
||||
uint32_t busClock_Hz; /*!< MMC bus clock united in Hz */
|
||||
uint32_t relativeAddress; /*!< Relative address of the card */
|
||||
bool enablePreDefinedBlockCount; /*!< Enable PRE-DEFINED block count when read/write */
|
||||
uint32_t flags; /*!< Capability flag in _mmc_card_flag */
|
||||
uint32_t rawCid[4U]; /*!< Raw CID content */
|
||||
uint32_t rawCsd[4U]; /*!< Raw CSD content */
|
||||
uint32_t rawExtendedCsd[MMC_EXTENDED_CSD_BYTES / 4U]; /*!< Raw MMC Extended CSD content */
|
||||
uint32_t ocr; /*!< Raw OCR content */
|
||||
mmc_cid_t cid; /*!< CID */
|
||||
mmc_csd_t csd; /*!< CSD */
|
||||
mmc_extended_csd_t extendedCsd; /*!< Extended CSD */
|
||||
uint32_t blockSize; /*!< Card block size */
|
||||
uint32_t userPartitionBlocks; /*!< Card total block number in user partition */
|
||||
uint32_t bootPartitionBlocks; /*!< Boot partition size united as block size */
|
||||
uint32_t eraseGroupBlocks; /*!< Erase group size united as block size */
|
||||
mmc_access_partition_t currentPartition; /*!< Current access partition */
|
||||
mmc_voltage_window_t hostVoltageWindowVCCQ; /*!< Host IO voltage window */
|
||||
mmc_voltage_window_t hostVoltageWindowVCC; /*!< application must set this value according to board specific */
|
||||
mmc_high_speed_timing_t busTiming; /*!< indicate the current work timing mode*/
|
||||
mmc_data_bus_width_t busWidth; /*!< indicate the current work bus width */
|
||||
} mmc_card_t;
|
||||
|
||||
/*************************************************************************************************
|
||||
* API
|
||||
************************************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name MMCCARD Function
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes the MMC card and host.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
*
|
||||
* @retval kStatus_SDMMC_HostNotReady host is not ready.
|
||||
* @retval kStatus_SDMMC_GoIdleFailed Go idle failed.
|
||||
* @retval kStatus_SDMMC_SendOperationConditionFailed Send operation condition failed.
|
||||
* @retval kStatus_SDMMC_AllSendCidFailed Send CID failed.
|
||||
* @retval kStatus_SDMMC_SetRelativeAddressFailed Set relative address failed.
|
||||
* @retval kStatus_SDMMC_SendCsdFailed Send CSD failed.
|
||||
* @retval kStatus_SDMMC_CardNotSupport Card not support.
|
||||
* @retval kStatus_SDMMC_SelectCardFailed Send SELECT_CARD command failed.
|
||||
* @retval kStatus_SDMMC_SendExtendedCsdFailed Send EXT_CSD failed.
|
||||
* @retval kStatus_SDMMC_SetBusWidthFailed Set bus width failed.
|
||||
* @retval kStatus_SDMMC_SwitchHighSpeedFailed Switch high speed failed.
|
||||
* @retval kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed.
|
||||
* @retval kStatus_Success Operate successfully.
|
||||
*/
|
||||
status_t MMC_Init(mmc_card_t *card);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes the card and host.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
*/
|
||||
void MMC_Deinit(mmc_card_t *card);
|
||||
|
||||
/*!
|
||||
* @brief intialize the card.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
*
|
||||
* @retval kStatus_SDMMC_HostNotReady host is not ready.
|
||||
* @retval kStatus_SDMMC_GoIdleFailed Go idle failed.
|
||||
* @retval kStatus_SDMMC_SendOperationConditionFailed Send operation condition failed.
|
||||
* @retval kStatus_SDMMC_AllSendCidFailed Send CID failed.
|
||||
* @retval kStatus_SDMMC_SetRelativeAddressFailed Set relative address failed.
|
||||
* @retval kStatus_SDMMC_SendCsdFailed Send CSD failed.
|
||||
* @retval kStatus_SDMMC_CardNotSupport Card not support.
|
||||
* @retval kStatus_SDMMC_SelectCardFailed Send SELECT_CARD command failed.
|
||||
* @retval kStatus_SDMMC_SendExtendedCsdFailed Send EXT_CSD failed.
|
||||
* @retval kStatus_SDMMC_SetBusWidthFailed Set bus width failed.
|
||||
* @retval kStatus_SDMMC_SwitchHighSpeedFailed Switch high speed failed.
|
||||
* @retval kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed.
|
||||
* @retval kStatus_Success Operate successfully.
|
||||
*/
|
||||
status_t MMC_CardInit(mmc_card_t *card);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes the card.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
*/
|
||||
void MMC_CardDeinit(mmc_card_t *card);
|
||||
|
||||
/*!
|
||||
* @brief initialize the host.
|
||||
*
|
||||
* This function deinitializes the specific host.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
*/
|
||||
status_t MMC_HostInit(mmc_card_t *card);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes the host.
|
||||
*
|
||||
* This function deinitializes the host.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
*/
|
||||
void MMC_HostDeinit(mmc_card_t *card);
|
||||
|
||||
/*!
|
||||
* @brief reset the host.
|
||||
*
|
||||
* This function reset the specific host.
|
||||
*
|
||||
* @param host host descriptor.
|
||||
*/
|
||||
void MMC_HostReset(SDMMCHOST_CONFIG *host);
|
||||
|
||||
/*!
|
||||
* @brief power on card.
|
||||
*
|
||||
* The power on operation depend on host or the user define power on function.
|
||||
* @param base host base address.
|
||||
* @param pwr user define power control configuration
|
||||
*/
|
||||
void MMC_PowerOnCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr);
|
||||
|
||||
/*!
|
||||
* @brief power off card.
|
||||
*
|
||||
* The power off operation depend on host or the user define power on function.
|
||||
* @param base host base address.
|
||||
* @param pwr user define power control configuration
|
||||
*/
|
||||
void MMC_PowerOffCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr);
|
||||
|
||||
/*!
|
||||
* @brief Checks if the card is read-only.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @retval true Card is read only.
|
||||
* @retval false Card isn't read only.
|
||||
*/
|
||||
bool MMC_CheckReadOnly(mmc_card_t *card);
|
||||
|
||||
/*!
|
||||
* @brief Reads data blocks from the card.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param buffer The buffer to save data.
|
||||
* @param startBlock The start block index.
|
||||
* @param blockCount The number of blocks to read.
|
||||
* @retval kStatus_InvalidArgument Invalid argument.
|
||||
* @retval kStatus_SDMMC_CardNotSupport Card not support.
|
||||
* @retval kStatus_SDMMC_SetBlockCountFailed Set block count failed.
|
||||
* @retval kStatus_SDMMC_TransferFailed Transfer failed.
|
||||
* @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed.
|
||||
* @retval kStatus_Success Operate successfully.
|
||||
*/
|
||||
status_t MMC_ReadBlocks(mmc_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount);
|
||||
|
||||
/*!
|
||||
* @brief Writes data blocks to the card.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param buffer The buffer to save data blocks.
|
||||
* @param startBlock Start block number to write.
|
||||
* @param blockCount Block count.
|
||||
* @retval kStatus_InvalidArgument Invalid argument.
|
||||
* @retval kStatus_SDMMC_NotSupportYet Not support now.
|
||||
* @retval kStatus_SDMMC_SetBlockCountFailed Set block count failed.
|
||||
* @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed.
|
||||
* @retval kStatus_SDMMC_TransferFailed Transfer failed.
|
||||
* @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed.
|
||||
* @retval kStatus_Success Operate successfully.
|
||||
*/
|
||||
status_t MMC_WriteBlocks(mmc_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockCount);
|
||||
|
||||
/*!
|
||||
* @brief Erases groups of the card.
|
||||
*
|
||||
* Erase group is the smallest erase unit in MMC card. The erase range is [startGroup, endGroup].
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param startGroup Start group number.
|
||||
* @param endGroup End group number.
|
||||
* @retval kStatus_InvalidArgument Invalid argument.
|
||||
* @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed.
|
||||
* @retval kStatus_SDMMC_TransferFailed Transfer failed.
|
||||
* @retval kStatus_Success Operate successfully.
|
||||
*/
|
||||
status_t MMC_EraseGroups(mmc_card_t *card, uint32_t startGroup, uint32_t endGroup);
|
||||
|
||||
/*!
|
||||
* @brief Selects the partition to access.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param partitionNumber The partition number.
|
||||
* @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure EXT_CSD failed.
|
||||
* @retval kStatus_Success Operate successfully.
|
||||
*/
|
||||
status_t MMC_SelectPartition(mmc_card_t *card, mmc_access_partition_t partitionNumber);
|
||||
|
||||
/*!
|
||||
* @brief Configures the boot activity of the card.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param config Boot configuration structure.
|
||||
* @retval kStatus_SDMMC_NotSupportYet Not support now.
|
||||
* @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure EXT_CSD failed.
|
||||
* @retval kStatus_SDMMC_ConfigureBootFailed Configure boot failed.
|
||||
* @retval kStatus_Success Operate successfully.
|
||||
*/
|
||||
status_t MMC_SetBootConfig(mmc_card_t *card, const mmc_boot_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief MMC card start boot.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param mmcConfig mmc Boot configuration structure.
|
||||
* @param buffer address to recieve data.
|
||||
* @param hostConfig host boot configurations.
|
||||
* @retval kStatus_Fail fail.
|
||||
* @retval kStatus_SDMMC_TransferFailed transfer fail.
|
||||
* @retval kStatus_SDMMC_GoIdleFailed reset card fail.
|
||||
* @retval kStatus_Success Operate successfully.
|
||||
*/
|
||||
status_t MMC_StartBoot(mmc_card_t *card,
|
||||
const mmc_boot_config_t *mmcConfig,
|
||||
uint8_t *buffer,
|
||||
SDMMCHOST_BOOT_CONFIG *hostConfig);
|
||||
|
||||
/*!
|
||||
* @brief MMC card set boot configuration write protect.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param wp write protect value.
|
||||
*/
|
||||
status_t MMC_SetBootConfigWP(mmc_card_t *card, uint8_t wp);
|
||||
|
||||
/*!
|
||||
* @brief MMC card continous read boot data.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param buffer buffer address.
|
||||
* @param hostConfig host boot configurations.
|
||||
*/
|
||||
status_t MMC_ReadBootData(mmc_card_t *card, uint8_t *buffer, SDMMCHOST_BOOT_CONFIG *hostConfig);
|
||||
|
||||
/*!
|
||||
* @brief MMC card stop boot mode.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param bootMode boot mode.
|
||||
*/
|
||||
status_t MMC_StopBoot(mmc_card_t *card, uint32_t bootMode);
|
||||
|
||||
/*!
|
||||
* @brief MMC card set boot partition write protect.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param bootPartitionWP boot partition write protect value.
|
||||
*/
|
||||
status_t MMC_SetBootPartitionWP(mmc_card_t *card, mmc_boot_partition_wp_t bootPartitionWP);
|
||||
|
||||
/* @} */
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
/*! @} */
|
||||
#endif /* _FSL_MMC_H_*/
|
||||
|
|
@ -0,0 +1,315 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _FSL_SD_H_
|
||||
#define _FSL_SD_H_
|
||||
|
||||
#include "fsl_sdmmc_common.h"
|
||||
/*!
|
||||
* @addtogroup SDCARD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/*! @brief SD card flags */
|
||||
enum _sd_card_flag
|
||||
{
|
||||
kSD_SupportHighCapacityFlag = (1U << 1U), /*!< Support high capacity */
|
||||
kSD_Support4BitWidthFlag = (1U << 2U), /*!< Support 4-bit data width */
|
||||
kSD_SupportSdhcFlag = (1U << 3U), /*!< Card is SDHC */
|
||||
kSD_SupportSdxcFlag = (1U << 4U), /*!< Card is SDXC */
|
||||
kSD_SupportVoltage180v = (1U << 5U), /*!< card support 1.8v voltage*/
|
||||
kSD_SupportSetBlockCountCmd = (1U << 6U), /*!< card support cmd23 flag*/
|
||||
kSD_SupportSpeedClassControlCmd = (1U << 7U), /*!< card support speed class control flag */
|
||||
};
|
||||
|
||||
/*!
|
||||
* @brief SD card state
|
||||
*
|
||||
* Define the card structure including the necessary fields to identify and describe the card.
|
||||
*/
|
||||
typedef struct _sd_card
|
||||
{
|
||||
SDMMCHOST_CONFIG host; /*!< Host information */
|
||||
|
||||
sdcard_usr_param_t usrParam; /*!< user parameter */
|
||||
bool isHostReady; /*!< use this flag to indicate if need host re-init or not*/
|
||||
bool noInteralAlign; /*!< use this flag to disable sdmmc align. If disable, sdmmc will not make sure the
|
||||
data buffer address is word align, otherwise all the transfer are align to low level driver */
|
||||
uint32_t busClock_Hz; /*!< SD bus clock frequency united in Hz */
|
||||
uint32_t relativeAddress; /*!< Relative address of the card */
|
||||
uint32_t version; /*!< Card version */
|
||||
uint32_t flags; /*!< Flags in _sd_card_flag */
|
||||
uint32_t rawCid[4U]; /*!< Raw CID content */
|
||||
uint32_t rawCsd[4U]; /*!< Raw CSD content */
|
||||
uint32_t rawScr[2U]; /*!< Raw CSD content */
|
||||
uint32_t ocr; /*!< Raw OCR content */
|
||||
sd_cid_t cid; /*!< CID */
|
||||
sd_csd_t csd; /*!< CSD */
|
||||
sd_scr_t scr; /*!< SCR */
|
||||
sd_status_t stat; /*!< sd 512 bit status */
|
||||
uint32_t blockCount; /*!< Card total block number */
|
||||
uint32_t blockSize; /*!< Card block size */
|
||||
sd_timing_mode_t currentTiming; /*!< current timing mode */
|
||||
sd_driver_strength_t driverStrength; /*!< driver strength */
|
||||
sd_max_current_t maxCurrent; /*!< card current limit */
|
||||
sdmmc_operation_voltage_t operationVoltage; /*!< card operation voltage */
|
||||
} sd_card_t;
|
||||
|
||||
/*************************************************************************************************
|
||||
* API
|
||||
************************************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name SDCARD Function
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes the card on a specific host controller.
|
||||
* @deprecated Do not use this function. It has been superceded by @ref SD_HostInit,SD_CardInit.
|
||||
|
||||
* This function initializes the card on a specific host controller, it is consist of
|
||||
* host init, card detect, card init function, however user can ignore this high level function,
|
||||
* instead of use the low level function, such as SD_CardInit, SD_HostInit, SD_CardDetect.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @retval kStatus_SDMMC_HostNotReady host is not ready.
|
||||
* @retval kStatus_SDMMC_GoIdleFailed Go idle failed.
|
||||
* @retval kStatus_SDMMC_NotSupportYet Card not support.
|
||||
* @retval kStatus_SDMMC_SendOperationConditionFailed Send operation condition failed.
|
||||
* @retval kStatus_SDMMC_AllSendCidFailed Send CID failed.
|
||||
* @retval kStatus_SDMMC_SendRelativeAddressFailed Send relative address failed.
|
||||
* @retval kStatus_SDMMC_SendCsdFailed Send CSD failed.
|
||||
* @retval kStatus_SDMMC_SelectCardFailed Send SELECT_CARD command failed.
|
||||
* @retval kStatus_SDMMC_SendScrFailed Send SCR failed.
|
||||
* @retval kStatus_SDMMC_SetBusWidthFailed Set bus width failed.
|
||||
* @retval kStatus_SDMMC_SwitchHighSpeedFailed Switch high speed failed.
|
||||
* @retval kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed.
|
||||
* @retval kStatus_Success Operate successfully.
|
||||
*/
|
||||
status_t SD_Init(sd_card_t *card);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes the card.
|
||||
* @deprecated Do not use this function. It has been superceded by @ref SD_HostDeinit,SD_CardDeinit.
|
||||
* This function deinitializes the specific card and host.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
*/
|
||||
void SD_Deinit(sd_card_t *card);
|
||||
|
||||
/*!
|
||||
* @brief Initializes the card.
|
||||
*
|
||||
* This function initializes the card only, make sure the host is ready when call this function,
|
||||
* otherwise it will return kStatus_SDMMC_HostNotReady.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @retval kStatus_SDMMC_HostNotReady host is not ready.
|
||||
* @retval kStatus_SDMMC_GoIdleFailed Go idle failed.
|
||||
* @retval kStatus_SDMMC_NotSupportYet Card not support.
|
||||
* @retval kStatus_SDMMC_SendOperationConditionFailed Send operation condition failed.
|
||||
* @retval kStatus_SDMMC_AllSendCidFailed Send CID failed.
|
||||
* @retval kStatus_SDMMC_SendRelativeAddressFailed Send relative address failed.
|
||||
* @retval kStatus_SDMMC_SendCsdFailed Send CSD failed.
|
||||
* @retval kStatus_SDMMC_SelectCardFailed Send SELECT_CARD command failed.
|
||||
* @retval kStatus_SDMMC_SendScrFailed Send SCR failed.
|
||||
* @retval kStatus_SDMMC_SetBusWidthFailed Set bus width failed.
|
||||
* @retval kStatus_SDMMC_SwitchHighSpeedFailed Switch high speed failed.
|
||||
* @retval kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed.
|
||||
* @retval kStatus_Success Operate successfully.
|
||||
*/
|
||||
status_t SD_CardInit(sd_card_t *card);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes the card.
|
||||
*
|
||||
* This function deinitializes the specific card.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
*/
|
||||
void SD_CardDeinit(sd_card_t *card);
|
||||
|
||||
/*!
|
||||
* @brief initialize the host.
|
||||
*
|
||||
* This function deinitializes the specific host.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
*/
|
||||
status_t SD_HostInit(sd_card_t *card);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes the host.
|
||||
*
|
||||
* This function deinitializes the host.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
*/
|
||||
void SD_HostDeinit(sd_card_t *card);
|
||||
|
||||
/*!
|
||||
* @brief reset the host.
|
||||
*
|
||||
* This function reset the specific host.
|
||||
*
|
||||
* @param host host descriptor.
|
||||
*/
|
||||
void SD_HostReset(SDMMCHOST_CONFIG *host);
|
||||
|
||||
/*!
|
||||
* @brief power on card.
|
||||
*
|
||||
* The power on operation depend on host or the user define power on function.
|
||||
* @param base host base address.
|
||||
* @param pwr user define power control configuration
|
||||
*/
|
||||
void SD_PowerOnCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr);
|
||||
|
||||
/*!
|
||||
* @brief power off card.
|
||||
*
|
||||
* The power off operation depend on host or the user define power on function.
|
||||
* @param base host base address.
|
||||
* @param pwr user define power control configuration
|
||||
*/
|
||||
void SD_PowerOffCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr);
|
||||
|
||||
/*!
|
||||
* @brief sd wait card detect function.
|
||||
*
|
||||
* Detect card through GPIO, CD, DATA3.
|
||||
*
|
||||
* @param card card descriptor.
|
||||
* @param card detect configuration
|
||||
* @param waitCardStatus wait card detect status
|
||||
*/
|
||||
status_t SD_WaitCardDetectStatus(SDMMCHOST_TYPE *hostBase, const sdmmchost_detect_card_t *cd, bool waitCardStatus);
|
||||
|
||||
/*!
|
||||
* @brief sd card present check function.
|
||||
*
|
||||
* @param card card descriptor.
|
||||
*/
|
||||
bool SD_IsCardPresent(sd_card_t *card);
|
||||
|
||||
/*!
|
||||
* @brief Checks whether the card is write-protected.
|
||||
*
|
||||
* This function checks if the card is write-protected via the CSD register.
|
||||
*
|
||||
* @param card The specific card.
|
||||
* @retval true Card is read only.
|
||||
* @retval false Card isn't read only.
|
||||
*/
|
||||
bool SD_CheckReadOnly(sd_card_t *card);
|
||||
|
||||
/*!
|
||||
* @brief Send SELECT_CARD command to set the card to be transfer state or not.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param isSelected True to set the card into transfer state, false to disselect.
|
||||
* @retval kStatus_SDMMC_TransferFailed Transfer failed.
|
||||
* @retval kStatus_Success Operate successfully.
|
||||
*/
|
||||
status_t SD_SelectCard(sd_card_t *card, bool isSelected);
|
||||
|
||||
/*!
|
||||
* @brief Send ACMD13 to get the card current status.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @retval kStatus_SDMMC_TransferFailed Transfer failed.
|
||||
* @retval kStatus_SDMMC_SendApplicationCommandFailed send application command failed.
|
||||
* @retval kStatus_Success Operate successfully.
|
||||
*/
|
||||
status_t SD_ReadStatus(sd_card_t *card);
|
||||
|
||||
/*!
|
||||
* @brief Reads blocks from the specific card.
|
||||
*
|
||||
* This function reads blocks from the specific card with default block size defined by the
|
||||
* SDHC_CARD_DEFAULT_BLOCK_SIZE.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param buffer The buffer to save the data read from card.
|
||||
* @param startBlock The start block index.
|
||||
* @param blockCount The number of blocks to read.
|
||||
* @retval kStatus_InvalidArgument Invalid argument.
|
||||
* @retval kStatus_SDMMC_CardNotSupport Card not support.
|
||||
* @retval kStatus_SDMMC_NotSupportYet Not support now.
|
||||
* @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed.
|
||||
* @retval kStatus_SDMMC_TransferFailed Transfer failed.
|
||||
* @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed.
|
||||
* @retval kStatus_Success Operate successfully.
|
||||
*/
|
||||
status_t SD_ReadBlocks(sd_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount);
|
||||
|
||||
/*!
|
||||
* @brief Writes blocks of data to the specific card.
|
||||
*
|
||||
* This function writes blocks to the specific card with default block size 512 bytes.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param buffer The buffer holding the data to be written to the card.
|
||||
* @param startBlock The start block index.
|
||||
* @param blockCount The number of blocks to write.
|
||||
* @retval kStatus_InvalidArgument Invalid argument.
|
||||
* @retval kStatus_SDMMC_NotSupportYet Not support now.
|
||||
* @retval kStatus_SDMMC_CardNotSupport Card not support.
|
||||
* @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed.
|
||||
* @retval kStatus_SDMMC_TransferFailed Transfer failed.
|
||||
* @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed.
|
||||
* @retval kStatus_Success Operate successfully.
|
||||
*/
|
||||
status_t SD_WriteBlocks(sd_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockCount);
|
||||
|
||||
/*!
|
||||
* @brief Erases blocks of the specific card.
|
||||
*
|
||||
* This function erases blocks of the specific card with default block size 512 bytes.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param startBlock The start block index.
|
||||
* @param blockCount The number of blocks to erase.
|
||||
* @retval kStatus_InvalidArgument Invalid argument.
|
||||
* @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed.
|
||||
* @retval kStatus_SDMMC_TransferFailed Transfer failed.
|
||||
* @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed.
|
||||
* @retval kStatus_Success Operate successfully.
|
||||
*/
|
||||
status_t SD_EraseBlocks(sd_card_t *card, uint32_t startBlock, uint32_t blockCount);
|
||||
|
||||
/*!
|
||||
* @brief select card driver strength
|
||||
* select card driver strength
|
||||
* @param card Card descriptor.
|
||||
* @param driverStrength Driver strength
|
||||
*/
|
||||
status_t SD_SetDriverStrength(sd_card_t *card, sd_driver_strength_t driverStrength);
|
||||
|
||||
/*!
|
||||
* @brief select max current
|
||||
* select max operation current
|
||||
* @param card Card descriptor.
|
||||
* @param maxCurrent Max current
|
||||
*/
|
||||
status_t SD_SetMaxCurrent(sd_card_t *card, sd_max_current_t maxCurrent);
|
||||
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
/*! @} */
|
||||
#endif /* _FSL_SD_H_*/
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _FSL_SDIO_H_
|
||||
#define _FSL_SDIO_H_
|
||||
|
||||
#include "fsl_sdmmc_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup SDIOCARD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/*! @brief Middleware version. */
|
||||
#define FSL_SDIO_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 11U)) /*2.2.11*/
|
||||
|
||||
/*!@brief sdio device support maximum IO number */
|
||||
#ifndef FSL_SDIO_MAX_IO_NUMS
|
||||
#define FSL_SDIO_MAX_IO_NUMS (7U)
|
||||
#endif
|
||||
/*!@brief sdio card descriptor */
|
||||
typedef struct _sdio_card sdio_card_t;
|
||||
/*!@brief sdio io handler */
|
||||
typedef void (*sdio_io_irq_handler_t)(sdio_card_t *card, uint32_t func);
|
||||
/*! @brief sdio io read/write direction */
|
||||
typedef enum _sdio_io_direction
|
||||
{
|
||||
kSDIO_IORead = 0U, /*!< io read */
|
||||
kSDIO_IOWrite = 1U, /*!< io write */
|
||||
} sdio_io_direction_t;
|
||||
|
||||
/*!
|
||||
* @brief SDIO card state
|
||||
*
|
||||
* Define the card structure including the necessary fields to identify and describe the card.
|
||||
*/
|
||||
struct _sdio_card
|
||||
{
|
||||
SDMMCHOST_CONFIG host; /*!< Host information */
|
||||
sdiocard_usr_param_t usrParam; /*!< user parameter */
|
||||
bool noInternalAlign; /*!< use this flag to disable sdmmc align. If disable, sdmmc will not make sure the
|
||||
data buffer address is word align, otherwise all the transfer are align to low level driver */
|
||||
bool isHostReady; /*!< use this flag to indicate if need host re-init or not*/
|
||||
bool memPresentFlag; /*!< indicate if memory present */
|
||||
|
||||
uint32_t busClock_Hz; /*!< SD bus clock frequency united in Hz */
|
||||
uint32_t relativeAddress; /*!< Relative address of the card */
|
||||
uint8_t sdVersion; /*!< SD version */
|
||||
sd_timing_mode_t currentTiming; /*!< current timing mode */
|
||||
sd_driver_strength_t driverStrength; /*!< driver strength */
|
||||
sd_max_current_t maxCurrent; /*!< card current limit */
|
||||
sdmmc_operation_voltage_t operationVoltage; /*!< card operation voltage */
|
||||
|
||||
uint8_t sdioVersion; /*!< SDIO version */
|
||||
uint8_t cccrVersioin; /*!< CCCR version */
|
||||
uint8_t ioTotalNumber; /*!< total number of IO function */
|
||||
uint32_t cccrflags; /*!< Flags in _sd_card_flag */
|
||||
uint32_t io0blockSize; /*!< record the io0 block size*/
|
||||
uint32_t ocr; /*!< Raw OCR content, only 24bit avalible for SDIO card */
|
||||
uint32_t commonCISPointer; /*!< point to common CIS */
|
||||
sdio_common_cis_t commonCIS; /*!< CIS table */
|
||||
|
||||
/* io registers/IRQ handler */
|
||||
sdio_fbr_t ioFBR[FSL_SDIO_MAX_IO_NUMS]; /*!< FBR table */
|
||||
sdio_func_cis_t funcCIS[FSL_SDIO_MAX_IO_NUMS]; /*!< function CIS table*/
|
||||
sdio_io_irq_handler_t ioIRQHandler[FSL_SDIO_MAX_IO_NUMS]; /*!< io IRQ handler */
|
||||
uint8_t ioIntIndex; /*!< used to record current enabled io interrupt index */
|
||||
uint8_t ioIntNums; /*!< used to record total enabled io interrupt numbers */
|
||||
};
|
||||
|
||||
/*************************************************************************************************
|
||||
* API
|
||||
************************************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
/*!
|
||||
* @name Initialization and deinitialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief SDIO card init function
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @retval kStatus_SDMMC_GoIdleFailed
|
||||
* @retval kStatus_SDMMC_HandShakeOperationConditionFailed
|
||||
* @retval kStatus_SDMMC_SDIO_InvalidCard
|
||||
* @retval kStatus_SDMMC_SDIO_InvalidVoltage
|
||||
* @retval kStatus_SDMMC_SendRelativeAddressFailed
|
||||
* @retval kStatus_SDMMC_SelectCardFailed
|
||||
* @retval kStatus_SDMMC_SDIO_SwitchHighSpeedFail
|
||||
* @retval kStatus_SDMMC_SDIO_ReadCISFail
|
||||
* @retval kStatus_SDMMC_TransferFailed
|
||||
* @retval kStatus_Success
|
||||
*/
|
||||
status_t SDIO_Init(sdio_card_t *card);
|
||||
|
||||
/*!
|
||||
* @brief SDIO card deinit, include card and host deinit.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
*/
|
||||
void SDIO_Deinit(sdio_card_t *card);
|
||||
|
||||
/*!
|
||||
* @brief Initializes the card.
|
||||
*
|
||||
* This function initializes the card only, make sure the host is ready when call this function,
|
||||
* otherwise it will return kStatus_SDMMC_HostNotReady.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @retval kStatus_SDMMC_HostNotReady host is not ready.
|
||||
* @retval kStatus_SDMMC_GoIdleFailed Go idle failed.
|
||||
* @retval kStatus_SDMMC_NotSupportYet Card not support.
|
||||
* @retval kStatus_SDMMC_SendOperationConditionFailed Send operation condition failed.
|
||||
* @retval kStatus_SDMMC_AllSendCidFailed Send CID failed.
|
||||
* @retval kStatus_SDMMC_SendRelativeAddressFailed Send relative address failed.
|
||||
* @retval kStatus_SDMMC_SendCsdFailed Send CSD failed.
|
||||
* @retval kStatus_SDMMC_SelectCardFailed Send SELECT_CARD command failed.
|
||||
* @retval kStatus_SDMMC_SendScrFailed Send SCR failed.
|
||||
* @retval kStatus_SDMMC_SetBusWidthFailed Set bus width failed.
|
||||
* @retval kStatus_SDMMC_SwitchHighSpeedFailed Switch high speed failed.
|
||||
* @retval kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed.
|
||||
* @retval kStatus_Success Operate successfully.
|
||||
*/
|
||||
status_t SDIO_CardInit(sdio_card_t *card);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes the card.
|
||||
*
|
||||
* This function deinitializes the specific card.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
*/
|
||||
void SDIO_CardDeinit(sdio_card_t *card);
|
||||
|
||||
/*!
|
||||
* @brief initialize the host.
|
||||
*
|
||||
* This function deinitializes the specific host.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
*/
|
||||
status_t SDIO_HostInit(sdio_card_t *card);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes the host.
|
||||
*
|
||||
* This function deinitializes the host.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
*/
|
||||
void SDIO_HostDeinit(sdio_card_t *card);
|
||||
|
||||
/*!
|
||||
* @brief reset the host.
|
||||
*
|
||||
* This function reset the specific host.
|
||||
*
|
||||
* @param host host descriptor.
|
||||
*/
|
||||
void SDIO_HostReset(SDMMCHOST_CONFIG *host);
|
||||
|
||||
/*!
|
||||
* @brief power on card.
|
||||
*
|
||||
* The power on operation depend on host or the user define power on function.
|
||||
* @param base host base address.
|
||||
* @param pwr user define power control configuration
|
||||
*/
|
||||
void SDIO_PowerOnCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr);
|
||||
|
||||
/*!
|
||||
* @brief power on card.
|
||||
*
|
||||
* The power off operation depend on host or the user define power on function.
|
||||
* @param base host base address.
|
||||
* @param pwr user define power control configuration
|
||||
*/
|
||||
void SDIO_PowerOffCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr);
|
||||
|
||||
/*!
|
||||
* @brief set SDIO card to inactive state
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @retval kStatus_SDMMC_TransferFailed
|
||||
* @retval kStatus_Success
|
||||
*/
|
||||
status_t SDIO_CardInActive(sdio_card_t *card);
|
||||
|
||||
/*!
|
||||
* @brief get SDIO card capability
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param function IO number
|
||||
* @retval kStatus_SDMMC_TransferFailed
|
||||
* @retval kStatus_Success
|
||||
*/
|
||||
status_t SDIO_GetCardCapability(sdio_card_t *card, sdio_func_num_t func);
|
||||
|
||||
/*!
|
||||
* @brief set SDIO card block size
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param function io number
|
||||
* @param block size
|
||||
* @retval kStatus_SDMMC_SetCardBlockSizeFailed
|
||||
* @retval kStatus_SDMMC_SDIO_InvalidArgument
|
||||
* @retval kStatus_Success
|
||||
*/
|
||||
status_t SDIO_SetBlockSize(sdio_card_t *card, sdio_func_num_t func, uint32_t blockSize);
|
||||
|
||||
/*!
|
||||
* @brief set SDIO card reset
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @retval kStatus_SDMMC_TransferFailed
|
||||
* @retval kStatus_Success
|
||||
*/
|
||||
status_t SDIO_CardReset(sdio_card_t *card);
|
||||
|
||||
/*!
|
||||
* @brief set SDIO card data bus width
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param data bus width
|
||||
* @retval kStatus_SDMMC_TransferFailed
|
||||
* @retval kStatus_Success
|
||||
*/
|
||||
status_t SDIO_SetDataBusWidth(sdio_card_t *card, sdio_bus_width_t busWidth);
|
||||
|
||||
/*!
|
||||
* @brief switch the card to high speed
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @retval kStatus_SDMMC_TransferFailed
|
||||
* @retval kStatus_SDMMC_SDIO_SwitchHighSpeedFail
|
||||
* @retval kStatus_Success
|
||||
*/
|
||||
status_t SDIO_SwitchToHighSpeed(sdio_card_t *card);
|
||||
|
||||
/*!
|
||||
* @brief read SDIO card CIS for each function
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param function io number
|
||||
* @param tuple code list
|
||||
* @param tuple code number
|
||||
* @retval kStatus_SDMMC_SDIO_ReadCISFail
|
||||
* @retval kStatus_SDMMC_TransferFailed
|
||||
* @retval kStatus_Success
|
||||
*/
|
||||
status_t SDIO_ReadCIS(sdio_card_t *card, sdio_func_num_t func, const uint32_t *tupleList, uint32_t tupleNum);
|
||||
|
||||
/*!
|
||||
* @brief sdio wait card detect function.
|
||||
*
|
||||
* Detect card through GPIO, CD, DATA3.
|
||||
*
|
||||
* @param card card descriptor.
|
||||
* @param card detect configuration
|
||||
* @param waitCardStatus wait card detect status
|
||||
*/
|
||||
status_t SDIO_WaitCardDetectStatus(SDMMCHOST_TYPE *hostBase,
|
||||
const sdmmchost_detect_card_t *cd,
|
||||
bool waitCardStatus);
|
||||
|
||||
/*!
|
||||
* @brief sdio card present check function.
|
||||
*
|
||||
* @param card card descriptor.
|
||||
*/
|
||||
bool SDIO_IsCardPresent(sdio_card_t *card);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name IO operations
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief IO direct write transfer function
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param function IO numner
|
||||
* @param register address
|
||||
* @param the data pinter to write
|
||||
* @param raw flag, indicate read after write or write only
|
||||
* @retval kStatus_SDMMC_TransferFailed
|
||||
* @retval kStatus_Success
|
||||
*/
|
||||
status_t SDIO_IO_Write_Direct(sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *data, bool raw);
|
||||
|
||||
/*!
|
||||
* @brief IO direct read transfer function
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param function IO number
|
||||
* @param register address
|
||||
* @param data pointer to read
|
||||
* @retval kStatus_SDMMC_TransferFailed
|
||||
* @retval kStatus_Success
|
||||
*/
|
||||
status_t SDIO_IO_Read_Direct(sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *data);
|
||||
|
||||
/*!
|
||||
* @brief IO direct read/write transfer function
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param direction io access direction, please reference sdio_io_direction_t.
|
||||
* @param function IO number
|
||||
* @param register address
|
||||
* @param dataIn data to write
|
||||
* @param dataOut data pointer for readback data, support both for read and write, when application want readback
|
||||
* the data after write command, dataOut should not be NULL.
|
||||
* @retval kStatus_SDMMC_TransferFailed
|
||||
* @retval kStatus_Success
|
||||
*/
|
||||
|
||||
status_t SDIO_IO_RW_Direct(sdio_card_t *card,
|
||||
sdio_io_direction_t direction,
|
||||
sdio_func_num_t func,
|
||||
uint32_t regAddr,
|
||||
uint8_t dataIn,
|
||||
uint8_t *dataOut);
|
||||
|
||||
/*!
|
||||
* @brief IO extended write transfer function
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param function IO number
|
||||
* @param register address
|
||||
* @param data buffer to write
|
||||
* @param data count
|
||||
* @param write flags
|
||||
* @retval kStatus_SDMMC_TransferFailed
|
||||
* @retval kStatus_SDMMC_SDIO_InvalidArgument
|
||||
* @retval kStatus_Success
|
||||
*/
|
||||
status_t SDIO_IO_Write_Extended(
|
||||
sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *buffer, uint32_t count, uint32_t flags);
|
||||
/*!
|
||||
* @brief IO extended read transfer function
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param function IO number
|
||||
* @param register address
|
||||
* @param data buffer to read
|
||||
* @param data count
|
||||
* @param write flags
|
||||
* @retval kStatus_SDMMC_TransferFailed
|
||||
* @retval kStatus_SDMMC_SDIO_InvalidArgument
|
||||
* @retval kStatus_Success
|
||||
*/
|
||||
status_t SDIO_IO_Read_Extended(
|
||||
sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *buffer, uint32_t count, uint32_t flags);
|
||||
/*!
|
||||
* @brief enable IO interrupt
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param function IO number
|
||||
* @param enable/disable flag
|
||||
* @retval kStatus_SDMMC_TransferFailed
|
||||
* @retval kStatus_Success
|
||||
*/
|
||||
status_t SDIO_EnableIOInterrupt(sdio_card_t *card, sdio_func_num_t func, bool enable);
|
||||
|
||||
/*!
|
||||
* @brief enable IO and wait IO ready
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param function IO number
|
||||
* @param enable/disable flag
|
||||
* @retval kStatus_SDMMC_TransferFailed
|
||||
* @retval kStatus_Success
|
||||
*/
|
||||
status_t SDIO_EnableIO(sdio_card_t *card, sdio_func_num_t func, bool enable);
|
||||
|
||||
/*!
|
||||
* @brief select IO
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param function IO number
|
||||
* @retval kStatus_SDMMC_TransferFailed
|
||||
* @retval kStatus_Success
|
||||
*/
|
||||
status_t SDIO_SelectIO(sdio_card_t *card, sdio_func_num_t func);
|
||||
|
||||
/*!
|
||||
* @brief Abort IO transfer
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param function IO number
|
||||
* @retval kStatus_SDMMC_TransferFailed
|
||||
* @retval kStatus_Success
|
||||
*/
|
||||
status_t SDIO_AbortIO(sdio_card_t *card, sdio_func_num_t func);
|
||||
|
||||
/*!
|
||||
* @brief Set driver strength.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param driverStrength target driver strength.
|
||||
* @retval kStatus_SDMMC_TransferFailed
|
||||
* @retval kStatus_Success
|
||||
*/
|
||||
status_t SDIO_SetDriverStrength(sdio_card_t *card, sd_driver_strength_t driverStrength);
|
||||
|
||||
/*!
|
||||
* @brief Enable/Disable Async interrupt.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param func function io number.
|
||||
* @param enable true is enable, false is disable.
|
||||
* @retval kStatus_SDMMC_TransferFailed
|
||||
* @retval kStatus_Success
|
||||
*/
|
||||
status_t SDIO_EnableAsyncInterrupt(sdio_card_t *card, bool enable);
|
||||
|
||||
/*!
|
||||
* @brief Get pending interrupt.
|
||||
*
|
||||
* @param card Card descriptor.
|
||||
* @param pendingInt pointer store pending interrupt
|
||||
* @retval kStatus_SDMMC_TransferFailed
|
||||
* @retval kStatus_Success
|
||||
*/
|
||||
status_t SDIO_GetPendingInterrupt(sdio_card_t *card, uint8_t *pendingInt);
|
||||
|
||||
/*!
|
||||
* @brief sdio card io transfer function.
|
||||
* This function can be used for trnansfer direct/extend command.
|
||||
* Please pay attention to the non-align data buffer address transfer,
|
||||
* if data buffer address can not meet host controller internal DMA requirement, sdio driver will try to use
|
||||
internal align buffer if data size is not bigger than internal buffer size,
|
||||
* Align address transfer always can get a better performance, so if application want sdio driver make sure buffer
|
||||
address align,
|
||||
* please redefine the SDMMC_GLOBAL_BUFFER_SIZE macro to a value which is big enough for your application.
|
||||
*
|
||||
* @param card card descriptor.
|
||||
* @param cmd command to transfer
|
||||
* @param argument argument to transfer
|
||||
* @param blockSize used for block mode.
|
||||
* @param txData tx buffer pointer or NULL
|
||||
* @param rxData rx buffer pointer or NULL
|
||||
* @param dataSize transfer data size
|
||||
* @param response reponse pointer, if application want read response back, please set it to a NON-NULL pointer.
|
||||
|
||||
*/
|
||||
status_t SDIO_IO_Transfer(sdio_card_t *card,
|
||||
sdio_command_t cmd,
|
||||
uint32_t argument,
|
||||
uint32_t blockSize,
|
||||
uint8_t *txData,
|
||||
uint8_t *rxData,
|
||||
uint16_t dataSize,
|
||||
uint32_t *response);
|
||||
|
||||
/*!
|
||||
* @brief sdio set io IRQ handler.
|
||||
*
|
||||
* @param card card descriptor.
|
||||
* @param func function io number.
|
||||
* @param handler, io IRQ handler.
|
||||
*/
|
||||
void SDIO_SetIOIRQHandler(sdio_card_t *card, sdio_func_num_t func, sdio_io_irq_handler_t handler);
|
||||
|
||||
/*!
|
||||
* @brief sdio card io pending interrupt handle function.
|
||||
* This function is used to handle the pending io interrupt.
|
||||
* To reigster a IO IRQ handler,
|
||||
* @code
|
||||
* //initialization
|
||||
* SDIO_EnableIOInterrupt(card, 0, true);
|
||||
* SDIO_SetIOIRQHandler(card, 0, func0_handler);
|
||||
* //call it in interrupt callback
|
||||
* SDIO_HandlePendingIOInterrupt(card);
|
||||
* @code
|
||||
* To releae a IO IRQ handler,
|
||||
* @code
|
||||
* SDIO_EnableIOInterrupt(card, 0, false);
|
||||
* SDIO_SetIOIRQHandler(card, 0, NULL);
|
||||
* @code
|
||||
* @param card card descriptor.
|
||||
*
|
||||
* @retval kStatus_SDMMC_TransferFailed
|
||||
* @retval kStatus_Success
|
||||
*/
|
||||
status_t SDIO_HandlePendingIOInterrupt(sdio_card_t *card);
|
||||
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
/*! @} */
|
||||
#endif /* _FSL_SDIO_H_*/
|
||||
|
|
@ -0,0 +1,258 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _FSL_SDMMC_COMMON_H_
|
||||
#define _FSL_SDMMC_COMMON_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_sdmmc_host.h"
|
||||
#include "fsl_sdmmc_spec.h"
|
||||
#include "stdlib.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup CARD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/*! @brief Middleware version. */
|
||||
#define FSL_SDMMC_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 11U)) /*2.2.11*/
|
||||
|
||||
/*! @brief Reverse byte sequence in uint32_t */
|
||||
#define SWAP_WORD_BYTE_SEQUENCE(x) (__REV(x))
|
||||
/*! @brief Reverse byte sequence for each half word in uint32_t */
|
||||
#define SWAP_HALF_WROD_BYTE_SEQUENCE(x) (__REV16(x))
|
||||
/*! @brief Maximum loop count to check the card operation voltage range */
|
||||
#define FSL_SDMMC_MAX_VOLTAGE_RETRIES (1000U)
|
||||
/*! @brief Maximum loop count to send the cmd */
|
||||
#define FSL_SDMMC_MAX_CMD_RETRIES (10U)
|
||||
/*! @brief Default block size */
|
||||
#define FSL_SDMMC_DEFAULT_BLOCK_SIZE (512U)
|
||||
#ifndef SDMMC_GLOBAL_BUFFER_SIZE
|
||||
/*! @brief SDMMC global data buffer size, word unit*/
|
||||
#define SDMMC_GLOBAL_BUFFER_SIZE (128U)
|
||||
#endif
|
||||
/*! @brief SDMMC enable software tuning */
|
||||
#define SDMMC_ENABLE_SOFTWARE_TUNING (0U)
|
||||
/* Common definition for cache line size align */
|
||||
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
|
||||
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||
#if defined(FSL_FEATURE_L2DCACHE_LINESIZE_BYTE)
|
||||
#define SDMMC_DATA_BUFFER_ALIGN_CACHE MAX(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE, FSL_FEATURE_L2DCACHE_LINESIZE_BYTE)
|
||||
#else
|
||||
#define SDMMC_DATA_BUFFER_ALIGN_CACHE FSL_FEATURE_L1DCACHE_LINESIZE_BYTE
|
||||
#endif
|
||||
#else
|
||||
#define SDMMC_DATA_BUFFER_ALIGN_CACHE 1
|
||||
#endif
|
||||
#else
|
||||
#define SDMMC_DATA_BUFFER_ALIGN_CACHE 1
|
||||
#endif
|
||||
|
||||
/*! @brief SD/MMC error log. */
|
||||
#if defined SDMMC_ENABLE_LOG_PRINT
|
||||
#include "fsl_debug_console.h"
|
||||
#define SDMMC_LOG(...) PRINTF(__VA_ARGS__)
|
||||
#else
|
||||
#define SDMMC_LOG(format, ...)
|
||||
#endif
|
||||
|
||||
/*! @brief SD/MMC card API's running status. */
|
||||
enum _sdmmc_status
|
||||
{
|
||||
kStatus_SDMMC_NotSupportYet = MAKE_STATUS(kStatusGroup_SDMMC, 0U), /*!< Haven't supported */
|
||||
kStatus_SDMMC_TransferFailed = MAKE_STATUS(kStatusGroup_SDMMC, 1U), /*!< Send command failed */
|
||||
kStatus_SDMMC_SetCardBlockSizeFailed = MAKE_STATUS(kStatusGroup_SDMMC, 2U), /*!< Set block size failed */
|
||||
kStatus_SDMMC_HostNotSupport = MAKE_STATUS(kStatusGroup_SDMMC, 3U), /*!< Host doesn't support */
|
||||
kStatus_SDMMC_CardNotSupport = MAKE_STATUS(kStatusGroup_SDMMC, 4U), /*!< Card doesn't support */
|
||||
kStatus_SDMMC_AllSendCidFailed = MAKE_STATUS(kStatusGroup_SDMMC, 5U), /*!< Send CID failed */
|
||||
kStatus_SDMMC_SendRelativeAddressFailed = MAKE_STATUS(kStatusGroup_SDMMC, 6U), /*!< Send relative address failed */
|
||||
kStatus_SDMMC_SendCsdFailed = MAKE_STATUS(kStatusGroup_SDMMC, 7U), /*!< Send CSD failed */
|
||||
kStatus_SDMMC_SelectCardFailed = MAKE_STATUS(kStatusGroup_SDMMC, 8U), /*!< Select card failed */
|
||||
kStatus_SDMMC_SendScrFailed = MAKE_STATUS(kStatusGroup_SDMMC, 9U), /*!< Send SCR failed */
|
||||
kStatus_SDMMC_SetDataBusWidthFailed = MAKE_STATUS(kStatusGroup_SDMMC, 10U), /*!< Set bus width failed */
|
||||
kStatus_SDMMC_GoIdleFailed = MAKE_STATUS(kStatusGroup_SDMMC, 11U), /*!< Go idle failed */
|
||||
kStatus_SDMMC_HandShakeOperationConditionFailed =
|
||||
MAKE_STATUS(kStatusGroup_SDMMC, 12U), /*!< Send Operation Condition failed */
|
||||
kStatus_SDMMC_SendApplicationCommandFailed =
|
||||
MAKE_STATUS(kStatusGroup_SDMMC, 13U), /*!< Send application command failed */
|
||||
kStatus_SDMMC_SwitchFailed = MAKE_STATUS(kStatusGroup_SDMMC, 14U), /*!< Switch command failed */
|
||||
kStatus_SDMMC_StopTransmissionFailed = MAKE_STATUS(kStatusGroup_SDMMC, 15U), /*!< Stop transmission failed */
|
||||
kStatus_SDMMC_WaitWriteCompleteFailed = MAKE_STATUS(kStatusGroup_SDMMC, 16U), /*!< Wait write complete failed */
|
||||
kStatus_SDMMC_SetBlockCountFailed = MAKE_STATUS(kStatusGroup_SDMMC, 17U), /*!< Set block count failed */
|
||||
kStatus_SDMMC_SetRelativeAddressFailed = MAKE_STATUS(kStatusGroup_SDMMC, 18U), /*!< Set relative address failed */
|
||||
kStatus_SDMMC_SwitchBusTimingFailed = MAKE_STATUS(kStatusGroup_SDMMC, 19U), /*!< Switch high speed failed */
|
||||
kStatus_SDMMC_SendExtendedCsdFailed = MAKE_STATUS(kStatusGroup_SDMMC, 20U), /*!< Send EXT_CSD failed */
|
||||
kStatus_SDMMC_ConfigureBootFailed = MAKE_STATUS(kStatusGroup_SDMMC, 21U), /*!< Configure boot failed */
|
||||
kStatus_SDMMC_ConfigureExtendedCsdFailed = MAKE_STATUS(kStatusGroup_SDMMC, 22U), /*!< Configure EXT_CSD failed */
|
||||
kStatus_SDMMC_EnableHighCapacityEraseFailed =
|
||||
MAKE_STATUS(kStatusGroup_SDMMC, 23U), /*!< Enable high capacity erase failed */
|
||||
kStatus_SDMMC_SendTestPatternFailed = MAKE_STATUS(kStatusGroup_SDMMC, 24U), /*!< Send test pattern failed */
|
||||
kStatus_SDMMC_ReceiveTestPatternFailed = MAKE_STATUS(kStatusGroup_SDMMC, 25U), /*!< Receive test pattern failed */
|
||||
kStatus_SDMMC_SDIO_ResponseError = MAKE_STATUS(kStatusGroup_SDMMC, 26U), /*!< sdio response error */
|
||||
kStatus_SDMMC_SDIO_InvalidArgument =
|
||||
MAKE_STATUS(kStatusGroup_SDMMC, 27U), /*!< sdio invalid argument response error */
|
||||
kStatus_SDMMC_SDIO_SendOperationConditionFail =
|
||||
MAKE_STATUS(kStatusGroup_SDMMC, 28U), /*!< sdio send operation condition fail */
|
||||
kStatus_SDMMC_InvalidVoltage = MAKE_STATUS(kStatusGroup_SDMMC, 29U), /*!< invaild voltage */
|
||||
kStatus_SDMMC_SDIO_SwitchHighSpeedFail = MAKE_STATUS(kStatusGroup_SDMMC, 30U), /*!< switch to high speed fail */
|
||||
kStatus_SDMMC_SDIO_ReadCISFail = MAKE_STATUS(kStatusGroup_SDMMC, 31U), /*!< read CIS fail */
|
||||
kStatus_SDMMC_SDIO_InvalidCard = MAKE_STATUS(kStatusGroup_SDMMC, 32U), /*!< invaild SDIO card */
|
||||
kStatus_SDMMC_TuningFail = MAKE_STATUS(kStatusGroup_SDMMC, 33U), /*!< tuning fail */
|
||||
|
||||
kStatus_SDMMC_SwitchVoltageFail = MAKE_STATUS(kStatusGroup_SDMMC, 34U), /*!< switch voltage fail*/
|
||||
kStatus_SDMMC_SwitchVoltage18VFail33VSuccess = MAKE_STATUS(kStatusGroup_SDMMC, 35U), /*!< switch voltage fail*/
|
||||
|
||||
kStatus_SDMMC_ReTuningRequest = MAKE_STATUS(kStatusGroup_SDMMC, 36U), /*!< retuning request */
|
||||
kStatus_SDMMC_SetDriverStrengthFail = MAKE_STATUS(kStatusGroup_SDMMC, 37U), /*!< set driver strength fail */
|
||||
kStatus_SDMMC_SetPowerClassFail = MAKE_STATUS(kStatusGroup_SDMMC, 38U), /*!< set power class fail */
|
||||
kStatus_SDMMC_HostNotReady = MAKE_STATUS(kStatusGroup_SDMMC, 39U), /*!< host controller not ready */
|
||||
kStatus_SDMMC_CardDetectFailed = MAKE_STATUS(kStatusGroup_SDMMC, 40U), /*!< card detect failed */
|
||||
kStatus_SDMMC_AuSizeNotSetProperly = MAKE_STATUS(kStatusGroup_SDMMC, 41U), /*!< AU size not set properly */
|
||||
|
||||
};
|
||||
|
||||
/*! @brief card operation voltage */
|
||||
typedef enum _sdmmc_operation_voltage
|
||||
{
|
||||
kCARD_OperationVoltageNone = 0U, /*!< indicate current voltage setting is not setting by suser*/
|
||||
kCARD_OperationVoltage330V = 1U, /*!< card operation voltage around 3.3v */
|
||||
kCARD_OperationVoltage300V = 2U, /*!< card operation voltage around 3.0v */
|
||||
kCARD_OperationVoltage180V = 3U, /*!< card operation voltage around 1.8v */
|
||||
} sdmmc_operation_voltage_t;
|
||||
|
||||
/*************************************************************************************************
|
||||
* API
|
||||
************************************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
/*!
|
||||
* @name common function
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Selects the card to put it into transfer state.
|
||||
*
|
||||
* @param base SDMMCHOST peripheral base address.
|
||||
* @param transfer SDMMCHOST transfer function.
|
||||
* @param relativeAddress Relative address.
|
||||
* @param isSelected True to put card into transfer state.
|
||||
* @retval kStatus_SDMMC_TransferFailed Transfer failed.
|
||||
* @retval kStatus_Success Operate successfully.
|
||||
*/
|
||||
status_t SDMMC_SelectCard(SDMMCHOST_TYPE *base,
|
||||
SDMMCHOST_TRANSFER_FUNCTION transfer,
|
||||
uint32_t relativeAddress,
|
||||
bool isSelected);
|
||||
|
||||
/*!
|
||||
* @brief Sends an application command.
|
||||
*
|
||||
* @param base SDMMCHOST peripheral base address.
|
||||
* @param transfer SDMMCHOST transfer function.
|
||||
* @param relativeAddress Card relative address.
|
||||
* @retval kStatus_SDMMC_TransferFailed Transfer failed.
|
||||
* @retval kStatus_SDMMC_CardNotSupport Card doesn't support.
|
||||
* @retval kStatus_Success Operate successfully.
|
||||
*/
|
||||
status_t SDMMC_SendApplicationCommand(SDMMCHOST_TYPE *base,
|
||||
SDMMCHOST_TRANSFER_FUNCTION transfer,
|
||||
uint32_t relativeAddress);
|
||||
|
||||
/*!
|
||||
* @brief Sets the block count.
|
||||
*
|
||||
* @param base SDMMCHOST peripheral base address.
|
||||
* @param transfer SDMMCHOST transfer function.
|
||||
* @param blockCount Block count.
|
||||
* @retval kStatus_SDMMC_TransferFailed Transfer failed.
|
||||
* @retval kStatus_Success Operate successfully.
|
||||
*/
|
||||
status_t SDMMC_SetBlockCount(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer, uint32_t blockCount);
|
||||
|
||||
/*!
|
||||
* @brief Sets the card to be idle state.
|
||||
*
|
||||
* @param base SDMMCHOST peripheral base address.
|
||||
* @param transfer SDMMCHOST transfer function.
|
||||
* @retval kStatus_SDMMC_TransferFailed Transfer failed.
|
||||
* @retval kStatus_Success Operate successfully.
|
||||
*/
|
||||
status_t SDMMC_GoIdle(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer);
|
||||
|
||||
/*!
|
||||
* @brief Sets data block size.
|
||||
*
|
||||
* @param base SDMMCHOST peripheral base address.
|
||||
* @param transfer SDMMCHOST transfer function.
|
||||
* @param blockSize Block size.
|
||||
* @retval kStatus_SDMMC_TransferFailed Transfer failed.
|
||||
* @retval kStatus_Success Operate successfully.
|
||||
*/
|
||||
status_t SDMMC_SetBlockSize(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer, uint32_t blockSize);
|
||||
|
||||
/*!
|
||||
* @brief Sets card to inactive status
|
||||
*
|
||||
* @param base SDMMCHOST peripheral base address.
|
||||
* @param transfer SDMMCHOST transfer function.
|
||||
* @retval kStatus_SDMMC_TransferFailed Transfer failed.
|
||||
* @retval kStatus_Success Operate successfully.
|
||||
*/
|
||||
status_t SDMMC_SetCardInactive(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer);
|
||||
|
||||
/*!
|
||||
* @brief provide a simple delay function for sdmmc
|
||||
*
|
||||
* @param num Delay num*10000.
|
||||
*/
|
||||
void SDMMC_Delay(uint32_t num);
|
||||
|
||||
/*!
|
||||
* @brief provide a voltage switch function for SD/SDIO card
|
||||
* @deprecated Do not use this function, it has been superceded by SDMMC_SwitchToVoltage.
|
||||
* @param base SDMMCHOST peripheral base address.
|
||||
* @param transfer SDMMCHOST transfer function.
|
||||
*/
|
||||
status_t SDMMC_SwitchVoltage(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer);
|
||||
|
||||
/*!
|
||||
* @brief provide a voltage switch function for SD/SDIO card
|
||||
*
|
||||
* @param base SDMMCHOST peripheral base address.
|
||||
* @param transfer SDMMCHOST transfer function.
|
||||
* @param switchVoltageFunc voltage switch function.
|
||||
* @return error code.
|
||||
*/
|
||||
|
||||
status_t SDMMC_SwitchToVoltage(SDMMCHOST_TYPE *base,
|
||||
SDMMCHOST_TRANSFER_FUNCTION transfer,
|
||||
sdmmchost_card_switch_voltage_t switchVoltageFunc);
|
||||
/*!
|
||||
* @brief excute tuning
|
||||
*
|
||||
* @param base SDMMCHOST peripheral base address.
|
||||
* @param transfer Host transfer function
|
||||
* @param tuningCmd Tuning cmd
|
||||
* @param blockSize Tuning block size
|
||||
*/
|
||||
status_t SDMMC_ExecuteTuning(SDMMCHOST_TYPE *base,
|
||||
SDMMCHOST_TRANSFER_FUNCTION transfer,
|
||||
uint32_t tuningCmd,
|
||||
uint32_t blockSize);
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
/* @} */
|
||||
#endif /* _FSL_SDMMC_COMMON_H_ */
|
||||
|
|
@ -0,0 +1,780 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _FSL_SDMMC_HOST_H
|
||||
#define _FSL_SDMMC_HOST_H
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "board.h"
|
||||
#if defined(FSL_FEATURE_SOC_SDHC_COUNT) && FSL_FEATURE_SOC_SDHC_COUNT > 0U
|
||||
#include "fsl_sdhc.h"
|
||||
#elif defined(FSL_FEATURE_SOC_SDIF_COUNT) && FSL_FEATURE_SOC_SDIF_COUNT > 0U
|
||||
#include "fsl_sdif.h"
|
||||
#elif defined(FSL_FEATURE_SOC_USDHC_COUNT) && FSL_FEATURE_SOC_USDHC_COUNT > 0U
|
||||
#include "fsl_usdhc.h"
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @addtogroup SDMMCHOST
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/* Common definition for support and not support macro */
|
||||
#define SDMMCHOST_NOT_SUPPORT 0U /*!< use this define to indicate the host not support feature*/
|
||||
#define SDMMCHOST_SUPPORT 1U /*!< use this define to indicate the host support feature*/
|
||||
|
||||
/* Common definition for board support SDR104/HS200/HS400 frequency */
|
||||
/* SDR104 mode freq */
|
||||
#if defined BOARD_SD_HOST_SUPPORT_SDR104_FREQ
|
||||
#define SDMMCHOST_SUPPORT_SDR104_FREQ BOARD_SD_HOST_SUPPORT_SDR104_FREQ
|
||||
#else
|
||||
#define SDMMCHOST_SUPPORT_SDR104_FREQ SD_CLOCK_208MHZ
|
||||
#endif
|
||||
/* HS200 mode freq */
|
||||
#if defined BOARD_SD_HOST_SUPPORT_HS200_FREQ
|
||||
#define SDMMCHOST_SUPPORT_HS200_FREQ BOARD_SD_HOST_SUPPORT_HS200_FREQ
|
||||
#else
|
||||
#define SDMMCHOST_SUPPORT_HS200_FREQ MMC_CLOCK_HS200
|
||||
#endif
|
||||
/* HS400 mode freq */
|
||||
#if defined BOARD_SD_HOST_SUPPORT_HS400_FREQ
|
||||
#define SDMMCHOST_SUPPORT_HS400_FREQ BOARD_SD_HOST_SUPPORT_HS400_FREQ
|
||||
#else
|
||||
#define SDMMCHOST_SUPPORT_HS400_FREQ MMC_CLOCK_HS400
|
||||
#endif
|
||||
|
||||
/* Common definition for SDMMCHOST transfer complete timeout */
|
||||
#define SDMMCHOST_TRANSFER_COMPLETE_TIMEOUT (500U)
|
||||
/* Common definition for card detect timeout */
|
||||
#define SDMMCHOST_CARD_DETECT_TIMEOUT (~0U)
|
||||
|
||||
/* Common definition for IRQ */
|
||||
#if defined(__CORTEX_M)
|
||||
#define SDMMCHOST_SET_IRQ_PRIORITY(id, priority) (NVIC_SetPriority(id, priority))
|
||||
#else
|
||||
#define SDMMCHOST_SET_IRQ_PRIORITY(id, priority) (GIC_SetPriority(id, priority))
|
||||
#endif
|
||||
|
||||
#define SDMMCHOST_ENABLE_IRQ(id) (EnableIRQ(id))
|
||||
|
||||
/*********************************************************SDHC**********************************************************/
|
||||
#if (defined(FSL_FEATURE_SOC_SDHC_COUNT) && (FSL_FEATURE_SOC_SDHC_COUNT > 0U))
|
||||
|
||||
/*define host baseaddr ,clk freq, IRQ number*/
|
||||
#define MMC_HOST_BASEADDR BOARD_SDHC_BASEADDR
|
||||
#define MMC_HOST_CLK_FREQ BOARD_SDHC_CLK_FREQ
|
||||
#define MMC_HOST_IRQ BOARD_SDHC_IRQ
|
||||
#define SD_HOST_BASEADDR BOARD_SDHC_BASEADDR
|
||||
#define SD_HOST_CLK_FREQ BOARD_SDHC_CLK_FREQ
|
||||
#define SD_HOST_IRQ BOARD_SDHC_IRQ
|
||||
|
||||
/* define for card bus speed/strength cnofig */
|
||||
#define CARD_BUS_FREQ_50MHZ (0U)
|
||||
#define CARD_BUS_FREQ_100MHZ0 (0U)
|
||||
#define CARD_BUS_FREQ_100MHZ1 (0U)
|
||||
#define CARD_BUS_FREQ_200MHZ (0U)
|
||||
|
||||
#define CARD_BUS_STRENGTH_0 (0U)
|
||||
#define CARD_BUS_STRENGTH_1 (0U)
|
||||
#define CARD_BUS_STRENGTH_2 (0U)
|
||||
#define CARD_BUS_STRENGTH_3 (0U)
|
||||
#define CARD_BUS_STRENGTH_4 (0U)
|
||||
#define CARD_BUS_STRENGTH_5 (0U)
|
||||
#define CARD_BUS_STRENGTH_6 (0U)
|
||||
#define CARD_BUS_STRENGTH_7 (0U)
|
||||
|
||||
#define SDMMCHOST_TYPE SDHC_Type
|
||||
#define SDMMCHOST_CONFIG sdhc_host_t
|
||||
#define SDMMCHOST_TRANSFER sdhc_transfer_t
|
||||
#define SDMMCHOST_COMMAND sdhc_command_t
|
||||
#define SDMMCHOST_DATA sdhc_data_t
|
||||
#define SDMMCHOST_BUS_WIDTH_TYPE sdhc_data_bus_width_t
|
||||
#define SDMMCHOST_CAPABILITY sdhc_capability_t
|
||||
#define SDMMCHOST_BOOT_CONFIG sdhc_boot_config_t
|
||||
|
||||
#define CARD_DATA0_STATUS_MASK (kSDHC_Data0LineLevelFlag)
|
||||
#define CARD_DATA0_NOT_BUSY (kSDHC_Data0LineLevelFlag)
|
||||
#define CARD_DATA1_STATUS_MASK (kSDHC_Data1LineLevelFlag)
|
||||
#define CARD_DATA2_STATUS_MASK (kSDHC_Data2LineLevelFlag)
|
||||
#define CARD_DATA3_STATUS_MASK (kSDHC_Data3LineLevelFlag)
|
||||
|
||||
#define kSDMMCHOST_DATABUSWIDTH1BIT kSDHC_DataBusWidth1Bit /*!< 1-bit mode */
|
||||
#define kSDMMCHOST_DATABUSWIDTH4BIT kSDHC_DataBusWidth4Bit /*!< 4-bit mode */
|
||||
#define kSDMMCHOST_DATABUSWIDTH8BIT kSDHC_DataBusWidth8Bit /*!< 8-bit mode */
|
||||
|
||||
#define SDMMCHOST_STANDARD_TUNING_START (0U) /*!< standard tuning start point */
|
||||
#define SDMMCHOST_TUINIG_STEP (1U) /*!< standard tuning step */
|
||||
#define SDMMCHOST_RETUNING_TIMER_COUNT (4U) /*!< Re-tuning timer */
|
||||
#define SDMMCHOST_TUNING_DELAY_MAX (0x7FU)
|
||||
#define SDMMCHOST_RETUNING_REQUEST (1U)
|
||||
#define SDMMCHOST_TUNING_ERROR (2U)
|
||||
|
||||
/* function pointer define */
|
||||
#define SDMMCHOST_TRANSFER_FUNCTION sdhc_transfer_function_t
|
||||
#define GET_SDMMCHOST_CAPABILITY(base, capability) (SDHC_GetCapability(base, capability))
|
||||
#define GET_SDMMCHOST_STATUS(base) (SDHC_GetPresentStatusFlags(base))
|
||||
#define SDMMCHOST_SET_CARD_CLOCK(base, sourceClock_HZ, busClock_HZ) (SDHC_SetSdClock(base, sourceClock_HZ, busClock_HZ))
|
||||
#define SDMMCHOST_SET_CARD_BUS_WIDTH(base, busWidth) (SDHC_SetDataBusWidth(base, busWidth))
|
||||
#define SDMMCHOST_SEND_CARD_ACTIVE(base, timeout) (SDHC_SetCardActive(base, timeout))
|
||||
#define SDMMCHOST_SWITCH_VOLTAGE180V(base, enable18v)
|
||||
#define SDMMCHOST_SWITCH_VOLTAGE120V(base, enable12v)
|
||||
#define SDMMCHOST_CONFIG_IO_STRENGTH(speed, strength)
|
||||
#define SDMMCHOST_EXECUTE_STANDARD_TUNING_ENABLE(base, flag)
|
||||
#define SDMMCHOST_EXECUTE_STANDARD_TUNING_STATUS(base) (0U)
|
||||
#define SDMMCHOST_EXECUTE_STANDARD_TUNING_RESULT(base) (1U)
|
||||
#define SDMMCHOST_CONFIG_SD_IO(speed, strength)
|
||||
#define SDMMCHOST_CONFIG_MMC_IO(speed, strength)
|
||||
#define SDMMCHOST_ENABLE_DDR_MODE(base, flag, nibblePos)
|
||||
#define SDMMCHOST_FORCE_SDCLOCK_ON(base, enable)
|
||||
#define SDMMCHOST_EXECUTE_MANUAL_TUNING_ENABLE(base, flag)
|
||||
#define SDMMCHOST_ADJUST_MANUAL_TUNING_DELAY(base, delay)
|
||||
#define SDMMCHOST_AUTO_MANUAL_TUNING_ENABLE(base, flag)
|
||||
#define SDMMCHOST_ENABLE_CARD_CLOCK(base, enable) (SDHC_EnableSdClock(base, enable))
|
||||
#define SDMMCHOST_RESET_TUNING(base, timeout)
|
||||
#define SDMMCHOST_CHECK_TUNING_ERROR(base) (0U)
|
||||
#define SDMMCHOST_ADJUST_TUNING_DELAY(base, delay)
|
||||
#define SDMMCHOST_AUTO_STANDARD_RETUNING_TIMER(base)
|
||||
#define SDMMCHOST_TRANSFER_DATA_ERROR kStatus_SDHC_TransferDataFailed
|
||||
#define SDMMCHOST_TRANSFER_CMD_ERROR kStatus_SDHC_SendCommandFailed
|
||||
#define SDMMCHOST_ENABLE_HS400_MODE(base, flag)
|
||||
#define SDMMCHOST_RESET_STROBE_DLL(base)
|
||||
#define SDMMCHOST_ENABLE_STROBE_DLL(base, flag)
|
||||
#define SDMMCHOST_CONFIG_STROBE_DLL(base, delay, updateInterval)
|
||||
#define SDMMCHOST_GET_STROBE_DLL_STATUS(base)
|
||||
/* sd card power */
|
||||
#define SDMMCHOST_INIT_SD_POWER()
|
||||
#define SDMMCHOST_ENABLE_SD_POWER(enable)
|
||||
#define SDMMCHOST_SWITCH_VCC_TO_180V()
|
||||
#define SDMMCHOST_SWITCH_VCC_TO_330V()
|
||||
/* mmc card power */
|
||||
#define SDMMCHOST_INIT_MMC_POWER()
|
||||
#define SDMMCHOST_ENABLE_MMC_POWER(enable)
|
||||
#define SDMMCHOST_ENABLE_TUNING_FLAG(data)
|
||||
#define SDMMCHOST_ENABLE_BOOT_FLAG(data)
|
||||
#define SDMMCHOST_ENABLE_BOOT_CONTINOUS_FLAG(data)
|
||||
#define SDMMCHOST_GET_HOST_CONFIG_BLOCK_SIZE(config) (0U)
|
||||
#define SDMMCHOST_GET_HOST_CONFIG_BLOCK_COUNT(config) (0U)
|
||||
#define SDMMCHOST_GET_HOST_CONFIG_BOOT_MODE(config) (0U)
|
||||
#define SDMMCHOST_EMPTY_CMD_FLAG(command)
|
||||
#define SDMMCHOST_CARD_DETECT_GPIO_INTERRUPT_HANDLER BOARD_SDHC_CD_PORT_IRQ_HANDLER
|
||||
#define SDMMCHOST_CARD_DETECT_IRQ BOARD_SDHC_CD_PORT_IRQ
|
||||
/* sd card detect through host CD */
|
||||
#define SDMMCHOST_CARD_DETECT_INSERT_ENABLE(base) (SDHC_EnableInterruptStatus(base, kSDHC_CardInsertionFlag))
|
||||
#define SDMMCHOST_CARD_DETECT_REMOVE_ENABLE(base) (SDHC_EnableInterruptStatus(base, kSDHC_CardRemovalFlag))
|
||||
#define SDMMCHOST_CARD_DETECT_INSERT_STATUS(base) (SDHC_GetInterruptStatusFlags(base) & kSDHC_CardInsertionFlag)
|
||||
#define SDMMCHOST_CARD_DETECT_REMOVE_STATUS(base) (SDHC_GetInterruptStatusFlags(base, kSDHC_CardRemovalFlag))
|
||||
#define SDMMCHOST_CARD_DETECT_INSERT_INTERRUPT_ENABLE(base) (SDHC_EnableInterruptSignal(base, kSDHC_CardInsertionFlag))
|
||||
#define SDMMCHOST_CARD_DETECT_INSERT_INTERRUPT_DISABLE(base) \
|
||||
(SDHC_DisableInterruptSignal(base, kSDHC_CardInsertionFlag))
|
||||
#define SDMMCHOST_CARD_DETECT_REMOVE_INTERRUPT_ENABLE(base) (SDHC_EnableInterruptSignal(base, kSDHC_CardRemovalFlag))
|
||||
#define SDMMCHOST_CARD_DETECT_DATA3_ENABLE(base, flag) (SDHC_CardDetectByData3(base, flag))
|
||||
#define SDMMCHOST_ENABLE_MMC_BOOT(base, flag)
|
||||
#define SDMMCHOST_SETMMCBOOTCONFIG(base, config) (SDHC_SetMmcBootConfig(base, config))
|
||||
/* define card detect pin voltage level when card inserted */
|
||||
#if defined BOARD_SDHC_CARD_INSERT_CD_LEVEL
|
||||
#define SDMMCHOST_CARD_INSERT_CD_LEVEL BOARD_SDHC_CARD_INSERT_CD_LEVEL
|
||||
#else
|
||||
#define SDMMCHOST_CARD_INSERT_CD_LEVEL (0U)
|
||||
#endif
|
||||
#define SDMMCHOST_AUTO_TUNING_ENABLE(base, flag)
|
||||
#define SDMMCHOST_ENABLE_SDIO_INT(base) \
|
||||
SDHC_EnableInterruptStatus(base, kSDHC_CardInterruptFlag); \
|
||||
SDHC_EnableInterruptSignal(base, kSDHC_CardInterruptFlag)
|
||||
#define SDMMCHOST_DISABLE_SDIO_INT(base) \
|
||||
SDHC_DisableInterruptStatus(base, kSDHC_CardInterruptFlag); \
|
||||
SDHC_DisableInterruptSignal(base, kSDHC_CardInterruptFlag)
|
||||
|
||||
/*! @brief SDHC host capability*/
|
||||
enum _host_capability
|
||||
{
|
||||
kSDMMCHOST_SupportAdma = kSDHC_SupportAdmaFlag,
|
||||
kSDMMCHOST_SupportHighSpeed = kSDHC_SupportHighSpeedFlag,
|
||||
kSDMMCHOST_SupportDma = kSDHC_SupportDmaFlag,
|
||||
kSDMMCHOST_SupportSuspendResume = kSDHC_SupportSuspendResumeFlag,
|
||||
kSDMMCHOST_SupportV330 = kSDHC_SupportV330Flag,
|
||||
kSDMMCHOST_SupportV300 = SDMMCHOST_NOT_SUPPORT,
|
||||
kSDMMCHOST_SupportV180 = SDMMCHOST_NOT_SUPPORT,
|
||||
kSDMMCHOST_SupportV120 = SDMMCHOST_NOT_SUPPORT,
|
||||
kSDMMCHOST_Support4BitBusWidth = kSDHC_Support4BitFlag,
|
||||
kSDMMCHOST_Support8BitBusWidth = kSDHC_Support8BitFlag,
|
||||
kSDMMCHOST_SupportDDR50 = SDMMCHOST_NOT_SUPPORT,
|
||||
kSDMMCHOST_SupportSDR104 = SDMMCHOST_NOT_SUPPORT,
|
||||
kSDMMCHOST_SupportSDR50 = SDMMCHOST_NOT_SUPPORT,
|
||||
kSDMMCHOST_SupportHS200 = SDMMCHOST_NOT_SUPPORT,
|
||||
kSDMMCHOST_SupportHS400 = SDMMCHOST_NOT_SUPPORT,
|
||||
};
|
||||
|
||||
/* Endian mode. */
|
||||
#define SDHC_ENDIAN_MODE kSDHC_EndianModeLittle
|
||||
|
||||
/* DMA mode */
|
||||
#define SDHC_DMA_MODE kSDHC_DmaModeAdma2
|
||||
/* address align */
|
||||
#define SDMMCHOST_DMA_BUFFER_ADDR_ALIGN (SDHC_ADMA2_ADDRESS_ALIGN)
|
||||
|
||||
/* Read/write watermark level. The bigger value indicates DMA has higher read/write performance. */
|
||||
#define SDHC_READ_WATERMARK_LEVEL (0x80U)
|
||||
#define SDHC_WRITE_WATERMARK_LEVEL (0x80U)
|
||||
|
||||
/* ADMA table length united as word.
|
||||
*
|
||||
* SD card driver can't support ADMA1 transfer mode currently.
|
||||
* One ADMA2 table item occupy two words which can transfer maximum 0xFFFFU bytes one time.
|
||||
* The more data to be transferred in one time, the bigger value of SDHC_ADMA_TABLE_WORDS need to be set.
|
||||
*/
|
||||
#define SDHC_ADMA_TABLE_WORDS (8U)
|
||||
|
||||
/*********************************************************SDIF**********************************************************/
|
||||
#elif (defined(FSL_FEATURE_SOC_SDIF_COUNT) && (FSL_FEATURE_SOC_SDIF_COUNT > 0U))
|
||||
|
||||
/*define host baseaddr ,clk freq, IRQ number*/
|
||||
#define MMC_HOST_BASEADDR BOARD_SDIF_BASEADDR
|
||||
#define MMC_HOST_CLK_FREQ BOARD_SDIF_CLK_FREQ
|
||||
#define MMC_HOST_IRQ BOARD_SDIF_IRQ
|
||||
#define SD_HOST_BASEADDR BOARD_SDIF_BASEADDR
|
||||
#define SD_HOST_CLK_FREQ BOARD_SDIF_CLK_FREQ
|
||||
#define SD_HOST_IRQ BOARD_SDIF_IRQ
|
||||
|
||||
/* define for card bus speed/strength cnofig */
|
||||
#define CARD_BUS_FREQ_50MHZ (0U)
|
||||
#define CARD_BUS_FREQ_100MHZ0 (0U)
|
||||
#define CARD_BUS_FREQ_100MHZ1 (0U)
|
||||
#define CARD_BUS_FREQ_200MHZ (0U)
|
||||
|
||||
#define CARD_BUS_STRENGTH_0 (0U)
|
||||
#define CARD_BUS_STRENGTH_1 (0U)
|
||||
#define CARD_BUS_STRENGTH_2 (0U)
|
||||
#define CARD_BUS_STRENGTH_3 (0U)
|
||||
#define CARD_BUS_STRENGTH_4 (0U)
|
||||
#define CARD_BUS_STRENGTH_5 (0U)
|
||||
#define CARD_BUS_STRENGTH_6 (0U)
|
||||
#define CARD_BUS_STRENGTH_7 (0U)
|
||||
|
||||
#define SDMMCHOST_TYPE SDIF_Type
|
||||
#define SDMMCHOST_CONFIG sdif_host_t
|
||||
#define SDMMCHOST_TRANSFER sdif_transfer_t
|
||||
#define SDMMCHOST_COMMAND sdif_command_t
|
||||
#define SDMMCHOST_DATA sdif_data_t
|
||||
#define SDMMCHOST_BUS_WIDTH_TYPE sdif_bus_width_t
|
||||
#define SDMMCHOST_CAPABILITY sdif_capability_t
|
||||
#define SDMMCHOST_BOOT_CONFIG void
|
||||
|
||||
#define CARD_DATA0_STATUS_MASK SDIF_STATUS_DATA_BUSY_MASK
|
||||
#define CARD_DATA0_NOT_BUSY 0U
|
||||
|
||||
#define CARD_DATA1_STATUS_MASK (0U)
|
||||
#define CARD_DATA2_STATUS_MASK (0U)
|
||||
#define CARD_DATA3_STATUS_MASK (0U)
|
||||
|
||||
#define kSDMMCHOST_DATABUSWIDTH1BIT kSDIF_Bus1BitWidth /*!< 1-bit mode */
|
||||
#define kSDMMCHOST_DATABUSWIDTH4BIT kSDIF_Bus4BitWidth /*!< 4-bit mode */
|
||||
#define kSDMMCHOST_DATABUSWIDTH8BIT kSDIF_Bus8BitWidth /*!< 8-bit mode */
|
||||
|
||||
#define SDMMCHOST_STANDARD_TUNING_START (0U) /*!< standard tuning start point */
|
||||
#define SDMMCHOST_TUINIG_STEP (1U) /*!< standard tuning step */
|
||||
#define SDMMCHOST_RETUNING_TIMER_COUNT (4U) /*!< Re-tuning timer */
|
||||
#define SDMMCHOST_TUNING_DELAY_MAX (0x7FU)
|
||||
#define SDMMCHOST_RETUNING_REQUEST (1U)
|
||||
#define SDMMCHOST_TUNING_ERROR (2U)
|
||||
/* function pointer define */
|
||||
#define SDMMCHOST_TRANSFER_FUNCTION sdif_transfer_function_t
|
||||
#define GET_SDMMCHOST_CAPABILITY(base, capability) (SDIF_GetCapability(base, capability))
|
||||
#define GET_SDMMCHOST_STATUS(base) (SDIF_GetControllerStatus(base))
|
||||
#define SDMMCHOST_SET_CARD_CLOCK(base, sourceClock_HZ, busClock_HZ) \
|
||||
(SDIF_SetCardClock(base, sourceClock_HZ, busClock_HZ))
|
||||
#define SDMMCHOST_SET_CARD_BUS_WIDTH(base, busWidth) (SDIF_SetCardBusWidth(base, busWidth))
|
||||
#define SDMMCHOST_SEND_CARD_ACTIVE(base, timeout) (SDIF_SendCardActive(base, timeout))
|
||||
#define SDMMCHOST_SWITCH_VOLTAGE180V(base, enable18v)
|
||||
#define SDMMCHOST_SWITCH_VOLTAGE120V(base, enable12v)
|
||||
#define SDMMCHOST_CONFIG_IO_STRENGTH(speed, strength)
|
||||
#define SDMMCHOST_EXECUTE_STANDARD_TUNING_ENABLE(base, flag)
|
||||
#define SDMMCHOST_EXECUTE_STANDARD_TUNING_STATUS(base) (0U)
|
||||
#define SDMMCHOST_EXECUTE_STANDARD_TUNING_RESULT(base) (1U)
|
||||
#define SDMMCHOST_CONFIG_SD_IO(speed, strength)
|
||||
#define SDMMCHOST_CONFIG_MMC_IO(speed, strength)
|
||||
#define SDMMCHOST_ENABLE_DDR_MODE(base, flag, nibblePos)
|
||||
#define SDMMCHOST_FORCE_SDCLOCK_ON(base, enable)
|
||||
#define SDMMCHOST_EXECUTE_MANUAL_TUNING_ENABLE(base, flag)
|
||||
#define SDMMCHOST_ADJUST_MANUAL_TUNING_DELAY(base, delay)
|
||||
#define SDMMCHOST_AUTO_MANUAL_TUNING_ENABLE(base, flag)
|
||||
#define SDMMCHOST_ENABLE_CARD_CLOCK(base, enable) (SDIF_EnableCardClock(base, enable))
|
||||
#define SDMMCHOST_RESET_TUNING(base, timeout)
|
||||
#define SDMMCHOST_CHECK_TUNING_ERROR(base) (0U)
|
||||
#define SDMMCHOST_ADJUST_TUNING_DELAY(base, delay)
|
||||
#define SDMMCHOST_AUTO_STANDARD_RETUNING_TIMER(base)
|
||||
|
||||
#define SDMMCHOST_ENABLE_HS400_MODE(base, flag)
|
||||
#define SDMMCHOST_RESET_STROBE_DLL(base)
|
||||
#define SDMMCHOST_ENABLE_STROBE_DLL(base, flag)
|
||||
#define SDMMCHOST_CONFIG_STROBE_DLL(base, delay, updateInterval)
|
||||
#define SDMMCHOST_GET_STROBE_DLL_STATUS(base)
|
||||
/* sd card power */
|
||||
#define SDMMCHOST_INIT_SD_POWER()
|
||||
#define SDMMCHOST_ENABLE_SD_POWER(enable)
|
||||
#define SDMMCHOST_SWITCH_VCC_TO_180V()
|
||||
#define SDMMCHOST_SWITCH_VCC_TO_330V()
|
||||
/* mmc card power */
|
||||
#define SDMMCHOST_INIT_MMC_POWER()
|
||||
#define SDMMCHOST_ENABLE_MMC_POWER(enable)
|
||||
#define SDMMCHOST_ENABLE_TUNING_FLAG(data)
|
||||
#define SDMMCHOST_ENABLE_MMC_BOOT(base, flag)
|
||||
#define SDMMCHOST_SETMMCBOOTCONFIG(base, config)
|
||||
#define SDMMCHOST_ENABLE_BOOT_FLAG(data)
|
||||
#define SDMMCHOST_ENABLE_BOOT_CONTINOUS_FLAG(data)
|
||||
#define SDMMCHOST_GET_HOST_CONFIG_BLOCK_SIZE(config) (0U)
|
||||
#define SDMMCHOST_GET_HOST_CONFIG_BLOCK_COUNT(config) (0U)
|
||||
#define SDMMCHOST_GET_HOST_CONFIG_BOOT_MODE(config) (0U)
|
||||
#define SDMMCHOST_EMPTY_CMD_FLAG(command)
|
||||
#define SDMMCHOST_CARD_DETECT_STATUS() BOARD_SDIF_CD_STATUS()
|
||||
#define SDMMCHOST_CARD_DETECT_INIT() BOARD_SDIF_CD_GPIO_INIT()
|
||||
#define SDMMCHOST_CARD_DETECT_INTERRUPT_STATUS() BOARD_SDIF_CD_INTERRUPT_STATUS()
|
||||
#define SDMMCHOST_CARD_DETECT_INTERRUPT_CLEAR(flag) BOARD_SDIF_CD_CLEAR_INTERRUPT(flag)
|
||||
#define SDMMCHOST_CARD_DETECT_GPIO_INTERRUPT_HANDLER BOARD_SDIF_CD_PORT_IRQ_HANDLER
|
||||
#define SDMMCHOST_CARD_DETECT_IRQ BOARD_SDIF_CD_PORT_IRQ
|
||||
#define SDMMCHOST_TRANSFER_DATA_ERROR kStatus_SDIF_DataTransferFail
|
||||
#define SDMMCHOST_TRANSFER_CMD_ERROR kStatus_SDIF_SendCmdFail
|
||||
/* define card detect pin voltage level when card inserted */
|
||||
#if defined BOARD_SDIF_CARD_INSERT_CD_LEVEL
|
||||
#define SDMMCHOST_CARD_INSERT_CD_LEVEL BOARD_SDIF_CARD_INSERT_CD_LEVEL
|
||||
#else
|
||||
#define SDMMCHOST_CARD_INSERT_CD_LEVEL (0U)
|
||||
#endif
|
||||
#define SDMMCHOST_AUTO_TUNING_ENABLE(base, flag)
|
||||
/* sd card detect through host CD */
|
||||
#define SDMMCHOST_CARD_DETECT_INSERT_ENABLE(base) (SDIF_EnableInterrupt(base, kSDIF_CardDetect))
|
||||
#define SDMMCHOST_CARD_DETECT_INSERT_STATUS(base, data3) (SDIF_DetectCardInsert(base, data3))
|
||||
#define SDMMCHOST_ENABLE_SDIO_INT(base)
|
||||
#define SDMMCHOST_DISABLE_SDIO_INT(base)
|
||||
/*! @brief SDIF host capability*/
|
||||
enum _host_capability
|
||||
{
|
||||
kSDMMCHOST_SupportHighSpeed = kSDIF_SupportHighSpeedFlag,
|
||||
kSDMMCHOST_SupportDma = kSDIF_SupportDmaFlag,
|
||||
kSDMMCHOST_SupportSuspendResume = kSDIF_SupportSuspendResumeFlag,
|
||||
kSDMMCHOST_SupportV330 = kSDIF_SupportV330Flag,
|
||||
kSDMMCHOST_SupportV300 = SDMMCHOST_NOT_SUPPORT,
|
||||
kSDMMCHOST_SupportV180 = SDMMCHOST_NOT_SUPPORT,
|
||||
kSDMMCHOST_SupportV120 = SDMMCHOST_NOT_SUPPORT,
|
||||
kSDMMCHOST_Support4BitBusWidth = kSDIF_Support4BitFlag,
|
||||
kSDMMCHOST_Support8BitBusWidth =
|
||||
SDMMCHOST_NOT_SUPPORT, /* mask the 8 bit here,user can change depend on your board */
|
||||
kSDMMCHOST_SupportDDR50 = SDMMCHOST_NOT_SUPPORT,
|
||||
kSDMMCHOST_SupportSDR104 = SDMMCHOST_NOT_SUPPORT,
|
||||
kSDMMCHOST_SupportSDR50 = SDMMCHOST_NOT_SUPPORT,
|
||||
kSDMMCHOST_SupportHS200 = SDMMCHOST_NOT_SUPPORT,
|
||||
kSDMMCHOST_SupportHS400 = SDMMCHOST_NOT_SUPPORT,
|
||||
|
||||
};
|
||||
|
||||
/*! @brief DMA table length united as word
|
||||
* One dma table item occupy four words which can transfer maximum 2*8188 bytes in dual DMA mode
|
||||
* and 8188 bytes in chain mode
|
||||
* The more data to be transferred in one time, the bigger value of SDHC_ADMA_TABLE_WORDS need to be set.
|
||||
* user need check the DMA descriptor table lenght if bigger enough.
|
||||
*/
|
||||
#define SDIF_DMA_TABLE_WORDS (0x40U)
|
||||
/* address align */
|
||||
#define SDMMCHOST_DMA_BUFFER_ADDR_ALIGN (4U)
|
||||
|
||||
/*********************************************************USDHC**********************************************************/
|
||||
#elif (defined(FSL_FEATURE_SOC_USDHC_COUNT) && (FSL_FEATURE_SOC_USDHC_COUNT > 0U))
|
||||
|
||||
/*define host baseaddr ,clk freq, IRQ number*/
|
||||
#define MMC_HOST_BASEADDR BOARD_MMC_HOST_BASEADDR
|
||||
#define MMC_HOST_CLK_FREQ BOARD_MMC_HOST_CLK_FREQ
|
||||
#define MMC_HOST_IRQ BOARD_MMC_HOST_IRQ
|
||||
#define SD_HOST_BASEADDR BOARD_SD_HOST_BASEADDR
|
||||
#define SD_HOST_CLK_FREQ BOARD_SD_HOST_CLK_FREQ
|
||||
#define SD_HOST_IRQ BOARD_SD_HOST_IRQ
|
||||
|
||||
#define SDMMCHOST_TYPE USDHC_Type
|
||||
#define SDMMCHOST_CONFIG usdhc_host_t
|
||||
#define SDMMCHOST_TRANSFER usdhc_transfer_t
|
||||
#define SDMMCHOST_COMMAND usdhc_command_t
|
||||
#define SDMMCHOST_DATA usdhc_data_t
|
||||
#define SDMMCHOST_BOOT_CONFIG usdhc_boot_config_t
|
||||
#define CARD_DATA0_STATUS_MASK (kUSDHC_Data0LineLevelFlag)
|
||||
#define CARD_DATA1_STATUS_MASK (kUSDHC_Data1LineLevelFlag)
|
||||
#define CARD_DATA2_STATUS_MASK (kUSDHC_Data2LineLevelFlag)
|
||||
#define CARD_DATA3_STATUS_MASK (kUSDHC_Data3LineLevelFlag)
|
||||
#define CARD_DATA0_NOT_BUSY (kUSDHC_Data0LineLevelFlag)
|
||||
|
||||
#define SDMMCHOST_BUS_WIDTH_TYPE usdhc_data_bus_width_t
|
||||
#define SDMMCHOST_CAPABILITY usdhc_capability_t
|
||||
|
||||
#define kSDMMCHOST_DATABUSWIDTH1BIT kUSDHC_DataBusWidth1Bit /*!< 1-bit mode */
|
||||
#define kSDMMCHOST_DATABUSWIDTH4BIT kUSDHC_DataBusWidth4Bit /*!< 4-bit mode */
|
||||
#define kSDMMCHOST_DATABUSWIDTH8BIT kUSDHC_DataBusWidth8Bit /*!< 8-bit mode */
|
||||
|
||||
#define SDMMCHOST_STANDARD_TUNING_START (10U) /*!< standard tuning start point */
|
||||
#define SDMMCHOST_TUINIG_STEP (2U) /*!< standard tuning step */
|
||||
#define SDMMCHOST_RETUNING_TIMER_COUNT (0U) /*!< Re-tuning timer */
|
||||
#define SDMMCHOST_TUNING_DELAY_MAX (0x7FU)
|
||||
#define SDMMCHOST_RETUNING_REQUEST kStatus_USDHC_ReTuningRequest
|
||||
#define SDMMCHOST_TUNING_ERROR kStatus_USDHC_TuningError
|
||||
#define SDMMCHOST_TRANSFER_DATA_ERROR kStatus_USDHC_TransferDataFailed
|
||||
#define SDMMCHOST_TRANSFER_CMD_ERROR kStatus_USDHC_SendCommandFailed
|
||||
/* define for card bus speed/strength cnofig */
|
||||
#define CARD_BUS_FREQ_50MHZ (0U)
|
||||
#define CARD_BUS_FREQ_100MHZ0 (1U)
|
||||
#define CARD_BUS_FREQ_100MHZ1 (2U)
|
||||
#define CARD_BUS_FREQ_200MHZ (3U)
|
||||
|
||||
#define CARD_BUS_STRENGTH_0 (0U)
|
||||
#define CARD_BUS_STRENGTH_1 (1U)
|
||||
#define CARD_BUS_STRENGTH_2 (2U)
|
||||
#define CARD_BUS_STRENGTH_3 (3U)
|
||||
#define CARD_BUS_STRENGTH_4 (4U)
|
||||
#define CARD_BUS_STRENGTH_5 (5U)
|
||||
#define CARD_BUS_STRENGTH_6 (6U)
|
||||
#define CARD_BUS_STRENGTH_7 (7U)
|
||||
|
||||
#define SDMMCHOST_STROBE_DLL_DELAY_TARGET (7U)
|
||||
#define SDMMCHOST_STROBE_DLL_DELAY_UPDATE_INTERVAL (4U)
|
||||
|
||||
/* function pointer define */
|
||||
#define SDMMCHOST_TRANSFER_FUNCTION usdhc_transfer_function_t
|
||||
#define GET_SDMMCHOST_CAPABILITY(base, capability) (USDHC_GetCapability(base, capability))
|
||||
#define GET_SDMMCHOST_STATUS(base) (USDHC_GetPresentStatusFlags(base))
|
||||
#define SDMMCHOST_SET_CARD_CLOCK(base, sourceClock_HZ, busClock_HZ) \
|
||||
(USDHC_SetSdClock(base, sourceClock_HZ, busClock_HZ))
|
||||
#define SDMMCHOST_ENABLE_CARD_CLOCK(base, enable)
|
||||
#define SDMMCHOST_FORCE_SDCLOCK_ON(base, enable) (USDHC_ForceClockOn(base, enable))
|
||||
#define SDMMCHOST_SET_CARD_BUS_WIDTH(base, busWidth) (USDHC_SetDataBusWidth(base, busWidth))
|
||||
#define SDMMCHOST_SEND_CARD_ACTIVE(base, timeout) (USDHC_SetCardActive(base, timeout))
|
||||
#define SDMMCHOST_SWITCH_VOLTAGE180V(base, enable18v) (UDSHC_SelectVoltage(base, enable18v))
|
||||
#define SDMMCHOST_SWITCH_VOLTAGE120V(base, enable12v)
|
||||
#define SDMMCHOST_CONFIG_SD_IO(speed, strength) BOARD_SD_Pin_Config(speed, strength)
|
||||
#define SDMMCHOST_CONFIG_MMC_IO(speed, strength) BOARD_MMC_Pin_Config(speed, strength)
|
||||
#define SDMMCHOST_SWITCH_VCC_TO_180V()
|
||||
#define SDMMCHOST_SWITCH_VCC_TO_330V()
|
||||
|
||||
#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE)
|
||||
#define SDMMCHOST_EXECUTE_STANDARD_TUNING_STATUS(base) (0U)
|
||||
#define SDMMCHOST_EXECUTE_STANDARD_TUNING_RESULT(base) (1U)
|
||||
#define SDMMCHOST_AUTO_STANDARD_RETUNING_TIMER(base)
|
||||
#define SDMMCHOST_EXECUTE_STANDARD_TUNING_ENABLE(base, flag)
|
||||
#define SDMMCHOST_CHECK_TUNING_ERROR(base) (0U)
|
||||
#define SDMMCHOST_ADJUST_TUNING_DELAY(base, delay)
|
||||
#else
|
||||
#define SDMMCHOST_EXECUTE_STANDARD_TUNING_ENABLE(base, flag) \
|
||||
(USDHC_EnableStandardTuning(base, SDMMCHOST_STANDARD_TUNING_START, SDMMCHOST_TUINIG_STEP, flag))
|
||||
#define SDMMCHOST_EXECUTE_STANDARD_TUNING_STATUS(base) (USDHC_GetExecuteStdTuningStatus(base))
|
||||
#define SDMMCHOST_EXECUTE_STANDARD_TUNING_RESULT(base) (USDHC_CheckStdTuningResult(base))
|
||||
#define SDMMCHOST_AUTO_STANDARD_RETUNING_TIMER(base) (USDHC_SetRetuningTimer(base, SDMMCHOST_RETUNING_TIMER_COUNT))
|
||||
#define SDMMCHOST_EXECUTE_MANUAL_TUNING_ENABLE(base, flag) (USDHC_EnableManualTuning(base, flag))
|
||||
#define SDMMCHOST_ADJUST_TUNING_DELAY(base, delay) (USDHC_AdjustDelayForManualTuning(base, delay))
|
||||
#define SDMMCHOST_AUTO_TUNING_ENABLE(base, flag) (USDHC_EnableAutoTuning(base, flag))
|
||||
#define SDMMCHOST_CHECK_TUNING_ERROR(base) (USDHC_CheckTuningError(base))
|
||||
#endif
|
||||
|
||||
#define SDMMCHOST_AUTO_TUNING_CONFIG(base) (USDHC_EnableAutoTuningForCmdAndData(base))
|
||||
#define SDMMCHOST_RESET_TUNING(base, timeout) \
|
||||
{ \
|
||||
(USDHC_Reset(base, kUSDHC_ResetTuning | kUSDHC_ResetData | kUSDHC_ResetCommand, timeout)); \
|
||||
}
|
||||
|
||||
#define SDMMCHOST_ENABLE_DDR_MODE(base, flag, nibblePos) (USDHC_EnableDDRMode(base, flag, nibblePos))
|
||||
|
||||
#if FSL_FEATURE_USDHC_HAS_HS400_MODE
|
||||
#define SDMMCHOST_ENABLE_HS400_MODE(base, flag) (USDHC_EnableHS400Mode(base, flag))
|
||||
#define SDMMCHOST_RESET_STROBE_DLL(base) (USDHC_ResetStrobeDLL(base))
|
||||
#define SDMMCHOST_ENABLE_STROBE_DLL(base, flag) (USDHC_EnableStrobeDLL(base, flag))
|
||||
#define SDMMCHOST_CONFIG_STROBE_DLL(base, delay, updateInterval) (USDHC_ConfigStrobeDLL(base, delay, updateInterval))
|
||||
#define SDMMCHOST_GET_STROBE_DLL_STATUS (base)(USDHC_GetStrobeDLLStatus(base))
|
||||
#else
|
||||
#define SDMMCHOST_ENABLE_HS400_MODE(base, flag)
|
||||
#define SDMMCHOST_RESET_STROBE_DLL(base)
|
||||
#define SDMMCHOST_ENABLE_STROBE_DLL(base, flag)
|
||||
#define SDMMCHOST_CONFIG_STROBE_DLL(base, delay, updateInterval)
|
||||
#define SDMMCHOST_GET_STROBE_DLL_STATUS(base)
|
||||
#endif
|
||||
|
||||
#define SDMMCHOST_ENABLE_MMC_BOOT(base, flag) (USDHC_EnableMmcBoot(base, flag))
|
||||
#define SDMMCHOST_SETMMCBOOTCONFIG(base, config) (USDHC_SetMmcBootConfig(base, config))
|
||||
/* sd card power */
|
||||
#define SDMMCHOST_INIT_SD_POWER() BOARD_USDHC_SDCARD_POWER_CONTROL_INIT()
|
||||
#define SDMMCHOST_ENABLE_SD_POWER(enable) BOARD_USDHC_SDCARD_POWER_CONTROL(enable)
|
||||
/* mmc card power */
|
||||
#define SDMMCHOST_INIT_MMC_POWER() BOARD_USDHC_MMCCARD_POWER_CONTROL_INIT()
|
||||
#define SDMMCHOST_ENABLE_MMC_POWER(enable) BOARD_USDHC_MMCCARD_POWER_CONTROL(enable)
|
||||
/* sd card detect through gpio */
|
||||
#define SDMMCHOST_CARD_DETECT_GPIO_STATUS() BOARD_USDHC_CD_STATUS()
|
||||
#define SDMMCHOST_CARD_DETECT_GPIO_INIT() BOARD_USDHC_CD_GPIO_INIT()
|
||||
#define SDMMCHOST_CARD_DETECT_GPIO_INTERRUPT_STATUS() BOARD_USDHC_CD_INTERRUPT_STATUS()
|
||||
#define SDMMCHOST_CARD_DETECT_GPIO_INTERRUPT_STATUS_CLEAR(flag) BOARD_USDHC_CD_CLEAR_INTERRUPT(flag)
|
||||
#define SDMMCHOST_CARD_DETECT_GPIO_INTERRUPT_HANDLER BOARD_USDHC_CD_PORT_IRQ_HANDLER
|
||||
#define SDMMCHOST_CARD_DETECT_GPIO_IRQ BOARD_USDHC_CD_PORT_IRQ
|
||||
/* sd card detect through host CD */
|
||||
#define SDMMCHOST_CARD_DETECT_INSERT_ENABLE(base) (USDHC_EnableInterruptStatus(base, kUSDHC_CardInsertionFlag))
|
||||
#define SDMMCHOST_CARD_DETECT_REMOVE_ENABLE(base) (USDHC_EnableInterruptStatus(base, kUSDHC_CardRemovalFlag))
|
||||
#define SDMMCHOST_CARD_DETECT_INSERT_STATUS(base) (USDHC_DetectCardInsert(base))
|
||||
#define SDMMCHOST_CARD_DETECT_REMOVE_STATUS(base) (USDHC_GetInterruptStatusFlags(base, kUSDHC_CardRemovalFlag))
|
||||
#define SDMMCHOST_CARD_DETECT_INSERT_INTERRUPT_ENABLE(base) \
|
||||
(USDHC_EnableInterruptSignal(base, kUSDHC_CardInsertionFlag))
|
||||
#define SDMMCHOST_CARD_DETECT_REMOVE_INTERRUPT_ENABLE(base) (USDHC_EnableInterruptSignal(base, kUSDHC_CardRemovalFlag))
|
||||
#define SDMMCHOST_CARD_DETECT_DATA3_ENABLE(base, flag) (USDHC_CardDetectByData3(base, flag))
|
||||
|
||||
/* define card detect pin voltage level when card inserted */
|
||||
#if defined BOARD_USDHC_CARD_INSERT_CD_LEVEL
|
||||
#define SDMMCHOST_CARD_INSERT_CD_LEVEL BOARD_USDHC_CARD_INSERT_CD_LEVEL
|
||||
#else
|
||||
#define SDMMCHOST_CARD_INSERT_CD_LEVEL (0U)
|
||||
#endif
|
||||
#define SDMMCHOST_ENABLE_TUNING_FLAG(data) (data.dataType = kUSDHC_TransferDataTuning)
|
||||
#define SDMMCHOST_ENABLE_BOOT_FLAG(data) (data.dataType = kUSDHC_TransferDataBoot)
|
||||
#define SDMMCHOST_ENABLE_BOOT_CONTINOUS_FLAG(data) (data.dataType = kUSDHC_TransferDataBootcontinous)
|
||||
#define SDMMCHOST_GET_HOST_CONFIG_BLOCK_SIZE(config) (config->blockSize)
|
||||
#define SDMMCHOST_GET_HOST_CONFIG_BLOCK_COUNT(config) (config->blockCount)
|
||||
#define SDMMCHOST_GET_HOST_CONFIG_BOOT_MODE(config) (config->bootMode)
|
||||
#define SDMMCHOST_EMPTY_CMD_FLAG(command) (command.type = kCARD_CommandTypeEmpty)
|
||||
#define SDMMCHOST_ENABLE_SDIO_INT(base) \
|
||||
USDHC_EnableInterruptStatus(base, kUSDHC_CardInterruptFlag); \
|
||||
USDHC_EnableInterruptSignal(base, kUSDHC_CardInterruptFlag)
|
||||
#define SDMMCHOST_DISABLE_SDIO_INT(base) \
|
||||
USDHC_DisableInterruptStatus(base, kUSDHC_CardInterruptFlag); \
|
||||
USDHC_DisableInterruptSignal(base, kUSDHC_CardInterruptFlag)
|
||||
/*! @brief USDHC host capability*/
|
||||
enum _host_capability
|
||||
{
|
||||
kSDMMCHOST_SupportAdma = kUSDHC_SupportAdmaFlag,
|
||||
kSDMMCHOST_SupportHighSpeed = kUSDHC_SupportHighSpeedFlag,
|
||||
kSDMMCHOST_SupportDma = kUSDHC_SupportDmaFlag,
|
||||
kSDMMCHOST_SupportSuspendResume = kUSDHC_SupportSuspendResumeFlag,
|
||||
kSDMMCHOST_SupportV330 = kUSDHC_SupportV330Flag, /* this define should depend on your board config */
|
||||
kSDMMCHOST_SupportV300 = kUSDHC_SupportV300Flag, /* this define should depend on your board config */
|
||||
#if defined(BOARD_SD_SUPPORT_180V) && !BOARD_SD_SUPPORT_180V
|
||||
kSDMMCHOST_SupportV180 = SDMMCHOST_NOT_SUPPORT, /* this define should depend on you board config */
|
||||
#else
|
||||
kSDMMCHOST_SupportV180 = kUSDHC_SupportV180Flag, /* this define should depend on you board config */
|
||||
#endif
|
||||
kSDMMCHOST_SupportV120 = SDMMCHOST_NOT_SUPPORT,
|
||||
kSDMMCHOST_Support4BitBusWidth = kUSDHC_Support4BitFlag,
|
||||
#if defined(BOARD_MMC_SUPPORT_8BIT_BUS)
|
||||
#if BOARD_MMC_SUPPORT_8BIT_BUS
|
||||
kSDMMCHOST_Support8BitBusWidth = kUSDHC_Support8BitFlag,
|
||||
#else
|
||||
kSDMMCHOST_Support8BitBusWidth = SDMMCHOST_NOT_SUPPORT,
|
||||
#endif
|
||||
#else
|
||||
kSDMMCHOST_Support8BitBusWidth = kUSDHC_Support8BitFlag,
|
||||
#endif
|
||||
kSDMMCHOST_SupportDDR50 = kUSDHC_SupportDDR50Flag,
|
||||
kSDMMCHOST_SupportSDR104 = kUSDHC_SupportSDR104Flag,
|
||||
kSDMMCHOST_SupportSDR50 = kUSDHC_SupportSDR50Flag,
|
||||
kSDMMCHOST_SupportHS200 = kUSDHC_SupportSDR104Flag,
|
||||
#if FSL_FEATURE_USDHC_HAS_HS400_MODE
|
||||
kSDMMCHOST_SupportHS400 = SDMMCHOST_SUPPORT
|
||||
#else
|
||||
kSDMMCHOST_SupportHS400 = SDMMCHOST_NOT_SUPPORT,
|
||||
#endif
|
||||
};
|
||||
|
||||
/* Endian mode. */
|
||||
#define USDHC_ENDIAN_MODE kUSDHC_EndianModeLittle
|
||||
|
||||
/* DMA mode */
|
||||
#define USDHC_DMA_MODE kUSDHC_DmaModeAdma2
|
||||
/* address align */
|
||||
#define SDMMCHOST_DMA_BUFFER_ADDR_ALIGN (USDHC_ADMA2_ADDRESS_ALIGN)
|
||||
|
||||
/* Read/write watermark level. The bigger value indicates DMA has higher read/write performance. */
|
||||
#define USDHC_READ_WATERMARK_LEVEL (0x80U)
|
||||
#define USDHC_WRITE_WATERMARK_LEVEL (0x80U)
|
||||
|
||||
/* ADMA table length united as word.
|
||||
*
|
||||
* One ADMA2 table item occupy two words which can transfer maximum 0xFFFFU bytes one time.
|
||||
* The more data to be transferred in one time, the bigger value of SDHC_ADMA_TABLE_WORDS need to be set.
|
||||
*/
|
||||
#define USDHC_ADMA_TABLE_WORDS (8U) /* define the ADMA descriptor table length */
|
||||
#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */
|
||||
#define USDHC_READ_BURST_LEN (8U) /*!< number of words USDHC read in a single burst */
|
||||
#define USDHC_WRITE_BURST_LEN (8U) /*!< number of words USDHC write in a single burst */
|
||||
#define USDHC_DATA_TIMEOUT (0xFU) /*!< data timeout counter value */
|
||||
|
||||
#endif /* (defined(FSL_FEATURE_SOC_SDHC_COUNT) && (FSL_FEATURE_SOC_SDHC_COUNT > 0U)) */
|
||||
|
||||
/*! @brief card detect callback definition */
|
||||
typedef void (*sdmmchost_cd_callback_t)(bool isInserted, void *userData);
|
||||
|
||||
/*! @brief host Endian mode
|
||||
* corresponding to driver define
|
||||
*/
|
||||
enum _sdmmchost_endian_mode
|
||||
{
|
||||
kSDMMCHOST_EndianModeBig = 0U, /*!< Big endian mode */
|
||||
kSDMMCHOST_EndianModeHalfWordBig = 1U, /*!< Half word big endian mode */
|
||||
kSDMMCHOST_EndianModeLittle = 2U, /*!< Little endian mode */
|
||||
};
|
||||
|
||||
/*! @brief sd card detect type */
|
||||
typedef enum _sdmmchost_detect_card_type
|
||||
{
|
||||
kSDMMCHOST_DetectCardByGpioCD, /*!< sd card detect by CD pin through GPIO */
|
||||
kSDMMCHOST_DetectCardByHostCD, /*!< sd card detect by CD pin through host */
|
||||
kSDMMCHOST_DetectCardByHostDATA3, /*!< sd card detect by DAT3 pin through host */
|
||||
} sdmmchost_detect_card_type_t;
|
||||
|
||||
/*! @brief sd card detect */
|
||||
typedef struct _sdmmchost_detect_card
|
||||
{
|
||||
sdmmchost_detect_card_type_t cdType; /*!< card detect type */
|
||||
uint32_t cdTimeOut_ms; /*!< card detect timeout which allow 0 - 0xFFFFFFF, value 0 will return immediately, value
|
||||
0xFFFFFFFF will block until card is insert */
|
||||
|
||||
sdmmchost_cd_callback_t cardInserted; /*!< card inserted callback which is meaningful for interrupt case */
|
||||
sdmmchost_cd_callback_t cardRemoved; /*!< card removed callback which is meaningful for interrupt case */
|
||||
|
||||
void *userData; /*!< user data */
|
||||
} sdmmchost_detect_card_t;
|
||||
|
||||
/*! @brief card power control function pointer */
|
||||
typedef void (*sdmmchost_pwr_t)(void);
|
||||
|
||||
/*! @brief card power control */
|
||||
typedef struct _sdmmchost_pwr_card
|
||||
{
|
||||
sdmmchost_pwr_t powerOn; /*!< power on function pointer */
|
||||
uint32_t powerOnDelay_ms; /*!< power on delay */
|
||||
|
||||
sdmmchost_pwr_t powerOff; /*!< power off function pointer */
|
||||
uint32_t powerOffDelay_ms; /*!< power off delay */
|
||||
} sdmmchost_pwr_card_t;
|
||||
|
||||
/*! @brief card interrupt function pointer */
|
||||
typedef void (*sdmmchost_card_int_callback_t)(void *userData);
|
||||
/*! @brief card interrupt application callback */
|
||||
typedef struct _sdmmchost_card_int
|
||||
{
|
||||
void *userData; /*!< user data */
|
||||
sdmmchost_card_int_callback_t cardInterrupt; /*!< card int call back */
|
||||
} sdmmchost_card_int_t;
|
||||
|
||||
/*! @brief card switch voltage function pointer */
|
||||
typedef void (*sdmmchost_card_switch_voltage_t)(void);
|
||||
/*! @brief card switch voltage function collection */
|
||||
typedef struct _sdmmchost_card_switch_voltage_func
|
||||
{
|
||||
sdmmchost_card_switch_voltage_t cardSignalLine1V8; /*!< switch to 1.8v function pointer */
|
||||
sdmmchost_card_switch_voltage_t cardSignalLine3V3; /*!<switch to 3.3V function pointer */
|
||||
} sdmmchost_card_switch_voltage_func_t;
|
||||
|
||||
/*! @brief card user parameter, user can define the parameter according the board, card capability */
|
||||
typedef struct _sdmmhostcard_usr_param
|
||||
{
|
||||
const sdmmchost_detect_card_t *cd; /*!< card detect type */
|
||||
const sdmmchost_pwr_card_t *pwr; /*!< power control configuration */
|
||||
const sdmmchost_card_int_t *cardInt; /*!< call back function for card interrupt */
|
||||
const sdmmchost_card_switch_voltage_func_t *cardVoltage; /*!< card voltage switch function */
|
||||
} sdmmhostcard_usr_param_t;
|
||||
|
||||
/*! @ brief specifiy card user parameter name*/
|
||||
typedef sdmmhostcard_usr_param_t sdcard_usr_param_t;
|
||||
typedef sdmmhostcard_usr_param_t sdiocard_usr_param_t;
|
||||
typedef sdmmhostcard_usr_param_t mmccard_usr_param_t;
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name adaptor function
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief host not support function, this function is used for host not support feature
|
||||
* @param void parameter ,used to avoid build warning
|
||||
* @retval kStatus_Fail ,host do not suppport
|
||||
*/
|
||||
static inline status_t SDMMCHOST_NotSupport(void *parameter)
|
||||
{
|
||||
parameter = parameter;
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Detect card insert, only need for SD cases.
|
||||
* @param base the pointer to host base address
|
||||
* @param cd card detect configuration
|
||||
* @param waitCardStatus status which user want to wait
|
||||
* @retval kStatus_Success detect card insert
|
||||
* @retval kStatus_Fail card insert event fail
|
||||
*/
|
||||
status_t SDMMCHOST_WaitCardDetectStatus(SDMMCHOST_TYPE *hostBase,
|
||||
const sdmmchost_detect_card_t *cd,
|
||||
bool waitCardStatus);
|
||||
|
||||
/*!
|
||||
* @brief check card is present or not.
|
||||
* @retval true card is present
|
||||
* @retval false card is not present
|
||||
*/
|
||||
bool SDMMCHOST_IsCardPresent(void);
|
||||
|
||||
/*!
|
||||
* @brief Init host controller.
|
||||
* @param host the pointer to host structure in card structure.
|
||||
* @param userData specific user data
|
||||
* @retval kStatus_Success host init success
|
||||
* @retval kStatus_Fail event fail
|
||||
*/
|
||||
status_t SDMMCHOST_Init(SDMMCHOST_CONFIG *host, void *userData);
|
||||
|
||||
/*!
|
||||
* @brief reset host controller.
|
||||
* @param host base address.
|
||||
*/
|
||||
void SDMMCHOST_Reset(SDMMCHOST_TYPE *base);
|
||||
|
||||
/*!
|
||||
* @brief host controller error recovery.
|
||||
* @param host base address.
|
||||
*/
|
||||
void SDMMCHOST_ErrorRecovery(SDMMCHOST_TYPE *base);
|
||||
|
||||
/*!
|
||||
* @brief Deinit host controller.
|
||||
* @param host the pointer to host structure in card structure.
|
||||
*/
|
||||
void SDMMCHOST_Deinit(void *host);
|
||||
|
||||
/*!
|
||||
* @brief host power off card function.
|
||||
* @param base host base address.
|
||||
* @param pwr depend on user define power configuration.
|
||||
*/
|
||||
void SDMMCHOST_PowerOffCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr);
|
||||
|
||||
/*!
|
||||
* @brief host power on card function.
|
||||
* @param base host base address.
|
||||
* @param pwr depend on user define power configuration.
|
||||
*/
|
||||
void SDMMCHOST_PowerOnCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr);
|
||||
|
||||
/*!
|
||||
* @brief SDMMC host delay function.
|
||||
* @param milliseconds delay counter.
|
||||
*/
|
||||
void SDMMCHOST_Delay(uint32_t milliseconds);
|
||||
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
/* @} */
|
||||
#endif /* _FSL_SDMMC_HOST_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,3 @@
|
|||
SRC_DIR += usdhc
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _FSL_SDMMC_EVENT_H_
|
||||
#define _FSL_SDMMC_EVENT_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/*! @brief Event type */
|
||||
typedef enum _sdmmc_event
|
||||
{
|
||||
kSDMMCEVENT_TransferComplete = 0U, /*!< Transfer complete event */
|
||||
kSDMMCEVENT_CardDetect = 1U, /*!< Card detect event */
|
||||
} sdmmc_event_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Event Function
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initialize timer to implement wait event timeout.
|
||||
*/
|
||||
void SDMMCEVENT_InitTimer(void);
|
||||
|
||||
/* Callback function for SDHC */
|
||||
|
||||
/*!
|
||||
* @brief Create event.
|
||||
* @param eventType The event type
|
||||
* @retval true Create event successfully.
|
||||
* @retval false Create event failed.
|
||||
*/
|
||||
bool SDMMCEVENT_Create(sdmmc_event_t eventType);
|
||||
|
||||
/*!
|
||||
* @brief Wait event.
|
||||
*
|
||||
* @param eventType The event type
|
||||
* @param timeoutMilliseconds Timeout time in milliseconds.
|
||||
* @retval true Wait event successfully.
|
||||
* @retval false Wait event failed.
|
||||
*/
|
||||
bool SDMMCEVENT_Wait(sdmmc_event_t eventType, uint32_t timeoutMilliseconds);
|
||||
|
||||
/*!
|
||||
* @brief Notify event.
|
||||
* @param eventType The event type
|
||||
* @retval true Notify event successfully.
|
||||
* @retval false Notify event failed.
|
||||
*/
|
||||
bool SDMMCEVENT_Notify(sdmmc_event_t eventType);
|
||||
|
||||
/*!
|
||||
* @brief Delete event.
|
||||
* @param eventType The event type
|
||||
*/
|
||||
void SDMMCEVENT_Delete(sdmmc_event_t eventType);
|
||||
|
||||
/*!
|
||||
* @brief sdmmc delay.
|
||||
* @param milliseconds time to delay
|
||||
*/
|
||||
void SDMMCEVENT_Delay(uint32_t milliseconds);
|
||||
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _FSL_SDMMC_EVENT_H_*/
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
SRC_DIR += polling
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
SRC_FILES := fsl_sdmmc_host.c fsl_sdmmc_event.c
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#include "fsl_sdmmc_event.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief Get event instance.
|
||||
* @param eventType The event type
|
||||
* @return The event instance's pointer.
|
||||
*/
|
||||
static volatile uint32_t *SDMMCEVENT_GetInstance(sdmmc_event_t eventType);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/*! @brief Card detect event. */
|
||||
static volatile uint32_t g_eventCardDetect;
|
||||
|
||||
/*! @brief transfer complete event. */
|
||||
static volatile uint32_t g_eventTransferComplete;
|
||||
|
||||
/*! @brief Time variable unites as milliseconds. */
|
||||
volatile uint32_t g_eventTimeMilliseconds;
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
static void SysTickHandler(void)
|
||||
{
|
||||
#ifdef __CA7_REV
|
||||
SystemClearSystickFlag();
|
||||
#endif
|
||||
g_eventTimeMilliseconds++;
|
||||
}
|
||||
|
||||
void SDMMCEVENT_InitTimer(void)
|
||||
{
|
||||
#ifdef __CA7_REV
|
||||
/* special for i.mx6ul */
|
||||
SystemSetupSystick(1000U, (void *)SysTickHandler, 32U);
|
||||
SystemClearSystickFlag();
|
||||
#else
|
||||
/* Set systick reload value to generate 1ms interrupt */
|
||||
SysTick_Config(CLOCK_GetFreq(kCLOCK_CoreSysClk) / 1000U);
|
||||
#endif
|
||||
}
|
||||
|
||||
static volatile uint32_t *SDMMCEVENT_GetInstance(sdmmc_event_t eventType)
|
||||
{
|
||||
volatile uint32_t *event;
|
||||
|
||||
switch (eventType)
|
||||
{
|
||||
case kSDMMCEVENT_TransferComplete:
|
||||
event = &g_eventTransferComplete;
|
||||
break;
|
||||
case kSDMMCEVENT_CardDetect:
|
||||
event = &g_eventCardDetect;
|
||||
break;
|
||||
default:
|
||||
event = NULL;
|
||||
break;
|
||||
}
|
||||
|
||||
return event;
|
||||
}
|
||||
|
||||
bool SDMMCEVENT_Create(sdmmc_event_t eventType)
|
||||
{
|
||||
volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType);
|
||||
|
||||
if (event)
|
||||
{
|
||||
*event = 0;
|
||||
return true;
|
||||
}
|
||||
else
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
bool SDMMCEVENT_Wait(sdmmc_event_t eventType, uint32_t timeoutMilliseconds)
|
||||
{
|
||||
uint32_t startTime;
|
||||
uint32_t elapsedTime;
|
||||
|
||||
volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType);
|
||||
|
||||
if (timeoutMilliseconds && event)
|
||||
{
|
||||
startTime = g_eventTimeMilliseconds;
|
||||
do
|
||||
{
|
||||
elapsedTime = (g_eventTimeMilliseconds - startTime);
|
||||
} while ((*event == 0U) && (elapsedTime < timeoutMilliseconds));
|
||||
*event = 0U;
|
||||
|
||||
return ((elapsedTime < timeoutMilliseconds) ? true : false);
|
||||
}
|
||||
else
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
bool SDMMCEVENT_Notify(sdmmc_event_t eventType)
|
||||
{
|
||||
volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType);
|
||||
|
||||
if (event)
|
||||
{
|
||||
*event = 1U;
|
||||
return true;
|
||||
}
|
||||
else
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
void SDMMCEVENT_Delete(sdmmc_event_t eventType)
|
||||
{
|
||||
volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType);
|
||||
|
||||
if (event)
|
||||
{
|
||||
*event = 0U;
|
||||
}
|
||||
}
|
||||
|
||||
void SDMMCEVENT_Delay(uint32_t milliseconds)
|
||||
{
|
||||
uint32_t startTime = g_eventTimeMilliseconds;
|
||||
uint32_t periodTime = 0;
|
||||
while (periodTime < milliseconds)
|
||||
{
|
||||
periodTime = g_eventTimeMilliseconds - startTime;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,437 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "fsl_sdmmc_event.h"
|
||||
#include "fsl_sdmmc_host.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief SDMMCHOST notify card insertion status.
|
||||
* @param inserted true is inserted, false is not
|
||||
* @param cd card detect descriptor
|
||||
*/
|
||||
static void SDMMCHOST_NofiyCardInsertStatus(bool inserted, const sdmmchost_detect_card_t *cd);
|
||||
|
||||
/*!
|
||||
* @brief SDMMCHOST detect card insert status by host controller.
|
||||
* @param base host base address.
|
||||
* @param userData user can register a application card insert callback through userData.
|
||||
*/
|
||||
static void SDMMCHOST_DetectCardInsertByHost(SDMMCHOST_TYPE *base, void *userData);
|
||||
|
||||
/*!
|
||||
* @brief SDMMCHOST detect card remove status by host controller.
|
||||
* @param base host base address.
|
||||
* @param userData user can register a application card insert callback through userData.
|
||||
*/
|
||||
static void SDMMCHOST_DetectCardRemoveByHost(SDMMCHOST_TYPE *base, void *userData);
|
||||
|
||||
/*!
|
||||
* @brief SDMMCHOST transfer function.
|
||||
* @param base host base address.
|
||||
* @param content transfer configurations.
|
||||
*/
|
||||
static status_t SDMMCHOST_TransferFunction(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER *content);
|
||||
|
||||
/*!
|
||||
* @brief SDMMCHOST transfer complete callback.
|
||||
* @param base host base address.
|
||||
* @param handle host handle.
|
||||
* @param status interrupt status.
|
||||
* @param userData user data.
|
||||
*/
|
||||
static void SDMMCHOST_TransferCompleteCallback(SDMMCHOST_TYPE *base,
|
||||
usdhc_handle_t *handle,
|
||||
status_t status,
|
||||
void *userData);
|
||||
|
||||
/*!
|
||||
* @brief SDMMCHOST re-tuning callback
|
||||
* @param base host base address.
|
||||
* @param userData user can register a application card insert callback through userData.
|
||||
*/
|
||||
static void SDMMCHOST_ReTuningCallback(SDMMCHOST_TYPE *base, void *userData);
|
||||
|
||||
/*!
|
||||
* @brief card detect deinit function.
|
||||
*/
|
||||
static void SDMMCHOST_CardDetectDeinit(void);
|
||||
|
||||
/*!
|
||||
* @brief card detect deinit function.
|
||||
* @param host base address.
|
||||
* @param host detect card configuration.
|
||||
*/
|
||||
static status_t SDMMCHOST_CardDetectInit(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/* DMA descriptor should allocate at non-cached memory */
|
||||
AT_NONCACHEABLE_SECTION_ALIGN(uint32_t g_usdhcAdma2Table[USDHC_ADMA_TABLE_WORDS], USDHC_ADMA2_ADDR_ALIGN);
|
||||
|
||||
usdhc_handle_t g_usdhcHandle;
|
||||
volatile status_t g_usdhcTransferStatus = kStatus_Success;
|
||||
static volatile bool s_sdInsertedFlag = false;
|
||||
volatile status_t g_reTuningFlag = false;
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
static void SDMMCHOST_NofiyCardInsertStatus(bool inserted, const sdmmchost_detect_card_t *cd)
|
||||
{
|
||||
if (inserted == false)
|
||||
{
|
||||
s_sdInsertedFlag = false;
|
||||
if (cd && (cd->cardRemoved))
|
||||
{
|
||||
cd->cardRemoved(false, cd->userData);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
s_sdInsertedFlag = true;
|
||||
if (cd && (cd->cardInserted))
|
||||
{
|
||||
cd->cardInserted(true, cd->userData);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void SDMMCHOST_DetectCardInsertByHost(SDMMCHOST_TYPE *base, void *userData)
|
||||
{
|
||||
s_sdInsertedFlag = true;
|
||||
SDMMCEVENT_Notify(kSDMMCEVENT_CardDetect);
|
||||
/* application callback */
|
||||
if (userData && (((sdmmhostcard_usr_param_t *)userData)->cd) &&
|
||||
((sdmmhostcard_usr_param_t *)userData)->cd->cardInserted)
|
||||
{
|
||||
((sdmmhostcard_usr_param_t *)userData)
|
||||
->cd->cardInserted(true, ((sdmmhostcard_usr_param_t *)userData)->cd->userData);
|
||||
}
|
||||
}
|
||||
|
||||
static void SDMMCHOST_DetectCardRemoveByHost(SDMMCHOST_TYPE *base, void *userData)
|
||||
{
|
||||
s_sdInsertedFlag = false;
|
||||
/* application callback */
|
||||
if (userData && (((sdmmhostcard_usr_param_t *)userData)->cd) &&
|
||||
((sdmmhostcard_usr_param_t *)userData)->cd->cardRemoved)
|
||||
{
|
||||
((sdmmhostcard_usr_param_t *)userData)
|
||||
->cd->cardRemoved(false, ((sdmmhostcard_usr_param_t *)userData)->cd->userData);
|
||||
}
|
||||
}
|
||||
|
||||
static void SDMMCHOST_CardInterrupt(SDMMCHOST_TYPE *base, void *userData)
|
||||
{
|
||||
/* application callback */
|
||||
if (userData && ((sdmmhostcard_usr_param_t *)userData)->cardInt)
|
||||
{
|
||||
((sdmmhostcard_usr_param_t *)userData)
|
||||
->cardInt->cardInterrupt(((sdmmhostcard_usr_param_t *)userData)->cardInt->userData);
|
||||
}
|
||||
}
|
||||
|
||||
void SDMMCHOST_CARD_DETECT_GPIO_INTERRUPT_HANDLER(void)
|
||||
{
|
||||
if (SDMMCHOST_CARD_DETECT_GPIO_INTERRUPT_STATUS() & (1U << BOARD_USDHC_CD_GPIO_PIN))
|
||||
{
|
||||
SDMMCHOST_NofiyCardInsertStatus((SDMMCHOST_CARD_DETECT_GPIO_STATUS() == SDMMCHOST_CARD_INSERT_CD_LEVEL),
|
||||
((sdmmhostcard_usr_param_t *)g_usdhcHandle.userData)->cd);
|
||||
}
|
||||
/* Clear interrupt flag.*/
|
||||
SDMMCHOST_CARD_DETECT_GPIO_INTERRUPT_STATUS_CLEAR(~0U);
|
||||
SDMMCEVENT_Notify(kSDMMCEVENT_CardDetect);
|
||||
}
|
||||
|
||||
static void SDMMCHOST_TransferCompleteCallback(SDMMCHOST_TYPE *base,
|
||||
usdhc_handle_t *handle,
|
||||
status_t status,
|
||||
void *userData)
|
||||
{
|
||||
/* if reading data from sdcard, ignore the command error, usdhc will continue transfer data */
|
||||
if (!((handle->data) && (handle->data->rxData) && (status == kStatus_USDHC_SendCommandFailed)))
|
||||
{
|
||||
SDMMCEVENT_Notify(kSDMMCEVENT_TransferComplete);
|
||||
}
|
||||
/* wait the target status and then notify the transfer complete */
|
||||
g_usdhcTransferStatus = status;
|
||||
}
|
||||
|
||||
static void SDMMCHOST_ReTuningCallback(SDMMCHOST_TYPE *base, void *userData)
|
||||
{
|
||||
g_reTuningFlag = true;
|
||||
SDMMCEVENT_Notify(kSDMMCEVENT_TransferComplete);
|
||||
}
|
||||
|
||||
static status_t SDMMCHOST_TransferFunction(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER *content)
|
||||
{
|
||||
status_t error = kStatus_Success;
|
||||
|
||||
usdhc_adma_config_t dmaConfig;
|
||||
|
||||
if (content->data != NULL)
|
||||
{
|
||||
memset(&dmaConfig, 0, sizeof(usdhc_adma_config_t));
|
||||
/* config adma */
|
||||
dmaConfig.dmaMode = USDHC_DMA_MODE;
|
||||
dmaConfig.burstLen = kUSDHC_EnBurstLenForINCR;
|
||||
dmaConfig.admaTable = g_usdhcAdma2Table;
|
||||
dmaConfig.admaTableWords = USDHC_ADMA_TABLE_WORDS;
|
||||
}
|
||||
|
||||
/* make sure complete event is cleared. */
|
||||
SDMMCEVENT_Delete(kSDMMCEVENT_TransferComplete);
|
||||
|
||||
do
|
||||
{
|
||||
error = USDHC_TransferNonBlocking(base, &g_usdhcHandle, &dmaConfig, content);
|
||||
} while (error == kStatus_USDHC_BusyTransferring);
|
||||
|
||||
if ((error != kStatus_Success) ||
|
||||
(false == SDMMCEVENT_Wait(kSDMMCEVENT_TransferComplete, SDMMCHOST_TRANSFER_COMPLETE_TIMEOUT)) ||
|
||||
(g_reTuningFlag) || (g_usdhcTransferStatus != kStatus_Success))
|
||||
{
|
||||
if (g_reTuningFlag || (error == kStatus_USDHC_ReTuningRequest))
|
||||
{
|
||||
if (g_reTuningFlag)
|
||||
{
|
||||
g_reTuningFlag = false;
|
||||
error = kStatus_USDHC_TuningError;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
error = g_usdhcTransferStatus;
|
||||
/* host error recovery */
|
||||
SDMMCHOST_ErrorRecovery(base);
|
||||
}
|
||||
}
|
||||
|
||||
return error;
|
||||
}
|
||||
|
||||
void SDMMCHOST_ErrorRecovery(SDMMCHOST_TYPE *base)
|
||||
{
|
||||
uint32_t status = 0U;
|
||||
/* get host present status */
|
||||
status = USDHC_GetPresentStatusFlags(base);
|
||||
/* check command inhibit status flag */
|
||||
if ((status & kUSDHC_CommandInhibitFlag) != 0U)
|
||||
{
|
||||
/* reset command line */
|
||||
USDHC_Reset(base, kUSDHC_ResetCommand, 100U);
|
||||
}
|
||||
/* check data inhibit status flag */
|
||||
if ((status & kUSDHC_DataInhibitFlag) != 0U)
|
||||
{
|
||||
/* reset data line */
|
||||
USDHC_Reset(base, kUSDHC_ResetData, 100U);
|
||||
}
|
||||
}
|
||||
|
||||
static status_t SDMMCHOST_CardDetectInit(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd)
|
||||
{
|
||||
sdmmchost_detect_card_type_t cdType = kSDMMCHOST_DetectCardByGpioCD;
|
||||
bool cardInserted = false;
|
||||
|
||||
if (cd != NULL)
|
||||
{
|
||||
cdType = cd->cdType;
|
||||
}
|
||||
|
||||
if (!SDMMCEVENT_Create(kSDMMCEVENT_CardDetect))
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
|
||||
if (cdType == kSDMMCHOST_DetectCardByGpioCD)
|
||||
{
|
||||
SDMMCHOST_CARD_DETECT_GPIO_INIT();
|
||||
|
||||
/* Open card detection pin NVIC. */
|
||||
SDMMCHOST_ENABLE_IRQ(SDMMCHOST_CARD_DETECT_GPIO_IRQ);
|
||||
/* detect card insert status */
|
||||
if (SDMMCHOST_CARD_DETECT_GPIO_STATUS() == SDMMCHOST_CARD_INSERT_CD_LEVEL)
|
||||
{
|
||||
cardInserted = true;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* enable card detect through DATA3 */
|
||||
if (cdType == kSDMMCHOST_DetectCardByHostDATA3)
|
||||
{
|
||||
SDMMCHOST_CARD_DETECT_DATA3_ENABLE(base, true);
|
||||
}
|
||||
/* enable card detect interrupt */
|
||||
SDMMCHOST_CARD_DETECT_INSERT_ENABLE(base);
|
||||
/* check if card is inserted */
|
||||
if (SDMMCHOST_CARD_DETECT_INSERT_STATUS(base))
|
||||
{
|
||||
cardInserted = true;
|
||||
}
|
||||
else
|
||||
{
|
||||
SDMMCHOST_CARD_DETECT_INSERT_INTERRUPT_ENABLE(base);
|
||||
SDMMCHOST_CARD_DETECT_REMOVE_INTERRUPT_ENABLE(base);
|
||||
}
|
||||
}
|
||||
|
||||
/* notify application about the card insertion status */
|
||||
SDMMCHOST_NofiyCardInsertStatus(cardInserted, cd);
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
static void SDMMCHOST_CardDetectDeinit(void)
|
||||
{
|
||||
SDMMCEVENT_Delete(kSDMMCEVENT_CardDetect);
|
||||
s_sdInsertedFlag = false;
|
||||
}
|
||||
|
||||
void SDMMCHOST_Delay(uint32_t milliseconds)
|
||||
{
|
||||
SDMMCEVENT_Delay(milliseconds);
|
||||
}
|
||||
|
||||
status_t SDMMCHOST_WaitCardDetectStatus(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd, bool waitCardStatus)
|
||||
{
|
||||
uint32_t timeout = SDMMCHOST_CARD_DETECT_TIMEOUT;
|
||||
|
||||
if (cd != NULL)
|
||||
{
|
||||
timeout = cd->cdTimeOut_ms;
|
||||
}
|
||||
|
||||
if (waitCardStatus != s_sdInsertedFlag)
|
||||
{
|
||||
/* Wait card inserted. */
|
||||
do
|
||||
{
|
||||
if (!SDMMCEVENT_Wait(kSDMMCEVENT_CardDetect, timeout))
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
} while (waitCardStatus != s_sdInsertedFlag);
|
||||
}
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
bool SDMMCHOST_IsCardPresent(void)
|
||||
{
|
||||
return s_sdInsertedFlag;
|
||||
}
|
||||
|
||||
void SDMMCHOST_PowerOffCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr)
|
||||
{
|
||||
if (pwr != NULL)
|
||||
{
|
||||
pwr->powerOff();
|
||||
SDMMCHOST_Delay(pwr->powerOffDelay_ms);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* only SD card need card detect*/
|
||||
SDMMCHOST_ENABLE_SD_POWER(false);
|
||||
/* Delay several milliseconds to make card stable. */
|
||||
SDMMCHOST_Delay(500U);
|
||||
}
|
||||
}
|
||||
|
||||
void SDMMCHOST_PowerOnCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr)
|
||||
{
|
||||
/* use user define the power on function */
|
||||
if (pwr != NULL)
|
||||
{
|
||||
pwr->powerOn();
|
||||
SDMMCHOST_Delay(pwr->powerOnDelay_ms);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* card power on */
|
||||
SDMMCHOST_ENABLE_SD_POWER(true);
|
||||
/* Delay several milliseconds to make card stable. */
|
||||
SDMMCHOST_Delay(500U);
|
||||
}
|
||||
}
|
||||
|
||||
status_t SDMMCHOST_Init(SDMMCHOST_CONFIG *host, void *userData)
|
||||
{
|
||||
usdhc_host_t *usdhcHost = (usdhc_host_t *)host;
|
||||
usdhc_transfer_callback_t callback = {
|
||||
.TransferComplete = SDMMCHOST_TransferCompleteCallback,
|
||||
.ReTuning = SDMMCHOST_ReTuningCallback,
|
||||
.CardInserted = SDMMCHOST_DetectCardInsertByHost,
|
||||
.CardRemoved = SDMMCHOST_DetectCardRemoveByHost,
|
||||
.SdioInterrupt = SDMMCHOST_CardInterrupt,
|
||||
.BlockGap = NULL,
|
||||
};
|
||||
/* init card power control */
|
||||
SDMMCHOST_INIT_SD_POWER();
|
||||
SDMMCHOST_INIT_MMC_POWER();
|
||||
|
||||
/* Initializes USDHC. */
|
||||
usdhcHost->config.dataTimeout = USDHC_DATA_TIMEOUT;
|
||||
usdhcHost->config.endianMode = USDHC_ENDIAN_MODE;
|
||||
usdhcHost->config.readWatermarkLevel = USDHC_READ_WATERMARK_LEVEL;
|
||||
usdhcHost->config.writeWatermarkLevel = USDHC_WRITE_WATERMARK_LEVEL;
|
||||
usdhcHost->config.readBurstLen = USDHC_READ_BURST_LEN;
|
||||
usdhcHost->config.writeBurstLen = USDHC_WRITE_BURST_LEN;
|
||||
|
||||
USDHC_Init(usdhcHost->base, &(usdhcHost->config));
|
||||
|
||||
/* disable the card insert/remove interrupt, due to use GPIO interrupt detect card */
|
||||
USDHC_DisableInterruptSignal(usdhcHost->base, kUSDHC_CardRemovalFlag | kUSDHC_CardInsertionFlag);
|
||||
/* create interrupt handler */
|
||||
USDHC_TransferCreateHandle(usdhcHost->base, &g_usdhcHandle, &callback, userData);
|
||||
/* Create transfer complete event. */
|
||||
SDMMCEVENT_InitTimer();
|
||||
|
||||
if (false == SDMMCEVENT_Create(kSDMMCEVENT_TransferComplete))
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
|
||||
/* Define transfer function. */
|
||||
usdhcHost->transfer = SDMMCHOST_TransferFunction;
|
||||
/* card detect init */
|
||||
SDMMCHOST_CardDetectInit(usdhcHost->base, (userData == NULL) ? NULL : (((sdmmhostcard_usr_param_t *)userData)->cd));
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
void SDMMCHOST_Reset(SDMMCHOST_TYPE *base)
|
||||
{
|
||||
/* voltage switch to normal but not 1.8V */
|
||||
SDMMCHOST_SWITCH_VOLTAGE180V(base, false);
|
||||
/* Disable DDR mode */
|
||||
SDMMCHOST_ENABLE_DDR_MODE(base, false, 0U);
|
||||
/* disable tuning */
|
||||
SDMMCHOST_EXECUTE_STANDARD_TUNING_ENABLE(base, false);
|
||||
/* Disable HS400 mode */
|
||||
SDMMCHOST_ENABLE_HS400_MODE(base, false);
|
||||
/* Disable DLL */
|
||||
SDMMCHOST_ENABLE_STROBE_DLL(base, false);
|
||||
}
|
||||
|
||||
void SDMMCHOST_Deinit(void *host)
|
||||
{
|
||||
usdhc_host_t *usdhcHost = (usdhc_host_t *)host;
|
||||
SDMMCHOST_Reset(usdhcHost->base);
|
||||
USDHC_Deinit(usdhcHost->base);
|
||||
SDMMCHOST_CardDetectDeinit();
|
||||
}
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
SRC_FILES := fsl_sdmmc_host.c fsl_sdmmc_event.c
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,154 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "fsl_sdmmc_event.h"
|
||||
#include "xizi.h"
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief Get event instance.
|
||||
* @param eventType The event type
|
||||
* @return The event instance's pointer.
|
||||
*/
|
||||
static volatile uint32_t *SDMMCEVENT_GetInstance(sdmmc_event_t eventType);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/*! @brief Card detect event. */
|
||||
static volatile uint32_t g_eventCardDetect;
|
||||
|
||||
/*! @brief transfer complete event. */
|
||||
static volatile uint32_t g_eventTransferComplete;
|
||||
|
||||
/*! @brief Time variable unites as milliseconds. */
|
||||
volatile uint32_t g_eventTimeMilliseconds;
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
// void SysTick_Handler(void)
|
||||
// {
|
||||
// #ifdef __CA7_REV
|
||||
// SystemClearSystickFlag();
|
||||
// #endif
|
||||
// g_eventTimeMilliseconds++;
|
||||
// }
|
||||
|
||||
void SDMMCEVENT_InitTimer(void)
|
||||
{
|
||||
#ifdef __CA7_REV
|
||||
/* special for i.mx6ul */
|
||||
SystemSetupSystick(1000U, (void *)SysTick_Handler, 32U);
|
||||
SystemClearSystickFlag();
|
||||
#else
|
||||
/* Set systick reload value to generate 1ms interrupt */
|
||||
SysTick_Config(CLOCK_GetFreq(kCLOCK_CoreSysClk) / 1000U);
|
||||
#endif
|
||||
}
|
||||
|
||||
static volatile uint32_t *SDMMCEVENT_GetInstance(sdmmc_event_t eventType)
|
||||
{
|
||||
volatile uint32_t *event;
|
||||
|
||||
switch (eventType)
|
||||
{
|
||||
case kSDMMCEVENT_TransferComplete:
|
||||
event = &g_eventTransferComplete;
|
||||
break;
|
||||
case kSDMMCEVENT_CardDetect:
|
||||
event = &g_eventCardDetect;
|
||||
break;
|
||||
default:
|
||||
event = NULL;
|
||||
break;
|
||||
}
|
||||
|
||||
return event;
|
||||
}
|
||||
|
||||
bool SDMMCEVENT_Create(sdmmc_event_t eventType)
|
||||
{
|
||||
volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType);
|
||||
|
||||
if (event)
|
||||
{
|
||||
*event = 0;
|
||||
return true;
|
||||
}
|
||||
else
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
bool SDMMCEVENT_Wait(sdmmc_event_t eventType, uint32_t timeoutMilliseconds)
|
||||
{
|
||||
uint32_t startTime;
|
||||
uint32_t elapsedTime;
|
||||
|
||||
volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType);
|
||||
|
||||
if (timeoutMilliseconds && event)
|
||||
{
|
||||
startTime = CurrentTicksGain();
|
||||
do
|
||||
{
|
||||
elapsedTime = (CurrentTicksGain() - startTime);
|
||||
} while ((*event == 0U) && (elapsedTime < timeoutMilliseconds));
|
||||
*event = 0U;
|
||||
|
||||
return ((elapsedTime < timeoutMilliseconds) ? true : false);
|
||||
}
|
||||
else
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
bool SDMMCEVENT_Notify(sdmmc_event_t eventType)
|
||||
{
|
||||
volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType);
|
||||
|
||||
if (event)
|
||||
{
|
||||
*event = 1U;
|
||||
return true;
|
||||
}
|
||||
else
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
void SDMMCEVENT_Delete(sdmmc_event_t eventType)
|
||||
{
|
||||
volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType);
|
||||
|
||||
if (event)
|
||||
{
|
||||
*event = 0U;
|
||||
}
|
||||
}
|
||||
|
||||
void SDMMCEVENT_Delay(uint32_t milliseconds)
|
||||
{
|
||||
uint32_t startTime = CurrentTicksGain();
|
||||
uint32_t periodTime = 0;
|
||||
while (periodTime < milliseconds)
|
||||
{
|
||||
KPrintf("period time %u millisecond %u event %u start %u\n",
|
||||
periodTime, milliseconds, CurrentTicksGain(), startTime);
|
||||
periodTime = CurrentTicksGain() - startTime;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,290 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "fsl_sdmmc_host.h"
|
||||
#include "fsl_sdmmc_event.h"
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief SDMMCHOST notify card insertion status.
|
||||
* @param inserted true is inserted, false is not
|
||||
* @param cd card detect descriptor
|
||||
*/
|
||||
static void SDMMCHOST_NofiyCardInsertStatus(bool inserted, const sdmmchost_detect_card_t *cd);
|
||||
|
||||
/*!
|
||||
* @brief SDMMCHOST transfer function.
|
||||
* @param base host base address.
|
||||
* @param content transfer configurations.
|
||||
*/
|
||||
static status_t SDMMCHOST_TransferFunction(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER *content);
|
||||
|
||||
/*!
|
||||
* @brief card detect deinit function.
|
||||
*/
|
||||
static void SDMMCHOST_CardDetectDeinit(void);
|
||||
|
||||
/*!
|
||||
* @brief card detect deinit function.
|
||||
* @param host base address.
|
||||
* @param host detect card configuration.
|
||||
*/
|
||||
static status_t SDMMCHOST_CardDetectInit(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd);
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/* DMA descriptor should allocate at non-cached memory */
|
||||
AT_NONCACHEABLE_SECTION_ALIGN(uint32_t g_usdhcAdma2Table[USDHC_ADMA_TABLE_WORDS], USDHC_ADMA2_ADDR_ALIGN);
|
||||
static volatile bool s_sdInsertedFlag = false;
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
static void SDMMCHOST_NofiyCardInsertStatus(bool inserted, const sdmmchost_detect_card_t *cd)
|
||||
{
|
||||
if (inserted == false)
|
||||
{
|
||||
s_sdInsertedFlag = false;
|
||||
if (cd && (cd->cardRemoved))
|
||||
{
|
||||
cd->cardRemoved(false, cd->userData);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
s_sdInsertedFlag = true;
|
||||
if (cd && (cd->cardInserted))
|
||||
{
|
||||
cd->cardInserted(true, cd->userData);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static status_t SDMMCHOST_TransferFunction(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER *content)
|
||||
{
|
||||
usdhc_adma_config_t dmaConfig;
|
||||
status_t error = kStatus_Success;
|
||||
|
||||
if (content->data != NULL)
|
||||
{
|
||||
memset(&dmaConfig, 0, sizeof(usdhc_adma_config_t));
|
||||
/* config adma */
|
||||
dmaConfig.dmaMode = USDHC_DMA_MODE;
|
||||
dmaConfig.burstLen = kUSDHC_EnBurstLenForINCR;
|
||||
dmaConfig.admaTable = g_usdhcAdma2Table;
|
||||
dmaConfig.admaTableWords = USDHC_ADMA_TABLE_WORDS;
|
||||
}
|
||||
|
||||
error = USDHC_TransferBlocking(base, &dmaConfig, content);
|
||||
|
||||
if (error != kStatus_Success)
|
||||
{
|
||||
/* host error recovery */
|
||||
SDMMCHOST_ErrorRecovery(base);
|
||||
}
|
||||
|
||||
return error;
|
||||
}
|
||||
|
||||
void SDMMCHOST_ErrorRecovery(SDMMCHOST_TYPE *base)
|
||||
{
|
||||
uint32_t status = 0U;
|
||||
/* get host present status */
|
||||
status = USDHC_GetPresentStatusFlags(base);
|
||||
/* check command inhibit status flag */
|
||||
if ((status & kUSDHC_CommandInhibitFlag) != 0U)
|
||||
{
|
||||
/* reset command line */
|
||||
USDHC_Reset(base, kUSDHC_ResetCommand, 100U);
|
||||
}
|
||||
/* check data inhibit status flag */
|
||||
if ((status & kUSDHC_DataInhibitFlag) != 0U)
|
||||
{
|
||||
/* reset data line */
|
||||
USDHC_Reset(base, kUSDHC_ResetData, 100U);
|
||||
}
|
||||
}
|
||||
|
||||
static status_t SDMMCHOST_CardDetectInit(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd)
|
||||
{
|
||||
sdmmchost_detect_card_type_t cdType = kSDMMCHOST_DetectCardByGpioCD;
|
||||
bool cardInserted = false;
|
||||
|
||||
if (cd != NULL)
|
||||
{
|
||||
cdType = cd->cdType;
|
||||
}
|
||||
|
||||
if (cdType == kSDMMCHOST_DetectCardByGpioCD)
|
||||
{
|
||||
SDMMCHOST_CARD_DETECT_GPIO_INIT();
|
||||
/* detect card insert status */
|
||||
if (SDMMCHOST_CARD_DETECT_GPIO_STATUS() == SDMMCHOST_CARD_INSERT_CD_LEVEL)
|
||||
{
|
||||
cardInserted = true;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* enable card detect through DATA3 */
|
||||
if (cdType == kSDMMCHOST_DetectCardByHostDATA3)
|
||||
{
|
||||
SDMMCHOST_CARD_DETECT_DATA3_ENABLE(base, true);
|
||||
}
|
||||
/* enable card detect status */
|
||||
SDMMCHOST_CARD_DETECT_INSERT_ENABLE(base);
|
||||
SDMMCHOST_CARD_DETECT_REMOVE_ENABLE(base);
|
||||
/* check if card is inserted */
|
||||
if (SDMMCHOST_CARD_DETECT_INSERT_STATUS(base))
|
||||
{
|
||||
cardInserted = true;
|
||||
}
|
||||
}
|
||||
|
||||
/* notify application about the card insertion status */
|
||||
SDMMCHOST_NofiyCardInsertStatus(cardInserted, cd);
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
static void SDMMCHOST_CardDetectDeinit(void)
|
||||
{
|
||||
SDMMCEVENT_Delete(kSDMMCEVENT_CardDetect);
|
||||
s_sdInsertedFlag = false;
|
||||
}
|
||||
|
||||
void SDMMCHOST_Delay(uint32_t milliseconds)
|
||||
{
|
||||
SDMMCEVENT_Delay(milliseconds);
|
||||
}
|
||||
|
||||
status_t SDMMCHOST_WaitCardDetectStatus(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd, bool waitCardStatus)
|
||||
{
|
||||
sdmmchost_detect_card_type_t cdType = kSDMMCHOST_DetectCardByGpioCD;
|
||||
|
||||
if (cd != NULL)
|
||||
{
|
||||
cdType = cd->cdType;
|
||||
}
|
||||
|
||||
if (waitCardStatus != s_sdInsertedFlag)
|
||||
{
|
||||
/* Wait card inserted. */
|
||||
do
|
||||
{
|
||||
if (cdType != kSDMMCHOST_DetectCardByGpioCD)
|
||||
{
|
||||
if (SDMMCHOST_CARD_DETECT_INSERT_STATUS(base))
|
||||
{
|
||||
s_sdInsertedFlag = true;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (SDMMCHOST_CARD_DETECT_INSERT_STATUS(base))
|
||||
{
|
||||
s_sdInsertedFlag = true;
|
||||
}
|
||||
}
|
||||
} while (waitCardStatus != s_sdInsertedFlag);
|
||||
}
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
bool SDMMCHOST_IsCardPresent(void)
|
||||
{
|
||||
return s_sdInsertedFlag;
|
||||
}
|
||||
|
||||
void SDMMCHOST_PowerOffCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr)
|
||||
{
|
||||
if (pwr != NULL)
|
||||
{
|
||||
pwr->powerOff();
|
||||
SDMMCHOST_Delay(pwr->powerOffDelay_ms);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* only SD card need card detect*/
|
||||
SDMMCHOST_ENABLE_SD_POWER(false);
|
||||
/* Delay several milliseconds to make card stable. */
|
||||
SDMMCHOST_Delay(500U);
|
||||
}
|
||||
}
|
||||
|
||||
void SDMMCHOST_PowerOnCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr)
|
||||
{
|
||||
/* use user define the power on function */
|
||||
if (pwr != NULL)
|
||||
{
|
||||
pwr->powerOn();
|
||||
SDMMCHOST_Delay(pwr->powerOnDelay_ms);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* card power on */
|
||||
SDMMCHOST_ENABLE_SD_POWER(true);
|
||||
/* Delay several milliseconds to make card stable. */
|
||||
SDMMCHOST_Delay(500U);
|
||||
}
|
||||
}
|
||||
|
||||
status_t SDMMCHOST_Init(SDMMCHOST_CONFIG *host, void *userData)
|
||||
{
|
||||
usdhc_host_t *usdhcHost = (usdhc_host_t *)host;
|
||||
|
||||
/* init card power control */
|
||||
SDMMCHOST_INIT_SD_POWER();
|
||||
SDMMCHOST_INIT_MMC_POWER();
|
||||
|
||||
/* Initializes SDHC. */
|
||||
usdhcHost->config.dataTimeout = USDHC_DATA_TIMEOUT;
|
||||
usdhcHost->config.endianMode = USDHC_ENDIAN_MODE;
|
||||
usdhcHost->config.readWatermarkLevel = USDHC_READ_WATERMARK_LEVEL;
|
||||
usdhcHost->config.writeWatermarkLevel = USDHC_WRITE_WATERMARK_LEVEL;
|
||||
usdhcHost->config.readBurstLen = USDHC_READ_BURST_LEN;
|
||||
usdhcHost->config.writeBurstLen = USDHC_WRITE_BURST_LEN;
|
||||
|
||||
USDHC_Init(usdhcHost->base, &(usdhcHost->config));
|
||||
|
||||
/* Define transfer function. */
|
||||
usdhcHost->transfer = SDMMCHOST_TransferFunction;
|
||||
/* event init timer */
|
||||
SDMMCEVENT_InitTimer();
|
||||
/* card detect init */
|
||||
SDMMCHOST_CardDetectInit(usdhcHost->base, (userData == NULL) ? NULL : (((sdmmhostcard_usr_param_t *)userData)->cd));
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
void SDMMCHOST_Reset(SDMMCHOST_TYPE *base)
|
||||
{
|
||||
/* voltage switch to normal but not 1.8V */
|
||||
SDMMCHOST_SWITCH_VOLTAGE180V(base, false);
|
||||
/* Disable DDR mode */
|
||||
SDMMCHOST_ENABLE_DDR_MODE(base, false, 0U);
|
||||
/* disable tuning */
|
||||
SDMMCHOST_EXECUTE_STANDARD_TUNING_ENABLE(base, false);
|
||||
/* Disable HS400 mode */
|
||||
SDMMCHOST_ENABLE_HS400_MODE(base, false);
|
||||
/* Disable DLL */
|
||||
SDMMCHOST_ENABLE_STROBE_DLL(base, false);
|
||||
}
|
||||
|
||||
void SDMMCHOST_Deinit(void *host)
|
||||
{
|
||||
usdhc_host_t *usdhcHost = (usdhc_host_t *)host;
|
||||
SDMMCHOST_Reset(usdhcHost->base);
|
||||
USDHC_Deinit(usdhcHost->base);
|
||||
SDMMCHOST_CardDetectDeinit();
|
||||
}
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
SRC_FILES := fsl_sd.c fsl_sdmmc_common.c
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,393 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "fsl_sdmmc_common.h"
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
SDK_ALIGN(uint32_t g_sdmmc[SDK_SIZEALIGN(SDMMC_GLOBAL_BUFFER_SIZE, SDMMC_DATA_BUFFER_ALIGN_CACHE)],
|
||||
MAX(SDMMC_DATA_BUFFER_ALIGN_CACHE, SDMMCHOST_DMA_BUFFER_ADDR_ALIGN));
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
status_t SDMMC_SelectCard(SDMMCHOST_TYPE *base,
|
||||
SDMMCHOST_TRANSFER_FUNCTION transfer,
|
||||
uint32_t relativeAddress,
|
||||
bool isSelected)
|
||||
{
|
||||
assert(transfer);
|
||||
|
||||
SDMMCHOST_TRANSFER content = {0};
|
||||
SDMMCHOST_COMMAND command = {0};
|
||||
|
||||
command.index = kSDMMC_SelectCard;
|
||||
if (isSelected)
|
||||
{
|
||||
command.argument = relativeAddress << 16U;
|
||||
command.responseType = kCARD_ResponseTypeR1;
|
||||
}
|
||||
else
|
||||
{
|
||||
command.argument = 0U;
|
||||
command.responseType = kCARD_ResponseTypeNone;
|
||||
}
|
||||
|
||||
content.command = &command;
|
||||
content.data = NULL;
|
||||
if ((kStatus_Success != transfer(base, &content)) || (command.response[0U] & SDMMC_R1_ALL_ERROR_FLAG))
|
||||
{
|
||||
return kStatus_SDMMC_TransferFailed;
|
||||
}
|
||||
|
||||
/* Wait until card to transfer state */
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
status_t SDMMC_SendApplicationCommand(SDMMCHOST_TYPE *base,
|
||||
SDMMCHOST_TRANSFER_FUNCTION transfer,
|
||||
uint32_t relativeAddress)
|
||||
{
|
||||
assert(transfer);
|
||||
|
||||
SDMMCHOST_TRANSFER content = {0};
|
||||
SDMMCHOST_COMMAND command = {0};
|
||||
|
||||
command.index = kSDMMC_ApplicationCommand;
|
||||
command.argument = (relativeAddress << 16U);
|
||||
command.responseType = kCARD_ResponseTypeR1;
|
||||
|
||||
content.command = &command;
|
||||
content.data = 0U;
|
||||
if ((kStatus_Success != transfer(base, &content)) || (command.response[0U] & SDMMC_R1_ALL_ERROR_FLAG))
|
||||
{
|
||||
return kStatus_SDMMC_TransferFailed;
|
||||
}
|
||||
|
||||
if (!(command.response[0U] & SDMMC_MASK(kSDMMC_R1ApplicationCommandFlag)))
|
||||
{
|
||||
return kStatus_SDMMC_CardNotSupport;
|
||||
}
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
status_t SDMMC_SetBlockCount(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer, uint32_t blockCount)
|
||||
{
|
||||
assert(transfer);
|
||||
|
||||
SDMMCHOST_TRANSFER content = {0};
|
||||
SDMMCHOST_COMMAND command = {0};
|
||||
|
||||
command.index = kSDMMC_SetBlockCount;
|
||||
command.argument = blockCount;
|
||||
command.responseType = kCARD_ResponseTypeR1;
|
||||
|
||||
content.command = &command;
|
||||
content.data = 0U;
|
||||
if ((kStatus_Success != transfer(base, &content)) || (command.response[0U] & SDMMC_R1_ALL_ERROR_FLAG))
|
||||
{
|
||||
return kStatus_SDMMC_TransferFailed;
|
||||
}
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
status_t SDMMC_GoIdle(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer)
|
||||
{
|
||||
assert(transfer);
|
||||
|
||||
SDMMCHOST_TRANSFER content = {0};
|
||||
SDMMCHOST_COMMAND command = {0};
|
||||
|
||||
command.index = kSDMMC_GoIdleState;
|
||||
|
||||
content.command = &command;
|
||||
content.data = 0U;
|
||||
if (kStatus_Success != transfer(base, &content))
|
||||
{
|
||||
return kStatus_SDMMC_TransferFailed;
|
||||
}
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
status_t SDMMC_SetBlockSize(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer, uint32_t blockSize)
|
||||
{
|
||||
assert(transfer);
|
||||
|
||||
SDMMCHOST_TRANSFER content = {0};
|
||||
SDMMCHOST_COMMAND command = {0};
|
||||
|
||||
command.index = kSDMMC_SetBlockLength;
|
||||
command.argument = blockSize;
|
||||
command.responseType = kCARD_ResponseTypeR1;
|
||||
|
||||
content.command = &command;
|
||||
content.data = 0U;
|
||||
if ((kStatus_Success != transfer(base, &content)) || (command.response[0U] & SDMMC_R1_ALL_ERROR_FLAG))
|
||||
{
|
||||
return kStatus_SDMMC_TransferFailed;
|
||||
}
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
status_t SDMMC_SetCardInactive(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer)
|
||||
{
|
||||
assert(transfer);
|
||||
|
||||
SDMMCHOST_TRANSFER content = {0};
|
||||
SDMMCHOST_COMMAND command = {0};
|
||||
|
||||
command.index = kSDMMC_GoInactiveState;
|
||||
command.argument = 0U;
|
||||
command.responseType = kCARD_ResponseTypeNone;
|
||||
|
||||
content.command = &command;
|
||||
content.data = 0U;
|
||||
if ((kStatus_Success != transfer(base, &content)))
|
||||
{
|
||||
return kStatus_SDMMC_TransferFailed;
|
||||
}
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
status_t SDMMC_SwitchVoltage(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer)
|
||||
{
|
||||
assert(transfer);
|
||||
|
||||
SDMMCHOST_TRANSFER content = {0};
|
||||
SDMMCHOST_COMMAND command = {0};
|
||||
status_t error = kStatus_Success;
|
||||
|
||||
if (kSDMMCHOST_SupportV180 != SDMMCHOST_NOT_SUPPORT)
|
||||
{
|
||||
command.index = kSD_VoltageSwitch;
|
||||
command.argument = 0U;
|
||||
command.responseType = kCARD_ResponseTypeR1;
|
||||
|
||||
content.command = &command;
|
||||
content.data = NULL;
|
||||
if (kStatus_Success != transfer(base, &content))
|
||||
{
|
||||
return kStatus_SDMMC_TransferFailed;
|
||||
}
|
||||
/* disable card clock */
|
||||
SDMMCHOST_ENABLE_CARD_CLOCK(base, false);
|
||||
|
||||
/* check data line and cmd line status */
|
||||
if ((GET_SDMMCHOST_STATUS(base) &
|
||||
(CARD_DATA1_STATUS_MASK | CARD_DATA2_STATUS_MASK | CARD_DATA3_STATUS_MASK | CARD_DATA0_NOT_BUSY)) != 0U)
|
||||
{
|
||||
return kStatus_SDMMC_SwitchVoltageFail;
|
||||
}
|
||||
|
||||
/* host switch to 1.8V */
|
||||
SDMMCHOST_SWITCH_VOLTAGE180V(base, true);
|
||||
|
||||
SDMMCHOST_Delay(100U);
|
||||
|
||||
/*enable sd clock*/
|
||||
SDMMCHOST_ENABLE_CARD_CLOCK(base, true);
|
||||
/*enable force clock on*/
|
||||
SDMMCHOST_FORCE_SDCLOCK_ON(base, true);
|
||||
/* dealy 1ms,not exactly correct when use while */
|
||||
SDMMCHOST_Delay(10U);
|
||||
/*disable force clock on*/
|
||||
SDMMCHOST_FORCE_SDCLOCK_ON(base, false);
|
||||
|
||||
/* check data line and cmd line status */
|
||||
if ((GET_SDMMCHOST_STATUS(base) &
|
||||
(CARD_DATA1_STATUS_MASK | CARD_DATA2_STATUS_MASK | CARD_DATA3_STATUS_MASK | CARD_DATA0_NOT_BUSY)) == 0U)
|
||||
{
|
||||
error = kStatus_SDMMC_SwitchVoltageFail;
|
||||
/* power reset the card */
|
||||
SDMMCHOST_ENABLE_SD_POWER(false);
|
||||
SDMMCHOST_Delay(10U);
|
||||
SDMMCHOST_ENABLE_SD_POWER(true);
|
||||
SDMMCHOST_Delay(10U);
|
||||
/* re-check the data line status */
|
||||
if ((GET_SDMMCHOST_STATUS(base) &
|
||||
(CARD_DATA1_STATUS_MASK | CARD_DATA2_STATUS_MASK | CARD_DATA3_STATUS_MASK | CARD_DATA0_NOT_BUSY)))
|
||||
{
|
||||
error = kStatus_SDMMC_SwitchVoltage18VFail33VSuccess;
|
||||
SDMMC_LOG(
|
||||
"\r\nNote: Current card support 1.8V, but board don't support, so sdmmc switch back to 3.3V.");
|
||||
}
|
||||
else
|
||||
{
|
||||
SDMMC_LOG(
|
||||
"\r\nError: Current card support 1.8V, but board don't support, sdmmc tried to switch back\
|
||||
to 3.3V, but failed, please check board setting.");
|
||||
}
|
||||
}
|
||||
|
||||
return error;
|
||||
}
|
||||
else
|
||||
{
|
||||
return kStatus_SDMMC_HostNotSupport;
|
||||
}
|
||||
}
|
||||
|
||||
status_t SDMMC_SwitchToVoltage(SDMMCHOST_TYPE *base,
|
||||
SDMMCHOST_TRANSFER_FUNCTION transfer,
|
||||
sdmmchost_card_switch_voltage_t switchVoltageFunc)
|
||||
{
|
||||
assert(transfer);
|
||||
|
||||
SDMMCHOST_TRANSFER content = {0};
|
||||
SDMMCHOST_COMMAND command = {0};
|
||||
status_t error = kStatus_Success;
|
||||
|
||||
if (kSDMMCHOST_SupportV180 != SDMMCHOST_NOT_SUPPORT)
|
||||
{
|
||||
command.index = kSD_VoltageSwitch;
|
||||
command.argument = 0U;
|
||||
command.responseType = kCARD_ResponseTypeR1;
|
||||
|
||||
content.command = &command;
|
||||
content.data = NULL;
|
||||
if (kStatus_Success != transfer(base, &content))
|
||||
{
|
||||
return kStatus_SDMMC_TransferFailed;
|
||||
}
|
||||
/* disable card clock */
|
||||
SDMMCHOST_ENABLE_CARD_CLOCK(base, false);
|
||||
|
||||
/* check data line and cmd line status */
|
||||
if ((GET_SDMMCHOST_STATUS(base) &
|
||||
(CARD_DATA1_STATUS_MASK | CARD_DATA2_STATUS_MASK | CARD_DATA3_STATUS_MASK | CARD_DATA0_NOT_BUSY)) != 0U)
|
||||
{
|
||||
return kStatus_SDMMC_SwitchVoltageFail;
|
||||
}
|
||||
|
||||
if (switchVoltageFunc != NULL)
|
||||
{
|
||||
switchVoltageFunc();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* host switch to 1.8V */
|
||||
SDMMCHOST_SWITCH_VOLTAGE180V(base, true);
|
||||
}
|
||||
|
||||
SDMMCHOST_Delay(100U);
|
||||
|
||||
/*enable sd clock*/
|
||||
SDMMCHOST_ENABLE_CARD_CLOCK(base, true);
|
||||
/*enable force clock on*/
|
||||
SDMMCHOST_FORCE_SDCLOCK_ON(base, true);
|
||||
/* dealy 1ms,not exactly correct when use while */
|
||||
SDMMCHOST_Delay(10U);
|
||||
/*disable force clock on*/
|
||||
SDMMCHOST_FORCE_SDCLOCK_ON(base, false);
|
||||
|
||||
/* check data line and cmd line status */
|
||||
if ((GET_SDMMCHOST_STATUS(base) &
|
||||
(CARD_DATA1_STATUS_MASK | CARD_DATA2_STATUS_MASK | CARD_DATA3_STATUS_MASK | CARD_DATA0_NOT_BUSY)) == 0U)
|
||||
{
|
||||
error = kStatus_SDMMC_SwitchVoltageFail;
|
||||
/* power reset the card */
|
||||
SDMMCHOST_ENABLE_SD_POWER(false);
|
||||
SDMMCHOST_Delay(10U);
|
||||
SDMMCHOST_ENABLE_SD_POWER(true);
|
||||
SDMMCHOST_Delay(10U);
|
||||
/* re-check the data line status */
|
||||
if ((GET_SDMMCHOST_STATUS(base) &
|
||||
(CARD_DATA1_STATUS_MASK | CARD_DATA2_STATUS_MASK | CARD_DATA3_STATUS_MASK | CARD_DATA0_NOT_BUSY)))
|
||||
{
|
||||
error = kStatus_SDMMC_SwitchVoltage18VFail33VSuccess;
|
||||
SDMMC_LOG(
|
||||
"\r\nNote: Current card support 1.8V, but board don't support, so sdmmc switch back to 3.3V.");
|
||||
}
|
||||
else
|
||||
{
|
||||
SDMMC_LOG(
|
||||
"\r\nError: Current card support 1.8V, but board don't support, sdmmc tried to switch back\
|
||||
to 3.3V, but failed, please check board setting.");
|
||||
}
|
||||
}
|
||||
|
||||
return error;
|
||||
}
|
||||
else
|
||||
{
|
||||
return kStatus_SDMMC_HostNotSupport;
|
||||
}
|
||||
}
|
||||
|
||||
status_t SDMMC_ExecuteTuning(SDMMCHOST_TYPE *base,
|
||||
SDMMCHOST_TRANSFER_FUNCTION transfer,
|
||||
uint32_t tuningCmd,
|
||||
uint32_t blockSize)
|
||||
{
|
||||
SDMMCHOST_TRANSFER content = {0U};
|
||||
SDMMCHOST_COMMAND command = {0U};
|
||||
SDMMCHOST_DATA data = {0U};
|
||||
uint32_t buffer[32U] = {0U};
|
||||
bool tuningError = true;
|
||||
|
||||
command.index = tuningCmd;
|
||||
command.argument = 0U;
|
||||
command.responseType = kCARD_ResponseTypeR1;
|
||||
|
||||
data.blockSize = blockSize;
|
||||
data.blockCount = 1U;
|
||||
data.rxData = buffer;
|
||||
/* add this macro for adpter to different driver */
|
||||
SDMMCHOST_ENABLE_TUNING_FLAG(data);
|
||||
|
||||
content.command = &command;
|
||||
content.data = &data;
|
||||
|
||||
/* enable the standard tuning */
|
||||
SDMMCHOST_EXECUTE_STANDARD_TUNING_ENABLE(base, true);
|
||||
|
||||
while (true)
|
||||
{
|
||||
/* send tuning block */
|
||||
if ((kStatus_Success != transfer(base, &content)))
|
||||
{
|
||||
return kStatus_SDMMC_TransferFailed;
|
||||
}
|
||||
SDMMCHOST_Delay(1U);
|
||||
|
||||
/*wait excute tuning bit clear*/
|
||||
if ((SDMMCHOST_EXECUTE_STANDARD_TUNING_STATUS(base) != 0U))
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
/* if tuning error , re-tuning again */
|
||||
if ((SDMMCHOST_CHECK_TUNING_ERROR(base) != 0U) && tuningError)
|
||||
{
|
||||
tuningError = false;
|
||||
/* enable the standard tuning */
|
||||
SDMMCHOST_EXECUTE_STANDARD_TUNING_ENABLE(base, true);
|
||||
SDMMCHOST_ADJUST_TUNING_DELAY(base, SDMMCHOST_STANDARD_TUNING_START);
|
||||
}
|
||||
else
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* check tuning result*/
|
||||
if (SDMMCHOST_EXECUTE_STANDARD_TUNING_RESULT(base) == 0U)
|
||||
{
|
||||
return kStatus_SDMMC_TuningFail;
|
||||
}
|
||||
|
||||
#if !SDMMC_ENABLE_SOFTWARE_TUNING
|
||||
SDMMCHOST_AUTO_TUNING_ENABLE(base, true);
|
||||
#endif
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
config BSP_USING_LPUART1
|
||||
bool "Enable LPUART1"
|
||||
default y
|
||||
if BSP_USING_LPUART1
|
||||
config SERIAL_BUS_NAME_1
|
||||
string "serial bus 1 name"
|
||||
default "uart1"
|
||||
config SERIAL_DRV_NAME_1
|
||||
string "serial bus 1 driver name"
|
||||
default "uart1_drv"
|
||||
config SERIAL_1_DEVICE_NAME_0
|
||||
string "serial bus 1 device name"
|
||||
default "uart1_dev1"
|
||||
endif
|
||||
|
||||
config BSP_USING_LPUART2
|
||||
bool "Enable LPUART2"
|
||||
default y
|
||||
if BSP_USING_LPUART2
|
||||
config SERIAL_BUS_NAME_2
|
||||
string "serial bus 2 name"
|
||||
default "uart2"
|
||||
config SERIAL_DRV_NAME_2
|
||||
string "serial bus 2 driver name"
|
||||
default "uart2_drv"
|
||||
config SERIAL_2_DEVICE_NAME_0
|
||||
string "serial bus 2 device name"
|
||||
default "uart2_dev2"
|
||||
endif
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
SRC_FILES := connect_uart.c fsl_lpuart.c
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,409 @@
|
|||
/*
|
||||
* Copyright 2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file connect_uart.c
|
||||
* @brief support imxrt1052-board uart function and register to bus framework
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021-05-28
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: connect_uart.c
|
||||
Description: support imxrt1052-board uart configure and uart bus register function
|
||||
Others: take SDK_2.6.1_MIMXRT1052xxxxB/components/uart/lpuart_adapter.c for references
|
||||
History:
|
||||
1. Date: 2021-05-28
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. support imxrt1052-board uart configure, write and read
|
||||
2. support imxrt1052-board uart bus device and driver register
|
||||
*************************************************/
|
||||
|
||||
#include <board.h>
|
||||
#include <connect_uart.h>
|
||||
#include <fsl_lpuart.h>
|
||||
|
||||
static void UartIsr(struct SerialBus *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev);
|
||||
|
||||
#ifdef BSP_USING_LPUART1
|
||||
struct SerialBus serial_bus_1;
|
||||
struct SerialDriver serial_driver_1;
|
||||
struct SerialHardwareDevice serial_device_1;
|
||||
|
||||
void LPUART1_IRQHandler(int irqn, void *arg)
|
||||
{
|
||||
x_base lock = 0;
|
||||
// KPrintf("LPUART1_IRQHandler \n");
|
||||
lock = DISABLE_INTERRUPT();
|
||||
|
||||
UartIsr(&serial_bus_1, &serial_driver_1, &serial_device_1);
|
||||
|
||||
ENABLE_INTERRUPT(lock);
|
||||
}
|
||||
DECLARE_HW_IRQ(UART1_IRQn, LPUART1_IRQHandler, NONE);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_LPUART2
|
||||
struct SerialBus serial_bus_2;
|
||||
struct SerialDriver serial_driver_2;
|
||||
struct SerialHardwareDevice serial_device_2;
|
||||
|
||||
void LPUART2_IRQHandler(int irqn, void *arg)
|
||||
{
|
||||
x_base lock = 0;
|
||||
lock = DISABLE_INTERRUPT();
|
||||
|
||||
UartIsr(&serial_bus_2, &serial_driver_2, &serial_device_2);
|
||||
|
||||
ENABLE_INTERRUPT(lock);
|
||||
}
|
||||
DECLARE_HW_IRQ(UART2_IRQn, LPUART2_IRQHandler, NONE);
|
||||
#endif
|
||||
|
||||
static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new)
|
||||
{
|
||||
struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg;
|
||||
struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg;
|
||||
|
||||
if ((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) {
|
||||
data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate;
|
||||
}
|
||||
|
||||
if ((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) {
|
||||
data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order;
|
||||
}
|
||||
|
||||
if ((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) {
|
||||
data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size;
|
||||
}
|
||||
|
||||
if ((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) {
|
||||
data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits;
|
||||
}
|
||||
|
||||
if ((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) {
|
||||
data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode;
|
||||
}
|
||||
|
||||
if ((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) {
|
||||
data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode;
|
||||
}
|
||||
|
||||
if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
|
||||
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
|
||||
}
|
||||
}
|
||||
|
||||
static void UartIsr(struct SerialBus *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
|
||||
{
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
|
||||
LPUART_Type *uart_base = (LPUART_Type *)serial_cfg->hw_cfg.private_data;
|
||||
|
||||
/* kLPUART_RxDataRegFullFlag can only cleared or set by hardware */
|
||||
if (LPUART_GetStatusFlags(uart_base) & kLPUART_RxDataRegFullFlag) {
|
||||
SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND);
|
||||
}
|
||||
|
||||
if (LPUART_GetStatusFlags(uart_base) & kLPUART_RxOverrunFlag) {
|
||||
/* Clear overrun flag, otherwise the RX does not work. */
|
||||
LPUART_ClearStatusFlags(uart_base, kLPUART_RxOverrunFlag);
|
||||
}
|
||||
}
|
||||
|
||||
static uint32 GetUartSrcFreq(void)
|
||||
{
|
||||
uint32 freq;
|
||||
|
||||
/* To make it simple, we assume default PLL and divider settings, and the only variable
|
||||
from application is use PLL3 source or OSC source */
|
||||
if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */ {
|
||||
freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
|
||||
} else {
|
||||
freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
|
||||
}
|
||||
|
||||
return freq;
|
||||
}
|
||||
|
||||
static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info)
|
||||
{
|
||||
NULL_PARAM_CHECK(serial_drv);
|
||||
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
|
||||
LPUART_Type *uart_base = (LPUART_Type *)serial_cfg->hw_cfg.private_data;
|
||||
|
||||
if (configure_info->private_data) {
|
||||
struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data;
|
||||
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
|
||||
}
|
||||
|
||||
lpuart_config_t config;
|
||||
LPUART_GetDefaultConfig(&config);
|
||||
config.baudRate_Bps = serial_cfg->data_cfg.serial_baud_rate;
|
||||
|
||||
switch (serial_cfg->data_cfg.serial_data_bits)
|
||||
{
|
||||
case DATA_BITS_7:
|
||||
config.dataBitsCount = kLPUART_SevenDataBits;
|
||||
break;
|
||||
|
||||
default:
|
||||
config.dataBitsCount = kLPUART_EightDataBits;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (serial_cfg->data_cfg.serial_stop_bits)
|
||||
{
|
||||
case STOP_BITS_2:
|
||||
config.stopBitCount = kLPUART_TwoStopBit;
|
||||
break;
|
||||
default:
|
||||
config.stopBitCount = kLPUART_OneStopBit;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (serial_cfg->data_cfg.serial_parity_mode)
|
||||
{
|
||||
case PARITY_ODD:
|
||||
config.parityMode = kLPUART_ParityOdd;
|
||||
break;
|
||||
case PARITY_EVEN:
|
||||
config.parityMode = kLPUART_ParityEven;
|
||||
break;
|
||||
default:
|
||||
config.parityMode = kLPUART_ParityDisabled;
|
||||
break;
|
||||
}
|
||||
|
||||
config.enableTx = true;
|
||||
config.enableRx = true;
|
||||
|
||||
LPUART_Init(uart_base, &config, GetUartSrcFreq());
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static uint32 SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd)
|
||||
{
|
||||
NULL_PARAM_CHECK(serial_drv);
|
||||
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
|
||||
LPUART_Type *uart_base = (LPUART_Type *)serial_cfg->hw_cfg.private_data;
|
||||
|
||||
switch (serial_operation_cmd)
|
||||
{
|
||||
case OPER_CLR_INT:
|
||||
DisableIRQ(serial_cfg->hw_cfg.serial_irq_interrupt);
|
||||
break;
|
||||
|
||||
case OPER_SET_INT:
|
||||
LPUART_EnableInterrupts(uart_base, kLPUART_RxDataRegFullInterruptEnable);
|
||||
NVIC_SetPriority(serial_cfg->hw_cfg.serial_irq_interrupt, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 4, 0));
|
||||
EnableIRQ(serial_cfg->hw_cfg.serial_irq_interrupt);
|
||||
break;
|
||||
}
|
||||
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static int SerialPutChar(struct SerialHardwareDevice *serial_dev, char c)
|
||||
{
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
|
||||
LPUART_Type *uart_base = (LPUART_Type *)serial_cfg->hw_cfg.private_data;
|
||||
|
||||
LPUART_WriteByte(uart_base, c);
|
||||
while (!(LPUART_GetStatusFlags(uart_base) & kLPUART_TxDataRegEmptyFlag));
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int SerialGetChar(struct SerialHardwareDevice *serial_dev)
|
||||
{
|
||||
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
|
||||
LPUART_Type *uart_base = (LPUART_Type *)serial_cfg->hw_cfg.private_data;
|
||||
|
||||
int c = -1;
|
||||
if (LPUART_GetStatusFlags(uart_base) & kLPUART_RxDataRegFullFlag) {
|
||||
c = LPUART_ReadByte(uart_base);
|
||||
}
|
||||
|
||||
return c;
|
||||
}
|
||||
|
||||
static uint32 SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
|
||||
{
|
||||
NULL_PARAM_CHECK(drv);
|
||||
NULL_PARAM_CHECK(configure_info);
|
||||
|
||||
x_err_t ret = EOK;
|
||||
int serial_operation_cmd;
|
||||
struct SerialDriver *serial_drv = (struct SerialDriver *)drv;
|
||||
|
||||
switch (configure_info->configure_cmd)
|
||||
{
|
||||
case OPE_INT:
|
||||
ret = SerialInit(serial_drv, configure_info);
|
||||
break;
|
||||
case OPE_CFG:
|
||||
serial_operation_cmd = *(int *)configure_info->private_data;
|
||||
ret = SerialConfigure(serial_drv, serial_operation_cmd);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct SerialDataCfg data_cfg_init =
|
||||
{
|
||||
.serial_baud_rate = BAUD_RATE_115200,
|
||||
.serial_data_bits = DATA_BITS_8,
|
||||
.serial_stop_bits = STOP_BITS_1,
|
||||
.serial_parity_mode = PARITY_NONE,
|
||||
.serial_bit_order = BIT_ORDER_LSB,
|
||||
.serial_invert_mode = NRZ_NORMAL,
|
||||
.serial_buffer_size = SERIAL_RB_BUFSZ,
|
||||
};
|
||||
|
||||
/*manage the serial device operations*/
|
||||
static const struct SerialDrvDone drv_done =
|
||||
{
|
||||
.init = SerialInit,
|
||||
.configure = SerialConfigure,
|
||||
};
|
||||
|
||||
/*manage the serial device hal operations*/
|
||||
static struct SerialHwDevDone hwdev_done =
|
||||
{
|
||||
.put_char = SerialPutChar,
|
||||
.get_char = SerialGetChar,
|
||||
};
|
||||
|
||||
static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
|
||||
/*Init the serial bus */
|
||||
ret = SerialBusInit(serial_bus, bus_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("Imrt1052HwUartInit SerialBusInit error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/*Init the serial driver*/
|
||||
ret = SerialDriverInit(serial_driver, drv_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("Imrt1052HwUartInit SerialDriverInit error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/*Attach the serial driver to the serial bus*/
|
||||
ret = SerialDriverAttachToBus(drv_name, bus_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("Imrt1052HwUartInit SerialDriverAttachToBus error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*Attach the serial device to the serial bus*/
|
||||
static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
|
||||
ret = SerialDeviceRegister(serial_device, serial_param, dev_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("Imrt1052HwUartInit SerialDeviceInit device %s error %d\n", dev_name, ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = SerialDeviceAttachToBus(dev_name, bus_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("Imrt1052HwUartInit SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int Imrt1052HwUartInit(void)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
|
||||
#ifdef BSP_USING_LPUART1
|
||||
static struct SerialCfgParam serial_cfg_1;
|
||||
memset(&serial_cfg_1, 0, sizeof(struct SerialCfgParam));
|
||||
|
||||
static struct SerialDevParam serial_dev_param_1;
|
||||
memset(&serial_dev_param_1, 0, sizeof(struct SerialDevParam));
|
||||
|
||||
serial_driver_1.drv_done = &drv_done;
|
||||
serial_driver_1.configure = &SerialDrvConfigure;
|
||||
serial_device_1.hwdev_done = &hwdev_done;
|
||||
|
||||
serial_cfg_1.data_cfg = data_cfg_init;
|
||||
|
||||
serial_cfg_1.hw_cfg.private_data = (void *)LPUART1;
|
||||
serial_cfg_1.hw_cfg.serial_irq_interrupt = LPUART1_IRQn;
|
||||
serial_driver_1.private_data = (void *)&serial_cfg_1;
|
||||
|
||||
serial_dev_param_1.serial_work_mode = SIGN_OPER_INT_RX;
|
||||
serial_device_1.haldev.private_data = (void *)&serial_dev_param_1;
|
||||
|
||||
ret = BoardSerialBusInit(&serial_bus_1, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1);
|
||||
if (EOK != ret) {
|
||||
KPrintf("Imrt1052HwUartInit uart error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg_1, SERIAL_BUS_NAME_1, SERIAL_1_DEVICE_NAME_0);
|
||||
if (EOK != ret) {
|
||||
KPrintf("Imrt1052HwUartInit uart error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_LPUART2
|
||||
static struct SerialCfgParam serial_cfg_2;
|
||||
memset(&serial_cfg_2, 0, sizeof(struct SerialCfgParam));
|
||||
|
||||
static struct SerialDevParam serial_dev_param_2;
|
||||
memset(&serial_dev_param_2, 0, sizeof(struct SerialDevParam));
|
||||
|
||||
serial_driver_2.drv_done = &drv_done;
|
||||
serial_driver_2.configure = &SerialDrvConfigure;
|
||||
serial_device_2.hwdev_done = &hwdev_done;
|
||||
|
||||
serial_cfg_2.data_cfg = data_cfg_init;
|
||||
|
||||
serial_cfg_2.hw_cfg.private_data = (void *)LPUART2;
|
||||
serial_cfg_2.hw_cfg.serial_irq_interrupt = LPUART2_IRQn;
|
||||
serial_driver_2.private_data = (void *)&serial_cfg_2;
|
||||
|
||||
serial_dev_param_2.serial_work_mode = SIGN_OPER_INT_RX;
|
||||
serial_device_2.haldev.private_data = (void *)&serial_dev_param_2;
|
||||
|
||||
ret = BoardSerialBusInit(&serial_bus_2, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2);
|
||||
if (EOK != ret) {
|
||||
KPrintf("Imrt1052HwUartInit uart error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = BoardSerialDevBend(&serial_device_2, (void *)&serial_cfg_2, SERIAL_BUS_NAME_2, SERIAL_2_DEVICE_NAME_0);
|
||||
if (EOK != ret) {
|
||||
KPrintf("Imrt1052HwUartInit uart error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,15 @@
|
|||
config BSP_USING_NXP_USBH
|
||||
bool "Using usb host by NXP library"
|
||||
default n
|
||||
if BSP_USING_NXP_USBH
|
||||
config USB_BUS_NAME
|
||||
string "usb bus name"
|
||||
default "usb"
|
||||
config USB_DRIVER_NAME
|
||||
string "usb bus driver name"
|
||||
default "usb_drv"
|
||||
config USB_DEVICE_NAME
|
||||
string "usb bus device name"
|
||||
default "usb_dev"
|
||||
endif
|
||||
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
SRC_DIR := nxp_usb_driver
|
||||
|
||||
SRC_FILES := connect_usb.c
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,296 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file connect_usb.c
|
||||
* @brief support usb host function using bus driver framework on OK1052 board
|
||||
* @version 2.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2022-02-09
|
||||
*/
|
||||
|
||||
/*************************************************
|
||||
File name: connect_usb.c
|
||||
Description: support imxrt1052-board usb host configure and sdio bus register function
|
||||
Others: take SDK_2.6.1_MIMXRT1052xxxxB/boards/evkbimxrt1050/usb_examples/usb_host_msd_command for references
|
||||
History:
|
||||
1. Date: 2022-02-09
|
||||
Author: AIIT XUOS Lab
|
||||
Modification:
|
||||
1. support imxrt1052-board usb host configure, write and read
|
||||
2. support imxrt1052-board usb host bus device and driver register
|
||||
*************************************************/
|
||||
#include <board.h>
|
||||
#include <connect_usb.h>
|
||||
|
||||
#define BSP_USING_NXP_USBH
|
||||
#ifdef BSP_USING_NXP_USBH
|
||||
|
||||
/*! @brief USB host msd command instance global variable */
|
||||
extern usb_host_msd_command_instance_t g_MsdCommandInstance;
|
||||
usb_host_handle g_HostHandle;
|
||||
|
||||
extern usb_status_t USB_HostMsdReadApi(usb_host_msd_command_instance_t *msdCommandInstance, uint8_t *buffer, uint32_t pos, uint32_t block_size, uint32_t block_num);
|
||||
extern usb_status_t USB_HostMsdWriteApi(usb_host_msd_command_instance_t *msdCommandInstance, const uint8_t *buffer, uint32_t pos, uint32_t block_size, uint32_t block_num);
|
||||
|
||||
//USB HOST ISR
|
||||
void UsbOtg2IrqHandler(int irqn, void *arg)
|
||||
{
|
||||
x_base lock = 0;
|
||||
lock = DISABLE_INTERRUPT();
|
||||
|
||||
USB_HostEhciIsrFunction(g_HostHandle);
|
||||
|
||||
ENABLE_INTERRUPT(lock);
|
||||
}
|
||||
DECLARE_HW_IRQ(USB2_IRQn, UsbOtg2IrqHandler, NONE);
|
||||
|
||||
void UsbHostClockInit(void)
|
||||
{
|
||||
usb_phy_config_struct_t phyConfig = {
|
||||
BOARD_USB_PHY_D_CAL,
|
||||
BOARD_USB_PHY_TXCAL45DP,
|
||||
BOARD_USB_PHY_TXCAL45DM,
|
||||
};
|
||||
|
||||
if (CONTROLLER_ID == kUSB_ControllerEhci0) {
|
||||
CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
|
||||
CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U);
|
||||
} else {
|
||||
CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
|
||||
CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, 480000000U);
|
||||
}
|
||||
USB_EhciPhyInit(CONTROLLER_ID, BOARD_XTAL0_CLK_HZ, &phyConfig);
|
||||
}
|
||||
|
||||
void UsbHostIsrEnable(void)
|
||||
{
|
||||
uint8_t irqNumber;
|
||||
|
||||
uint8_t usbHOSTEhciIrq[] = USBHS_IRQS;
|
||||
irqNumber = usbHOSTEhciIrq[CONTROLLER_ID - kUSB_ControllerEhci0];
|
||||
/* USB_HOST_CONFIG_EHCI */
|
||||
|
||||
/* Install isr, set priority, and enable IRQ. */
|
||||
NVIC_SetPriority((IRQn_Type)irqNumber, USB_HOST_INTERRUPT_PRIORITY);
|
||||
EnableIRQ((IRQn_Type)irqNumber);
|
||||
}
|
||||
|
||||
void UsbHostTaskFn(void *param)
|
||||
{
|
||||
USB_HostEhciTaskFunction(param);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief USB isr function.
|
||||
*/
|
||||
static usb_status_t UsbHostEvent(usb_device_handle deviceHandle,
|
||||
usb_host_configuration_handle configurationHandle,
|
||||
uint32_t eventCode)
|
||||
{
|
||||
usb_status_t status = kStatus_USB_Success;
|
||||
switch (eventCode)
|
||||
{
|
||||
case kUSB_HostEventAttach:
|
||||
KPrintf("usb device attached\n");
|
||||
status = USB_HostMsdEvent(deviceHandle, configurationHandle, eventCode);
|
||||
break;
|
||||
|
||||
case kUSB_HostEventNotSupported:
|
||||
KPrintf("device not supported.\r\n");
|
||||
break;
|
||||
|
||||
case kUSB_HostEventEnumerationDone:
|
||||
status = USB_HostMsdEvent(deviceHandle, configurationHandle, eventCode);
|
||||
break;
|
||||
|
||||
case kUSB_HostEventDetach:
|
||||
KPrintf("usb device detached\n");
|
||||
status = USB_HostMsdEvent(deviceHandle, configurationHandle, eventCode);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
static void UsbHostApplicationInit(void)
|
||||
{
|
||||
usb_status_t status = kStatus_USB_Success;
|
||||
|
||||
UsbHostClockInit();
|
||||
|
||||
status = USB_HostInit(CONTROLLER_ID, &g_HostHandle, UsbHostEvent);
|
||||
if (status != kStatus_USB_Success) {
|
||||
KPrintf("host init error\r\n");
|
||||
return;
|
||||
}
|
||||
UsbHostIsrEnable();
|
||||
|
||||
KPrintf("host init done\r\n");
|
||||
}
|
||||
|
||||
#if defined(FS_VFS)
|
||||
void UsbMountFileSystem()
|
||||
{
|
||||
if (MountFilesystem(USB_BUS_NAME, USB_DEVICE_NAME, USB_DRIVER_NAME, FSTYPE_FATFS, UDISK_MOUNTPOINT) == 0)
|
||||
KPrintf("Mount FAT on Udisk successful.\n");
|
||||
else
|
||||
KPrintf("Mount FAT on Udisk failed.\n");
|
||||
}
|
||||
|
||||
void UsbUnmountFileSystem()
|
||||
{
|
||||
UnmountFileSystem(UDISK_MOUNTPOINT);
|
||||
}
|
||||
#endif
|
||||
|
||||
static uint32 UsbHostOpen(void *dev)
|
||||
{
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static uint32 UsbHostClose(void *dev)
|
||||
{
|
||||
return EOK;
|
||||
}
|
||||
|
||||
static uint32 UsbHostRead(void *dev, struct BusBlockReadParam *read_param)
|
||||
{
|
||||
usb_status_t status;
|
||||
|
||||
status = USB_HostMsdReadApi(&g_MsdCommandInstance, (uint8 *)read_param->buffer, read_param->pos, USB_SINGLE_BLOCK_SIZE, read_param->size);
|
||||
if (kStatus_USB_Success == status) {
|
||||
return read_param->size;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static uint32 UsbHostWrite(void *dev, struct BusBlockWriteParam *write_param)
|
||||
{
|
||||
usb_status_t status;
|
||||
|
||||
status = USB_HostMsdWriteApi(&g_MsdCommandInstance, (const uint8 *)write_param->buffer, write_param->pos, USB_SINGLE_BLOCK_SIZE, write_param->size);
|
||||
if (kStatus_USB_Success == status) {
|
||||
return write_param->size;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*manage the usb device operations*/
|
||||
static const struct UsbDevDone dev_done =
|
||||
{
|
||||
.open = UsbHostOpen,
|
||||
.close = UsbHostClose,
|
||||
.write = UsbHostWrite,
|
||||
.read = UsbHostRead,
|
||||
};
|
||||
|
||||
static void UsbHostTask(void* parameter)
|
||||
{
|
||||
while (1) {
|
||||
UsbHostTaskFn(g_HostHandle);
|
||||
USB_HostMsdTask(&g_MsdCommandInstance);
|
||||
}
|
||||
}
|
||||
|
||||
/*Init usb host bus、driver*/
|
||||
static int BoardUsbBusInit(struct UsbBus *usb_bus, struct UsbDriver *usb_driver)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
|
||||
/*Init the usb bus */
|
||||
ret = UsbBusInit(usb_bus, USB_BUS_NAME);
|
||||
if (EOK != ret) {
|
||||
KPrintf("board_usb_init UsbBusInit error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/*Init the usb driver*/
|
||||
ret = UsbDriverInit(usb_driver, USB_DRIVER_NAME);
|
||||
if (EOK != ret){
|
||||
KPrintf("board_usb_init UsbDriverInit error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/*Attach the usb driver to the usb bus*/
|
||||
ret = UsbDriverAttachToBus(USB_DRIVER_NAME, USB_BUS_NAME);
|
||||
if (EOK != ret) {
|
||||
KPrintf("board_usb_init USEDriverAttachToBus error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*Attach the usb device to the usb bus*/
|
||||
static int BoardUsbDevBend(void)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
static struct UsbHardwareDevice usb_device;
|
||||
memset(&usb_device, 0, sizeof(struct UsbHardwareDevice));
|
||||
|
||||
usb_device.dev_done = &dev_done;
|
||||
|
||||
ret = USBDeviceRegister(&usb_device, NONE, USB_DEVICE_NAME);
|
||||
if (EOK != ret) {
|
||||
KPrintf("USBDeviceRegister device %s error %d\n", USB_DEVICE_NAME, ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = USBDeviceAttachToBus(USB_DEVICE_NAME, USB_BUS_NAME);
|
||||
if (EOK != ret) {
|
||||
KPrintf("USBDeviceAttachToBus device %s error %d\n", USB_DEVICE_NAME, ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*RT1052 BOARD USB INIT*/
|
||||
int Imrt1052HwUsbHostInit(void)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
int32 usb_host_task = 0;
|
||||
|
||||
static struct UsbBus usb_bus;
|
||||
memset(&usb_bus, 0, sizeof(struct UsbBus));
|
||||
|
||||
static struct UsbDriver usb_driver;
|
||||
memset(&usb_driver, 0, sizeof(struct UsbDriver));
|
||||
|
||||
UsbHostApplicationInit();
|
||||
|
||||
ret = BoardUsbBusInit(&usb_bus, &usb_driver);
|
||||
if (EOK != ret) {
|
||||
KPrintf("BoardUsbBusInit error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = BoardUsbDevBend();
|
||||
if (EOK != ret) {
|
||||
KPrintf("BoardUsbDevBend error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
usb_host_task = KTaskCreate("usbh", UsbHostTask, NONE,
|
||||
USB_HOST_STACK_SIZE, 8);
|
||||
if(usb_host_task < 0) {
|
||||
KPrintf("usb_host_task create failed ...%s %d.\n", __FUNCTION__,__LINE__);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
StartupKTask(usb_host_task);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
SRC_DIR += host phy osa
|
||||
|
||||
SRC_FILES := host_msd_command.c
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
SRC_DIR += class
|
||||
|
||||
SRC_FILES += usb_host_devices.c usb_host_framework.c usb_host_ehci.c usb_host_hci.c
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
SRC_FILES += usb_host_msd_ufi.c usb_host_msd.c usb_host_hub.c usb_host_hub_app.c
|
||||
|
||||
include $(KERNEL_ROOT)/compiler.mk
|
||||
|
|
@ -0,0 +1,608 @@
|
|||
/*
|
||||
* Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "usb_host_config.h"
|
||||
#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB))
|
||||
#include "usb_host.h"
|
||||
#include "usb_host_hub.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief hub control transfer callback.
|
||||
*
|
||||
* @param param callback parameter.
|
||||
* @param transfer callback transfer.
|
||||
* @param status transfer status.
|
||||
*/
|
||||
static void USB_HostHubControlCallback(void *param, usb_host_transfer_t *transfer, usb_status_t status);
|
||||
|
||||
/*!
|
||||
* @brief hub interrupt in transfer callback.
|
||||
*
|
||||
* @param param callback parameter.
|
||||
* @param transfer callback transfer.
|
||||
* @param status transfer status.
|
||||
*/
|
||||
static void USB_HostHubInPipeCallback(void *param, usb_host_transfer_t *transfer, usb_status_t status);
|
||||
|
||||
/*!
|
||||
* @brief USB_HostHubSendPortReset's transfer callback.
|
||||
*
|
||||
* @param param callback parameter.
|
||||
* @param transfer callback transfer.
|
||||
* @param status transfer status.
|
||||
*/
|
||||
static void USB_HostHubResetCallback(void *param, usb_host_transfer_t *transfer, usb_status_t status);
|
||||
|
||||
/*!
|
||||
* @brief hub control transfer common code.
|
||||
*
|
||||
* @param classHandle the class handle.
|
||||
* @param requestType request type.
|
||||
* @param request setup packet request field.
|
||||
* @param wvalue setup packet wValue field.
|
||||
* @param windex setup packet wIndex field.
|
||||
* @param buffer the buffer pointer.
|
||||
* @param bufferLength the buffer length.
|
||||
* @param callbackFn this callback is called after this function completes.
|
||||
* @param callbackParam the first parameter in the callback function.
|
||||
*
|
||||
* @return kStatus_USB_Success or error codes.
|
||||
*/
|
||||
static usb_status_t USB_HostHubClassRequestCommon(usb_host_class_handle classHandle,
|
||||
uint8_t requestType,
|
||||
uint8_t request,
|
||||
uint16_t wvalue,
|
||||
uint16_t windex,
|
||||
uint8_t *buffer,
|
||||
uint16_t bufferLength,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
static void USB_HostHubControlCallback(void *param, usb_host_transfer_t *transfer, usb_status_t status)
|
||||
{
|
||||
usb_host_hub_instance_t *hubInstance = (usb_host_hub_instance_t *)param;
|
||||
|
||||
hubInstance->controlTransfer = NULL;
|
||||
if (hubInstance->controlCallbackFn)
|
||||
{
|
||||
/* callback to application, callback function is initialized in the USB_HostPrinterControl,
|
||||
USB_HostPrinterSetInterface
|
||||
or USB_HostHubClassRequestCommon, but is the same function */
|
||||
hubInstance->controlCallbackFn(hubInstance->controlCallbackParam, transfer->transferBuffer,
|
||||
transfer->transferSofar, status); /* callback to application */
|
||||
}
|
||||
USB_HostFreeTransfer(hubInstance->hostHandle, transfer);
|
||||
}
|
||||
|
||||
static void USB_HostHubInPipeCallback(void *param, usb_host_transfer_t *transfer, usb_status_t status)
|
||||
{
|
||||
usb_host_hub_instance_t *hubInstance = (usb_host_hub_instance_t *)param;
|
||||
|
||||
if (hubInstance->inCallbackFn)
|
||||
{
|
||||
/* callback to application, callback function is initialized in the USB_HostHubInterruptRecv */
|
||||
hubInstance->inCallbackFn(hubInstance->inCallbackParam, transfer->transferBuffer, transfer->transferSofar,
|
||||
status); /* callback to application */
|
||||
}
|
||||
USB_HostFreeTransfer(hubInstance->hostHandle, transfer);
|
||||
}
|
||||
|
||||
static void USB_HostHubResetCallback(void *param, usb_host_transfer_t *transfer, usb_status_t status)
|
||||
{
|
||||
usb_host_hub_instance_t *hubInstance = (usb_host_hub_instance_t *)param;
|
||||
|
||||
/* note: there is not callback to application, the re-enumeration will start automatically after reset. */
|
||||
USB_HostFreeTransfer(hubInstance->hostHandle, transfer);
|
||||
}
|
||||
|
||||
static usb_status_t USB_HostHubClassRequestCommon(usb_host_class_handle classHandle,
|
||||
uint8_t requestType,
|
||||
uint8_t request,
|
||||
uint16_t wvalue,
|
||||
uint16_t windex,
|
||||
uint8_t *buffer,
|
||||
uint16_t bufferLength,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
usb_host_hub_instance_t *hubInstance = (usb_host_hub_instance_t *)classHandle;
|
||||
usb_host_transfer_t *transfer;
|
||||
|
||||
if (hubInstance->controlTransfer != NULL)
|
||||
{
|
||||
return kStatus_USB_Busy;
|
||||
}
|
||||
|
||||
/* get transfer */
|
||||
if (USB_HostMallocTransfer(hubInstance->hostHandle, &transfer) != kStatus_USB_Success)
|
||||
{
|
||||
#ifdef HOST_ECHO
|
||||
usb_echo("error to get transfer\r\n");
|
||||
#endif
|
||||
return kStatus_USB_Error;
|
||||
}
|
||||
|
||||
/* save hub application callback */
|
||||
hubInstance->controlCallbackFn = callbackFn;
|
||||
hubInstance->controlCallbackParam = callbackParam;
|
||||
|
||||
/* initialize transfer */
|
||||
transfer->transferBuffer = buffer;
|
||||
transfer->transferLength = bufferLength;
|
||||
transfer->callbackFn = USB_HostHubControlCallback;
|
||||
transfer->callbackParam = hubInstance;
|
||||
transfer->setupPacket->bmRequestType = requestType;
|
||||
transfer->setupPacket->bRequest = request;
|
||||
transfer->setupPacket->wValue = USB_SHORT_TO_LITTLE_ENDIAN(wvalue);
|
||||
transfer->setupPacket->wIndex = USB_SHORT_TO_LITTLE_ENDIAN(windex);
|
||||
transfer->setupPacket->wLength = USB_SHORT_TO_LITTLE_ENDIAN(bufferLength);
|
||||
|
||||
/* send transfer */
|
||||
if (USB_HostSendSetup(hubInstance->hostHandle, hubInstance->controlPipe, transfer) != kStatus_USB_Success)
|
||||
{
|
||||
#ifdef HOST_ECHO
|
||||
usb_echo("Error in hid get report descriptor\r\n");
|
||||
#endif
|
||||
USB_HostFreeTransfer(hubInstance->hostHandle, transfer);
|
||||
return kStatus_USB_Error;
|
||||
}
|
||||
hubInstance->controlTransfer = transfer; /* record the on-going setup transfer */
|
||||
return kStatus_USB_Success;
|
||||
}
|
||||
|
||||
usb_status_t USB_HostHubInit(usb_device_handle deviceHandle, usb_host_class_handle *classHandle)
|
||||
{
|
||||
/* malloc the hub instance */
|
||||
usb_host_hub_instance_t *hubInstance =
|
||||
(usb_host_hub_instance_t *)USB_OsaMemoryAllocate(sizeof(usb_host_hub_instance_t));
|
||||
|
||||
uint32_t infoValue;
|
||||
|
||||
if (hubInstance == NULL)
|
||||
{
|
||||
return kStatus_USB_AllocFail;
|
||||
}
|
||||
|
||||
#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U))
|
||||
hubInstance->hubDescriptor = (uint8_t *)SDK_Malloc(7 + (USB_HOST_HUB_MAX_PORT >> 3) + 1, USB_CACHE_LINESIZE);
|
||||
hubInstance->portStatusBuffer = (uint8_t *)SDK_Malloc(4, USB_CACHE_LINESIZE);
|
||||
hubInstance->hubStatusBuffer = (uint8_t *)SDK_Malloc(4, USB_CACHE_LINESIZE);
|
||||
hubInstance->hubBitmapBuffer = (uint8_t *)SDK_Malloc((USB_HOST_HUB_MAX_PORT >> 3) + 1, USB_CACHE_LINESIZE);
|
||||
#endif
|
||||
|
||||
/* initialize hub instance structure */
|
||||
hubInstance->deviceHandle = deviceHandle;
|
||||
hubInstance->interfaceHandle = NULL;
|
||||
USB_HostHelperGetPeripheralInformation(deviceHandle, kUSB_HostGetHostHandle, &infoValue);
|
||||
hubInstance->hostHandle = (usb_host_handle)infoValue;
|
||||
USB_HostHelperGetPeripheralInformation(deviceHandle, kUSB_HostGetDeviceControlPipe, &infoValue);
|
||||
hubInstance->controlPipe = (usb_host_pipe_handle)infoValue;
|
||||
USB_HostHelperGetPeripheralInformation(deviceHandle, kUSB_HostGetDeviceLevel, &infoValue);
|
||||
hubInstance->hubLevel = infoValue;
|
||||
|
||||
*classHandle = hubInstance; /* return the hub class handle */
|
||||
return kStatus_USB_Success;
|
||||
}
|
||||
|
||||
usb_status_t USB_HostHubSetInterface(usb_host_class_handle classHandle,
|
||||
usb_host_interface_handle interfaceHandle,
|
||||
uint8_t alternateSetting,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
usb_status_t status;
|
||||
usb_host_hub_instance_t *hubInstance = (usb_host_hub_instance_t *)classHandle;
|
||||
usb_host_interface_t *interface = (usb_host_interface_t *)interfaceHandle;
|
||||
usb_descriptor_endpoint_t *epDesc = NULL;
|
||||
usb_host_pipe_init_t pipeInit;
|
||||
uint8_t epIndex;
|
||||
|
||||
if (classHandle == NULL)
|
||||
{
|
||||
return kStatus_USB_InvalidHandle;
|
||||
}
|
||||
|
||||
hubInstance->interfaceHandle = interfaceHandle; /* save the interface handle */
|
||||
|
||||
/* notify the host driver that the interface is used by class */
|
||||
status = USB_HostOpenDeviceInterface(hubInstance->deviceHandle, interfaceHandle);
|
||||
if (status != kStatus_USB_Success)
|
||||
{
|
||||
return status;
|
||||
}
|
||||
|
||||
/* close opened hub interrupt pipe */
|
||||
if (hubInstance->interruptPipe != NULL)
|
||||
{
|
||||
status = USB_HostCancelTransfer(hubInstance->hostHandle, hubInstance->interruptPipe, NULL);
|
||||
status = USB_HostClosePipe(hubInstance->hostHandle, hubInstance->interruptPipe);
|
||||
if (status != kStatus_USB_Success)
|
||||
{
|
||||
#ifdef HOST_ECHO
|
||||
usb_echo("error when close pipe\r\n");
|
||||
#endif
|
||||
}
|
||||
hubInstance->interruptPipe = NULL;
|
||||
}
|
||||
|
||||
/* open hub interrupt pipe */
|
||||
for (epIndex = 0; epIndex < interface->epCount; ++epIndex)
|
||||
{
|
||||
epDesc = interface->epList[epIndex].epDesc;
|
||||
if (((epDesc->bEndpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) ==
|
||||
USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_IN) &&
|
||||
((epDesc->bmAttributes & USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_TYPE_MASK) == USB_ENDPOINT_INTERRUPT))
|
||||
{
|
||||
/* get pipe information from endpoint descriptor */
|
||||
pipeInit.devInstance = hubInstance->deviceHandle;
|
||||
pipeInit.pipeType = USB_ENDPOINT_INTERRUPT;
|
||||
pipeInit.direction = USB_IN;
|
||||
pipeInit.endpointAddress = (epDesc->bEndpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_NUMBER_MASK);
|
||||
pipeInit.interval = epDesc->bInterval;
|
||||
pipeInit.maxPacketSize = (uint16_t)(USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(epDesc->wMaxPacketSize) &
|
||||
USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_SIZE_MASK);
|
||||
pipeInit.numberPerUframe = (USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(epDesc->wMaxPacketSize) &
|
||||
USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_MASK);
|
||||
pipeInit.nakCount = USB_HOST_CONFIG_MAX_NAK;
|
||||
|
||||
/* open hub interrupt in pipe */
|
||||
status = USB_HostOpenPipe(hubInstance->hostHandle, &hubInstance->interruptPipe, &pipeInit);
|
||||
if (status != kStatus_USB_Success)
|
||||
{
|
||||
#ifdef HOST_ECHO
|
||||
usb_echo("usb_host_hid_set_interface fail to open pipe\r\n");
|
||||
#endif
|
||||
return kStatus_USB_Error;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* hub don't support alternatesetting that is not 0 */
|
||||
if (alternateSetting == 0)
|
||||
{
|
||||
if (callbackFn != NULL)
|
||||
{
|
||||
callbackFn(callbackParam, NULL, 0, kStatus_USB_Success);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
#ifdef HOST_ECHO
|
||||
usb_echo("host don't support alternate setting\r\n");
|
||||
#endif
|
||||
return kStatus_USB_Error;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
usb_status_t USB_HostHubDeinit(usb_device_handle deviceHandle, usb_host_class_handle classHandle)
|
||||
{
|
||||
usb_host_hub_instance_t *hubInstance = (usb_host_hub_instance_t *)classHandle;
|
||||
uint8_t status;
|
||||
if (deviceHandle == NULL)
|
||||
{
|
||||
return kStatus_USB_InvalidHandle;
|
||||
}
|
||||
|
||||
if (classHandle != NULL)
|
||||
{
|
||||
/* close opened hub interrupt pipe */
|
||||
if (hubInstance->interruptPipe != NULL)
|
||||
{
|
||||
status = USB_HostCancelTransfer(hubInstance->hostHandle, hubInstance->interruptPipe, NULL);
|
||||
status = USB_HostClosePipe(hubInstance->hostHandle, hubInstance->interruptPipe);
|
||||
if (status != kStatus_USB_Success)
|
||||
{
|
||||
#ifdef HOST_ECHO
|
||||
usb_echo("hub close interrupt pipe error\r\n");
|
||||
#endif
|
||||
}
|
||||
hubInstance->interruptPipe = NULL;
|
||||
}
|
||||
|
||||
/* cancel control transfer if exist */
|
||||
if ((hubInstance->controlPipe != NULL) && (hubInstance->controlTransfer != NULL))
|
||||
{
|
||||
status =
|
||||
USB_HostCancelTransfer(hubInstance->hostHandle, hubInstance->controlPipe, hubInstance->controlTransfer);
|
||||
}
|
||||
|
||||
/* notify host driver that the interface will not be used */
|
||||
USB_HostCloseDeviceInterface(deviceHandle, hubInstance->interfaceHandle);
|
||||
#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U))
|
||||
SDK_Free(hubInstance->hubDescriptor);
|
||||
SDK_Free(hubInstance->portStatusBuffer);
|
||||
SDK_Free(hubInstance->hubStatusBuffer);
|
||||
SDK_Free(hubInstance->hubBitmapBuffer);
|
||||
#endif
|
||||
USB_OsaMemoryFree(hubInstance);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* notify host driver that the interface will not be used */
|
||||
USB_HostCloseDeviceInterface(deviceHandle, NULL);
|
||||
}
|
||||
|
||||
return kStatus_USB_Success;
|
||||
}
|
||||
|
||||
usb_status_t USB_HostHubInterruptRecv(usb_host_class_handle classHandle,
|
||||
uint8_t *buffer,
|
||||
uint16_t bufferLength,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
usb_host_hub_instance_t *hubInstance = (usb_host_hub_instance_t *)classHandle;
|
||||
usb_host_transfer_t *transfer;
|
||||
|
||||
if (classHandle == NULL)
|
||||
{
|
||||
return kStatus_USB_InvalidHandle;
|
||||
}
|
||||
|
||||
/* get transfer */
|
||||
if (USB_HostMallocTransfer(hubInstance->hostHandle, &transfer) != kStatus_USB_Success)
|
||||
{
|
||||
#ifdef HOST_ECHO
|
||||
usb_echo("error to get transfer\r\n");
|
||||
#endif
|
||||
return kStatus_USB_Error;
|
||||
}
|
||||
|
||||
/* save hub application callback */
|
||||
hubInstance->inCallbackFn = callbackFn;
|
||||
hubInstance->inCallbackParam = callbackParam;
|
||||
|
||||
/* initialize transfer */
|
||||
transfer->transferBuffer = buffer;
|
||||
transfer->transferLength = bufferLength;
|
||||
transfer->callbackFn = USB_HostHubInPipeCallback;
|
||||
transfer->callbackParam = hubInstance;
|
||||
|
||||
/* call host driver API to receive data */
|
||||
if (USB_HostRecv(hubInstance->hostHandle, hubInstance->interruptPipe, transfer) != kStatus_USB_Success)
|
||||
{
|
||||
#ifdef HOST_ECHO
|
||||
usb_echo("failed to USB_HostRecv\r\n");
|
||||
#endif
|
||||
USB_HostFreeTransfer(hubInstance->hostHandle, transfer);
|
||||
return kStatus_USB_Error;
|
||||
}
|
||||
|
||||
return kStatus_USB_Success;
|
||||
}
|
||||
|
||||
usb_status_t USB_HostHubSendPortReset(usb_host_class_handle classHandle, uint8_t portNumber)
|
||||
{
|
||||
usb_host_hub_instance_t *hubInstance = (usb_host_hub_instance_t *)classHandle;
|
||||
usb_host_transfer_t *transfer;
|
||||
|
||||
if (classHandle == NULL)
|
||||
{
|
||||
return kStatus_USB_InvalidHandle;
|
||||
}
|
||||
|
||||
/* get transfer */
|
||||
if (USB_HostMallocTransfer(hubInstance->hostHandle, &transfer) != kStatus_USB_Success)
|
||||
{
|
||||
#ifdef HOST_ECHO
|
||||
usb_echo("error to get transfer\r\n");
|
||||
#endif
|
||||
return kStatus_USB_Busy;
|
||||
}
|
||||
|
||||
/* initialize transfer */
|
||||
transfer->transferBuffer = NULL;
|
||||
transfer->transferLength = 0;
|
||||
transfer->callbackFn = USB_HostHubResetCallback;
|
||||
transfer->callbackParam = hubInstance;
|
||||
transfer->setupPacket->bmRequestType =
|
||||
USB_REQUEST_TYPE_DIR_OUT | USB_REQUEST_TYPE_TYPE_CLASS | USB_REQUEST_TYPE_RECIPIENT_OTHER;
|
||||
transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_SET_FEATURE;
|
||||
transfer->setupPacket->wValue = USB_SHORT_TO_LITTLE_ENDIAN(PORT_RESET);
|
||||
transfer->setupPacket->wIndex = USB_SHORT_TO_LITTLE_ENDIAN(portNumber);
|
||||
transfer->setupPacket->wLength = 0;
|
||||
|
||||
/* send the transfer */
|
||||
if (USB_HostSendSetup(hubInstance->hostHandle, hubInstance->controlPipe, transfer) != kStatus_USB_Success)
|
||||
{
|
||||
#ifdef HOST_ECHO
|
||||
usb_echo("Error in hid get report descriptor\r\n");
|
||||
#endif
|
||||
USB_HostFreeTransfer(hubInstance->hostHandle, transfer);
|
||||
return kStatus_USB_Error;
|
||||
}
|
||||
return kStatus_USB_Success;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief hub get descriptor.
|
||||
*
|
||||
* This function implements get hub descriptor specific request.
|
||||
*
|
||||
* @param classHandle the class handle.
|
||||
* @param buffer the buffer pointer.
|
||||
* @param bufferLength the buffer length.
|
||||
* @param callbackFn this callback is called after this function completes.
|
||||
* @param callbackParam the first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success send successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy There is no idle transfer.
|
||||
* @retval kStatus_USB_Error pipe is not initialized.
|
||||
* Or, send transfer fail, please reference to USB_HostSendSetup.
|
||||
*/
|
||||
usb_status_t USB_HostHubGetDescriptor(usb_host_class_handle classHandle,
|
||||
uint8_t *buffer,
|
||||
uint16_t bufferLength,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
return USB_HostHubClassRequestCommon(
|
||||
classHandle, USB_REQUEST_TYPE_DIR_IN | USB_REQUEST_TYPE_TYPE_CLASS | USB_REQUEST_TYPE_RECIPIENT_DEVICE,
|
||||
USB_REQUEST_STANDARD_GET_DESCRIPTOR, 0x00, 0, buffer, bufferLength, callbackFn, callbackParam);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief hub clear feature.
|
||||
*
|
||||
* This function implements clear hub feature specific request.
|
||||
*
|
||||
* @param classHandle the class handle.
|
||||
* @param buffer the buffer pointer.
|
||||
* @param bufferLength the buffer length.
|
||||
* @param callbackFn this callback is called after this function completes.
|
||||
* @param callbackParam the first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success send successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy There is no idle transfer.
|
||||
* @retval kStatus_USB_Error pipe is not initialized.
|
||||
* Or, send transfer fail, please reference to USB_HostSendSetup.
|
||||
*/
|
||||
usb_status_t USB_HostHubClearFeature(usb_host_class_handle classHandle,
|
||||
uint8_t feature,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
return USB_HostHubClassRequestCommon(classHandle, USB_REQUEST_TYPE_DIR_OUT | USB_REQUEST_TYPE_TYPE_CLASS,
|
||||
USB_REQUEST_STANDARD_CLEAR_FEATURE, feature, 0, NULL, 0, callbackFn,
|
||||
callbackParam);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief hub get status.
|
||||
*
|
||||
* This function implements get hub status specific request.
|
||||
*
|
||||
* @param classHandle the class handle.
|
||||
* @param buffer the buffer pointer.
|
||||
* @param bufferLength the buffer length.
|
||||
* @param callbackFn this callback is called after this function completes.
|
||||
* @param callbackParam the first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success send successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy There is no idle transfer.
|
||||
* @retval kStatus_USB_Error pipe is not initialized.
|
||||
* Or, send transfer fail, please reference to USB_HostSendSetup.
|
||||
*/
|
||||
usb_status_t USB_HostHubGetStatus(usb_host_class_handle classHandle,
|
||||
uint8_t *buffer,
|
||||
uint16_t bufferLength,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
return USB_HostHubClassRequestCommon(classHandle, USB_REQUEST_TYPE_DIR_IN | USB_REQUEST_TYPE_TYPE_CLASS,
|
||||
USB_REQUEST_STANDARD_GET_STATUS, 0, 0, buffer, bufferLength, callbackFn,
|
||||
callbackParam);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief hub set feature.
|
||||
*
|
||||
* This function implements set hub feature specific request.
|
||||
*
|
||||
* @param classHandle the class handle.
|
||||
* @param buffer the buffer pointer.
|
||||
* @param bufferLength the buffer length.
|
||||
* @param callbackFn this callback is called after this function completes.
|
||||
* @param callbackParam the first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success send successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy There is no idle transfer.
|
||||
* @retval kStatus_USB_Error pipe is not initialized.
|
||||
* Or, send transfer fail, please reference to USB_HostSendSetup.
|
||||
*/
|
||||
usb_status_t USB_HostHubSetPortFeature(usb_host_class_handle classHandle,
|
||||
uint8_t portNumber,
|
||||
uint8_t feature,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
return USB_HostHubClassRequestCommon(
|
||||
classHandle, USB_REQUEST_TYPE_DIR_OUT | USB_REQUEST_TYPE_TYPE_CLASS | USB_REQUEST_TYPE_RECIPIENT_OTHER,
|
||||
USB_REQUEST_STANDARD_SET_FEATURE, feature, portNumber, NULL, 0, callbackFn, callbackParam);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief hub clear port feature.
|
||||
*
|
||||
* This function implements clear hub port feature specific request.
|
||||
*
|
||||
* @param classHandle the class handle.
|
||||
* @param buffer the buffer pointer.
|
||||
* @param bufferLength the buffer length.
|
||||
* @param callbackFn this callback is called after this function completes.
|
||||
* @param callbackParam the first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success send successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy There is no idle transfer.
|
||||
* @retval kStatus_USB_Error pipe is not initialized.
|
||||
* Or, send transfer fail, please reference to USB_HostSendSetup.
|
||||
*/
|
||||
usb_status_t USB_HostHubClearPortFeature(usb_host_class_handle classHandle,
|
||||
uint8_t portNumber,
|
||||
uint8_t feature,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
return USB_HostHubClassRequestCommon(
|
||||
classHandle, USB_REQUEST_TYPE_DIR_OUT | USB_REQUEST_TYPE_TYPE_CLASS | USB_REQUEST_TYPE_RECIPIENT_OTHER,
|
||||
USB_REQUEST_STANDARD_CLEAR_FEATURE, feature, portNumber, NULL, 0, callbackFn, callbackParam);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief hub port get status.
|
||||
*
|
||||
* This function implements get hub port status specific request.
|
||||
*
|
||||
* @param classHandle the class handle.
|
||||
* @param buffer the buffer pointer.
|
||||
* @param bufferLength the buffer length.
|
||||
* @param callbackFn this callback is called after this function completes.
|
||||
* @param callbackParam the first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success send successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy There is no idle transfer.
|
||||
* @retval kStatus_USB_Error pipe is not initialized.
|
||||
* Or, send transfer fail, please reference to USB_HostSendSetup.
|
||||
*/
|
||||
usb_status_t USB_HostHubGetPortStatus(usb_host_class_handle classHandle,
|
||||
uint8_t portNumber,
|
||||
uint8_t *buffer,
|
||||
uint16_t bufferLength,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
return USB_HostHubClassRequestCommon(
|
||||
classHandle, USB_REQUEST_TYPE_DIR_IN | USB_REQUEST_TYPE_TYPE_CLASS | USB_REQUEST_TYPE_RECIPIENT_OTHER,
|
||||
USB_REQUEST_STANDARD_GET_STATUS, 0, portNumber, buffer, bufferLength, callbackFn, callbackParam);
|
||||
}
|
||||
|
||||
#endif /* USB_HOST_CONFIG_HUB */
|
||||
|
|
@ -0,0 +1,379 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _USB_HOST_HUB_H_
|
||||
#define _USB_HOST_HUB_H_
|
||||
|
||||
#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB))
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief USB host HUB maximum port count */
|
||||
#define USB_HOST_HUB_MAX_PORT (7U)
|
||||
|
||||
/*! @brief HUB class code */
|
||||
#define USB_HOST_HUB_CLASS_CODE (9U)
|
||||
/*! @brief HUB sub-class code */
|
||||
#define USB_HOST_HUB_SUBCLASS_CODE_NONE (0U)
|
||||
|
||||
/* HUB and PORT status according to Table 11-17 in chapter 11.*/
|
||||
/*! @brief Local Power Status Change: This field indicates that a change has occurred in the HUB's Local Power Source */
|
||||
#define C_HUB_LOCAL_POWER (0U)
|
||||
/*! @brief Over-Current Change: This field indicates if a change has occurred in the Over-Current field*/
|
||||
#define C_HUB_OVER_CURRENT (1U)
|
||||
/*! @brief Current Connect Status: This field reflects whether or not a device is currently connected to this port*/
|
||||
#define PORT_CONNECTION (0U)
|
||||
/*! @brief Port Enabled/Disabled: Ports can be enabled by the USB System Software only. Ports
|
||||
can be disabled by either a fault condition (disconnect event or other fault condition) or by the USB System
|
||||
Software*/
|
||||
#define PORT_ENABLE (1U)
|
||||
/*! @brief Suspend: This field indicates whether or not the device on this port is suspended */
|
||||
#define PORT_SUSPEND (2U)
|
||||
/*! @brief this field indicate that the current drain on the port exceeds the specified maximum. */
|
||||
#define PORT_OVER_CURRENT (3U)
|
||||
/*! @brief This field is set when the host wishes to reset the attached device */
|
||||
#define PORT_RESET (4U)
|
||||
/*! @brief This field reflects a port's logical, power control state */
|
||||
#define PORT_POWER (8U)
|
||||
/*! @brief Low- Speed Device Attached: This is relevant only if a device is attached */
|
||||
#define PORT_LOW_SPEED (9U)
|
||||
/*! @brief High-speed Device Attached: This is relevant only if a device is attached */
|
||||
#define PORT_HIGH_SPEED (10U)
|
||||
/*! @brief Connect Status Change: Indicates a change has occurred in the port's Current Connect Status */
|
||||
#define C_PORT_CONNECTION (16U)
|
||||
/*! @brief Port Enable/Disable Change: This field is set to one when a port is disabled because of a Port_Error
|
||||
* condition */
|
||||
#define C_PORT_ENABLE (17U)
|
||||
/*! @brief Suspend Change: This field indicates a change in the host-visible suspend state of the attached device */
|
||||
#define C_PORT_SUSPEND (18U)
|
||||
/*! @brief Over-Current Indicator Change: This field applies only to HUBs that report over-current conditions on a
|
||||
* per-port basis */
|
||||
#define C_PORT_OVER_CURRENT (19U)
|
||||
/*! @brief Reset Change: This field is set when reset processing on this port is complete */
|
||||
#define C_PORT_RESET (20U)
|
||||
|
||||
/*! @brief Get HUB think time value */
|
||||
#define USB_HOST_HUB_DESCRIPTOR_CHARACTERISTICS_THINK_TIME_MASK (0x60U)
|
||||
/*! @brief Get HUB think time value */
|
||||
#define USB_HOST_HUB_DESCRIPTOR_CHARACTERISTICS_THINK_TIME_SHIFT (5U)
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief HUB descriptor structure */
|
||||
typedef struct _usb_host_hub_descriptor
|
||||
{
|
||||
uint8_t blength; /*!< Number of bytes in this descriptor*/
|
||||
uint8_t bdescriptortype; /*!< Descriptor Type*/
|
||||
uint8_t bnrports; /*!< Number of downstream facing ports that this HUB supports*/
|
||||
uint8_t whubcharacteristics[2]; /*!< HUB characteristics please reference to Table 11-13 in usb2.0 specification*/
|
||||
uint8_t bpwron2pwrgood; /*!< Time (in 2 ms intervals) from the time the power-on sequence begins on a port until
|
||||
power is good on that port.*/
|
||||
uint8_t bhubcontrcurrent; /*!< Maximum current requirements of the HUB Controller electronics in mA*/
|
||||
uint8_t deviceremovable; /*!< Indicates if a port has a removable device attached*/
|
||||
} usb_host_hub_descriptor_t;
|
||||
|
||||
/*! @brief HUB port instance structure */
|
||||
typedef struct _usb_host_hub_port_instance
|
||||
{
|
||||
usb_device_handle deviceHandle; /*!< Device handle*/
|
||||
uint8_t portStatus; /*!< Port running status*/
|
||||
uint8_t resetCount; /*!< Port reset time*/
|
||||
uint8_t speed; /*!< Port's device speed*/
|
||||
} usb_host_hub_port_instance_t;
|
||||
|
||||
/*! @brief HUB instance structure */
|
||||
typedef struct _usb_host_hub_instance
|
||||
{
|
||||
struct _usb_host_hub_instance *next; /*!< Next HUB instance*/
|
||||
usb_host_handle hostHandle; /*!< Host handle*/
|
||||
usb_device_handle deviceHandle; /*!< Device handle*/
|
||||
usb_host_interface_handle interfaceHandle; /*!< Interface handle*/
|
||||
usb_host_pipe_handle controlPipe; /*!< Control pipe handle*/
|
||||
usb_host_pipe_handle interruptPipe; /*!< HUB interrupt in pipe handle*/
|
||||
usb_host_hub_port_instance_t *portList; /*!< HUB's port instance list*/
|
||||
usb_host_transfer_t *controlTransfer; /*!< Control transfer in progress*/
|
||||
transfer_callback_t inCallbackFn; /*!< Interrupt in callback*/
|
||||
void *inCallbackParam; /*!< Interrupt in callback parameter*/
|
||||
transfer_callback_t controlCallbackFn; /*!< Control callback*/
|
||||
void *controlCallbackParam; /*!< Control callback parameter*/
|
||||
/* HUB property */
|
||||
uint16_t totalThinktime; /*!< HUB total think time*/
|
||||
uint8_t hubLevel; /*!< HUB level, the root HUB's level is 1*/
|
||||
|
||||
/* HUB application parameter */
|
||||
#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U))
|
||||
uint8_t *hubDescriptor; /*!< HUB descriptor buffer*/
|
||||
uint8_t *hubBitmapBuffer; /*!< HUB receiving bitmap data buffer*/
|
||||
uint8_t *hubStatusBuffer; /*!< HUB status buffer*/
|
||||
uint8_t *portStatusBuffer; /*!< Port status buffer*/
|
||||
#else
|
||||
uint8_t hubDescriptor[7 + (USB_HOST_HUB_MAX_PORT >> 3) + 1]; /*!< HUB descriptor buffer*/
|
||||
uint8_t hubBitmapBuffer[(USB_HOST_HUB_MAX_PORT >> 3) + 1]; /*!< HUB receiving bitmap data buffer*/
|
||||
uint8_t hubStatusBuffer[4]; /*!< HUB status buffer*/
|
||||
uint8_t portStatusBuffer[4]; /*!< Port status buffer*/
|
||||
#endif
|
||||
uint8_t hubStatus; /*!< HUB instance running status*/
|
||||
uint8_t portCount; /*!< HUB port count*/
|
||||
uint8_t portIndex; /*!< Record the index when processing ports in turn*/
|
||||
uint8_t portProcess; /*!< The port that is processing*/
|
||||
uint8_t primeStatus; /*!< Data prime transfer status*/
|
||||
uint8_t invalid; /*!< 0/1, when invalid, cannot send transfer to the class*/
|
||||
#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U))
|
||||
uint8_t supportRemoteWakeup; /*!< The HUB supports remote wakeup or not*/
|
||||
uint8_t controlRetry; /*!< Retry count for set remote wakeup feature*/
|
||||
#endif
|
||||
} usb_host_hub_instance_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Initializes the HUB instance.
|
||||
*
|
||||
* This function allocates the resource for HUB instance.
|
||||
*
|
||||
* @param deviceHandle The device handle.
|
||||
* @param classHandle Return class handle.
|
||||
*
|
||||
* @retval kStatus_USB_Success The device is initialized successfully.
|
||||
* @retval kStatus_USB_AllocFail Allocate memory fail.
|
||||
*/
|
||||
extern usb_status_t USB_HostHubInit(usb_device_handle deviceHandle, usb_host_class_handle *classHandle);
|
||||
|
||||
/*!
|
||||
* @brief Sets interface.
|
||||
*
|
||||
* This function binds the interfaces with the HUB instance.
|
||||
*
|
||||
* @param classHandle The class handle.
|
||||
* @param interfaceHandle The interface handle.
|
||||
* @param alternateSetting The alternate setting value.
|
||||
* @param callbackFn This callback is called after this function completes.
|
||||
* @param callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success The device is initialized successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy There is no idle transfer.
|
||||
* @retval kStatus_USB_Error Open pipe fail. See the USB_HostOpenPipe.
|
||||
* Or send transfer fail. See the USB_HostSendSetup,
|
||||
*/
|
||||
extern usb_status_t USB_HostHubSetInterface(usb_host_class_handle classHandle,
|
||||
usb_host_interface_handle interfaceHandle,
|
||||
uint8_t alternateSetting,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes the HUB instance.
|
||||
*
|
||||
* This function releases the resource for HUB instance.
|
||||
*
|
||||
* @param deviceHandle The device handle.
|
||||
* @param classHandle The class handle.
|
||||
*
|
||||
* @retval kStatus_USB_Success The device is deinitialized successfully.
|
||||
*/
|
||||
extern usb_status_t USB_HostHubDeinit(usb_device_handle deviceHandle, usb_host_class_handle classHandle);
|
||||
|
||||
/*!
|
||||
* @brief Receives data.
|
||||
*
|
||||
* This function implements the HUB receiving data.
|
||||
*
|
||||
* @param classHandle The class handle.
|
||||
* @param buffer The buffer pointer.
|
||||
* @param bufferLength The buffer length.
|
||||
* @param callbackFn This callback is called after this function completes.
|
||||
* @param callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success Receive request successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy There is no idle transfer.
|
||||
* @retval kStatus_USB_Error Pipe is not initialized.
|
||||
* Or, send transfer fail. See the USB_HostRecv.
|
||||
*/
|
||||
extern usb_status_t USB_HostHubInterruptRecv(usb_host_class_handle classHandle,
|
||||
uint8_t *buffer,
|
||||
uint16_t bufferLength,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Port reset setup.
|
||||
*
|
||||
* This function sends the HUB port reset transfer.
|
||||
*
|
||||
* @param classHandle The class handle.
|
||||
* @param portNumber Port number.
|
||||
*
|
||||
* @retval kStatus_USB_Success Send successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy There is no idle transfer.
|
||||
* @retval kStatus_USB_Error Pipe is not initialized.
|
||||
* Or, send transfer fail. See the USB_HostSendSetup.
|
||||
*/
|
||||
extern usb_status_t USB_HostHubSendPortReset(usb_host_class_handle classHandle, uint8_t portNumber);
|
||||
|
||||
/*!
|
||||
* @brief HUB get descriptor.
|
||||
*
|
||||
* This function implements get HUB descriptor-specific request.
|
||||
*
|
||||
* @param classHandle The class handle.
|
||||
* @param buffer The buffer pointer.
|
||||
* @param bufferLength The buffer length.
|
||||
* @param callbackFn This callback is called after this function completes.
|
||||
* @param callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success Send successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy There is no idle transfer.
|
||||
* @retval kStatus_USB_Error Pipe is not initialized.
|
||||
* Or, send transfer fail. See the USB_HostSendSetup.
|
||||
*/
|
||||
extern usb_status_t USB_HostHubGetDescriptor(usb_host_class_handle classHandle,
|
||||
uint8_t *buffer,
|
||||
uint16_t bufferLength,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief HUB clear feature.
|
||||
*
|
||||
* This function implements clear HUB feature specific request.
|
||||
*
|
||||
* @param classHandle the class handle.
|
||||
* @param buffer the buffer pointer.
|
||||
* @param bufferLength the buffer length.
|
||||
* @param callbackFn this callback is called after this function completes.
|
||||
* @param callbackParam the first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success send successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy There is no idle transfer.
|
||||
* @retval kStatus_USB_Error pipe is not initialized.
|
||||
* Or, send transfer fail, please reference to USB_HostSendSetup.
|
||||
*/
|
||||
extern usb_status_t USB_HostHubClearFeature(usb_host_class_handle classHandle,
|
||||
uint8_t feature,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief HUB get status.
|
||||
*
|
||||
* This function implements the get HUB status-specific request.
|
||||
*
|
||||
* @param classHandle The class handle.
|
||||
* @param buffer The buffer pointer.
|
||||
* @param bufferLength The buffer length.
|
||||
* @param callbackFn This callback is called after this function completes.
|
||||
* @param callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success Send successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy There is no idle transfer.
|
||||
* @retval kStatus_USB_Error Pipe is not initialized.
|
||||
* Or, send transfer fail. See the USB_HostSendSetup.
|
||||
*/
|
||||
extern usb_status_t USB_HostHubGetStatus(usb_host_class_handle classHandle,
|
||||
uint8_t *buffer,
|
||||
uint16_t bufferLength,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief HUB set feature.
|
||||
*
|
||||
* This function implements the set HUB feature-specific request.
|
||||
*
|
||||
* @param classHandle The class handle.
|
||||
* @param buffer The buffer pointer.
|
||||
* @param bufferLength The buffer length.
|
||||
* @param callbackFn This callback is called after this function completes.
|
||||
* @param callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success Send successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy There is no idle transfer.
|
||||
* @retval kStatus_USB_Error Pipe is not initialized.
|
||||
* Or, send transfer fail. See the USB_HostSendSetup.
|
||||
*/
|
||||
extern usb_status_t USB_HostHubSetPortFeature(usb_host_class_handle classHandle,
|
||||
uint8_t portNumber,
|
||||
uint8_t feature,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief HUB clear port feature.
|
||||
*
|
||||
* This function implements the clear HUB port feature-specific request.
|
||||
*
|
||||
* @param classHandle The class handle.
|
||||
* @param buffer The buffer pointer.
|
||||
* @param bufferLength The buffer length.
|
||||
* @param callbackFn This callback is called after this function completes.
|
||||
* @param callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success Send successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy There is no idle transfer.
|
||||
* @retval kStatus_USB_Error Pipe is not initialized.
|
||||
* Or, send transfer fail. See the USB_HostSendSetup.
|
||||
*/
|
||||
extern usb_status_t USB_HostHubClearPortFeature(usb_host_class_handle classHandle,
|
||||
uint8_t portNumber,
|
||||
uint8_t feature,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief HUB port get status.
|
||||
*
|
||||
* This function implements the get HUB port status-specific request.
|
||||
*
|
||||
* @param classHandle The class handle.
|
||||
* @param buffer The buffer pointer.
|
||||
* @param bufferLength The buffer length.
|
||||
* @param callbackFn This callback is called after this function completes.
|
||||
* @param callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success Send successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy There is no idle transfer.
|
||||
* @retval kStatus_USB_Error Pipe is not initialized.
|
||||
* Or, send transfer fail. See the USB_HostSendSetup.
|
||||
*/
|
||||
extern usb_status_t USB_HostHubGetPortStatus(usb_host_class_handle classHandle,
|
||||
uint8_t portNumber,
|
||||
uint8_t *buffer,
|
||||
uint16_t bufferLength,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* USB_HOST_CONFIG_HUB */
|
||||
|
||||
#endif /* _USB_HSOT_HUB_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _USB_HOST_HUB_APP_H_
|
||||
#define _USB_HOST_HUB_APP_H_
|
||||
|
||||
#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB))
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief HUB reset times*/
|
||||
#define USB_HOST_HUB_PORT_RESET_TIMES (1)
|
||||
|
||||
#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U))
|
||||
/*! @brief HUB Control tansaction retry times for remote wakeup*/
|
||||
#define USB_HOST_HUB_REMOTE_WAKEUP_TIMES (3U)
|
||||
#endif
|
||||
|
||||
/*! @brief HUB application global structure */
|
||||
typedef struct _usb_host_hub_global
|
||||
{
|
||||
usb_host_handle hostHandle; /*!< This HUB list belong to this host*/
|
||||
usb_host_hub_instance_t *hubProcess; /*!< HUB in processing*/
|
||||
usb_host_hub_instance_t *hubList; /*!< host's HUB list*/
|
||||
usb_osa_mutex_handle hubMutex; /*!< HUB mutex*/
|
||||
} usb_host_hub_global_t;
|
||||
|
||||
/*! @brief HUB application status */
|
||||
typedef enum _usb_host_hub_app_status
|
||||
{
|
||||
kHubRunIdle = 0, /*!< Idle */
|
||||
kHubRunInvalid, /*!< Invalid state */
|
||||
kHubRunWaitSetInterface, /*!< Wait callback of set interface */
|
||||
kHubRunGetDescriptor7, /*!< Get 7 bytes HUB descriptor */
|
||||
kHubRunGetDescriptor, /*!< Get all HUB descriptor */
|
||||
kHubRunSetPortPower, /*!< Set HUB's port power */
|
||||
kHubRunGetStatusDone, /*!< HUB status changed */
|
||||
kHubRunClearDone, /*!< clear HUB feature callback */
|
||||
} usb_host_hub_app_status_t;
|
||||
|
||||
/*! @brief HUB port application status */
|
||||
typedef enum _usb_host_port_app_status
|
||||
{
|
||||
kPortRunIdle = 0, /*!< Idle */
|
||||
kPortRunInvalid, /*!< Invalid state */
|
||||
kPortRunWaitPortChange, /*!< Wait port status change */
|
||||
kPortRunCheckCPortConnection, /*!< Check C_PORT_CONNECTION */
|
||||
kPortRunGetPortConnection, /*!< Get port status data */
|
||||
kPortRunCheckPortConnection, /*!< Check PORT_CONNECTION */
|
||||
kPortRunWaitPortResetDone, /*!< Wait port reset transfer done */
|
||||
kPortRunWaitCPortReset, /*!< Wait C_PORT_RESET */
|
||||
KPortRunCheckCPortReset, /*!< Check C_PORT_RESET */
|
||||
kPortRunResetAgain, /*!< Reset port again */
|
||||
kPortRunPortAttached, /*!< Device is attached on the port */
|
||||
kPortRunCheckPortDetach, /*!< Check port is detached */
|
||||
kPortRunGetConnectionBit, /*!< Get the port status data */
|
||||
kPortRunCheckConnectionBit, /*!< Check PORT_CONNECTION */
|
||||
#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U))
|
||||
kPortRunClearCPortSuspend, /*!< Clear C_PORT_SUSPEND */
|
||||
kPortRunCheckPortSuspend, /*!< Check PORT_SUSPEND */
|
||||
kPortRunPortSuspended, /*!< Port is suspended */
|
||||
#endif
|
||||
} usb_host_port_app_status_t;
|
||||
|
||||
/*! @brief HUB data prime status */
|
||||
typedef enum _usb_host_hub_prime_status
|
||||
{
|
||||
kPrimeNone = 0, /*!< Don't prime data*/
|
||||
kPrimeHubControl, /*!< Prime HUB control transfer*/
|
||||
kPrimePortControl, /*!< Prime port control transfer*/
|
||||
kPrimeInterrupt, /*!< Prime interrupt transfer*/
|
||||
} usb_host_hub_prime_status_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#endif /* USB_HOST_CONFIG_HUB */
|
||||
|
||||
#endif /* _USB_HOST_HUB_APP_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,851 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _USB_HOST_MSD_H_
|
||||
#define _USB_HOST_MSD_H_
|
||||
|
||||
/*******************************************************************************
|
||||
* MSD class private structure, enumeration, macro
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/* CBW and CSW Macros */
|
||||
#define USB_HOST_MSD_CBW_FLAGS_DIRECTION_OUT (0x00U)
|
||||
#define USB_HOST_MSD_CBW_FLAGS_DIRECTION_IN (0x80U)
|
||||
#define USB_HOST_MSD_CBW_SIGNATURE (0x43425355U)
|
||||
#define USB_HOST_MSD_CSW_SIGNATURE (0x53425355U)
|
||||
|
||||
/* UFI data bit macro */
|
||||
#define USB_HOST_UFI_BLOCK_DATA_VALID_LENGTH (10U)
|
||||
#define USB_HOST_UFI_LOGICAL_UNIT_POSITION (5U)
|
||||
#define USB_HOST_UFI_CBW_LENGTH (31U)
|
||||
#define USB_HOST_UFI_CSW_LENGTH (13U)
|
||||
#define USB_HOST_UFI_MODE_SENSE_PAGE_CONTROL_SHIFT (6U)
|
||||
#define USB_HOST_UFI_MODE_SENSE_PAGE_CODE_SHIFT (0U)
|
||||
#define USB_HOST_UFI_START_STOP_UNIT_LOEJ_SHIFT (1U)
|
||||
#define USB_HOST_UFI_START_STOP_UNIT_START_SHIFT (0U)
|
||||
#define USB_HOST_UFI_SEND_DIAGNOSTIC_SELF_TEST_SHIFT (2U)
|
||||
|
||||
/*******************************************************************************
|
||||
* MSD class public structure, enumeration, macro, function
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @addtogroup usb_host_msc_drv
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @brief retry time when transfer fail, when all the retries fail the transfer callback with error status */
|
||||
#define USB_HOST_MSD_RETRY_MAX_TIME (1U)
|
||||
/*! @brief mass storage block size */
|
||||
#define USB_HOST_MSD_BLOCK_SIZE (512U)
|
||||
|
||||
/*! @brief MSD class code */
|
||||
#define USB_HOST_MSD_CLASS_CODE (8U)
|
||||
/*! @brief MSD sub-class code */
|
||||
#define USB_HOST_MSD_SUBCLASS_CODE_UFI (4U)
|
||||
/*! @brief MSD sub-class code */
|
||||
#define USB_HOST_MSD_SUBCLASS_CODE_SCSI (6U)
|
||||
/*! @brief MSD protocol code */
|
||||
#define USB_HOST_MSD_PROTOCOL_BULK (0x50U)
|
||||
|
||||
/*! @brief MSD class-specific request (mass storage reset) */
|
||||
#define USB_HOST_HID_MASS_STORAGE_RESET (0xFFU)
|
||||
/*! @brief MSD class-specific request (get maximum logical unit number) */
|
||||
#define USB_HOST_HID_GET_MAX_LUN (0xFEU)
|
||||
|
||||
/*! @brief UFI command process status */
|
||||
typedef enum _usb_host_msd_command_status
|
||||
{
|
||||
kMSD_CommandIdle = 0,
|
||||
kMSD_CommandTransferCBW,
|
||||
kMSD_CommandTransferData,
|
||||
kMSD_CommandTransferCSW,
|
||||
kMSD_CommandDone,
|
||||
kMSD_CommandCancel,
|
||||
kMSD_CommandErrorDone,
|
||||
} usb_host_msd_command_status_t;
|
||||
|
||||
/*! @brief MSC Bulk-Only command block wrapper (CBW) */
|
||||
typedef struct _usb_host_cbw
|
||||
{
|
||||
uint32_t CBWSignature; /*!< Signature that helps identify this data packet as a CBW. The signature field shall
|
||||
contain the value 43425355h (little endian), indicating a CBW */
|
||||
uint32_t
|
||||
CBWTag; /*!< A Command Block Tag sent by the host. The device shall echo the contents of this field back to the
|
||||
host in the dCSWTag field of the associated CSW */
|
||||
uint32_t CBWDataTransferLength; /*!< The number of bytes of data that the host expects to transfer on the Bulk-In or
|
||||
Bulk-Out endpoint during the execution of this command */
|
||||
uint8_t CBWFlags; /*!<
|
||||
Bit 7 Direction - the device shall ignore this bit if the dCBWDataTransferLength field is
|
||||
zero, otherwise:
|
||||
0 = Data-Out from host to the device,
|
||||
1 = Data-In from the device to the host.
|
||||
Bit 6 Obsolete. The host shall set this bit to zero.
|
||||
Bits 5..0 Reserved - the host shall set these bits to zero.
|
||||
*/
|
||||
uint8_t CBWLun; /*!< The device Logical Unit Number (LUN) to which the command block is being sent */
|
||||
uint8_t CBWCBLength; /*!< The valid length of the CBWCB in bytes. This defines the valid length of the command
|
||||
block. The only legal values are 1 through 16 (01h through 10h).*/
|
||||
uint8_t CBWCB[16]; /*!< The command block to be executed by the device*/
|
||||
} usb_host_cbw_t;
|
||||
|
||||
/*! @brief MSC Bulk-Only command status wrapper (CSW) */
|
||||
typedef struct _usb_host_csw
|
||||
{
|
||||
uint32_t CSWSignature; /*!< Signature that helps identify this data packet as a CSW. The signature field shall
|
||||
contain the value 53425355h (little endian), indicating CSW.*/
|
||||
uint32_t CSWTag; /*!< The device shall set this field to the value received in the dCBWTag of the associated CBW*/
|
||||
uint32_t CSWDataResidue; /*!< the difference between the amount of data expected as stated in the
|
||||
dCBWDataTransferLength and the actual amount of relevant data processed by the device.*/
|
||||
uint8_t CSWStatus; /*!<
|
||||
bCSWStatus indicates the success or failure of the command.
|
||||
00h - Command passed.
|
||||
01h - Command Failed.
|
||||
02h - Phase error.
|
||||
others - Reserved.
|
||||
*/
|
||||
} usb_host_csw_t;
|
||||
|
||||
/*! @brief MSC UFI command information structure */
|
||||
typedef struct _usb_host_msd_command
|
||||
{
|
||||
usb_host_cbw_t cbwBlock; /*!< CBW data block*/
|
||||
usb_host_csw_t cswBlock; /*!< CSW data block*/
|
||||
uint8_t *dataBuffer; /*!< Data buffer pointer*/
|
||||
uint32_t dataLength; /*!< Data buffer length*/
|
||||
uint32_t dataSofar; /*!< Successful transfer data length*/
|
||||
usb_host_transfer_t *transfer; /*!< The transfer is used for processing the UFI command*/
|
||||
uint8_t retryTime; /*!< The UFI command residual retry time, when it reduce to zero the UFI command fail */
|
||||
uint8_t dataDirection; /*!< The data direction, its value is USB_OUT or USB_IN*/
|
||||
} usb_host_msd_command_t;
|
||||
|
||||
/*! @brief MSD instance structure, MSD usb_host_class_handle pointer to this structure */
|
||||
typedef struct _usb_host_msd_instance
|
||||
{
|
||||
usb_host_handle hostHandle; /*!< This instance's related host handle*/
|
||||
usb_device_handle deviceHandle; /*!< This instance's related device handle*/
|
||||
usb_host_interface_handle interfaceHandle; /*!< This instance's related interface handle*/
|
||||
usb_host_pipe_handle controlPipe; /*!< This instance's related device control pipe*/
|
||||
usb_host_pipe_handle outPipe; /*!< MSD bulk out pipe*/
|
||||
usb_host_pipe_handle inPipe; /*!< MSD bulk in pipe*/
|
||||
transfer_callback_t commandCallbackFn; /*!< MSD UFI command callback function pointer*/
|
||||
void *commandCallbackParam; /*!< MSD UFI command callback parameter*/
|
||||
transfer_callback_t controlCallbackFn; /*!< MSD control transfer callback function pointer*/
|
||||
void *controlCallbackParam; /*!< MSD control transfer callback parameter*/
|
||||
usb_host_transfer_t *controlTransfer; /*!< Ongoing control transfer*/
|
||||
usb_host_msd_command_t msdCommand; /*!< Ongoing MSD UFI command information*/
|
||||
uint8_t commandStatus; /*!< UFI command process status, see command_status_t*/
|
||||
uint8_t internalResetRecovery; /*!< 1 - class driver internal mass storage reset recovery is on-going; 0 -
|
||||
application call USB_HostMsdMassStorageReset to reset or there is no reset*/
|
||||
} usb_host_msd_instance_t;
|
||||
|
||||
/*! @brief UFI standard sense data structure */
|
||||
typedef struct _usb_host_ufi_sense_data
|
||||
{
|
||||
uint8_t errorCode; /*!< This field shall contain a value of 70h to indicate current errors*/
|
||||
uint8_t reserved1; /*!< Reserved field*/
|
||||
uint8_t senseKey; /*!< Provide a hierarchy of error or command result information*/
|
||||
uint8_t information[4]; /*!< This field is command-specific; it is typically used by some commands to return a
|
||||
logical block address denoting where an error occurred*/
|
||||
uint8_t additionalSenseLength; /*!< The UFI device sets the value of this field to ten, to indicate that ten more
|
||||
bytes of sense data follow this field*/
|
||||
uint8_t reserved2[4]; /*!< Reserved field*/
|
||||
uint8_t additionalSenseCode; /*!< Provide a hierarchy of error or command result information*/
|
||||
uint8_t additionalSenseCodeQualifier; /*!< Provide a hierarchy of error or command result information*/
|
||||
uint8_t reserved3[4]; /*!< Reserved field*/
|
||||
} usb_host_ufi_sense_data_t;
|
||||
|
||||
/*! @brief UFI standard inquiry data structure */
|
||||
typedef struct _usb_host_ufi_inquiry_data
|
||||
{
|
||||
uint8_t peripheralDeviceType; /*!< Identifies the device currently connected to the requested logical unit*/
|
||||
uint8_t removableMediaBit; /*!< This shall be set to one to indicate removable media*/
|
||||
uint8_t version; /*!< Version*/
|
||||
uint8_t responseDataFormat; /*!< A value of 01h shall be used for UFI device*/
|
||||
uint8_t additionalLength; /*!< Specify the length in bytes of the parameters*/
|
||||
uint8_t reserved1[3]; /*!< Reserved field*/
|
||||
uint8_t vendorInformation[8]; /*!< Contains 8 bytes of ASCII data identifying the vendor of the product*/
|
||||
uint8_t productIdentification[16]; /*!< Contains 16 bytes of ASCII data as defined by the vendor*/
|
||||
uint8_t productRevisionLevel[4]; /*!< Contains 4 bytes of ASCII data as defined by the vendor*/
|
||||
} usb_host_ufi_inquiry_data_t;
|
||||
|
||||
/*! @brief UFI read capacity data structure */
|
||||
typedef struct _usb_host_ufi_read_capacity
|
||||
{
|
||||
uint8_t lastLogicalBlockAddress[4]; /*!< The logical block number*/
|
||||
uint8_t blockLengthInBytes[4]; /*!< Block size*/
|
||||
} usb_host_ufi_read_capacity_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @name USB host MSD class APIs
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes the MSD instance.
|
||||
*
|
||||
* This function allocates the resources for the MSD instance.
|
||||
*
|
||||
* @param[in] deviceHandle The device handle.
|
||||
* @param[out] classHandle Return class handle.
|
||||
*
|
||||
* @retval kStatus_USB_Success The device is initialized successfully.
|
||||
* @retval kStatus_USB_AllocFail Allocate memory fail.
|
||||
*/
|
||||
extern usb_status_t USB_HostMsdInit(usb_device_handle deviceHandle, usb_host_class_handle *classHandle);
|
||||
|
||||
/*!
|
||||
* @brief Sets the interface.
|
||||
*
|
||||
* This function binds the interface with the MSD instance.
|
||||
*
|
||||
* @param[in] classHandle The class handle.
|
||||
* @param[in] interfaceHandle The interface handle.
|
||||
* @param[in] alternateSetting The alternate setting value.
|
||||
* @param[in] callbackFn This callback is called after this function completes.
|
||||
* @param[in] callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success The device is initialized successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy There is no idle transfer.
|
||||
* @retval kStatus_USB_Error Send transfer fail. See the USB_HostSendSetup.
|
||||
* @retval kStatus_USB_Success Callback return status, the command succeeded.
|
||||
* @retval kStatus_USB_Busy Callback return status, there is no idle pipe.
|
||||
* @retval kStatus_USB_TransferStall Callback return status, the transfer is stalled by the device.
|
||||
* @retval kStatus_USB_Error Callback return status, open pipe fail. See the USB_HostOpenPipe.
|
||||
*/
|
||||
extern usb_status_t USB_HostMsdSetInterface(usb_host_class_handle classHandle,
|
||||
usb_host_interface_handle interfaceHandle,
|
||||
uint8_t alternateSetting,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes the MSD instance.
|
||||
*
|
||||
* This function frees the resource for the MSD instance.
|
||||
*
|
||||
* @param[in] deviceHandle The device handle.
|
||||
* @param[in] classHandle The class handle.
|
||||
*
|
||||
* @retval kStatus_USB_Success The device is de-initialized successfully.
|
||||
*/
|
||||
extern usb_status_t USB_HostMsdDeinit(usb_device_handle deviceHandle, usb_host_class_handle classHandle);
|
||||
|
||||
/*!
|
||||
* @brief Mass storage reset.
|
||||
*
|
||||
* This function implements the mass storage reset request.
|
||||
*
|
||||
* @param[in] classHandle The class handle.
|
||||
* @param[in] callbackFn This callback is called after this function completes.
|
||||
* @param[in] callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success The device is initialized successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy There is no idle transfer.
|
||||
* @retval kStatus_USB_Error Send transfer fail. See the USB_HostSendSetup.
|
||||
*/
|
||||
extern usb_status_t USB_HostMsdMassStorageReset(usb_host_class_handle classHandle,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Gets the maximum logical unit number.
|
||||
*
|
||||
* This function implements the get maximum LUN request.
|
||||
*
|
||||
* @param[in] classHandle The class handle.
|
||||
* @param[out] logicalUnitNumber Return logical unit number value.
|
||||
* @param[in] callbackFn This callback is called after this function completes.
|
||||
* @param[in] callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success The device is initialized successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy There is no idle transfer.
|
||||
* @retval kStatus_USB_Error Send transfer fail. See the USB_HostSendSetup.
|
||||
* @retval kStatus_USB_Success Callback return status, the command succeed.
|
||||
* @retval kStatus_USB_MSDStatusFail Callback return status, the CSW status indicate this command fail.
|
||||
* @retval kStatus_USB_Error Callback return status, the command fail.
|
||||
*/
|
||||
extern usb_status_t USB_HostMsdGetMaxLun(usb_host_class_handle classHandle,
|
||||
uint8_t *logicalUnitNumber,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Mass storage read (10).
|
||||
*
|
||||
* This function implements the UFI READ(10) command. This command requests that the UFI
|
||||
* device transfer data to the host.
|
||||
*
|
||||
* @param[in] classHandle The class MSD handle.
|
||||
* @param[in] logicalUnit Logical unit number.
|
||||
* @param[in] blockAddress The start block address.
|
||||
* @param[out] buffer Buffer pointer.
|
||||
* @param[in] bufferLength The buffer length.
|
||||
* @param[in] blockNumber Read block number.
|
||||
* @param[in] callbackFn This callback is called after this command completes.
|
||||
* @param[in] callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success The device is initialized successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy The previous command is executing or there is no idle transfer.
|
||||
* @retval kStatus_USB_Error Send transfer fail. See the USB_HostSend/USB_HostRecv.
|
||||
* @retval kStatus_USB_Success Callback return status, the command succeed.
|
||||
* @retval kStatus_USB_MSDStatusFail Callback return status, the CSW status indicate this command fail.
|
||||
* @retval kStatus_USB_Error Callback return status, the command fail.
|
||||
*/
|
||||
extern usb_status_t USB_HostMsdRead10(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint32_t blockAddress,
|
||||
uint8_t *buffer,
|
||||
uint32_t bufferLength,
|
||||
uint32_t blockNumber,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Mass storage read (12).
|
||||
*
|
||||
* This function implements the UFI READ(12) command and requests that the UFI
|
||||
* device transfer data to the host.
|
||||
*
|
||||
* @param[in] classHandle The class MSD handle.
|
||||
* @param[in] logicalUnit Logical unit number.
|
||||
* @param[in] blockAddress The start block address.
|
||||
* @param[out] buffer Buffer pointer.
|
||||
* @param[in] bufferLength The buffer length.
|
||||
* @param[in] blockNumber Read block number.
|
||||
* @param[in] callbackFn This callback is called after this command completes.
|
||||
* @param[in] callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success The device is initialized successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy The previous command is executing or there is no idle transfer.
|
||||
* @retval kStatus_USB_Error Send transfer fail. See the USB_HostSend/USB_HostRecv.
|
||||
* @retval kStatus_USB_Success Callback return status, the command succeed.
|
||||
* @retval kStatus_USB_MSDStatusFail Callback return status, the CSW status indicate this command fail.
|
||||
* @retval kStatus_USB_Error Callback return status, the command fail.
|
||||
*/
|
||||
extern usb_status_t USB_HostMsdRead12(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint32_t blockAddress,
|
||||
uint8_t *buffer,
|
||||
uint32_t bufferLength,
|
||||
uint32_t blockNumber,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Mass storage write (10).
|
||||
*
|
||||
* This function implements the UFI WRITE(10) command and requests that the UFI device
|
||||
* write the data transferred by the host to the medium.
|
||||
*
|
||||
* @param[in] classHandle The class MSD handle.
|
||||
* @param[in] logicalUnit Logical unit number.
|
||||
* @param[in] blockAddress The start block address.
|
||||
* @param[in] buffer Buffer pointer.
|
||||
* @param[in] bufferLength The buffer length.
|
||||
* @param[in] blockNumber Write block number.
|
||||
* @param[in] callbackFn This callback is called after this command completes.
|
||||
* @param[in] callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success The device is initialized successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy The previous command is executing or there is no idle transfer.
|
||||
* @retval kStatus_USB_Error Send transfer fail. See the USB_HostSend/USB_HostRecv.
|
||||
* @retval kStatus_USB_Success Callback return status, the command succeed.
|
||||
* @retval kStatus_USB_MSDStatusFail Callback return status, the CSW status indicate this command fail.
|
||||
* @retval kStatus_USB_Error Callback return status, the command fail.
|
||||
*/
|
||||
extern usb_status_t USB_HostMsdWrite10(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint32_t blockAddress,
|
||||
uint8_t *buffer,
|
||||
uint32_t bufferLength,
|
||||
uint32_t blockNumber,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Mass storage write (12).
|
||||
*
|
||||
* This function implements the UFI WRITE(12) command and requests that the UFI device
|
||||
* write the data transferred by the host to the medium.
|
||||
*
|
||||
* @param[in] classHandle The class MSD handle.
|
||||
* @param[in] logicalUnit Logical unit number.
|
||||
* @param[in] blockAddress The start block address.
|
||||
* @param[in] buffer Buffer pointer.
|
||||
* @param[in] bufferLength The buffer length.
|
||||
* @param[in] blockNumber Write block number.
|
||||
* @param[in] callbackFn This callback is called after this command completes.
|
||||
* @param[in] callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success The device is initialized successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy The previous command is executing or there is no idle transfer.
|
||||
* @retval kStatus_USB_Error Send transfer fail. See the USB_HostSend/USB_HostRecv.
|
||||
* @retval kStatus_USB_Success Callback return status, the command succeed.
|
||||
* @retval kStatus_USB_MSDStatusFail Callback return status, the CSW status indicate this command fail.
|
||||
* @retval kStatus_USB_Error Callback return status, the command fail.
|
||||
*/
|
||||
extern usb_status_t USB_HostMsdWrite12(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint32_t blockAddress,
|
||||
uint8_t *buffer,
|
||||
uint32_t bufferLength,
|
||||
uint32_t blockNumber,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Mass storage read capacity.
|
||||
*
|
||||
* This function implements the UFI READ CAPACITY command and allows the host to request
|
||||
* capacities of the currently installed medium.
|
||||
*
|
||||
* @param[in] classHandle The class MSD handle.
|
||||
* @param[in] logicalUnit Logical unit number.
|
||||
* @param[out] buffer Buffer pointer.
|
||||
* @param[in] bufferLength The buffer length.
|
||||
* @param[in] callbackFn This callback is called after this command completes.
|
||||
* @param[in] callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success The device is initialized successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy The previous command is executing or there is no idle transfer.
|
||||
* @retval kStatus_USB_Error Send transfer fail. See the USB_HostSend/USB_HostRecv.
|
||||
* @retval kStatus_USB_Success Callback return status, the command succeed.
|
||||
* @retval kStatus_USB_MSDStatusFail Callback return status, the CSW status indicate this command fail.
|
||||
* @retval kStatus_USB_Error Callback return status, the command fail.
|
||||
*/
|
||||
extern usb_status_t USB_HostMsdReadCapacity(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint8_t *buffer,
|
||||
uint32_t bufferLength,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Mass storage test unit ready.
|
||||
*
|
||||
* This function implements the UFI TEST UNIT READY command and
|
||||
* checks if the UFI device is ready.
|
||||
*
|
||||
* @param[in] classHandle The class MSD handle.
|
||||
* @param[in] logicalUnit Logical unit number.
|
||||
* @param[in] callbackFn This callback is called after this command completes.
|
||||
* @param[in] callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success The device is initialized successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy The previous command is executing or there is no idle transfer.
|
||||
* @retval kStatus_USB_Error Send transfer fail. See the USB_HostSend/USB_HostRecv.
|
||||
* @retval kStatus_USB_Success Callback return status, the command succeed.
|
||||
* @retval kStatus_USB_MSDStatusFail Callback return status, the CSW status indicate this command fail.
|
||||
* @retval kStatus_USB_Error Callback return status, the command fail.
|
||||
*/
|
||||
extern usb_status_t USB_HostMsdTestUnitReady(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief mass storage request sense.
|
||||
*
|
||||
* This function implements the UFI REQUEST SENSE command, this command instructs
|
||||
* the UFI device to transfer sense data to the host for the specified logical unit.
|
||||
*
|
||||
* @param[in] classHandle The class MSD handle.
|
||||
* @param[in] logicalUnit Logical unit number.
|
||||
* @param[out] buffer Buffer pointer.
|
||||
* @param[in] bufferLength The buffer length.
|
||||
* @param[in] callbackFn This callback is called after this command completes.
|
||||
* @param[in] callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success The device is initialized successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy The previous command is executing or there is no idle transfer.
|
||||
* @retval kStatus_USB_Error Send transfer fail. See the USB_HostSend/USB_HostRecv.
|
||||
* @retval kStatus_USB_Success Callback return status, the command succeed.
|
||||
* @retval kStatus_USB_MSDStatusFail Callback return status, the CSW status indicate this command fail.
|
||||
* @retval kStatus_USB_Error Callback return status, the command fail.
|
||||
*/
|
||||
extern usb_status_t USB_HostMsdRequestSense(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint8_t *buffer,
|
||||
uint32_t bufferLength,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Mass storage mode select.
|
||||
*
|
||||
* This function implements the UFI MODE SELECT command and allows the host
|
||||
* to specify medium or device parameters to the UFI device.
|
||||
*
|
||||
* @param[in] classHandle The class MSD handle.
|
||||
* @param[in] logicalUnit Logical unit number.
|
||||
* @param[in] buffer Buffer pointer.
|
||||
* @param[in] bufferLength The buffer length.
|
||||
* @param[in] callbackFn This callback is called after this command completes.
|
||||
* @param[in] callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success The device is initialized successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy The previous command is executing or there is no idle transfer.
|
||||
* @retval kStatus_USB_Error Send transfer fail. See the USB_HostSend/USB_HostRecv.
|
||||
* @retval kStatus_USB_Success Callback return status, the command succeed.
|
||||
* @retval kStatus_USB_MSDStatusFail Callback return status, the CSW status indicate this command fail.
|
||||
* @retval kStatus_USB_Error Callback return status, the command fail.
|
||||
*/
|
||||
extern usb_status_t USB_HostMsdModeSelect(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint8_t *buffer,
|
||||
uint32_t bufferLength,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Mass storage mode sense.
|
||||
*
|
||||
* This function implements the UFI MODE SENSE command and allows the UFI
|
||||
* device to report medium or device parameters to the host.
|
||||
*
|
||||
* @param[in] classHandle The class MSD handle.
|
||||
* @param[in] logicalUnit Logical unit number.
|
||||
* @param[in] pageControl The page control field specifies the type of mode parameters to return.
|
||||
* @param[in] pageCode Buffer pointer.
|
||||
* @param[out] buffer Buffer pointer.
|
||||
* @param[in] bufferLength The buffer length.
|
||||
* @param[in] callbackFn This callback is called after this command completes.
|
||||
* @param[in] callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success The device is initialized successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy The previous command is executing or there is no idle transfer.
|
||||
* @retval kStatus_USB_Error Send transfer fail. See the USB_HostSend/USB_HostRecv.
|
||||
* @retval kStatus_USB_Success Callback return status, the command succeed.
|
||||
* @retval kStatus_USB_MSDStatusFail Callback return status, the CSW status indicate this command fail.
|
||||
* @retval kStatus_USB_Error Callback return status, the command fail.
|
||||
*/
|
||||
extern usb_status_t USB_HostMsdModeSense(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint8_t pageControl,
|
||||
uint8_t pageCode,
|
||||
uint8_t *buffer,
|
||||
uint32_t bufferLength,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Mass storage inquiry.
|
||||
*
|
||||
* This function implements the UFI INQUIRY command and requests that information regarding
|
||||
* parameters of the UFI device itself be sent to the host.
|
||||
*
|
||||
* @param[in] classHandle The class MSD handle.
|
||||
* @param[in] logicalUnit Logical unit number.
|
||||
* @param[out] buffer Buffer pointer.
|
||||
* @param[in] bufferLength The buffer length.
|
||||
* @param[in] callbackFn This callback is called after this command completes.
|
||||
* @param[in] callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success The device is initialized successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy The previous command is executing or there is no idle transfer.
|
||||
* @retval kStatus_USB_Error Send transfer fail. See the USB_HostSend/USB_HostRecv.
|
||||
* @retval kStatus_USB_Success Callback return status, the command succeed.
|
||||
* @retval kStatus_USB_MSDStatusFail Callback return status, the CSW status indicate this command fail.
|
||||
* @retval kStatus_USB_Error Callback return status, the command fail.
|
||||
*/
|
||||
extern usb_status_t USB_HostMsdInquiry(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint8_t *buffer,
|
||||
uint32_t bufferLength,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Mass storage read format capacities.
|
||||
*
|
||||
* This function implements the UFI READ FORMAT CAPACITIES command and allows the host to request
|
||||
* a list of the possible capacities that can be formatted on the currently installed medium.
|
||||
*
|
||||
* @param[in] classHandle The class MSD handle.
|
||||
* @param[in] logicalUnit Logical unit number.
|
||||
* @param[out] buffer Buffer pointer.
|
||||
* @param[in] bufferLength The buffer length.
|
||||
* @param[in] callbackFn This callback is called after this command completes.
|
||||
* @param[in] callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success The device is initialized successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy The previous command is executing or there is no idle transfer.
|
||||
* @retval kStatus_USB_Error Send transfer fail. See the USB_HostSend/USB_HostRecv.
|
||||
* @retval kStatus_USB_Success Callback return status, the command succeed.
|
||||
* @retval kStatus_USB_MSDStatusFail Callback return status, the CSW status indicate this command fail.
|
||||
* @retval kStatus_USB_Error Callback return status, the command fail.
|
||||
*/
|
||||
extern usb_status_t USB_HostMsdReadFormatCapacities(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint8_t *buffer,
|
||||
uint32_t bufferLength,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Mass storage format unit.
|
||||
*
|
||||
* This function implements the UFI FORMAT UNIT command and the host sends this command to physically format one
|
||||
* track of a diskette according to the selected options.
|
||||
*
|
||||
* @param[in] classHandle The class MSD handle.
|
||||
* @param[in] logicalUnit Logical unit number.
|
||||
* @param[in] trackNumber This specifies which track is to be formatted.
|
||||
* @param[in] interLeave This specifies the interleave that shall be used for formatting.
|
||||
* @param[in] buffer Buffer pointer.
|
||||
* @param[in] bufferLength The buffer length.
|
||||
* @param[in] callbackFn This callback is called after this command completes.
|
||||
* @param[in] callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success The device is initialized successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy The previous command is executing or there is no idle transfer.
|
||||
* @retval kStatus_USB_Error Send transfer fail. See the USB_HostSend/USB_HostRecv.
|
||||
* @retval kStatus_USB_Success Callback return status, the command succeed.
|
||||
* @retval kStatus_USB_MSDStatusFail Callback return status, the CSW status indicate this command fail.
|
||||
* @retval kStatus_USB_Error Callback return status, the command fail.
|
||||
*/
|
||||
extern usb_status_t USB_HostMsdFormatUnit(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint8_t trackNumber,
|
||||
uint16_t interLeave,
|
||||
uint8_t *buffer,
|
||||
uint32_t bufferLength,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Mass storage prevents/allows a medium removal.
|
||||
*
|
||||
* This function implements the UFI PREVENT-ALLOW MEDIUM REMOVAL command and notifies the FUI device
|
||||
* to enable or disable the removal of the medium in the logical unit.
|
||||
*
|
||||
* @param[in] classHandle The class MSD handle.
|
||||
* @param[in] logicalUnit Logical unit number.
|
||||
* @param[in] prevent Prevent or allow
|
||||
* - 0: enable (allow) the removal of the medium
|
||||
* - 1: disable (prevent) removal of the medium
|
||||
* @param[in] callbackFn This callback is called after this command completes.
|
||||
* @param[in] callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success The device is initialized successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy The previous command is executing or there is no idle transfer.
|
||||
* @retval kStatus_USB_Error Send transfer fail. See the USB_HostSend/USB_HostRecv.
|
||||
* @retval kStatus_USB_Success Callback return status, the command succeed.
|
||||
* @retval kStatus_USB_MSDStatusFail Callback return status, the CSW status indicate this command fail.
|
||||
* @retval kStatus_USB_Error Callback return status, the command fail.
|
||||
*/
|
||||
extern usb_status_t USB_HostMsdPreventAllowRemoval(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint8_t prevent,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Mass storage write and verify.
|
||||
*
|
||||
* This function implements the UFI WRITE AND VERIFY command and requests that the UFI device
|
||||
* writes the data transferred by the host to the medium, then verifies the data on the medium.
|
||||
*
|
||||
* @param[in] classHandle The class MSD handle.
|
||||
* @param[in] logicalUnit Logical unit number.
|
||||
* @param[in] blockAddress The start block address.
|
||||
* @param[in] buffer Buffer pointer.
|
||||
* @param[in] bufferLength The buffer length.
|
||||
* @param[in] blockNumber Write and verify block number.
|
||||
* @param[in] callbackFn This callback is called after this command completes.
|
||||
* @param[in] callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success The device is initialized successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy The previous command is executing or there is no idle transfer.
|
||||
* @retval kStatus_USB_Error Send transfer fail. See the USB_HostSend/USB_HostRecv.
|
||||
* @retval kStatus_USB_Success Callback return status, the command succeed.
|
||||
* @retval kStatus_USB_MSDStatusFail Callback return status, the CSW status indicate this command fail.
|
||||
* @retval kStatus_USB_Error Callback return status, the command fail.
|
||||
*/
|
||||
extern usb_status_t USB_HostMsdWriteAndVerify(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint32_t blockAddress,
|
||||
uint8_t *buffer,
|
||||
uint32_t bufferLength,
|
||||
uint32_t blockNumber,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Mass storage start stop unit.
|
||||
*
|
||||
* This function implements the UFI START-STOP UNIT command and instructs the UFI device
|
||||
* to enable or disable media access operations .
|
||||
*
|
||||
* @param[in] classHandle The class MSD handle.
|
||||
* @param[in] logicalUnit Logical unit number.
|
||||
* @param[in] loadEject A Load Eject (LoEj) bit of zero requests that no eject action be performed. A LoEj bit of
|
||||
* one, with the
|
||||
* Start bit cleared to zero, which instructs the UFI device to eject the media.
|
||||
* @param[in] start A Start bit of one instructs the UFI device to enable media access operations. A Start bit
|
||||
* of zero instructs the UFI device to disable media access operations.
|
||||
* @param[in] callbackFn This callback is called after this command completes.
|
||||
* @param[in] callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success The device is initialized successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy The previous command is executing or there is no idle transfer.
|
||||
* @retval kStatus_USB_Error Send transfer fail. See the USB_HostSend/USB_HostRecv.
|
||||
* @retval kStatus_USB_Success Callback return status, the command succeed.
|
||||
* @retval kStatus_USB_MSDStatusFail Callback return status, the CSW status indicate this command fail.
|
||||
* @retval kStatus_USB_Error Callback return status, the command fail.
|
||||
*/
|
||||
extern usb_status_t USB_HostMsdStartStopUnit(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint8_t loadEject,
|
||||
uint8_t start,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Mass storage verify.
|
||||
*
|
||||
* This function implements the UFI VERIFY command and requests that the UFI device
|
||||
* verify the data on the medium.
|
||||
*
|
||||
* @param[in] classHandle The class MSD handle.
|
||||
* @param[in] logicalUnit Logical unit number.
|
||||
* @param[in] blockAddress The start block address.
|
||||
* @param[in] verificationLength The data length that need to be verified.
|
||||
* @param[in] callbackFn This callback is called after this command completes.
|
||||
* @param[in] callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success The device is initialized successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy The previous command is executing or there is no idle transfer.
|
||||
* @retval kStatus_USB_Error Send transfer fail. See the USB_HostSend/USB_HostRecv.
|
||||
* @retval kStatus_USB_Success Callback return status, the command succeed.
|
||||
* @retval kStatus_USB_MSDStatusFail Callback return status, the CSW status indicate this command fail.
|
||||
* @retval kStatus_USB_Error Callback return status, the command fail.
|
||||
*/
|
||||
extern usb_status_t USB_HostMsdVerify(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint32_t blockAddress,
|
||||
uint16_t verificationLength,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Mass storage rezero.
|
||||
*
|
||||
* This function implements the UFI REZERO UNIT command. This command positions the head of
|
||||
* the drive to the cylinder 0.
|
||||
*
|
||||
* @param[in] classHandle The class MSD handle.
|
||||
* @param[in] logicalUnit Logical unit number.
|
||||
* @param[in] callbackFn This callback is called after this command completes.
|
||||
* @param[in] callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success The device is initialized successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy The previous command is executing or there is no idle transfer.
|
||||
* @retval kStatus_USB_Error Send transfer fail. See the USB_HostSend/USB_HostRecv.
|
||||
* @retval kStatus_USB_Success Callback return status, the command succeed.
|
||||
* @retval kStatus_USB_MSDStatusFail Callback return status, the CSW status indicate this command fail.
|
||||
* @retval kStatus_USB_Error Callback return status, the command fail.
|
||||
*/
|
||||
extern usb_status_t USB_HostMsdRezeroUnit(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Mass storage seek(10).
|
||||
*
|
||||
* This function implements the UFI SEEK(10) command and requests that the UFI device
|
||||
* seek to the specified Logical Block Address.
|
||||
*
|
||||
* @param[in] classHandle The class MSD handle.
|
||||
* @param[in] logicalUnit Logical unit number.
|
||||
* @param[in] blockAddress The start block address.
|
||||
* @param[in] callbackFn This callback is called after this command completes.
|
||||
* @param[in] callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success The device is initialized successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy The previous command is executing or there is no idle transfer.
|
||||
* @retval kStatus_USB_Error Send transfer fail. See the USB_HostSend/USB_HostRecv.
|
||||
* @retval kStatus_USB_Success Callback return status, the command succeed.
|
||||
* @retval kStatus_USB_MSDStatusFail Callback return status, the CSW status indicate this command fail.
|
||||
* @retval kStatus_USB_Error Callback return status, the command fail.
|
||||
*/
|
||||
extern usb_status_t USB_HostMsdSeek10(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint32_t blockAddress,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*!
|
||||
* @brief Mass storage send diagnostic.
|
||||
*
|
||||
* This function implements the UFI SEND DIAGNOSTIC command. This command requests the UFI device
|
||||
* to do a reset or perform a self-test.
|
||||
*
|
||||
* @param[in] classHandle The class MSD handle.
|
||||
* @param[in] logicalUnit Logical unit number.
|
||||
* @param[in] selfTest 0 = perform special diagnostic test; 1 = perform default self-test.
|
||||
* @param[in] callbackFn This callback is called after this command completes.
|
||||
* @param[in] callbackParam The first parameter in the callback function.
|
||||
*
|
||||
* @retval kStatus_USB_Success The device is initialized successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The classHandle is NULL pointer.
|
||||
* @retval kStatus_USB_Busy The previous command is executing or there is no idle transfer.
|
||||
* @retval kStatus_USB_Error Send transfer fail. See the USB_HostSend/USB_HostRecv.
|
||||
* @retval kStatus_USB_Success Callback return status, the command succeed.
|
||||
* @retval kStatus_USB_MSDStatusFail Callback return status, the CSW status indicate this command fail.
|
||||
* @retval kStatus_USB_Error Callback return status, the command fail.
|
||||
*/
|
||||
extern usb_status_t USB_HostMsdSendDiagnostic(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint8_t selfTest,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam);
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _USB_HOST_MSD_H_ */
|
||||
|
|
@ -0,0 +1,451 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "usb_host_config.h"
|
||||
#if ((defined USB_HOST_CONFIG_MSD) && (USB_HOST_CONFIG_MSD))
|
||||
#include "usb_host.h"
|
||||
#include "usb_host_msd.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/* UFI command code */
|
||||
#define UFI_FORMAT_UNIT (0x04U)
|
||||
#define UFI_INQUIRY (0x12U)
|
||||
#define UFI_START_STOP (0x1BU)
|
||||
#define UFI_MODE_SELECT (0x55U)
|
||||
#define UFI_MODE_SENSE (0x5AU)
|
||||
#define UFI_MEDIUM_REMOVAL (0x1EU)
|
||||
#define UFI_READ10 (0x28U)
|
||||
#define UFI_READ12 (0xA8U)
|
||||
#define UFI_READ_CAPACITY (0x25U)
|
||||
#define UFI_READ_FORMAT_CAPACITY (0x23U)
|
||||
#define UFI_REQUEST_SENSE (0x03U)
|
||||
#define UFI_REZERO_UINT (0x01U)
|
||||
#define UFI_SEEK (0x2BU)
|
||||
#define UFI_SEND_DIAGNOSTIC (0x1DU)
|
||||
#define UFI_TEST_UNIT_READY (0x00U)
|
||||
#define UFI_VERIFY (0x2FU)
|
||||
#define UFI_WRITE10 (0x2AU)
|
||||
#define UFI_WRITE12 (0xAAU)
|
||||
#define UFI_WRITE_VERIFY (0x2EU)
|
||||
|
||||
#define GET_BYTE_FROM_LE_LONG(b, n) \
|
||||
((uint8_t)((USB_LONG_TO_LITTLE_ENDIAN(b)) >> (n * 8))) /* get the byte from the long value */
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
extern usb_status_t USB_HostMsdCommand(usb_host_class_handle classHandle,
|
||||
uint8_t *buffer,
|
||||
uint32_t bufferLength,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam,
|
||||
uint8_t direction,
|
||||
uint8_t byteValues[10]);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
usb_status_t USB_HostMsdRead10(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint32_t blockAddress,
|
||||
uint8_t *buffer,
|
||||
uint32_t bufferLength,
|
||||
uint32_t blockNumber,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
uint8_t ufiBytes[] = {UFI_READ10,
|
||||
(uint8_t)(logicalUnit << USB_HOST_UFI_LOGICAL_UNIT_POSITION),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 3),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 2),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 1),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 0),
|
||||
0x00,
|
||||
GET_BYTE_FROM_LE_LONG(blockNumber, 1),
|
||||
GET_BYTE_FROM_LE_LONG(blockNumber, 0),
|
||||
0x00};
|
||||
return USB_HostMsdCommand(classHandle, buffer, bufferLength, callbackFn, callbackParam,
|
||||
USB_HOST_MSD_CBW_FLAGS_DIRECTION_IN, ufiBytes);
|
||||
}
|
||||
|
||||
usb_status_t USB_HostMsdRead12(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint32_t blockAddress,
|
||||
uint8_t *buffer,
|
||||
uint32_t bufferLength,
|
||||
uint32_t blockNumber,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
uint8_t ufiBytes[] = {UFI_READ12,
|
||||
(uint8_t)(logicalUnit << USB_HOST_UFI_LOGICAL_UNIT_POSITION),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 3),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 2),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 1),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 0),
|
||||
GET_BYTE_FROM_LE_LONG(blockNumber, 3),
|
||||
GET_BYTE_FROM_LE_LONG(blockNumber, 2),
|
||||
GET_BYTE_FROM_LE_LONG(blockNumber, 1),
|
||||
GET_BYTE_FROM_LE_LONG(blockNumber, 0)};
|
||||
return USB_HostMsdCommand(classHandle, buffer, bufferLength, callbackFn, callbackParam,
|
||||
USB_HOST_MSD_CBW_FLAGS_DIRECTION_IN, ufiBytes);
|
||||
}
|
||||
|
||||
usb_status_t USB_HostMsdWrite10(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint32_t blockAddress,
|
||||
uint8_t *buffer,
|
||||
uint32_t bufferLength,
|
||||
uint32_t blockNumber,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
uint8_t ufiBytes[] = {UFI_WRITE10,
|
||||
(uint8_t)(logicalUnit << USB_HOST_UFI_LOGICAL_UNIT_POSITION),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 3),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 2),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 1),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 0),
|
||||
0x00,
|
||||
GET_BYTE_FROM_LE_LONG(blockNumber, 1),
|
||||
GET_BYTE_FROM_LE_LONG(blockNumber, 0),
|
||||
0x00};
|
||||
return USB_HostMsdCommand(classHandle, buffer, bufferLength, callbackFn, callbackParam,
|
||||
USB_HOST_MSD_CBW_FLAGS_DIRECTION_OUT, ufiBytes);
|
||||
}
|
||||
|
||||
usb_status_t USB_HostMsdWrite12(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint32_t blockAddress,
|
||||
uint8_t *buffer,
|
||||
uint32_t bufferLength,
|
||||
uint32_t blockNumber,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
uint8_t ufiBytes[] = {UFI_WRITE12,
|
||||
(uint8_t)(logicalUnit << USB_HOST_UFI_LOGICAL_UNIT_POSITION),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 3),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 2),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 1),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 0),
|
||||
GET_BYTE_FROM_LE_LONG(blockNumber, 3),
|
||||
GET_BYTE_FROM_LE_LONG(blockNumber, 2),
|
||||
GET_BYTE_FROM_LE_LONG(blockNumber, 1),
|
||||
GET_BYTE_FROM_LE_LONG(blockNumber, 0)};
|
||||
return USB_HostMsdCommand(classHandle, buffer, bufferLength, callbackFn, callbackParam,
|
||||
USB_HOST_MSD_CBW_FLAGS_DIRECTION_OUT, ufiBytes);
|
||||
}
|
||||
|
||||
usb_status_t USB_HostMsdReadCapacity(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint8_t *buffer,
|
||||
uint32_t bufferLength,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
uint8_t ufiBytes[] = {UFI_READ_CAPACITY,
|
||||
(uint8_t)(logicalUnit << USB_HOST_UFI_LOGICAL_UNIT_POSITION),
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00};
|
||||
return USB_HostMsdCommand(classHandle, buffer, bufferLength, callbackFn, callbackParam,
|
||||
USB_HOST_MSD_CBW_FLAGS_DIRECTION_IN, ufiBytes);
|
||||
}
|
||||
|
||||
usb_status_t USB_HostMsdTestUnitReady(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
uint8_t ufiBytes[] = {UFI_TEST_UNIT_READY,
|
||||
(uint8_t)(logicalUnit << USB_HOST_UFI_LOGICAL_UNIT_POSITION),
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00};
|
||||
return USB_HostMsdCommand(classHandle, NULL, 0, callbackFn, callbackParam, USB_HOST_MSD_CBW_FLAGS_DIRECTION_OUT,
|
||||
ufiBytes);
|
||||
}
|
||||
|
||||
usb_status_t USB_HostMsdRequestSense(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint8_t *buffer,
|
||||
uint32_t bufferLength,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
uint8_t ufiBytes[] = {UFI_REQUEST_SENSE,
|
||||
(uint8_t)(logicalUnit << USB_HOST_UFI_LOGICAL_UNIT_POSITION),
|
||||
0x00,
|
||||
0x00,
|
||||
(uint8_t)bufferLength,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00};
|
||||
return USB_HostMsdCommand(classHandle, buffer, bufferLength, callbackFn, callbackParam,
|
||||
USB_HOST_MSD_CBW_FLAGS_DIRECTION_IN, ufiBytes);
|
||||
}
|
||||
|
||||
usb_status_t USB_HostMsdModeSelect(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint8_t *buffer,
|
||||
uint32_t bufferLength,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
uint8_t ufiBytes[] = {UFI_MODE_SELECT,
|
||||
(uint8_t)(logicalUnit << USB_HOST_UFI_LOGICAL_UNIT_POSITION),
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
GET_BYTE_FROM_LE_LONG(bufferLength, 1),
|
||||
GET_BYTE_FROM_LE_LONG(bufferLength, 0),
|
||||
0x00};
|
||||
return USB_HostMsdCommand(classHandle, buffer, bufferLength, callbackFn, callbackParam,
|
||||
USB_HOST_MSD_CBW_FLAGS_DIRECTION_OUT, ufiBytes);
|
||||
}
|
||||
|
||||
usb_status_t USB_HostMsdModeSense(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint8_t pageControl,
|
||||
uint8_t pageCode,
|
||||
uint8_t *buffer,
|
||||
uint32_t bufferLength,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
uint8_t ufiBytes[] = {UFI_MODE_SENSE, (uint8_t)(logicalUnit << USB_HOST_UFI_LOGICAL_UNIT_POSITION),
|
||||
(uint8_t)(((uint32_t)pageCode << USB_HOST_UFI_MODE_SENSE_PAGE_CONTROL_SHIFT) |
|
||||
((uint32_t)pageCode << USB_HOST_UFI_MODE_SENSE_PAGE_CODE_SHIFT)),
|
||||
0x00, 0x00, 0x00, 0x00, GET_BYTE_FROM_LE_LONG(bufferLength, 1),
|
||||
GET_BYTE_FROM_LE_LONG(bufferLength, 0), 0x00};
|
||||
return USB_HostMsdCommand(classHandle, buffer, bufferLength, callbackFn, callbackParam,
|
||||
USB_HOST_MSD_CBW_FLAGS_DIRECTION_IN, ufiBytes);
|
||||
}
|
||||
|
||||
usb_status_t USB_HostMsdInquiry(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint8_t *buffer,
|
||||
uint32_t bufferLength,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
uint8_t ufiBytes[] = {UFI_INQUIRY,
|
||||
(uint8_t)(logicalUnit << USB_HOST_UFI_LOGICAL_UNIT_POSITION),
|
||||
0x00,
|
||||
0x00,
|
||||
(uint8_t)bufferLength,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00};
|
||||
return USB_HostMsdCommand(classHandle, buffer, bufferLength, callbackFn, callbackParam,
|
||||
USB_HOST_MSD_CBW_FLAGS_DIRECTION_IN, ufiBytes);
|
||||
}
|
||||
|
||||
usb_status_t USB_HostMsdReadFormatCapacities(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint8_t *buffer,
|
||||
uint32_t bufferLength,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
uint8_t ufiBytes[] = {UFI_READ_FORMAT_CAPACITY,
|
||||
(uint8_t)(logicalUnit << USB_HOST_UFI_LOGICAL_UNIT_POSITION),
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
GET_BYTE_FROM_LE_LONG(bufferLength, 1),
|
||||
GET_BYTE_FROM_LE_LONG(bufferLength, 0),
|
||||
0x00};
|
||||
return USB_HostMsdCommand(classHandle, buffer, bufferLength, callbackFn, callbackParam,
|
||||
USB_HOST_MSD_CBW_FLAGS_DIRECTION_IN, ufiBytes);
|
||||
}
|
||||
|
||||
usb_status_t USB_HostMsdFormatUnit(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint8_t trackNumber,
|
||||
uint16_t interLeave,
|
||||
uint8_t *buffer,
|
||||
uint32_t bufferLength,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
uint8_t ufiBytes[] = {UFI_FORMAT_UNIT,
|
||||
(uint8_t)(logicalUnit << USB_HOST_UFI_LOGICAL_UNIT_POSITION),
|
||||
trackNumber,
|
||||
GET_BYTE_FROM_LE_LONG(interLeave, 1),
|
||||
GET_BYTE_FROM_LE_LONG(interLeave, 0),
|
||||
0x00,
|
||||
0x00,
|
||||
GET_BYTE_FROM_LE_LONG(bufferLength, 1),
|
||||
GET_BYTE_FROM_LE_LONG(bufferLength, 0),
|
||||
0x00};
|
||||
return USB_HostMsdCommand(classHandle, buffer, bufferLength, callbackFn, callbackParam,
|
||||
USB_HOST_MSD_CBW_FLAGS_DIRECTION_OUT, ufiBytes);
|
||||
}
|
||||
|
||||
usb_status_t USB_HostMsdPreventAllowRemoval(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint8_t prevent,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
uint8_t ufiBytes[] = {UFI_MEDIUM_REMOVAL,
|
||||
(uint8_t)(logicalUnit << USB_HOST_UFI_LOGICAL_UNIT_POSITION),
|
||||
0x00,
|
||||
0x00,
|
||||
prevent,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00};
|
||||
return USB_HostMsdCommand(classHandle, NULL, 0, callbackFn, callbackParam, USB_HOST_MSD_CBW_FLAGS_DIRECTION_OUT,
|
||||
ufiBytes);
|
||||
}
|
||||
|
||||
usb_status_t USB_HostMsdWriteAndVerify(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint32_t blockAddress,
|
||||
uint8_t *buffer,
|
||||
uint32_t bufferLength,
|
||||
uint32_t blockNumber,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
uint8_t ufiBytes[] = {UFI_WRITE_VERIFY,
|
||||
(uint8_t)(logicalUnit << USB_HOST_UFI_LOGICAL_UNIT_POSITION),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 3),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 2),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 1),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 0),
|
||||
0x00,
|
||||
GET_BYTE_FROM_LE_LONG(blockNumber, 1),
|
||||
GET_BYTE_FROM_LE_LONG(blockNumber, 0),
|
||||
0x00};
|
||||
return USB_HostMsdCommand(classHandle, buffer, bufferLength, callbackFn, callbackParam,
|
||||
USB_HOST_MSD_CBW_FLAGS_DIRECTION_OUT, ufiBytes);
|
||||
}
|
||||
|
||||
usb_status_t USB_HostMsdStartStopUnit(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint8_t loadEject,
|
||||
uint8_t start,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
uint8_t ufiBytes[] = {UFI_START_STOP, (uint8_t)(logicalUnit << USB_HOST_UFI_LOGICAL_UNIT_POSITION), 0x00, 0x00,
|
||||
(uint8_t)(((uint32_t)loadEject << USB_HOST_UFI_START_STOP_UNIT_LOEJ_SHIFT) |
|
||||
((uint32_t)start << USB_HOST_UFI_START_STOP_UNIT_START_SHIFT)),
|
||||
0x00, 0x00, 0x00, 0x00, 0x00};
|
||||
return USB_HostMsdCommand(classHandle, NULL, 0, callbackFn, callbackParam, USB_HOST_MSD_CBW_FLAGS_DIRECTION_OUT,
|
||||
ufiBytes);
|
||||
}
|
||||
|
||||
usb_status_t USB_HostMsdVerify(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint32_t blockAddress,
|
||||
uint16_t verificationLength,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
uint8_t ufiBytes[] = {UFI_VERIFY,
|
||||
(uint8_t)(logicalUnit << USB_HOST_UFI_LOGICAL_UNIT_POSITION),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 3),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 2),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 1),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 0),
|
||||
0x00,
|
||||
GET_BYTE_FROM_LE_LONG(verificationLength, 1),
|
||||
GET_BYTE_FROM_LE_LONG(verificationLength, 0),
|
||||
0x00};
|
||||
return USB_HostMsdCommand(classHandle, NULL, 0, callbackFn, callbackParam, USB_HOST_MSD_CBW_FLAGS_DIRECTION_OUT,
|
||||
ufiBytes);
|
||||
}
|
||||
|
||||
usb_status_t USB_HostMsdRezeroUnit(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
uint8_t ufiBytes[] = {UFI_REZERO_UINT,
|
||||
(uint8_t)(logicalUnit << USB_HOST_UFI_LOGICAL_UNIT_POSITION),
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00};
|
||||
return USB_HostMsdCommand(classHandle, NULL, 0, callbackFn, callbackParam, USB_HOST_MSD_CBW_FLAGS_DIRECTION_OUT,
|
||||
ufiBytes);
|
||||
}
|
||||
|
||||
usb_status_t USB_HostMsdSeek10(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint32_t blockAddress,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
uint8_t ufiBytes[] = {UFI_SEEK,
|
||||
(uint8_t)(logicalUnit << USB_HOST_UFI_LOGICAL_UNIT_POSITION),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 3),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 2),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 1),
|
||||
GET_BYTE_FROM_LE_LONG(blockAddress, 0),
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00};
|
||||
return USB_HostMsdCommand(classHandle, NULL, 0, callbackFn, callbackParam, USB_HOST_MSD_CBW_FLAGS_DIRECTION_OUT,
|
||||
ufiBytes);
|
||||
}
|
||||
|
||||
usb_status_t USB_HostMsdSendDiagnostic(usb_host_class_handle classHandle,
|
||||
uint8_t logicalUnit,
|
||||
uint8_t selfTest,
|
||||
transfer_callback_t callbackFn,
|
||||
void *callbackParam)
|
||||
{
|
||||
uint8_t ufiBytes[] = {UFI_REZERO_UINT,
|
||||
(uint8_t)(((uint32_t)logicalUnit << USB_HOST_UFI_LOGICAL_UNIT_POSITION) |
|
||||
((uint32_t)selfTest << USB_HOST_UFI_SEND_DIAGNOSTIC_SELF_TEST_SHIFT)),
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
|
||||
return USB_HostMsdCommand(classHandle, NULL, 0, callbackFn, callbackParam, USB_HOST_MSD_CBW_FLAGS_DIRECTION_OUT,
|
||||
ufiBytes);
|
||||
}
|
||||
|
||||
#endif /* USB_HOST_CONFIG_MSD */
|
||||
|
|
@ -0,0 +1,705 @@
|
|||
/*
|
||||
* Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _USB_HOST_H_
|
||||
#define _USB_HOST_H_
|
||||
|
||||
#include "usb.h"
|
||||
#include "usb_misc.h"
|
||||
#include "usb_spec.h"
|
||||
#include "usb_host_framework.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
struct _usb_host_transfer; /* for cross reference */
|
||||
|
||||
/*!
|
||||
* @addtogroup usb_host_drv
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @brief USB host class handle type define */
|
||||
typedef void *usb_host_class_handle;
|
||||
|
||||
/*! @brief USB host controller handle type define */
|
||||
typedef void *usb_host_controller_handle;
|
||||
|
||||
/*! @brief USB host configuration handle type define */
|
||||
typedef void *usb_host_configuration_handle;
|
||||
|
||||
/*! @brief USB host interface handle type define */
|
||||
typedef void *usb_host_interface_handle;
|
||||
|
||||
/*! @brief USB host pipe handle type define */
|
||||
typedef void *usb_host_pipe_handle;
|
||||
|
||||
/*! @brief Event codes for device attach/detach */
|
||||
typedef enum _usb_host_event
|
||||
{
|
||||
kUSB_HostEventAttach = 1U, /*!< Device is attached */
|
||||
kUSB_HostEventDetach, /*!< Device is detached */
|
||||
kUSB_HostEventEnumerationDone, /*!< Device's enumeration is done and the device is supported */
|
||||
kUSB_HostEventNotSupported, /*!< Device's enumeration is done and the device is not supported */
|
||||
#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U))
|
||||
kUSB_HostEventNotSuspended, /*!< Suspend failed */
|
||||
kUSB_HostEventSuspended, /*!< Suspend successful */
|
||||
kUSB_HostEventNotResumed, /*!< Resume failed */
|
||||
kUSB_HostEventDetectResume, /*!< Detect resume signal */
|
||||
kUSB_HostEventResumed, /*!< Resume successful */
|
||||
kUSB_HostEventL1Sleeped, /*!< L1 Sleep successful,state transition was successful (ACK) */
|
||||
kUSB_HostEventL1SleepNYET, /*!< Device was unable to enter the L1 state at this time (NYET) */
|
||||
kUSB_HostEventL1SleepNotSupport, /*!< Device does not support the L1 state (STALL) */
|
||||
kUSB_HostEventL1SleepError, /*!< Device failed to respond or an error occurred */
|
||||
kUSB_HostEventL1NotResumed, /*!< Resume failed */
|
||||
kUSB_HostEventL1DetectResume, /*!< Detect resume signal */
|
||||
kUSB_HostEventL1Resumed, /*!< Resume successful */
|
||||
#endif
|
||||
} usb_host_event_t;
|
||||
|
||||
/*! @brief USB host device information code */
|
||||
typedef enum _usb_host_dev_info
|
||||
{
|
||||
kUSB_HostGetDeviceAddress = 1U, /*!< Device's address */
|
||||
kUSB_HostGetDeviceHubNumber, /*!< Device's first hub address */
|
||||
kUSB_HostGetDevicePortNumber, /*!< Device's first hub port number */
|
||||
kUSB_HostGetDeviceSpeed, /*!< Device's speed */
|
||||
kUSB_HostGetDeviceHSHubNumber, /*!< Device's first high-speed hub address */
|
||||
kUSB_HostGetDeviceHSHubPort, /*!< Device's first high-speed hub number */
|
||||
kUSB_HostGetDeviceLevel, /*!< Device's hub level */
|
||||
kUSB_HostGetHostHandle, /*!< Device's host handle */
|
||||
kUSB_HostGetDeviceControlPipe, /*!< Device's control pipe handle */
|
||||
kUSB_HostGetDevicePID, /*!< Device's PID */
|
||||
kUSB_HostGetDeviceVID, /*!< Device's VID */
|
||||
kUSB_HostGetHubThinkTime, /*!< Device's hub total think time */
|
||||
kUSB_HostGetDeviceConfigIndex, /*!< Device's running zero-based config index */
|
||||
kUSB_HostGetConfigurationDes, /*!< Device's configuration descriptor pointer */
|
||||
kUSB_HostGetConfigurationLength, /*!< Device's configuration descriptor pointer */
|
||||
} usb_host_dev_info_t;
|
||||
|
||||
/*!
|
||||
* @brief Host callback function typedef.
|
||||
*
|
||||
* This callback function is used to notify application device attach/detach event.
|
||||
* This callback pointer is passed when initializing the host.
|
||||
*
|
||||
* @param deviceHandle The device handle, which indicates the attached device.
|
||||
* @param configurationHandle The configuration handle contains the attached device's configuration information.
|
||||
* @param event_code The callback event code; See the enumeration host_event_t.
|
||||
*
|
||||
* @return A USB error code or kStatus_USB_Success.
|
||||
* @retval kStatus_USB_Success Application handles the attached device successfully.
|
||||
* @retval kStatus_USB_NotSupported Application don't support the attached device.
|
||||
* @retval kStatus_USB_Error Application handles the attached device falsely.
|
||||
*/
|
||||
typedef usb_status_t (*host_callback_t)(usb_device_handle deviceHandle,
|
||||
usb_host_configuration_handle configurationHandle,
|
||||
uint32_t eventCode);
|
||||
|
||||
/*!
|
||||
* @brief Transfer callback function typedef.
|
||||
*
|
||||
* This callback function is used to notify the upper layer the result of the transfer.
|
||||
* This callback pointer is passed when calling the send/receive APIs.
|
||||
*
|
||||
* @param param The parameter pointer, which is passed when calling the send/receive APIs.
|
||||
* @param data The data buffer pointer.
|
||||
* @param data_len The result data length.
|
||||
* @param status A USB error code or kStatus_USB_Success.
|
||||
*/
|
||||
typedef void (*transfer_callback_t)(void *param, uint8_t *data, uint32_t dataLen, usb_status_t status);
|
||||
|
||||
/*!
|
||||
* @brief Host stack inner transfer callback function typedef.
|
||||
*
|
||||
* This callback function is used to notify the upper layer the result of a transfer.
|
||||
* This callback pointer is passed when initializing the structure usb_host_transfer_t.
|
||||
*
|
||||
* @param param The parameter pointer, which is passed when calling the send/receive APIs.
|
||||
* @param transfer The transfer information; See the structure usb_host_transfer_t.
|
||||
* @param status A USB error code or kStatus_USB_Success.
|
||||
*/
|
||||
typedef void (*host_inner_transfer_callback_t)(void *param, struct _usb_host_transfer *transfer, usb_status_t status);
|
||||
|
||||
/*! @brief USB host endpoint information structure */
|
||||
typedef struct _usb_host_ep
|
||||
{
|
||||
usb_descriptor_endpoint_t *epDesc; /*!< Endpoint descriptor pointer*/
|
||||
uint8_t *epExtension; /*!< Endpoint extended descriptor pointer*/
|
||||
uint16_t epExtensionLength; /*!< Extended descriptor length*/
|
||||
} usb_host_ep_t;
|
||||
|
||||
/*! @brief USB host interface information structure */
|
||||
typedef struct _usb_host_interface
|
||||
{
|
||||
usb_host_ep_t epList[USB_HOST_CONFIG_INTERFACE_MAX_EP]; /*!< Endpoint array*/
|
||||
usb_descriptor_interface_t *interfaceDesc; /*!< Interface descriptor pointer*/
|
||||
uint8_t *interfaceExtension; /*!< Interface extended descriptor pointer*/
|
||||
uint16_t interfaceExtensionLength; /*!< Extended descriptor length*/
|
||||
uint8_t interfaceIndex; /*!< The interface index*/
|
||||
uint8_t alternateSettingNumber; /*!< The interface alternate setting value*/
|
||||
uint8_t epCount; /*!< Interface's endpoint number*/
|
||||
} usb_host_interface_t;
|
||||
|
||||
/*! @brief USB host configuration information structure */
|
||||
typedef struct _usb_host_configuration
|
||||
{
|
||||
usb_host_interface_t interfaceList[USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE]; /*!< Interface array*/
|
||||
usb_descriptor_configuration_t *configurationDesc; /*!< Configuration descriptor pointer*/
|
||||
uint8_t *configurationExtension; /*!< Configuration extended descriptor pointer*/
|
||||
uint16_t configurationExtensionLength; /*!< Extended descriptor length*/
|
||||
uint8_t interfaceCount; /*!< The configuration's interface number*/
|
||||
} usb_host_configuration_t;
|
||||
|
||||
/*! @brief USB host pipe common structure */
|
||||
typedef struct _usb_host_pipe
|
||||
{
|
||||
struct _usb_host_pipe *next; /*!< Link the idle pipes*/
|
||||
usb_device_handle deviceHandle; /*!< This pipe's device's handle*/
|
||||
uint16_t currentCount; /*!< For KHCI transfer*/
|
||||
uint16_t nakCount; /*!< Maximum NAK count*/
|
||||
uint16_t maxPacketSize; /*!< Maximum packet size*/
|
||||
uint16_t interval; /*!< FS/LS: frame unit; HS: micro-frame unit*/
|
||||
uint8_t open; /*!< 0 - closed, 1 - open*/
|
||||
uint8_t nextdata01; /*!< Data toggle*/
|
||||
uint8_t endpointAddress; /*!< Endpoint address*/
|
||||
uint8_t direction; /*!< Pipe direction*/
|
||||
uint8_t pipeType; /*!< Pipe type, for example USB_ENDPOINT_BULK*/
|
||||
uint8_t numberPerUframe; /*!< Transaction number per micro-frame*/
|
||||
} usb_host_pipe_t;
|
||||
|
||||
/*! @brief USB host transfer structure */
|
||||
typedef struct _usb_host_transfer
|
||||
{
|
||||
struct _usb_host_transfer *next; /*!< The next transfer structure*/
|
||||
uint8_t *transferBuffer; /*!< Transfer data buffer*/
|
||||
uint32_t transferLength; /*!< Transfer data length*/
|
||||
uint32_t transferSofar; /*!< Length transferred so far*/
|
||||
host_inner_transfer_callback_t callbackFn; /*!< Transfer callback function*/
|
||||
void *callbackParam; /*!< Transfer callback parameter*/
|
||||
usb_host_pipe_t *transferPipe; /*!< Transfer pipe pointer*/
|
||||
usb_setup_struct_t *setupPacket; /*!< Set up packet buffer*/
|
||||
uint8_t direction; /*!< Transfer direction; it's values are USB_OUT or USB_IN*/
|
||||
uint8_t setupStatus; /*!< Set up the transfer status*/
|
||||
union
|
||||
{
|
||||
uint32_t unitHead; /*!< xTD head for this transfer*/
|
||||
int32_t transferResult; /*!< KHCI transfer result */
|
||||
} union1;
|
||||
|
||||
union
|
||||
{
|
||||
uint32_t unitTail; /*!<xTD tail for this transfer*/
|
||||
uint32_t frame; /*!< KHCI transfer frame number */
|
||||
} union2;
|
||||
|
||||
#if USB_HOST_CONFIG_KHCI
|
||||
uint16_t nakTimeout; /*!< KHCI transfer NAK timeout */
|
||||
uint16_t retry; /*!< KHCI transfer retry */
|
||||
#endif
|
||||
} usb_host_transfer_t;
|
||||
|
||||
/*! @brief USB host pipe information structure for opening pipe */
|
||||
typedef struct _usb_host_pipe_init
|
||||
{
|
||||
void *devInstance; /*!< Device instance handle*/
|
||||
uint16_t nakCount; /*!< Maximum NAK retry count. MUST be zero for interrupt*/
|
||||
uint16_t maxPacketSize; /*!< Pipe's maximum packet size*/
|
||||
uint8_t interval; /*!< Pipe's interval*/
|
||||
uint8_t endpointAddress; /*!< Endpoint address*/
|
||||
uint8_t direction; /*!< Endpoint direction*/
|
||||
uint8_t pipeType; /*!< Endpoint type, the value is USB_ENDPOINT_INTERRUPT, USB_ENDPOINT_CONTROL,
|
||||
USB_ENDPOINT_ISOCHRONOUS, USB_ENDPOINT_BULK*/
|
||||
uint8_t numberPerUframe; /*!< Transaction number for each micro-frame*/
|
||||
} usb_host_pipe_init_t;
|
||||
|
||||
/*! @brief Cancel transfer parameter structure */
|
||||
typedef struct _usb_host_cancel_param
|
||||
{
|
||||
usb_host_pipe_handle pipeHandle; /*!< Canceling pipe handle*/
|
||||
usb_host_transfer_t *transfer; /*!< Canceling transfer*/
|
||||
} usb_host_cancel_param_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name USB host APIs Part 1
|
||||
* The following APIs are recommended for application use.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes the USB host stack.
|
||||
*
|
||||
* This function initializes the USB host module specified by the controllerId.
|
||||
*
|
||||
* @param[in] controllerId The controller ID of the USB IP. See the enumeration usb_controller_index_t.
|
||||
* @param[out] hostHandle Returns the host handle.
|
||||
* @param[in] callbackFn Host callback function notifies device attach/detach.
|
||||
*
|
||||
* @retval kStatus_USB_Success The host is initialized successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The hostHandle is a NULL pointer.
|
||||
* @retval kStatus_USB_ControllerNotFound Cannot find the controller according to the controller ID.
|
||||
* @retval kStatus_USB_AllocFail Allocation memory fail.
|
||||
* @retval kStatus_USB_Error Host mutex create fail; KHCI/EHCI mutex or KHCI/EHCI event create fail,
|
||||
* or, KHCI/EHCI IP initialize fail.
|
||||
*/
|
||||
extern usb_status_t USB_HostInit(uint8_t controllerId, usb_host_handle *hostHandle, host_callback_t callbackFn);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes the USB host stack.
|
||||
*
|
||||
* This function deinitializes the USB host module specified by the hostHandle.
|
||||
*
|
||||
* @param[in] hostHandle The host handle.
|
||||
*
|
||||
* @retval kStatus_USB_Success The host is initialized successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The hostHandle is a NULL pointer.
|
||||
* @retval kStatus_USB_Error Controller deinitialization fail.
|
||||
*/
|
||||
extern usb_status_t USB_HostDeinit(usb_host_handle hostHandle);
|
||||
|
||||
/*!
|
||||
* @brief Gets the device information.
|
||||
*
|
||||
* This function gets the device information.
|
||||
*
|
||||
* @param[in] deviceHandle Removing device handle.
|
||||
* @param[in] infoCode See the enumeration host_dev_info_t.
|
||||
* @param[out] infoValue Return the information value.
|
||||
*
|
||||
* @retval kStatus_USB_Success Close successfully.
|
||||
* @retval kStatus_USB_InvalidParameter The deviceHandle or info_value is a NULL pointer.
|
||||
* @retval kStatus_USB_Error The info_code is not the host_dev_info_t value.
|
||||
*/
|
||||
extern usb_status_t USB_HostHelperGetPeripheralInformation(usb_device_handle deviceHandle,
|
||||
uint32_t infoCode,
|
||||
uint32_t *infoValue);
|
||||
|
||||
/*!
|
||||
* @brief Parses the alternate interface descriptor.
|
||||
*
|
||||
* This function parses the alternate interface descriptor and returns an interface information through the structure
|
||||
* usb_host_interface_t.
|
||||
*
|
||||
* @param[in] interfaceHandle The whole interface handle.
|
||||
* @param[in] alternateSetting Alternate setting value.
|
||||
* @param[out] interface Return interface information.
|
||||
*
|
||||
* @retval kStatus_USB_Success Close successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The interfaceHandle is a NULL pointer.
|
||||
* @retval kStatus_USB_InvalidParameter The alternateSetting is 0.
|
||||
* @retval kStatus_USB_Error The interface descriptor is wrong.
|
||||
*/
|
||||
extern usb_status_t USB_HostHelperParseAlternateSetting(usb_host_interface_handle interfaceHandle,
|
||||
uint8_t alternateSetting,
|
||||
usb_host_interface_t *interface);
|
||||
|
||||
/*!
|
||||
* @brief Removes the attached device.
|
||||
*
|
||||
* This function removes the attached device.
|
||||
* This function should not be used all the time.
|
||||
*
|
||||
* @param[in] hostHandle The host handle.
|
||||
* @param[in] deviceHandle Removing device handle.
|
||||
*
|
||||
* @retval kStatus_USB_Success Remove successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The hostHandle or deviceHandle is a NULL pointer.
|
||||
* @retval kStatus_USB_InvalidParameter The deviceHandle instance don't belong to hostHandle instance.
|
||||
*/
|
||||
extern usb_status_t USB_HostRemoveDevice(usb_host_handle hostHandle, usb_device_handle deviceHandle);
|
||||
|
||||
/*!
|
||||
* @brief KHCI task function.
|
||||
*
|
||||
* The function is used to handle the KHCI controller message.
|
||||
* In the bare metal environment, this function should be called periodically in the main function.
|
||||
* In the RTOS environment, this function should be used as a function entry to create a task.
|
||||
*
|
||||
* @param[in] hostHandle The host handle.
|
||||
*/
|
||||
extern void USB_HostKhciTaskFunction(void *hostHandle);
|
||||
|
||||
/*!
|
||||
* @brief EHCI task function.
|
||||
*
|
||||
* The function is used to handle the EHCI controller message.
|
||||
* In the bare metal environment, this function should be called periodically in the main function.
|
||||
* In the RTOS environment, this function should be used as a function entry to create a task.
|
||||
*
|
||||
* @param[in] hostHandle The host handle.
|
||||
*/
|
||||
extern void USB_HostEhciTaskFunction(void *hostHandle);
|
||||
|
||||
/*!
|
||||
* @brief OHCI task function.
|
||||
*
|
||||
* The function is used to handle the OHCI controller message.
|
||||
* In the bare metal environment, this function should be called periodically in the main function.
|
||||
* In the RTOS environment, this function should be used as a function entry to create a task.
|
||||
*
|
||||
* @param[in] hostHandle The host handle.
|
||||
*/
|
||||
extern void USB_HostOhciTaskFunction(void *hostHandle);
|
||||
|
||||
/*!
|
||||
* @brief IP3516HS task function.
|
||||
*
|
||||
* The function is used to handle the IP3516HS controller message.
|
||||
* In the bare metal environment, this function should be called periodically in the main function.
|
||||
* In the RTOS environment, this function should be used as a function entry to create a task.
|
||||
*
|
||||
* @param[in] hostHandle The host handle.
|
||||
*/
|
||||
extern void USB_HostIp3516HsTaskFunction(void *hostHandle);
|
||||
|
||||
/*!
|
||||
* @brief Device KHCI ISR function.
|
||||
*
|
||||
* The function is the KHCI interrupt service routine.
|
||||
*
|
||||
* @param[in] hostHandle The host handle.
|
||||
*/
|
||||
extern void USB_HostKhciIsrFunction(void *hostHandle);
|
||||
|
||||
/*!
|
||||
* @brief Device EHCI ISR function.
|
||||
*
|
||||
* The function is the EHCI interrupt service routine.
|
||||
*
|
||||
* @param[in] hostHandle The host handle.
|
||||
*/
|
||||
extern void USB_HostEhciIsrFunction(void *hostHandle);
|
||||
|
||||
/*!
|
||||
* @brief Device OHCI ISR function.
|
||||
*
|
||||
* The function is the OHCI interrupt service routine.
|
||||
*
|
||||
* @param[in] hostHandle The host handle.
|
||||
*/
|
||||
extern void USB_HostOhciIsrFunction(void *hostHandle);
|
||||
|
||||
/*!
|
||||
* @brief Device IP3516HS ISR function.
|
||||
*
|
||||
* The function is the IP3516HS interrupt service routine.
|
||||
*
|
||||
* @param[in] hostHandle The host handle.
|
||||
*/
|
||||
extern void USB_HostIp3516HsIsrFunction(void *hostHandle);
|
||||
|
||||
/*! @}*/
|
||||
|
||||
/*!
|
||||
* @name USB host APIs Part 2.
|
||||
* The following APIs are not recommended for application use. They are mainly used in the class driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Opens the USB host pipe.
|
||||
*
|
||||
* This function opens a pipe according to the pipe_init_ptr parameter.
|
||||
*
|
||||
* @param[in] hostHandle The host handle.
|
||||
* @param[out] pipeHandle The pipe handle pointer used to return the pipe handle.
|
||||
* @param[in] pipeInit Used to initialize the pipe.
|
||||
*
|
||||
* @retval kStatus_USB_Success The host is initialized successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The hostHandle or pipe_handle_ptr is a NULL pointer.
|
||||
* @retval kStatus_USB_Error There is no idle pipe.
|
||||
* Or, there is no idle QH for EHCI.
|
||||
* Or, bandwidth allocate fail for EHCI.
|
||||
*/
|
||||
extern usb_status_t USB_HostOpenPipe(usb_host_handle hostHandle,
|
||||
usb_host_pipe_handle *pipeHandle,
|
||||
usb_host_pipe_init_t *pipeInit);
|
||||
|
||||
/*!
|
||||
* @brief Closes the USB host pipe.
|
||||
*
|
||||
* This function closes a pipe and frees the related resources.
|
||||
*
|
||||
* @param[in] hostHandle The host handle.
|
||||
* @param[in] pipeHandle The closing pipe handle.
|
||||
*
|
||||
* @retval kStatus_USB_Success The host is initialized successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The hostHandle or pipeHandle is a NULL pointer.
|
||||
*/
|
||||
extern usb_status_t USB_HostClosePipe(usb_host_handle hostHandle, usb_host_pipe_handle pipeHandle);
|
||||
|
||||
/*!
|
||||
* @brief Sends data to a pipe.
|
||||
*
|
||||
* This function requests to send the transfer to the specified pipe.
|
||||
*
|
||||
* @param[in] hostHandle The host handle.
|
||||
* @param[in] pipeHandle The sending pipe handle.
|
||||
* @param[in] transfer The transfer information.
|
||||
*
|
||||
* @retval kStatus_USB_Success Send successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The hostHandle, pipeHandle or transfer is a NULL pointer.
|
||||
* @retval kStatus_USB_LackSwapBuffer There is no swap buffer for KHCI.
|
||||
* @retval kStatus_USB_Error There is no idle QTD/ITD/SITD for EHCI.
|
||||
*/
|
||||
extern usb_status_t USB_HostSend(usb_host_handle hostHandle,
|
||||
usb_host_pipe_handle pipeHandle,
|
||||
usb_host_transfer_t *transfer);
|
||||
|
||||
/*!
|
||||
* @brief Sends a setup transfer to the pipe.
|
||||
*
|
||||
* This function request to send the setup transfer to the specified pipe.
|
||||
*
|
||||
* @param[in] hostHandle The host handle.
|
||||
* @param[in] pipeHandle The sending pipe handle.
|
||||
* @param[in] transfer The transfer information.
|
||||
*
|
||||
* @retval kStatus_USB_Success Send successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The hostHandle, pipeHandle or transfer is a NULL pointer.
|
||||
* @retval kStatus_USB_LackSwapBuffer There is no swap buffer for KHCI.
|
||||
* @retval kStatus_USB_Error There is no idle QTD/ITD/SITD for EHCI.
|
||||
*/
|
||||
extern usb_status_t USB_HostSendSetup(usb_host_handle hostHandle,
|
||||
usb_host_pipe_handle pipeHandle,
|
||||
usb_host_transfer_t *transfer);
|
||||
|
||||
/*!
|
||||
* @brief Receives the data from the pipe.
|
||||
*
|
||||
* This function requests to receive the transfer from the specified pipe.
|
||||
*
|
||||
* @param[in] hostHandle The host handle.
|
||||
* @param[in] pipeHandle The receiving pipe handle.
|
||||
* @param[in] transfer The transfer information.
|
||||
*
|
||||
* @retval kStatus_USB_Success Receive successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The hostHandle, pipeHandle or transfer is a NULL pointer.
|
||||
* @retval kStatus_USB_LackSwapBuffer There is no swap buffer for KHCI.
|
||||
* @retval kStatus_USB_Error There is no idle QTD/ITD/SITD for EHCI.
|
||||
*/
|
||||
extern usb_status_t USB_HostRecv(usb_host_handle hostHandle,
|
||||
usb_host_pipe_handle pipeHandle,
|
||||
usb_host_transfer_t *transfer);
|
||||
|
||||
/*!
|
||||
* @brief Cancel the pipe's transfers.
|
||||
*
|
||||
* This function cancels all pipe's transfers when the parameter transfer is NULL or cancels the transfers altogether.
|
||||
*
|
||||
* @param[in] hostHandle The host handle.
|
||||
* @param[in] pipeHandle The receiving pipe handle.
|
||||
* @param[in] transfer The transfer information.
|
||||
*
|
||||
* @retval kStatus_USB_Success Cancel successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The hostHandle or pipeHandle is a NULL pointer.
|
||||
*/
|
||||
extern usb_status_t USB_HostCancelTransfer(usb_host_handle hostHandle,
|
||||
usb_host_pipe_handle pipeHandle,
|
||||
usb_host_transfer_t *transfer);
|
||||
|
||||
/*!
|
||||
* @brief Allocates a transfer resource.
|
||||
*
|
||||
* This function allocates a transfer. This transfer is used to pass data information to a low level stack.
|
||||
*
|
||||
* @param[in] hostHandle The host handle.
|
||||
* @param[out] transfer Return the transfer.
|
||||
*
|
||||
* @retval kStatus_USB_Success Allocate successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The hostHandle or transfer is a NULL pointer.
|
||||
* @retval kStatus_USB_Error There is no idle transfer.
|
||||
*/
|
||||
extern usb_status_t USB_HostMallocTransfer(usb_host_handle hostHandle, usb_host_transfer_t **transfer);
|
||||
|
||||
/*!
|
||||
* @brief Frees a transfer resource.
|
||||
*
|
||||
* This function frees a transfer. This transfer is used to pass data information to a low level stack.
|
||||
*
|
||||
* @param[in] hostHandle The host handle.
|
||||
* @param[in] transfer Release the transfer.
|
||||
*
|
||||
* @retval kStatus_USB_Success Free successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The hostHandle or transfer is a NULL pointer.
|
||||
*/
|
||||
extern usb_status_t USB_HostFreeTransfer(usb_host_handle hostHandle, usb_host_transfer_t *transfer);
|
||||
|
||||
/*!
|
||||
* @brief Requests the USB standard request.
|
||||
*
|
||||
* This function sends the USB standard request packet.
|
||||
*
|
||||
* @param[in] deviceHandle The device handle for control transfer.
|
||||
* @param[in] usbRequest A USB standard request code. See the usb_spec.h.
|
||||
* @param[in] transfer The used transfer.
|
||||
* @param[in] param The parameter structure is different for different request, see
|
||||
* usb_host_framework.h.
|
||||
*
|
||||
* @retval kStatus_USB_Success Send successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The deviceHandle is a NULL pointer.
|
||||
* @retval kStatus_USB_LackSwapBuffer There is no swap buffer for KHCI.
|
||||
* @retval kStatus_USB_Error There is no idle QTD/ITD/SITD for EHCI,
|
||||
* Or, the request is not standard request.
|
||||
*/
|
||||
extern usb_status_t USB_HostRequestControl(usb_device_handle deviceHandle,
|
||||
uint8_t usbRequest,
|
||||
usb_host_transfer_t *transfer,
|
||||
void *param);
|
||||
|
||||
/*!
|
||||
* @brief Opens the interface.
|
||||
*
|
||||
* This function opens the interface. It is used to notify the host driver the interface is used by APP or class driver.
|
||||
*
|
||||
* @param[in] deviceHandle Removing device handle.
|
||||
* @param[in] interfaceHandle Opening interface handle.
|
||||
*
|
||||
* @retval kStatus_USB_Success Open successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The deviceHandle or interfaceHandle is a NULL pointer.
|
||||
*/
|
||||
extern usb_status_t USB_HostOpenDeviceInterface(usb_device_handle deviceHandle,
|
||||
usb_host_interface_handle interfaceHandle);
|
||||
|
||||
/*!
|
||||
* @brief Closes an interface.
|
||||
*
|
||||
* This function opens an interface. It is used to notify the host driver the interface is not used by APP or class
|
||||
* driver.
|
||||
*
|
||||
* @param[in] deviceHandle Removing device handle.
|
||||
* @param[in] interfaceHandle Opening interface handle.
|
||||
*
|
||||
* @retval kStatus_USB_Success Close successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The deviceHandle is a NULL pointer.
|
||||
*/
|
||||
extern usb_status_t USB_HostCloseDeviceInterface(usb_device_handle deviceHandle,
|
||||
usb_host_interface_handle interfaceHandle);
|
||||
|
||||
/*!
|
||||
* @brief Gets a host stack version function.
|
||||
*
|
||||
* The function is used to get the host stack version.
|
||||
*
|
||||
* @param[out] version The version structure pointer to keep the host stack version.
|
||||
*
|
||||
*/
|
||||
extern void USB_HostGetVersion(uint32_t *version);
|
||||
|
||||
#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U))
|
||||
/*!
|
||||
* @brief Send a bus or device suspend request.
|
||||
*
|
||||
* This function is used to send a bus or device suspend request.
|
||||
*
|
||||
* @param[in] hostHandle The host handle.
|
||||
* @param[in] deviceHandle The device handle.
|
||||
*
|
||||
* @retval kStatus_USB_Success Request successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The hostHandle is a NULL pointer. Or the controller handle is invalid.
|
||||
* @retval kStatus_USB_Error There is no idle transfer.
|
||||
* Or, the deviceHandle is invalid.
|
||||
* Or, the request is invalid.
|
||||
*/
|
||||
extern usb_status_t USB_HostSuspendDeviceResquest(usb_host_handle hostHandle, usb_device_handle deviceHandle);
|
||||
|
||||
/*!
|
||||
* @brief Send a bus or device resume request.
|
||||
*
|
||||
* This function is used to send a bus or device resume request.
|
||||
*
|
||||
* @param[in] hostHandle The host handle.
|
||||
* @param[in] deviceHandle The device handle.
|
||||
*
|
||||
* @retval kStatus_USB_Success Request successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The hostHandle is a NULL pointer. Or the controller handle is invalid.
|
||||
* @retval kStatus_USB_Error There is no idle transfer.
|
||||
* Or, the deviceHandle is invalid.
|
||||
* Or, the request is invalid.
|
||||
*/
|
||||
extern usb_status_t USB_HostResumeDeviceResquest(usb_host_handle hostHandle, usb_device_handle deviceHandle);
|
||||
#if ((defined(USB_HOST_CONFIG_LPM_L1)) && (USB_HOST_CONFIG_LPM_L1 > 0U))
|
||||
/*!
|
||||
* @brief Send a bus or device suspend request.
|
||||
*
|
||||
* This function is used to send a bus or device suspend request.
|
||||
*
|
||||
* @param[in] hostHandle The host handle.
|
||||
* @param[in] deviceHandle The device handle.
|
||||
*@param[in] sleeptype Bus suspend or single device suspend.
|
||||
*
|
||||
* @retval kStatus_USB_Success Request successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The hostHandle is a NULL pointer. Or the controller handle is invalid.
|
||||
* @retval kStatus_USB_Error There is no idle transfer.
|
||||
* Or, the deviceHandle is invalid.
|
||||
* Or, the request is invalid.
|
||||
*/
|
||||
extern usb_status_t USB_HostL1SleepDeviceResquest(usb_host_handle hostHandle,
|
||||
usb_device_handle deviceHandle,
|
||||
uint8_t sleeptype);
|
||||
|
||||
/*!
|
||||
* @brief Send a bus or device resume request.
|
||||
*
|
||||
* This function is used to send a bus or device resume request.
|
||||
*
|
||||
* @param[in] hostHandle The host handle.
|
||||
* @param[in] deviceHandle The device handle.
|
||||
* *@param[in] sleeptype Bus suspend or single device suspend.
|
||||
*
|
||||
* @retval kStatus_USB_Success Request successfully.
|
||||
* @retval kStatus_USB_InvalidHandle The hostHandle is a NULL pointer. Or the controller handle is invalid.
|
||||
* @retval kStatus_USB_Error There is no idle transfer.
|
||||
* Or, the deviceHandle is invalid.
|
||||
* Or, the request is invalid.
|
||||
*/
|
||||
extern usb_status_t USB_HostL1ResumeDeviceResquest(usb_host_handle hostHandle,
|
||||
usb_device_handle deviceHandle,
|
||||
uint8_t sleepType);
|
||||
/*!
|
||||
* @brief Update the lpm param.
|
||||
*
|
||||
* The function is used to configure the lpm token.
|
||||
*
|
||||
* @param[in] hostHandle The host handle.
|
||||
* @param[in] lpmParam HIRD value and whether enable remotewakeup.
|
||||
*
|
||||
*/
|
||||
extern usb_status_t USB_HostL1SleepDeviceResquestConfig(usb_host_handle hostHandle, uint8_t *lpmParam);
|
||||
#endif
|
||||
/*!
|
||||
* @brief Update the hardware tick.
|
||||
*
|
||||
* The function is used to update the hardware tick.
|
||||
*
|
||||
* @param[in] hostHandle The host handle.
|
||||
* @param[in] tick Current hardware tick(uint is ms).
|
||||
*
|
||||
*/
|
||||
extern usb_status_t USB_HostUpdateHwTick(usb_host_handle hostHandle, uint64_t tick);
|
||||
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _USB_HOST_H_ */
|
||||
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Reference in New Issue