diff --git a/Ubiquitous/XiZi_AIoT/services/app/Makefile b/Ubiquitous/XiZi_AIoT/services/app/Makefile index 5a2fe86c8..ba504d2ca 100644 --- a/Ubiquitous/XiZi_AIoT/services/app/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/app/Makefile @@ -64,7 +64,7 @@ eth_driver: enet_drv.o enet_test.o board_network.o enet_iomux_config.o imx6dq_gp @${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs} @${objdump} -S $@ > $@.asm -ethernet: test_gmac.o gmac.o gmac_3568.o hal_base.o hal_bsp.o hal_pinctrl_v2.o hal_cru.o hal_cache.o hal_gpio.o hal_timer.o hal_cru_rk3568.o libserial.o printf.o libmem.o usyscall.o arch_usyscall.o session.o libipc.o +ethernet: test_gmac.o hal_gmac.o hal_gmac_3568.o hal_base.o hal_bsp.o hal_pinctrl_v2.o hal_cru.o hal_cache.o hal_gpio.o hal_timer.o hal_cru_rk3568.o system_rk3568.o hal_debug.o libserial.o printf.o libmem.o usyscall.o arch_usyscall.o session.o libipc.o @${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs} @${objdump} -S $@ > $@.asm diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/Makefile index 272d0afd7..2c285fffa 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/Makefile @@ -1,4 +1,4 @@ -SRC_DIR := ethernet +SRC_DIR := hal include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_bsp.c b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_bsp.c deleted file mode 100644 index 75cd0ae6a..000000000 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_bsp.c +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ - -#include "hal_bsp.h" -#include "rk3568.h" -#include "soc.h" -#include "hal_gmac.h" - -const struct HAL_GMAC_DEV g_gmac0Dev = -{ - .pReg = GMAC0, - .clkID = CLK_MAC0_2TOP, - .clkGateID = CLK_MAC0_2TOP_GATE, - .pclkID = PCLK_PHP, - .pclkGateID = PCLK_GMAC0_GATE, - .irqNum = GMAC0_IRQn, -}; - -const struct HAL_GMAC_DEV g_gmac1Dev = -{ - .pReg = GMAC1, - .clkID = CLK_MAC1_2TOP, - .clkGateID = CLK_MAC1_2TOP_GATE, - .pclkID = PCLK_USB, - .pclkGateID = PCLK_GMAC1_GATE, - .irqNum = GMAC1_IRQn, -}; - -void BSP_Init(void) -{ -} diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/Makefile similarity index 81% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/Makefile rename to Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/Makefile index b7608086b..8a19c2829 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/Makefile @@ -9,7 +9,7 @@ ld = ${toolchain}g++ objdump = ${toolchain}objdump user_ldflags = -N -Ttext 0 -cflags = -std=c11 -g \ +cflags = -std=c11 -g -march=armv7-a -mtune=cortex-a9 \ -Wno-unused -Wno-format -fno-common -ffreestanding -fno-builtin -static \ -Wno-unaligned-access -fdce -Wall -Werror -Wno-uninitialized -Wno-strict-aliasing -fdiagnostics-show-option \ -mapcs -marm -mfpu=neon -ftree-vectorize -fno-math-errno -funsafe-math-optimizations -fno-signed-zeros -mfloat-abi=softfp \ @@ -29,7 +29,21 @@ INC_DIR = -I$(KERNEL_ROOT)/services/app \ -I$(KERNEL_ROOT)/services/lib/memory -all: gmac.o gmac_3568.o test_gmac.o hal_base.o hal_bsp.o hal_pinctrl_v2.o hal_cru.o hal_cache.o hal_gpio.o hal_timer.o hal_cru_rk3568.o +objs = hal_gmac.o \ + hal_gmac_3568.o \ + test_gmac.o \ + hal_base.o \ + hal_bsp.o \ + hal_pinctrl_v2.o \ + hal_cru.o \ + hal_cache.o \ + hal_gpio.o \ + hal_timer.o \ + hal_cru_rk3568.o \ + hal_debug.o \ + system_rk3568.o + +all: ${objs} @mv $^ $(KERNEL_ROOT)/services/app %.o: %.c diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_base.c b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_base.c similarity index 65% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_base.c rename to Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_base.c index a7064fae9..6edf236dc 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_base.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_base.c @@ -4,9 +4,7 @@ */ #include "hal_base.h" -#include "hal_def.h" -#include "hal_bsp.h" -#include "hal_timer.h" + /** @addtogroup RK_HAL_Driver * @{ */ @@ -51,20 +49,7 @@ /********************* Private MACRO Definition ******************************/ #define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ -#define SYSTEM_CLOCK 816000000U -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} /********************* Private Structure Definition **************************/ /********************* Private Variable Definition ***************************/ @@ -73,10 +58,25 @@ static __IO uint32_t uwTick; static eHAL_tickFreq uwTickFreq = HAL_TICK_FREQ_DEFAULT; /********************* Private Function Definition ***************************/ - +#if defined(__CORTEX_A) || defined(__CORTEX_M) +#if __CORTEX_M == 0U || !defined(__GNUC__) static void CPUCycleLoop(uint32_t cycles) { - __asm volatile ( + uint32_t count; + + if (cycles < 100U) { + return; + } + + count = cycles / 3; + while (count-- > 0) { + __asm volatile ("nop"); + } +} +#else +static void CPUCycleLoop(uint32_t cycles) +{ + __ASM volatile ( "mov r0, %0\n\t" "adds r0, r0, #2\n\t" // 1 2 Round to the nearest multiple of 4. "lsrs r0, r0, #2\n\t" // 1 2 Divide by 4 and set flags. @@ -91,8 +91,32 @@ static void CPUCycleLoop(uint32_t cycles) : : "r" (cycles) ); } +#endif +#elif defined(__RISC_V) +static void CPUCycleLoop(uint32_t cycles) +{ + asm volatile ( + "mv a0, %0\n\t" + "addi a0, a0, 2\n\t" // 1 2 Round to the nearest multiple of 4. + "li a1, 4\n\t" + "div a0, a0, a1\n\t" // 1 2 Divide by 4 and set flags. + "li a1, 2\n\t" + "bnez a0, 1f\n\t" // 2 2 Skip if 0. + "j 2f\n\t" + ".align 6\n\t" + "1:\n\t" + "addi a0, a0, 1\n\t" // 1 2 Increment the counter. + "sub a0, a0, a1\n\t" // 1 2 Decrement the counter by 2. + "bnez a0, 1b\n\t" // (1)2 2 2 CPU cycles (if branch is taken). + "nop\n\t" // 1 2 Loop alignment padding. + "2:" + : : "r" (cycles) + ); +} +#endif -static inline HAL_Status TimerDelayUs(uint32_t us) +#if defined(SYS_TIMER) && defined(HAL_TIMER_MODULE_ENABLED) +__STATIC_FORCEINLINE HAL_Status TimerDelayUs(uint32_t us) { uint64_t count, from, now, pass; @@ -106,7 +130,7 @@ static inline HAL_Status TimerDelayUs(uint32_t us) return HAL_OK; } - +#endif /** @} */ /********************* Public Function Definition ***************************/ @@ -121,6 +145,28 @@ static inline HAL_Status TimerDelayUs(uint32_t us) * @brief Init HAL driver basic code. * @return HAL_OK. */ +HAL_Status HAL_Init(void) +{ +#ifdef __CORTEX_M +#ifdef HAL_NVIC_MODULE_ENABLED + /* Set Interrupt Group Priority */ + HAL_NVIC_Init(); + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_DEFAULT); +#endif +#endif + +#if defined(SYS_TIMER) && defined(HAL_TIMER_MODULE_ENABLED) + HAL_TIMER_SysTimerInit(SYS_TIMER); +#endif + +#ifdef HAL_PINCTRL_MODULE_ENABLED + HAL_PINCTRL_Init(); +#endif + + return HAL_OK; +} /** * @brief HAL system update with new core clock and systick clock source. @@ -149,7 +195,16 @@ HAL_Status HAL_SystemCoreClockUpdate(uint32_t hz, eHAL_systickClkSource clkSourc return ret; } +/** + * @brief HAL deinit. + * @return HAL_Status: HAL_OK. + */ +HAL_Status HAL_DeInit(void) +{ + /* TO-DO */ + return HAL_OK; +} /** @} */ @@ -175,7 +230,7 @@ HAL_Status HAL_IncTick(void) */ uint32_t HAL_GetTick(void) { - +#if defined(SYS_TIMER) && defined(HAL_TIMER_MODULE_ENABLED) uint64_t tick = HAL_TIMER_GetCount(SYS_TIMER); uint32_t base = PLL_INPUT_OSC_RATE / 1000; @@ -184,8 +239,10 @@ uint32_t HAL_GetTick(void) } return (uint32_t)HAL_DivU64(tick, base); +#else - + return uwTick; +#endif } /** @@ -195,15 +252,17 @@ uint32_t HAL_GetTick(void) */ uint64_t HAL_GetSysTimerCount(void) { - +#if defined(SYS_TIMER) && defined(HAL_TIMER_MODULE_ENABLED) uint64_t count = HAL_TIMER_GetCount(SYS_TIMER); if (count >> 62) { count = ~count; } return count; +#else - + return 0LLU; +#endif } /** @@ -212,7 +271,7 @@ uint64_t HAL_GetSysTimerCount(void) */ HAL_Status HAL_SetTickFreq(eHAL_tickFreq freq) { - // HAL_ASSERT(IS_TICKFREQ(freq)); + HAL_ASSERT(IS_TICKFREQ(freq)); uwTickFreq = freq; @@ -237,7 +296,7 @@ eHAL_tickFreq HAL_GetTickFreq(void) * certain period of time to continuously query HW status, use HAL_GetTick * to do timeout, that will be more accurate. */ -__attribute__((weak)) HAL_Status HAL_DelayMs(uint32_t ms) +__WEAK HAL_Status HAL_DelayMs(uint32_t ms) { for (uint32_t i = 0; i < ms; i++) { HAL_DelayUs(1000); @@ -290,6 +349,77 @@ HAL_Status HAL_CPUDelayUs(uint32_t us) return HAL_OK; } +#if defined(HAL_CPU_USAGE_ENABLED) +static uint64_t g_last_enter_idle_time = 0; /* Last time current CPU entered the idle state. */ +static uint64_t g_total_idle_time = 0; /* Total time for current CPU to enter idle state. */ +static uint64_t g_last_elapsed_time = 0; /* Last elapsed time for current CPU. */ + +/** + * @brief Get current CPU usage. + * @return 0-100 + * @attention The cpu usage function depends on HAL_CPUEnterIdle function. + */ +uint32_t HAL_GetCPUUsage(void) +{ + uint64_t elapsed_time, active_time, current_time; + uint32_t usage; + + current_time = HAL_GetSysTimerCount(); + elapsed_time = current_time - g_last_elapsed_time; + + /* Prevent the risk of dividing by 0 caused by repeated calls for a short time. */ + if (!elapsed_time) { + return 0; + } + + HAL_ASSERT(elapsed_time > g_total_idle_time); + active_time = elapsed_time - g_total_idle_time; + usage = (active_time * 100) / elapsed_time; + g_total_idle_time = 0; + g_last_elapsed_time = current_time; + + return usage; +} +#endif + +/** + * @brief CPU enter idle. + */ +void HAL_CPU_EnterIdle(void) +{ +#if defined(HAL_CPU_USAGE_ENABLED) + uint64_t idle_time; + + __disable_irq(); + g_last_enter_idle_time = HAL_GetSysTimerCount(); +#endif + + // __asm__ volatile ("wfi"); + +#if defined(HAL_CPU_USAGE_ENABLED) + idle_time = HAL_GetSysTimerCount() - g_last_enter_idle_time; + g_total_idle_time += idle_time; + __enable_irq(); +#endif +} + +/** @} */ + +/** @} */ + +/** @} */ +/********************* Public Function Definition ***************************/ +/** @defgroup HAL_BASE_EX_Exported_Functions_Group5 Other Functions + * @{ + */ + +/** + * @brief uint64_t numerator / uint32_t denominator with remainder + * @param numerator + * @param denominator + * @param pRemainder [out] pointer to unsigned 32bit remainder + * @return uint64_t result. sets *pRemainder if pRemainder is not null + */ uint64_t HAL_DivU64Rem(uint64_t numerator, uint32_t denominator, uint32_t *pRemainder) { uint64_t remainder = numerator; @@ -325,9 +455,3 @@ uint64_t HAL_DivU64Rem(uint64_t numerator, uint32_t denominator, uint32_t *pRema return result; } - -/** @} */ - -/** @} */ - -/** @} */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_bsp.c b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_bsp.c new file mode 100644 index 000000000..c985ca48f --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_bsp.c @@ -0,0 +1,398 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_bsp.h" + +#ifdef HAL_PL330_MODULE_ENABLED +struct HAL_PL330_DEV g_pl330Dev0 = +{ + .pReg = DMA0, + .peripReqType = BURST, + .irq[0] = DMAC0_IRQn, + .irq[1] = DMAC0_ABORT_IRQn, + .pd = 0, +}; + +struct HAL_PL330_DEV g_pl330Dev1 = +{ + .pReg = DMA1, + .peripReqType = BURST, + .irq[0] = DMAC1_IRQn, + .irq[1] = DMAC1_ABORT_IRQn, + .pd = 0, +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +const struct HAL_SPI_DEV g_spi0Dev = { + .base = SPI0_BASE, + .clkId = CLK_SPI0, + .clkGateID = CLK_SPI0_GATE, + .pclkGateID = PCLK_SPI0_GATE, + .irqNum = SPI0_IRQn, + .isSlave = false, + .txDma = { + .channel = DMA_REQ_SPI0_TX, + .direction = DMA_MEM_TO_DEV, + .addr = SPI0_BASE + 0x400, + .dmac = DMA0, + }, + .rxDma = { + .channel = DMA_REQ_SPI0_RX, + .direction = DMA_DEV_TO_MEM, + .addr = SPI0_BASE + 0x800, + .dmac = DMA0, + }, +}; + +const struct HAL_SPI_DEV g_spi1Dev = { + .base = SPI1_BASE, + .clkId = CLK_SPI1, + .clkGateID = CLK_SPI1_GATE, + .pclkGateID = PCLK_SPI1_GATE, + .irqNum = SPI1_IRQn, + .isSlave = false, + .txDma = { + .channel = DMA_REQ_SPI1_TX, + .direction = DMA_MEM_TO_DEV, + .addr = SPI1_BASE + 0x400, + .dmac = DMA0, + }, + .rxDma = { + .channel = DMA_REQ_SPI1_RX, + .direction = DMA_DEV_TO_MEM, + .addr = SPI1_BASE + 0x800, + .dmac = DMA0, + }, +}; + +const struct HAL_SPI_DEV g_spi2Dev = { + .base = SPI2_BASE, + .clkId = CLK_SPI2, + .clkGateID = CLK_SPI2_GATE, + .pclkGateID = PCLK_SPI2_GATE, + .irqNum = SPI2_IRQn, + .isSlave = false, + .txDma = { + .channel = DMA_REQ_SPI2_TX, + .direction = DMA_MEM_TO_DEV, + .addr = SPI2_BASE + 0x400, + .dmac = DMA0, + }, + .rxDma = { + .channel = DMA_REQ_SPI2_RX, + .direction = DMA_DEV_TO_MEM, + .addr = SPI2_BASE + 0x800, + .dmac = DMA0, + }, +}; + +const struct HAL_SPI_DEV g_spi3Dev = { + .base = SPI3_BASE, + .clkId = CLK_SPI3, + .clkGateID = CLK_SPI3_GATE, + .pclkGateID = PCLK_SPI3_GATE, + .irqNum = SPI3_IRQn, + .isSlave = false, + .txDma = { + .channel = DMA_REQ_SPI3_TX, + .direction = DMA_MEM_TO_DEV, + .addr = SPI3_BASE + 0x400, + .dmac = DMA0, + }, + .rxDma = { + .channel = DMA_REQ_SPI3_RX, + .direction = DMA_DEV_TO_MEM, + .addr = SPI3_BASE + 0x800, + .dmac = DMA0, + }, +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +const struct HAL_UART_DEV g_uart0Dev = +{ + .pReg = UART0, + .sclkID = CLK_UART0, + .irqNum = UART0_IRQn, + .isAutoFlow = false, +}; + +const struct HAL_UART_DEV g_uart1Dev = +{ + .pReg = UART1, + .sclkID = CLK_UART1, + .sclkGateID = SCLK_UART1_GATE, + .pclkGateID = PCLK_UART1_GATE, + .irqNum = UART1_IRQn, + .isAutoFlow = false, +}; + +const struct HAL_UART_DEV g_uart2Dev = +{ + .pReg = UART2, + .sclkID = CLK_UART2, + .sclkGateID = SCLK_UART2_GATE, + .pclkGateID = PCLK_UART2_GATE, + .irqNum = UART2_IRQn, + .isAutoFlow = false, +}; + +const struct HAL_UART_DEV g_uart3Dev = +{ + .pReg = UART3, + .sclkID = CLK_UART3, + .sclkGateID = SCLK_UART3_GATE, + .pclkGateID = PCLK_UART3_GATE, + .irqNum = UART3_IRQn, + .isAutoFlow = false, +}; + +const struct HAL_UART_DEV g_uart4Dev = +{ + .pReg = UART4, + .sclkID = CLK_UART4, + .sclkGateID = SCLK_UART4_GATE, + .pclkGateID = PCLK_UART4_GATE, + .irqNum = UART4_IRQn, + .isAutoFlow = false, +}; + +const struct HAL_UART_DEV g_uart5Dev = +{ + .pReg = UART5, + .sclkID = CLK_UART5, + .sclkGateID = SCLK_UART5_GATE, + .pclkGateID = PCLK_UART5_GATE, + .irqNum = UART5_IRQn, + .isAutoFlow = false, +}; + +const struct HAL_UART_DEV g_uart6Dev = +{ + .pReg = UART6, + .sclkID = CLK_UART6, + .sclkGateID = SCLK_UART6_GATE, + .pclkGateID = PCLK_UART6_GATE, + .irqNum = UART6_IRQn, + .isAutoFlow = false, +}; + +const struct HAL_UART_DEV g_uart7Dev = +{ + .pReg = UART7, + .sclkID = CLK_UART7, + .sclkGateID = SCLK_UART7_GATE, + .pclkGateID = PCLK_UART7_GATE, + .irqNum = UART7_IRQn, + .isAutoFlow = false, +}; + +const struct HAL_UART_DEV g_uart8Dev = +{ + .pReg = UART8, + .sclkID = CLK_UART8, + .sclkGateID = SCLK_UART8_GATE, + .pclkGateID = PCLK_UART8_GATE, + .irqNum = UART8_IRQn, + .isAutoFlow = false, +}; + +const struct HAL_UART_DEV g_uart9Dev = +{ + .pReg = UART9, + .sclkID = CLK_UART9, + .sclkGateID = SCLK_UART9_GATE, + .pclkGateID = PCLK_UART9_GATE, + .irqNum = UART9_IRQn, + .isAutoFlow = false, +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +const struct HAL_I2C_DEV g_i2c0Dev = +{ + .pReg = I2C0, + .irqNum = I2C0_IRQn, + .clkID = CLK_I2C, + .clkGateID = CLK_I2C0_GATE, + .pclkGateID = PCLK_I2C0_GATE, + .runtimeID = PM_RUNTIME_ID_I2C0, +}; + +const struct HAL_I2C_DEV g_i2c1Dev = +{ + .pReg = I2C1, + .irqNum = I2C1_IRQn, + .clkID = CLK_I2C, + .clkGateID = CLK_I2C1_GATE, + .pclkGateID = PCLK_I2C1_GATE, + .runtimeID = PM_RUNTIME_ID_I2C1, +}; + +const struct HAL_I2C_DEV g_i2c2Dev = +{ + .pReg = I2C2, + .irqNum = I2C2_IRQn, + .clkID = CLK_I2C, + .clkGateID = CLK_I2C2_GATE, + .pclkGateID = PCLK_I2C2_GATE, + .runtimeID = PM_RUNTIME_ID_I2C2, +}; + +const struct HAL_I2C_DEV g_i2c3Dev = +{ + .pReg = I2C3, + .irqNum = I2C3_IRQn, + .clkID = CLK_I2C, + .clkGateID = CLK_I2C3_GATE, + .pclkGateID = PCLK_I2C3_GATE, + .runtimeID = PM_RUNTIME_ID_I2C3, +}; + +const struct HAL_I2C_DEV g_i2c4Dev = +{ + .pReg = I2C4, + .irqNum = I2C4_IRQn, + .clkID = CLK_I2C, + .clkGateID = CLK_I2C4_GATE, + .pclkGateID = PCLK_I2C4_GATE, + .runtimeID = PM_RUNTIME_ID_I2C4, +}; + +const struct HAL_I2C_DEV g_i2c5Dev = +{ + .pReg = I2C5, + .irqNum = I2C5_IRQn, + .clkID = CLK_I2C, + .clkGateID = CLK_I2C5_GATE, + .pclkGateID = PCLK_I2C5_GATE, + .runtimeID = PM_RUNTIME_ID_I2C5, +}; +#endif + +#ifdef HAL_FSPI_MODULE_ENABLED +struct HAL_FSPI_HOST g_fspi0Dev = +{ + .instance = FSPI, + .sclkGate = SCLK_SFC_GATE, + .hclkGate = HCLK_SFC_GATE, + .xipClkGate = 0, + .sclkID = 0, + .irqNum = FSPI0_IRQn, + .xipMemCode = 0, + .xipMemData = 0, + .xmmcDev[0] = + { + .type = 0, + }, +}; +#endif + +#ifdef HAL_CANFD_MODULE_ENABLED +const struct HAL_CANFD_DEV g_can0Dev = +{ + .pReg = CAN0, + .sclkID = CLK_CAN0, + .sclkGateID = CLK_CAN0_GATE, + .pclkGateID = PCLK_CAN0_GATE, + .irqNum = CAN0_IRQn, +}; + +const struct HAL_CANFD_DEV g_can1Dev = +{ + .pReg = CAN1, + .sclkID = CLK_CAN1, + .sclkGateID = CLK_CAN1_GATE, + .pclkGateID = PCLK_CAN1_GATE, + .irqNum = CAN1_IRQn, +}; + +const struct HAL_CANFD_DEV g_can2Dev = +{ + .pReg = CAN2, + .sclkID = CLK_CAN2, + .sclkGateID = CLK_CAN2_GATE, + .pclkGateID = PCLK_CAN2_GATE, + .irqNum = CAN2_IRQn, +}; +#endif + +#ifdef HAL_GMAC_MODULE_ENABLED +const struct HAL_GMAC_DEV g_gmac0Dev = +{ + .pReg = GMAC0, + .clkID = CLK_MAC0_2TOP, + .clkGateID = CLK_MAC0_2TOP_GATE, + .pclkID = PCLK_PHP, + .pclkGateID = PCLK_GMAC0_GATE, + .irqNum = GMAC0_IRQn, +}; + +const struct HAL_GMAC_DEV g_gmac1Dev = +{ + .pReg = GMAC1, + .clkID = CLK_MAC1_2TOP, + .clkGateID = CLK_MAC1_2TOP_GATE, + .pclkID = PCLK_USB, + .pclkGateID = PCLK_GMAC1_GATE, + .irqNum = GMAC1_IRQn, +}; +#endif + +#ifdef HAL_PCIE_MODULE_ENABLED +struct HAL_PCIE_DEV g_pcieDev = +{ + .apbBase = PCIE3X2_APB_BASE, + .dbiBase = PCIE3X2_DBI_BASE, + .cfgBase = 0xF0000000, + .lanes = 2, + .gen = 3, + .firstBusNo = 0x20, + .legacyIrqNum = PCIE30x2_LEGACY_IRQn, +}; +#endif + +#ifdef HAL_PWM_MODULE_ENABLED +const struct HAL_PWM_DEV g_pwm0Dev = +{ + .pReg = PWM0, + .clkID = 0, + .clkGateID = CLK_PWM0_GATE, + .pclkGateID = PCLK_PWM0_GATE, + .irqNum = PWM_PMU_IRQn, +}; + +const struct HAL_PWM_DEV g_pwm1Dev = +{ + .pReg = PWM1, + .clkID = CLK_PWM1, + .clkGateID = CLK_PWM1_GATE, + .pclkGateID = PCLK_PWM1_GATE, + .irqNum = PWM1_IRQn, +}; + +const struct HAL_PWM_DEV g_pwm2Dev = +{ + .pReg = PWM2, + .clkID = CLK_PWM2, + .clkGateID = CLK_PWM2_GATE, + .pclkGateID = PCLK_PWM2_GATE, + .irqNum = PWM2_IRQn, +}; + +const struct HAL_PWM_DEV g_pwm3Dev = +{ + .pReg = PWM3, + .clkID = CLK_PWM3, + .clkGateID = CLK_PWM3_GATE, + .pclkGateID = PCLK_PWM3_GATE, + .irqNum = PWM3_IRQn, +}; +#endif + +void BSP_Init(void) +{ +} diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_cache.c b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_cache.c similarity index 98% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_cache.c rename to Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_cache.c index e874ce475..db171ec44 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_cache.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_cache.c @@ -12,7 +12,6 @@ */ #include "hal_base.h" #include "hal_cache.h" -#include "hal_def.h" /** @defgroup CACHE_Exported_Definition_Group1 Basic Definition * @{ @@ -30,7 +29,7 @@ /********************* Private Function Definition ***************************/ #if defined(__CORTEX_M) -static inline unsigned long HAL_SYS_EnterCriticalSection(void) +__STATIC_INLINE unsigned long HAL_SYS_EnterCriticalSection(void) { unsigned long flags; @@ -40,12 +39,12 @@ static inline unsigned long HAL_SYS_EnterCriticalSection(void) return flags; } -static inline void HAL_SYS_ExitCriticalSection(unsigned long flags) +__STATIC_INLINE void HAL_SYS_ExitCriticalSection(unsigned long flags) { __set_PRIMASK(flags); } #elif defined(__RISC_V) -static inline unsigned long HAL_SYS_EnterCriticalSection(void) +__STATIC_INLINE unsigned long HAL_SYS_EnterCriticalSection(void) { unsigned long flags; @@ -57,7 +56,7 @@ static inline unsigned long HAL_SYS_EnterCriticalSection(void) return flags; } -static inline void HAL_SYS_ExitCriticalSection(unsigned long flags) +__STATIC_INLINE void HAL_SYS_ExitCriticalSection(unsigned long flags) { __asm volatile ("csrw mstatus, %0" : @@ -65,12 +64,12 @@ static inline void HAL_SYS_ExitCriticalSection(unsigned long flags) : "memory"); } #else -static inline unsigned long HAL_SYS_EnterCriticalSection(void) +__STATIC_INLINE unsigned long HAL_SYS_EnterCriticalSection(void) { return 0; } -static inline void HAL_SYS_ExitCriticalSection(unsigned long flags) +__STATIC_INLINE void HAL_SYS_ExitCriticalSection(unsigned long flags) { } #endif @@ -126,7 +125,7 @@ uint32_t HAL_CpuAddrToDmaAddr(uint32_t cpuAddr) * @brief check mpu is enable. * @return HAL_ENABLE if mpu enable. */ -static inline HAL_FuncStatus HAL_MPU_IsEnable(void) +__STATIC_INLINE HAL_FuncStatus HAL_MPU_IsEnable(void) { HAL_FuncStatus ret = HAL_DISABLE; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_cru.c b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_cru.c similarity index 73% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_cru.c rename to Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_cru.c index 6c623ecd3..7e835eee8 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_cru.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_cru.c @@ -4,8 +4,8 @@ */ #include "hal_base.h" -#include "hal_def.h" -#include "hal_cru.h" + +#ifdef HAL_CRU_MODULE_ENABLED /** @addtogroup RK_HAL_Driver * @{ @@ -42,7 +42,40 @@ * @{ */ /********************* Private MACRO Definition ******************************/ +#if defined(SOC_RV1108) +#define PWRDOWN_SHIFT 0 +#define PWRDOWN_MASK 1 << PWRDOWN_SHIFT +#define PLL_POSTDIV1_SHIFT 8 +#define PLL_POSTDIV1_MASK 0x7 << PLL_POSTDIV1_SHIFT +#define PLL_FBDIV_SHIFT 0 +#define PLL_FBDIV_MASK 0xfff << PLL_FBDIV_SHIFT +#define PLL_POSTDIV2_SHIFT 12 +#define PLL_POSTDIV2_MASK 0x7 << PLL_POSTDIV2_SHIFT +#define PLL_REFDIV_SHIFT 0 +#define PLL_REFDIV_MASK 0x3f << PLL_REFDIV_SHIFT +#define PLL_DSMPD_SHIFT 3 +#define PLL_DSMPD_MASK 1 << PLL_DSMPD_SHIFT +#define PLL_FRAC_SHIFT 0 +#define PLL_FRAC_MASK 0xffffff << PLL_FRAC_SHIFT +#elif defined(SOC_RK3588) +#define PLLCON0_M_SHIFT 0 +#define PLLCON0_M_MASK 0x3ff << PLLCON0_M_SHIFT +#define PLLCON1_P_SHIFT 0 +#define PLLCON1_P_MASK 0x3f << PLLCON1_P_SHIFT +#define PLLCON1_S_SHIFT 6 +#define PLLCON1_S_MASK 0x7 << PLLCON1_S_SHIFT +#define PLLCON2_K_SHIFT 0 +#define PLLCON2_K_MASK 0xffff << PLLCON2_K_SHIFT +#define PLLCON1_PWRDOWN BIT(13) +#define PLLCON6_LOCK_STATUS BIT(15) +#define BYPASS_SHIFT 15 +#define BYPASS_MASK (1 << BYPASS_SHIFT) + +#define PWRDOWN_SHIFT 13 +#define PWRDOWN_MASK (1 << PWRDOWN_SHIFT) + +#else #define PWRDOWN_SHIFT 13 #define PWRDOWN_MASK 1 << PWRDOWN_SHIFT #define PLL_POSTDIV1_SHIFT 12 @@ -57,7 +90,7 @@ #define PLL_DSMPD_MASK 1 << PLL_DSMPD_SHIFT #define PLL_FRAC_SHIFT 0 #define PLL_FRAC_MASK 0xffffff << PLL_FRAC_SHIFT - +#endif #define MIN_FOUTVCO_FREQ (800 * MHZ) #define MAX_FOUTVCO_FREQ (2000 * MHZ) @@ -87,7 +120,7 @@ /********************* Private Structure Definition **************************/ static struct PLL_CONFIG g_rockchipAutoTable; -__attribute__((weak)) const struct HAL_CRU_DEV g_cruDev; +__WEAK const struct HAL_CRU_DEV g_cruDev; /********************* Private Variable Definition ***************************/ /********************* Private Function Definition ***************************/ @@ -224,8 +257,81 @@ int HAL_CRU_RoundFreqGetMux2(uint32_t freq, uint32_t pFreq0, uint32_t pFreq1, ui return HAL_CRU_RoundFreqGetMux4(freq, pFreq0, pFreq1, 0, 0, pFreqOut); } +#if defined(SOC_RK3588) +/** + * @brief Get pll parameter by auto. + * @param finHz: pll intput freq + * @param foutHz: pll output freq + * @return struct PLL_CONFIG. + * How to calculate the PLL: + * FFVCO = ((m + k / 65536) * FFIN) / p + * FFOUT = ((m + k / 65536) * FFIN) / (p * 2^s) + */ +static const struct PLL_CONFIG *CRU_PllSetByAuto(uint32_t finHz, uint32_t foutHz) +{ + struct PLL_CONFIG *rateTable = &g_rockchipAutoTable; + uint64_t fvcoMin = 2250ULL * MHZ, fvcoMax = 4500ULL * MHZ; + uint64_t foutMin = 37ULL * MHZ, foutMax = 4500ULL * MHZ; + uint64_t fvco, fref, fout, ffrac; + uint32_t p, m, s; + if (finHz == 0 || foutHz == 0 || foutHz == finHz) { + return NULL; + } + if (foutHz > foutMax || foutHz < foutMin) { + return NULL; + } + + if (finHz / MHZ * MHZ == finHz && foutHz / MHZ * MHZ == foutHz) { + for (s = 0; s <= 6; s++) { + fvco = (uint64_t)foutHz << s; + if (fvco < fvcoMin || fvco > fvcoMax) { + continue; + } + + for (p = 2; p <= 4; p++) { + for (m = 64; m <= 1023; m++) { + if (fvco == m * finHz / p) { + rateTable->p = p; + rateTable->m = m; + rateTable->s = s; + rateTable->k = 0; + + return rateTable; + } + } + } + } + } else { + for (s = 0; s <= 6; s++) { + fvco = (uint64_t)foutHz << s; + if (fvco < fvcoMin || fvco > fvcoMax) { + continue; + } + + for (p = 1; p <= 4; p++) { + for (m = 64; m <= 1023; m++) { + if ((fvco >= m * finHz / p) && (fvco < (m + 1) * finHz / p)) { + rateTable->p = p; + rateTable->m = m; + rateTable->s = s; + fref = finHz / p; + ffrac = fvco - (m * fref); + fout = ffrac * 65536; + rateTable->k = fout / fref; + + return rateTable; + } + } + } + } + } + + return NULL; +} + +#else /** * @brief Rockchip pll clk set postdiv. * @param foutHz: output freq @@ -351,7 +457,7 @@ static const struct PLL_CONFIG *CRU_PllSetByAuto(uint32_t finHz, return rateTable; } - +#endif /** * @brief Get pll parameter by rateTable. @@ -390,7 +496,309 @@ static const struct PLL_CONFIG *CRU_PllGetSettings(struct PLL_SETUP *pSetup, * @{ */ +#if defined(SOC_RV1108) +/* + * Formulas also embedded within the fractional PLL Verilog model: + * If DSMPD = 1 (DSM is disabled, "integer mode") + * FOUTVCO = FREF / REFDIV * FBDIV + * FOUT = FOUTVCO / POSTDIV1 / POSTDIV2 + * If DSMPD = 0 (DSM is enabled, "fractional mode") + * FOUTVCO = (FREF / REFDIV) * (FBDIV + FRAC / (2^24)) + * FOUTPOSTDIV = FOUTVCO / (POSTDIV1*POSTDIV2) + * FOUT = FOUTVCO / POSTDIV1 / POSTDIV2 + */ +uint32_t HAL_CRU_GetPllFreq(struct PLL_SETUP *pSetup) +{ + uint32_t refDiv, fbDiv, postdDv1, postDiv2, frac, dsmpd; + uint32_t mode = 0, rate = PLL_INPUT_OSC_RATE; + mode = PLL_GET_PLLMODE(READ_REG(*(pSetup->modeOffset)), pSetup->modeShift, + pSetup->modeMask); + + switch (mode) { + case RK_PLL_MODE_SLOW: + rate = PLL_INPUT_OSC_RATE; + break; + case RK_PLL_MODE_NORMAL: + fbDiv = PLL_GET_FBDIV(READ_REG(*(pSetup->conOffset0))); + postdDv1 = PLL_GET_POSTDIV1(READ_REG(*(pSetup->conOffset1))); + postDiv2 = PLL_GET_POSTDIV2(READ_REG(*(pSetup->conOffset1))); + refDiv = PLL_GET_REFDIV(READ_REG(*(pSetup->conOffset1))); + dsmpd = PLL_GET_DSMPD(READ_REG(*(pSetup->conOffset3))); + frac = PLL_GET_FRAC(READ_REG(*(pSetup->conOffset2))); + rate = (rate / refDiv) * fbDiv; + if (dsmpd == 0) { + uint64_t fracRate = PLL_INPUT_OSC_RATE; + + fracRate *= frac; + fracRate = fracRate >> EXPONENT_OF_FRAC_PLL; + fracRate = fracRate / refDiv; + rate += fracRate; + } + rate = rate / (postdDv1 * postDiv2); + rate = CRU_PLL_ROUND_UP_TO_KHZ(rate); + break; + case RK_PLL_MODE_DEEP: + default: + rate = 32768; + break; + } + + return rate; +} + +/* + * Force PLL into slow mode + * Pll Power down + * Pll Config fbDiv, refDiv, postdDv1, postDiv2, dsmpd, frac + * Pll Power up + * Waiting for pll lock + * Force PLL into normal mode + */ +HAL_Status HAL_CRU_SetPllFreq(struct PLL_SETUP *pSetup, uint32_t rate) +{ + const struct PLL_CONFIG *pConfig; + int delay = 2400; + + if (rate == HAL_CRU_GetPllFreq(pSetup)) { + return HAL_OK; + } else if (rate < MIN_FOUT_FREQ) { + return HAL_INVAL; + } else if (rate > MAX_FOUT_FREQ) { + return HAL_INVAL; + } + + pConfig = CRU_PllGetSettings(pSetup, rate); + if (!pConfig) { + return HAL_ERROR; + } + + /* Force PLL into slow mode to ensure output stable clock */ + WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_SLOW << pSetup->modeShift); + + /* Pll Power down */ + WRITE_REG_MASK_WE(*(pSetup->conOffset3), PWRDOWN_MASK, 1 << PWRDOWN_SHIFT); + + /* Pll Config */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLL_POSTDIV2_MASK, pConfig->postDiv2 << PLL_POSTDIV2_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLL_REFDIV_MASK, pConfig->refDiv << PLL_REFDIV_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLL_POSTDIV1_MASK, pConfig->postDiv1 << PLL_POSTDIV1_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset0), PLL_FBDIV_MASK, pConfig->fbDiv << PLL_FBDIV_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset3), PLL_DSMPD_MASK, pConfig->dsmpd << PLL_DSMPD_SHIFT); + + if (pConfig->frac) { + WRITE_REG(*(pSetup->conOffset2), (READ_REG(*(pSetup->conOffset2)) & 0xff000000) | pConfig->frac); + } + + WRITE_REG_MASK_WE(*(pSetup->conOffset3), PWRDOWN_MASK, 0 << PWRDOWN_SHIFT); + + /* Waiting for pll lock */ + while (delay > 0) { + if (READ_REG(*(pSetup->conOffset2)) & (1 << pSetup->lockShift)) { + break; + } + HAL_CPUDelayUs(1000); + delay--; + } + if (delay == 0) { + return HAL_TIMEOUT; + } + + /* Force PLL into normal mode */ + WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_NORMAL << pSetup->modeShift); + + return HAL_OK; +} + +HAL_Status HAL_CRU_SetPllPowerUp(struct PLL_SETUP *pSetup) +{ + int delay = 2400; + + /* Pll Power up */ + WRITE_REG_MASK_WE(*(pSetup->conOffset3), PWRDOWN_MASK, 0 << PWRDOWN_SHIFT); + + /* Waiting for pll lock */ + while (delay > 0) { + if (READ_REG(*(pSetup->conOffset2)) & (1 << pSetup->lockShift)) { + break; + } + HAL_CPUDelayUs(1000); + delay--; + } + if (delay == 0) { + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup) +{ + /* Pll Power down */ + WRITE_REG_MASK_WE(*(pSetup->conOffset3), PWRDOWN_MASK, 1 << PWRDOWN_SHIFT); + + return HAL_OK; +} + +#elif defined(SOC_RK3588) +/* + * Formulas also embedded within the fractional PLL Verilog model: + * If K = 0 (DSM is disabled, "integer mode") + * FOUTVCO = FREF / P * M + * FOUT = FOUTVCO / 2^S + * If K > 0 (DSM is enabled, "fractional mode") + * FOUTVCO = (FREF / P) * (M + K / 65536) + * FOUT = FOUTVCO / 2^S + */ +uint32_t HAL_CRU_GetPllFreq(struct PLL_SETUP *pSetup) +{ + uint32_t m, p, s, k; + uint64_t rate = PLL_INPUT_OSC_RATE; + uint32_t mode = 0; + + if (pSetup->modeMask) { + mode = PLL_GET_PLLMODE(READ_REG(*(pSetup->modeOffset)), pSetup->modeShift, + pSetup->modeMask); + } else { + mode = RK_PLL_MODE_NORMAL; + } + + switch (mode) { + case RK_PLL_MODE_SLOW: + rate = PLL_INPUT_OSC_RATE; + break; + + case RK_PLL_MODE_NORMAL: + m = (READ_REG(*(pSetup->conOffset0)) & PLLCON0_M_MASK) >> PLLCON0_M_SHIFT; + p = (READ_REG(*(pSetup->conOffset1)) & PLLCON1_P_MASK) >> PLLCON1_P_SHIFT; + s = (READ_REG(*(pSetup->conOffset1)) & PLLCON1_S_MASK) >> PLLCON1_S_SHIFT; + k = (READ_REG(*(pSetup->conOffset2)) & PLLCON2_K_MASK) >> PLLCON2_K_SHIFT; + + rate *= m; + rate = rate / p; + if (k) { + /* fractional mode */ + uint64_t frac = PLL_INPUT_OSC_RATE / p; + + frac *= k; + frac = frac / 65536; + rate += frac; + } + rate = rate >> s; + break; + + case RK_PLL_MODE_DEEP: + default: + rate = 32768; + break; + } + + return rate; +} + +/* + * Force PLL into slow mode + * Pll Power down + * Pll Config M, P, S, K + * Pll Power up + * Waiting for pll lock + * Force PLL into normal mode + */ +HAL_Status HAL_CRU_SetPllFreq(struct PLL_SETUP *pSetup, uint32_t rate) +{ + const struct PLL_CONFIG *pConfig; + int delay = 24000000; + + if (rate == HAL_CRU_GetPllFreq(pSetup)) { + return HAL_OK; + } else if (rate < MIN_FOUT_FREQ) { + return HAL_INVAL; + } else if (rate > MAX_FOUT_FREQ) { + return HAL_INVAL; + } + + pConfig = CRU_PllGetSettings(pSetup, rate); + if (!pConfig) { + return HAL_ERROR; + } + + /* Force PLL into slow mode to ensure output stable clock */ + if (pSetup->modeMask) { + WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_SLOW << pSetup->modeShift); + } + + /* Pll Power down */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 1 << PWRDOWN_SHIFT); + + /* Pll Config */ + WRITE_REG_MASK_WE(*(pSetup->conOffset0), PLLCON0_M_MASK, pConfig->m << PLLCON0_M_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLLCON1_P_MASK, pConfig->p << PLLCON1_P_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLLCON1_S_MASK, pConfig->s << PLLCON1_S_SHIFT); + if (pConfig->k) { + WRITE_REG_MASK_WE(*(pSetup->conOffset2), PLLCON2_K_MASK, pConfig->k << PLLCON2_K_SHIFT); + } + + /* Pll Power up */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 0 << PWRDOWN_SHIFT); + + /* Waiting for pll lock */ + while (delay > 0) { + if (READ_REG(*(pSetup->conOffset6)) & (1 << pSetup->lockShift)) { + break; + } + delay--; + } + if (delay == 0) { + return HAL_TIMEOUT; + } + + /* Force PLL into normal mode */ + if (pSetup->modeMask) { + WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_NORMAL << pSetup->modeShift); + } + + /* + * PLL operates normally. + * + * ATF system suspend requires memory repair operation which would + * bypass the pll, let's ensure it's on normal mode. + */ + WRITE_REG_MASK_WE(*(pSetup->conOffset0), BYPASS_MASK, 0 << BYPASS_SHIFT); + + return HAL_OK; +} + +HAL_Status HAL_CRU_SetPllPowerUp(struct PLL_SETUP *pSetup) +{ + int delay = 2400; + + /* Pll Power up */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 0 << PWRDOWN_SHIFT); + + /* Waiting for pll lock */ + while (delay > 0) { + if (READ_REG(*(pSetup->conOffset6)) & (1 << pSetup->lockShift)) { + break; + } + HAL_CPUDelayUs(1000); + delay--; + } + if (delay == 0) { + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup) +{ + /* Pll Power down */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 1 << PWRDOWN_SHIFT); + + return HAL_OK; +} + +#else /* * Formulas also embedded within the fractional PLL Verilog model: * If DSMPD = 1 (DSM is disabled, "integer mode") @@ -546,7 +954,7 @@ HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup) return HAL_OK; } - +#endif #ifdef CRU_CLK_USE_CON_BANK static const struct HAL_CRU_DEV *CRU_GetInfo(void) @@ -1211,14 +1619,14 @@ HAL_Status HAL_CRU_ClkNp5BestDiv(eCLOCK_Name clockName, uint32_t rate, uint32_t return HAL_ERROR; } -__attribute__((weak)) HAL_Status HAL_CRU_VopDclkEnable(uint32_t gateId) +__WEAK HAL_Status HAL_CRU_VopDclkEnable(uint32_t gateId) { HAL_CRU_ClkEnable(gateId); return HAL_OK; } -__attribute__((weak)) HAL_Status HAL_CRU_VopDclkDisable(uint32_t gateId) +__WEAK HAL_Status HAL_CRU_VopDclkDisable(uint32_t gateId) { HAL_CRU_ClkDisable(gateId); @@ -1247,4 +1655,4 @@ HAL_Status HAL_CRU_SetGlbSrst(eCRU_GlbSrstType type) /** @} */ - +#endif /* HAL_CRU_MODULE_ENABLED */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_cru_rk3568.c b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_cru_rk3568.c similarity index 99% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_cru_rk3568.c rename to Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_cru_rk3568.c index 2c32cd09c..1653613a9 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_cru_rk3568.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_cru_rk3568.c @@ -4,8 +4,8 @@ */ #include "hal_base.h" -#include "hal_cru.h" +#if defined(SOC_RK3568) && defined(HAL_CRU_MODULE_ENABLED) /** @addtogroup RK_HAL_Driver * @{ @@ -1077,4 +1077,4 @@ HAL_Status HAL_CRU_WdtGlbRstEnable(eCRU_WdtRstType wdtType) /** @} */ - +#endif /* SOC_RK3568 && HAL_CRU_MODULE_ENABLED */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_debug.c b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_debug.c similarity index 95% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_debug.c rename to Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_debug.c index fb8421e80..f2673dcba 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_debug.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_debug.c @@ -39,7 +39,6 @@ @} */ #include "hal_base.h" -#include "hal_debug.h" /** @defgroup DEBUG_Private_Definition Private Definition * @{ @@ -68,7 +67,7 @@ * @param file: pointer to the source file name * @param line: HAL_ASSERT error line source number */ - __attribute__((weak)) void HAL_AssertFailed(const char *file, uint32_t line) +__WEAK void HAL_AssertFailed(const char *file, uint32_t line) { HAL_DBG_ERR("assert failed at %s %lu\n", file, line); while (1) { @@ -139,7 +138,7 @@ extern int _write(int fd, char *ptr, int len); * @param format: format printf param. only support: \%d, \%s, \%ld, \%lld * @return int32_t. */ - __attribute__((weak)) int32_t HAL_DBG_Printf(const char *format, ...) +__WEAK int32_t HAL_DBG_Printf(const char *format, ...) { static char g_printf_buf[HAL_PRINTF_BUF_SIZE]; char *str = g_printf_buf; @@ -215,7 +214,7 @@ extern int _write(int fd, char *ptr, int len); * @param format: format printf param. * @return int32_t. */ - __attribute__((weak)) int32_t HAL_DBG_Printf(const char *format, ...) +__WEAK int32_t HAL_DBG_Printf(const char *format, ...) { return 0; } diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_gmac.c b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_gmac.c similarity index 99% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_gmac.c rename to Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_gmac.c index 6245dcc4e..1d8cb32a7 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_gmac.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_gmac.c @@ -4,10 +4,8 @@ */ #include "hal_base.h" -#include "hal_def.h" -#include "hal_gmac.h" -#include "hal_debug.h" +#ifdef HAL_GMAC_MODULE_ENABLED /** @addtogroup RK_HAL_Driver * @{ @@ -2206,3 +2204,10 @@ HAL_Status HAL_GMAC_DeInit(struct GMAC_HANDLE *pGMAC) return HAL_OK; } +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* HAL_GMAC_MODULE_ENABLED */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_gmac_3568.c b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_gmac_3568.c similarity index 97% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_gmac_3568.c rename to Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_gmac_3568.c index d58c76fe9..6da4c7675 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_gmac_3568.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_gmac_3568.c @@ -4,9 +4,8 @@ */ #include "hal_base.h" -#include "hal_gmac.h" -#include "hal_debug.h" -#include "hal_cru.h" + +#if defined(SOC_RK3568) && defined(HAL_GMAC_MODULE_ENABLED) /** @addtogroup RK_HAL_Driver * @{ @@ -197,3 +196,10 @@ void HAL_GMAC_SetRMIISpeed(struct GMAC_HANDLE *pGMAC, int32_t speed) HAL_GMAC_SetRGMIISpeed(pGMAC, speed); } +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* SOC_RK3568 && HAL_GMAC_MODULE_ENABLED */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_gpio.c b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_gpio.c similarity index 99% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_gpio.c rename to Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_gpio.c index 60ad70471..58385d101 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_gpio.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_gpio.c @@ -4,8 +4,8 @@ */ #include "hal_base.h" -#include "hal_pinctrl.h" -#include "hal_gpio.h" + +#ifdef HAL_GPIO_MODULE_ENABLED /** @addtogroup RK_HAL_Driver * @{ @@ -462,7 +462,7 @@ void HAL_GPIO_DisableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin) * NOTE: This function Should not be modified, when the callback is needed, * the HAL_GPIO_IRQDispatch could be implemented in the user file. */ -__attribute__((weak)) void HAL_GPIO_IRQDispatch(eGPIO_bankId bank, uint32_t pin) +__WEAK void HAL_GPIO_IRQDispatch(eGPIO_bankId bank, uint32_t pin) { UNUSED(bank); UNUSED(pin); @@ -574,4 +574,4 @@ HAL_Status HAL_GPIO_SetVirtualModel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS p /** @} */ - +#endif /* HAL_GPIO_MODULE_ENABLED */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_pinctrl_v2.c b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_pinctrl_v2.c similarity index 99% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_pinctrl_v2.c rename to Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_pinctrl_v2.c index 5f60b423a..9bc8590fa 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_pinctrl_v2.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_pinctrl_v2.c @@ -4,8 +4,8 @@ */ #include "hal_base.h" -#include "hal_def.h" -#include "hal_pinctrl.h" + +#if defined(HAL_PINCTRL_MODULE_ENABLED) && (defined(SOC_RV1126) || defined(SOC_SWALLOW) || defined(SOC_RK3568) || defined(RKMCU_RK2106)) /** @addtogroup RK_HAL_Driver * @{ @@ -562,4 +562,4 @@ HAL_Status HAL_PINCTRL_SetIOMUX(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_conf /** @} */ - +#endif /* HAL_PINCTRL_MODULE_ENABLED */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_timer.c b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_timer.c similarity index 97% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_timer.c rename to Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_timer.c index e317d5d0a..f5e1f05e4 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_timer.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/hal_timer.c @@ -4,8 +4,8 @@ */ #include "hal_base.h" -#include "hal_def.h" -#include "hal_timer.h" + +#ifdef HAL_TIMER_MODULE_ENABLED /** @addtogroup RK_HAL_Driver * @{ @@ -279,7 +279,7 @@ HAL_Status HAL_TIMER_ClrInt(struct TIMER_REG *pReg) * @return HAL_Status: HAL_OK. * Clear interrupt status. */ -__attribute__((weak)) HAL_Status HAL_TIMER0_Handler(void) +__WEAK HAL_Status HAL_TIMER0_Handler(void) { HAL_TIMER_ClrInt(TIMER0); @@ -291,7 +291,7 @@ __attribute__((weak)) HAL_Status HAL_TIMER0_Handler(void) * @return HAL_Status: HAL_OK. * Clear interrupt status. */ -__attribute__((weak)) HAL_Status HAL_TIMER1_Handler(void) +__WEAK HAL_Status HAL_TIMER1_Handler(void) { HAL_TIMER_ClrInt(TIMER1); @@ -304,3 +304,4 @@ __attribute__((weak)) HAL_Status HAL_TIMER1_Handler(void) /** @} */ +#endif /* HAL_TIMER_MODULE_ENABLED */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/system_rk3568.c b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/system_rk3568.c new file mode 100644 index 000000000..a8c33ec56 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/system_rk3568.c @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" +#include "soc.h" + +/* The frequency of SYSTEM_CLOCK is determined by the previous firmware. */ +#define SYSTEM_CLOCK 816000000U + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System Initialization + *----------------------------------------------------------------------------*/ +// void SystemInit (void) +// { +// #if defined(HAL_AP_CORE) && defined(HAL_DCACHE_MODULE_ENABLED) +// /* do not use global variables because this function is called before +// reaching pre-main. RW section may be overwritten afterwards. */ + +// // Invalidate entire Unified TLB +// __set_TLBIALL(0); + +// // Invalidate entire branch predictor array +// __set_BPIALL(0); +// __DSB(); +// __ISB(); + +// // Invalidate instruction cache and flush branch target cache +// __set_ICIALLU(0); +// __DSB(); +// __ISB(); + +// // Invalidate data cache +// L1C_InvalidateDCacheAll(); +// #endif + +// #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) +// // Enable FPU +// __FPU_Enable(); +// #endif + +// #if defined(HAL_AP_CORE) && defined(HAL_DCACHE_MODULE_ENABLED) +// // Create Translation Table +// MMU_CreateTranslationTable(); + +// // Enable MMU +// MMU_Enable(); + +// // Enable Caches +// L1C_EnableCaches(); +// L1C_EnableBTAC(); +// #endif + +// #if defined(HAL_MCU_CORE) && defined(HAL_INTMUX_MODULE_ENABLED) +// HAL_INTMUX_Init(); +// #endif +// } + +// void DataInit (void) +// { +// #ifdef HAL_AP_CORE + +// typedef struct { +// unsigned long* dest; +// unsigned long wlen; +// } __zero_table_t; + +// extern const __zero_table_t __zero_table_start__; +// extern const __zero_table_t __zero_table_end__; + +// for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { +// for (unsigned long i = 0u; i < pTable->wlen; ++i) { +// pTable->dest[i] = 0u; +// } +// } +// #endif /* HAL_AP_CORE */ +// } diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/test_gmac.c b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/test_gmac.c similarity index 89% rename from Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/test_gmac.c rename to Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/test_gmac.c index 4e2fd19d7..5baf84ae9 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/test_gmac.c +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/hal/test_gmac.c @@ -6,15 +6,8 @@ #include "hal_bsp.h" #include "hal_base.h" #include "hal_gmac.h" -#include "hal_pinctrl.h" -#include "hal_debug.h" -#include "hal_timer.h" -#include "hal_cache.h" -#include "hal_gpio.h" -#include "hal_cru.h" -#include "libserial.h" -#include "stdlib.h" +#if (defined(HAL_GMAC_MODULE_ENABLED) || defined(HAL_GMAC1000_MODULE_ENABLED)) /*************************** GMAC DRIVER ****************************/ @@ -109,9 +102,10 @@ static unsigned int m_nocachemem_inited = 0; static uint8_t dstAddr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; +#if defined(HAL_GMAC_MODULE_ENABLED) && defined(SOC_RK3568) static struct GMAC_ETH_CONFIG ethConfigTable[] = { - +#ifdef HAL_GMAC0 { .halDev = &g_gmac0Dev, .mode = PHY_INTERFACE_MODE_RGMII, @@ -127,25 +121,69 @@ static struct GMAC_ETH_CONFIG ethConfigTable[] = .txDelay = 0x3C, .rxDelay = 0x2f, }, +#endif - // { - // .halDev = &g_gmac1Dev, - // .mode = PHY_INTERFACE_MODE_RGMII, - // .maxSpeed = 1000, - // .phyAddr = 1, +#ifdef HAL_GMAC1 + { + .halDev = &g_gmac1Dev, + .mode = PHY_INTERFACE_MODE_RGMII, + .maxSpeed = 1000, + .phyAddr = 1, - // .extClk = false, + .extClk = false, - // .resetGpioBank = GPIO2, - // .resetGpioNum = GPIO_PIN_D1, - // .resetDelayMs = { 0, 20, 100 }, + .resetGpioBank = GPIO2, + .resetGpioNum = GPIO_PIN_D1, + .resetDelayMs = { 0, 20, 100 }, - // .txDelay = 0x4f, - // .rxDelay = 0x26, - // }, + .txDelay = 0x4f, + .rxDelay = 0x26, + }, +#endif }; +#endif +#if defined(HAL_GMAC1000_MODULE_ENABLED) && defined(SOC_RK3358) +static struct GMAC_ETH_CONFIG ethConfigTable[] = +{ +#ifdef HAL_GMAC0 + { + .halDev = &g_gmacDev, + .mode = PHY_INTERFACE_MODE_RMII, + .maxSpeed = 100, + .speed = 100, + .phyAddr = 0, + .extClk = false, + + .resetGpioBank = GPIO2, + .resetGpioNum = GPIO_PIN_B5, + .resetDelayMs = { 0, 50, 50 }, + }, +#endif +}; +#endif + +#if defined(HAL_GMAC1000_MODULE_ENABLED) && defined(SOC_RK3308) +static struct GMAC_ETH_CONFIG ethConfigTable[] = +{ +#ifdef HAL_GMAC0 + { + .halDev = &g_gmac0Dev, + .mode = PHY_INTERFACE_MODE_RMII, + .maxSpeed = 100, + .speed = 100, + .phyAddr = 0, + + .extClk = true, + + .resetGpioBank = GPIO4, + .resetGpioNum = GPIO_PIN_C0, + .resetDelayMs = { 0, 50, 50 }, + }, +#endif +}; +#endif /********************* Private Function Definition ***************************/ @@ -299,7 +337,7 @@ static inline void NET_Random_ETHAddr(uint8_t *addr) uint8_t i; for (i = 0; i < 6; i++) { - addr[i] = 0xae; + addr[i] = rand(); } addr[0] &= 0xfe; /* clear multicast bit */ @@ -312,7 +350,7 @@ static inline void NET_Random_Package(uint8_t *addr, uint16_t len) uint16_t i; for (i = 0; i < len; i++) { - addr[i] = 0xae; + addr[i] = rand(); } } @@ -622,8 +660,7 @@ static HAL_Status GMAC_Init(uint8_t id) /*************************** GMAC TEST ****************************/ #define GMAC_MAX_DEVICES 2 - - +#ifdef SOC_RK3568 /** * @brief Config iomux for GMAC0 */ @@ -671,55 +708,7 @@ static void GMAC0_Iomux_Config(void) (0 << GRF_IO_VSEL1_POC_VCCIO4_SEL33_SHIFT)); #endif } - - - -/** - * @brief Config iomux for GMAC1 - */ -// static void GMAC1_M1_Iomux_Config(void) -// { -// /* GMAC1 M1 iomux */ -// HAL_PINCTRL_SetIOMUX(GPIO_BANK4, -// GPIO_PIN_B6 | /* gmac1_mdcm1 */ -// GPIO_PIN_B7 | /* gmac1_mdiom1 */ -// GPIO_PIN_B1 | /* gmac1_rxdvcrsm1 */ -// GPIO_PIN_A7 | /* gmac1_rxd0m1 */ -// GPIO_PIN_B0 | /* gmac1_rxd1m1 */ -// GPIO_PIN_A1 | /* gmac1_rxd2m1 */ -// GPIO_PIN_A2 | /* gmac1_rxd3m1 */ -// GPIO_PIN_A6 | /* gmac1_txenm1 */ -// GPIO_PIN_A3, /* gmac1_rxclkm1 */ -// PIN_CONFIG_MUX_FUNC3); - -// HAL_PINCTRL_SetIOMUX(GPIO_BANK4, -// GPIO_PIN_A0, /* gmac1_txd1m1 */ -// PIN_CONFIG_MUX_FUNC3 | PIN_CONFIG_DRV_LEVEL3); - -// HAL_PINCTRL_SetIOMUX(GPIO_BANK4, -// GPIO_PIN_A4 | /* gmac1_txd0m1 */ -// GPIO_PIN_A5, /* gmac1_txd1m1 */ -// PIN_CONFIG_MUX_FUNC3 | PIN_CONFIG_DRV_LEVEL2); - -// /* GMAC1 M1 iomux */ -// HAL_PINCTRL_SetIOMUX(GPIO_BANK3, -// GPIO_PIN_D6 | /* gmac1_txd2m1 */ -// GPIO_PIN_D7, /* gmac1_txd3m1 */ -// PIN_CONFIG_MUX_FUNC3 | PIN_CONFIG_DRV_LEVEL2); - -// HAL_PINCTRL_IOFuncSelForGMAC1(IOFUNC_SEL_M1); - -// #if 0 -// /* io-domian: 1.8v or 3.3v for vccio6 */ -// WRITE_REG_MASK_WE(GRF->IO_VSEL0, -// GRF_IO_VSEL0_POC_VCCIO6_SEL18_MASK, -// (1 << GRF_IO_VSEL0_POC_VCCIO6_SEL18_SHIFT)); - -// WRITE_REG_MASK_WE(GRF->IO_VSEL1, -// GRF_IO_VSEL1_POC_VCCIO6_SEL33_MASK, -// (0 << GRF_IO_VSEL1_POC_VCCIO6_SEL33_SHIFT)); -// #endif -// } +#endif static void GMAC_Iomux_Config(uint8_t id) @@ -730,11 +719,15 @@ static void GMAC_Iomux_Config(uint8_t id) GMAC0_Iomux_Config(); // } } +#endif + + + /*************************** GMAC TEST MAIN ****************************/ -void main(){ +void main() { struct GMAC_ETH_CONFIG *eth; struct GMAC_HANDLE *pGMAC; int32_t bus, num = 0, i; @@ -798,3 +791,4 @@ void main(){ free_align(eth->rxBuff); } } + diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/cmsis_compiler.h b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/cmsis_compiler.h new file mode 100644 index 000000000..192f9b7c9 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/cmsis_compiler.h @@ -0,0 +1,303 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.3.0 + * @date 04. April 2023 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + +/* + * TI Arm Clang Compiler (tiarmclang) + */ +#elif defined (__ti__) + #include "cmsis_tiarmclang.h" + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler (armcl) + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + #ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".bss.noinit"))) + #endif + #ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) + #endif + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + #ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".bss.noinit"))) + #endif + #ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) + #endif + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + #ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".bss.noinit"))) + #endif + #ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) + #endif + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/cmsis_cp15.h b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/cmsis_cp15.h new file mode 100644 index 000000000..891bec2ae --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/cmsis_cp15.h @@ -0,0 +1,514 @@ +/**************************************************************************//** + * @file cmsis_cp15.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.1 + * @date 07. Sep 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_CP15_H +#define __CMSIS_CP15_H + +/** \brief Get ACTLR + \return Auxiliary Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_ACTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 1); + return(result); +} + +/** \brief Set ACTLR + \param [in] actlr Auxiliary Control value to set + */ +__STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr) +{ + __set_CP(15, 0, actlr, 1, 0, 1); +} + +/** \brief Get CPACR + \return Coprocessor Access Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPACR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 2); + return result; +} + +/** \brief Set CPACR + \param [in] cpacr Coprocessor Access Control value to set + */ +__STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr) +{ + __set_CP(15, 0, cpacr, 1, 0, 2); +} + +/** \brief Get DFSR + \return Data Fault Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_DFSR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 5, 0, 0); + return result; +} + +/** \brief Set DFSR + \param [in] dfsr Data Fault Status value to set + */ +__STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr) +{ + __set_CP(15, 0, dfsr, 5, 0, 0); +} + +/** \brief Get IFSR + \return Instruction Fault Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IFSR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 5, 0, 1); + return result; +} + +/** \brief Set IFSR + \param [in] ifsr Instruction Fault Status value to set + */ +__STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr) +{ + __set_CP(15, 0, ifsr, 5, 0, 1); +} + +/** \brief Get ISR + \return Interrupt Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_ISR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 1, 0); + return result; +} + +/** \brief Get CBAR + \return Configuration Base Address register value + */ +__STATIC_FORCEINLINE uint32_t __get_CBAR(void) +{ + uint32_t result; + __get_CP(15, 4, result, 15, 0, 0); + return result; +} + +/** \brief Get TTBR0 + + This function returns the value of the Translation Table Base Register 0. + + \return Translation Table Base Register 0 value + */ +__STATIC_FORCEINLINE uint32_t __get_TTBR0(void) +{ + uint32_t result; + __get_CP(15, 0, result, 2, 0, 0); + return result; +} + +/** \brief Set TTBR0 + + This function assigns the given value to the Translation Table Base Register 0. + + \param [in] ttbr0 Translation Table Base Register 0 value to set + */ +__STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0) +{ + __set_CP(15, 0, ttbr0, 2, 0, 0); +} + +/** \brief Get DACR + + This function returns the value of the Domain Access Control Register. + + \return Domain Access Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_DACR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 3, 0, 0); + return result; +} + +/** \brief Set DACR + + This function assigns the given value to the Domain Access Control Register. + + \param [in] dacr Domain Access Control Register value to set + */ +__STATIC_FORCEINLINE void __set_DACR(uint32_t dacr) +{ + __set_CP(15, 0, dacr, 3, 0, 0); +} + +/** \brief Set SCTLR + + This function assigns the given value to the System Control Register. + + \param [in] sctlr System Control Register value to set + */ +__STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr) +{ + __set_CP(15, 0, sctlr, 1, 0, 0); +} + +/** \brief Get SCTLR + \return System Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_SCTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 0); + return result; +} + +/** \brief Set ACTRL + \param [in] actrl Auxiliary Control Register value to set + */ +__STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl) +{ + __set_CP(15, 0, actrl, 1, 0, 1); +} + +/** \brief Get ACTRL + \return Auxiliary Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_ACTRL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 1); + return result; +} + +/** \brief Get MPIDR + + This function returns the value of the Multiprocessor Affinity Register. + + \return Multiprocessor Affinity Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MPIDR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 0, 5); + return result; +} + +/** \brief Get VBAR + + This function returns the value of the Vector Base Address Register. + + \return Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_VBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 0, 0); + return result; +} + +/** \brief Set VBAR + + This function assigns the given value to the Vector Base Address Register. + + \param [in] vbar Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar) +{ + __set_CP(15, 0, vbar, 12, 0, 0); +} + +/** \brief Get MVBAR + + This function returns the value of the Monitor Vector Base Address Register. + + \return Monitor Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_MVBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 0, 1); + return result; +} + +/** \brief Set MVBAR + + This function assigns the given value to the Monitor Vector Base Address Register. + + \param [in] mvbar Monitor Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar) +{ + __set_CP(15, 0, mvbar, 12, 0, 1); +} + +#if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \ + defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \ + defined(DOXYGEN) + +/** \brief Set CNTFRQ + + This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ). + + \param [in] value CNTFRQ Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value) +{ + __set_CP(15, 0, value, 14, 0, 0); +} + +/** \brief Get CNTFRQ + + This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ). + + \return CNTFRQ Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 0 , 0); + return result; +} + +/** \brief Set CNTP_TVAL + + This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL). + + \param [in] value CNTP_TVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 2, 0); +} + +/** \brief Get CNTP_TVAL + + This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL). + + \return CNTP_TVAL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 2, 0); + return result; +} + +/** \brief Get CNTPCT + + This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT). + + \return CNTPCT Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void) +{ + uint64_t result; + __get_CP64(15, 0, result, 14); + return result; +} + +/** \brief Set CNTP_CVAL + + This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + + \param [in] value CNTP_CVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value) +{ + __set_CP64(15, 2, value, 14); +} + +/** \brief Get CNTP_CVAL + + This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + + \return CNTP_CVAL Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void) +{ + uint64_t result; + __get_CP64(15, 2, result, 14); + return result; +} + +/** \brief Set CNTP_CTL + + This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL). + + \param [in] value CNTP_CTL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 2, 1); +} + +/** \brief Get CNTP_CTL register + \return CNTP_CTL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 2, 1); + return result; +} + +#endif + +/** \brief Set TLBIALL + + TLB Invalidate All + */ +__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value) +{ + __set_CP(15, 0, value, 8, 7, 0); +} + +/** \brief Set BPIALL. + + Branch Predictor Invalidate All + */ +__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 6); +} + +/** \brief Set ICIALLU + + Instruction Cache Invalidate All + */ +__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 0); +} + +/** \brief Set DCCMVAC + + Data cache clean + */ +__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 10, 1); +} + +/** \brief Set DCIMVAC + + Data cache invalidate + */ +__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 6, 1); +} + +/** \brief Set DCCIMVAC + + Data cache clean and invalidate + */ +__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 14, 1); +} + +/** \brief Set CSSELR + */ +__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value) +{ +// __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory"); + __set_CP(15, 2, value, 0, 0, 0); +} + +/** \brief Get CSSELR + \return CSSELR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CSSELR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 2, %0, c0, c0, 0" : "=r"(result) : : "memory"); + __get_CP(15, 2, result, 0, 0, 0); + return result; +} + +/** \brief Set CCSIDR + \deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead. + */ +CMSIS_DEPRECATED +__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value) +{ + __set_CSSELR(value); +} + +/** \brief Get CCSIDR + \return CCSIDR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory"); + __get_CP(15, 1, result, 0, 0, 0); + return result; +} + +/** \brief Get CLIDR + \return CLIDR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CLIDR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory"); + __get_CP(15, 1, result, 0, 0, 1); + return result; +} + +/** \brief Set DCISW + */ +__STATIC_FORCEINLINE void __set_DCISW(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(value) : "memory") + __set_CP(15, 0, value, 7, 6, 2); +} + +/** \brief Set DCCSW + */ +__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(value) : "memory") + __set_CP(15, 0, value, 7, 10, 2); +} + +/** \brief Set DCCISW + */ +__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(value) : "memory") + __set_CP(15, 0, value, 7, 14, 2); +} + +#endif diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/cmsis_gcc.h b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/cmsis_gcc.h new file mode 100644 index 000000000..23d61205d --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/cmsis_gcc.h @@ -0,0 +1,913 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.3.0 + * @date 17. December 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ + +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE __attribute__((always_inline)) +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + + +/* ########################## Core Instruction Access ######################### */ +/** + \brief No Operation + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + +/** + \brief Wait For Event + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + +/** + \brief Send Event + */ +#define __SEV() __ASM volatile ("sev") + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : "=r" (result) : "r" (value) ); + return result; +#endif +} + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + __ASM ("rev16 %0, %1" : "=r" (result) : "r" (value)); + return result; +} + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return result; +#endif +} + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + +/** + \brief Count leading zeros + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +/* ########################### Core Function Access ########################### */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value +*/ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #if __has_builtin(__builtin_arm_get_fpscr) + // Re-enable using built-in when GCC has been fixed + // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); + #else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); + #endif + #else + return(0U); + #endif +} + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set +*/ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #if __has_builtin(__builtin_arm_set_fpscr) + // Re-enable using built-in when GCC has been fixed + // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); + #else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + #endif + #else + (void)fpscr; + #endif +} + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ +__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) +{ + uint32_t cpsr = __get_CPSR(); + uint32_t result; + __ASM volatile( + "CPS #0x1F \n" + "MOV %0, sp " : "=r"(result) : : "memory" + ); + __set_CPSR(cpsr); + __ISB(); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr = __get_CPSR(); + __ASM volatile( + "CPS #0x1F \n" + "MOV sp, %0 " : : "r" (topOfProcStack) : "memory" + ); + __set_CPSR(cpsr); + __ISB(); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) ); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE void __FPU_Enable(void) +{ + __ASM volatile( + //Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB \n" + + //Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + //Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + //Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#if (defined(__ARM_NEON) && (__ARM_NEON == 1)) + //Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + + //Initialise FPSCR to a known state + " VMRS R1,FPSCR \n" + " LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R1,R1,R2 \n" + " VMSR FPSCR,R1 " + : : : "cc", "r1", "r2" + ); +} + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/core_ca.h b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/core_ca.h new file mode 100644 index 000000000..c4f926900 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/core_ca.h @@ -0,0 +1,2614 @@ +/**************************************************************************//** + * @file core_ca.h + * @brief CMSIS Cortex-A Core Peripheral Access Layer Header File + * @version V1.0.3 + * @date 28. January 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CA_H_GENERIC +#define __CORE_CA_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ + +/* CMSIS CA definitions */ +#define __CA_CMSIS_VERSION_MAIN (1U) /*!< \brief [31:16] CMSIS-Core(A) main version */ +#define __CA_CMSIS_VERSION_SUB (1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */ +#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \ + __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */ + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CA_H_DEPENDANT +#define __CORE_CA_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + + /* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CA_REV + #define __CA_REV 0x0000U + #warning "__CA_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __GIC_PRESENT + #define __GIC_PRESENT 1U + #warning "__GIC_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __TIM_PRESENT + #define __TIM_PRESENT 1U + #warning "__TIM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __L2C_PRESENT + #define __L2C_PRESENT 0U + #warning "__L2C_PRESENT not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< \brief Defines 'read only' permissions */ +#else + #define __I volatile const /*!< \brief Defines 'read only' permissions */ +#endif +#define __O volatile /*!< \brief Defines 'write only' permissions */ +#define __IO volatile /*!< \brief Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*!< \brief Defines 'read only' structure member permissions */ +#define __OM volatile /*!< \brief Defines 'write only' structure member permissions */ +#define __IOM volatile /*!< \brief Defines 'read / write' structure member permissions */ +#define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas + + /******************************************************************************* + * Register Abstraction + Core Register contain: + - CPSR + - CP15 Registers + - L2C-310 Cache Controller + - Generic Interrupt Controller Distributor + - Generic Interrupt Controller Interface + ******************************************************************************/ + +/* Core Register CPSR */ +typedef union +{ + struct + { + uint32_t M:5; /*!< \brief bit: 0.. 4 Mode field */ + uint32_t T:1; /*!< \brief bit: 5 Thumb execution state bit */ + uint32_t F:1; /*!< \brief bit: 6 FIQ mask bit */ + uint32_t I:1; /*!< \brief bit: 7 IRQ mask bit */ + uint32_t A:1; /*!< \brief bit: 8 Asynchronous abort mask bit */ + uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */ + uint32_t IT1:6; /*!< \brief bit: 10..15 If-Then execution state bits 2-7 */ + uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */ + RESERVED(0:4, uint32_t) + uint32_t J:1; /*!< \brief bit: 24 Jazelle bit */ + uint32_t IT0:2; /*!< \brief bit: 25..26 If-Then execution state bits 0-1 */ + uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< \brief bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< \brief bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< \brief bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< \brief bit: 31 Negative condition code flag */ + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CPSR_Type; + + + +/* CPSR Register Definitions */ +#define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */ +#define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */ + +#define CPSR_Z_Pos 30U /*!< \brief CPSR: Z Position */ +#define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< \brief CPSR: Z Mask */ + +#define CPSR_C_Pos 29U /*!< \brief CPSR: C Position */ +#define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< \brief CPSR: C Mask */ + +#define CPSR_V_Pos 28U /*!< \brief CPSR: V Position */ +#define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< \brief CPSR: V Mask */ + +#define CPSR_Q_Pos 27U /*!< \brief CPSR: Q Position */ +#define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< \brief CPSR: Q Mask */ + +#define CPSR_IT0_Pos 25U /*!< \brief CPSR: IT0 Position */ +#define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< \brief CPSR: IT0 Mask */ + +#define CPSR_J_Pos 24U /*!< \brief CPSR: J Position */ +#define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< \brief CPSR: J Mask */ + +#define CPSR_GE_Pos 16U /*!< \brief CPSR: GE Position */ +#define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< \brief CPSR: GE Mask */ + +#define CPSR_IT1_Pos 10U /*!< \brief CPSR: IT1 Position */ +#define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< \brief CPSR: IT1 Mask */ + +#define CPSR_E_Pos 9U /*!< \brief CPSR: E Position */ +#define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< \brief CPSR: E Mask */ + +#define CPSR_A_Pos 8U /*!< \brief CPSR: A Position */ +#define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< \brief CPSR: A Mask */ + +#define CPSR_I_Pos 7U /*!< \brief CPSR: I Position */ +#define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< \brief CPSR: I Mask */ + +#define CPSR_F_Pos 6U /*!< \brief CPSR: F Position */ +#define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< \brief CPSR: F Mask */ + +#define CPSR_T_Pos 5U /*!< \brief CPSR: T Position */ +#define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< \brief CPSR: T Mask */ + +#define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */ +#define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */ + +#define CPSR_M_USR 0x10U /*!< \brief CPSR: M User mode (PL0) */ +#define CPSR_M_FIQ 0x11U /*!< \brief CPSR: M Fast Interrupt mode (PL1) */ +#define CPSR_M_IRQ 0x12U /*!< \brief CPSR: M Interrupt mode (PL1) */ +#define CPSR_M_SVC 0x13U /*!< \brief CPSR: M Supervisor mode (PL1) */ +#define CPSR_M_MON 0x16U /*!< \brief CPSR: M Monitor mode (PL1) */ +#define CPSR_M_ABT 0x17U /*!< \brief CPSR: M Abort mode (PL1) */ +#define CPSR_M_HYP 0x1AU /*!< \brief CPSR: M Hypervisor mode (PL2) */ +#define CPSR_M_UND 0x1BU /*!< \brief CPSR: M Undefined mode (PL1) */ +#define CPSR_M_SYS 0x1FU /*!< \brief CPSR: M System mode (PL1) */ + +/* CP15 Register SCTLR */ +typedef union +{ + struct + { + uint32_t M:1; /*!< \brief bit: 0 MMU enable */ + uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */ + uint32_t C:1; /*!< \brief bit: 2 Cache enable */ + RESERVED(0:2, uint32_t) + uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */ + RESERVED(1:1, uint32_t) + uint32_t B:1; /*!< \brief bit: 7 Endianness model */ + RESERVED(2:2, uint32_t) + uint32_t SW:1; /*!< \brief bit: 10 SWP and SWPB enable */ + uint32_t Z:1; /*!< \brief bit: 11 Branch prediction enable */ + uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */ + uint32_t V:1; /*!< \brief bit: 13 Vectors bit */ + uint32_t RR:1; /*!< \brief bit: 14 Round Robin select */ + RESERVED(3:2, uint32_t) + uint32_t HA:1; /*!< \brief bit: 17 Hardware Access flag enable */ + RESERVED(4:1, uint32_t) + uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */ + uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */ + uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */ + uint32_t U:1; /*!< \brief bit: 22 Alignment model */ + RESERVED(5:1, uint32_t) + uint32_t VE:1; /*!< \brief bit: 24 Interrupt Vectors Enable */ + uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */ + RESERVED(6:1, uint32_t) + uint32_t NMFI:1; /*!< \brief bit: 27 Non-maskable FIQ (NMFI) support */ + uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */ + uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */ + uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */ + RESERVED(7:1, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} SCTLR_Type; + +#define SCTLR_TE_Pos 30U /*!< \brief SCTLR: TE Position */ +#define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< \brief SCTLR: TE Mask */ + +#define SCTLR_AFE_Pos 29U /*!< \brief SCTLR: AFE Position */ +#define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< \brief SCTLR: AFE Mask */ + +#define SCTLR_TRE_Pos 28U /*!< \brief SCTLR: TRE Position */ +#define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< \brief SCTLR: TRE Mask */ + +#define SCTLR_NMFI_Pos 27U /*!< \brief SCTLR: NMFI Position */ +#define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< \brief SCTLR: NMFI Mask */ + +#define SCTLR_EE_Pos 25U /*!< \brief SCTLR: EE Position */ +#define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< \brief SCTLR: EE Mask */ + +#define SCTLR_VE_Pos 24U /*!< \brief SCTLR: VE Position */ +#define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< \brief SCTLR: VE Mask */ + +#define SCTLR_U_Pos 22U /*!< \brief SCTLR: U Position */ +#define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< \brief SCTLR: U Mask */ + +#define SCTLR_FI_Pos 21U /*!< \brief SCTLR: FI Position */ +#define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< \brief SCTLR: FI Mask */ + +#define SCTLR_UWXN_Pos 20U /*!< \brief SCTLR: UWXN Position */ +#define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< \brief SCTLR: UWXN Mask */ + +#define SCTLR_WXN_Pos 19U /*!< \brief SCTLR: WXN Position */ +#define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< \brief SCTLR: WXN Mask */ + +#define SCTLR_HA_Pos 17U /*!< \brief SCTLR: HA Position */ +#define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< \brief SCTLR: HA Mask */ + +#define SCTLR_RR_Pos 14U /*!< \brief SCTLR: RR Position */ +#define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< \brief SCTLR: RR Mask */ + +#define SCTLR_V_Pos 13U /*!< \brief SCTLR: V Position */ +#define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< \brief SCTLR: V Mask */ + +#define SCTLR_I_Pos 12U /*!< \brief SCTLR: I Position */ +#define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< \brief SCTLR: I Mask */ + +#define SCTLR_Z_Pos 11U /*!< \brief SCTLR: Z Position */ +#define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< \brief SCTLR: Z Mask */ + +#define SCTLR_SW_Pos 10U /*!< \brief SCTLR: SW Position */ +#define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< \brief SCTLR: SW Mask */ + +#define SCTLR_B_Pos 7U /*!< \brief SCTLR: B Position */ +#define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< \brief SCTLR: B Mask */ + +#define SCTLR_CP15BEN_Pos 5U /*!< \brief SCTLR: CP15BEN Position */ +#define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< \brief SCTLR: CP15BEN Mask */ + +#define SCTLR_C_Pos 2U /*!< \brief SCTLR: C Position */ +#define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< \brief SCTLR: C Mask */ + +#define SCTLR_A_Pos 1U /*!< \brief SCTLR: A Position */ +#define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< \brief SCTLR: A Mask */ + +#define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */ +#define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */ + +/* CP15 Register ACTLR */ +typedef union +{ +#if __CORTEX_A == 5 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A5 */ + struct + { + uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ + RESERVED(0:5, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ + RESERVED(1:2, uint32_t) + uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ + uint32_t DWBST:1; /*!< \brief bit: 11 AXI data write bursts to Normal memory */ + uint32_t RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ + uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ + uint32_t BP:2; /*!< \brief bit:16..15 Branch prediction policy */ + uint32_t RSDIS:1; /*!< \brief bit: 17 Disable return stack operation */ + uint32_t BTDIS:1; /*!< \brief bit: 18 Disable indirect Branch Target Address Cache (BTAC) */ + RESERVED(3:9, uint32_t) + uint32_t DBDI:1; /*!< \brief bit: 28 Disable branch dual issue */ + RESERVED(7:3, uint32_t) + } b; +#endif +#if __CORTEX_A == 7 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A7 */ + struct + { + RESERVED(0:6, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + RESERVED(1:3, uint32_t) + uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ + uint32_t L2RADIS:1; /*!< \brief bit: 11 L2 Data Cache read-allocate mode disable */ + uint32_t L1RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ + uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ + uint32_t DDVM:1; /*!< \brief bit: 15 Disable Distributed Virtual Memory (DVM) transactions */ + RESERVED(3:12, uint32_t) + uint32_t DDI:1; /*!< \brief bit: 28 Disable dual issue */ + RESERVED(7:3, uint32_t) + } b; +#endif +#if __CORTEX_A == 9 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A9 */ + struct + { + uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ + RESERVED(0:1, uint32_t) + uint32_t L1PE:1; /*!< \brief bit: 2 Dside prefetch */ + uint32_t WFLZM:1; /*!< \brief bit: 3 Cache and TLB maintenance broadcast */ + RESERVED(1:2, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ + uint32_t AOW:1; /*!< \brief bit: 8 Enable allocation in one cache way only */ + uint32_t PARITY:1; /*!< \brief bit: 9 Support for parity checking, if implemented */ + RESERVED(7:22, uint32_t) + } b; +#endif + uint32_t w; /*!< \brief Type used for word access */ +} ACTLR_Type; + +#define ACTLR_DDI_Pos 28U /*!< \brief ACTLR: DDI Position */ +#define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /*!< \brief ACTLR: DDI Mask */ + +#define ACTLR_DBDI_Pos 28U /*!< \brief ACTLR: DBDI Position */ +#define ACTLR_DBDI_Msk (1UL << ACTLR_DBDI_Pos) /*!< \brief ACTLR: DBDI Mask */ + +#define ACTLR_BTDIS_Pos 18U /*!< \brief ACTLR: BTDIS Position */ +#define ACTLR_BTDIS_Msk (1UL << ACTLR_BTDIS_Pos) /*!< \brief ACTLR: BTDIS Mask */ + +#define ACTLR_RSDIS_Pos 17U /*!< \brief ACTLR: RSDIS Position */ +#define ACTLR_RSDIS_Msk (1UL << ACTLR_RSDIS_Pos) /*!< \brief ACTLR: RSDIS Mask */ + +#define ACTLR_BP_Pos 15U /*!< \brief ACTLR: BP Position */ +#define ACTLR_BP_Msk (3UL << ACTLR_BP_Pos) /*!< \brief ACTLR: BP Mask */ + +#define ACTLR_DDVM_Pos 15U /*!< \brief ACTLR: DDVM Position */ +#define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /*!< \brief ACTLR: DDVM Mask */ + +#define ACTLR_L1PCTL_Pos 13U /*!< \brief ACTLR: L1PCTL Position */ +#define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /*!< \brief ACTLR: L1PCTL Mask */ + +#define ACTLR_RADIS_Pos 12U /*!< \brief ACTLR: RADIS Position */ +#define ACTLR_RADIS_Msk (1UL << ACTLR_RADIS_Pos) /*!< \brief ACTLR: RADIS Mask */ + +#define ACTLR_L1RADIS_Pos 12U /*!< \brief ACTLR: L1RADIS Position */ +#define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /*!< \brief ACTLR: L1RADIS Mask */ + +#define ACTLR_DWBST_Pos 11U /*!< \brief ACTLR: DWBST Position */ +#define ACTLR_DWBST_Msk (1UL << ACTLR_DWBST_Pos) /*!< \brief ACTLR: DWBST Mask */ + +#define ACTLR_L2RADIS_Pos 11U /*!< \brief ACTLR: L2RADIS Position */ +#define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /*!< \brief ACTLR: L2RADIS Mask */ + +#define ACTLR_DODMBS_Pos 10U /*!< \brief ACTLR: DODMBS Position */ +#define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /*!< \brief ACTLR: DODMBS Mask */ + +#define ACTLR_PARITY_Pos 9U /*!< \brief ACTLR: PARITY Position */ +#define ACTLR_PARITY_Msk (1UL << ACTLR_PARITY_Pos) /*!< \brief ACTLR: PARITY Mask */ + +#define ACTLR_AOW_Pos 8U /*!< \brief ACTLR: AOW Position */ +#define ACTLR_AOW_Msk (1UL << ACTLR_AOW_Pos) /*!< \brief ACTLR: AOW Mask */ + +#define ACTLR_EXCL_Pos 7U /*!< \brief ACTLR: EXCL Position */ +#define ACTLR_EXCL_Msk (1UL << ACTLR_EXCL_Pos) /*!< \brief ACTLR: EXCL Mask */ + +#define ACTLR_SMP_Pos 6U /*!< \brief ACTLR: SMP Position */ +#define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /*!< \brief ACTLR: SMP Mask */ + +#define ACTLR_WFLZM_Pos 3U /*!< \brief ACTLR: WFLZM Position */ +#define ACTLR_WFLZM_Msk (1UL << ACTLR_WFLZM_Pos) /*!< \brief ACTLR: WFLZM Mask */ + +#define ACTLR_L1PE_Pos 2U /*!< \brief ACTLR: L1PE Position */ +#define ACTLR_L1PE_Msk (1UL << ACTLR_L1PE_Pos) /*!< \brief ACTLR: L1PE Mask */ + +#define ACTLR_FW_Pos 0U /*!< \brief ACTLR: FW Position */ +#define ACTLR_FW_Msk (1UL << ACTLR_FW_Pos) /*!< \brief ACTLR: FW Mask */ + +/* CP15 Register CPACR */ +typedef union +{ + struct + { + uint32_t CP0:2; /*!< \brief bit: 0..1 Access rights for coprocessor 0 */ + uint32_t CP1:2; /*!< \brief bit: 2..3 Access rights for coprocessor 1 */ + uint32_t CP2:2; /*!< \brief bit: 4..5 Access rights for coprocessor 2 */ + uint32_t CP3:2; /*!< \brief bit: 6..7 Access rights for coprocessor 3 */ + uint32_t CP4:2; /*!< \brief bit: 8..9 Access rights for coprocessor 4 */ + uint32_t CP5:2; /*!< \brief bit:10..11 Access rights for coprocessor 5 */ + uint32_t CP6:2; /*!< \brief bit:12..13 Access rights for coprocessor 6 */ + uint32_t CP7:2; /*!< \brief bit:14..15 Access rights for coprocessor 7 */ + uint32_t CP8:2; /*!< \brief bit:16..17 Access rights for coprocessor 8 */ + uint32_t CP9:2; /*!< \brief bit:18..19 Access rights for coprocessor 9 */ + uint32_t CP10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */ + uint32_t CP11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */ + uint32_t CP12:2; /*!< \brief bit:24..25 Access rights for coprocessor 11 */ + uint32_t CP13:2; /*!< \brief bit:26..27 Access rights for coprocessor 11 */ + uint32_t TRCDIS:1; /*!< \brief bit: 28 Disable CP14 access to trace registers */ + RESERVED(0:1, uint32_t) + uint32_t D32DIS:1; /*!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file */ + uint32_t ASEDIS:1; /*!< \brief bit: 31 Disable Advanced SIMD Functionality */ + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CPACR_Type; + +#define CPACR_ASEDIS_Pos 31U /*!< \brief CPACR: ASEDIS Position */ +#define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< \brief CPACR: ASEDIS Mask */ + +#define CPACR_D32DIS_Pos 30U /*!< \brief CPACR: D32DIS Position */ +#define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ + +#define CPACR_TRCDIS_Pos 28U /*!< \brief CPACR: D32DIS Position */ +#define CPACR_TRCDIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ + +#define CPACR_CP_Pos_(n) (n*2U) /*!< \brief CPACR: CPn Position */ +#define CPACR_CP_Msk_(n) (3UL << CPACR_CP_Pos_(n)) /*!< \brief CPACR: CPn Mask */ + +#define CPACR_CP_NA 0U /*!< \brief CPACR CPn field: Access denied. */ +#define CPACR_CP_PL1 1U /*!< \brief CPACR CPn field: Accessible from PL1 only. */ +#define CPACR_CP_FA 3U /*!< \brief CPACR CPn field: Full access. */ + +/* CP15 Register DFSR */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ + uint32_t Domain:4; /*!< \brief bit: 4.. 7 Fault on which domain */ + RESERVED(0:1, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ + uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ + RESERVED(1:18, uint32_t) + } s; /*!< \brief Structure used for bit access in short format */ + struct + { + uint32_t STATUS:5; /*!< \brief bit: 0.. 5 Fault Status bits */ + RESERVED(0:3, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + RESERVED(1:1, uint32_t) + uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ + RESERVED(2:18, uint32_t) + } l; /*!< \brief Structure used for bit access in long format */ + uint32_t w; /*!< \brief Type used for word access */ +} DFSR_Type; + +#define DFSR_CM_Pos 13U /*!< \brief DFSR: CM Position */ +#define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< \brief DFSR: CM Mask */ + +#define DFSR_Ext_Pos 12U /*!< \brief DFSR: Ext Position */ +#define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< \brief DFSR: Ext Mask */ + +#define DFSR_WnR_Pos 11U /*!< \brief DFSR: WnR Position */ +#define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< \brief DFSR: WnR Mask */ + +#define DFSR_FS1_Pos 10U /*!< \brief DFSR: FS1 Position */ +#define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< \brief DFSR: FS1 Mask */ + +#define DFSR_LPAE_Pos 9U /*!< \brief DFSR: LPAE Position */ +#define DFSR_LPAE_Msk (1UL << DFSR_LPAE_Pos) /*!< \brief DFSR: LPAE Mask */ + +#define DFSR_Domain_Pos 4U /*!< \brief DFSR: Domain Position */ +#define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< \brief DFSR: Domain Mask */ + +#define DFSR_FS0_Pos 0U /*!< \brief DFSR: FS0 Position */ +#define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< \brief DFSR: FS0 Mask */ + +#define DFSR_STATUS_Pos 0U /*!< \brief DFSR: STATUS Position */ +#define DFSR_STATUS_Msk (0x3FUL << DFSR_STATUS_Pos) /*!< \brief DFSR: STATUS Mask */ + +/* CP15 Register IFSR */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ + RESERVED(0:5, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ + RESERVED(1:1, uint32_t) + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + RESERVED(2:19, uint32_t) + } s; /*!< \brief Structure used for bit access in short format */ + struct + { + uint32_t STATUS:6; /*!< \brief bit: 0.. 5 Fault Status bits */ + RESERVED(0:3, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + RESERVED(1:2, uint32_t) + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + RESERVED(2:19, uint32_t) + } l; /*!< \brief Structure used for bit access in long format */ + uint32_t w; /*!< \brief Type used for word access */ +} IFSR_Type; + +#define IFSR_ExT_Pos 12U /*!< \brief IFSR: ExT Position */ +#define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< \brief IFSR: ExT Mask */ + +#define IFSR_FS1_Pos 10U /*!< \brief IFSR: FS1 Position */ +#define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< \brief IFSR: FS1 Mask */ + +#define IFSR_LPAE_Pos 9U /*!< \brief IFSR: LPAE Position */ +#define IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) /*!< \brief IFSR: LPAE Mask */ + +#define IFSR_FS0_Pos 0U /*!< \brief IFSR: FS0 Position */ +#define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< \brief IFSR: FS0 Mask */ + +#define IFSR_STATUS_Pos 0U /*!< \brief IFSR: STATUS Position */ +#define IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) /*!< \brief IFSR: STATUS Mask */ + +/* CP15 Register ISR */ +typedef union +{ + struct + { + RESERVED(0:6, uint32_t) + uint32_t F:1; /*!< \brief bit: 6 FIQ pending bit */ + uint32_t I:1; /*!< \brief bit: 7 IRQ pending bit */ + uint32_t A:1; /*!< \brief bit: 8 External abort pending bit */ + RESERVED(1:23, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} ISR_Type; + +#define ISR_A_Pos 13U /*!< \brief ISR: A Position */ +#define ISR_A_Msk (1UL << ISR_A_Pos) /*!< \brief ISR: A Mask */ + +#define ISR_I_Pos 12U /*!< \brief ISR: I Position */ +#define ISR_I_Msk (1UL << ISR_I_Pos) /*!< \brief ISR: I Mask */ + +#define ISR_F_Pos 11U /*!< \brief ISR: F Position */ +#define ISR_F_Msk (1UL << ISR_F_Pos) /*!< \brief ISR: F Mask */ + +/* DACR Register */ +#define DACR_D_Pos_(n) (2U*n) /*!< \brief DACR: Dn Position */ +#define DACR_D_Msk_(n) (3UL << DACR_D_Pos_(n)) /*!< \brief DACR: Dn Mask */ +#define DACR_Dn_NOACCESS 0U /*!< \brief DACR Dn field: No access */ +#define DACR_Dn_CLIENT 1U /*!< \brief DACR Dn field: Client */ +#define DACR_Dn_MANAGER 3U /*!< \brief DACR Dn field: Manager */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param [in] field Name of the register bit field. + \param [in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param [in] field Name of the register bit field. + \param [in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + + +/** + \brief Union type to access the L2C_310 Cache Controller. +*/ +#if (__L2C_PRESENT == 1U) || defined(DOXYGEN) +typedef struct +{ + __IM uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 (R/ ) Cache ID Register */ + __IM uint32_t CACHE_TYPE; /*!< \brief Offset: 0x0004 (R/ ) Cache Type Register */ + RESERVED(0[0x3e], uint32_t) + __IOM uint32_t CONTROL; /*!< \brief Offset: 0x0100 (R/W) Control Register */ + __IOM uint32_t AUX_CNT; /*!< \brief Offset: 0x0104 (R/W) Auxiliary Control */ + RESERVED(1[0x3e], uint32_t) + __IOM uint32_t EVENT_CONTROL; /*!< \brief Offset: 0x0200 (R/W) Event Counter Control */ + __IOM uint32_t EVENT_COUNTER1_CONF; /*!< \brief Offset: 0x0204 (R/W) Event Counter 1 Configuration */ + __IOM uint32_t EVENT_COUNTER0_CONF; /*!< \brief Offset: 0x0208 (R/W) Event Counter 1 Configuration */ + RESERVED(2[0x2], uint32_t) + __IOM uint32_t INTERRUPT_MASK; /*!< \brief Offset: 0x0214 (R/W) Interrupt Mask */ + __IM uint32_t MASKED_INT_STATUS; /*!< \brief Offset: 0x0218 (R/ ) Masked Interrupt Status */ + __IM uint32_t RAW_INT_STATUS; /*!< \brief Offset: 0x021c (R/ ) Raw Interrupt Status */ + __OM uint32_t INTERRUPT_CLEAR; /*!< \brief Offset: 0x0220 ( /W) Interrupt Clear */ + RESERVED(3[0x143], uint32_t) + __IOM uint32_t CACHE_SYNC; /*!< \brief Offset: 0x0730 (R/W) Cache Sync */ + RESERVED(4[0xf], uint32_t) + __IOM uint32_t INV_LINE_PA; /*!< \brief Offset: 0x0770 (R/W) Invalidate Line By PA */ + RESERVED(6[2], uint32_t) + __IOM uint32_t INV_WAY; /*!< \brief Offset: 0x077c (R/W) Invalidate by Way */ + RESERVED(5[0xc], uint32_t) + __IOM uint32_t CLEAN_LINE_PA; /*!< \brief Offset: 0x07b0 (R/W) Clean Line by PA */ + RESERVED(7[1], uint32_t) + __IOM uint32_t CLEAN_LINE_INDEX_WAY; /*!< \brief Offset: 0x07b8 (R/W) Clean Line by Index/Way */ + __IOM uint32_t CLEAN_WAY; /*!< \brief Offset: 0x07bc (R/W) Clean by Way */ + RESERVED(8[0xc], uint32_t) + __IOM uint32_t CLEAN_INV_LINE_PA; /*!< \brief Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA */ + RESERVED(9[1], uint32_t) + __IOM uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< \brief Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way */ + __IOM uint32_t CLEAN_INV_WAY; /*!< \brief Offset: 0x07fc (R/W) Clean and Invalidate by Way */ + RESERVED(10[0x40], uint32_t) + __IOM uint32_t DATA_LOCK_0_WAY; /*!< \brief Offset: 0x0900 (R/W) Data Lockdown 0 by Way */ + __IOM uint32_t INST_LOCK_0_WAY; /*!< \brief Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way */ + __IOM uint32_t DATA_LOCK_1_WAY; /*!< \brief Offset: 0x0908 (R/W) Data Lockdown 1 by Way */ + __IOM uint32_t INST_LOCK_1_WAY; /*!< \brief Offset: 0x090c (R/W) Instruction Lockdown 1 by Way */ + __IOM uint32_t DATA_LOCK_2_WAY; /*!< \brief Offset: 0x0910 (R/W) Data Lockdown 2 by Way */ + __IOM uint32_t INST_LOCK_2_WAY; /*!< \brief Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way */ + __IOM uint32_t DATA_LOCK_3_WAY; /*!< \brief Offset: 0x0918 (R/W) Data Lockdown 3 by Way */ + __IOM uint32_t INST_LOCK_3_WAY; /*!< \brief Offset: 0x091c (R/W) Instruction Lockdown 3 by Way */ + __IOM uint32_t DATA_LOCK_4_WAY; /*!< \brief Offset: 0x0920 (R/W) Data Lockdown 4 by Way */ + __IOM uint32_t INST_LOCK_4_WAY; /*!< \brief Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way */ + __IOM uint32_t DATA_LOCK_5_WAY; /*!< \brief Offset: 0x0928 (R/W) Data Lockdown 5 by Way */ + __IOM uint32_t INST_LOCK_5_WAY; /*!< \brief Offset: 0x092c (R/W) Instruction Lockdown 5 by Way */ + __IOM uint32_t DATA_LOCK_6_WAY; /*!< \brief Offset: 0x0930 (R/W) Data Lockdown 5 by Way */ + __IOM uint32_t INST_LOCK_6_WAY; /*!< \brief Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way */ + __IOM uint32_t DATA_LOCK_7_WAY; /*!< \brief Offset: 0x0938 (R/W) Data Lockdown 6 by Way */ + __IOM uint32_t INST_LOCK_7_WAY; /*!< \brief Offset: 0x093c (R/W) Instruction Lockdown 6 by Way */ + RESERVED(11[0x4], uint32_t) + __IOM uint32_t LOCK_LINE_EN; /*!< \brief Offset: 0x0950 (R/W) Lockdown by Line Enable */ + __IOM uint32_t UNLOCK_ALL_BY_WAY; /*!< \brief Offset: 0x0954 (R/W) Unlock All Lines by Way */ + RESERVED(12[0xaa], uint32_t) + __IOM uint32_t ADDRESS_FILTER_START; /*!< \brief Offset: 0x0c00 (R/W) Address Filtering Start */ + __IOM uint32_t ADDRESS_FILTER_END; /*!< \brief Offset: 0x0c04 (R/W) Address Filtering End */ + RESERVED(13[0xce], uint32_t) + __IOM uint32_t DEBUG_CONTROL; /*!< \brief Offset: 0x0f40 (R/W) Debug Control Register */ +} L2C_310_TypeDef; + +#define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 register set access pointer */ +#endif + +#if (__GIC_PRESENT == 1U) || defined(DOXYGEN) + +/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD) +*/ +typedef struct +{ + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) Distributor Control Register */ + __IM uint32_t TYPER; /*!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IM uint32_t IIDR; /*!< \brief Offset: 0x008 (R/ ) Distributor Implementer Identification Register */ + RESERVED(0, uint32_t) + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional */ + RESERVED(1[11], uint32_t) + __OM uint32_t SETSPI_NSR; /*!< \brief Offset: 0x040 ( /W) Set SPI Register */ + RESERVED(2, uint32_t) + __OM uint32_t CLRSPI_NSR; /*!< \brief Offset: 0x048 ( /W) Clear SPI Register */ + RESERVED(3, uint32_t) + __OM uint32_t SETSPI_SR; /*!< \brief Offset: 0x050 ( /W) Set SPI, Secure Register */ + RESERVED(4, uint32_t) + __OM uint32_t CLRSPI_SR; /*!< \brief Offset: 0x058 ( /W) Clear SPI, Secure Register */ + RESERVED(5[9], uint32_t) + __IOM uint32_t IGROUPR[32]; /*!< \brief Offset: 0x080 (R/W) Interrupt Group Registers */ + __IOM uint32_t ISENABLER[32]; /*!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registers */ + __IOM uint32_t ICENABLER[32]; /*!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */ + __IOM uint32_t ISPENDR[32]; /*!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Registers */ + __IOM uint32_t ICPENDR[32]; /*!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */ + __IOM uint32_t ISACTIVER[32]; /*!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registers */ + __IOM uint32_t ICACTIVER[32]; /*!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Registers */ + __IOM uint32_t IPRIORITYR[255]; /*!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers */ + RESERVED(6, uint32_t) + __IOM uint32_t ITARGETSR[255]; /*!< \brief Offset: 0x800 (R/W) Interrupt Targets Registers */ + RESERVED(7, uint32_t) + __IOM uint32_t ICFGR[64]; /*!< \brief Offset: 0xC00 (R/W) Interrupt Configuration Registers */ + __IOM uint32_t IGRPMODR[32]; /*!< \brief Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */ + RESERVED(8[32], uint32_t) + __IOM uint32_t NSACR[64]; /*!< \brief Offset: 0xE00 (R/W) Non-secure Access Control Registers */ + __OM uint32_t SGIR; /*!< \brief Offset: 0xF00 ( /W) Software Generated Interrupt Register */ + RESERVED(9[3], uint32_t) + __IOM uint32_t CPENDSGIR[4]; /*!< \brief Offset: 0xF10 (R/W) SGI Clear-Pending Registers */ + __IOM uint32_t SPENDSGIR[4]; /*!< \brief Offset: 0xF20 (R/W) SGI Set-Pending Registers */ + RESERVED(10[5236], uint32_t) + __IOM uint64_t IROUTER[988]; /*!< \brief Offset: 0x6100(R/W) Interrupt Routing Registers */ +} GICDistributor_Type; + +#define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< \brief GIC Distributor register set access pointer */ + +/** \brief Structure type to access the Generic Interrupt Controller Interface (GICC) +*/ +typedef struct +{ + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) CPU Interface Control Register */ + __IOM uint32_t PMR; /*!< \brief Offset: 0x004 (R/W) Interrupt Priority Mask Register */ + __IOM uint32_t BPR; /*!< \brief Offset: 0x008 (R/W) Binary Point Register */ + __IM uint32_t IAR; /*!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Register */ + __OM uint32_t EOIR; /*!< \brief Offset: 0x010 ( /W) End Of Interrupt Register */ + __IM uint32_t RPR; /*!< \brief Offset: 0x014 (R/ ) Running Priority Register */ + __IM uint32_t HPPIR; /*!< \brief Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */ + __IOM uint32_t ABPR; /*!< \brief Offset: 0x01C (R/W) Aliased Binary Point Register */ + __IM uint32_t AIAR; /*!< \brief Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */ + __OM uint32_t AEOIR; /*!< \brief Offset: 0x024 ( /W) Aliased End Of Interrupt Register */ + __IM uint32_t AHPPIR; /*!< \brief Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */ + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x02C (R/W) Error Reporting Status Register, optional */ + RESERVED(1[40], uint32_t) + __IOM uint32_t APR[4]; /*!< \brief Offset: 0x0D0 (R/W) Active Priority Register */ + __IOM uint32_t NSAPR[4]; /*!< \brief Offset: 0x0E0 (R/W) Non-secure Active Priority Register */ + RESERVED(2[3], uint32_t) + __IM uint32_t IIDR; /*!< \brief Offset: 0x0FC (R/ ) CPU Interface Identification Register */ + RESERVED(3[960], uint32_t) + __OM uint32_t DIR; /*!< \brief Offset: 0x1000( /W) Deactivate Interrupt Register */ +} GICInterface_Type; + +#define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< \brief GIC Interface register set access pointer */ +#endif + +#if (__TIM_PRESENT == 1U) || defined(DOXYGEN) +#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) +/** \brief Structure type to access the Private Timer +*/ +typedef struct +{ + __IOM uint32_t LOAD; //!< \brief Offset: 0x000 (R/W) Private Timer Load Register + __IOM uint32_t COUNTER; //!< \brief Offset: 0x004 (R/W) Private Timer Counter Register + __IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register + __IOM uint32_t ISR; //!< \brief Offset: 0x00C (R/W) Private Timer Interrupt Status Register + RESERVED(0[4], uint32_t) + __IOM uint32_t WLOAD; //!< \brief Offset: 0x020 (R/W) Watchdog Load Register + __IOM uint32_t WCOUNTER; //!< \brief Offset: 0x024 (R/W) Watchdog Counter Register + __IOM uint32_t WCONTROL; //!< \brief Offset: 0x028 (R/W) Watchdog Control Register + __IOM uint32_t WISR; //!< \brief Offset: 0x02C (R/W) Watchdog Interrupt Status Register + __IOM uint32_t WRESET; //!< \brief Offset: 0x030 (R/W) Watchdog Reset Status Register + __OM uint32_t WDISABLE; //!< \brief Offset: 0x034 ( /W) Watchdog Disable Register +} Timer_Type; +#define PTIM ((Timer_Type *) TIMER_BASE ) /*!< \brief Timer register struct */ +#endif +#endif + + /******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - L1 Cache Functions + - L2C-310 Cache Controller Functions + - PL1 Timer Functions + - GIC Functions + - MMU Functions + ******************************************************************************/ + +/* ########################## L1 Cache functions ################################# */ + +/** \brief Enable Caches by setting I and C bits in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_EnableCaches(void) { + __set_SCTLR( __get_SCTLR() | SCTLR_I_Msk | SCTLR_C_Msk); + __ISB(); +} + +/** \brief Disable Caches by clearing I and C bits in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_DisableCaches(void) { + __set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk)); + __ISB(); +} + +/** \brief Enable Branch Prediction by setting Z bit in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_EnableBTAC(void) { + __set_SCTLR( __get_SCTLR() | SCTLR_Z_Msk); + __ISB(); +} + +/** \brief Disable Branch Prediction by clearing Z bit in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_DisableBTAC(void) { + __set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk)); + __ISB(); +} + +/** \brief Invalidate entire branch predictor array +*/ +__STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) { + __set_BPIALL(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new state +} + +/** \brief Invalidate the whole instruction cache +*/ +__STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) { + __set_ICIALLU(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new I cache state +} + +/** \brief Clean data cache line by address. +* \param [in] va Pointer to data to clear the cache for. +*/ +__STATIC_FORCEINLINE void L1C_CleanDCacheMVA(void *va) { + __set_DCCMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Invalidate data cache line by address. +* \param [in] va Pointer to data to invalidate the cache for. +*/ +__STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA(void *va) { + __set_DCIMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Clean and Invalidate data cache by address. +* \param [in] va Pointer to data to invalidate the cache for. +*/ +__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA(void *va) { + __set_DCCIMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Calculate log2 rounded up +* - log(0) => 0 +* - log(1) => 0 +* - log(2) => 1 +* - log(3) => 2 +* - log(4) => 2 +* - log(5) => 3 +* : : +* - log(16) => 4 +* - log(32) => 5 +* : : +* \param [in] n input value parameter +* \return log2(n) +*/ +__STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n) +{ + if (n < 2U) { + return 0U; + } + uint8_t log = 0U; + uint32_t t = n; + while(t > 1U) + { + log++; + t >>= 1U; + } + if (n & 1U) { log++; } + return log; +} + +/** \brief Apply cache maintenance to given cache level. +* \param [in] level cache level to be maintained +* \param [in] maint 0 - invalidate, 1 - clean, otherwise - invalidate and clean +*/ +__STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint) +{ + uint32_t Dummy; + uint32_t ccsidr; + uint32_t num_sets; + uint32_t num_ways; + uint32_t shift_way; + uint32_t log2_linesize; + int32_t log2_num_ways; + + Dummy = level << 1U; + /* set csselr, select ccsidr register */ + __set_CSSELR(Dummy); + /* get current ccsidr register */ + ccsidr = __get_CCSIDR(); + num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U; + num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U; + log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U; + log2_num_ways = __log2_up(num_ways); + if ((log2_num_ways < 0) || (log2_num_ways > 32)) { + return; // FATAL ERROR + } + shift_way = 32U - (uint32_t)log2_num_ways; + for(int32_t way = num_ways-1; way >= 0; way--) + { + for(int32_t set = num_sets-1; set >= 0; set--) + { + Dummy = (level << 1U) | (((uint32_t)set) << log2_linesize) | (((uint32_t)way) << shift_way); + switch (maint) + { + case 0U: __set_DCISW(Dummy); break; + case 1U: __set_DCCSW(Dummy); break; + default: __set_DCCISW(Dummy); break; + } + } + } + __DMB(); +} + +/** \brief Clean and Invalidate the entire data or unified cache +* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency +* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean +*/ +__STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) { + uint32_t clidr; + uint32_t cache_type; + clidr = __get_CLIDR(); + for(uint32_t i = 0U; i<7U; i++) + { + cache_type = (clidr >> i*3U) & 0x7UL; + if ((cache_type >= 2U) && (cache_type <= 4U)) + { + __L1C_MaintainDCacheSetWay(i, op); + } + } +} + +/** \brief Clean and Invalidate the entire data or unified cache +* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency +* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean +* \deprecated Use generic L1C_CleanInvalidateCache instead. +*/ +CMSIS_DEPRECATED +__STATIC_FORCEINLINE void __L1C_CleanInvalidateCache(uint32_t op) { + L1C_CleanInvalidateCache(op); +} + +/** \brief Invalidate the whole data cache. +*/ +__STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) { + L1C_CleanInvalidateCache(0); +} + +/** \brief Clean the whole data cache. + */ +__STATIC_FORCEINLINE void L1C_CleanDCacheAll(void) { + L1C_CleanInvalidateCache(1); +} + +/** \brief Clean and invalidate the whole data cache. + */ +__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) { + L1C_CleanInvalidateCache(2); +} + +/* ########################## L2 Cache functions ################################# */ +#if (__L2C_PRESENT == 1U) || defined(DOXYGEN) +/** \brief Cache Sync operation by writing CACHE_SYNC register. +*/ +__STATIC_INLINE void L2C_Sync(void) +{ + L2C_310->CACHE_SYNC = 0x0; +} + +/** \brief Read cache controller cache ID from CACHE_ID register. + * \return L2C_310_TypeDef::CACHE_ID + */ +__STATIC_INLINE int L2C_GetID (void) +{ + return L2C_310->CACHE_ID; +} + +/** \brief Read cache controller cache type from CACHE_TYPE register. +* \return L2C_310_TypeDef::CACHE_TYPE +*/ +__STATIC_INLINE int L2C_GetType (void) +{ + return L2C_310->CACHE_TYPE; +} + +/** \brief Invalidate all cache by way +*/ +__STATIC_INLINE void L2C_InvAllByWay (void) +{ + unsigned int assoc; + + if (L2C_310->AUX_CNT & (1U << 16U)) { + assoc = 16U; + } else { + assoc = 8U; + } + + L2C_310->INV_WAY = (1U << assoc) - 1U; + while(L2C_310->INV_WAY & ((1U << assoc) - 1U)); //poll invalidate + + L2C_Sync(); +} + +/** \brief Clean and Invalidate all cache by way +*/ +__STATIC_INLINE void L2C_CleanInvAllByWay (void) +{ + unsigned int assoc; + + if (L2C_310->AUX_CNT & (1U << 16U)) { + assoc = 16U; + } else { + assoc = 8U; + } + + L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U; + while(L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); //poll invalidate + + L2C_Sync(); +} + +/** \brief Enable Level 2 Cache +*/ +__STATIC_INLINE void L2C_Enable(void) +{ + L2C_310->CONTROL = 0; + L2C_310->INTERRUPT_CLEAR = 0x000001FFuL; + L2C_310->DEBUG_CONTROL = 0; + L2C_310->DATA_LOCK_0_WAY = 0; + L2C_310->CACHE_SYNC = 0; + L2C_310->CONTROL = 0x01; + L2C_Sync(); +} + +/** \brief Disable Level 2 Cache +*/ +__STATIC_INLINE void L2C_Disable(void) +{ + L2C_310->CONTROL = 0x00; + L2C_Sync(); +} + +/** \brief Invalidate cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_InvPa (void *pa) +{ + L2C_310->INV_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} + +/** \brief Clean cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_CleanPa (void *pa) +{ + L2C_310->CLEAN_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} + +/** \brief Clean and invalidate cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_CleanInvPa (void *pa) +{ + L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} +#endif + +/* ########################## GIC functions ###################################### */ +#if (__GIC_PRESENT == 1U) || defined(DOXYGEN) + +/** \brief Enable the interrupt distributor using the GIC's CTLR register. +*/ +__STATIC_INLINE void GIC_EnableDistributor(void) +{ + GICDistributor->CTLR |= 1U; +} + +/** \brief Disable the interrupt distributor using the GIC's CTLR register. +*/ +__STATIC_INLINE void GIC_DisableDistributor(void) +{ + GICDistributor->CTLR &=~1U; +} + +/** \brief Read the GIC's TYPER register. +* \return GICDistributor_Type::TYPER +*/ +__STATIC_INLINE uint32_t GIC_DistributorInfo(void) +{ + return (GICDistributor->TYPER); +} + +/** \brief Reads the GIC's IIDR register. +* \return GICDistributor_Type::IIDR +*/ +__STATIC_INLINE uint32_t GIC_DistributorImplementer(void) +{ + return (GICDistributor->IIDR); +} + +/** \brief Sets the GIC's ITARGETSR register for the given interrupt. +* \param [in] IRQn Interrupt to be configured. +* \param [in] cpu_target CPU interfaces to assign this interrupt to. +*/ +__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target) +{ + uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U)); +} + +/** \brief Read the GIC's ITARGETSR register. +* \param [in] IRQn Interrupt to acquire the configuration for. +* \return GICDistributor_Type::ITARGETSR +*/ +__STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn) +{ + return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; +} + +/** \brief Enable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_EnableInterface(void) +{ + GICInterface->CTLR |= 1U; //enable interface +} + +/** \brief Disable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_DisableInterface(void) +{ + GICInterface->CTLR &=~1U; //disable distributor +} + +/** \brief Read the CPU's IAR register. +* \return GICInterface_Type::IAR +*/ +__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void) +{ + return (IRQn_Type)(GICInterface->IAR); +} + +/** \brief Writes the given interrupt number to the CPU's EOIR register. +* \param [in] IRQn The interrupt to be signaled as finished. +*/ +__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn) +{ + GICInterface->EOIR = IRQn; +} + +/** \brief Enables the given interrupt using GIC's ISENABLER register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn) +{ + GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U); +} + +/** \brief Get interrupt enable status using GIC's ISENABLER register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - interrupt is not enabled, 1 - interrupt is enabled. +*/ +__STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn) +{ + return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL; +} + +/** \brief Disables the given interrupt using GIC's ICENABLER register. +* \param [in] IRQn The interrupt to be disabled. +*/ +__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn) +{ + GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U); +} + +/** \brief Get interrupt pending status from GIC's ISPENDR register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - interrupt is not pending, 1 - interrupt is pendig. +*/ +__STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn) +{ + uint32_t pend; + + if (IRQn >= 16U) { + pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; + } else { + // INTID 0-15 Software Generated Interrupt + pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; + // No CPU identification offered + if (pend != 0U) { + pend = 1U; + } else { + pend = 0U; + } + } + + return (pend); +} + +/** \brief Sets the given interrupt as pending using GIC's ISPENDR register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if (IRQn >= 16U) { + GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U); + } else { + // INTID 0-15 Software Generated Interrupt + // Forward the interrupt to the CPU interface that requested it + GICDistributor->SGIR = (IRQn | 0x02000000U); + } +} + +/** \brief Clears the given interrupt from being pending using GIC's ICPENDR register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if (IRQn >= 16U) { + GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U); + } else { + // INTID 0-15 Software Generated Interrupt + GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U); + } +} + +/** \brief Sets the interrupt configuration using GIC's ICFGR register. +* \param [in] IRQn The interrupt to be configured. +* \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) +* Bit 1: 0 - level sensitive, 1 - edge triggered +*/ +__STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config) +{ + uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U]; + uint32_t shift = (IRQn % 16U) << 1U; + + icfgr &= (~(3U << shift)); + icfgr |= ( int_config << shift); + + GICDistributor->ICFGR[IRQn / 16U] = icfgr; +} + +/** \brief Get the interrupt configuration from the GIC's ICFGR register. +* \param [in] IRQn Interrupt to acquire the configuration for. +* \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) +* Bit 1: 0 - level sensitive, 1 - edge triggered +*/ +__STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn) +{ + return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U)); +} + +/** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register. +* \param [in] IRQn The interrupt to be configured. +* \param [in] priority The priority for the interrupt, lower values denote higher priorities. +*/ +__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U)); +} + +/** \brief Read the current interrupt priority from GIC's IPRIORITYR register. +* \param [in] IRQn The interrupt to be queried. +*/ +__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn) +{ + return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; +} + +/** \brief Set the interrupt priority mask using CPU's PMR register. +* \param [in] priority Priority mask to be set. +*/ +__STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority) +{ + GICInterface->PMR = priority & 0xFFUL; //set priority mask +} + +/** \brief Read the current interrupt priority mask from CPU's PMR register. +* \result GICInterface_Type::PMR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void) +{ + return GICInterface->PMR; +} + +/** \brief Configures the group priority and subpriority split point using CPU's BPR register. +* \param [in] binary_point Amount of bits used as subpriority. +*/ +__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point) +{ + GICInterface->BPR = binary_point & 7U; //set binary point +} + +/** \brief Read the current group priority and subpriority split point from CPU's BPR register. +* \return GICInterface_Type::BPR +*/ +__STATIC_INLINE uint32_t GIC_GetBinaryPoint(void) +{ + return GICInterface->BPR; +} + +/** \brief Get the status for a given interrupt. +* \param [in] IRQn The interrupt to get status for. +* \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active +*/ +__STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn) +{ + uint32_t pending, active; + + active = ((GICDistributor->ISACTIVER[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; + pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; + + return ((active<<1U) | pending); +} + +/** \brief Generate a software interrupt using GIC's SGIR register. +* \param [in] IRQn Software interrupt to be generated. +* \param [in] target_list List of CPUs the software interrupt should be forwarded to. +* \param [in] filter_list Filter to be applied to determine interrupt receivers. +*/ +__STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list) +{ + GICDistributor->SGIR = ((filter_list & 3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL); +} + +/** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register. +* \return GICInterface_Type::HPPIR +*/ +__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void) +{ + return GICInterface->HPPIR; +} + +/** \brief Provides information about the implementer and revision of the CPU interface. +* \return GICInterface_Type::IIDR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfaceId(void) +{ + return GICInterface->IIDR; +} + +/** \brief Set the interrupt group from the GIC's IGROUPR register. +* \param [in] IRQn The interrupt to be queried. +* \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1 +*/ +__STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group) +{ + uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U]; + uint32_t shift = (IRQn % 32U); + + igroupr &= (~(1U << shift)); + igroupr |= ( (group & 1U) << shift); + + GICDistributor->IGROUPR[IRQn / 32U] = igroupr; +} +#define GIC_SetSecurity GIC_SetGroup + +/** \brief Get the interrupt group from the GIC's IGROUPR register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - Group 0, 1 - Group 1 +*/ +__STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn) +{ + return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; +} +#define GIC_GetSecurity GIC_GetGroup + +/** \brief Initialize the interrupt distributor. +*/ +__STATIC_INLINE void GIC_DistInit(void) +{ + uint32_t i; + uint32_t num_irq = 0U; + uint32_t priority_field; + + //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableDistributor(); + //Get the maximum number of interrupts that the GIC supports + num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0U, 0xFFU); + priority_field = GIC_GetPriority((IRQn_Type)0U); + + for (i = 32U; i < num_irq; i++) + { + //Disable the SPI interrupt + GIC_DisableIRQ((IRQn_Type)i); + //Set level-sensitive (and N-N model) + GIC_SetConfiguration((IRQn_Type)i, 0U); + //Set priority + GIC_SetPriority((IRQn_Type)i, priority_field/2U); + //Set target list to CPU0 + GIC_SetTarget((IRQn_Type)i, 1U); + } + //Enable distributor + GIC_EnableDistributor(); +} + +/** \brief Initialize the CPU's interrupt interface +*/ +__STATIC_INLINE void GIC_CPUInterfaceInit(void) +{ + uint32_t i; + uint32_t priority_field; + + //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableInterface(); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0U, 0xFFU); + priority_field = GIC_GetPriority((IRQn_Type)0U); + + //SGI and PPI + for (i = 0U; i < 32U; i++) + { + if(i > 15U) { + //Set level-sensitive (and N-N model) for PPI + GIC_SetConfiguration((IRQn_Type)i, 0U); + } + //Disable SGI and PPI interrupts + GIC_DisableIRQ((IRQn_Type)i); + //Set priority + GIC_SetPriority((IRQn_Type)i, priority_field/2U); + } + //Enable interface + GIC_EnableInterface(); + //Set binary point to 0 + GIC_SetBinaryPoint(0U); + //Set priority mask + GIC_SetInterfacePriorityMask(0xFFU); +} + +/** \brief Initialize and enable the GIC +*/ +__STATIC_INLINE void GIC_Enable(void) +{ + GIC_DistInit(); + GIC_CPUInterfaceInit(); //per CPU +} +#endif + +/* ########################## Generic Timer functions ############################ */ +#if (__TIM_PRESENT == 1U) || defined(DOXYGEN) + +/* PL1 Physical Timer */ +#if (__CORTEX_A == 7U) || defined(DOXYGEN) + +/** \brief Physical Timer Control register */ +typedef union +{ + struct + { + uint32_t ENABLE:1; /*!< \brief bit: 0 Enables the timer. */ + uint32_t IMASK:1; /*!< \brief bit: 1 Timer output signal mask bit. */ + uint32_t ISTATUS:1; /*!< \brief bit: 2 The status of the timer. */ + RESERVED(0:29, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CNTP_CTL_Type; + +/** \brief Configures the frequency the timer shall run at. +* \param [in] value The timer frequency in Hz. +*/ +__STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value) +{ + __set_CNTFRQ(value); + __ISB(); +} + +/** \brief Sets the reset value of the timer. +* \param [in] value The value the timer is loaded with. +*/ +__STATIC_INLINE void PL1_SetLoadValue(uint32_t value) +{ + __set_CNTP_TVAL(value); + __ISB(); +} + +/** \brief Get the current counter value. +* \return Current counter value. +*/ +__STATIC_INLINE uint32_t PL1_GetCurrentValue(void) +{ + return(__get_CNTP_TVAL()); +} + +/** \brief Get the current physical counter value. +* \return Current physical counter value. +*/ +__STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void) +{ + return(__get_CNTPCT()); +} + +/** \brief Set the physical compare value. +* \param [in] value New physical timer compare value. +*/ +__STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value) +{ + __set_CNTP_CVAL(value); + __ISB(); +} + +/** \brief Get the physical compare value. +* \return Physical compare value. +*/ +__STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void) +{ + return(__get_CNTP_CVAL()); +} + +/** \brief Configure the timer by setting the control value. +* \param [in] value New timer control value. +*/ +__STATIC_INLINE void PL1_SetControl(uint32_t value) +{ + __set_CNTP_CTL(value); + __ISB(); +} + +/** \brief Get the control value. +* \return Control value. +*/ +__STATIC_INLINE uint32_t PL1_GetControl(void) +{ + return(__get_CNTP_CTL()); +} +#endif + +/* Private Timer */ +#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) +/** \brief Set the load value to timers LOAD register. +* \param [in] value The load value to be set. +*/ +__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) +{ + PTIM->LOAD = value; +} + +/** \brief Get the load value from timers LOAD register. +* \return Timer_Type::LOAD +*/ +__STATIC_INLINE uint32_t PTIM_GetLoadValue(void) +{ + return(PTIM->LOAD); +} + +/** \brief Set current counter value from its COUNTER register. +*/ +__STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value) +{ + PTIM->COUNTER = value; +} + +/** \brief Get current counter value from timers COUNTER register. +* \result Timer_Type::COUNTER +*/ +__STATIC_INLINE uint32_t PTIM_GetCurrentValue(void) +{ + return(PTIM->COUNTER); +} + +/** \brief Configure the timer using its CONTROL register. +* \param [in] value The new configuration value to be set. +*/ +__STATIC_INLINE void PTIM_SetControl(uint32_t value) +{ + PTIM->CONTROL = value; +} + +/** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register. +* \return Timer_Type::CONTROL +*/ +__STATIC_INLINE uint32_t PTIM_GetControl(void) +{ + return(PTIM->CONTROL); +} + +/** ref Timer_Type::CONTROL Get the event flag in timers ISR register. +* \return 0 - flag is not set, 1- flag is set +*/ +__STATIC_INLINE uint32_t PTIM_GetEventFlag(void) +{ + return (PTIM->ISR & 1UL); +} + +/** ref Timer_Type::CONTROL Clears the event flag in timers ISR register. +*/ +__STATIC_INLINE void PTIM_ClearEventFlag(void) +{ + PTIM->ISR = 1; +} +#endif +#endif + +/* ########################## MMU functions ###################################### */ + +#define SECTION_DESCRIPTOR (0x2) +#define SECTION_MASK (0xFFFFFFFC) + +#define SECTION_TEXCB_MASK (0xFFFF8FF3) +#define SECTION_B_SHIFT (2) +#define SECTION_C_SHIFT (3) +#define SECTION_TEX0_SHIFT (12) +#define SECTION_TEX1_SHIFT (13) +#define SECTION_TEX2_SHIFT (14) + +#define SECTION_XN_MASK (0xFFFFFFEF) +#define SECTION_XN_SHIFT (4) + +#define SECTION_DOMAIN_MASK (0xFFFFFE1F) +#define SECTION_DOMAIN_SHIFT (5) + +#define SECTION_P_MASK (0xFFFFFDFF) +#define SECTION_P_SHIFT (9) + +#define SECTION_AP_MASK (0xFFFF73FF) +#define SECTION_AP_SHIFT (10) +#define SECTION_AP2_SHIFT (15) + +#define SECTION_S_MASK (0xFFFEFFFF) +#define SECTION_S_SHIFT (16) + +#define SECTION_NG_MASK (0xFFFDFFFF) +#define SECTION_NG_SHIFT (17) + +#define SECTION_NS_MASK (0xFFF7FFFF) +#define SECTION_NS_SHIFT (19) + +#define PAGE_L1_DESCRIPTOR (0x1) +#define PAGE_L1_MASK (0xFFFFFFFC) + +#define PAGE_L2_4K_DESC (0x2) +#define PAGE_L2_4K_MASK (0xFFFFFFFD) + +#define PAGE_L2_64K_DESC (0x1) +#define PAGE_L2_64K_MASK (0xFFFFFFFC) + +#define PAGE_4K_TEXCB_MASK (0xFFFFFE33) +#define PAGE_4K_B_SHIFT (2) +#define PAGE_4K_C_SHIFT (3) +#define PAGE_4K_TEX0_SHIFT (6) +#define PAGE_4K_TEX1_SHIFT (7) +#define PAGE_4K_TEX2_SHIFT (8) + +#define PAGE_64K_TEXCB_MASK (0xFFFF8FF3) +#define PAGE_64K_B_SHIFT (2) +#define PAGE_64K_C_SHIFT (3) +#define PAGE_64K_TEX0_SHIFT (12) +#define PAGE_64K_TEX1_SHIFT (13) +#define PAGE_64K_TEX2_SHIFT (14) + +#define PAGE_TEXCB_MASK (0xFFFF8FF3) +#define PAGE_B_SHIFT (2) +#define PAGE_C_SHIFT (3) +#define PAGE_TEX_SHIFT (12) + +#define PAGE_XN_4K_MASK (0xFFFFFFFE) +#define PAGE_XN_4K_SHIFT (0) +#define PAGE_XN_64K_MASK (0xFFFF7FFF) +#define PAGE_XN_64K_SHIFT (15) + +#define PAGE_DOMAIN_MASK (0xFFFFFE1F) +#define PAGE_DOMAIN_SHIFT (5) + +#define PAGE_P_MASK (0xFFFFFDFF) +#define PAGE_P_SHIFT (9) + +#define PAGE_AP_MASK (0xFFFFFDCF) +#define PAGE_AP_SHIFT (4) +#define PAGE_AP2_SHIFT (9) + +#define PAGE_S_MASK (0xFFFFFBFF) +#define PAGE_S_SHIFT (10) + +#define PAGE_NG_MASK (0xFFFFF7FF) +#define PAGE_NG_SHIFT (11) + +#define PAGE_NS_MASK (0xFFFFFFF7) +#define PAGE_NS_SHIFT (3) + +#define OFFSET_1M (0x00100000) +#define OFFSET_64K (0x00010000) +#define OFFSET_4K (0x00001000) + +#define DESCRIPTOR_FAULT (0x00000000) + +/* Attributes enumerations */ + +/* Region size attributes */ +typedef enum +{ + SECTION, + PAGE_4k, + PAGE_64k, +} mmu_region_size_Type; + +/* Region type attributes */ +typedef enum +{ + NORMAL, + DEVICE, + SHARED_DEVICE, + NON_SHARED_DEVICE, + STRONGLY_ORDERED +} mmu_memory_Type; + +/* Region cacheability attributes */ +typedef enum +{ + NON_CACHEABLE, + WB_WA, + WT, + WB_NO_WA, +} mmu_cacheability_Type; + +/* Region parity check attributes */ +typedef enum +{ + ECC_DISABLED, + ECC_ENABLED, +} mmu_ecc_check_Type; + +/* Region execution attributes */ +typedef enum +{ + EXECUTE, + NON_EXECUTE, +} mmu_execute_Type; + +/* Region global attributes */ +typedef enum +{ + GLOBAL, + NON_GLOBAL, +} mmu_global_Type; + +/* Region shareability attributes */ +typedef enum +{ + NON_SHARED, + SHARED, +} mmu_shared_Type; + +/* Region security attributes */ +typedef enum +{ + SECURE, + NON_SECURE, +} mmu_secure_Type; + +/* Region access attributes */ +typedef enum +{ + NO_ACCESS, + RW, + READ, +} mmu_access_Type; + +/* Memory Region definition */ +typedef struct RegionStruct { + mmu_region_size_Type rg_t; + mmu_memory_Type mem_t; + uint8_t domain; + mmu_cacheability_Type inner_norm_t; + mmu_cacheability_Type outer_norm_t; + mmu_ecc_check_Type e_t; + mmu_execute_Type xn_t; + mmu_global_Type g_t; + mmu_secure_Type sec_t; + mmu_access_Type priv_t; + mmu_access_Type user_t; + mmu_shared_Type sh_t; + +} mmu_region_attributes_Type; + +//Following macros define the descriptors and attributes +//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0 +#define section_normal(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_NC. Outer & inner non-cacheable, non-shareable, executable, rw, domain 0 +#define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0 +#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_RO. Sect_Normal_Cod, but not executable +#define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable +#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); +//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 +#define section_so(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0 +#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Device_RW. Sect_Device_RO, but writeable +#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); +//Page_4k_Device_RW. Shared device, not executable, rw, domain 0 +#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = SHARED_DEVICE; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); + +//Page_64k_Device_RW. Shared device, not executable, rw, domain 0 +#define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = SHARED_DEVICE; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); + +/** \brief Set section execution-never attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE. + + \return 0 +*/ +__STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn) +{ + *descriptor_l1 &= SECTION_XN_MASK; + *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT); + return 0; +} + +/** \brief Set section domain + + \param [out] descriptor_l1 L1 descriptor. + \param [in] domain Section domain + + \return 0 +*/ +__STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain) +{ + *descriptor_l1 &= SECTION_DOMAIN_MASK; + *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT); + return 0; +} + +/** \brief Set section parity check + + \param [out] descriptor_l1 L1 descriptor. + \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED + + \return 0 +*/ +__STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) +{ + *descriptor_l1 &= SECTION_P_MASK; + *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); + return 0; +} + +/** \brief Set section access privileges + + \param [out] descriptor_l1 L1 descriptor. + \param [in] user User Level Access: NO_ACCESS, RW, READ + \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ + \param [in] afe Access flag enable + + \return 0 +*/ +__STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) +{ + uint32_t ap = 0; + + if (afe == 0) { //full access + if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } + else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == READ)) { ap = 0x2; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + else { //Simplified access + if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + *descriptor_l1 &= SECTION_AP_MASK; + *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT; + *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT; + + return 0; +} + +/** \brief Set section shareability + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit Section shareability: NON_SHARED, SHARED + + \return 0 +*/ +__STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit) +{ + *descriptor_l1 &= SECTION_S_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT); + return 0; +} + +/** \brief Set section Global attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL + + \return 0 +*/ +__STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit) +{ + *descriptor_l1 &= SECTION_NG_MASK; + *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT); + return 0; +} + +/** \brief Set section Security attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit Section Security attribute: SECURE, NON_SECURE + + \return 0 +*/ +__STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit) +{ + *descriptor_l1 &= SECTION_NS_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT); + return 0; +} + +/* Page 4k or 64k */ +/** \brief Set 4k/64k page execution-never attribute + + \param [out] descriptor_l2 L2 descriptor. + \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE. + \param [in] page Page size: PAGE_4k, PAGE_64k, + + \return 0 +*/ +__STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page) +{ + if (page == PAGE_4k) + { + *descriptor_l2 &= PAGE_XN_4K_MASK; + *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT); + } + else + { + *descriptor_l2 &= PAGE_XN_64K_MASK; + *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT); + } + return 0; +} + +/** \brief Set 4k/64k page domain + + \param [out] descriptor_l1 L1 descriptor. + \param [in] domain Page domain + + \return 0 +*/ +__STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain) +{ + *descriptor_l1 &= PAGE_DOMAIN_MASK; + *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page parity check + + \param [out] descriptor_l1 L1 descriptor. + \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED + + \return 0 +*/ +__STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) +{ + *descriptor_l1 &= SECTION_P_MASK; + *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page access privileges + + \param [out] descriptor_l2 L2 descriptor. + \param [in] user User Level Access: NO_ACCESS, RW, READ + \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ + \param [in] afe Access flag enable + + \return 0 +*/ +__STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) +{ + uint32_t ap = 0; + + if (afe == 0) { //full access + if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } + else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == READ)) { ap = 0x2; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x6; } + } + + else { //Simplified access + if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + *descriptor_l2 &= PAGE_AP_MASK; + *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT; + *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT; + + return 0; +} + +/** \brief Set 4k/64k page shareability + + \param [out] descriptor_l2 L2 descriptor. + \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED + + \return 0 +*/ +__STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit) +{ + *descriptor_l2 &= PAGE_S_MASK; + *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page Global attribute + + \param [out] descriptor_l2 L2 descriptor. + \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL + + \return 0 +*/ +__STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit) +{ + *descriptor_l2 &= PAGE_NG_MASK; + *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page Security attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE + + \return 0 +*/ +__STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit) +{ + *descriptor_l1 &= PAGE_NS_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT); + return 0; +} + +/** \brief Set Section memory attributes + + \param [out] descriptor_l1 L1 descriptor. + \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED + \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + + \return 0 +*/ +__STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner) +{ + *descriptor_l1 &= SECTION_TEXCB_MASK; + + if (STRONGLY_ORDERED == mem) + { + return 0; + } + else if (SHARED_DEVICE == mem) + { + *descriptor_l1 |= (1 << SECTION_B_SHIFT); + } + else if (NON_SHARED_DEVICE == mem) + { + *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT); + } + else if (NORMAL == mem) + { + *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT; + switch(inner) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l1 |= (1 << SECTION_B_SHIFT); + break; + case WT: + *descriptor_l1 |= 1 << SECTION_C_SHIFT; + break; + case WB_NO_WA: + *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT); + break; + } + switch(outer) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT); + break; + case WT: + *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT; + break; + case WB_NO_WA: + *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT); + break; + } + } + return 0; +} + +/** \brief Set 4k/64k page memory attributes + + \param [out] descriptor_l2 L2 descriptor. + \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED + \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] page Page size + + \return 0 +*/ +__STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page) +{ + *descriptor_l2 &= PAGE_4K_TEXCB_MASK; + + if (page == PAGE_64k) + { + //same as section + MMU_MemorySection(descriptor_l2, mem, outer, inner); + } + else + { + if (STRONGLY_ORDERED == mem) + { + return 0; + } + else if (SHARED_DEVICE == mem) + { + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); + } + else if (NON_SHARED_DEVICE == mem) + { + *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT); + } + else if (NORMAL == mem) + { + *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT; + switch(inner) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); + break; + case WT: + *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT; + break; + case WB_NO_WA: + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT); + break; + } + switch(outer) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT); + break; + case WT: + *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT; + break; + case WB_NO_WA: + *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT); + break; + } + } + } + + return 0; +} + +/** \brief Create a L1 section descriptor + + \param [out] descriptor L1 descriptor + \param [in] reg Section attributes + + \return 0 +*/ +__STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg) +{ + *descriptor = 0; + + MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t); + MMU_XNSection(descriptor,reg.xn_t); + MMU_DomainSection(descriptor, reg.domain); + MMU_PSection(descriptor, reg.e_t); + MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1); + MMU_SharedSection(descriptor,reg.sh_t); + MMU_GlobalSection(descriptor,reg.g_t); + MMU_SecureSection(descriptor,reg.sec_t); + *descriptor &= SECTION_MASK; + *descriptor |= SECTION_DESCRIPTOR; + + return 0; +} + + +/** \brief Create a L1 and L2 4k/64k page descriptor + + \param [out] descriptor L1 descriptor + \param [out] descriptor2 L2 descriptor + \param [in] reg 4k/64k page attributes + + \return 0 +*/ +__STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg) +{ + *descriptor = 0; + *descriptor2 = 0; + + switch (reg.rg_t) + { + case PAGE_4k: + MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k); + MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k); + MMU_DomainPage(descriptor, reg.domain); + MMU_PPage(descriptor, reg.e_t); + MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1); + MMU_SharedPage(descriptor2,reg.sh_t); + MMU_GlobalPage(descriptor2,reg.g_t); + MMU_SecurePage(descriptor,reg.sec_t); + *descriptor &= PAGE_L1_MASK; + *descriptor |= PAGE_L1_DESCRIPTOR; + *descriptor2 &= PAGE_L2_4K_MASK; + *descriptor2 |= PAGE_L2_4K_DESC; + break; + + case PAGE_64k: + MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k); + MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k); + MMU_DomainPage(descriptor, reg.domain); + MMU_PPage(descriptor, reg.e_t); + MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1); + MMU_SharedPage(descriptor2,reg.sh_t); + MMU_GlobalPage(descriptor2,reg.g_t); + MMU_SecurePage(descriptor,reg.sec_t); + *descriptor &= PAGE_L1_MASK; + *descriptor |= PAGE_L1_DESCRIPTOR; + *descriptor2 &= PAGE_L2_64K_MASK; + *descriptor2 |= PAGE_L2_64K_DESC; + break; + + case SECTION: + //error + break; + } + + return 0; +} + +/** \brief Create a 1MB Section + + \param [in] ttb Translation table base address + \param [in] base_address Section base address + \param [in] count Number of sections to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1) +{ + uint32_t offset; + uint32_t entry; + uint32_t i; + + offset = base_address >> 20; + entry = (base_address & 0xFFF00000) | descriptor_l1; + + //4 bytes aligned + ttb = ttb + offset; + + for (i = 0; i < count; i++ ) + { + //4 bytes aligned + *ttb++ = entry; + entry += OFFSET_1M; + } +} + +/** \brief Create a 4k page entry + + \param [in] ttb L1 table base address + \param [in] base_address 4k base address + \param [in] count Number of 4k pages to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + \param [in] ttb_l2 L2 table base address + \param [in] descriptor_l2 L2 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) +{ + + uint32_t offset, offset2; + uint32_t entry, entry2; + uint32_t i; + + offset = base_address >> 20; + entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; + + //4 bytes aligned + ttb += offset; + //create l1_entry + *ttb = entry; + + offset2 = (base_address & 0xff000) >> 12; + ttb_l2 += offset2; + entry2 = (base_address & 0xFFFFF000) | descriptor_l2; + for (i = 0; i < count; i++ ) + { + //4 bytes aligned + *ttb_l2++ = entry2; + entry2 += OFFSET_4K; + } +} + +/** \brief Create a 64k page entry + + \param [in] ttb L1 table base address + \param [in] base_address 64k base address + \param [in] count Number of 64k pages to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + \param [in] ttb_l2 L2 table base address + \param [in] descriptor_l2 L2 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) +{ + uint32_t offset, offset2; + uint32_t entry, entry2; + uint32_t i,j; + + + offset = base_address >> 20; + entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; + + //4 bytes aligned + ttb += offset; + //create l1_entry + *ttb = entry; + + offset2 = (base_address & 0xff000) >> 12; + ttb_l2 += offset2; + entry2 = (base_address & 0xFFFF0000) | descriptor_l2; + for (i = 0; i < count; i++ ) + { + //create 16 entries + for (j = 0; j < 16; j++) + { + //4 bytes aligned + *ttb_l2++ = entry2; + } + entry2 += OFFSET_64K; + } +} + +/** \brief Enable MMU +*/ +__STATIC_INLINE void MMU_Enable(void) +{ + // Set M bit 0 to enable the MMU + // Set AFE bit to enable simplified access permissions model + // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking + __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29)); + __ISB(); +} + +/** \brief Disable MMU +*/ +__STATIC_INLINE void MMU_Disable(void) +{ + // Clear M bit 0 to disable the MMU + __set_SCTLR( __get_SCTLR() & ~1); + __ISB(); +} + +/** \brief Invalidate entire unified TLB +*/ + +__STATIC_INLINE void MMU_InvalidateTLB(void) +{ + __set_TLBIALL(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new state +} + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_base.h b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_base.h index bf11b7346..5e9cbe660 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_base.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_base.h @@ -14,8 +14,8 @@ #ifndef _HAL_BASE_H_ #define _HAL_BASE_H_ -#include "stdint.h" -#include "hal_def.h" +#include "hal_conf.h" +#include "hal_driver.h" #include "hal_debug.h" /***************************** MACRO Definition ******************************/ @@ -46,7 +46,8 @@ typedef enum { * @{ */ - +HAL_Status HAL_Init(void); +HAL_Status HAL_DeInit(void); HAL_Status HAL_InitTick(uint32_t tickPriority); HAL_Status HAL_IncTick(void); uint32_t HAL_GetTick(void); @@ -61,6 +62,10 @@ HAL_Status HAL_SystemCoreClockUpdate(uint32_t hz, eHAL_systickClkSource clkSourc uint64_t HAL_DivU64Rem(uint64_t numerator, uint32_t denominator, uint32_t *pRemainder); uint64_t HAL_GetSysTimerCount(void); +void HAL_CPU_EnterIdle(void); +#if defined(HAL_CPU_USAGE_ENABLED) +uint32_t HAL_GetCPUUsage(void); +#endif /** @} */ @@ -75,7 +80,7 @@ uint64_t HAL_GetSysTimerCount(void); * @param denominator * @return uint64_t result */ -static inline uint64_t HAL_DivU64(uint64_t numerator, uint32_t denominator) +__STATIC_INLINE uint64_t HAL_DivU64(uint64_t numerator, uint32_t denominator) { return HAL_DivU64Rem(numerator, denominator, NULL); } @@ -86,7 +91,7 @@ static inline uint64_t HAL_DivU64(uint64_t numerator, uint32_t denominator) * @param denominator * @return uint32_t result rounded to nearest integer */ -static inline uint32_t HAL_DivRoundClosest(uint32_t numerator, uint32_t denominator) +__STATIC_INLINE uint32_t HAL_DivRoundClosest(uint32_t numerator, uint32_t denominator) { return (numerator + (denominator / 2)) / denominator; } diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_bsp.h b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_bsp.h index 7116a5bb7..7ab0da026 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_bsp.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_bsp.h @@ -11,11 +11,64 @@ /***************************** MACRO Definition ******************************/ /***************************** Structure Definition **************************/ +#ifdef HAL_PL330_MODULE_ENABLED +extern struct HAL_PL330_DEV g_pl330Dev0; +extern struct HAL_PL330_DEV g_pl330Dev1; +#endif -#define SYS_TIMER TIMER5 +#ifdef HAL_SPI_MODULE_ENABLED +extern const struct HAL_SPI_DEV g_spi0Dev; +extern const struct HAL_SPI_DEV g_spi1Dev; +extern const struct HAL_SPI_DEV g_spi2Dev; +extern const struct HAL_SPI_DEV g_spi3Dev; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +extern const struct HAL_UART_DEV g_uart0Dev; +extern const struct HAL_UART_DEV g_uart1Dev; +extern const struct HAL_UART_DEV g_uart2Dev; +extern const struct HAL_UART_DEV g_uart3Dev; +extern const struct HAL_UART_DEV g_uart4Dev; +extern const struct HAL_UART_DEV g_uart5Dev; +extern const struct HAL_UART_DEV g_uart6Dev; +extern const struct HAL_UART_DEV g_uart7Dev; +extern const struct HAL_UART_DEV g_uart8Dev; +extern const struct HAL_UART_DEV g_uart9Dev; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +extern const struct HAL_I2C_DEV g_i2c0Dev; +extern const struct HAL_I2C_DEV g_i2c1Dev; +extern const struct HAL_I2C_DEV g_i2c2Dev; +extern const struct HAL_I2C_DEV g_i2c3Dev; +extern const struct HAL_I2C_DEV g_i2c4Dev; +extern const struct HAL_I2C_DEV g_i2c5Dev; +#endif + +#ifdef HAL_FSPI_MODULE_ENABLED +extern struct HAL_FSPI_HOST g_fspi0Dev; +#endif +#ifdef HAL_CANFD_MODULE_ENABLED +extern const struct HAL_CANFD_DEV g_can0Dev; +extern const struct HAL_CANFD_DEV g_can1Dev; +extern const struct HAL_CANFD_DEV g_can2Dev; +#endif + +#ifdef HAL_GMAC_MODULE_ENABLED extern const struct HAL_GMAC_DEV g_gmac0Dev; extern const struct HAL_GMAC_DEV g_gmac1Dev; +#endif +#ifdef HAL_PCIE_MODULE_ENABLED +extern struct HAL_PCIE_DEV g_pcieDev; +#endif + +#ifdef HAL_PWM_MODULE_ENABLED +extern const struct HAL_PWM_DEV g_pwm0Dev; +extern const struct HAL_PWM_DEV g_pwm1Dev; +extern const struct HAL_PWM_DEV g_pwm2Dev; +extern const struct HAL_PWM_DEV g_pwm3Dev; +#endif /***************************** Function Declare ******************************/ void BSP_Init(void); diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_conf.h b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_conf.h new file mode 100644 index 000000000..ed06d25d9 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_conf.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + + +#ifndef _HAL_CONF_H_ +#define _HAL_CONF_H_ + +/* HAL CPU config */ +#define SOC_RK3568 +#define HAL_AP_CORE +#define SYS_TIMER TIMER5 /* System timer designation (RK TIMER) */ + +/* HAL Driver Config */ +// #define HAL_CACHE_ECC_MODULE_ENABLED +// #define HAL_CPU_TOPOLOGY_MODULE_ENABLED +#define HAL_CRU_MODULE_ENABLED +#define HAL_DCACHE_MODULE_ENABLED +// #define HAL_DDR_ECC_MODULE_ENABLED +// #define HAL_FSPI_MODULE_ENABLED +// #define HAL_GIC_MODULE_ENABLED +#define HAL_GMAC_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +// #define HAL_GPIO_IRQ_GROUP_MODULE_ENABLED +// #define HAL_SPINLOCK_MODULE_ENABLED +// #define HAL_HWSPINLOCK_MODULE_ENABLED +// #define HAL_I2C_MODULE_ENABLED +// #define HAL_IRQ_HANDLER_MODULE_ENABLED +// #define HAL_MBOX_MODULE_ENABLED +// #define HAL_PCIE_MODULE_ENABLED +#define HAL_PINCTRL_MODULE_ENABLED +// #define HAL_PL330_MODULE_ENABLED +// #define HAL_PWM_MODULE_ENABLED +// #define HAL_SARADC_MODULE_ENABLED +// #define HAL_SMCCC_MODULE_ENABLED +// #define HAL_SNOR_MODULE_ENABLED +// #define HAL_SPI_MODULE_ENABLED +#define HAL_TIMER_MODULE_ENABLED +// #define HAL_TSADC_MODULE_ENABLED +// #define HAL_UART_MODULE_ENABLED +// #define HAL_WDT_MODULE_ENABLED +// #define HAL_CANFD_MODULE_ENABLED + +/* HAL_DBG SUB CONFIG */ +#define HAL_DBG_USING_LIBC_PRINTF +#define HAL_DBG_ON +#define HAL_DBG_INFO_ON +#define HAL_DBG_WRN_ON +#define HAL_DBG_ERR_ON +#define HAL_ASSERT_ON + +#ifdef HAL_SNOR_MODULE_ENABLED +#define HAL_SNOR_FSPI_HOST +#endif + +#ifdef HAL_GIC_MODULE_ENABLED +#define HAL_GIC_AMP_FEATURE_ENABLED +#define HAL_GIC_PREEMPT_FEATURE_ENABLED +//#define HAL_GIC_WAIT_LINUX_INIT_ENABLED +#endif + +#ifdef HAL_GPIO_MODULE_ENABLED +#define HAL_GPIO_IRQ_DISPATCH_FEATURE_ENABLED +#endif + +#ifdef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED +#define HAL_GPIO_IRQ_GROUP_PRIO_LEVEL_MAX (3) +#endif + +#endif diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_cru.h b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_cru.h index bb1a65baa..b22809b81 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_cru.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_cru.h @@ -3,6 +3,9 @@ * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. */ +#include "hal_conf.h" + +#ifdef HAL_CRU_MODULE_ENABLED /** @addtogroup RK_HAL_Driver * @{ @@ -471,4 +474,4 @@ void HAL_CRU_AsEnable(uint8_t ch, uint8_t en); /** @} */ - +#endif /* HAL_CRU_MODULE_ENABLED */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_debug.h b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_debug.h index bce5fc442..a4e018d2d 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_debug.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_debug.h @@ -6,8 +6,6 @@ #ifndef _HAL_DEBUG_H_ #define _HAL_DEBUG_H_ -#include "hal_def.h" -#include "libserial.h" /** @addtogroup RK_HAL_Driver * @{ */ @@ -22,8 +20,19 @@ //#define HAL_DBG_USING_RTT_SERIAL //#define HAL_DBG_USING_LIBC_PRINTF //#define HAL_DBG_USING_HAL_PRINTF +#ifdef HAL_DBG_USING_RTT_SERIAL +#include +#include +#define HAL_SYSLOG rt_kprintf +#elif defined(HAL_DBG_USING_LIBC_PRINTF) #define HAL_SYSLOG printf +#elif defined(HAL_DBG_USING_HAL_PRINTF) +#define HAL_SYSLOG HAL_DBG_Printf +#ifndef HAL_PRINTF_BUF_SIZE +#define HAL_PRINTF_BUF_SIZE 128 +#endif +#endif /** @defgroup DEBUG_Exported_Definition_Group1 Basic Definition * @{ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_def.h b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_def.h index bd60d925e..f61871607 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_def.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_def.h @@ -14,7 +14,7 @@ #ifndef _HAL_DEF_H_ #define _HAL_DEF_H_ -// #include +#include "libserial.h" #include #include #include diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_driver.h b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_driver.h new file mode 100644 index 000000000..e408b3f76 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_driver.h @@ -0,0 +1,282 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2018-2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef _HAL_DRIVER_H_ +#define _HAL_DRIVER_H_ + +#include "hal_pm.h" + +#ifdef HAL_ACDCDIG_MODULE_ENABLED +#include "hal_acdcdig.h" +#endif + +#ifdef HAL_ACODEC_MODULE_ENABLED +#include "hal_acodec.h" +#endif + +#ifdef HAL_ARCHTIMER_MODULE_ENABLED +#include "hal_archtimer.h" +#endif + +#ifdef HAL_AUDIOPWM_MODULE_ENABLED +#include "hal_audiopwm.h" +#endif + +#include "hal_cache.h" + +#ifdef HAL_BUFMGR_MODULE_ENABLED +#include "hal_bufmgr.h" +#endif + +#ifdef HAL_CANFD_MODULE_ENABLED +#include "hal_canfd.h" +#endif + +#ifdef HAL_CKCAL_MODULE_ENABLED +#include "hal_ckcal.h" +#endif + +#ifdef HAL_CACHE_ECC_MODULE_ENABLED +#include "hal_cache_ecc.h" +#endif + +#ifdef HAL_CPU_TOPOLOGY_MODULE_ENABLED +#include "hal_cpu_topology.h" +#endif + +#ifdef HAL_CRU_MODULE_ENABLED +#include "hal_cru.h" +#endif + +#ifdef HAL_CRYPTO_MODULE_ENABLED +#include "hal_crypto.h" +#endif + +#ifdef HAL_DSI_MODULE_ENABLED +#include "hal_display.h" +#include "hal_dsi.h" +#endif + +#ifdef HAL_DEMO_MODULE_ENABLED +#include "hal_demo.h" +#endif + +#ifdef HAL_DDR_ECC_MODULE_ENABLED +#include "hal_ddr_ecc.h" +#endif + +#ifdef HAL_DSP_MODULE_ENABLED +#include "hal_dsp.h" +#endif + +// #include "hal_dma.h" + +#ifdef HAL_DWDMA_MODULE_ENABLED +#include "hal_dwdma.h" +#endif + +#ifdef HAL_EFUSE_MODULE_ENABLED +#include "hal_efuse.h" +#endif + +#if defined(HAL_GMAC_MODULE_ENABLED) || defined(HAL_GMAC1000_MODULE_ENABLED) +#include "hal_gmac.h" +#endif + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "hal_gpio.h" +#endif + +#ifdef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED +#include "hal_gpio_irq_group.h" +#endif + +#ifdef HAL_PINCTRL_MODULE_ENABLED +#include "hal_pinctrl.h" +#endif + +#if defined(HAL_HCD_MODULE_ENABLED) || defined(HAL_PCD_MODULE_ENABLED) +#include "hal_usb_core.h" +#include "hal_usb_phy.h" +#endif + +#if defined(HAL_EHCI_MODULE_ENABLED) || defined(HAL_OHCI_MODULE_ENABLED) +#include "hal_usbh.h" +#endif + +#ifdef HAL_HCD_MODULE_ENABLED +#include "hal_hcd.h" +#endif + +#ifdef HAL_HWSPINLOCK_MODULE_ENABLED +#include "hal_hwspinlock.h" +#endif + +#ifdef HAL_HYPERPSRAM_MODULE_ENABLED +#include "hal_hyperpsram.h" +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +#include "hal_i2c.h" +#endif + +#ifdef HAL_I2S_MODULE_ENABLED +#include "hal_i2s.h" +#endif + +#ifdef HAL_I2STDM_MODULE_ENABLED +#include "hal_i2stdm.h" +#endif + +#ifdef HAL_INTC_MODULE_ENABLED +#include "hal_intc.h" +#endif + +#ifdef HAL_INTMUX_MODULE_ENABLED +#include "hal_intmux.h" +#endif + +#ifdef HAL_IRQ_HANDLER_MODULE_ENABLED +#include "hal_irq_handler.h" +#endif + +#ifdef HAL_GIC_MODULE_ENABLED +#include "hal_gic.h" +#endif + +#ifdef HAL_MBOX_MODULE_ENABLED +#include "hal_mbox.h" +#endif + +#ifdef HAL_NVIC_MODULE_ENABLED +#include "hal_nvic.h" +#endif + +#ifdef HAL_PCD_MODULE_ENABLED +#include "hal_pcd.h" +#endif + +#ifdef HAL_PCIE_MODULE_ENABLED +#include "hal_pci_core.h" +#include "hal_pcie_dma.h" +#include "hal_pcie.h" +#endif + +#ifdef HAL_PDM_MODULE_ENABLED +#include "hal_pdm.h" +#endif + +#ifdef HAL_PL330_MODULE_ENABLED +#include "hal_pl330.h" +#endif + +#ifdef HAL_PMU_MODULE_ENABLED +#include "hal_pd.h" +#endif + +#ifdef HAL_PVTM_MODULE_ENABLED +#include "hal_pvtm.h" +#endif + +#ifdef HAL_PWM_MODULE_ENABLED +#include "hal_pwm.h" +#endif + +// #include "hal_pwr.h" + +#ifdef HAL_RISCVIC_MODULE_ENABLED +#include "hal_riscvic.h" +#endif + +#ifdef HAL_SDIO_MODULE_ENABLED +#include "hal_sdio.h" +#endif + +#ifdef HAL_SNOR_MODULE_ENABLED +#include "hal_spi_mem.h" +#include "hal_snor.h" +#endif + +#ifdef HAL_SFC_MODULE_ENABLED +#include "hal_sfc.h" +#endif + +#ifdef HAL_SPINAND_MODULE_ENABLED +#include "hal_spi_mem.h" +#include "hal_spinand.h" +#endif + +#ifdef HAL_SPINLOCK_MODULE_ENABLED +#include "hal_spinlock.h" +#endif + +#ifdef HAL_SYSTICK_MODULE_ENABLED +#include "hal_systick.h" +#endif + +#ifdef HAL_FSPI_MODULE_ENABLED +#include "hal_spi_mem.h" +#include "hal_fspi.h" +#endif + +#ifdef HAL_QPIPSRAM_MODULE_ENABLED +#include "hal_spi_mem.h" +#include "hal_qpipsram.h" +#endif + +#ifdef HAL_TOUCHKEY_MODULE_ENABLED +#include "hal_touchkey.h" +#endif + +#ifdef HAL_TSADC_MODULE_ENABLED +#include "hal_tsadc.h" +#endif + +#ifdef HAL_SARADC_MODULE_ENABLED +#include "hal_saradc.h" +#endif + +#ifdef HAL_SMCCC_MODULE_ENABLED +#include "hal_smccc.h" +#endif + +#ifdef HAL_KEYCTRL_MODULE_ENABLED +#include "hal_keyctrl.h" +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +#include "hal_spi.h" +#endif + +#ifdef HAL_SPI2APB_MODULE_ENABLED +#include "hal_spi2apb.h" +#endif + +#ifdef HAL_TIMER_MODULE_ENABLED +#include "hal_timer.h" +#endif + +#ifdef HAL_UART_MODULE_ENABLED +#include "hal_uart.h" +#endif + +#ifdef HAL_VAD_MODULE_ENABLED +#include "hal_vad.h" +#endif + +#ifdef HAL_VICAP_MODULE_ENABLED +#include "hal_vicap.h" +#endif + +#ifdef HAL_VOP_MODULE_ENABLED +#include "hal_display.h" +#include "hal_vop.h" +#endif + +#ifdef HAL_WDT_MODULE_ENABLED +#include "hal_wdt.h" +#endif + +#endif diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_gmac.h b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_gmac.h index 6bfdc5833..c7fbfb38c 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_gmac.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_gmac.h @@ -3,6 +3,10 @@ * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. */ +#include "hal_conf.h" + +#if (defined(HAL_GMAC_MODULE_ENABLED) || defined(HAL_GMAC1000_MODULE_ENABLED)) + /** @addtogroup RK_HAL_Driver * @{ */ @@ -274,87 +278,6 @@ struct GMAC_HANDLE { uint32_t rxSize; /**< Rx descriptor size */ }; - -#define PM_RUNTIME_TYPE_MUTI_SFT (3) -#define PM_RUNTIME_PER_TYPE_NUM (8) - -#define PM_RUNTIME_TYPE_TO_FIRST_ID(type) ((type) << PM_RUNTIME_TYPE_MUTI_SFT) -#define PM_RUNTIME_ID_TO_TYPE(id) ((id) >> PM_RUNTIME_TYPE_MUTI_SFT) -#define PM_RUNTIME_ID_TO_TYPE_OFFSET(id) ((id) % PM_RUNTIME_PER_TYPE_NUM) -#define PM_RUNTIME_ID_TYPE_BIT_MSK(id) HAL_BIT(((id) % PM_RUNTIME_PER_TYPE_NUM)) - -#define PM_DISPLAY_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_DISPLAY]) -#define PM_UART_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_UART]) -#define PM_I2C_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_I2C]) -#define PM_INTF_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_INTF]) -#define PM_HS_INTF_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_HS_INTF]) -#define PM_SPI_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_SPI]) -#define PM_CIF_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_CIF]) - -/* suspend config id */ -#define PM_SLEEP_MODE_CONFIG 0x01 -#define PM_SLEEP_WAKEUP_SOURCE 0x02 - -enum { - PM_RUNTIME_TYPE_INTF = 0, /**< normal interface */ - PM_RUNTIME_TYPE_DISPLAY, - PM_RUNTIME_TYPE_AUDIO, - PM_RUNTIME_TYPE_HS_INTF, /**< high speed interface */ - PM_RUNTIME_TYPE_STORAGE, - PM_RUNTIME_TYPE_UART, - PM_RUNTIME_TYPE_I2C, - PM_RUNTIME_TYPE_SPI, - PM_RUNTIME_TYPE_CIF, - PM_RUNTIME_TYPE_DEVICE, - PM_RUNTIME_TYPE_END, -}; - -typedef enum { - PM_RUNTIME_IDLE_ONLY = 0, - PM_RUNTIME_IDLE_NORMAL, - PM_RUNTIME_IDLE_DEEP, - PM_RUNTIME_IDLE_DEEP1, - PM_RUNTIME_IDLE_DEEP2, -} ePM_RUNTIME_idleMode; - -typedef enum { - PM_RUNTIME_ID_INTF_INVLD = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_INTF), /**< the id = 0, is means invalid */ - PM_RUNTIME_ID_SPI_APB, - PM_RUNTIME_ID_VOP = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_DISPLAY), - PM_RUNTIME_ID_MIPI, - - PM_RUNTIME_ID_I2S = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_AUDIO), - PM_RUNTIME_ID_I2S1, - PM_RUNTIME_ID_I2S2, - PM_RUNTIME_ID_ADC, - PM_RUNTIME_ID_DMA, - - PM_RUNTIME_ID_USB = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_HS_INTF), - PM_RUNTIME_ID_SDIO, - - PM_RUNTIME_ID_UART0 = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_UART), - PM_RUNTIME_ID_UART1, - PM_RUNTIME_ID_UART2, - PM_RUNTIME_ID_UART3, - PM_RUNTIME_ID_UART4, - PM_RUNTIME_ID_UART5, - PM_RUNTIME_ID_UART6, - PM_RUNTIME_ID_UART7, - PM_RUNTIME_ID_UART8, - PM_RUNTIME_ID_UART9, - - PM_RUNTIME_ID_I2C0 = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_I2C), - PM_RUNTIME_ID_I2C1, - PM_RUNTIME_ID_I2C2, - PM_RUNTIME_ID_I2C3, - PM_RUNTIME_ID_I2C4, - PM_RUNTIME_ID_I2C5, - - PM_RUNTIME_ID_SPI = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_SPI), - PM_RUNTIME_ID_CIF = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_CIF), - - PM_RUNTIME_ID_END, -} ePM_RUNTIME_ID; /** * @brief GMAC HW Information Definition */ @@ -423,3 +346,5 @@ void HAL_GMAC_SetExtclkSrc(struct GMAC_HANDLE *pGMAC, bool extClk); /** @} */ /** @} */ + +#endif /* HAL_GMAC_MODULE_ENABLED */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_gpio.h b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_gpio.h index 7a0cf8ed9..ec0a0a39f 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_gpio.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_gpio.h @@ -3,6 +3,7 @@ * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. */ +#include "hal_conf.h" /** @addtogroup RK_HAL_Driver * @{ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_list.h b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_list.h index a71fc343e..4e3678ef0 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_list.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_list.h @@ -45,7 +45,7 @@ typedef struct HAL_LIST_NODE HAL_LIST; * @brief initialize a list * @param l: list to be initialized */ -static inline void HAL_LIST_Init(HAL_LIST *l) +__STATIC_INLINE void HAL_LIST_Init(HAL_LIST *l) { l->next = l->prev = l; } @@ -55,7 +55,7 @@ static inline void HAL_LIST_Init(HAL_LIST *l) * @param l: list to insert it * @param n: new node to be inserted */ -static inline void HAL_LIST_InsertAfter(HAL_LIST *l, HAL_LIST *n) +__STATIC_INLINE void HAL_LIST_InsertAfter(HAL_LIST *l, HAL_LIST *n) { l->next->prev = n; n->next = l->next; @@ -69,7 +69,7 @@ static inline void HAL_LIST_InsertAfter(HAL_LIST *l, HAL_LIST *n) * @param n: new node to be inserted * @param l: list to insert it */ -static inline void HAL_LIST_InsertBefore(HAL_LIST *l, HAL_LIST *n) +__STATIC_INLINE void HAL_LIST_InsertBefore(HAL_LIST *l, HAL_LIST *n) { l->prev->next = n; n->prev = l->prev; @@ -82,7 +82,7 @@ static inline void HAL_LIST_InsertBefore(HAL_LIST *l, HAL_LIST *n) * @brief remove node from list. * @param n: the node to remove from the list. */ -static inline void HAL_LIST_Remove(HAL_LIST *n) +__STATIC_INLINE void HAL_LIST_Remove(HAL_LIST *n) { n->next->prev = n->prev; n->prev->next = n->next; @@ -94,7 +94,7 @@ static inline void HAL_LIST_Remove(HAL_LIST *n) * @brief tests whether a list is empty * @param l: the list to test. */ -static inline int HAL_LIST_IsEmpty(const HAL_LIST *l) +__STATIC_INLINE int HAL_LIST_IsEmpty(const HAL_LIST *l) { return l->next == l; } @@ -103,7 +103,7 @@ static inline int HAL_LIST_IsEmpty(const HAL_LIST *l) * @brief get the list length * @param l: the list to get. */ -static inline uint32_t HAL_LIST_Len(const HAL_LIST *l) +__STATIC_INLINE uint32_t HAL_LIST_Len(const HAL_LIST *l) { uint32_t len = 0; const HAL_LIST *p = l; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_pinctrl.h b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_pinctrl.h index 98f25bbe8..10e852ca0 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_pinctrl.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_pinctrl.h @@ -3,7 +3,7 @@ * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. */ - +#include "hal_conf.h" /** @addtogroup RK_HAL_Driver * @{ @@ -470,14 +470,27 @@ typedef enum { PIN_CONFIG_MUX_FUNC15 = (0xf << SHIFT_MUX | FLAG_MUX), PIN_CONFIG_MUX_DEFAULT = PIN_CONFIG_MUX_FUNC0, - +#if defined(SOC_SWALLOW) PIN_CONFIG_PUL_NORMAL = (0x1 << SHIFT_PUL | FLAG_PUL), PIN_CONFIG_PUL_DEFAULT = (0x0 << SHIFT_PUL | FLAG_PUL), PIN_CONFIG_PUL_UP = PIN_CONFIG_PUL_DEFAULT, PIN_CONFIG_PUL_DOWN = PIN_CONFIG_PUL_DEFAULT, PIN_CONFIG_PUL_KEEP = PIN_CONFIG_PUL_DEFAULT, +#elif defined(SOC_RK3588) + PIN_CONFIG_PUL_NORMAL = (0x0 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_DOWN = (0x1 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_KEEP = (0x2 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_UP = (0x3 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_DEFAULT = PIN_CONFIG_PUL_NORMAL, +#else + PIN_CONFIG_PUL_NORMAL = (0x0 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_UP = (0x1 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_DOWN = (0x2 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_KEEP = (0x3 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_DEFAULT = PIN_CONFIG_PUL_NORMAL, +#endif - +#if defined(SOC_RK3568) || defined(SOC_RV1106) || defined(SOC_RK3562) PIN_CONFIG_DRV_LEVEL0 = (0x1 << SHIFT_DRV | FLAG_DRV), PIN_CONFIG_DRV_LEVEL1 = (0x3 << SHIFT_DRV | FLAG_DRV), PIN_CONFIG_DRV_LEVEL2 = (0x7 << SHIFT_DRV | FLAG_DRV), @@ -485,14 +498,50 @@ typedef enum { PIN_CONFIG_DRV_LEVEL4 = (0x1f << SHIFT_DRV | FLAG_DRV), PIN_CONFIG_DRV_LEVEL5 = (0x3f << SHIFT_DRV | FLAG_DRV), PIN_CONFIG_DRV_LEVEL_DEFAULT = PIN_CONFIG_DRV_LEVEL2, +#elif defined(SOC_RK3588) + PIN_CONFIG_DRV_LEVEL0 = (0x0 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL1 = (0x2 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL2 = (0x1 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL3 = (0x3 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL_DEFAULT = PIN_CONFIG_DRV_LEVEL2, +#else + PIN_CONFIG_DRV_LEVEL0 = (0x0 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL1 = (0x1 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL2 = (0x2 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL3 = (0x3 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL4 = (0x4 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL5 = (0x5 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL6 = (0x6 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL7 = (0x7 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL_DEFAULT = PIN_CONFIG_DRV_LEVEL2, +#endif +#if defined(SOC_RV1106) + PIN_CONFIG_SRT_SLOW = (0x0 << SHIFT_SRT | FLAG_SRT), + PIN_CONFIG_SRT_FAST = (0x3 << SHIFT_SRT | FLAG_SRT), + PIN_CONFIG_SRT_DEFAULT = PIN_CONFIG_SRT_FAST, +#elif defined(SOC_RK3562) + PIN_CONFIG_SRT_LEVEL0 = (0x0 << SHIFT_SRT | FLAG_SRT), + PIN_CONFIG_SRT_LEVEL1 = (0x1 << SHIFT_SRT | FLAG_SRT), + PIN_CONFIG_SRT_LEVEL2 = (0x2 << SHIFT_SRT | FLAG_SRT), + PIN_CONFIG_SRT_LEVEL3 = (0x3 << SHIFT_SRT | FLAG_SRT), + PIN_CONFIG_SRT_DEFAULT = PIN_CONFIG_SRT_LEVEL3, +#else PIN_CONFIG_SRT_SLOW = (0x0 << SHIFT_SRT | FLAG_SRT), PIN_CONFIG_SRT_FAST = (0x1 << SHIFT_SRT | FLAG_SRT), PIN_CONFIG_SRT_DEFAULT = PIN_CONFIG_SRT_SLOW, +#endif +#if defined(SOC_RK3562) + PIN_CONFIG_SMT_DISABLE_ALL = (0x0 << SHIFT_SMT | FLAG_SMT), + PIN_CONFIG_SMT_DISABLE_IE = (0x1 << SHIFT_SMT | FLAG_SMT), + PIN_CONFIG_SMT_ENABLE_ALL = (0x2 << SHIFT_SMT | FLAG_SMT), + PIN_CONFIG_SMT_DEFAULT = PIN_CONFIG_SMT_DISABLE_IE, +#else PIN_CONFIG_SMT_DISABLE = (0x0 << SHIFT_SMT | FLAG_SMT), PIN_CONFIG_SMT_ENABLE = (0x1 << SHIFT_SMT | FLAG_SMT), PIN_CONFIG_SMT_DEFAULT = PIN_CONFIG_SMT_DISABLE, +#endif PIN_CONFIG_MAX = 0xFFFFFFFFU, } ePINCTRL_configParam; diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_pm.h b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_pm.h new file mode 100644 index 000000000..5ce30c909 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_pm.h @@ -0,0 +1,200 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup PM + * @{ + */ + +#ifndef _HAL_PM_H_ +#define _HAL_PM_H_ + +#include "hal_def.h" + +/***************************** MACRO Definition ******************************/ +/** @defgroup DEMO_Exported_Definition_Group1 Basic Definition + * @{ + */ + +#define PM_RUNTIME_TYPE_MUTI_SFT (3) +#define PM_RUNTIME_PER_TYPE_NUM (8) + +#define PM_RUNTIME_TYPE_TO_FIRST_ID(type) ((type) << PM_RUNTIME_TYPE_MUTI_SFT) +#define PM_RUNTIME_ID_TO_TYPE(id) ((id) >> PM_RUNTIME_TYPE_MUTI_SFT) +#define PM_RUNTIME_ID_TO_TYPE_OFFSET(id) ((id) % PM_RUNTIME_PER_TYPE_NUM) +#define PM_RUNTIME_ID_TYPE_BIT_MSK(id) HAL_BIT(((id) % PM_RUNTIME_PER_TYPE_NUM)) + +#define PM_DISPLAY_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_DISPLAY]) +#define PM_UART_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_UART]) +#define PM_I2C_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_I2C]) +#define PM_INTF_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_INTF]) +#define PM_HS_INTF_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_HS_INTF]) +#define PM_SPI_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_SPI]) +#define PM_CIF_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_CIF]) + +/* suspend config id */ +#define PM_SLEEP_MODE_CONFIG 0x01 +#define PM_SLEEP_WAKEUP_SOURCE 0x02 + +enum { + PM_RUNTIME_TYPE_INTF = 0, /**< normal interface */ + PM_RUNTIME_TYPE_DISPLAY, + PM_RUNTIME_TYPE_AUDIO, + PM_RUNTIME_TYPE_HS_INTF, /**< high speed interface */ + PM_RUNTIME_TYPE_STORAGE, + PM_RUNTIME_TYPE_UART, + PM_RUNTIME_TYPE_I2C, + PM_RUNTIME_TYPE_SPI, + PM_RUNTIME_TYPE_CIF, + PM_RUNTIME_TYPE_DEVICE, + PM_RUNTIME_TYPE_END, +}; + +typedef enum { + PM_RUNTIME_IDLE_ONLY = 0, + PM_RUNTIME_IDLE_NORMAL, + PM_RUNTIME_IDLE_DEEP, + PM_RUNTIME_IDLE_DEEP1, + PM_RUNTIME_IDLE_DEEP2, +} ePM_RUNTIME_idleMode; + +typedef enum { + PM_RUNTIME_ID_INTF_INVLD = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_INTF), /**< the id = 0, is means invalid */ + PM_RUNTIME_ID_SPI_APB, + PM_RUNTIME_ID_VOP = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_DISPLAY), + PM_RUNTIME_ID_MIPI, + + PM_RUNTIME_ID_I2S = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_AUDIO), + PM_RUNTIME_ID_I2S1, + PM_RUNTIME_ID_I2S2, + PM_RUNTIME_ID_ADC, + PM_RUNTIME_ID_DMA, + + PM_RUNTIME_ID_USB = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_HS_INTF), + PM_RUNTIME_ID_SDIO, + + PM_RUNTIME_ID_UART0 = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_UART), + PM_RUNTIME_ID_UART1, + PM_RUNTIME_ID_UART2, + PM_RUNTIME_ID_UART3, + PM_RUNTIME_ID_UART4, + PM_RUNTIME_ID_UART5, + PM_RUNTIME_ID_UART6, + PM_RUNTIME_ID_UART7, + PM_RUNTIME_ID_UART8, + PM_RUNTIME_ID_UART9, + + PM_RUNTIME_ID_I2C0 = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_I2C), + PM_RUNTIME_ID_I2C1, + PM_RUNTIME_ID_I2C2, + PM_RUNTIME_ID_I2C3, + PM_RUNTIME_ID_I2C4, + PM_RUNTIME_ID_I2C5, + + PM_RUNTIME_ID_SPI = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_SPI), + PM_RUNTIME_ID_CIF = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_CIF), + + PM_RUNTIME_ID_END, +} ePM_RUNTIME_ID; + +/***************************** Structure Definition **************************/ +struct PM_RUNTIME_INFO { + uint8_t bits[PM_RUNTIME_TYPE_END]; +}; + +#ifdef HAL_PM_SLEEP_MODULE_ENABLED +struct PM_SUSPEND_INFO { + union { + struct { + uint32_t uartChannel : 4; /*!< bit: 0.. 3 uart debug channel num */ + uint32_t uartValid : 1; /*!< bit: 4 uart channel valid flag */ + uint32_t _reserved : 27; /*!< bit: 5..31 Reserved */ + } flag; + uint32_t suspendFlag; + }; +}; + +struct SLEEP_CONFIG_DATA { + uint32_t suspendMode; + uint32_t suspendWkupSrc; +}; +#endif + +/** @} */ +/***************************** Function Declare ******************************/ +/** @defgroup PM_Public_Function_Declare Public Function Declare + * @{ + */ +#ifdef HAL_PM_SLEEP_MODULE_ENABLED +/** + * @brief it is the enterpoint for suspend invoked by a os's powermanager implement. + * @param suspendInfo: suspend information for controlling + * @return HAL_Status + */ +int HAL_SYS_Suspend(struct PM_SUSPEND_INFO *suspendInfo); +struct SLEEP_CONFIG_DATA *HAL_SYS_GetSuspendConfig(void); +HAL_Status HAL_SYS_SuspendConfig(uint32_t id, uint32_t data); +#endif + +#ifdef HAL_PM_CPU_SLEEP_MODULE_ENABLED +void HAL_CPU_ArchSuspend(uint32_t *ptr); +void HAL_CPU_ArchResume(void); +void HAL_CPU_DoResume(void); + +void HAL_NVIC_SuspendSave(void); +void HAL_NVIC_ResumeRestore(void); + +void HAL_SCB_SuspendSave(void); +void HAL_SCB_ResumeRestore(void); + +int HAL_CPU_SuspendEnter(uint32_t flag, int (*suspend)(uint32_t)); +void HAL_CPU_SuspendSave(uint32_t *ptr, uint32_t ptrsz, uint32_t sp, uint32_t *ptrSave); +#endif + +#ifdef HAL_PM_RUNTIME_MODULE_ENABLED +HAL_Status HAL_PM_RuntimeRequest(ePM_RUNTIME_ID runtimeId); +HAL_Status HAL_PM_RuntimeRelease(ePM_RUNTIME_ID runtimeId); +const struct PM_RUNTIME_INFO *HAL_PM_RuntimeGetData(void); + +/** + * @brief it is for runtime power manager. + * @param idleMode: the soc pm mode will be config + * @return the mask bits indicate request source. + */ +uint32_t HAL_PM_RuntimeEnter(ePM_RUNTIME_idleMode idleMode); +#endif + +/** + * @brief it is for statting a pm timer . + * @param timeoutCount: the next timeout count + * @param needTimeout: if ture, need to start a timer. + * @return HAL_Status. + */ +HAL_Status HAL_PM_TimerStart(uint64_t timeoutCount, bool needTimeout); + +/** + * @brief it is for stopping a pm timer . + * @return HAL_Status. + */ +HAL_Status HAL_PM_TimerStop(void); + +/** + * @brief it is for getting the sleep time. + * @return the sleep time. + */ +uint64_t HAL_PM_GetTimerCount(void); + +/** @} */ + +#endif + +/** @} */ + +/** @} */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_timer.h b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_timer.h index f6a2586a0..0f815b941 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_timer.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_timer.h @@ -3,8 +3,9 @@ * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. */ +#include "hal_conf.h" - +#ifdef HAL_TIMER_MODULE_ENABLED /** @addtogroup RK_HAL_Driver * @{ @@ -60,3 +61,4 @@ HAL_Status HAL_TIMER_ClrInt(struct TIMER_REG *pReg); /** @} */ +#endif /* HAL_TIMER_MODULE_ENABLED */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/rk3568.h b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/rk3568.h index 38ee4ab13..e7c2c2163 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/rk3568.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/rk3568.h @@ -14,7 +14,6 @@ /* */ /****************************************************************************************/ #ifndef __ASSEMBLY__ -#include "soc.h" /* GRF Register Structure Define */ struct GRF_REG { __IO uint32_t GPIO0A_IOMUX_L; /* Address Offset: 0x0000 */ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/soc.h b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/soc.h index bcadb909e..3933b3709 100644 --- a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/soc.h +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/soc.h @@ -9,6 +9,7 @@ extern "C" { #endif +#include "hal_conf.h" /* IO definitions (access restrictions to peripheral registers) */ #ifdef __cplusplus @@ -263,9 +264,9 @@ typedef enum #error "HAL_AP_CORE and HAL_MCU_CORE only one of them can be enabled" #endif -// #if !defined(HAL_AP_CORE) && !defined(HAL_MCU_CORE) -// #error "Please define HAL_AP_CORE or HAL_MCU_CORE on hal_conf.h" -// #endif +#if !defined(HAL_AP_CORE) && !defined(HAL_MCU_CORE) +#error "Please define HAL_AP_CORE or HAL_MCU_CORE on hal_conf.h" +#endif #ifdef HAL_AP_CORE #define __CORTEX_A 55U /* Cortex-A55 Core */ @@ -279,13 +280,13 @@ typedef enum #define __RISC_V #endif -// #ifndef __ASSEMBLY__ -// #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ -// #ifdef __CORTEX_A -// #include "core_ca.h" -// #endif -// #include "system_rk3568.h" -// #endif /* __ASSEMBLY__ */ +#ifndef __ASSEMBLY__ +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ +#ifdef __CORTEX_A +#include "core_ca.h" +#endif +#include "system_rk3568.h" +#endif /* __ASSEMBLY__ */ #include "rk3568.h" /****************************************************************************************/ diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/system_rk3568.h b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/system_rk3568.h new file mode 100644 index 000000000..87e9c5f08 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/system_rk3568.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef __SYSTEM_RK3568_H_ +#define __SYSTEM_RK3568_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + \brief Setup the system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +extern void DataInit (void); + +#if defined(HAL_AP_CORE) +extern void MMU_CreateTranslationTable(void); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_RK3568_H_ */