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clean code

This commit is contained in:
tuyuyang 2024-07-08 21:06:12 +08:00
parent d1072fd3c2
commit 3e5895d972
6 changed files with 46 additions and 179 deletions
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56
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/boot.S
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@ -31,27 +31,27 @@ _boot_start:
// clear some registers
msr elr_el1, XZR
ldr x0, =stacks_top
mov x1, #MODE_STACK_SIZE
ldr x0, =stacks_top
mov x1, #MODE_STACK_SIZE
// get cpu id, and subtract the offset from the stacks base address
mrs x2, mpidr_el1
and x2, x2, #0xFFF
lsr x2, x2, #8
mov x5, x2
mul x3, x2, x1
sub x0, x0, x3
mov sp, x0
mrs x2, mpidr_el1
and x2, x2, #0xFFF
lsr x2, x2, #8
mov x5, x2
mul x3, x2, x1
sub x0, x0, x3
mov sp, x0
mov x2, #ARM_MODE_EL1_h | DIS_INT
msr spsr_el1, x2
// check cpu id - cpu0 is primary cpu
mrs x2, mpidr_el1
and x2, x2, #0xFFF
lsr x2, x2, #8
mov x5, x2
cmp x5, #0
mrs x2, mpidr_el1
and x2, x2, #0xFFF
lsr x2, x2, #8
mov x5, x2
cmp x5, #0
beq primary_cpu_init
bl bootmain // for secondary cpus, jump to argument function pointer passed in by ROM
@ -60,13 +60,13 @@ _boot_start:
primary_cpu_init:
/* init .bss */
/* clear the .bss section (zero init) */
ldr x1, =boot_start_addr
ldr x2, =boot_end_addr
mov x3, #0
ldr x1, =boot_start_addr
ldr x2, =boot_end_addr
mov x3, #0
1:
cmp x1, x2
stp x3, x3, [x1], #16
b.lt 1b
cmp x1, x2
stp x3, x3, [x1], #16
b.lt 1b
bl bootmain
@ -92,7 +92,7 @@ el2_setup:
/* Populate ID registers. */
mrs x0, midr_el1
mrs x1, mpidr_el1
msr vpidr_el2, x0
msr vpidr_el2, x0
msr vmpidr_el2, x1
/* Disable Coprocessor traps. */
@ -104,16 +104,16 @@ el2_setup:
mov x0, sp
msr sp_el1, x0
mrs x0, sctlr_el1
orr x0, x0, #(1 << 0)
bic x0, x0, #(1 << 1)
orr x0, x0, #(1 << 2)
msr sctlr_el1, x0
mrs x0, sctlr_el1
orr x0, x0, #(1 << 0)
bic x0, x0, #(1 << 1)
orr x0, x0, #(1 << 2)
msr sctlr_el1, x0
/* spsr */
mov x0, #SPSR_EL2_VALUE
msr spsr_el2, x0
msr elr_el2, lr
msr spsr_el2, x0
msr elr_el2, lr
eret
.endfunc

3
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/config.mk
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@ -1,7 +1,6 @@
export CROSS_COMPILE ?= aarch64-none-elf-
export DEVICE = -mtune=cortex-a55 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie
export CFLAGS := $(DEVICE) -Wall -Werror -O0 -g -fno-omit-frame-pointer -fPIC
# export AFLAGS := -c $(DEVICE) -x assembler-with-cpp -D__ASSEMBLY__ -gdwarf-2
export CFLAGS := $(DEVICE) -Wall -Werror -O2 -g -fno-omit-frame-pointer -fPIC
export LFLAGS := $(DEVICE) -Wl,-T -Wl,$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/3568.lds -Wl,--start-group,-lgcc,-lc,--end-group
export CXXFLAGS :=

32
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/smp.c
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@ -49,42 +49,34 @@ Modification:
#define PSCI_CPUON 0xc4000003
struct arm_smccc_res {
unsigned long a0;
unsigned long a1;
unsigned long a2;
unsigned long a3;
unsigned long a0;
unsigned long a1;
unsigned long a2;
unsigned long a3;
};
extern void _boot_start();
extern void __print();
extern void __arm_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2,
unsigned long a3, unsigned long a4, unsigned long a5,
unsigned long a6, unsigned long a7, struct arm_smccc_res *res);
unsigned long a3, unsigned long a4, unsigned long a5,
unsigned long a6, unsigned long a7, struct arm_smccc_res* res);
static struct arm_smccc_res __invoke_sip_fn_smc(unsigned long function_id,
unsigned long arg0,
unsigned long arg1,
unsigned long arg2)
unsigned long arg0,
unsigned long arg1,
unsigned long arg2)
{
struct arm_smccc_res res;
struct arm_smccc_res res;
__arm_smccc_smc(function_id, arg0, arg1, arg2, 0, 0, 0, 0, &res);
return res;
__arm_smccc_smc(function_id, arg0, arg1, arg2, 0, 0, 0, 0, &res);
return res;
}
void cpu_start_secondary(uint8_t cpu_id)
{
//psci_call(PSCI_CPUON, cpu_id, (uintptr_t)&_boot_start, 0);
__invoke_sip_fn_smc(PSCI_CPUON, cpu_id, (uintptr_t)0xa00000, 0);
}
//void psci_call(uint64_t fn, uint8_t cpuid, uint64_t entry, uint64_t ctxid);
// int psci_cpu_on(unsigned long cpuid, unsigned long entry_point)
// {
// __invoke_sip_fn_smc(PSCI_CPUON, cpuid, entry_point, 0);
// }
void start_smp_cache_broadcast(int cpu_id)
{
return;

26
Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a55/l1_cache.c vendored
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@ -157,38 +157,14 @@ void FlushL1Dcache(uintptr_t start, uintptr_t end)
void FlushL1DcacheAll(void)
{
// uint64_t ccsidr_el1; // Cache Size ID
// int num_sets; // number of sets
// int num_ways; // number of ways
// uint32_t wayset; // wayset parameter
// __asm__ __volatile__("mrs %0, ccsidr_el1" : "=r"(ccsidr_el1)); // Read Cache Size ID
// // Fill number of sets and number of ways from ccsidr_el1 register This walues are decremented by 1
// num_sets = ((ccsidr_el1 >> 32) & 0x7FFF) + 1;
// num_ways = ((ccsidr_el1 >> 0) & 0x7FFF) + 1;
// // clean and invalidate all lines (all Sets in all ways)
// for (int way = 0; way < num_ways; way++) {
// for (int set = 0; set < num_sets; set++) {
// wayset = (way << 30) | (set << 5);
// __asm__ __volatile__("dc cisw, %0" : : "r"(wayset));
// }
// }
// // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
// DSB();
__asm_flush_dcache_all();
__asm_flush_l3_dcache();
}
void InvalidateL1IcacheAll()
{
// __asm__ __volatile__("ic iallu\n\t");
// // synchronize context on this processor
// ISB();
__asm_invalidate_icache_all();
__asm_invalidate_l3_icache();
__asm_invalidate_l3_icache();
}
void InvalidateL1Icache(uintptr_t start, uintptr_t end)

43
Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/bootmmu.c
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@ -51,9 +51,9 @@ extern uint64_t kernel_data_begin[];
#define L4_PTE_NORMAL ((0b01) << 2) // Device memory
#define L4_PTE_AF (1 << 10) // Data Access Permissions
#define L4_PTE_PXN (1UL << 53) // Privileged eXecute Never
#define L4_PTE_UXN (1UL << 54) // Unprivileged(user) eXecute Never
#define L4_PTE_XN (PTE_PXN|PTE_UXN) // eXecute Never
#define L4_PTE_PXN (1UL << 53) // Privileged eXecute Never
#define L4_PTE_UXN (1UL << 54) // Unprivileged(user) eXecute Never
#define L4_PTE_XN (PTE_PXN|PTE_UXN) // eXecute Never
#define IDX_MASK (0b111111111)
#define L3_PDE_INDEX(idx) ((idx << LEVEL3_PDE_SHIFT) & L3_IDX_MASK)
@ -86,19 +86,11 @@ static void build_boot_pgdir()
if (cur_mem_paddr >= DEV_PHYMEM_BASE && cur_mem_paddr < DEV_PHYMEM_BASE + DEV_MEM_SIZE) {
boot_dev_l4pgdirs[i][j] = cur_mem_paddr | 0x403;
} else {
// boot_dev_l4pgdirs[i][j] = cur_mem_paddr | 0x713;
boot_dev_l4pgdirs[i][j] = cur_mem_paddr | 0x403;
}
cur_mem_paddr += PAGE_SIZE;
}
// if (cur_mem_paddr >= DEV_PHYMEM_BASE && cur_mem_paddr < DEV_PHYMEM_BASE + DEV_MEM_SIZE) {
// boot_dev_l3pgdir[i] = cur_mem_paddr | 0x401;
// } else {
// boot_dev_l3pgdir[i] = cur_mem_paddr | 0x711;
// }
// cur_mem_paddr += PAGE_SIZE * 0x200;
}
// identical mem
@ -110,7 +102,6 @@ static void build_boot_pgdir()
boot_kern_l3pgdir[i] = (uint64_t)boot_kern_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID;
for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) {
// boot_kern_l4pgdirs[i][j] = cur_mem_paddr | L4_TYPE_PAGE | L4_PTE_NORMAL | L4_PTE_AF;
boot_kern_l4pgdirs[i][j] = cur_mem_paddr | 0x713;
cur_mem_paddr += PAGE_SIZE;
@ -121,7 +112,6 @@ static void build_boot_pgdir()
}
}
#include "log.h"
static void load_boot_pgdir()
{
@ -135,37 +125,10 @@ static void load_boot_pgdir()
tcr |= 0x19;
TCR_W(tcr);
// Enable paging using read/modify/write
// uint32_t val = 0;
// SCTLR_R(val);
// debug_printf_("Old SCTLR: %016lx\r\n", val);
// val |= (1 << 0); // EL1 and EL0 stage 1 address translation enabled.
// debug_printf_("New SCTLR: %08x\r\n", val);
// val &= (uint32_t) ~(0x1 << 2);
// debug_printf_("New SCTLR: %08x\r\n", val);
// SCTLR_W(val);
// debug_printf_("l2[0]: %p\r\n", boot_l2pgdir[0]);
// debug_printf_("l2[1]: %p\r\n", boot_l2pgdir[1]);
// debug_printf_("l2[2]: %p\r\n", boot_l2pgdir[2]);
// debug_printf_("l2[3]: %p\r\n", boot_l2pgdir[3]);
// debug_printf_("test upper address: %x\r\n", *(uintptr_t*)boot_l2pgdir);
// debug_printf_("pgdir[%d] = %p\r\n", 384, boot_l2pgdir[384]);
// debug_printf_("test upper address: %x\r\n", *(uintptr_t*)P2V(boot_l2pgdir));
// flush all TLB
// debug_printf_("Flushing TLB.\r\n");
DSB();
CLEARTLB(0);
ISB();
}
static inline unsigned int current_el(void)
{
unsigned int el;
asm volatile("mrs %0, CurrentEL" : "=r"(el) : : "cc");
return el >> 2;
}
extern void main(void);
static bool _bss_inited = false;
void bootmain()

65
Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/uart_io_for_3568/uart.c
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@ -11,82 +11,19 @@
// at address UART0. this macro returns the
// address of one of the registers.
// the transmit output buffer.
#define UART_TX_BUF_SIZE 32
// static char uart_tx_buf[UART_TX_BUF_SIZE];
uint64_t uart_tx_w; // write next to uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE]
uint64_t uart_tx_r; // read next from uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE]
void uartinit(void)
{
// // disable uart
// UART_WRITE_REG(CR, 0);
// // disable interrupts.
// UART_WRITE_REG(IMSC, 0);
// // in qemu, it is not necessary to set baudrate.
// // enable FIFOs.
// // set word length to 8 bits, no parity.
// UART_WRITE_REG(LCRH, LCRH_FEN | LCRH_WLEN_8BIT);
// // enable RXE, TXE and enable uart.
// UART_WRITE_REG(CR, 0x301);
// // enable transmit and receive interrupts.
// UART_WRITE_REG(IMSC, INT_RX_ENABLE | INT_TX_ENABLE);
_debug_uart_init();
}
// if the UART is idle, and a character is waiting
// in the transmit buffer, send it.
// caller must hold uart_tx_lock.
// called from both the top- and bottom-half.
void uartstart()
{
// while (1) {
// if (uart_tx_w == uart_tx_r) {
// // transmit buffer is empty.
// return;
// }
// if (UART_READ_REG(FR) & FR_TXFF) {
// // the UART transmit holding register is full,
// // so we cannot give it another byte.
// // it will interrupt when it's ready for a new byte.
// return;
// }
// int c = uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE];
// uart_tx_r += 1;
// // maybe uartputc() is waiting for space in the buffer.
// UART_WRITE_REG(DR, c);
// }
}
void uartputc(uint8_t c)
{
// while (uart_tx_w == uart_tx_r + UART_TX_BUF_SIZE)
// ;
// uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE] = c;
// uart_tx_w += 1;
// uartstart();
// return;
_debug_uart_putc((int)c);
}
// read one input character from the UART.
// return -1 if none is waiting.
static uint8_t uartgetc(void)
{
// if (UART_READ_REG(FR) & FR_RXFE)
// return 0xFF;
// else
// return UART_READ_REG(DR);
return 0xFF;
return (uint8_t)_debug_uart_getc();
}
static uint32_t UartGetIrqnum()