forked from xuos/xiuos
clean code
This commit is contained in:
tuyuyang
parent
d1072fd3c2
commit
3e5895d972
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@ -1,7 +1,6 @@
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export CROSS_COMPILE ?= aarch64-none-elf-
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export DEVICE = -mtune=cortex-a55 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie
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export CFLAGS := $(DEVICE) -Wall -Werror -O0 -g -fno-omit-frame-pointer -fPIC
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# export AFLAGS := -c $(DEVICE) -x assembler-with-cpp -D__ASSEMBLY__ -gdwarf-2
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export CFLAGS := $(DEVICE) -Wall -Werror -O2 -g -fno-omit-frame-pointer -fPIC
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export LFLAGS := $(DEVICE) -Wl,-T -Wl,$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/3568.lds -Wl,--start-group,-lgcc,-lc,--end-group
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export CXXFLAGS :=
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@ -74,17 +74,9 @@ static struct arm_smccc_res __invoke_sip_fn_smc(unsigned long function_id,
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void cpu_start_secondary(uint8_t cpu_id)
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{
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//psci_call(PSCI_CPUON, cpu_id, (uintptr_t)&_boot_start, 0);
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__invoke_sip_fn_smc(PSCI_CPUON, cpu_id, (uintptr_t)0xa00000, 0);
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}
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//void psci_call(uint64_t fn, uint8_t cpuid, uint64_t entry, uint64_t ctxid);
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// int psci_cpu_on(unsigned long cpuid, unsigned long entry_point)
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// {
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// __invoke_sip_fn_smc(PSCI_CPUON, cpuid, entry_point, 0);
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// }
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void start_smp_cache_broadcast(int cpu_id)
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{
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return;
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@ -157,36 +157,12 @@ void FlushL1Dcache(uintptr_t start, uintptr_t end)
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void FlushL1DcacheAll(void)
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{
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// uint64_t ccsidr_el1; // Cache Size ID
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// int num_sets; // number of sets
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// int num_ways; // number of ways
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// uint32_t wayset; // wayset parameter
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// __asm__ __volatile__("mrs %0, ccsidr_el1" : "=r"(ccsidr_el1)); // Read Cache Size ID
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// // Fill number of sets and number of ways from ccsidr_el1 register This walues are decremented by 1
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// num_sets = ((ccsidr_el1 >> 32) & 0x7FFF) + 1;
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// num_ways = ((ccsidr_el1 >> 0) & 0x7FFF) + 1;
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// // clean and invalidate all lines (all Sets in all ways)
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// for (int way = 0; way < num_ways; way++) {
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// for (int set = 0; set < num_sets; set++) {
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// wayset = (way << 30) | (set << 5);
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// __asm__ __volatile__("dc cisw, %0" : : "r"(wayset));
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// }
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// }
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// // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
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// DSB();
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__asm_flush_dcache_all();
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__asm_flush_l3_dcache();
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}
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void InvalidateL1IcacheAll()
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{
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// __asm__ __volatile__("ic iallu\n\t");
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// // synchronize context on this processor
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// ISB();
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__asm_invalidate_icache_all();
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__asm_invalidate_l3_icache();
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}
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@ -86,19 +86,11 @@ static void build_boot_pgdir()
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if (cur_mem_paddr >= DEV_PHYMEM_BASE && cur_mem_paddr < DEV_PHYMEM_BASE + DEV_MEM_SIZE) {
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boot_dev_l4pgdirs[i][j] = cur_mem_paddr | 0x403;
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} else {
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// boot_dev_l4pgdirs[i][j] = cur_mem_paddr | 0x713;
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boot_dev_l4pgdirs[i][j] = cur_mem_paddr | 0x403;
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}
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cur_mem_paddr += PAGE_SIZE;
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}
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// if (cur_mem_paddr >= DEV_PHYMEM_BASE && cur_mem_paddr < DEV_PHYMEM_BASE + DEV_MEM_SIZE) {
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// boot_dev_l3pgdir[i] = cur_mem_paddr | 0x401;
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// } else {
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// boot_dev_l3pgdir[i] = cur_mem_paddr | 0x711;
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// }
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// cur_mem_paddr += PAGE_SIZE * 0x200;
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}
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// identical mem
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@ -110,7 +102,6 @@ static void build_boot_pgdir()
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boot_kern_l3pgdir[i] = (uint64_t)boot_kern_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID;
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for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) {
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// boot_kern_l4pgdirs[i][j] = cur_mem_paddr | L4_TYPE_PAGE | L4_PTE_NORMAL | L4_PTE_AF;
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boot_kern_l4pgdirs[i][j] = cur_mem_paddr | 0x713;
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cur_mem_paddr += PAGE_SIZE;
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@ -121,7 +112,6 @@ static void build_boot_pgdir()
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}
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}
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#include "log.h"
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static void load_boot_pgdir()
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{
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@ -135,37 +125,10 @@ static void load_boot_pgdir()
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tcr |= 0x19;
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TCR_W(tcr);
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// Enable paging using read/modify/write
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// uint32_t val = 0;
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// SCTLR_R(val);
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// debug_printf_("Old SCTLR: %016lx\r\n", val);
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// val |= (1 << 0); // EL1 and EL0 stage 1 address translation enabled.
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// debug_printf_("New SCTLR: %08x\r\n", val);
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// val &= (uint32_t) ~(0x1 << 2);
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// debug_printf_("New SCTLR: %08x\r\n", val);
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// SCTLR_W(val);
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// debug_printf_("l2[0]: %p\r\n", boot_l2pgdir[0]);
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// debug_printf_("l2[1]: %p\r\n", boot_l2pgdir[1]);
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// debug_printf_("l2[2]: %p\r\n", boot_l2pgdir[2]);
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// debug_printf_("l2[3]: %p\r\n", boot_l2pgdir[3]);
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// debug_printf_("test upper address: %x\r\n", *(uintptr_t*)boot_l2pgdir);
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// debug_printf_("pgdir[%d] = %p\r\n", 384, boot_l2pgdir[384]);
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// debug_printf_("test upper address: %x\r\n", *(uintptr_t*)P2V(boot_l2pgdir));
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// flush all TLB
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// debug_printf_("Flushing TLB.\r\n");
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DSB();
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CLEARTLB(0);
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ISB();
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}
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static inline unsigned int current_el(void)
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{
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unsigned int el;
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asm volatile("mrs %0, CurrentEL" : "=r"(el) : : "cc");
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return el >> 2;
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}
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extern void main(void);
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static bool _bss_inited = false;
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void bootmain()
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@ -11,82 +11,19 @@
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// at address UART0. this macro returns the
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// address of one of the registers.
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// the transmit output buffer.
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#define UART_TX_BUF_SIZE 32
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// static char uart_tx_buf[UART_TX_BUF_SIZE];
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uint64_t uart_tx_w; // write next to uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE]
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uint64_t uart_tx_r; // read next from uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE]
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void uartinit(void)
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{
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// // disable uart
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// UART_WRITE_REG(CR, 0);
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// // disable interrupts.
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// UART_WRITE_REG(IMSC, 0);
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// // in qemu, it is not necessary to set baudrate.
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// // enable FIFOs.
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// // set word length to 8 bits, no parity.
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// UART_WRITE_REG(LCRH, LCRH_FEN | LCRH_WLEN_8BIT);
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// // enable RXE, TXE and enable uart.
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// UART_WRITE_REG(CR, 0x301);
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// // enable transmit and receive interrupts.
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// UART_WRITE_REG(IMSC, INT_RX_ENABLE | INT_TX_ENABLE);
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_debug_uart_init();
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}
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// if the UART is idle, and a character is waiting
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// in the transmit buffer, send it.
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// caller must hold uart_tx_lock.
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// called from both the top- and bottom-half.
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void uartstart()
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{
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// while (1) {
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// if (uart_tx_w == uart_tx_r) {
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// // transmit buffer is empty.
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// return;
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// }
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// if (UART_READ_REG(FR) & FR_TXFF) {
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// // the UART transmit holding register is full,
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// // so we cannot give it another byte.
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// // it will interrupt when it's ready for a new byte.
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// return;
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// }
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// int c = uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE];
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// uart_tx_r += 1;
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// // maybe uartputc() is waiting for space in the buffer.
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// UART_WRITE_REG(DR, c);
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// }
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}
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void uartputc(uint8_t c)
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{
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// while (uart_tx_w == uart_tx_r + UART_TX_BUF_SIZE)
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// ;
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// uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE] = c;
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// uart_tx_w += 1;
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// uartstart();
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// return;
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_debug_uart_putc((int)c);
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}
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// read one input character from the UART.
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// return -1 if none is waiting.
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static uint8_t uartgetc(void)
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{
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// if (UART_READ_REG(FR) & FR_RXFE)
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// return 0xFF;
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// else
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// return UART_READ_REG(DR);
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return 0xFF;
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return (uint8_t)_debug_uart_getc();
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}
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static uint32_t UartGetIrqnum()
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