clean code

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/config.mk

@@ -1,7 +1,6 @@
 export CROSS_COMPILE ?= aarch64-none-elf-
 export DEVICE = -mtune=cortex-a55 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie
-export CFLAGS := $(DEVICE) -Wall -Werror -O0 -g -fno-omit-frame-pointer -fPIC
+export CFLAGS := $(DEVICE) -Wall -Werror -O2 -g -fno-omit-frame-pointer -fPIC
-# export AFLAGS := -c $(DEVICE) -x assembler-with-cpp -D__ASSEMBLY__ -gdwarf-2
 export LFLAGS := $(DEVICE) -Wl,-T -Wl,$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/3568.lds -Wl,--start-group,-lgcc,-lc,--end-group
 export CXXFLAGS := 
 

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/smp.c

@@ -59,7 +59,7 @@ extern void _boot_start();
 extern void __print();
 extern void __arm_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2,
     unsigned long a3, unsigned long a4, unsigned long a5,
-		  unsigned long a6, unsigned long a7, struct arm_smccc_res *res);
+    unsigned long a6, unsigned long a7, struct arm_smccc_res* res);
 
 static struct arm_smccc_res __invoke_sip_fn_smc(unsigned long function_id,
     unsigned long arg0,
@@ -74,17 +74,9 @@ static struct arm_smccc_res __invoke_sip_fn_smc(unsigned long function_id,
 
 void cpu_start_secondary(uint8_t cpu_id)
 {
-    //psci_call(PSCI_CPUON, cpu_id, (uintptr_t)&_boot_start, 0);
     __invoke_sip_fn_smc(PSCI_CPUON, cpu_id, (uintptr_t)0xa00000, 0);
 }
 
-
-//void psci_call(uint64_t fn, uint8_t cpuid, uint64_t entry, uint64_t ctxid);
-// int psci_cpu_on(unsigned long cpuid, unsigned long entry_point)
-// {
-//     __invoke_sip_fn_smc(PSCI_CPUON, cpuid, entry_point, 0);
-// }
-
 void start_smp_cache_broadcast(int cpu_id)
 {
     return;

Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a55/l1_cache.c

@@ -157,36 +157,12 @@ void FlushL1Dcache(uintptr_t start, uintptr_t end)
 
 void FlushL1DcacheAll(void)
 {
-    // uint64_t ccsidr_el1; // Cache Size ID
-    // int num_sets; // number of sets
-    // int num_ways; // number of ways
-    // uint32_t wayset; // wayset parameter
-
-    // __asm__ __volatile__("mrs %0, ccsidr_el1" : "=r"(ccsidr_el1)); // Read Cache Size ID
-
-    // // Fill number of sets  and number of ways from ccsidr_el1 register  This walues are decremented by 1
-    // num_sets = ((ccsidr_el1 >> 32) & 0x7FFF) + 1;
-    // num_ways = ((ccsidr_el1 >> 0) & 0x7FFF) + 1;
-
-    // // clean and invalidate all lines (all Sets in all ways)
-    // for (int way = 0; way < num_ways; way++) {
-    //     for (int set = 0; set < num_sets; set++) {
-    //         wayset = (way << 30) | (set << 5);
-    //         __asm__ __volatile__("dc cisw, %0" : : "r"(wayset));
-    //     }
-    // }
-
-    // // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
-    // DSB();
     __asm_flush_dcache_all();
     __asm_flush_l3_dcache();
 }
 
 void InvalidateL1IcacheAll()
 {
-    // __asm__ __volatile__("ic iallu\n\t");
-    // // synchronize context on this processor
-    // ISB();
     __asm_invalidate_icache_all();
     __asm_invalidate_l3_icache();
 }

Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/bootmmu.c

@@ -86,19 +86,11 @@ static void build_boot_pgdir()
                 if (cur_mem_paddr >= DEV_PHYMEM_BASE && cur_mem_paddr < DEV_PHYMEM_BASE + DEV_MEM_SIZE) {
                     boot_dev_l4pgdirs[i][j] = cur_mem_paddr | 0x403;
                 } else {
-                    // boot_dev_l4pgdirs[i][j] = cur_mem_paddr | 0x713;
                     boot_dev_l4pgdirs[i][j] = cur_mem_paddr | 0x403;
                 }
 
                 cur_mem_paddr += PAGE_SIZE;
             }
-
-            // if (cur_mem_paddr >= DEV_PHYMEM_BASE && cur_mem_paddr < DEV_PHYMEM_BASE + DEV_MEM_SIZE) {
-            //     boot_dev_l3pgdir[i] = cur_mem_paddr | 0x401;
-            // } else {
-            //     boot_dev_l3pgdir[i] = cur_mem_paddr | 0x711;
-            // }
-            // cur_mem_paddr += PAGE_SIZE * 0x200;
         }
 
         // identical mem
@@ -110,7 +102,6 @@ static void build_boot_pgdir()
             boot_kern_l3pgdir[i] = (uint64_t)boot_kern_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID;
 
             for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) {
-                // boot_kern_l4pgdirs[i][j] = cur_mem_paddr | L4_TYPE_PAGE | L4_PTE_NORMAL | L4_PTE_AF;
                 boot_kern_l4pgdirs[i][j] = cur_mem_paddr | 0x713;
 
                 cur_mem_paddr += PAGE_SIZE;
@@ -121,7 +112,6 @@ static void build_boot_pgdir()
     }
 }
 
-#include "log.h"
 static void load_boot_pgdir()
 {
 
@@ -135,37 +125,10 @@ static void load_boot_pgdir()
     tcr |= 0x19;
     TCR_W(tcr);
 
-    // Enable paging using read/modify/write
-    // uint32_t val = 0;
-    // SCTLR_R(val);
-    // debug_printf_("Old SCTLR: %016lx\r\n", val);
-    // val |= (1 << 0); // EL1 and EL0 stage 1 address translation enabled.
-    // debug_printf_("New SCTLR: %08x\r\n", val);
-    // val &= (uint32_t) ~(0x1 << 2);
-    // debug_printf_("New SCTLR: %08x\r\n", val);
-    // SCTLR_W(val);
-    // debug_printf_("l2[0]: %p\r\n", boot_l2pgdir[0]);
-    // debug_printf_("l2[1]: %p\r\n", boot_l2pgdir[1]);
-    // debug_printf_("l2[2]: %p\r\n", boot_l2pgdir[2]);
-    // debug_printf_("l2[3]: %p\r\n", boot_l2pgdir[3]);
-    // debug_printf_("test upper address: %x\r\n", *(uintptr_t*)boot_l2pgdir);
-    // debug_printf_("pgdir[%d] = %p\r\n", 384, boot_l2pgdir[384]);
-    // debug_printf_("test upper address: %x\r\n", *(uintptr_t*)P2V(boot_l2pgdir));
-
-    // flush all TLB
-    // debug_printf_("Flushing TLB.\r\n");
-    DSB();
     CLEARTLB(0);
     ISB();
 }
 
-static inline unsigned int current_el(void)
-{
-    unsigned int el;
-    asm volatile("mrs %0, CurrentEL" : "=r"(el) : : "cc");
-    return el >> 2;
-}
-
 extern void main(void);
 static bool _bss_inited = false;
 void bootmain()

Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a55/uart_io_for_3568/uart.c

@@ -11,82 +11,19 @@
 // at address UART0. this macro returns the
 // address of one of the registers.
 
-// the transmit output buffer.
-#define UART_TX_BUF_SIZE 32
-// static char uart_tx_buf[UART_TX_BUF_SIZE];
-uint64_t uart_tx_w; // write next to uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE]
-uint64_t uart_tx_r; // read next from uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE]
-
 void uartinit(void)
 {
-    // // disable uart
-    // UART_WRITE_REG(CR, 0);
-
-    // // disable interrupts.
-    // UART_WRITE_REG(IMSC, 0);
-
-    // // in qemu, it is not necessary to set baudrate.
-    // // enable FIFOs.
-    // // set word length to 8 bits, no parity.
-    // UART_WRITE_REG(LCRH, LCRH_FEN | LCRH_WLEN_8BIT);
-
-    // // enable RXE, TXE and enable uart.
-    // UART_WRITE_REG(CR, 0x301);
-
-    // // enable transmit and receive interrupts.
-    // UART_WRITE_REG(IMSC, INT_RX_ENABLE | INT_TX_ENABLE);
-
     _debug_uart_init();
 }
 
-// if the UART is idle, and a character is waiting
-// in the transmit buffer, send it.
-// caller must hold uart_tx_lock.
-// called from both the top- and bottom-half.
-void uartstart()
-{
-    // while (1) {
-    //     if (uart_tx_w == uart_tx_r) {
-    //         // transmit buffer is empty.
-    //         return;
-    //     }
-
-    //     if (UART_READ_REG(FR) & FR_TXFF) {
-    //         // the UART transmit holding register is full,
-    //         // so we cannot give it another byte.
-    //         // it will interrupt when it's ready for a new byte.
-    //         return;
-    //     }
-
-    //     int c = uart_tx_buf[uart_tx_r % UART_TX_BUF_SIZE];
-    //     uart_tx_r += 1;
-
-    //     // maybe uartputc() is waiting for space in the buffer.
-
-    //     UART_WRITE_REG(DR, c);
-    // }
-}
-
 void uartputc(uint8_t c)
 {
-    // while (uart_tx_w == uart_tx_r + UART_TX_BUF_SIZE)
-    //     ;
-    // uart_tx_buf[uart_tx_w % UART_TX_BUF_SIZE] = c;
-    // uart_tx_w += 1;
-    // uartstart();
-    // return;
     _debug_uart_putc((int)c);
 }
 
-// read one input character from the UART.
-// return -1 if none is waiting.
 static uint8_t uartgetc(void)
 {
-    // if (UART_READ_REG(FR) & FR_RXFE)
+    return (uint8_t)_debug_uart_getc();
-    //     return 0xFF;
-    // else
-    //     return UART_READ_REG(DR);
-    return 0xFF;
 }
 
 static uint32_t UartGetIrqnum()