/* * Copyright 2017-2018 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ /** * @file board.h * @brief define imxrt1052-board init configure and start-up function * @version 1.0 * @author AIIT XUOS Lab * @date 2021-05-28 */ /************************************************* File name: board.h Description: define imxrt1052-board board init function and struct Others: History: 1. Date: 2021-05-28 Author: AIIT XUOS Lab Modification: 1. define imxrt-board InitBoardHardware 2. define imxrt-board heap struct *************************************************/ #ifndef __BOARD_H__ #define __BOARD_H__ #include "fsl_common.h" #include "fsl_gpio.h" #include "fsl_clock.h" #include "fsl_enet.h" #include "clock_config.h" // #include #include extern int heap_start; extern int heap_end; #define HEAP_BEGIN (&heap_start) #define HEAP_END (&heap_end) #define HEAP_SIZE ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN) void InitBoardHardware(void); /******************************************************************************* * Definitions ******************************************************************************/ /*! @brief The board name */ #define BOARD_NAME "IMXRT1050" #define configMAC_ADDR {0x02, 0x12, 0x13, 0x10, 0x15, 0x11} #define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority 4 bits for subpriority */ #define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority 3 bits for subpriority */ #define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority 2 bits for subpriority */ #define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority 1 bits for subpriority */ #define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority*/ /*! @brief The ENET PHY address. */ #define BOARD_ENET0_PHY_ADDRESS (0x0U) /* Phy address of enet port 0. */ /* USB PHY condfiguration */ #define BOARD_USB_PHY_D_CAL (0x0CU) #define BOARD_USB_PHY_TXCAL45DP (0x06U) #define BOARD_USB_PHY_TXCAL45DM (0x06U) #define BOARD_ARDUINO_INT_IRQ (GPIO1_INT3_IRQn) #define BOARD_ARDUINO_I2C_IRQ (LPI2C1_IRQn) #define BOARD_ARDUINO_I2C_INDEX (1) #define BOARD_USDHC1_BASEADDR USDHC1 #define BOARD_USDHC2_BASEADDR USDHC2 #define BOARD_USDHC_CD_GPIO_BASE GPIO2 #define BOARD_USDHC_CD_GPIO_PIN 28 #define BOARD_USDHC_CD_PORT_IRQ GPIO2_Combined_16_31_IRQn #define BOARD_USDHC_CD_PORT_IRQ_HANDLER GPIO2_Combined_16_31_IRQHandler #define BOARD_USDHC_CD_STATUS() (GPIO_PinRead(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN)) #define BOARD_USDHC_CD_INTERRUPT_STATUS() (GPIO_PortGetInterruptFlags(BOARD_USDHC_CD_GPIO_BASE)) #define BOARD_USDHC_CD_CLEAR_INTERRUPT(flag) (GPIO_PortClearInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, flag)) #define BOARD_USDHC_CD_GPIO_INIT() \ { \ gpio_pin_config_t sw_config = { \ kGPIO_DigitalInput, \ 0, \ kGPIO_IntRisingOrFallingEdge, \ }; \ GPIO_PinInit(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN, &sw_config); \ GPIO_PortEnableInterrupts(BOARD_USDHC_CD_GPIO_BASE, 1U << BOARD_USDHC_CD_GPIO_PIN); \ GPIO_PortClearInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, ~0); \ } #define BOARD_HAS_SDCARD (1U) #define BOARD_SD_POWER_RESET_GPIO (GPIO1) #define BOARD_SD_POWER_RESET_GPIO_PIN (5U) #define BOARD_USDHC_CARD_INSERT_CD_LEVEL (0U) #define BOARD_USDHC_MMCCARD_POWER_CONTROL(state) #define BOARD_USDHC_MMCCARD_POWER_CONTROL_INIT() \ { \ gpio_pin_config_t sw_config = { \ kGPIO_DigitalOutput, \ 0, \ kGPIO_NoIntmode, \ }; \ GPIO_PinInit(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, &sw_config); \ GPIO_PinWrite(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, true); \ } #define BOARD_USDHC_SDCARD_POWER_CONTROL_INIT() \ { \ gpio_pin_config_t sw_config = { \ kGPIO_DigitalOutput, \ 0, \ kGPIO_NoIntmode, \ }; \ GPIO_PinInit(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, &sw_config); \ } #define BOARD_USDHC_SDCARD_POWER_CONTROL(state) \ (GPIO_PinWrite(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, state)) #define BOARD_USDHC1_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) / (CLOCK_GetDiv(kCLOCK_Usdhc1Div) + 1U)) #define BOARD_USDHC2_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) / (CLOCK_GetDiv(kCLOCK_Usdhc2Div) + 1U)) #define BOARD_SD_HOST_BASEADDR BOARD_USDHC1_BASEADDR #define BOARD_SD_HOST_CLK_FREQ BOARD_USDHC1_CLK_FREQ #define BOARD_SD_HOST_IRQ USDHC1_IRQn #define BOARD_MMC_HOST_BASEADDR BOARD_USDHC2_BASEADDR #define BOARD_MMC_HOST_CLK_FREQ BOARD_USDHC2_CLK_FREQ #define BOARD_MMC_HOST_IRQ USDHC2_IRQn #define BOARD_MMC_VCCQ_SUPPLY kMMC_VoltageWindow170to195 #define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360 /* we are using the BB SD socket to DEMO the MMC example,but the * SD socket provide 4bit bus only, so we define this macro to avoid * 8bit data bus test */ #define BOARD_MMC_SUPPORT_8BIT_BUS (1U) #define BOARD_SD_HOST_SUPPORT_SDR104_FREQ (200000000U) #define BOARD_SD_HOST_SUPPORT_HS200_FREQ (180000000U) /* @Brief Board accelerator sensor configuration */ #define BOARD_ACCEL_I2C_BASEADDR LPI2C1 /* Select USB1 PLL (480 MHz) as LPI2C's clock source */ #define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U) /* Clock divider for LPI2C clock source */ #define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U) #define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U)) #define BOARD_CODEC_I2C_BASEADDR LPI2C1 #define BOARD_CODEC_I2C_INSTANCE 1U #define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U) #define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U) #define BOARD_CODEC_I2C_CLOCK_FREQ (10000000U) #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ void BOARD_ConfigMPU(void); void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength); void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength); #if defined(__cplusplus) } #endif /* __cplusplus */ #endif /* _BOARD_H_ */