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add pin config for riscv64 board

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This commit is contained in:
Wang_Weigen
2022-03-15 16:04:51 +08:00
parent cb8da02a88
commit 7ebc769017
6 changed files with 45 additions and 77 deletions
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Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/ch438.c
+9 -7
View File
@@ -6,7 +6,7 @@
#include "ch438.h"
#include "sleep.h"
static rt_sem_t ch438_sem;
static struct rt_semaphore ch438_sem;
static rt_uint8_t offsetadd[] = {0x00,0x10,0x20,0x30,0x08,0x18,0x28,0x38,}; /* Offset address of serial port number */
rt_uint8_t RevLen ,Ch438Buff[8][BUFFSIZE],Ch438BuffPtr[8];
@@ -364,18 +364,18 @@ const struct rt_uart_ops extuart_ops =
static int Ch438Irq(void *parameter)
{
rt_sem_release(ch438_sem);
rt_sem_release(&ch438_sem);
}
void Ch438InitDefault(void)
int Ch438InitDefault(void)
{
rt_err_t flag;
flag = rt_sem_init(ch438_sem, "sem_438",0,RT_IPC_FLAG_FIFO);
flag = rt_sem_init(&ch438_sem, "sem_438",0,RT_IPC_FLAG_FIFO);
if (flag != RT_EOK)
{
rt_kprintf("ch438.drv create sem failed .\n");
return ;
return -1;
}
gpiohs_set_drive_mode(FPIOA_CH438_INT, GPIO_DM_INPUT_PULL_UP);
@@ -383,7 +383,9 @@ void Ch438InitDefault(void)
gpiohs_irq_register(FPIOA_CH438_INT, 1, Ch438Irq, 0);
CH438_INIT();
return 0;
}
INIT_APP_EXPORT(Ch438InitDefault);
int rt_hw_ch438_init(void)
{
@@ -464,7 +466,7 @@ int rt_hw_ch438_init(void)
// uart);
// }
// #endif
Ch438InitDefault();
// Ch438InitDefault();
return 0;
}
INIT_DEVICE_EXPORT(rt_hw_ch438_init);
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_io_config.c
+14
View File
@@ -139,6 +139,20 @@ static struct io_config
#ifdef BSP_PWM_CHN3_ENABLE
IOCONFIG(BSP_PWM_CHN3_PIN, FUNC_TIMER2_TOGGLE4),
#endif
IOCONFIG(BSP_CH438_ALE_PIN, HS_GPIO(FPIOA_CH438_ALE)),
IOCONFIG(BSP_CH438_NWR_PIN, HS_GPIO(FPIOA_CH438_NWR)),
IOCONFIG(BSP_CH438_NRD_PIN, HS_GPIO(FPIOA_CH438_NRD)),
IOCONFIG(BSP_CH438_INT_PIN, HS_GPIO(FPIOA_CH438_INT)),
IOCONFIG(BSP_CH438_D0_PIN, HS_GPIO(FPIOA_CH438_D0)),
IOCONFIG(BSP_CH438_D1_PIN, HS_GPIO(FPIOA_CH438_D1)),
IOCONFIG(BSP_CH438_D2_PIN, HS_GPIO(FPIOA_CH438_D2)),
IOCONFIG(BSP_CH438_D3_PIN, HS_GPIO(FPIOA_CH438_D3)),
IOCONFIG(BSP_CH438_D4_PIN, HS_GPIO(FPIOA_CH438_D4)),
IOCONFIG(BSP_CH438_D5_PIN, HS_GPIO(FPIOA_CH438_D5)),
IOCONFIG(BSP_CH438_D6_PIN, HS_GPIO(FPIOA_CH438_D6)),
IOCONFIG(BSP_CH438_D7_PIN, HS_GPIO(FPIOA_CH438_D7)),
};
static int print_io_config()
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/drv_io_config.h
+15
View File
@@ -58,6 +58,21 @@ enum HS_GPIO_CONFIG
#define FPIOA_CH438_INT 22
#define FPIOA_485_DIR 23
//PIN.define
#define BSP_CH438_ALE_PIN 23
#define BSP_CH438_NWR_PIN 24
#define BSP_CH438_NRD_PIN 25
#define BSP_CH438_D0_PIN 27
#define BSP_CH438_D1_PIN 28
#define BSP_CH438_D2_PIN 29
#define BSP_CH438_D3_PIN 30
#define BSP_CH438_D4_PIN 31
#define BSP_CH438_D5_PIN 32
#define BSP_CH438_D6_PIN 33
#define BSP_CH438_D7_PIN 34
#define BSP_CH438_INT_PIN 35
extern int io_config_init(void);
#endif