forked from xuos/xiuos
add cortex-m0 support and fix some bugs
This commit is contained in:
Kiritoy
@@ -1,4 +1,4 @@
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SRC_FILES := pendsv.S prepare_ahwstack.c arm32_switch.c
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SRC_FILES := prepare_ahwstack.c
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include $(KERNEL_ROOT)/compiler.mk
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@@ -1,154 +0,0 @@
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/*
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* Copyright (c) 2020 AIIT XUOS Lab
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* XiUOS is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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* See the Mulan PSL v2 for more details.
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*/
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#include <xs_base.h>
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#include <xs_ktask.h>
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#define SCB_VTOR "0xE000ED08"
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#define NVIC_INT_CTRL "0xE000ED04"
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#define NVIC_SYSPRI2 "0xE000ED20"
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#define NVIC_PENDSV_PRI "0x00FF0000"
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#define NVIC_PENDSVSET "0x10000000"
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void __attribute__((naked)) HwInterruptcontextSwitch(x_ubase from, x_ubase to, struct TaskDescriptor *to_task, void *context)
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{
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asm volatile ("LDR r4, =KtaskSwitchInterruptFlag");
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asm volatile ("LDR r5, [r4]");
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asm volatile ("CMP r5, #1");
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asm volatile ("BEQ Arm32SwitchReswitch");
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asm volatile ("MOV r5, #1");
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asm volatile ("STR r5, [r4]");
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asm volatile ("LDR r4, =InterruptFromKtask");
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asm volatile ("STR r0, [r4]");
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asm volatile ("B Arm32SwitchReswitch");
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}
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void __attribute__((naked)) Arm32SwitchReswitch()
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{
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asm volatile ("LDR r4, =InterruptToKtask");
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asm volatile ("STR r1, [r4]");
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asm volatile ("LDR r4, =InterruptToKtaskDescriptor");
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asm volatile ("STR r2, [r4]");
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asm volatile ("LDR r0, =" NVIC_INT_CTRL);
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asm volatile ("LDR r1, =" NVIC_PENDSVSET);
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asm volatile ("STR r1, [r0]");
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asm volatile ("BX LR");
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}
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void __attribute__((naked)) SwitchKtaskContext(x_ubase from, x_ubase to, struct TaskDescriptor *to_task)
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{
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asm volatile("B HwInterruptcontextSwitch");
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}
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void __attribute__((naked)) SwitchKtaskContextTo(x_ubase to, struct TaskDescriptor *to_task)
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{
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asm volatile ("LDR r2, =InterruptToKtask");
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asm volatile ("STR r0, [r2]");
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asm volatile ("LDR r2, =InterruptToKtaskDescriptor");
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asm volatile ("STR r1, [r2]");
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#if defined (__VFP_FP__) && !defined(__SOFTFP__)
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asm volatile ("MRS r2, CONTROL");
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asm volatile ("BIC r2, #0x04");
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asm volatile ("MSR CONTROL, r2");
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#endif
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asm volatile ("LDR r1, =InterruptFromKtask");
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asm volatile ("MOV r0, #0x0");
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asm volatile ("STR r0, [r1]");
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asm volatile ("LDR r1, =KtaskSwitchInterruptFlag");
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asm volatile ("MOV r0, #1");
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asm volatile ("STR r0, [r1]");
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asm volatile ("LDR r0, =" NVIC_SYSPRI2);
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asm volatile ("LDR r1, =" NVIC_PENDSV_PRI);
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asm volatile ("LDR.W r2, [r0,#0x00]");
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asm volatile ("ORR r1,r1,r2");
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asm volatile ("STR r1, [r0]");
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asm volatile ("LDR r0, =" NVIC_INT_CTRL);
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asm volatile ("LDR r1, =" NVIC_PENDSVSET);
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asm volatile ("STR r1, [r0]");
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asm volatile ("LDR r0, =" SCB_VTOR);
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asm volatile ("LDR r0, [r0]");
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asm volatile ("LDR r0, [r0]");
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asm volatile ("NOP");
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asm volatile ("MSR msp, r0");
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asm volatile ("CPSIE F");
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asm volatile ("CPSIE I");
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asm volatile ("BX lr");
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}
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void __attribute__((naked)) HardFaultHandler()
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{
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asm volatile ("MRS r0, msp");
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asm volatile ("TST lr, #0x04");
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asm volatile ("BEQ Arm32SwitchGetSpDone");
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asm volatile ("MRS r0, psp");
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asm volatile ("B Arm32SwitchGetSpDone");
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}
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void __attribute__((naked)) Arm32SwitchGetSpDone()
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{
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asm volatile ("MRS r3, primask");
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asm volatile ("STMFD r0!, {r3 - r11}");
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asm volatile ("STMFD r0!, {lr}");
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#if defined (__VFP_FP__) && !defined(__SOFTFP__)
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asm volatile ("MOV r4, #0x00");
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asm volatile ("TST lr, #0x10");
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asm volatile ("MOVEQ r4, #0x01");
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asm volatile ("STMFD r0!, {r4}");
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#endif
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asm volatile ("TST lr, #0x04");
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asm volatile ("BEQ Arm32SwitchUpdateMsp");
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asm volatile ("MSR psp, r0");
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asm volatile ("B Arm32SwitchUpdateDone");
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asm volatile ("B Arm32SwitchUpdateMsp");
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}
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void __attribute__((naked)) Arm32SwitchUpdateMsp()
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{
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asm volatile ("MSR msp, r0");
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asm volatile ("B Arm32SwitchUpdateDone");
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}
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void __attribute__((naked)) Arm32SwitchUpdateDone()
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{
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asm volatile ("PUSH {LR}");
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asm volatile ("BL HwHardFaultException");
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asm volatile ("POP {LR}");
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asm volatile ("ORR lr, lr, #0x04");
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asm volatile ("BX lr");
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}
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void __attribute__((naked)) MemFaultHandler()
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{
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asm volatile ("MRS r0, msp");
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asm volatile ("TST lr, #0x04");
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asm volatile ("BEQ Arm32Switch1");
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asm volatile ("MRS r0, psp");
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asm volatile ("B Arm32Switch1");
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}
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void __attribute__((naked)) Arm32Switch1()
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{
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asm volatile ("MRS r3, primask");
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asm volatile ("STMFD r0!, {r3 - r11}");
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#if defined (__VFP_FP__) && !defined(__SOFTFP__)
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asm volatile ("MOV r4, #0x00");
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asm volatile ("TST lr, #0x10");
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asm volatile ("MOVEQ r4, #0x01");
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asm volatile ("STMFD r0!, {r4}");
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#endif
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asm volatile ("STMFD r0!, {lr}");
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asm volatile ("PUSH {LR}");
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asm volatile ("BL MemFaultHandle");
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asm volatile ("POP {LR}");
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asm volatile ("ORR lr, lr, #0x04");
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asm volatile ("BX lr");
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}
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@@ -1,118 +0,0 @@
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2009-10-11 Bernard first version
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* 2012-01-01 aozima support context switch load/store FPU register.
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* 2013-06-18 aozima add restore MSP feature.
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* 2013-06-23 aozima support lazy stack optimized.
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* 2018-07-24 aozima enhancement hard fault exception handler.
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*/
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/*************************************************
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File name: pendsv.S
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Description: PendSV interrupt handler
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Others: take RT-Thread v4.0.2/libcpu/arm/cortex-m4/context_gcc.S for references
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https://github.com/RT-Thread/rt-thread/tree/v4.0.2
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History:
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1. Date: 2021-04-25
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Author: AIIT XUOS Lab
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*************************************************/
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#include <xsconfig.h>
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.cpu cortex-m4
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.syntax unified
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.thumb
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.text
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.equ SCB_VTOR, 0xE000ED08
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.equ NVIC_INT_CTRL, 0xE000ED04
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.equ NVIC_SYSPRI2, 0xE000ED20
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.equ NVIC_PENDSV_PRI, 0x00FF0000
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.equ NVIC_PENDSVSET, 0x10000000
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.globl PendSV_Handler
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.type PendSV_Handler, %function
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PendSV_Handler:
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MRS r3, PRIMASK
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CPSID I
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LDR r0, =KtaskSwitchInterruptFlag
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LDR r1, [r0]
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CBZ r1, pendsv_exit
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MOV r1, #0x00
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STR r1, [r0]
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LDR r0, =InterruptFromKtask
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LDR r1, [r0]
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CBZ r1, switch_to_task
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MRS r1, psp
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STMFD r1!, {r3 - r11}
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#if defined (__VFP_FP__) && !defined(__SOFTFP__)
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MOV r4, #0x00
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TST lr, #0x10
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MOVEQ r4, #0x01
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STMFD r1!, {r4}
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#endif
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LDR r0, [r0]
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STR r1, [r0]
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switch_to_task:
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PUSH {lr}
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BL UpdateRunningTask
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POP {lr}
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#ifdef TASK_ISOLATION
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PUSH {lr}
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BL GetTaskPrivilege
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POP {lr}
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#endif
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LDR r1, =InterruptToKtask
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LDR r1, [r1]
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LDR r1, [r1]
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#if defined (__VFP_FP__) && !defined(__SOFTFP__)
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LDMFD r1!, {r2}
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#endif
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LDMFD r1!, {r3 - r11}
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MSR psp, r1
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#if defined (__VFP_FP__) && !defined(__SOFTFP__)
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ORR lr, lr, #0x10
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CMP r2, #0
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BICNE lr, lr, #0x10
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#endif
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MRS r2, control
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#ifdef TASK_ISOLATION
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CMP r0, #1
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BEQ unprivilege
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privilege:
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BIC r2, r2, #0x01
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B exit
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unprivilege:
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ORR r2, r2, #0x01
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#else
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BIC r2, r2, #0x01
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#endif
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exit:
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MSR control, r2
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pendsv_exit:
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ORR lr, lr, #0x04
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MSR PRIMASK, r3
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BX lr
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