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boot cpu0 and 1 successfully

This commit is contained in:
lr 2024-07-08 17:42:59 +08:00
parent ff37506a09
commit ef0df95a36
4 changed files with 13 additions and 9 deletions
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2
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/core.h
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@ -73,7 +73,7 @@ Modification:
#include "cortex_a55.h" #include "cortex_a55.h"
#define NR_CPU 4 // maximum number of CPUs #define NR_CPU 2 // maximum number of CPUs
__attribute__((always_inline)) static inline uint64_t EL0_mode() // Set ARM mode to EL0 __attribute__((always_inline)) static inline uint64_t EL0_mode() // Set ARM mode to EL0
{ {

12
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/boot.S
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@ -36,7 +36,8 @@ _boot_start:
// get cpu id, and subtract the offset from the stacks base address // get cpu id, and subtract the offset from the stacks base address
mrs x2, mpidr_el1 mrs x2, mpidr_el1
and x2, x2, #0x3 and x2, x2, #0xFFF
lsr x2, x2, #8
mov x5, x2 mov x5, x2
mul x3, x2, x1 mul x3, x2, x1
sub x0, x0, x3 sub x0, x0, x3
@ -45,11 +46,10 @@ _boot_start:
mov x2, #ARM_MODE_EL1_h | DIS_INT mov x2, #ARM_MODE_EL1_h | DIS_INT
msr spsr_el1, x2 msr spsr_el1, x2
// bl el2_setup
// check cpu id - cpu0 is primary cpu // check cpu id - cpu0 is primary cpu
mrs x2, mpidr_el1 mrs x2, mpidr_el1
and x2, x2, #0x3 and x2, x2, #0xFFF
lsr x2, x2, #8
mov x5, x2 mov x5, x2
cmp x5, #0 cmp x5, #0
beq primary_cpu_init beq primary_cpu_init
@ -66,7 +66,7 @@ primary_cpu_init:
1: 1:
cmp x1, x2 cmp x1, x2
stp x3, x3, [x1], #16 stp x3, x3, [x1], #16
b.lt 1b b.lt 1b
bl bootmain bl bootmain
@ -117,4 +117,4 @@ el2_setup:
eret eret
.endfunc .endfunc
.end .end

2
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_3568/smp.c
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@ -75,7 +75,7 @@ static struct arm_smccc_res __invoke_sip_fn_smc(unsigned long function_id,
void cpu_start_secondary(uint8_t cpu_id) void cpu_start_secondary(uint8_t cpu_id)
{ {
//psci_call(PSCI_CPUON, cpu_id, (uintptr_t)&_boot_start, 0); //psci_call(PSCI_CPUON, cpu_id, (uintptr_t)&_boot_start, 0);
__invoke_sip_fn_smc(PSCI_CPUON, cpu_id, (uintptr_t)&__print, 0); __invoke_sip_fn_smc(PSCI_CPUON, cpu_id, (uintptr_t)0xa00000, 0);
} }

6
Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a55/bootmmu.c
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@ -253,7 +253,11 @@ extern void main(void);
static bool _bss_inited = false; static bool _bss_inited = false;
void bootmain() void bootmain()
{ {
// __print(); __print();
// if(_bss_inited){
// unsigned int* p = (unsigned int*)0xffffffff;
// *p = 0;
// }
build_boot_pgdir(); build_boot_pgdir();
load_boot_pgdir(); load_boot_pgdir();
__asm__ __volatile__("add sp, sp, %0" ::"r"(KERN_OFFSET)); __asm__ __volatile__("add sp, sp, %0" ::"r"(KERN_OFFSET));