forked from xuos/xiuos
fix SYSTIMER for rk3568 at eth
This commit is contained in:
lr
parent
6bc856b7a6
commit
6ae8b6e160
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@ -36,8 +36,8 @@ Modification:
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/* A55 physical memory layout */
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#define PHY_MEM_BASE (0x0000000010000000ULL)
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#define PHY_USER_FREEMEM_BASE (0x0000000040000000ULL)
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#define PHY_USER_FREEMEM_TOP (0x00000000e0000000ULL)
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#define PHY_MEM_STOP (0x00000000e0000000ULL)
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#define PHY_USER_FREEMEM_TOP (0x00000000E0000000ULL)
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#define PHY_MEM_STOP (0x00000000E0000000ULL)
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/* PTE-PAGE_SIZE */
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#define LEVEL4_PTE_SHIFT 12
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@ -312,13 +312,12 @@ __attribute__((weak)) HAL_Status HAL_DelayMs(uint32_t ms)
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*/
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HAL_Status HAL_DelayUs(uint32_t us)
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{
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// #if defined(SYS_TIMER) && defined(HAL_TIMER_MODULE_ENABLED)
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// return TimerDelayUs(us);
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// #else
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#if defined(SYS_TIMER) && defined(HAL_TIMER_MODULE_ENABLED)
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return TimerDelayUs(us);
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#else
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return HAL_CPUDelayUs(us);
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// #endif
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#endif
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}
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/**
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@ -321,21 +321,43 @@ const struct HAL_CANFD_DEV g_can2Dev =
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#endif
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#ifdef HAL_GMAC_MODULE_ENABLED
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// const struct HAL_GMAC_DEV g_gmac0Dev =
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// {
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// .pReg = GMAC0,
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// .clkID = CLK_MAC0_2TOP,
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// .clkGateID = CLK_MAC0_2TOP_GATE,
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// .pclkID = PCLK_PHP,
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// .pclkGateID = PCLK_GMAC0_GATE,
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// .irqNum = GMAC0_IRQn,
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// };
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const struct HAL_GMAC_DEV g_gmac0Dev =
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{
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.pReg = GMAC0,
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.clkID = CLK_MAC0_2TOP,
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.clkGateID = CLK_MAC0_2TOP_GATE,
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.clkID125M = CLK_MAC0_2TOP,
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.clkID50M = CLK_MAC0_2TOP,
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.clkGateID125M = CLK_MAC0_2TOP_GATE,
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.clkGateID50M = CLK_MAC0_2TOP_GATE,
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.pclkID = PCLK_PHP,
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.pclkGateID = PCLK_GMAC0_GATE,
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.irqNum = GMAC0_IRQn,
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};
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// const struct HAL_GMAC_DEV g_gmac1Dev =
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// {
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// .pReg = GMAC1,
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// .clkID = CLK_MAC1_2TOP,
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// .clkGateID = CLK_MAC1_2TOP_GATE,
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// .pclkID = PCLK_USB,
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// .pclkGateID = PCLK_GMAC1_GATE,
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// .irqNum = GMAC1_IRQn,
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// };
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const struct HAL_GMAC_DEV g_gmac1Dev =
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{
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.pReg = GMAC1,
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.clkID = CLK_MAC1_2TOP,
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.clkGateID = CLK_MAC1_2TOP_GATE,
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.clkID125M = CLK_MAC1_2TOP,
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.clkID50M = CLK_MAC1_2TOP,
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.clkGateID125M = CLK_MAC1_2TOP_GATE,
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.clkGateID50M = CLK_MAC1_2TOP_GATE,
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.pclkID = PCLK_USB,
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.pclkGateID = PCLK_GMAC1_GATE,
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.irqNum = GMAC1_IRQn,
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@ -115,8 +115,8 @@
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#define CRU_PLL_ROUND_UP_TO_KHZ(x) (HAL_DIV_ROUND_UP((x), KHZ) * KHZ)
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#define CRU_READ(r) (*(volatile uint32_t *)(r))
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#define CRU_WRITE(r, b, w, v) (*(volatile uint32_t *)(r) = ((w) << (16) | (v) << (b)))
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#define CRU_READ(r) (*(volatile uint32_t *)((uintptr_t)(r)))
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#define CRU_WRITE(r, b, w, v) (*(volatile uint32_t *)((uintptr_t)(r)) = ((w) << (16) | (v) << (b)))
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/********************* Private Structure Definition **************************/
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static struct PLL_CONFIG g_rockchipAutoTable;
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@ -147,6 +147,22 @@ static int isBetterFreq(uint32_t now, uint32_t new, uint32_t best)
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return (new <= now && new > best);
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}
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int HAL_CRU_FreqGetMuxArray(uint32_t freq, uint32_t *table, int num)
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{
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uint32_t best = 0, mux = 0;
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int i;
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for (i = 0; i < num; i++) {
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if (isBetterFreq(freq, table[i], best)) {
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best = table[i];
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mux = i;
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break;
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}
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}
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return mux;
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}
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int HAL_CRU_FreqGetMux4(uint32_t freq, uint32_t freq0, uint32_t freq1,
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uint32_t freq2, uint32_t freq3)
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{
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@ -191,6 +207,17 @@ int HAL_CRU_FreqGetMux2(uint32_t freq, uint32_t freq0, uint32_t freq1)
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return HAL_CRU_FreqGetMux4(freq, freq0, freq1, freq1, freq1);
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}
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uint32_t HAL_CRU_MuxGetFreqArray(uint32_t muxName, uint32_t *table, int num)
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{
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uint32_t mux = HAL_CRU_ClkGetMux(muxName);
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if (mux <= (uint32_t)num) {
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return table[mux];
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} else {
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return HAL_INVAL;
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}
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}
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uint32_t HAL_CRU_MuxGetFreq4(uint32_t muxName, uint32_t freq0, uint32_t freq1,
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uint32_t freq2, uint32_t freq3)
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{
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@ -223,6 +250,30 @@ uint32_t HAL_CRU_MuxGetFreq2(uint32_t muxName, uint32_t freq0, uint32_t freq1)
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return HAL_CRU_MuxGetFreq4(muxName, freq0, freq1, freq1, freq1);
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}
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int HAL_CRU_RoundFreqGetMuxArray(uint32_t freq, uint32_t *table, int num, uint32_t *pFreqOut, bool is_div)
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{
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uint32_t mux = 0;
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int i = 0;
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for (i = 0; i < num; i++) {
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if (is_div) {
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if (table[i] && (table[i] % freq == 0)) {
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mux = i;
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break;
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}
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} else {
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if (table[i] && (table[i] == freq)) {
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mux = i;
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break;
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}
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}
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}
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*pFreqOut = table[mux];
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return mux;
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}
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int HAL_CRU_RoundFreqGetMux4(uint32_t freq, uint32_t pFreq0,
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uint32_t pFreq1, uint32_t pFreq2,
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uint32_t pFreq3, uint32_t *pFreqOut)
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@ -811,7 +862,7 @@ HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup)
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*/
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uint32_t HAL_CRU_GetPllFreq(struct PLL_SETUP *pSetup)
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{
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uint32_t refDiv, fbDiv, postdDv1, postDiv2, frac, dsmpd;
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uint64_t refDiv, fbDiv, postdDv1, postDiv2, frac, dsmpd;
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uint32_t mode = 0, rate = PLL_INPUT_OSC_RATE;
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mode = PLL_GET_PLLMODE(READ_REG(*(pSetup->modeOffset)), pSetup->modeShift,
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@ -956,6 +1007,271 @@ HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup)
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}
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#endif
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#ifdef CRU_CLK_USE_CON_BANK
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static const struct HAL_CRU_DEV *CRU_GetInfo(void)
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{
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return &g_cruDev;
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}
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HAL_Check HAL_CRU_ClkIsEnabled(uint32_t clk)
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{
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const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
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uint32_t index = CLK_GATE_GET_REG_OFFSET(clk);
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uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk);
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uint32_t bank = CLK_GATE_GET_REG_BANK(clk);
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uint32_t reg;
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HAL_Check ret;
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reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].gateOffset + index * 4;
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ret = (HAL_Check)(!((CRU_READ(reg) & (1 << shift)) >> shift));
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return ret;
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}
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HAL_SECTION_SRAM_CODE
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HAL_Status HAL_CRU_ClkEnable(uint32_t clk)
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{
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const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
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uint32_t index = CLK_GATE_GET_REG_OFFSET(clk);
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uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk);
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uint32_t bank = CLK_GATE_GET_REG_BANK(clk);
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uint32_t reg;
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reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].gateOffset + index * 4;
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CRU_WRITE(reg, shift, 1U << shift, 0U);
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return HAL_OK;
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}
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HAL_Status HAL_CRU_ClkDisable(uint32_t clk)
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{
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const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
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uint32_t index = CLK_GATE_GET_REG_OFFSET(clk);
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uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk);
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uint32_t bank = CLK_GATE_GET_REG_BANK(clk);
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uint32_t reg;
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reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].gateOffset + index * 4;
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CRU_WRITE(reg, shift, 1U << shift, 1U);
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return HAL_OK;
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}
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HAL_Status HAL_CRU_ClkDisableUnused(uint32_t bank, uint32_t index, uint32_t val)
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{
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const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
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uint32_t reg;
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reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].gateOffset + index * 4;
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CRU_WRITE(reg, 0, 0, val);
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return HAL_OK;
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}
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HAL_Check HAL_CRU_ClkIsReset(uint32_t clk)
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{
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const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
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uint32_t index = CLK_GATE_GET_REG_OFFSET(clk);
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uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk);
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uint32_t bank = CLK_GATE_GET_REG_BANK(clk);
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uint32_t reg;
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HAL_Check ret;
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reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4;
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ret = (HAL_Check)((CRU_READ(reg) & (1 << shift)) >> shift);
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return ret;
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}
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HAL_Status HAL_CRU_ClkResetAssert(uint32_t clk)
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{
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const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
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uint32_t index = CLK_RESET_GET_REG_OFFSET(clk);
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uint32_t shift = CLK_RESET_GET_BITS_SHIFT(clk);
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uint32_t bank = CLK_GATE_GET_REG_BANK(clk);
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uint32_t reg;
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HAL_ASSERT(shift < 16);
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reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4;
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CRU_WRITE(reg, shift, 1U << shift, 1U);
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return HAL_OK;
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}
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HAL_Status HAL_CRU_ClkResetDeassert(uint32_t clk)
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{
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const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
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uint32_t index = CLK_RESET_GET_REG_OFFSET(clk);
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uint32_t shift = CLK_RESET_GET_BITS_SHIFT(clk);
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uint32_t bank = CLK_GATE_GET_REG_BANK(clk);
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uint32_t reg;
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HAL_ASSERT(shift < 16);
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reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4;
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CRU_WRITE(reg, shift, 1U << shift, 0U);
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return HAL_OK;
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}
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HAL_Status HAL_CRU_ClkResetSyncAssert(int numClks, uint32_t *clks)
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{
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const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
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uint32_t index = CLK_RESET_GET_REG_OFFSET(clks[0]);
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uint32_t bank = CLK_GATE_GET_REG_BANK(clks[0]);
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uint32_t val = 0;
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uint32_t reg;
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int i;
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for (i = 0; i < numClks; i++) {
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val |= HAL_BIT(CLK_RESET_GET_BITS_SHIFT(clks[i]));
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if (index != CLK_RESET_GET_REG_OFFSET(clks[i])) {
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return HAL_ERROR;
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}
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}
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reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4;
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CRU_WRITE(reg, 0, val, val);
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HAL_DBG("%s: index: 0x%lx, val: 0x%lx\n", __func__, index, val);
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return HAL_OK;
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}
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HAL_Status HAL_CRU_ClkResetSyncDeassert(int numClks, uint32_t *clks)
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{
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const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
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uint32_t index = CLK_RESET_GET_REG_OFFSET(clks[0]);
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uint32_t bank = CLK_GATE_GET_REG_BANK(clks[0]);
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uint32_t val = 0;
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uint32_t reg;
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int i;
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for (i = 0; i < numClks; i++) {
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val |= HAL_BIT(CLK_RESET_GET_BITS_SHIFT(clks[i]));
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if (index != CLK_RESET_GET_REG_OFFSET(clks[i])) {
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return HAL_ERROR;
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}
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}
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reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4;
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CRU_WRITE(reg, 0, val, 0);
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HAL_DBG("%s: index: 0x%lx, val: 0x%lx\n", __func__, index, val);
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return HAL_OK;
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}
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HAL_SECTION_SRAM_CODE
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HAL_Status HAL_CRU_ClkSetDiv(uint32_t divName, uint32_t divValue)
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{
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const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
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uint32_t shift, mask, index;
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uint32_t reg, bank, maxDiv;
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index = CLK_DIV_GET_REG_OFFSET(divName);
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shift = CLK_DIV_GET_BITS_SHIFT(divName);
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HAL_ASSERT(shift < 16);
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mask = CLK_DIV_GET_MASK(divName);
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maxDiv = CLK_DIV_GET_MAXDIV(divName) + 1;
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if (divValue > maxDiv) {
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divValue = maxDiv;
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}
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bank = CLK_DIV_GET_BANK(divName);
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reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4;
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CRU_WRITE(reg, shift, mask, (divValue - 1U));
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return HAL_OK;
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}
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uint32_t HAL_CRU_ClkGetDiv(uint32_t divName)
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{
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const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
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uint32_t shift, mask, index, divValue;
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uint32_t reg, bank;
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index = CLK_DIV_GET_REG_OFFSET(divName);
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shift = CLK_DIV_GET_BITS_SHIFT(divName);
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HAL_ASSERT(shift < 16);
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mask = CLK_DIV_GET_MASK(divName);
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bank = CLK_DIV_GET_BANK(divName);
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reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4;
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divValue = ((CRU_READ(reg) & mask) >> shift) + 1;
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return divValue;
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}
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HAL_SECTION_SRAM_CODE
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HAL_Status HAL_CRU_ClkSetMux(uint32_t muxName, uint32_t muxValue)
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{
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const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
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uint32_t shift, mask, index;
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uint32_t reg, bank;
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index = CLK_MUX_GET_REG_OFFSET(muxName);
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shift = CLK_MUX_GET_BITS_SHIFT(muxName);
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HAL_ASSERT(shift < 16);
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mask = CLK_MUX_GET_MASK(muxName);
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bank = CLK_MUX_GET_BANK(muxName);
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reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4;
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CRU_WRITE(reg, shift, mask, muxValue);
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return HAL_OK;
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}
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HAL_SECTION_SRAM_CODE
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uint32_t HAL_CRU_ClkGetMux(uint32_t muxName)
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{
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const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
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uint32_t shift, mask, index, muxValue;
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uint32_t reg, bank;
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index = CLK_MUX_GET_REG_OFFSET(muxName);
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shift = CLK_MUX_GET_BITS_SHIFT(muxName);
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HAL_ASSERT(shift < 16);
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mask = CLK_MUX_GET_MASK(muxName);
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bank = CLK_MUX_GET_BANK(muxName);
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reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4;
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muxValue = ((CRU_READ(reg) & mask) >> shift);
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return muxValue;
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}
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HAL_Status HAL_CRU_ClkSetFracDiv(uint32_t fracDivName,
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uint32_t numerator,
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uint32_t denominator)
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{
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const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
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uint32_t reg, bank;
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uint32_t index;
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index = CLK_DIV_GET_REG_OFFSET(fracDivName);
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bank = CLK_DIV_GET_BANK(fracDivName);
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reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4;
|
||||
CRU_WRITE(reg, 0, 0, ((numerator << 16) | denominator));
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
HAL_Status HAL_CRU_ClkGetFracDiv(uint32_t fracDivName,
|
||||
uint32_t *numerator,
|
||||
uint32_t *denominator)
|
||||
{
|
||||
const struct HAL_CRU_DEV *ctrl = CRU_GetInfo();
|
||||
uint32_t reg, bank;
|
||||
uint32_t index;
|
||||
uint32_t val;
|
||||
|
||||
index = CLK_DIV_GET_REG_OFFSET(fracDivName);
|
||||
bank = CLK_DIV_GET_BANK(fracDivName);
|
||||
reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4;
|
||||
val = CRU_READ(reg);
|
||||
|
||||
*numerator = (val & 0xffff0000) >> 16;
|
||||
*denominator = (val & 0x0000ffff);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
#else /* CRU_CLK_USE_CON_BANK */
|
||||
|
||||
HAL_Check HAL_CRU_ClkIsEnabled(uint32_t clk)
|
||||
{
|
||||
uint32_t index = CLK_GATE_GET_REG_OFFSET(clk);
|
||||
|
|
@ -1153,16 +1469,18 @@ HAL_Status HAL_CRU_ClkResetSyncDeassert(int numClks, uint32_t *clks)
|
|||
return HAL_OK;
|
||||
}
|
||||
|
||||
HAL_SECTION_SRAM_CODE
|
||||
HAL_Status HAL_CRU_ClkSetDiv(uint32_t divName, uint32_t divValue)
|
||||
{
|
||||
uint32_t shift, mask, index;
|
||||
uint32_t shift, mask, index, maxDiv;
|
||||
|
||||
index = CLK_DIV_GET_REG_OFFSET(divName);
|
||||
shift = CLK_DIV_GET_BITS_SHIFT(divName);
|
||||
HAL_ASSERT(shift < 16);
|
||||
mask = CLK_DIV_GET_MASK(divName);
|
||||
if (divValue > mask) {
|
||||
divValue = mask;
|
||||
maxDiv = CLK_DIV_GET_MAXDIV(divName) + 1;
|
||||
if (divValue > maxDiv) {
|
||||
divValue = maxDiv;
|
||||
}
|
||||
|
||||
#ifdef CRU_CLK_DIV_CON_CNT
|
||||
|
|
@ -1313,7 +1631,7 @@ HAL_Status HAL_CRU_ClkGetFracDiv(uint32_t fracDivName,
|
|||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
#endif /* CRU_CLK_USE_CON_BANK */
|
||||
|
||||
HAL_Status HAL_CRU_FracdivGetConfig(uint32_t rateOut, uint32_t rate,
|
||||
uint32_t *numerator,
|
||||
|
|
@ -1340,6 +1658,31 @@ HAL_Status HAL_CRU_FracdivGetConfig(uint32_t rateOut, uint32_t rate,
|
|||
return HAL_OK;
|
||||
}
|
||||
|
||||
HAL_Status HAL_CRU_FracdivGetConfigV2(uint32_t rateOut, uint32_t rate,
|
||||
uint32_t *numerator,
|
||||
uint32_t *denominator)
|
||||
{
|
||||
uint32_t gcdVal;
|
||||
|
||||
gcdVal = CRU_Gcd(rate, rateOut);
|
||||
if (!gcdVal) {
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
*numerator = rateOut / gcdVal;
|
||||
*denominator = rate / gcdVal;
|
||||
|
||||
if (*numerator < 4) {
|
||||
*numerator *= 4;
|
||||
*denominator *= 4;
|
||||
}
|
||||
if (*numerator > 0xffffff || *denominator > 0xffffff) {
|
||||
return HAL_INVAL;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
HAL_Status HAL_CRU_ClkNp5BestDiv(eCLOCK_Name clockName, uint32_t rate, uint32_t pRate, uint32_t *bestdiv)
|
||||
{
|
||||
uint32_t div = CLK_GET_DIV(clockName);
|
||||
|
|
|
|||
|
|
@ -874,6 +874,23 @@ uint32_t HAL_CRU_ClkGetFreq(eCLOCK_Name clockName)
|
|||
}
|
||||
|
||||
return freq;
|
||||
case CLK_SDMMC0:
|
||||
if (HAL_CRU_ClkGetMux(clkMux) == 1) {
|
||||
freq = 400000000;
|
||||
} else if (HAL_CRU_ClkGetMux(clkMux) == 2) {
|
||||
freq = 300000000;
|
||||
} else if (HAL_CRU_ClkGetMux(clkMux) == 3) {
|
||||
freq = 100000000;
|
||||
} else if (HAL_CRU_ClkGetMux(clkMux) == 4) {
|
||||
freq = 50000000;
|
||||
} else if (HAL_CRU_ClkGetMux(clkMux) == 5) {
|
||||
freq = 750000;
|
||||
} else {
|
||||
freq = PLL_INPUT_OSC_RATE;
|
||||
}
|
||||
|
||||
return freq;
|
||||
|
||||
case ACLK_USB:
|
||||
case HCLK_USB:
|
||||
case PCLK_USB:
|
||||
|
|
@ -1002,6 +1019,22 @@ HAL_Status HAL_CRU_ClkSetFreq(eCLOCK_Name clockName, uint32_t rate)
|
|||
mux = 0;
|
||||
}
|
||||
|
||||
break;
|
||||
case CLK_SDMMC0:
|
||||
if (rate == 400000000) {
|
||||
mux = 1;
|
||||
} else if (rate == 750000) {
|
||||
mux = 5;
|
||||
} else if (rate == 50000000) {
|
||||
mux = 4;
|
||||
} else if (rate == 100000000) {
|
||||
mux = 3;
|
||||
} else if (rate == 300000000) {
|
||||
mux = 2;
|
||||
} else {
|
||||
mux = 0;
|
||||
}
|
||||
|
||||
break;
|
||||
case ACLK_USB:
|
||||
case HCLK_USB:
|
||||
|
|
|
|||
|
|
@ -283,7 +283,9 @@
|
|||
#define GMAC_DESC3_FD (0x1 << 29)
|
||||
#define GMAC_DESC3_LD (0x1 << 28)
|
||||
#define GMAC_DESC3_BUF1V (0x1 << 24)
|
||||
#define GMAC_DESC3_CIC (0x3 << 16)
|
||||
|
||||
#define DES3_ERROR_SUMMARY (1 << 15)
|
||||
#define DES3_ERROR_SUMMARY (1 << 15)
|
||||
|
||||
/* Generic MII registers. */
|
||||
|
|
@ -1123,7 +1125,7 @@ int32_t HAL_GMAC_MDIORead(struct GMAC_HANDLE *pGMAC, int32_t mdioAddr,
|
|||
|
||||
HAL_ASSERT(pGMAC != NULL);
|
||||
|
||||
HAL_DBG("Mdio Read addr=%ld, reg=%ld\n", mdioAddr, mdioReg);
|
||||
// HAL_DBG("Mdio Read addr=%ld, reg=%ld\n", mdioAddr, mdioReg);
|
||||
status = Mdio_WaitIdle(pGMAC);
|
||||
if (status) {
|
||||
HAL_DBG("MDIO not idle at entry");
|
||||
|
|
@ -1173,8 +1175,8 @@ HAL_Status HAL_GMAC_MDIOWrite(struct GMAC_HANDLE *pGMAC, int32_t mdioAddr,
|
|||
|
||||
HAL_ASSERT(pGMAC != NULL);
|
||||
|
||||
HAL_DBG("%s(addr=%lx, reg=%ld, val=%x):\n", __func__,
|
||||
mdioAddr, mdioReg, mdioVal);
|
||||
// HAL_DBG("%s(addr=%lx, reg=%ld, val=%x):\n", __func__,
|
||||
// mdioAddr, mdioReg, mdioVal);
|
||||
status = Mdio_WaitIdle(pGMAC);
|
||||
if (status) {
|
||||
HAL_DBG("MDIO not idle at entry");
|
||||
|
|
@ -1347,7 +1349,6 @@ HAL_Status HAL_GMAC_PHYParseLink(struct GMAC_HANDLE *pGMAC)
|
|||
if (pGMAC->phyStatus.neg == PHY_AUTONEG_ENABLE) {
|
||||
uint32_t lpa = 0, estatus = 0;
|
||||
int32_t gblpa = 0;
|
||||
|
||||
/* Check for gigabit capability */
|
||||
if (pGMAC->phyStatus.supported & (HAL_GMAC_PHY_SUPPORTED_1000baseT_Full |
|
||||
HAL_GMAC_PHY_SUPPORTED_1000baseT_Half)) {
|
||||
|
|
@ -1746,6 +1747,13 @@ HAL_Status HAL_GMAC_AdjustLink(struct GMAC_HANDLE *pGMAC, int32_t txDelay,
|
|||
*
|
||||
* @return HAL status
|
||||
*/
|
||||
#define GENMASK(h, l) (((1U << ((h) - (l) + 1)) - 1) << (l))
|
||||
#define DMA_AXI_WR_OSR_LMT GENMASK(27, 24)
|
||||
#define DMA_AXI_WR_OSR_LMT_SHIFT 24
|
||||
#define DMA_AXI_RD_OSR_LMT GENMASK(19, 16)
|
||||
#define DMA_AXI_RD_OSR_LMT_SHIFT 16
|
||||
#define DMA_AXI_OSR_MAX 0xf
|
||||
|
||||
HAL_Status HAL_GMAC_Start(struct GMAC_HANDLE *pGMAC, uint8_t *addr)
|
||||
{
|
||||
uint32_t mmc_mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
|
||||
|
|
@ -1764,6 +1772,7 @@ HAL_Status HAL_GMAC_Start(struct GMAC_HANDLE *pGMAC, uint8_t *addr)
|
|||
value = READ_REG(pGMAC->pReg->DMA_MODE);
|
||||
WRITE_REG(pGMAC->pReg->DMA_MODE, value | DMA_MODE_SWR);
|
||||
/* Wait for software Reset */
|
||||
HAL_DelayMs(100);
|
||||
while (limit--) {
|
||||
if (!(READ_REG(pGMAC->pReg->DMA_MODE) & DMA_MODE_SWR)) {
|
||||
break;
|
||||
|
|
@ -1777,10 +1786,16 @@ HAL_Status HAL_GMAC_Start(struct GMAC_HANDLE *pGMAC, uint8_t *addr)
|
|||
}
|
||||
|
||||
HAL_DelayMs(100);
|
||||
value = READ_REG(pGMAC->pReg->DMA_SYSBUS_MODE);
|
||||
value &= ~DMA_AXI_WR_OSR_LMT;
|
||||
value |= (0x0 & DMA_AXI_OSR_MAX) << DMA_AXI_WR_OSR_LMT_SHIFT;
|
||||
|
||||
value &= ~DMA_AXI_RD_OSR_LMT;
|
||||
value |= (0x2 & DMA_AXI_OSR_MAX) << DMA_AXI_RD_OSR_LMT_SHIFT;
|
||||
|
||||
/* DMA init */
|
||||
WRITE_REG(pGMAC->pReg->DMA_SYSBUS_MODE, DMA_SYSBUS_MODE_BLEN16 |
|
||||
DMA_SYSBUS_MODE_BLEN8 | DMA_SYSBUS_MODE_BLEN4 | 1 << 12 | 1 << 14);
|
||||
WRITE_REG(pGMAC->pReg->DMA_SYSBUS_MODE, value | DMA_SYSBUS_MODE_BLEN16 |
|
||||
DMA_SYSBUS_MODE_BLEN8 | DMA_SYSBUS_MODE_BLEN4);
|
||||
|
||||
/* Mask interrupts by writing to CSR7 */
|
||||
WRITE_REG(pGMAC->pReg->DMA_CH0_INTERRUPT_ENABLE, DMA_CHAN_INTR_DEFAULT_MASK);
|
||||
|
|
@ -1789,6 +1804,7 @@ HAL_Status HAL_GMAC_Start(struct GMAC_HANDLE *pGMAC, uint8_t *addr)
|
|||
/* Set the HW DMA mode and the COE */
|
||||
txFifosz = 128 << ((hwCap & GMAC_HW_TXFIFOSIZE) >> GMAC_HW_TXFIFOSIZE_SHIFT);
|
||||
rxFifosz = 128 << ((hwCap & GMAC_HW_RXFIFOSIZE) >> GMAC_HW_RXFIFOSIZE_SHIFT);
|
||||
|
||||
|
||||
/* init rx chan */
|
||||
value = READ_REG(pGMAC->pReg->DMA_CH0_RX_CONTROL);
|
||||
|
|
@ -1800,9 +1816,13 @@ HAL_Status HAL_GMAC_Start(struct GMAC_HANDLE *pGMAC, uint8_t *addr)
|
|||
WRITE_REG(pGMAC->pReg->DMA_CH0_RXDESC_TAIL_POINTER,
|
||||
(uint32_t)(uint64_t)(pGMAC->rxDescs_dma + pGMAC->rxSize));
|
||||
|
||||
value = READ_REG(pGMAC->pReg->DMA_CH0_CONTROL);
|
||||
value = value | 1 << 16;
|
||||
WRITE_REG(pGMAC->pReg->DMA_CH0_CONTROL, value);
|
||||
|
||||
/* init tx chan */
|
||||
value = READ_REG(pGMAC->pReg->DMA_CH0_TX_CONTROL);
|
||||
value = value | (8 << DMA_CH0_TX_CONTROL_TXPBL_SHIFT);
|
||||
value = value | (32 << DMA_CH0_TX_CONTROL_TXPBL_SHIFT);
|
||||
value |= DMA_CH0_TX_CONTROL_OSF;
|
||||
WRITE_REG(pGMAC->pReg->DMA_CH0_TX_CONTROL, value);
|
||||
|
||||
|
|
@ -2002,7 +2022,7 @@ HAL_Status HAL_GMAC_Send(struct GMAC_HANDLE *pGMAC, void *packet,
|
|||
|
||||
desc->des0 = (uint32_t)(uint64_t)packet;
|
||||
desc->des1 = 0;
|
||||
desc->des2 = length;
|
||||
desc->des2 = length | 1<<31;
|
||||
/*
|
||||
* Make sure that if HW sees the _OWN write below, it will see all the
|
||||
* writes to the rest of the descriptor too.
|
||||
|
|
@ -2046,10 +2066,9 @@ uint8_t *HAL_GMAC_Recv(struct GMAC_HANDLE *pGMAC, int32_t *length)
|
|||
|
||||
*length = 0;
|
||||
desc = pGMAC->rxDescs + pGMAC->rxDescIdx;
|
||||
HAL_DBG("Rx at %p\n", desc->des0);
|
||||
des3 = desc->des3;
|
||||
if (des3 & GMAC_DESC3_OWN) {
|
||||
HAL_DBG("%s: RX packet not available\n", __func__);
|
||||
HAL_DBG("%p: RX packet not available\n", desc->des0);
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
|
@ -2106,10 +2125,9 @@ void HAL_GMAC_CleanRX(struct GMAC_HANDLE *pGMAC)
|
|||
desc->des1 = 0;
|
||||
desc->des2 = 0;
|
||||
desc->des3 = GMAC_DESC3_OWN | GMAC_DESC3_BUF1V | GMAC_DESC3_IOC;
|
||||
HAL_DBG("Clean buff %p\n", desc->des0);
|
||||
desc_dma = pGMAC->rxDescs_dma + pGMAC->rxDescIdx;
|
||||
HAL_DBG("Clean desc %p\n", desc_dma);
|
||||
WRITE_REG(pGMAC->pReg->DMA_CH0_RXDESC_TAIL_POINTER, (uint32_t)(uint64_t)desc_dma);
|
||||
|
||||
WRITE_REG(pGMAC->pReg->DMA_CH0_RXDESC_TAIL_POINTER,
|
||||
(uint32_t)(uint64_t)(pGMAC->rxDescs_dma + pGMAC->rxDescIdx));
|
||||
|
||||
pGMAC->rxDescIdx++;
|
||||
pGMAC->rxDescIdx %= pGMAC->rxSize;
|
||||
|
|
@ -2172,7 +2190,6 @@ HAL_Status HAL_GMAC_Init(struct GMAC_HANDLE *pGMAC, struct GMAC_REG *pReg,
|
|||
|
||||
pGMAC->txDescIdx = 0;
|
||||
pGMAC->rxDescIdx = 0;
|
||||
|
||||
/* Get CR bits depending on hclk value */
|
||||
if ((freq >= 20000000) && (freq < 35000000)) {
|
||||
/* CSR Clock Range between 20-35 MHz */
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@
|
|||
*/
|
||||
static void GPIO_SetEOI(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
|
||||
{
|
||||
#if (GPIO_VER_ID == 0x01000C2BU)
|
||||
#if (GPIO_VER_ID >= 0x01000C2BU)
|
||||
if (IS_GPIO_HIGH_PIN(pin)) {
|
||||
pin &= 0xFFFF0000;
|
||||
pGPIO->PORT_EOI_H = pin | (pin >> 16);
|
||||
|
|
@ -82,7 +82,7 @@ static uint32_t GPIO_GetIntType(struct GPIO_REG *pGPIO)
|
|||
{
|
||||
uint32_t type;
|
||||
|
||||
#if (GPIO_VER_ID == 0x01000C2BU)
|
||||
#if (GPIO_VER_ID >= 0x01000C2BU)
|
||||
type = (pGPIO->INT_TYPE_L & 0xffff);
|
||||
type |= ((pGPIO->INT_TYPE_H & 0xffff) << 16);
|
||||
type |= (pGPIO->INT_BOTHEDGE_L & 0xffff);
|
||||
|
|
@ -161,7 +161,7 @@ HAL_Status HAL_GPIO_SetIntType(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, e
|
|||
return HAL_INVAL;
|
||||
}
|
||||
|
||||
#if (GPIO_VER_ID == 0x01000C2BU)
|
||||
#if (GPIO_VER_ID >= 0x01000C2BU)
|
||||
if (IS_GPIO_HIGH_PIN(pin)) {
|
||||
pin &= 0xFFFF0000;
|
||||
pGPIO->INT_TYPE_H = (type) ? (pin | (pin >> 16)) : (pin);
|
||||
|
|
@ -195,7 +195,7 @@ HAL_Status HAL_GPIO_SetIntType(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, e
|
|||
*/
|
||||
HAL_Status HAL_GPIO_SetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinDirection direction)
|
||||
{
|
||||
#if (GPIO_VER_ID == 0x01000C2BU)
|
||||
#if (GPIO_VER_ID >= 0x01000C2BU)
|
||||
if (IS_GPIO_HIGH_PIN(pin)) {
|
||||
pin &= 0xFFFF0000;
|
||||
pGPIO->SWPORT_DDR_H = (direction == GPIO_OUT) ? (pin | (pin >> 16)) : (pin);
|
||||
|
|
@ -251,7 +251,7 @@ eGPIO_pinDirection HAL_GPIO_GetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPI
|
|||
eGPIO_pinDirection direction;
|
||||
uint32_t value;
|
||||
|
||||
#if (GPIO_VER_ID == 0x01000C2BU)
|
||||
#if (GPIO_VER_ID >= 0x01000C2BU)
|
||||
value = IS_GPIO_HIGH_PIN(pin) ? (pGPIO->SWPORT_DDR_H & (pin >> 16)) : (pGPIO->SWPORT_DDR_L & pin);
|
||||
#else
|
||||
value = pGPIO->SWPORTA_DDR & pin;
|
||||
|
|
@ -275,7 +275,7 @@ eGPIO_pinDirection HAL_GPIO_GetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPI
|
|||
*/
|
||||
HAL_Status HAL_GPIO_SetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinLevel level)
|
||||
{
|
||||
#if (GPIO_VER_ID == 0x01000C2BU)
|
||||
#if (GPIO_VER_ID >= 0x01000C2BU)
|
||||
if (IS_GPIO_HIGH_PIN(pin)) {
|
||||
pin &= 0xFFFF0000;
|
||||
pGPIO->SWPORT_DR_H = (level == GPIO_HIGH) ? (pin | (pin >> 16)) : (pin);
|
||||
|
|
@ -340,7 +340,7 @@ eGPIO_pinLevel HAL_GPIO_GetPinData(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pi
|
|||
eGPIO_pinLevel level;
|
||||
uint32_t value;
|
||||
|
||||
#if (GPIO_VER_ID == 0x01000C2BU)
|
||||
#if (GPIO_VER_ID >= 0x01000C2BU)
|
||||
value = IS_GPIO_HIGH_PIN(pin) ? (pGPIO->SWPORT_DR_H & (pin >> 16)) : (pGPIO->SWPORT_DR_L & pin);
|
||||
#else
|
||||
value = pGPIO->SWPORTA_DR & pin;
|
||||
|
|
@ -365,7 +365,7 @@ eGPIO_pinLevel HAL_GPIO_GetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS p
|
|||
{
|
||||
uint32_t value;
|
||||
|
||||
#if (GPIO_VER_ID == 0x01000C2BU)
|
||||
#if (GPIO_VER_ID >= 0x01000C2BU)
|
||||
value = (pGPIO->EXT_PORT & pin);
|
||||
#else
|
||||
value = (pGPIO->EXT_PORTA & pin);
|
||||
|
|
@ -383,7 +383,7 @@ uint32_t HAL_GPIO_GetBankLevel(struct GPIO_REG *pGPIO)
|
|||
{
|
||||
uint32_t value;
|
||||
|
||||
#if (GPIO_VER_ID == 0x01000C2BU)
|
||||
#if (GPIO_VER_ID >= 0x01000C2BU)
|
||||
value = (pGPIO->EXT_PORT);
|
||||
#else
|
||||
value = (pGPIO->EXT_PORTA);
|
||||
|
|
@ -404,7 +404,7 @@ uint32_t HAL_GPIO_GetBankLevel(struct GPIO_REG *pGPIO)
|
|||
*/
|
||||
void HAL_GPIO_EnableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
|
||||
{
|
||||
#if (GPIO_VER_ID == 0x01000C2BU)
|
||||
#if (GPIO_VER_ID >= 0x01000C2BU)
|
||||
if (IS_GPIO_HIGH_PIN(pin)) {
|
||||
pin &= 0xFFFF0000;
|
||||
#ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED
|
||||
|
|
@ -433,7 +433,7 @@ void HAL_GPIO_EnableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
|
|||
*/
|
||||
void HAL_GPIO_DisableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
|
||||
{
|
||||
#if (GPIO_VER_ID == 0x01000C2BU)
|
||||
#if (GPIO_VER_ID >= 0x01000C2BU)
|
||||
if (IS_GPIO_HIGH_PIN(pin)) {
|
||||
pin &= 0xFFFF0000;
|
||||
pGPIO->INT_EN_H = pin;
|
||||
|
|
@ -511,7 +511,7 @@ void HAL_GPIO_IRQHandler(struct GPIO_REG *pGPIO, eGPIO_bankId bank)
|
|||
*/
|
||||
HAL_Status HAL_GPIO_EnableVirtualModel(struct GPIO_REG *pGPIO)
|
||||
{
|
||||
#if (GPIO_VER_ID == 0x01000C2BU)
|
||||
#if (GPIO_VER_ID >= 0x01000C2BU)
|
||||
pGPIO->GPIO_VIRTUAL_EN = 0x10001;
|
||||
|
||||
return HAL_OK;
|
||||
|
|
@ -527,7 +527,7 @@ HAL_Status HAL_GPIO_EnableVirtualModel(struct GPIO_REG *pGPIO)
|
|||
*/
|
||||
HAL_Status HAL_GPIO_DisableVirtualModel(struct GPIO_REG *pGPIO)
|
||||
{
|
||||
#if (GPIO_VER_ID == 0x01000C2BU)
|
||||
#if (GPIO_VER_ID >= 0x01000C2BU)
|
||||
pGPIO->GPIO_VIRTUAL_EN = 0x10000;
|
||||
|
||||
return HAL_OK;
|
||||
|
|
@ -545,22 +545,51 @@ HAL_Status HAL_GPIO_DisableVirtualModel(struct GPIO_REG *pGPIO)
|
|||
*/
|
||||
HAL_Status HAL_GPIO_SetVirtualModel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_VirtualModel vmodel)
|
||||
{
|
||||
#if (GPIO_VER_ID == 0x01000C2BU)
|
||||
uint32_t low_pins, high_pins;
|
||||
#if (GPIO_VER_ID >= 0x01000C2BU)
|
||||
uint32_t lowPins, highPins;
|
||||
|
||||
low_pins = pin & 0x0000ffff;
|
||||
high_pins = (pin & 0xffff0000) >> 16;
|
||||
lowPins = pin & 0x0000ffff;
|
||||
highPins = (pin & 0xffff0000) >> 16;
|
||||
|
||||
#if defined(GPIO0_EXP)
|
||||
/* Support OS_A and OS_B */
|
||||
if (vmodel == GPIO_VIRTUAL_MODEL_OS_B) {
|
||||
pGPIO->GPIO_REG_GROUP_L = low_pins << 16;
|
||||
pGPIO->GPIO_REG_GROUP_H = high_pins << 16;
|
||||
pGPIO->GPIO_REG_GROUP_L = lowPins << 16;
|
||||
pGPIO->GPIO_REG_GROUP_H = highPins << 16;
|
||||
} else {
|
||||
pGPIO->GPIO_REG_GROUP_L = low_pins | (low_pins << 16);
|
||||
pGPIO->GPIO_REG_GROUP_H = high_pins | (high_pins << 16);
|
||||
pGPIO->GPIO_REG_GROUP_L = lowPins | (lowPins << 16);
|
||||
pGPIO->GPIO_REG_GROUP_H = highPins | (highPins << 16);
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
#elif defined(GPIO0_EXP3)
|
||||
/* Support 4 OS */
|
||||
switch (vmodel) {
|
||||
case GPIO_VIRTUAL_MODEL_OS_A:
|
||||
pGPIO->GPIO_REG_GROUP_L = lowPins | (lowPins << 16);
|
||||
pGPIO->GPIO_REG_GROUP_H = highPins | (highPins << 16);
|
||||
break;
|
||||
case GPIO_VIRTUAL_MODEL_OS_B:
|
||||
pGPIO->GPIO_REG_GROUP1_L = lowPins | (lowPins << 16);
|
||||
pGPIO->GPIO_REG_GROUP1_H = highPins | (highPins << 16);
|
||||
break;
|
||||
case GPIO_VIRTUAL_MODEL_OS_C:
|
||||
pGPIO->GPIO_REG_GROUP2_L = lowPins | (lowPins << 16);
|
||||
pGPIO->GPIO_REG_GROUP2_H = highPins | (highPins << 16);
|
||||
break;
|
||||
case GPIO_VIRTUAL_MODEL_OS_D:
|
||||
pGPIO->GPIO_REG_GROUP3_L = lowPins | (lowPins << 16);
|
||||
pGPIO->GPIO_REG_GROUP3_H = highPins | (highPins << 16);
|
||||
break;
|
||||
default:
|
||||
HAL_DBG("unknown gpio virtual model-%d\n", vmodel);
|
||||
break;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
#else
|
||||
#error missing GPIO EXP register definition!
|
||||
#endif
|
||||
#endif
|
||||
|
||||
return HAL_ERROR;
|
||||
|
|
|
|||
|
|
@ -85,7 +85,7 @@ struct GMAC_ETH_CONFIG {
|
|||
/********************* Private Variable Definition ***************************/
|
||||
|
||||
|
||||
static uint8_t dstAddr[6] = { 0x00, 0x0C, 0x29, 0xf8, 0x7a, 0x6b };
|
||||
static uint8_t dstAddr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
|
||||
|
||||
#if defined(HAL_GMAC_MODULE_ENABLED) && defined(SOC_RK3568)
|
||||
static struct GMAC_ETH_CONFIG ethConfigTable[] =
|
||||
|
|
@ -349,7 +349,6 @@ static void *malloc_align(size_t size, size_t align, uintptr_t va, uintptr_t *pa
|
|||
/* get total aligned size */
|
||||
align_size = ((size + 0x03) & ~0x03);
|
||||
/* allocate memory block from heap */
|
||||
HAL_DBG("size: %d, align:%d\n",align_size, align);
|
||||
// ptr = malloc(align_size);
|
||||
|
||||
if (naive_mmap(&va, pa, align_size, true) < 0){
|
||||
|
|
@ -417,7 +416,7 @@ static HAL_Status GMAC_Send_Test(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE
|
|||
}
|
||||
|
||||
/* dump packages */
|
||||
// Dump_Hex("Tx", ptr, len);
|
||||
Dump_Hex("Tx", ptr, len);
|
||||
|
||||
// HAL_DCACHE_CleanByRange((uint64_t)ptr, len);
|
||||
uint8_t * ptr_dma = (uint8_t *)HAL_GMAC_GetTXBufferDMA(pGMAC);
|
||||
|
|
@ -426,7 +425,6 @@ static HAL_Status GMAC_Send_Test(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE
|
|||
printf("GMAC send failed: %d\n", status);
|
||||
}
|
||||
|
||||
print_desc(pGMAC);
|
||||
return status;
|
||||
}
|
||||
|
||||
|
|
@ -444,7 +442,6 @@ static uint16_t GMAC_Recv_Test(struct GMAC_HANDLE *pGMAC)
|
|||
status = GMAC_ETH_IRQ(pGMAC);
|
||||
ptr = HAL_GMAC_Recv(pGMAC, &size);
|
||||
while (status && ptr) {
|
||||
print_desc(pGMAC);
|
||||
if (size > 0 && ptr) {
|
||||
/* dump packages */
|
||||
Dump_Hex("Rx", ptr, size);
|
||||
|
|
@ -462,20 +459,21 @@ static uint16_t GMAC_Recv_Test(struct GMAC_HANDLE *pGMAC)
|
|||
|
||||
static HAL_Status GMAC_Memory_Init(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE *pGMAC)
|
||||
{
|
||||
uintptr_t rx_va = 0x1000000000, rx_pa = 0;
|
||||
if (naive_mmap(&rx_va, &rx_pa, GMAC_DESC_RX_SIZE, true) < 0){
|
||||
HAL_DBG("RX Desc alloc failed\n");
|
||||
}
|
||||
eth->rxDescs = (struct GMAC_Desc *)0x1000000000;
|
||||
eth->rxDescs_dma = (struct GMAC_Desc *)rx_pa;
|
||||
|
||||
uintptr_t tx_va = 0x1000400000, tx_pa = 0;
|
||||
uintptr_t tx_va = 0x1000000000, tx_pa = 0;
|
||||
if (naive_mmap(&tx_va, &tx_pa, GMAC_DESC_TX_SIZE, true) < 0){
|
||||
HAL_DBG("TX Desc alloc failed\n");
|
||||
}
|
||||
eth->txDescs = (struct GMAC_Desc *)0x1000400000;
|
||||
eth->txDescs = (struct GMAC_Desc *)0x1000000000;
|
||||
eth->txDescs_dma = (struct GMAC_Desc *)tx_pa;
|
||||
|
||||
uintptr_t rx_va = 0x1000400000, rx_pa = 0;
|
||||
if (naive_mmap(&rx_va, &rx_pa, GMAC_DESC_RX_SIZE, true) < 0){
|
||||
HAL_DBG("RX Desc alloc failed\n");
|
||||
}
|
||||
eth->rxDescs = (struct GMAC_Desc *)0x1000400000;
|
||||
eth->rxDescs_dma = (struct GMAC_Desc *)rx_pa;
|
||||
|
||||
if (!eth->rxDescs || !eth->txDescs_dma ||
|
||||
!eth->txDescs || !eth->txDescs_dma){
|
||||
return -1;
|
||||
|
|
@ -484,14 +482,16 @@ static HAL_Status GMAC_Memory_Init(struct GMAC_ETH_CONFIG *eth, struct GMAC_HAND
|
|||
HAL_DBG("rx:%p, %p\n",eth->rxDescs, eth->rxDescs_dma);
|
||||
HAL_DBG("tx:%p, %p\n",eth->txDescs, eth->txDescs_dma);
|
||||
|
||||
uintptr_t rxbuf_va = 0x1000800000, rxbuf_pa = 0;
|
||||
uintptr_t txbuf_va = 0x1000C00000, txbuf_pa = 0;
|
||||
eth->rxBuff = malloc_align(GMAC_RX_BUFFER_SIZE, ARCH_DMA_MINALIGN, rxbuf_va, &rxbuf_pa);
|
||||
eth->rxBuff = (void *)0x1000800000;
|
||||
eth->rxBuff_dma = (void *)rxbuf_pa;
|
||||
|
||||
uintptr_t txbuf_va = 0x1000800000, txbuf_pa = 0;
|
||||
eth->txBuff = malloc_align(GMAC_TX_BUFFER_SIZE, ARCH_DMA_MINALIGN, txbuf_va, &txbuf_pa);
|
||||
eth->txBuff = (void *)0x1000C00000;
|
||||
eth->txBuff = (void *)0x1000800000;
|
||||
eth->txBuff_dma = (void *)txbuf_pa;
|
||||
|
||||
uintptr_t rxbuf_va = 0x1000c00000, rxbuf_pa = 0;
|
||||
eth->rxBuff = malloc_align(GMAC_RX_BUFFER_SIZE, ARCH_DMA_MINALIGN, rxbuf_va, &rxbuf_pa);
|
||||
eth->rxBuff = (void *)0x1000c00000;
|
||||
eth->rxBuff_dma = (void *)rxbuf_pa;
|
||||
|
||||
if (!eth->rxBuff || !eth->txBuff ||
|
||||
!eth->rxBuff_dma || !eth->txBuff_dma){
|
||||
|
|
@ -499,8 +499,6 @@ static HAL_Status GMAC_Memory_Init(struct GMAC_ETH_CONFIG *eth, struct GMAC_HAND
|
|||
}
|
||||
HAL_DBG("rx_buff:%p,%p\n",eth->rxBuff, eth->rxBuff_dma);
|
||||
HAL_DBG("tx_buff:%p,%p,\n",eth->txBuff, eth->txBuff_dma);
|
||||
HAL_DBG("GMAC_DESC_RX_SIZE:%d\n", GMAC_DESC_RX_SIZE);
|
||||
HAL_DBG("GMAC_RX_BUFFER_SIZE:%d\n", GMAC_RX_BUFFER_SIZE);
|
||||
memset(eth->rxDescs, 0, GMAC_DESC_RX_SIZE);
|
||||
memset(eth->txDescs, 0, GMAC_DESC_TX_SIZE);
|
||||
memset(eth->rxBuff, 0, GMAC_RX_BUFFER_SIZE);
|
||||
|
|
@ -540,9 +538,9 @@ static HAL_Status GMAC_Init(uint8_t id)
|
|||
interface = eth->mode;
|
||||
|
||||
if (interface == PHY_INTERFACE_MODE_RGMII) {
|
||||
HAL_CRU_ClkSetFreq(gmacDev->clkID, 125000000);
|
||||
HAL_CRU_ClkSetFreq(gmacDev->clkID125M, 125000000);
|
||||
} else {
|
||||
HAL_CRU_ClkSetFreq(gmacDev->clkID, 50000000);
|
||||
HAL_CRU_ClkSetFreq(gmacDev->clkID50M, 50000000);
|
||||
}
|
||||
|
||||
freq = HAL_CRU_ClkGetFreq(gmacDev->pclkID);
|
||||
|
|
@ -583,7 +581,6 @@ static void GMAC0_Iomux_Config(void)
|
|||
GPIO_PIN_B6, /* gmac0_rxd0 */
|
||||
PIN_CONFIG_MUX_FUNC1);
|
||||
HAL_PINCTRL_SetIOMUX(GPIO_BANK2,
|
||||
GPIO_PIN_C0 | ///* eth0_refclko25m */
|
||||
GPIO_PIN_C3 | /* gmac0_mdc */
|
||||
GPIO_PIN_C4 | /* gmac0_mdio */
|
||||
GPIO_PIN_C0 | /* gmac0_rxdvcrs */
|
||||
|
|
@ -646,19 +643,19 @@ int main() {
|
|||
} else {
|
||||
return -1;
|
||||
}
|
||||
HAL_DBG("map GMAC0\n");
|
||||
|
||||
if (!mmap(0x2000000000ULL+ GMAC0_BASE, GMAC0_BASE, 0x10000, true)) {
|
||||
printf("eth_hal: mmap GMAC0(%8x) failed\n", GMAC0);
|
||||
exit(1);
|
||||
}
|
||||
HAL_DBG("map GPIO2\n");
|
||||
|
||||
if (!mmap(0x2000000000ULL + GPIO2_BASE, GPIO2_BASE, 0x10000, true)) {
|
||||
printf("eth_hal: mmap GPIO2(%8x) failed\n", GPIO2);
|
||||
exit(1);
|
||||
}
|
||||
HAL_DBG("map GPIO3\n");
|
||||
|
||||
if (!mmap(0x2000000000ULL + GPIO3_BASE, GPIO3_BASE, 0x10000, true)) {
|
||||
printf("eth_hal: mmap GPIO2(%8x) failed\n", GPIO2);
|
||||
printf("eth_hal: mmap GPIO3(%8x) failed\n", GPIO3);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
|
|
@ -668,65 +665,69 @@ int main() {
|
|||
}
|
||||
|
||||
if (!mmap(0x2000000000ULL + CRU_BASE, CRU_BASE, 0x10000, true)) {
|
||||
printf("eth_hal: mmap GRF(%8x) failed\n", GRF);
|
||||
printf("eth_hal: mmap CRU(%8x) failed\n", CRU);
|
||||
exit(1);
|
||||
}
|
||||
if (!mmap(0x2000000000ULL + TIMER5_BASE, CRU_BASE, 32, true)) {
|
||||
printf("eth_hal: mmap GRF(%8x) failed\n", GRF);
|
||||
if (!mmap(0x2000000000ULL + TIMER5_BASE, TIMER5_BASE, 32, true)) {
|
||||
printf("eth_hal: mmap TIMER5(%8x) failed\n", TIMER5);
|
||||
exit(1);
|
||||
}
|
||||
if (!mmap(0x2000000000ULL + PMUCRU_BASE, PMUCRU_BASE, 0x10000, true)) {
|
||||
printf("eth_hal: mmap GRF(%8x) failed\n", GRF);
|
||||
printf("eth_hal: mmap PMUCRU(%8x) failed\n", PMUCRU);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
HAL_DBG("config iomux\n");
|
||||
HAL_TIMER_SysTimerInit(TIMER5);
|
||||
|
||||
/* ionmux */
|
||||
GMAC_Iomux_Config(bus);
|
||||
HAL_DBG("config cru\n");
|
||||
HAL_CRU_ClkEnable(eth->halDev->pclkGateID);
|
||||
HAL_CRU_ClkEnable(eth->halDev->clkGateID);
|
||||
HAL_CRU_ClkEnable(eth->halDev->clkGateID125M);
|
||||
HAL_CRU_ClkEnable(eth->halDev->clkGateID50M);
|
||||
|
||||
/* Register irq */
|
||||
// register_irq(eth->halDev->irqNum, );
|
||||
/* PHY reset */
|
||||
HAL_DBG("reset phy\n");
|
||||
GMAC_PHY_Reset(eth);
|
||||
|
||||
/* GMAC Init */
|
||||
HAL_DBG("init gmac\n");
|
||||
GMAC_Init(bus);
|
||||
|
||||
HAL_DBG("init memory\n");
|
||||
GMAC_Memory_Init(eth, pGMAC);
|
||||
|
||||
/* Enable GMAC and DMA transmission and reception */
|
||||
HAL_DBG("start gmac\n");
|
||||
HAL_GMAC_Start(pGMAC, eth->macAddr);
|
||||
// print_desc(pGMAC);
|
||||
|
||||
/* Update links information */
|
||||
HAL_DBG("phy update link\n");
|
||||
PHY_Update_Links(eth, pGMAC, bus);
|
||||
// print_desc(pGMAC);
|
||||
|
||||
/* Dump MAC Regs */
|
||||
Dump_Regs(pGMAC);
|
||||
|
||||
/* Dump PHY Regs */
|
||||
// PHY_Dump(eth, pGMAC);
|
||||
HAL_DBG("Init Down\n");
|
||||
for (i = 0; i < GMAC_TEST_TIMES; i++) {
|
||||
HAL_DBG("TEST Send %d\n", i);
|
||||
HAL_DBG("TEST %d\n", i);
|
||||
|
||||
/* GMAC Send 64 bytes */
|
||||
// GMAC_Send_Test(eth, pGMAC, 64);
|
||||
/* GMAC Send 1500 bytes */
|
||||
GMAC_Send_Test(eth, pGMAC, 1500);
|
||||
HAL_DBG("--------------GMAC_Send_Test START!--------------\n");
|
||||
GMAC_Send_Test(eth, pGMAC, 64);
|
||||
HAL_DBG("--------------GMAC_Send_Test END!--------------\n");
|
||||
|
||||
HAL_DelayMs(1000);
|
||||
HAL_DBG("TEST Recv %d\n", i);
|
||||
print_desc(pGMAC);
|
||||
|
||||
/* GMAC Recv */
|
||||
HAL_DBG("--------------GMAC_Recv_Test START! -------------- \n");
|
||||
GMAC_Recv_Test(pGMAC);
|
||||
HAL_DBG("--------------GMAC_Recv_Test END!!-------------- \n");
|
||||
|
||||
HAL_DelayMs(1000);
|
||||
Dump_Regs(pGMAC);
|
||||
}
|
||||
Dump_Regs(pGMAC);
|
||||
HAL_CRU_ClkDisable(eth->halDev->pclkGateID);
|
||||
HAL_CRU_ClkDisable(eth->halDev->clkGateID);
|
||||
HAL_CRU_ClkDisable(eth->halDev->clkGateID125M);
|
||||
HAL_CRU_ClkDisable(eth->halDev->clkGateID50M);
|
||||
|
||||
// free_align(eth->txBuff);
|
||||
// free_align(eth->rxBuff);
|
||||
|
|
|
|||
|
|
@ -159,6 +159,11 @@ typedef enum {
|
|||
GLB_RST_SND_WDT1,
|
||||
GLB_RST_FST_WDT2,
|
||||
GLB_RST_SND_WDT2,
|
||||
GLB_RST_FST_WDT3,
|
||||
GLB_RST_SND_WDT3,
|
||||
GLB_RST_FST_WDT4,
|
||||
GLB_RST_SND_WDT4,
|
||||
|
||||
} eCRU_WdtRstType;
|
||||
|
||||
struct CRU_BANK_INFO {
|
||||
|
|
@ -192,12 +197,14 @@ int HAL_CRU_FreqGetMux4(uint32_t freq, uint32_t freq0, uint32_t freq1,
|
|||
int HAL_CRU_FreqGetMux3(uint32_t freq, uint32_t freq0, uint32_t freq1,
|
||||
uint32_t freq2);
|
||||
int HAL_CRU_FreqGetMux2(uint32_t freq, uint32_t freq0, uint32_t freq1);
|
||||
int HAL_CRU_FreqGetMuxArray(uint32_t freq, uint32_t *table, int num);
|
||||
|
||||
uint32_t HAL_CRU_MuxGetFreq4(uint32_t muxName, uint32_t freq0, uint32_t freq1,
|
||||
uint32_t freq2, uint32_t freq3);
|
||||
uint32_t HAL_CRU_MuxGetFreq3(uint32_t muxName, uint32_t freq0, uint32_t freq1,
|
||||
uint32_t freq2);
|
||||
uint32_t HAL_CRU_MuxGetFreq2(uint32_t muxName, uint32_t freq0, uint32_t freq1);
|
||||
uint32_t HAL_CRU_MuxGetFreqArray(uint32_t muxName, uint32_t *table, int num);
|
||||
|
||||
int HAL_CRU_RoundFreqGetMux4(uint32_t freq, uint32_t pFreq0, uint32_t pFreq1,
|
||||
uint32_t pFreq2, uint32_t pFreq3, uint32_t *pFreqOut);
|
||||
|
|
@ -205,6 +212,7 @@ int HAL_CRU_RoundFreqGetMux3(uint32_t freq, uint32_t pFreq0, uint32_t pFreq1,
|
|||
uint32_t pFreq2, uint32_t *pFreqOut);
|
||||
int HAL_CRU_RoundFreqGetMux2(uint32_t freq, uint32_t pFreq0, uint32_t pFreq1,
|
||||
uint32_t *pFreqOut);
|
||||
int HAL_CRU_RoundFreqGetMuxArray(uint32_t freq, uint32_t *table, int num, uint32_t *pFreqOut, bool is_div);
|
||||
|
||||
/** @} */
|
||||
|
||||
|
|
@ -371,6 +379,21 @@ uint32_t HAL_CRU_ClkGetMux(uint32_t muxName);
|
|||
HAL_Status HAL_CRU_FracdivGetConfig(uint32_t rateOut, uint32_t rate,
|
||||
uint32_t *numerator,
|
||||
uint32_t *denominator);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get frac div config V2(24bit).
|
||||
* @param rateOut: clk out rate.
|
||||
* @param rate: clk src rate.
|
||||
* @param numerator: the returned numerator.
|
||||
* @param denominator: the returned denominator.
|
||||
* @return HAL_Status.
|
||||
*/
|
||||
HAL_Status HAL_CRU_FracdivGetConfigV2(uint32_t rateOut, uint32_t rate,
|
||||
uint32_t *numerator,
|
||||
uint32_t *denominator);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get clk freq.
|
||||
* @param clockName: CLOCK_Name id.
|
||||
|
|
|
|||
|
|
@ -207,10 +207,10 @@ struct GMAC_Link {
|
|||
* @brief GMAC DMA Descriptors Data Structure Definition
|
||||
*/
|
||||
struct GMAC_Desc {
|
||||
uint32_t des0; /**< DMA Descriptors first word */
|
||||
uint32_t des1; /**< DMA Descriptors second word */
|
||||
uint32_t des2; /**< DMA Descriptors third word */
|
||||
uint32_t des3; /**< DMA Descriptors four word */
|
||||
volatile uint32_t des0; /**< DMA Descriptors first word */
|
||||
volatile uint32_t des1; /**< DMA Descriptors second word */
|
||||
volatile uint32_t des2; /**< DMA Descriptors third word */
|
||||
volatile uint32_t des3; /**< DMA Descriptors four word */
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -287,8 +287,10 @@ struct GMAC_HANDLE {
|
|||
*/
|
||||
struct HAL_GMAC_DEV {
|
||||
struct GMAC_REG *pReg;
|
||||
eCLOCK_Name clkID;
|
||||
uint32_t clkGateID;
|
||||
eCLOCK_Name clkID125M;
|
||||
eCLOCK_Name clkID50M;
|
||||
uint32_t clkGateID125M;
|
||||
uint32_t clkGateID50M;
|
||||
eCLOCK_Name pclkID;
|
||||
uint32_t pclkGateID;
|
||||
IRQn_Type irqNum;
|
||||
|
|
|
|||
|
|
@ -370,6 +370,516 @@ typedef enum {
|
|||
GPIO4_EXP_D5,
|
||||
GPIO4_EXP_D6,
|
||||
GPIO4_EXP_D7,
|
||||
#endif
|
||||
#if defined(GPIO0_EXP1)
|
||||
GPIO0_EXP1_A0 = 160,
|
||||
GPIO0_EXP1_A1,
|
||||
GPIO0_EXP1_A2,
|
||||
GPIO0_EXP1_A3,
|
||||
GPIO0_EXP1_A4,
|
||||
GPIO0_EXP1_A5,
|
||||
GPIO0_EXP1_A6,
|
||||
GPIO0_EXP1_A7,
|
||||
GPIO0_EXP1_B0 = 168,
|
||||
GPIO0_EXP1_B1,
|
||||
GPIO0_EXP1_B2,
|
||||
GPIO0_EXP1_B3,
|
||||
GPIO0_EXP1_B4,
|
||||
GPIO0_EXP1_B5,
|
||||
GPIO0_EXP1_B6,
|
||||
GPIO0_EXP1_B7,
|
||||
GPIO0_EXP1_C0 = 176,
|
||||
GPIO0_EXP1_C1,
|
||||
GPIO0_EXP1_C2,
|
||||
GPIO0_EXP1_C3,
|
||||
GPIO0_EXP1_C4,
|
||||
GPIO0_EXP1_C5,
|
||||
GPIO0_EXP1_C6,
|
||||
GPIO0_EXP1_C7,
|
||||
GPIO0_EXP1_D0 = 184,
|
||||
GPIO0_EXP1_D1,
|
||||
GPIO0_EXP1_D2,
|
||||
GPIO0_EXP1_D3,
|
||||
GPIO0_EXP1_D4,
|
||||
GPIO0_EXP1_D5,
|
||||
GPIO0_EXP1_D6,
|
||||
GPIO0_EXP1_D7,
|
||||
#endif
|
||||
#if defined(GPIO1_EXP1)
|
||||
GPIO1_EXP1_A0 = 192,
|
||||
GPIO1_EXP1_A1,
|
||||
GPIO1_EXP1_A2,
|
||||
GPIO1_EXP1_A3,
|
||||
GPIO1_EXP1_A4,
|
||||
GPIO1_EXP1_A5,
|
||||
GPIO1_EXP1_A6,
|
||||
GPIO1_EXP1_A7,
|
||||
GPIO1_EXP1_B0 = 200,
|
||||
GPIO1_EXP1_B1,
|
||||
GPIO1_EXP1_B2,
|
||||
GPIO1_EXP1_B3,
|
||||
GPIO1_EXP1_B4,
|
||||
GPIO1_EXP1_B5,
|
||||
GPIO1_EXP1_B6,
|
||||
GPIO1_EXP1_B7,
|
||||
GPIO1_EXP1_C0 = 208,
|
||||
GPIO1_EXP1_C1,
|
||||
GPIO1_EXP1_C2,
|
||||
GPIO1_EXP1_C3,
|
||||
GPIO1_EXP1_C4,
|
||||
GPIO1_EXP1_C5,
|
||||
GPIO1_EXP1_C6,
|
||||
GPIO1_EXP1_C7,
|
||||
GPIO1_EXP1_D0 = 216,
|
||||
GPIO1_EXP1_D1,
|
||||
GPIO1_EXP1_D2,
|
||||
GPIO1_EXP1_D3,
|
||||
GPIO1_EXP1_D4,
|
||||
GPIO1_EXP1_D5,
|
||||
GPIO1_EXP1_D6,
|
||||
GPIO1_EXP1_D7,
|
||||
#endif
|
||||
#if defined(GPIO2_EXP1)
|
||||
GPIO2_EXP1_A0 = 224,
|
||||
GPIO2_EXP1_A1,
|
||||
GPIO2_EXP1_A2,
|
||||
GPIO2_EXP1_A3,
|
||||
GPIO2_EXP1_A4,
|
||||
GPIO2_EXP1_A5,
|
||||
GPIO2_EXP1_A6,
|
||||
GPIO2_EXP1_A7,
|
||||
GPIO2_EXP1_B0 = 232,
|
||||
GPIO2_EXP1_B1,
|
||||
GPIO2_EXP1_B2,
|
||||
GPIO2_EXP1_B3,
|
||||
GPIO2_EXP1_B4,
|
||||
GPIO2_EXP1_B5,
|
||||
GPIO2_EXP1_B6,
|
||||
GPIO2_EXP1_B7,
|
||||
GPIO2_EXP1_C0 = 240,
|
||||
GPIO2_EXP1_C1,
|
||||
GPIO2_EXP1_C2,
|
||||
GPIO2_EXP1_C3,
|
||||
GPIO2_EXP1_C4,
|
||||
GPIO2_EXP1_C5,
|
||||
GPIO2_EXP1_C6,
|
||||
GPIO2_EXP1_C7,
|
||||
GPIO2_EXP1_D0 = 248,
|
||||
GPIO2_EXP1_D1,
|
||||
GPIO2_EXP1_D2,
|
||||
GPIO2_EXP1_D3,
|
||||
GPIO2_EXP1_D4,
|
||||
GPIO2_EXP1_D5,
|
||||
GPIO2_EXP1_D6,
|
||||
GPIO2_EXP1_D7,
|
||||
#endif
|
||||
#if defined(GPIO3_EXP1)
|
||||
GPIO3_EXP1_A0 = 256,
|
||||
GPIO3_EXP1_A1,
|
||||
GPIO3_EXP1_A2,
|
||||
GPIO3_EXP1_A3,
|
||||
GPIO3_EXP1_A4,
|
||||
GPIO3_EXP1_A5,
|
||||
GPIO3_EXP1_A6,
|
||||
GPIO3_EXP1_A7,
|
||||
GPIO3_EXP1_B0 = 264,
|
||||
GPIO3_EXP1_B1,
|
||||
GPIO3_EXP1_B2,
|
||||
GPIO3_EXP1_B3,
|
||||
GPIO3_EXP1_B4,
|
||||
GPIO3_EXP1_B5,
|
||||
GPIO3_EXP1_B6,
|
||||
GPIO3_EXP1_B7,
|
||||
GPIO3_EXP1_C0 = 272,
|
||||
GPIO3_EXP1_C1,
|
||||
GPIO3_EXP1_C2,
|
||||
GPIO3_EXP1_C3,
|
||||
GPIO3_EXP1_C4,
|
||||
GPIO3_EXP1_C5,
|
||||
GPIO3_EXP1_C6,
|
||||
GPIO3_EXP1_C7,
|
||||
GPIO3_EXP1_D0 = 280,
|
||||
GPIO3_EXP1_D1,
|
||||
GPIO3_EXP1_D2,
|
||||
GPIO3_EXP1_D3,
|
||||
GPIO3_EXP1_D4,
|
||||
GPIO3_EXP1_D5,
|
||||
GPIO3_EXP1_D6,
|
||||
GPIO3_EXP1_D7,
|
||||
#endif
|
||||
#if defined(GPIO4_EXP1)
|
||||
GPIO4_EXP1_A0 = 288,
|
||||
GPIO4_EXP1_A1,
|
||||
GPIO4_EXP1_A2,
|
||||
GPIO4_EXP1_A3,
|
||||
GPIO4_EXP1_A4,
|
||||
GPIO4_EXP1_A5,
|
||||
GPIO4_EXP1_A6,
|
||||
GPIO4_EXP1_A7,
|
||||
GPIO4_EXP1_B0 = 296,
|
||||
GPIO4_EXP1_B1,
|
||||
GPIO4_EXP1_B2,
|
||||
GPIO4_EXP1_B3,
|
||||
GPIO4_EXP1_B4,
|
||||
GPIO4_EXP1_B5,
|
||||
GPIO4_EXP1_B6,
|
||||
GPIO4_EXP1_B7,
|
||||
GPIO4_EXP1_C0 = 304,
|
||||
GPIO4_EXP1_C1,
|
||||
GPIO4_EXP1_C2,
|
||||
GPIO4_EXP1_C3,
|
||||
GPIO4_EXP1_C4,
|
||||
GPIO4_EXP1_C5,
|
||||
GPIO4_EXP1_C6,
|
||||
GPIO4_EXP1_C7,
|
||||
GPIO4_EXP1_D0 = 312,
|
||||
GPIO4_EXP1_D1,
|
||||
GPIO4_EXP1_D2,
|
||||
GPIO4_EXP1_D3,
|
||||
GPIO4_EXP1_D4,
|
||||
GPIO4_EXP1_D5,
|
||||
GPIO4_EXP1_D6,
|
||||
GPIO4_EXP1_D7,
|
||||
#endif
|
||||
#if defined(GPIO0_EXP2)
|
||||
GPIO0_EXP2_A0 = 320,
|
||||
GPIO0_EXP2_A1,
|
||||
GPIO0_EXP2_A2,
|
||||
GPIO0_EXP2_A3,
|
||||
GPIO0_EXP2_A4,
|
||||
GPIO0_EXP2_A5,
|
||||
GPIO0_EXP2_A6,
|
||||
GPIO0_EXP2_A7,
|
||||
GPIO0_EXP2_B0 = 328,
|
||||
GPIO0_EXP2_B1,
|
||||
GPIO0_EXP2_B2,
|
||||
GPIO0_EXP2_B3,
|
||||
GPIO0_EXP2_B4,
|
||||
GPIO0_EXP2_B5,
|
||||
GPIO0_EXP2_B6,
|
||||
GPIO0_EXP2_B7,
|
||||
GPIO0_EXP2_C0 = 336,
|
||||
GPIO0_EXP2_C1,
|
||||
GPIO0_EXP2_C2,
|
||||
GPIO0_EXP2_C3,
|
||||
GPIO0_EXP2_C4,
|
||||
GPIO0_EXP2_C5,
|
||||
GPIO0_EXP2_C6,
|
||||
GPIO0_EXP2_C7,
|
||||
GPIO0_EXP2_D0 = 344,
|
||||
GPIO0_EXP2_D1,
|
||||
GPIO0_EXP2_D2,
|
||||
GPIO0_EXP2_D3,
|
||||
GPIO0_EXP2_D4,
|
||||
GPIO0_EXP2_D5,
|
||||
GPIO0_EXP2_D6,
|
||||
GPIO0_EXP2_D7,
|
||||
#endif
|
||||
#if defined(GPIO1_EXP2)
|
||||
GPIO1_EXP2_A0 = 352,
|
||||
GPIO1_EXP2_A1,
|
||||
GPIO1_EXP2_A2,
|
||||
GPIO1_EXP2_A3,
|
||||
GPIO1_EXP2_A4,
|
||||
GPIO1_EXP2_A5,
|
||||
GPIO1_EXP2_A6,
|
||||
GPIO1_EXP2_A7,
|
||||
GPIO1_EXP2_B0 = 360,
|
||||
GPIO1_EXP2_B1,
|
||||
GPIO1_EXP2_B2,
|
||||
GPIO1_EXP2_B3,
|
||||
GPIO1_EXP2_B4,
|
||||
GPIO1_EXP2_B5,
|
||||
GPIO1_EXP2_B6,
|
||||
GPIO1_EXP2_B7,
|
||||
GPIO1_EXP2_C0 = 368,
|
||||
GPIO1_EXP2_C1,
|
||||
GPIO1_EXP2_C2,
|
||||
GPIO1_EXP2_C3,
|
||||
GPIO1_EXP2_C4,
|
||||
GPIO1_EXP2_C5,
|
||||
GPIO1_EXP2_C6,
|
||||
GPIO1_EXP2_C7,
|
||||
GPIO1_EXP2_D0 = 376,
|
||||
GPIO1_EXP2_D1,
|
||||
GPIO1_EXP2_D2,
|
||||
GPIO1_EXP2_D3,
|
||||
GPIO1_EXP2_D4,
|
||||
GPIO1_EXP2_D5,
|
||||
GPIO1_EXP2_D6,
|
||||
GPIO1_EXP2_D7,
|
||||
#endif
|
||||
#if defined(GPIO2_EXP2)
|
||||
GPIO2_EXP2_A0 = 384,
|
||||
GPIO2_EXP2_A1,
|
||||
GPIO2_EXP2_A2,
|
||||
GPIO2_EXP2_A3,
|
||||
GPIO2_EXP2_A4,
|
||||
GPIO2_EXP2_A5,
|
||||
GPIO2_EXP2_A6,
|
||||
GPIO2_EXP2_A7,
|
||||
GPIO2_EXP2_B0 = 392,
|
||||
GPIO2_EXP2_B1,
|
||||
GPIO2_EXP2_B2,
|
||||
GPIO2_EXP2_B3,
|
||||
GPIO2_EXP2_B4,
|
||||
GPIO2_EXP2_B5,
|
||||
GPIO2_EXP2_B6,
|
||||
GPIO2_EXP2_B7,
|
||||
GPIO2_EXP2_C0 = 400,
|
||||
GPIO2_EXP2_C1,
|
||||
GPIO2_EXP2_C2,
|
||||
GPIO2_EXP2_C3,
|
||||
GPIO2_EXP2_C4,
|
||||
GPIO2_EXP2_C5,
|
||||
GPIO2_EXP2_C6,
|
||||
GPIO2_EXP2_C7,
|
||||
GPIO2_EXP2_D0 = 408,
|
||||
GPIO2_EXP2_D1,
|
||||
GPIO2_EXP2_D2,
|
||||
GPIO2_EXP2_D3,
|
||||
GPIO2_EXP2_D4,
|
||||
GPIO2_EXP2_D5,
|
||||
GPIO2_EXP2_D6,
|
||||
GPIO2_EXP2_D7,
|
||||
#endif
|
||||
#if defined(GPIO3_EXP2)
|
||||
GPIO3_EXP2_A0 = 416,
|
||||
GPIO3_EXP2_A1,
|
||||
GPIO3_EXP2_A2,
|
||||
GPIO3_EXP2_A3,
|
||||
GPIO3_EXP2_A4,
|
||||
GPIO3_EXP2_A5,
|
||||
GPIO3_EXP2_A6,
|
||||
GPIO3_EXP2_A7,
|
||||
GPIO3_EXP2_B0 = 424,
|
||||
GPIO3_EXP2_B1,
|
||||
GPIO3_EXP2_B2,
|
||||
GPIO3_EXP2_B3,
|
||||
GPIO3_EXP2_B4,
|
||||
GPIO3_EXP2_B5,
|
||||
GPIO3_EXP2_B6,
|
||||
GPIO3_EXP2_B7,
|
||||
GPIO3_EXP2_C0 = 432,
|
||||
GPIO3_EXP2_C1,
|
||||
GPIO3_EXP2_C2,
|
||||
GPIO3_EXP2_C3,
|
||||
GPIO3_EXP2_C4,
|
||||
GPIO3_EXP2_C5,
|
||||
GPIO3_EXP2_C6,
|
||||
GPIO3_EXP2_C7,
|
||||
GPIO3_EXP2_D0 = 440,
|
||||
GPIO3_EXP2_D1,
|
||||
GPIO3_EXP2_D2,
|
||||
GPIO3_EXP2_D3,
|
||||
GPIO3_EXP2_D4,
|
||||
GPIO3_EXP2_D5,
|
||||
GPIO3_EXP2_D6,
|
||||
GPIO3_EXP2_D7,
|
||||
#endif
|
||||
#if defined(GPIO4_EXP2)
|
||||
GPIO4_EXP2_A0 = 448,
|
||||
GPIO4_EXP2_A1,
|
||||
GPIO4_EXP2_A2,
|
||||
GPIO4_EXP2_A3,
|
||||
GPIO4_EXP2_A4,
|
||||
GPIO4_EXP2_A5,
|
||||
GPIO4_EXP2_A6,
|
||||
GPIO4_EXP2_A7,
|
||||
GPIO4_EXP2_B0 = 456,
|
||||
GPIO4_EXP2_B1,
|
||||
GPIO4_EXP2_B2,
|
||||
GPIO4_EXP2_B3,
|
||||
GPIO4_EXP2_B4,
|
||||
GPIO4_EXP2_B5,
|
||||
GPIO4_EXP2_B6,
|
||||
GPIO4_EXP2_B7,
|
||||
GPIO4_EXP2_C0 = 464,
|
||||
GPIO4_EXP2_C1,
|
||||
GPIO4_EXP2_C2,
|
||||
GPIO4_EXP2_C3,
|
||||
GPIO4_EXP2_C4,
|
||||
GPIO4_EXP2_C5,
|
||||
GPIO4_EXP2_C6,
|
||||
GPIO4_EXP2_C7,
|
||||
GPIO4_EXP2_D0 = 472,
|
||||
GPIO4_EXP2_D1,
|
||||
GPIO4_EXP2_D2,
|
||||
GPIO4_EXP2_D3,
|
||||
GPIO4_EXP2_D4,
|
||||
GPIO4_EXP2_D5,
|
||||
GPIO4_EXP2_D6,
|
||||
GPIO4_EXP2_D7,
|
||||
#endif
|
||||
#if defined(GPIO0_EXP3)
|
||||
GPIO0_EXP3_A0 = 480,
|
||||
GPIO0_EXP3_A1,
|
||||
GPIO0_EXP3_A2,
|
||||
GPIO0_EXP3_A3,
|
||||
GPIO0_EXP3_A4,
|
||||
GPIO0_EXP3_A5,
|
||||
GPIO0_EXP3_A6,
|
||||
GPIO0_EXP3_A7,
|
||||
GPIO0_EXP3_B0 = 488,
|
||||
GPIO0_EXP3_B1,
|
||||
GPIO0_EXP3_B2,
|
||||
GPIO0_EXP3_B3,
|
||||
GPIO0_EXP3_B4,
|
||||
GPIO0_EXP3_B5,
|
||||
GPIO0_EXP3_B6,
|
||||
GPIO0_EXP3_B7,
|
||||
GPIO0_EXP3_C0 = 496,
|
||||
GPIO0_EXP3_C1,
|
||||
GPIO0_EXP3_C2,
|
||||
GPIO0_EXP3_C3,
|
||||
GPIO0_EXP3_C4,
|
||||
GPIO0_EXP3_C5,
|
||||
GPIO0_EXP3_C6,
|
||||
GPIO0_EXP3_C7,
|
||||
GPIO0_EXP3_D0 = 504,
|
||||
GPIO0_EXP3_D1,
|
||||
GPIO0_EXP3_D2,
|
||||
GPIO0_EXP3_D3,
|
||||
GPIO0_EXP3_D4,
|
||||
GPIO0_EXP3_D5,
|
||||
GPIO0_EXP3_D6,
|
||||
GPIO0_EXP3_D7,
|
||||
#endif
|
||||
#if defined(GPIO1_EXP3)
|
||||
GPIO1_EXP3_A0 = 512,
|
||||
GPIO1_EXP3_A1,
|
||||
GPIO1_EXP3_A2,
|
||||
GPIO1_EXP3_A3,
|
||||
GPIO1_EXP3_A4,
|
||||
GPIO1_EXP3_A5,
|
||||
GPIO1_EXP3_A6,
|
||||
GPIO1_EXP3_A7,
|
||||
GPIO1_EXP3_B0 = 520,
|
||||
GPIO1_EXP3_B1,
|
||||
GPIO1_EXP3_B2,
|
||||
GPIO1_EXP3_B3,
|
||||
GPIO1_EXP3_B4,
|
||||
GPIO1_EXP3_B5,
|
||||
GPIO1_EXP3_B6,
|
||||
GPIO1_EXP3_B7,
|
||||
GPIO1_EXP3_C0 = 528,
|
||||
GPIO1_EXP3_C1,
|
||||
GPIO1_EXP3_C2,
|
||||
GPIO1_EXP3_C3,
|
||||
GPIO1_EXP3_C4,
|
||||
GPIO1_EXP3_C5,
|
||||
GPIO1_EXP3_C6,
|
||||
GPIO1_EXP3_C7,
|
||||
GPIO1_EXP3_D0 = 536,
|
||||
GPIO1_EXP3_D1,
|
||||
GPIO1_EXP3_D2,
|
||||
GPIO1_EXP3_D3,
|
||||
GPIO1_EXP3_D4,
|
||||
GPIO1_EXP3_D5,
|
||||
GPIO1_EXP3_D6,
|
||||
GPIO1_EXP3_D7,
|
||||
#endif
|
||||
#if defined(GPIO2_EXP3)
|
||||
GPIO2_EXP3_A0 = 544,
|
||||
GPIO2_EXP3_A1,
|
||||
GPIO2_EXP3_A2,
|
||||
GPIO2_EXP3_A3,
|
||||
GPIO2_EXP3_A4,
|
||||
GPIO2_EXP3_A5,
|
||||
GPIO2_EXP3_A6,
|
||||
GPIO2_EXP3_A7,
|
||||
GPIO2_EXP3_B0 = 552,
|
||||
GPIO2_EXP3_B1,
|
||||
GPIO2_EXP3_B2,
|
||||
GPIO2_EXP3_B3,
|
||||
GPIO2_EXP3_B4,
|
||||
GPIO2_EXP3_B5,
|
||||
GPIO2_EXP3_B6,
|
||||
GPIO2_EXP3_B7,
|
||||
GPIO2_EXP3_C0 = 560,
|
||||
GPIO2_EXP3_C1,
|
||||
GPIO2_EXP3_C2,
|
||||
GPIO2_EXP3_C3,
|
||||
GPIO2_EXP3_C4,
|
||||
GPIO2_EXP3_C5,
|
||||
GPIO2_EXP3_C6,
|
||||
GPIO2_EXP3_C7,
|
||||
GPIO2_EXP3_D0 = 568,
|
||||
GPIO2_EXP3_D1,
|
||||
GPIO2_EXP3_D2,
|
||||
GPIO2_EXP3_D3,
|
||||
GPIO2_EXP3_D4,
|
||||
GPIO2_EXP3_D5,
|
||||
GPIO2_EXP3_D6,
|
||||
GPIO2_EXP3_D7,
|
||||
#endif
|
||||
#if defined(GPIO3_EXP3)
|
||||
GPIO3_EXP3_A0 = 576,
|
||||
GPIO3_EXP3_A1,
|
||||
GPIO3_EXP3_A2,
|
||||
GPIO3_EXP3_A3,
|
||||
GPIO3_EXP3_A4,
|
||||
GPIO3_EXP3_A5,
|
||||
GPIO3_EXP3_A6,
|
||||
GPIO3_EXP3_A7,
|
||||
GPIO3_EXP3_B0 = 584,
|
||||
GPIO3_EXP3_B1,
|
||||
GPIO3_EXP3_B2,
|
||||
GPIO3_EXP3_B3,
|
||||
GPIO3_EXP3_B4,
|
||||
GPIO3_EXP3_B5,
|
||||
GPIO3_EXP3_B6,
|
||||
GPIO3_EXP3_B7,
|
||||
GPIO3_EXP3_C0 = 592,
|
||||
GPIO3_EXP3_C1,
|
||||
GPIO3_EXP3_C2,
|
||||
GPIO3_EXP3_C3,
|
||||
GPIO3_EXP3_C4,
|
||||
GPIO3_EXP3_C5,
|
||||
GPIO3_EXP3_C6,
|
||||
GPIO3_EXP3_C7,
|
||||
GPIO3_EXP3_D0 = 600,
|
||||
GPIO3_EXP3_D1,
|
||||
GPIO3_EXP3_D2,
|
||||
GPIO3_EXP3_D3,
|
||||
GPIO3_EXP3_D4,
|
||||
GPIO3_EXP3_D5,
|
||||
GPIO3_EXP3_D6,
|
||||
GPIO3_EXP3_D7,
|
||||
#endif
|
||||
#if defined(GPIO4_EXP3)
|
||||
GPIO4_EXP3_A0 = 608,
|
||||
GPIO4_EXP3_A1,
|
||||
GPIO4_EXP3_A2,
|
||||
GPIO4_EXP3_A3,
|
||||
GPIO4_EXP3_A4,
|
||||
GPIO4_EXP3_A5,
|
||||
GPIO4_EXP3_A6,
|
||||
GPIO4_EXP3_A7,
|
||||
GPIO4_EXP3_B0 = 616,
|
||||
GPIO4_EXP3_B1,
|
||||
GPIO4_EXP3_B2,
|
||||
GPIO4_EXP3_B3,
|
||||
GPIO4_EXP3_B4,
|
||||
GPIO4_EXP3_B5,
|
||||
GPIO4_EXP3_B6,
|
||||
GPIO4_EXP3_B7,
|
||||
GPIO4_EXP3_C0 = 624,
|
||||
GPIO4_EXP3_C1,
|
||||
GPIO4_EXP3_C2,
|
||||
GPIO4_EXP3_C3,
|
||||
GPIO4_EXP3_C4,
|
||||
GPIO4_EXP3_C5,
|
||||
GPIO4_EXP3_C6,
|
||||
GPIO4_EXP3_C7,
|
||||
GPIO4_EXP3_D0 = 632,
|
||||
GPIO4_EXP3_D1,
|
||||
GPIO4_EXP3_D2,
|
||||
GPIO4_EXP3_D3,
|
||||
GPIO4_EXP3_D4,
|
||||
GPIO4_EXP3_D5,
|
||||
GPIO4_EXP3_D6,
|
||||
GPIO4_EXP3_D7,
|
||||
#endif
|
||||
GPIO_NUM_MAX
|
||||
} ePINCTRL_PIN;
|
||||
|
|
@ -476,7 +986,7 @@ typedef enum {
|
|||
PIN_CONFIG_PUL_UP = PIN_CONFIG_PUL_DEFAULT,
|
||||
PIN_CONFIG_PUL_DOWN = PIN_CONFIG_PUL_DEFAULT,
|
||||
PIN_CONFIG_PUL_KEEP = PIN_CONFIG_PUL_DEFAULT,
|
||||
#elif defined(SOC_RK3588)
|
||||
#elif defined(SOC_RK3588) || defined(SOC_RK3576)
|
||||
PIN_CONFIG_PUL_NORMAL = (0x0 << SHIFT_PUL | FLAG_PUL),
|
||||
PIN_CONFIG_PUL_DOWN = (0x1 << SHIFT_PUL | FLAG_PUL),
|
||||
PIN_CONFIG_PUL_KEEP = (0x2 << SHIFT_PUL | FLAG_PUL),
|
||||
|
|
@ -490,7 +1000,7 @@ typedef enum {
|
|||
PIN_CONFIG_PUL_DEFAULT = PIN_CONFIG_PUL_NORMAL,
|
||||
#endif
|
||||
|
||||
#if defined(SOC_RK3568) || defined(SOC_RV1106) || defined(SOC_RK3562)
|
||||
#if defined(SOC_RK3568) || defined(SOC_RV1106) || defined(SOC_RK3562) || defined(RKMCU_RK2118)
|
||||
PIN_CONFIG_DRV_LEVEL0 = (0x1 << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL1 = (0x3 << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL2 = (0x7 << SHIFT_DRV | FLAG_DRV),
|
||||
|
|
@ -504,6 +1014,14 @@ typedef enum {
|
|||
PIN_CONFIG_DRV_LEVEL2 = (0x1 << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL3 = (0x3 << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL_DEFAULT = PIN_CONFIG_DRV_LEVEL2,
|
||||
#elif defined(SOC_RK3576)
|
||||
PIN_CONFIG_DRV_LEVEL0 = (0x0 << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL1 = (0x4 << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL2 = (0x2 << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL3 = (0x6 << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL4 = (0x1 << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL5 = (0x5 << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL_DEFAULT = PIN_CONFIG_DRV_LEVEL2,
|
||||
#else
|
||||
PIN_CONFIG_DRV_LEVEL0 = (0x0 << SHIFT_DRV | FLAG_DRV),
|
||||
PIN_CONFIG_DRV_LEVEL1 = (0x1 << SHIFT_DRV | FLAG_DRV),
|
||||
|
|
@ -678,6 +1196,9 @@ HAL_Status HAL_PINCTRL_DeInit(void);
|
|||
|
||||
HAL_Status HAL_PINCTRL_SetParam(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param);
|
||||
HAL_Status HAL_PINCTRL_SetIOMUX(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param);
|
||||
#ifdef RM0_IO
|
||||
HAL_Status HAL_PINCTRL_SetRMIO(eGPIO_bankId bank, uint32_t rmioPin, eRMIO_Name rmioFunc);
|
||||
#endif
|
||||
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForCIF(eIOFUNC_SEL mode);
|
||||
HAL_Status HAL_PINCTRL_IOFuncSelForEMMC(eIOFUNC_SEL mode);
|
||||
|
|
|
|||
|
|
@ -415,6 +415,7 @@ typedef enum CLOCK_Name {
|
|||
ACLK_USB = CLK(ACLK_USB_SEL, 0U),
|
||||
HCLK_USB = CLK(HCLK_USB_SEL, 0U),
|
||||
PCLK_USB = CLK(0U, PCLK_USB_DIV),
|
||||
CLK_SDMMC0 = CLK(CLK_SDMMC0_SEL, 0U),
|
||||
} eCLOCK_Name;
|
||||
#endif
|
||||
/****************************************MBOX********************************************/
|
||||
|
|
@ -425,10 +426,10 @@ typedef enum CLOCK_Name {
|
|||
#define GRF_DS_BIT_PER_PIN (8)
|
||||
#define GRF_PULL_BIT_PER_PIN (2)
|
||||
/****************************************GPIO********************************************/
|
||||
#ifdef GPIO_VER_ID
|
||||
#undef GPIO_VER_ID
|
||||
#define GPIO_VER_ID (0x01000C2BU)
|
||||
#endif
|
||||
// #ifdef GPIO_VER_ID
|
||||
// #undef GPIO_VER_ID
|
||||
// #define GPIO_VER_ID (0x01000C2BU)
|
||||
// #endif
|
||||
/****************************************PMU*********************************************/
|
||||
#ifndef __ASSEMBLY__
|
||||
typedef enum PD_Id {
|
||||
|
|
@ -438,6 +439,10 @@ typedef enum PD_Id {
|
|||
/****************************************FSPI********************************************/
|
||||
#define FSPI_CHIP_CNT (2)
|
||||
|
||||
/****************************************WDT*********************************************/
|
||||
#define GLB_RST_SND_WDT GLB_RST_SND_WDT0
|
||||
#define GLB_RST_FST_WDT GLB_RST_FST_WDT0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
|
|
|||
Loading…
Reference in New Issue